rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

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Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_49 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_49( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_47 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1]}, credit_alloc : { `6` : { alloc : UInt<1>, tail : UInt<1>}[1], `5` : { alloc : UInt<1>, tail : UInt<1>}[1], `4` : { alloc : UInt<1>, tail : UInt<1>}[1], `3` : { alloc : UInt<1>, tail : UInt<1>}[1], `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[10]}, switch_sel : { `6` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `5` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `4` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `3` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_272 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_273 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_274 connect arbs_2.clock, clock connect arbs_2.reset, reset inst arbs_3 of SwitchArbiter_275 connect arbs_3.clock, clock connect arbs_3.reset, reset inst arbs_4 of SwitchArbiter_276 connect arbs_4.clock, clock connect arbs_4.reset, reset inst arbs_5 of SwitchArbiter_277 connect arbs_5.clock, clock connect arbs_5.reset, reset inst arbs_6 of SwitchArbiter_278 connect arbs_6.clock, clock connect arbs_6.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) connect arbs_3.io.out[0].ready, UInt<1>(0h1) connect arbs_4.io.out[0].ready, UInt<1>(0h1) connect arbs_5.io.out[0].ready, UInt<1>(0h1) connect arbs_6.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[7] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_0_valid_T_4 = or(_arbs_0_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_0_valid_T_5 = or(_arbs_0_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_0_valid_T_6 = or(_arbs_0_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_0_valid_T_7 = or(_arbs_0_io_in_0_valid_T_6, io.req.`0`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_0_valid_T_8 = or(_arbs_0_io_in_0_valid_T_7, io.req.`0`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_0_valid_T_9 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_8) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_9 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _arbs_3_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[0].valid, _arbs_3_io_in_0_valid_T connect arbs_3.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_3.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_3_T = and(arbs_3.io.in[0].ready, arbs_3.io.in[0].valid) connect fires[3], _fires_3_T node _arbs_4_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[0].valid, _arbs_4_io_in_0_valid_T connect arbs_4.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_4.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_4_T = and(arbs_4.io.in[0].ready, arbs_4.io.in[0].valid) connect fires[4], _fires_4_T node _arbs_5_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[0].valid, _arbs_5_io_in_0_valid_T connect arbs_5.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_5.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_5_T = and(arbs_5.io.in[0].ready, arbs_5.io.in[0].valid) connect fires[5], _fires_5_T node _arbs_6_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[0].valid, _arbs_6_io_in_0_valid_T connect arbs_6.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_6.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_6_T = and(arbs_6.io.in[0].ready, arbs_6.io.in[0].valid) connect fires[6], _fires_6_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) node _io_req_0_0_ready_T_2 = or(_io_req_0_0_ready_T_1, fires[3]) node _io_req_0_0_ready_T_3 = or(_io_req_0_0_ready_T_2, fires[4]) node _io_req_0_0_ready_T_4 = or(_io_req_0_0_ready_T_3, fires[5]) node _io_req_0_0_ready_T_5 = or(_io_req_0_0_ready_T_4, fires[6]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_5 wire fires_1 : UInt<1>[7] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_1_valid_T_4 = or(_arbs_0_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_1_valid_T_5 = or(_arbs_0_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_1_valid_T_6 = or(_arbs_0_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_1_valid_T_7 = or(_arbs_0_io_in_1_valid_T_6, io.req.`1`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_1_valid_T_8 = or(_arbs_0_io_in_1_valid_T_7, io.req.`1`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_1_valid_T_9 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_8) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_9 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _arbs_3_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[1].valid, _arbs_3_io_in_1_valid_T connect arbs_3.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_3.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_3_T_1 = and(arbs_3.io.in[1].ready, arbs_3.io.in[1].valid) connect fires_1[3], _fires_3_T_1 node _arbs_4_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[1].valid, _arbs_4_io_in_1_valid_T connect arbs_4.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_4.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_4_T_1 = and(arbs_4.io.in[1].ready, arbs_4.io.in[1].valid) connect fires_1[4], _fires_4_T_1 node _arbs_5_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[1].valid, _arbs_5_io_in_1_valid_T connect arbs_5.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_5.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_5_T_1 = and(arbs_5.io.in[1].ready, arbs_5.io.in[1].valid) connect fires_1[5], _fires_5_T_1 node _arbs_6_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[1].valid, _arbs_6_io_in_1_valid_T connect arbs_6.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_6.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_6_T_1 = and(arbs_6.io.in[1].ready, arbs_6.io.in[1].valid) connect fires_1[6], _fires_6_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) node _io_req_1_0_ready_T_2 = or(_io_req_1_0_ready_T_1, fires_1[3]) node _io_req_1_0_ready_T_3 = or(_io_req_1_0_ready_T_2, fires_1[4]) node _io_req_1_0_ready_T_4 = or(_io_req_1_0_ready_T_3, fires_1[5]) node _io_req_1_0_ready_T_5 = or(_io_req_1_0_ready_T_4, fires_1[6]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_5 wire fires_2 : UInt<1>[7] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_2_valid_T_4 = or(_arbs_0_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_2_valid_T_5 = or(_arbs_0_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_2_valid_T_6 = or(_arbs_0_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_2_valid_T_7 = or(_arbs_0_io_in_2_valid_T_6, io.req.`2`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_2_valid_T_8 = or(_arbs_0_io_in_2_valid_T_7, io.req.`2`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_2_valid_T_9 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_8) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_9 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _arbs_3_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[2].valid, _arbs_3_io_in_2_valid_T connect arbs_3.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_3.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_3_T_2 = and(arbs_3.io.in[2].ready, arbs_3.io.in[2].valid) connect fires_2[3], _fires_3_T_2 node _arbs_4_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[2].valid, _arbs_4_io_in_2_valid_T connect arbs_4.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_4.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_4_T_2 = and(arbs_4.io.in[2].ready, arbs_4.io.in[2].valid) connect fires_2[4], _fires_4_T_2 node _arbs_5_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[2].valid, _arbs_5_io_in_2_valid_T connect arbs_5.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_5.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_5_T_2 = and(arbs_5.io.in[2].ready, arbs_5.io.in[2].valid) connect fires_2[5], _fires_5_T_2 node _arbs_6_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[2].valid, _arbs_6_io_in_2_valid_T connect arbs_6.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_6.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_6_T_2 = and(arbs_6.io.in[2].ready, arbs_6.io.in[2].valid) connect fires_2[6], _fires_6_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) node _io_req_2_0_ready_T_2 = or(_io_req_2_0_ready_T_1, fires_2[3]) node _io_req_2_0_ready_T_3 = or(_io_req_2_0_ready_T_2, fires_2[4]) node _io_req_2_0_ready_T_4 = or(_io_req_2_0_ready_T_3, fires_2[5]) node _io_req_2_0_ready_T_5 = or(_io_req_2_0_ready_T_4, fires_2[6]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_5 wire fires_3 : UInt<1>[7] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_3_valid_T_2 = or(_arbs_0_io_in_3_valid_T_1, io.req.`3`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_3_valid_T_3 = or(_arbs_0_io_in_3_valid_T_2, io.req.`3`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_3_valid_T_4 = or(_arbs_0_io_in_3_valid_T_3, io.req.`3`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_3_valid_T_5 = or(_arbs_0_io_in_3_valid_T_4, io.req.`3`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_3_valid_T_6 = or(_arbs_0_io_in_3_valid_T_5, io.req.`3`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_3_valid_T_7 = or(_arbs_0_io_in_3_valid_T_6, io.req.`3`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_3_valid_T_8 = or(_arbs_0_io_in_3_valid_T_7, io.req.`3`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_3_valid_T_9 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_8) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_9 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _arbs_3_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[3].valid, _arbs_3_io_in_3_valid_T connect arbs_3.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_3.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_3_T_3 = and(arbs_3.io.in[3].ready, arbs_3.io.in[3].valid) connect fires_3[3], _fires_3_T_3 node _arbs_4_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[3].valid, _arbs_4_io_in_3_valid_T connect arbs_4.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_4.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_4_T_3 = and(arbs_4.io.in[3].ready, arbs_4.io.in[3].valid) connect fires_3[4], _fires_4_T_3 node _arbs_5_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[3].valid, _arbs_5_io_in_3_valid_T connect arbs_5.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_5.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_5_T_3 = and(arbs_5.io.in[3].ready, arbs_5.io.in[3].valid) connect fires_3[5], _fires_5_T_3 node _arbs_6_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[3].valid, _arbs_6_io_in_3_valid_T connect arbs_6.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_6.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_6_T_3 = and(arbs_6.io.in[3].ready, arbs_6.io.in[3].valid) connect fires_3[6], _fires_6_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) node _io_req_3_0_ready_T_2 = or(_io_req_3_0_ready_T_1, fires_3[3]) node _io_req_3_0_ready_T_3 = or(_io_req_3_0_ready_T_2, fires_3[4]) node _io_req_3_0_ready_T_4 = or(_io_req_3_0_ready_T_3, fires_3[5]) node _io_req_3_0_ready_T_5 = or(_io_req_3_0_ready_T_4, fires_3[6]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_5 wire fires_4 : UInt<1>[7] node _arbs_0_io_in_4_valid_T = or(io.req.`4`[0].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_4_valid_T_1 = or(_arbs_0_io_in_4_valid_T, io.req.`4`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_4_valid_T_2 = or(_arbs_0_io_in_4_valid_T_1, io.req.`4`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_4_valid_T_3 = or(_arbs_0_io_in_4_valid_T_2, io.req.`4`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_4_valid_T_4 = or(_arbs_0_io_in_4_valid_T_3, io.req.`4`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_4_valid_T_5 = or(_arbs_0_io_in_4_valid_T_4, io.req.`4`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_4_valid_T_6 = or(_arbs_0_io_in_4_valid_T_5, io.req.`4`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_4_valid_T_7 = or(_arbs_0_io_in_4_valid_T_6, io.req.`4`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_4_valid_T_8 = or(_arbs_0_io_in_4_valid_T_7, io.req.`4`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_4_valid_T_9 = and(io.req.`4`[0].valid, _arbs_0_io_in_4_valid_T_8) connect arbs_0.io.in[4].valid, _arbs_0_io_in_4_valid_T_9 connect arbs_0.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_0.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_0_T_4 = and(arbs_0.io.in[4].ready, arbs_0.io.in[4].valid) connect fires_4[0], _fires_0_T_4 node _arbs_1_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[4].valid, _arbs_1_io_in_4_valid_T connect arbs_1.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_1.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_1_T_4 = and(arbs_1.io.in[4].ready, arbs_1.io.in[4].valid) connect fires_4[1], _fires_1_T_4 node _arbs_2_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[4].valid, _arbs_2_io_in_4_valid_T connect arbs_2.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_2.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_2_T_4 = and(arbs_2.io.in[4].ready, arbs_2.io.in[4].valid) connect fires_4[2], _fires_2_T_4 node _arbs_3_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[4].valid, _arbs_3_io_in_4_valid_T connect arbs_3.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_3.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_3_T_4 = and(arbs_3.io.in[4].ready, arbs_3.io.in[4].valid) connect fires_4[3], _fires_3_T_4 node _arbs_4_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[4].valid, _arbs_4_io_in_4_valid_T connect arbs_4.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_4.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_4_T_4 = and(arbs_4.io.in[4].ready, arbs_4.io.in[4].valid) connect fires_4[4], _fires_4_T_4 node _arbs_5_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[4].valid, _arbs_5_io_in_4_valid_T connect arbs_5.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_5.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_5_T_4 = and(arbs_5.io.in[4].ready, arbs_5.io.in[4].valid) connect fires_4[5], _fires_5_T_4 node _arbs_6_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[4].valid, _arbs_6_io_in_4_valid_T connect arbs_6.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_6.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_6_T_4 = and(arbs_6.io.in[4].ready, arbs_6.io.in[4].valid) connect fires_4[6], _fires_6_T_4 node _io_req_4_0_ready_T = or(fires_4[0], fires_4[1]) node _io_req_4_0_ready_T_1 = or(_io_req_4_0_ready_T, fires_4[2]) node _io_req_4_0_ready_T_2 = or(_io_req_4_0_ready_T_1, fires_4[3]) node _io_req_4_0_ready_T_3 = or(_io_req_4_0_ready_T_2, fires_4[4]) node _io_req_4_0_ready_T_4 = or(_io_req_4_0_ready_T_3, fires_4[5]) node _io_req_4_0_ready_T_5 = or(_io_req_4_0_ready_T_4, fires_4[6]) connect io.req.`4`[0].ready, _io_req_4_0_ready_T_5 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_0_0_4_0_T = bits(arbs_0.io.chosen_oh[0], 4, 4) node _io_switch_sel_0_0_4_0_T_1 = and(arbs_0.io.in[4].valid, _io_switch_sel_0_0_4_0_T) node _io_switch_sel_0_0_4_0_T_2 = and(_io_switch_sel_0_0_4_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`4`[0], _io_switch_sel_0_0_4_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_1_0_4_0_T = bits(arbs_1.io.chosen_oh[0], 4, 4) node _io_switch_sel_1_0_4_0_T_1 = and(arbs_1.io.in[4].valid, _io_switch_sel_1_0_4_0_T) node _io_switch_sel_1_0_4_0_T_2 = and(_io_switch_sel_1_0_4_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`4`[0], _io_switch_sel_1_0_4_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 node _io_switch_sel_2_0_4_0_T = bits(arbs_2.io.chosen_oh[0], 4, 4) node _io_switch_sel_2_0_4_0_T_1 = and(arbs_2.io.in[4].valid, _io_switch_sel_2_0_4_0_T) node _io_switch_sel_2_0_4_0_T_2 = and(_io_switch_sel_2_0_4_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`4`[0], _io_switch_sel_2_0_4_0_T_2 node _io_switch_sel_3_0_0_0_T = bits(arbs_3.io.chosen_oh[0], 0, 0) node _io_switch_sel_3_0_0_0_T_1 = and(arbs_3.io.in[0].valid, _io_switch_sel_3_0_0_0_T) node _io_switch_sel_3_0_0_0_T_2 = and(_io_switch_sel_3_0_0_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`0`[0], _io_switch_sel_3_0_0_0_T_2 node _io_switch_sel_3_0_1_0_T = bits(arbs_3.io.chosen_oh[0], 1, 1) node _io_switch_sel_3_0_1_0_T_1 = and(arbs_3.io.in[1].valid, _io_switch_sel_3_0_1_0_T) node _io_switch_sel_3_0_1_0_T_2 = and(_io_switch_sel_3_0_1_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`1`[0], _io_switch_sel_3_0_1_0_T_2 node _io_switch_sel_3_0_2_0_T = bits(arbs_3.io.chosen_oh[0], 2, 2) node _io_switch_sel_3_0_2_0_T_1 = and(arbs_3.io.in[2].valid, _io_switch_sel_3_0_2_0_T) node _io_switch_sel_3_0_2_0_T_2 = and(_io_switch_sel_3_0_2_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`2`[0], _io_switch_sel_3_0_2_0_T_2 node _io_switch_sel_3_0_3_0_T = bits(arbs_3.io.chosen_oh[0], 3, 3) node _io_switch_sel_3_0_3_0_T_1 = and(arbs_3.io.in[3].valid, _io_switch_sel_3_0_3_0_T) node _io_switch_sel_3_0_3_0_T_2 = and(_io_switch_sel_3_0_3_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`3`[0], _io_switch_sel_3_0_3_0_T_2 node _io_switch_sel_3_0_4_0_T = bits(arbs_3.io.chosen_oh[0], 4, 4) node _io_switch_sel_3_0_4_0_T_1 = and(arbs_3.io.in[4].valid, _io_switch_sel_3_0_4_0_T) node _io_switch_sel_3_0_4_0_T_2 = and(_io_switch_sel_3_0_4_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`4`[0], _io_switch_sel_3_0_4_0_T_2 node _io_switch_sel_4_0_0_0_T = bits(arbs_4.io.chosen_oh[0], 0, 0) node _io_switch_sel_4_0_0_0_T_1 = and(arbs_4.io.in[0].valid, _io_switch_sel_4_0_0_0_T) node _io_switch_sel_4_0_0_0_T_2 = and(_io_switch_sel_4_0_0_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`0`[0], _io_switch_sel_4_0_0_0_T_2 node _io_switch_sel_4_0_1_0_T = bits(arbs_4.io.chosen_oh[0], 1, 1) node _io_switch_sel_4_0_1_0_T_1 = and(arbs_4.io.in[1].valid, _io_switch_sel_4_0_1_0_T) node _io_switch_sel_4_0_1_0_T_2 = and(_io_switch_sel_4_0_1_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`1`[0], _io_switch_sel_4_0_1_0_T_2 node _io_switch_sel_4_0_2_0_T = bits(arbs_4.io.chosen_oh[0], 2, 2) node _io_switch_sel_4_0_2_0_T_1 = and(arbs_4.io.in[2].valid, _io_switch_sel_4_0_2_0_T) node _io_switch_sel_4_0_2_0_T_2 = and(_io_switch_sel_4_0_2_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`2`[0], _io_switch_sel_4_0_2_0_T_2 node _io_switch_sel_4_0_3_0_T = bits(arbs_4.io.chosen_oh[0], 3, 3) node _io_switch_sel_4_0_3_0_T_1 = and(arbs_4.io.in[3].valid, _io_switch_sel_4_0_3_0_T) node _io_switch_sel_4_0_3_0_T_2 = and(_io_switch_sel_4_0_3_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`3`[0], _io_switch_sel_4_0_3_0_T_2 node _io_switch_sel_4_0_4_0_T = bits(arbs_4.io.chosen_oh[0], 4, 4) node _io_switch_sel_4_0_4_0_T_1 = and(arbs_4.io.in[4].valid, _io_switch_sel_4_0_4_0_T) node _io_switch_sel_4_0_4_0_T_2 = and(_io_switch_sel_4_0_4_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`4`[0], _io_switch_sel_4_0_4_0_T_2 node _io_switch_sel_5_0_0_0_T = bits(arbs_5.io.chosen_oh[0], 0, 0) node _io_switch_sel_5_0_0_0_T_1 = and(arbs_5.io.in[0].valid, _io_switch_sel_5_0_0_0_T) node _io_switch_sel_5_0_0_0_T_2 = and(_io_switch_sel_5_0_0_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`0`[0], _io_switch_sel_5_0_0_0_T_2 node _io_switch_sel_5_0_1_0_T = bits(arbs_5.io.chosen_oh[0], 1, 1) node _io_switch_sel_5_0_1_0_T_1 = and(arbs_5.io.in[1].valid, _io_switch_sel_5_0_1_0_T) node _io_switch_sel_5_0_1_0_T_2 = and(_io_switch_sel_5_0_1_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`1`[0], _io_switch_sel_5_0_1_0_T_2 node _io_switch_sel_5_0_2_0_T = bits(arbs_5.io.chosen_oh[0], 2, 2) node _io_switch_sel_5_0_2_0_T_1 = and(arbs_5.io.in[2].valid, _io_switch_sel_5_0_2_0_T) node _io_switch_sel_5_0_2_0_T_2 = and(_io_switch_sel_5_0_2_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`2`[0], _io_switch_sel_5_0_2_0_T_2 node _io_switch_sel_5_0_3_0_T = bits(arbs_5.io.chosen_oh[0], 3, 3) node _io_switch_sel_5_0_3_0_T_1 = and(arbs_5.io.in[3].valid, _io_switch_sel_5_0_3_0_T) node _io_switch_sel_5_0_3_0_T_2 = and(_io_switch_sel_5_0_3_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`3`[0], _io_switch_sel_5_0_3_0_T_2 node _io_switch_sel_5_0_4_0_T = bits(arbs_5.io.chosen_oh[0], 4, 4) node _io_switch_sel_5_0_4_0_T_1 = and(arbs_5.io.in[4].valid, _io_switch_sel_5_0_4_0_T) node _io_switch_sel_5_0_4_0_T_2 = and(_io_switch_sel_5_0_4_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`4`[0], _io_switch_sel_5_0_4_0_T_2 node _io_switch_sel_6_0_0_0_T = bits(arbs_6.io.chosen_oh[0], 0, 0) node _io_switch_sel_6_0_0_0_T_1 = and(arbs_6.io.in[0].valid, _io_switch_sel_6_0_0_0_T) node _io_switch_sel_6_0_0_0_T_2 = and(_io_switch_sel_6_0_0_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`0`[0], _io_switch_sel_6_0_0_0_T_2 node _io_switch_sel_6_0_1_0_T = bits(arbs_6.io.chosen_oh[0], 1, 1) node _io_switch_sel_6_0_1_0_T_1 = and(arbs_6.io.in[1].valid, _io_switch_sel_6_0_1_0_T) node _io_switch_sel_6_0_1_0_T_2 = and(_io_switch_sel_6_0_1_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`1`[0], _io_switch_sel_6_0_1_0_T_2 node _io_switch_sel_6_0_2_0_T = bits(arbs_6.io.chosen_oh[0], 2, 2) node _io_switch_sel_6_0_2_0_T_1 = and(arbs_6.io.in[2].valid, _io_switch_sel_6_0_2_0_T) node _io_switch_sel_6_0_2_0_T_2 = and(_io_switch_sel_6_0_2_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`2`[0], _io_switch_sel_6_0_2_0_T_2 node _io_switch_sel_6_0_3_0_T = bits(arbs_6.io.chosen_oh[0], 3, 3) node _io_switch_sel_6_0_3_0_T_1 = and(arbs_6.io.in[3].valid, _io_switch_sel_6_0_3_0_T) node _io_switch_sel_6_0_3_0_T_2 = and(_io_switch_sel_6_0_3_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`3`[0], _io_switch_sel_6_0_3_0_T_2 node _io_switch_sel_6_0_4_0_T = bits(arbs_6.io.chosen_oh[0], 4, 4) node _io_switch_sel_6_0_4_0_T_1 = and(arbs_6.io.in[4].valid, _io_switch_sel_6_0_4_0_T) node _io_switch_sel_6_0_4_0_T_2 = and(_io_switch_sel_6_0_4_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`4`[0], _io_switch_sel_6_0_4_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`4`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`5`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`6`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[5].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[6].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[7].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[8].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[9].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`3`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`4`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`5`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`6`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3]) when _T_3 : connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4]) when _T_4 : connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail node _T_5 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[5]) when _T_5 : connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[5].tail, arbs_0.io.out[0].bits.tail node _T_6 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[6]) when _T_6 : connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[6].tail, arbs_0.io.out[0].bits.tail node _T_7 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[7]) when _T_7 : connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[7].tail, arbs_0.io.out[0].bits.tail node _T_8 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[8]) when _T_8 : connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[8].tail, arbs_0.io.out[0].bits.tail node _T_9 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[9]) when _T_9 : connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[9].tail, arbs_0.io.out[0].bits.tail node _T_10 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_10 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_11 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_11 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail node _T_12 = and(arbs_3.io.out[0].valid, arbs_3.io.out[0].bits.vc_sel.`3`[0]) when _T_12 : connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`3`[0].tail, arbs_3.io.out[0].bits.tail node _T_13 = and(arbs_4.io.out[0].valid, arbs_4.io.out[0].bits.vc_sel.`4`[0]) when _T_13 : connect io.credit_alloc.`4`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`4`[0].tail, arbs_4.io.out[0].bits.tail node _T_14 = and(arbs_5.io.out[0].valid, arbs_5.io.out[0].bits.vc_sel.`5`[0]) when _T_14 : connect io.credit_alloc.`5`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`5`[0].tail, arbs_5.io.out[0].bits.tail node _T_15 = and(arbs_6.io.out[0].valid, arbs_6.io.out[0].bits.vc_sel.`6`[0]) when _T_15 : connect io.credit_alloc.`6`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`6`[0].tail, arbs_6.io.out[0].bits.tail	module SwitchAllocator_47( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_4_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_4_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_6_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_6_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_5_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_5_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_4_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_4_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_6_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_7_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_8_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_9_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_6_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_6_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_5_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_4_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 \| io_req_2_0_bits_vc_sel_0_1 \| io_req_2_0_bits_vc_sel_0_2 \| io_req_2_0_bits_vc_sel_0_3 \| io_req_2_0_bits_vc_sel_0_4 \| io_req_2_0_bits_vc_sel_0_5 \| io_req_2_0_bits_vc_sel_0_6 \| io_req_2_0_bits_vc_sel_0_7 \| io_req_2_0_bits_vc_sel_0_8 \| io_req_2_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_4_valid = io_req_4_0_valid & (io_req_4_0_bits_vc_sel_0_0 \| io_req_4_0_bits_vc_sel_0_1 \| io_req_4_0_bits_vc_sel_0_2 \| io_req_4_0_bits_vc_sel_0_3 \| io_req_4_0_bits_vc_sel_0_4 \| io_req_4_0_bits_vc_sel_0_5 \| io_req_4_0_bits_vc_sel_0_6 \| io_req_4_0_bits_vc_sel_0_7 \| io_req_4_0_bits_vc_sel_0_8 \| io_req_4_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_4_0_alloc_0 = _arbs_4_io_out_0_valid & _arbs_4_io_out_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_5_0_alloc_0 = _arbs_5_io_out_0_valid & _arbs_5_io_out_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_6_0_alloc_0 = _arbs_6_io_out_0_valid & _arbs_6_io_out_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_272 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused /), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_0_io_in_4_ready), .io_in_4_valid (arbs_0_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2), .io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5), .io_out_0_bits_vc_sel_0_6 (_arbs_0_io_out_0_bits_vc_sel_0_6), .io_out_0_bits_vc_sel_0_7 (_arbs_0_io_out_0_bits_vc_sel_0_7), .io_out_0_bits_vc_sel_0_8 (_arbs_0_io_out_0_bits_vc_sel_0_8), .io_out_0_bits_vc_sel_0_9 (_arbs_0_io_out_0_bits_vc_sel_0_9), .io_out_0_bits_tail (/ unused /), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_1_io_in_4_ready), .io_in_4_valid (arbs_1_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_2_io_in_4_ready), .io_in_4_valid (arbs_2_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_3 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (arbs_3_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_3_io_in_4_ready), .io_in_4_valid (arbs_3_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_3_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_3_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_4 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_4_io_in_0_ready), .io_in_0_valid (arbs_4_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_4_io_in_2_ready), .io_in_2_valid (arbs_4_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_4_io_in_4_ready), .io_in_4_valid (arbs_4_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_4_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (_arbs_4_io_out_0_bits_vc_sel_4_0), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_4_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_4_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_5 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_5_io_in_0_ready), .io_in_0_valid (arbs_5_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_5_io_in_2_ready), .io_in_2_valid (arbs_5_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_5_io_in_4_ready), .io_in_4_valid (arbs_5_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_5_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/ unused /), .io_out_0_bits_vc_sel_5_0 (_arbs_5_io_out_0_bits_vc_sel_5_0), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_5_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_5_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_6 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_6_io_in_0_ready), .io_in_0_valid (arbs_6_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_6_io_in_2_ready), .io_in_2_valid (arbs_6_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_6_io_in_4_ready), .io_in_4_valid (arbs_6_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_6_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (_arbs_6_io_out_0_bits_vc_sel_6_0), .io_out_0_bits_vc_sel_5_0 (/ unused /), .io_out_0_bits_vc_sel_4_0 (/ unused /), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_2 (/ unused /), .io_out_0_bits_vc_sel_0_3 (/ unused /), .io_out_0_bits_vc_sel_0_4 (/ unused /), .io_out_0_bits_vc_sel_0_5 (/ unused /), .io_out_0_bits_vc_sel_0_6 (/ unused /), .io_out_0_bits_vc_sel_0_7 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused */), .io_out_0_bits_tail (_arbs_6_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_6_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_4_0_ready = _arbs_0_io_in_4_ready & arbs_0_io_in_4_valid \| _arbs_1_io_in_4_ready & arbs_1_io_in_4_valid \| _arbs_2_io_in_4_ready & arbs_2_io_in_4_valid \| _arbs_3_io_in_4_ready & arbs_3_io_in_4_valid \| _arbs_4_io_in_4_ready & arbs_4_io_in_4_valid \| _arbs_5_io_in_4_ready & arbs_5_io_in_4_valid \| _arbs_6_io_in_4_ready & arbs_6_io_in_4_valid; // @[Decoupled.scala:51:35] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid \| _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid \| _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid \| _arbs_3_io_in_2_ready & arbs_3_io_in_2_valid \| _arbs_4_io_in_2_ready & arbs_4_io_in_2_valid \| _arbs_5_io_in_2_ready & arbs_5_io_in_2_valid \| _arbs_6_io_in_2_ready & arbs_6_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid \| _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid \| _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid \| _arbs_4_io_in_0_ready & arbs_4_io_in_0_valid \| _arbs_5_io_in_0_ready & arbs_5_io_in_0_valid \| _arbs_6_io_in_0_ready & arbs_6_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_6_0_alloc = io_credit_alloc_6_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_6_0_tail = io_credit_alloc_6_0_alloc_0 & _arbs_6_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_5_0_alloc = io_credit_alloc_5_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_5_0_tail = io_credit_alloc_5_0_alloc_0 & _arbs_5_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_4_0_alloc = io_credit_alloc_4_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_4_0_tail = io_credit_alloc_4_0_alloc_0 & _arbs_4_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_6_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_7_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_8_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_9_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_6_0_4_0 = arbs_6_io_in_4_valid & _arbs_6_io_chosen_oh_0[4] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_6_0_2_0 = arbs_6_io_in_2_valid & _arbs_6_io_chosen_oh_0[2] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_6_0_0_0 = arbs_6_io_in_0_valid & _arbs_6_io_chosen_oh_0[0] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_4_0 = arbs_5_io_in_4_valid & _arbs_5_io_chosen_oh_0[4] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_2_0 = arbs_5_io_in_2_valid & _arbs_5_io_chosen_oh_0[2] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_0_0 = arbs_5_io_in_0_valid & _arbs_5_io_chosen_oh_0[0] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_4_0 = arbs_4_io_in_4_valid & _arbs_4_io_chosen_oh_0[4] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_2_0 = arbs_4_io_in_2_valid & _arbs_4_io_chosen_oh_0[2] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_0_0 = arbs_4_io_in_0_valid & _arbs_4_io_chosen_oh_0[0] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_4_0 = arbs_3_io_in_4_valid & _arbs_3_io_chosen_oh_0[4] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_2_0 = arbs_3_io_in_2_valid & _arbs_3_io_chosen_oh_0[2] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_4_0 = arbs_2_io_in_4_valid & _arbs_2_io_chosen_oh_0[4] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_4_0 = arbs_1_io_in_4_valid & _arbs_1_io_chosen_oh_0[4] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_4_0 = arbs_0_io_in_4_valid & _arbs_0_io_chosen_oh_0[4] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<12>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<12>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 3, 0) node _req_clientBit_T = shr(request.source, 4) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<1>(0h1)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<4>(0h8)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 3, 0) node _req_clientBit_T_6 = shr(request.source, 4) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<1>(0h0)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<4>(0h8)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(_T_110, UInt<1>(0h0)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_111, UInt<1>(0h1), "") : assert_14 node _T_115 = eq(before, UInt<4>(0h8)) node _T_116 = eq(after, UInt<3>(0h5)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_118, UInt<1>(0h1), "") : assert_15 node _T_122 = eq(before, UInt<4>(0h8)) node _T_123 = eq(after, UInt<3>(0h4)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_125, UInt<1>(0h1), "") : assert_16 node _T_129 = eq(before, UInt<4>(0h8)) node _T_130 = eq(after, UInt<3>(0h6)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(_T_131, UInt<1>(0h0)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_132, UInt<1>(0h1), "") : assert_17 node _T_136 = eq(before, UInt<4>(0h8)) node _T_137 = eq(after, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(before, UInt<4>(0h8)) node _T_140 = eq(after, UInt<2>(0h2)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(_T_141, UInt<1>(0h0)) node _T_143 = asUInt(reset) node _T_144 = eq(_T_143, UInt<1>(0h0)) when _T_144 : node _T_145 = eq(_T_142, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_142, UInt<1>(0h1), "") : assert_18 node _T_146 = eq(before, UInt<1>(0h1)) node _T_147 = eq(after, UInt<4>(0h8)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_149, UInt<1>(0h1), "") : assert_19 node _T_153 = eq(before, UInt<1>(0h1)) node _T_154 = eq(after, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_156, UInt<1>(0h1), "") : assert_20 node _T_160 = eq(before, UInt<1>(0h1)) node _T_161 = eq(after, UInt<3>(0h7)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_163, UInt<1>(0h1), "") : assert_21 node _T_167 = eq(before, UInt<1>(0h1)) node _T_168 = eq(after, UInt<3>(0h5)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_170, UInt<1>(0h1), "") : assert_22 node _T_174 = eq(before, UInt<1>(0h1)) node _T_175 = eq(after, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_177, UInt<1>(0h1), "") : assert_23 node _T_181 = eq(before, UInt<1>(0h1)) node _T_182 = eq(after, UInt<3>(0h6)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_184, UInt<1>(0h1), "") : assert_24 node _T_188 = eq(before, UInt<1>(0h1)) node _T_189 = eq(after, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(before, UInt<1>(0h1)) node _T_196 = eq(after, UInt<2>(0h2)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(_T_198, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_198, UInt<1>(0h1), "") : assert_26 node _T_202 = eq(before, UInt<1>(0h0)) node _T_203 = eq(after, UInt<4>(0h8)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_205, UInt<1>(0h1), "") : assert_27 node _T_209 = eq(before, UInt<1>(0h0)) node _T_210 = eq(after, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(_T_212, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_212, UInt<1>(0h1), "") : assert_28 node _T_216 = eq(before, UInt<1>(0h0)) node _T_217 = eq(after, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(_T_218, UInt<1>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_219, UInt<1>(0h1), "") : assert_29 node _T_223 = eq(before, UInt<1>(0h0)) node _T_224 = eq(after, UInt<3>(0h5)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_226, UInt<1>(0h1), "") : assert_30 node _T_230 = eq(before, UInt<1>(0h0)) node _T_231 = eq(after, UInt<3>(0h6)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_233, UInt<1>(0h1), "") : assert_31 node _T_237 = eq(before, UInt<1>(0h0)) node _T_238 = eq(after, UInt<3>(0h4)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(_T_239, UInt<1>(0h0)) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_240, UInt<1>(0h1), "") : assert_32 node _T_244 = eq(before, UInt<1>(0h0)) node _T_245 = eq(after, UInt<2>(0h3)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(_T_246, UInt<1>(0h0)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_247, UInt<1>(0h1), "") : assert_33 node _T_251 = eq(before, UInt<1>(0h0)) node _T_252 = eq(after, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_254, UInt<1>(0h1), "") : assert_34 node _T_258 = eq(before, UInt<3>(0h7)) node _T_259 = eq(after, UInt<4>(0h8)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_261, UInt<1>(0h1), "") : assert_35 node _T_265 = eq(before, UInt<3>(0h7)) node _T_266 = eq(after, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_268, UInt<1>(0h1), "") : assert_36 node _T_272 = eq(before, UInt<3>(0h7)) node _T_273 = eq(after, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_275, UInt<1>(0h1), "") : assert_37 node _T_279 = eq(before, UInt<3>(0h7)) node _T_280 = eq(after, UInt<3>(0h5)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_282, UInt<1>(0h1), "") : assert_38 node _T_286 = eq(before, UInt<3>(0h7)) node _T_287 = eq(after, UInt<3>(0h6)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = asUInt(reset) node _T_291 = eq(_T_290, UInt<1>(0h0)) when _T_291 : node _T_292 = eq(_T_289, UInt<1>(0h0)) when _T_292 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_289, UInt<1>(0h1), "") : assert_39 node _T_293 = eq(before, UInt<3>(0h7)) node _T_294 = eq(after, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_296, UInt<1>(0h1), "") : assert_40 node _T_300 = eq(before, UInt<3>(0h7)) node _T_301 = eq(after, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(before, UInt<3>(0h7)) node _T_304 = eq(after, UInt<2>(0h2)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(_T_305, UInt<1>(0h0)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_306, UInt<1>(0h1), "") : assert_41 node _T_310 = eq(before, UInt<3>(0h5)) node _T_311 = eq(after, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_313, UInt<1>(0h1), "") : assert_42 node _T_317 = eq(before, UInt<3>(0h5)) node _T_318 = eq(after, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_320, UInt<1>(0h1), "") : assert_43 node _T_324 = eq(before, UInt<3>(0h5)) node _T_325 = eq(after, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_327, UInt<1>(0h1), "") : assert_44 node _T_331 = eq(before, UInt<3>(0h5)) node _T_332 = eq(after, UInt<3>(0h7)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(before, UInt<3>(0h5)) node _T_335 = eq(after, UInt<3>(0h6)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_337, UInt<1>(0h1), "") : assert_45 node _T_341 = eq(before, UInt<3>(0h5)) node _T_342 = eq(after, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_344, UInt<1>(0h1), "") : assert_46 node _T_348 = eq(before, UInt<3>(0h5)) node _T_349 = eq(after, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(before, UInt<3>(0h5)) node _T_352 = eq(after, UInt<2>(0h2)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_354, UInt<1>(0h1), "") : assert_47 node _T_358 = eq(before, UInt<3>(0h6)) node _T_359 = eq(after, UInt<4>(0h8)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_361, UInt<1>(0h1), "") : assert_48 node _T_365 = eq(before, UInt<3>(0h6)) node _T_366 = eq(after, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(_T_367, UInt<1>(0h0)) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_368, UInt<1>(0h1), "") : assert_49 node _T_372 = eq(before, UInt<3>(0h6)) node _T_373 = eq(after, UInt<1>(0h0)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_375, UInt<1>(0h1), "") : assert_50 node _T_379 = eq(before, UInt<3>(0h6)) node _T_380 = eq(after, UInt<3>(0h7)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(_T_381, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_382, UInt<1>(0h1), "") : assert_51 node _T_386 = eq(before, UInt<3>(0h6)) node _T_387 = eq(after, UInt<3>(0h5)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(_T_388, UInt<1>(0h0)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_389, UInt<1>(0h1), "") : assert_52 node _T_393 = eq(before, UInt<3>(0h6)) node _T_394 = eq(after, UInt<3>(0h4)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_396, UInt<1>(0h1), "") : assert_53 node _T_400 = eq(before, UInt<3>(0h6)) node _T_401 = eq(after, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(_T_402, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_403, UInt<1>(0h1), "") : assert_54 node _T_407 = eq(before, UInt<3>(0h6)) node _T_408 = eq(after, UInt<2>(0h2)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(before, UInt<3>(0h4)) node _T_411 = eq(after, UInt<4>(0h8)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(_T_412, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_413, UInt<1>(0h1), "") : assert_55 node _T_417 = eq(before, UInt<3>(0h4)) node _T_418 = eq(after, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_420, UInt<1>(0h1), "") : assert_56 node _T_424 = eq(before, UInt<3>(0h4)) node _T_425 = eq(after, UInt<1>(0h0)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_427, UInt<1>(0h1), "") : assert_57 node _T_431 = eq(before, UInt<3>(0h4)) node _T_432 = eq(after, UInt<3>(0h7)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_434, UInt<1>(0h1), "") : assert_58 node _T_438 = eq(before, UInt<3>(0h4)) node _T_439 = eq(after, UInt<3>(0h5)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_441, UInt<1>(0h1), "") : assert_59 node _T_445 = eq(before, UInt<3>(0h4)) node _T_446 = eq(after, UInt<3>(0h6)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(before, UInt<3>(0h4)) node _T_449 = eq(after, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(_T_450, UInt<1>(0h0)) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_451, UInt<1>(0h1), "") : assert_60 node _T_455 = eq(before, UInt<3>(0h4)) node _T_456 = eq(after, UInt<2>(0h2)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(before, UInt<2>(0h3)) node _T_459 = eq(after, UInt<4>(0h8)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(_T_460, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_461, UInt<1>(0h1), "") : assert_61 node _T_465 = eq(before, UInt<2>(0h3)) node _T_466 = eq(after, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(_T_467, UInt<1>(0h0)) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_468, UInt<1>(0h1), "") : assert_62 node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<1>(0h0)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_475, UInt<1>(0h1), "") : assert_63 node _T_479 = eq(before, UInt<2>(0h3)) node _T_480 = eq(after, UInt<3>(0h7)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(before, UInt<2>(0h3)) node _T_483 = eq(after, UInt<3>(0h5)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(before, UInt<2>(0h3)) node _T_486 = eq(after, UInt<3>(0h6)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(before, UInt<2>(0h3)) node _T_489 = eq(after, UInt<3>(0h4)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(before, UInt<2>(0h3)) node _T_492 = eq(after, UInt<2>(0h2)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(before, UInt<2>(0h2)) node _T_495 = eq(after, UInt<4>(0h8)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(_T_496, UInt<1>(0h0)) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_497, UInt<1>(0h1), "") : assert_64 node _T_501 = eq(before, UInt<2>(0h2)) node _T_502 = eq(after, UInt<1>(0h1)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(_T_503, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_504, UInt<1>(0h1), "") : assert_65 node _T_508 = eq(before, UInt<2>(0h2)) node _T_509 = eq(after, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(_T_510, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_511, UInt<1>(0h1), "") : assert_66 node _T_515 = eq(before, UInt<2>(0h2)) node _T_516 = eq(after, UInt<3>(0h7)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_518, UInt<1>(0h1), "") : assert_67 node _T_522 = eq(before, UInt<2>(0h2)) node _T_523 = eq(after, UInt<3>(0h5)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(_T_524, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68 assert(clock, _T_525, UInt<1>(0h1), "") : assert_68 node _T_529 = eq(before, UInt<2>(0h2)) node _T_530 = eq(after, UInt<3>(0h6)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(before, UInt<2>(0h2)) node _T_533 = eq(after, UInt<3>(0h4)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(before, UInt<2>(0h2)) node _T_536 = eq(after, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(_T_537, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69 assert(clock, _T_538, UInt<1>(0h1), "") : assert_69 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 3, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 4) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<1>(0h1)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<4>(0h8)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 3, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 4) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<1>(0h0)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<4>(0h8)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_542 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_543 = and(probe_toN, _T_542) node _T_544 = eq(probe_toN, UInt<1>(0h0)) node _T_545 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_546 = and(_T_544, _T_545) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_547 = eq(set_pprobeack, UInt<1>(0h0)) node _T_548 = and(_T_547, w_rprobeackfirst) node _T_549 = and(set_pprobeack, w_rprobeackfirst) node _T_550 = neq(meta.state, UInt<2>(0h0)) node _T_551 = eq(io.sinkc.bits.tag, meta.tag) node _T_552 = and(_T_550, _T_551) node _T_553 = and(_T_552, io.sinkc.bits.data) when _T_553 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_554 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_555 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_556 = or(_T_554, _T_555) when _T_556 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_557 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_558 = eq(request.offset, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_561 = neq(request.offset, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_563 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_563 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 3, 0) node _new_clientBit_T = shr(new_request.source, 4) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<1>(0h1)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<4>(0h8)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 3, 0) node _new_clientBit_T_6 = shr(new_request.source, 4) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<1>(0h0)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<4>(0h8)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_564 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_564 : node _T_565 = eq(prior, UInt<4>(0h8)) node _T_566 = eq(prior, UInt<1>(0h1)) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_70 assert(clock, _T_567, UInt<1>(0h1), "") : assert_70 node _T_571 = eq(prior, UInt<1>(0h0)) node _T_572 = eq(_T_571, UInt<1>(0h0)) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_71 assert(clock, _T_572, UInt<1>(0h1), "") : assert_71 node _T_576 = eq(prior, UInt<3>(0h7)) node _T_577 = eq(prior, UInt<3>(0h5)) node _T_578 = eq(prior, UInt<3>(0h4)) node _T_579 = eq(prior, UInt<3>(0h6)) node _T_580 = eq(prior, UInt<2>(0h3)) node _T_581 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_582 = eq(request_valid, UInt<1>(0h0)) node _T_583 = and(io.schedule.ready, io.schedule.valid) node _T_584 = and(no_wait, _T_583) node _T_585 = or(_T_582, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_72 assert(clock, _T_585, UInt<1>(0h1), "") : assert_72 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_589 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_590 = or(io.directory.valid, _T_589) when _T_590 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_591 = and(new_request.prio[2], UInt<1>(0h1)) when _T_591 : connect s_execute, UInt<1>(0h0) node _T_592 = bits(new_request.opcode, 0, 0) node _T_593 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) when _T_594 : connect s_writeback, UInt<1>(0h0) node _T_595 = eq(new_request.param, UInt<3>(0h0)) node _T_596 = eq(new_request.param, UInt<3>(0h4)) node _T_597 = or(_T_595, _T_596) node _T_598 = eq(new_meta.state, UInt<2>(0h2)) node _T_599 = and(_T_597, _T_598) when _T_599 : connect s_writeback, UInt<1>(0h0) node _T_600 = eq(new_request.param, UInt<3>(0h1)) node _T_601 = eq(new_request.param, UInt<3>(0h2)) node _T_602 = or(_T_600, _T_601) node _T_603 = eq(new_request.param, UInt<3>(0h5)) node _T_604 = or(_T_602, _T_603) node _T_605 = and(new_meta.clients, new_clientBit) node _T_606 = neq(_T_605, UInt<1>(0h0)) node _T_607 = and(_T_604, _T_606) when _T_607 : connect s_writeback, UInt<1>(0h0) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(new_meta.hit, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_73 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_73 else : node _T_611 = and(new_request.control, UInt<1>(0h1)) when _T_611 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_612 = neq(new_meta.clients, UInt<1>(0h0)) node _T_613 = and(UInt<1>(0h1), _T_612) when _T_613 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_614 = eq(new_meta.hit, UInt<1>(0h0)) node _T_615 = neq(new_meta.state, UInt<2>(0h0)) node _T_616 = and(_T_614, _T_615) when _T_616 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_617 = neq(new_meta.clients, UInt<1>(0h0)) node _T_618 = and(UInt<1>(0h1), _T_617) when _T_618 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_619 = eq(new_meta.hit, UInt<1>(0h0)) node _T_620 = eq(new_meta.state, UInt<2>(0h1)) node _T_621 = and(_T_620, new_needT) node _T_622 = or(_T_619, _T_621) when _T_622 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_623 = eq(new_meta.state, UInt<2>(0h2)) node _T_624 = or(new_needT, _T_623) node _T_625 = and(new_meta.hit, _T_624) node _T_626 = not(new_skipProbe) node _T_627 = and(new_meta.clients, _T_626) node _T_628 = neq(_T_627, UInt<1>(0h0)) node _T_629 = and(_T_625, _T_628) node _T_630 = and(UInt<1>(0h1), _T_629) when _T_630 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_631 = eq(new_request.opcode, UInt<3>(0h6)) node _T_632 = eq(new_request.opcode, UInt<3>(0h7)) node _T_633 = or(_T_631, _T_632) when _T_633 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_634 = bits(new_request.opcode, 2, 2) node _T_635 = eq(_T_634, UInt<1>(0h0)) node _T_636 = and(_T_635, new_meta.hit) node _T_637 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_638 = and(_T_636, _T_637) when _T_638 : connect s_writeback, UInt<1>(0h0)	module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [4:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [11:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [11:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_590 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(_T_12, _T_19) node _T_35 = or(_T_34, _T_26) node _T_36 = or(_T_35, _T_33) node _T_37 = or(_T_5, _T_36) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_37, UInt<1>(0h1), "") : assert_1 node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_42 = or(_T_41, UInt<1>(0h0)) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = or(_T_46, UInt<1>(0h0)) node _T_48 = asUInt(reset) node _T_49 = eq(_T_48, UInt<1>(0h0)) when _T_49 : node _T_50 = eq(_T_47, UInt<1>(0h0)) when _T_50 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_47, UInt<1>(0h1), "") : assert_3	module NoCMonitor_9( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_40 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_40( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - 12'h2B; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_470 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_214 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_470( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_214 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_23 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} inst main of BranchKillableQueue_22 connect main.clock, clock connect main.reset, reset reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect main.io.enq, io.enq connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect main.io.brupdate.b2.taken, io.brupdate.b2.taken connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect main.io.flush, io.flush node _io_empty_T = eq(out_valid, UInt<1>(0h0)) node _io_empty_T_1 = and(main.io.empty, _io_empty_T) connect io.empty, _io_empty_T_1 node _io_count_T = add(main.io.count, out_valid) node _io_count_T_1 = tail(_io_count_T, 1) connect io.count, _io_count_T_1 connect io.deq.valid, out_valid connect io.deq.bits, out_reg connect io.deq.bits.uop, out_uop wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out, out_uop node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T) connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1 connect out_uop, out_uop_out node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask) node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0)) node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0)) node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0)) node _out_valid_T_4 = and(out_valid, _out_valid_T_3) node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq) node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0)) node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6) connect out_valid, _out_valid_T_7 connect main.io.deq.ready, UInt<1>(0h0) node _T = and(io.deq.ready, io.deq.valid) node _T_1 = eq(out_valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) when _T_2 : node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask) node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0)) node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0)) node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0)) node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11) node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq) node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0)) node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14) connect out_valid, _out_valid_T_15 connect out_reg, main.io.deq.bits wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out_1, main.io.deq.bits.uop node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2) connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3 connect out_uop, out_uop_out_1 connect main.io.deq.ready, UInt<1>(0h1)	module BranchKillableQueue_23( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _out_valid_T_12; // @[util.scala:496:38] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27] wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94] wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [33:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [33:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22] reg [1:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 \| ~out_valid; // @[Decoupled.scala:51:35] wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}] wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_22 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_out_valid_T_12), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e11_s53_i32_6 : input clock : Clock input reset : Reset output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 11, 11) node posExp = bits(rawIn.sExp, 10, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 51, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 51) node _alignedSig_T_1 = bits(shiftedSig, 50, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) node _roundCarryBut2_T = bits(unroundedInt, 29, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<6>(0h20)) node _common_overflow_T_1 = bits(unroundedInt, 30, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 30, 30) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1	module RecFNToIN_e11_s53_i32_6( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [83:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[83:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = \|_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = \|_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 \| _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = \|_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 \| _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 \| magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T \| _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min \| roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 \| _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 \| _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [31:0] roundedInt = {_roundedInt_T_3[31:1], _roundedInt_T_3[0] \| _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = \|(posExp[10:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = \|_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 \| roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge \| _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign \| _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T \| _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN \| rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] \| _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc \| common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_52 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_52( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s6k4z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d128s6k4z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d128s6k4z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d128s6k4z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d128s6k4z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d128s6k4z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready	module TLBuffer_a32d128s6k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [5:0] auto_out_b_bits_source = 6'h20; // @[Decoupled.scala:362:21] wire [5:0] nodeOut_b_bits_source = 6'h20; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s6k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s6k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s6k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s6k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s6k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<18>(0h2f000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = and(_T_192, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_191, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<5>(0h10)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_12) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<5>(0h11)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_13) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<5>(0h12)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_14) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<5>(0h13)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_15) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_231 = shr(io.in.a.bits.source, 4) node _T_232 = eq(_T_231, UInt<1>(0h1)) node _T_233 = leq(UInt<1>(0h0), uncommonBits_16) node _T_234 = and(_T_232, _T_233) node _T_235 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_17) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_236 connect _WIRE[8], _T_242 connect _WIRE[9], _T_243 connect _WIRE[10], _T_244 node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0)) node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = or(_T_246, _T_247) node _T_258 = or(_T_257, _T_248) node _T_259 = or(_T_258, _T_249) node _T_260 = or(_T_259, _T_250) node _T_261 = or(_T_260, _T_251) node _T_262 = or(_T_261, _T_252) node _T_263 = or(_T_262, _T_253) node _T_264 = or(_T_263, _T_254) node _T_265 = or(_T_264, _T_255) node _T_266 = or(_T_265, _T_256) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_266 node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_269 = and(_T_267, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<18>(0h2f000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_WIRE_1, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_278, UInt<1>(0h1), "") : assert_3 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_286 = asUInt(reset) node _T_287 = eq(_T_286, UInt<1>(0h0)) when _T_287 : node _T_288 = eq(_T_285, UInt<1>(0h0)) when _T_288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_285, UInt<1>(0h1), "") : assert_5 node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(is_aligned, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_292, UInt<1>(0h1), "") : assert_7 node _T_296 = not(io.in.a.bits.mask) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_297, UInt<1>(0h1), "") : assert_8 node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_301, UInt<1>(0h1), "") : assert_9 node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_305 : node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_310 = shr(io.in.a.bits.source, 2) node _T_311 = eq(_T_310, UInt<5>(0h10)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_18) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_316 = shr(io.in.a.bits.source, 2) node _T_317 = eq(_T_316, UInt<5>(0h11)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_19) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_322 = shr(io.in.a.bits.source, 2) node _T_323 = eq(_T_322, UInt<5>(0h12)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_20) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_327 = and(_T_325, _T_326) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_328 = shr(io.in.a.bits.source, 2) node _T_329 = eq(_T_328, UInt<5>(0h13)) node _T_330 = leq(UInt<1>(0h0), uncommonBits_21) node _T_331 = and(_T_329, _T_330) node _T_332 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_336 = shr(io.in.a.bits.source, 4) node _T_337 = eq(_T_336, UInt<1>(0h1)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_22) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_342 = shr(io.in.a.bits.source, 4) node _T_343 = eq(_T_342, UInt<1>(0h0)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_23) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_350 = or(_T_309, _T_315) node _T_351 = or(_T_350, _T_321) node _T_352 = or(_T_351, _T_327) node _T_353 = or(_T_352, _T_333) node _T_354 = or(_T_353, _T_334) node _T_355 = or(_T_354, _T_335) node _T_356 = or(_T_355, _T_341) node _T_357 = or(_T_356, _T_347) node _T_358 = or(_T_357, _T_348) node _T_359 = or(_T_358, _T_349) node _T_360 = and(_T_308, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_364 = cvt(_T_363) node _T_365 = and(_T_364, asSInt(UInt<18>(0h2f000))) node _T_366 = asSInt(_T_365) node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) node _T_368 = and(_T_362, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = and(_T_361, _T_369) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_370, UInt<1>(0h1), "") : assert_10 node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<5>(0h10)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_24) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_381 = shr(io.in.a.bits.source, 2) node _T_382 = eq(_T_381, UInt<5>(0h11)) node _T_383 = leq(UInt<1>(0h0), uncommonBits_25) node _T_384 = and(_T_382, _T_383) node _T_385 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_387 = shr(io.in.a.bits.source, 2) node _T_388 = eq(_T_387, UInt<5>(0h12)) node _T_389 = leq(UInt<1>(0h0), uncommonBits_26) node _T_390 = and(_T_388, _T_389) node _T_391 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_392 = and(_T_390, _T_391) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_393 = shr(io.in.a.bits.source, 2) node _T_394 = eq(_T_393, UInt<5>(0h13)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_27) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_401 = shr(io.in.a.bits.source, 4) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_28) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_407 = shr(io.in.a.bits.source, 4) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_29) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_374 connect _WIRE_2[1], _T_380 connect _WIRE_2[2], _T_386 connect _WIRE_2[3], _T_392 connect _WIRE_2[4], _T_398 connect _WIRE_2[5], _T_399 connect _WIRE_2[6], _T_400 connect _WIRE_2[7], _T_406 connect _WIRE_2[8], _T_412 connect _WIRE_2[9], _T_413 connect _WIRE_2[10], _T_414 node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0)) node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = or(_T_416, _T_417) node _T_428 = or(_T_427, _T_418) node _T_429 = or(_T_428, _T_419) node _T_430 = or(_T_429, _T_420) node _T_431 = or(_T_430, _T_421) node _T_432 = or(_T_431, _T_422) node _T_433 = or(_T_432, _T_423) node _T_434 = or(_T_433, _T_424) node _T_435 = or(_T_434, _T_425) node _T_436 = or(_T_435, _T_426) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_436 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<18>(0h2f000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_WIRE_3, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_448, UInt<1>(0h1), "") : assert_11 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_T_455, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_455, UInt<1>(0h1), "") : assert_13 node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(is_aligned, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_462, UInt<1>(0h1), "") : assert_15 node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_466, UInt<1>(0h1), "") : assert_16 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_471, UInt<1>(0h1), "") : assert_17 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_475, UInt<1>(0h1), "") : assert_18 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<5>(0h10)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_30) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<5>(0h11)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_31) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<5>(0h12)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_32) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<5>(0h13)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_33) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_510 = shr(io.in.a.bits.source, 4) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_34) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_516 = shr(io.in.a.bits.source, 4) node _T_517 = eq(_T_516, UInt<1>(0h0)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_35) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_524 = or(_T_483, _T_489) node _T_525 = or(_T_524, _T_495) node _T_526 = or(_T_525, _T_501) node _T_527 = or(_T_526, _T_507) node _T_528 = or(_T_527, _T_508) node _T_529 = or(_T_528, _T_509) node _T_530 = or(_T_529, _T_515) node _T_531 = or(_T_530, _T_521) node _T_532 = or(_T_531, _T_522) node _T_533 = or(_T_532, _T_523) node _T_534 = and(_T_482, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_535, UInt<1>(0h1), "") : assert_19 node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_541 = and(_T_539, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<18>(0h2f000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = and(_T_542, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_549, UInt<1>(0h1), "") : assert_20 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(source_ok, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(is_aligned, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_559, UInt<1>(0h1), "") : assert_23 node _T_563 = eq(io.in.a.bits.mask, mask) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_563, UInt<1>(0h1), "") : assert_24 node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_567, UInt<1>(0h1), "") : assert_25 node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_571 : node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<5>(0h10)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_36) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<5>(0h11)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_37) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<5>(0h12)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_38) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<5>(0h13)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_39) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_602 = shr(io.in.a.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_40) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_608 = shr(io.in.a.bits.source, 4) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_41) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_616 = or(_T_575, _T_581) node _T_617 = or(_T_616, _T_587) node _T_618 = or(_T_617, _T_593) node _T_619 = or(_T_618, _T_599) node _T_620 = or(_T_619, _T_600) node _T_621 = or(_T_620, _T_601) node _T_622 = or(_T_621, _T_607) node _T_623 = or(_T_622, _T_613) node _T_624 = or(_T_623, _T_614) node _T_625 = or(_T_624, _T_615) node _T_626 = and(_T_574, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_630 = and(_T_628, _T_629) node _T_631 = or(UInt<1>(0h0), _T_630) node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_633 = cvt(_T_632) node _T_634 = and(_T_633, asSInt(UInt<18>(0h2f000))) node _T_635 = asSInt(_T_634) node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0))) node _T_637 = and(_T_631, _T_636) node _T_638 = or(UInt<1>(0h0), _T_637) node _T_639 = and(_T_627, _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_639, UInt<1>(0h1), "") : assert_26 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_649, UInt<1>(0h1), "") : assert_29 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_653, UInt<1>(0h1), "") : assert_30 node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_657 : node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_662 = shr(io.in.a.bits.source, 2) node _T_663 = eq(_T_662, UInt<5>(0h10)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_42) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_668 = shr(io.in.a.bits.source, 2) node _T_669 = eq(_T_668, UInt<5>(0h11)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_43) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_673 = and(_T_671, _T_672) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_674 = shr(io.in.a.bits.source, 2) node _T_675 = eq(_T_674, UInt<5>(0h12)) node _T_676 = leq(UInt<1>(0h0), uncommonBits_44) node _T_677 = and(_T_675, _T_676) node _T_678 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_680 = shr(io.in.a.bits.source, 2) node _T_681 = eq(_T_680, UInt<5>(0h13)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_45) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_688 = shr(io.in.a.bits.source, 4) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_46) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_694 = shr(io.in.a.bits.source, 4) node _T_695 = eq(_T_694, UInt<1>(0h0)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_47) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_702 = or(_T_661, _T_667) node _T_703 = or(_T_702, _T_673) node _T_704 = or(_T_703, _T_679) node _T_705 = or(_T_704, _T_685) node _T_706 = or(_T_705, _T_686) node _T_707 = or(_T_706, _T_687) node _T_708 = or(_T_707, _T_693) node _T_709 = or(_T_708, _T_699) node _T_710 = or(_T_709, _T_700) node _T_711 = or(_T_710, _T_701) node _T_712 = and(_T_660, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_716 = and(_T_714, _T_715) node _T_717 = or(UInt<1>(0h0), _T_716) node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<18>(0h2f000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = and(_T_713, _T_724) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_725, UInt<1>(0h1), "") : assert_31 node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(source_ok, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(is_aligned, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_735, UInt<1>(0h1), "") : assert_34 node _T_739 = not(mask) node _T_740 = and(io.in.a.bits.mask, _T_739) node _T_741 = eq(_T_740, UInt<1>(0h0)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_741, UInt<1>(0h1), "") : assert_35 node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_745 : node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<5>(0h10)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_48) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<5>(0h11)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_49) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<5>(0h12)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_50) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_768 = shr(io.in.a.bits.source, 2) node _T_769 = eq(_T_768, UInt<5>(0h13)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_51) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_773 = and(_T_771, _T_772) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_776 = shr(io.in.a.bits.source, 4) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_52) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_782 = shr(io.in.a.bits.source, 4) node _T_783 = eq(_T_782, UInt<1>(0h0)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_53) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_787 = and(_T_785, _T_786) node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_790 = or(_T_749, _T_755) node _T_791 = or(_T_790, _T_761) node _T_792 = or(_T_791, _T_767) node _T_793 = or(_T_792, _T_773) node _T_794 = or(_T_793, _T_774) node _T_795 = or(_T_794, _T_775) node _T_796 = or(_T_795, _T_781) node _T_797 = or(_T_796, _T_787) node _T_798 = or(_T_797, _T_788) node _T_799 = or(_T_798, _T_789) node _T_800 = and(_T_748, _T_799) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<18>(0h2f000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = and(_T_801, _T_809) node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_T_810, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_810, UInt<1>(0h1), "") : assert_36 node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(source_ok, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(is_aligned, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_820, UInt<1>(0h1), "") : assert_39 node _T_824 = eq(io.in.a.bits.mask, mask) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_824, UInt<1>(0h1), "") : assert_40 node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_828 : node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<5>(0h10)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_54) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<5>(0h11)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_55) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<5>(0h12)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_56) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<5>(0h13)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_57) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_859 = shr(io.in.a.bits.source, 4) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_58) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_865 = shr(io.in.a.bits.source, 4) node _T_866 = eq(_T_865, UInt<1>(0h0)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_59) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_873 = or(_T_832, _T_838) node _T_874 = or(_T_873, _T_844) node _T_875 = or(_T_874, _T_850) node _T_876 = or(_T_875, _T_856) node _T_877 = or(_T_876, _T_857) node _T_878 = or(_T_877, _T_858) node _T_879 = or(_T_878, _T_864) node _T_880 = or(_T_879, _T_870) node _T_881 = or(_T_880, _T_871) node _T_882 = or(_T_881, _T_872) node _T_883 = and(_T_831, _T_882) node _T_884 = or(UInt<1>(0h0), _T_883) node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<18>(0h2f000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = and(_T_885, _T_890) node _T_892 = or(UInt<1>(0h0), _T_891) node _T_893 = and(_T_884, _T_892) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_893, UInt<1>(0h1), "") : assert_41 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(source_ok, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(is_aligned, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_903, UInt<1>(0h1), "") : assert_44 node _T_907 = eq(io.in.a.bits.mask, mask) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_907, UInt<1>(0h1), "") : assert_45 node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_911 : node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_914 = and(_T_912, _T_913) node _T_915 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_916 = shr(io.in.a.bits.source, 2) node _T_917 = eq(_T_916, UInt<5>(0h10)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_60) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_922 = shr(io.in.a.bits.source, 2) node _T_923 = eq(_T_922, UInt<5>(0h11)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_61) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_928 = shr(io.in.a.bits.source, 2) node _T_929 = eq(_T_928, UInt<5>(0h12)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_62) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<5>(0h13)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_63) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_942 = shr(io.in.a.bits.source, 4) node _T_943 = eq(_T_942, UInt<1>(0h1)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_64) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_948 = shr(io.in.a.bits.source, 4) node _T_949 = eq(_T_948, UInt<1>(0h0)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_65) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_953 = and(_T_951, _T_952) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_956 = or(_T_915, _T_921) node _T_957 = or(_T_956, _T_927) node _T_958 = or(_T_957, _T_933) node _T_959 = or(_T_958, _T_939) node _T_960 = or(_T_959, _T_940) node _T_961 = or(_T_960, _T_941) node _T_962 = or(_T_961, _T_947) node _T_963 = or(_T_962, _T_953) node _T_964 = or(_T_963, _T_954) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_914, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_970 = cvt(_T_969) node _T_971 = and(_T_970, asSInt(UInt<18>(0h2f000))) node _T_972 = asSInt(_T_971) node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) node _T_974 = and(_T_968, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = and(_T_967, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_976, UInt<1>(0h1), "") : assert_46 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_986, UInt<1>(0h1), "") : assert_49 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_990, UInt<1>(0h1), "") : assert_50 node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_994, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_998, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54 node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55 node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57 node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1022 : node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(source_ok_1, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(sink_ok, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60 node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61 node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62 node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64 node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1050 : node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok_1, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(sink_ok, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67 node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68 node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69 node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1070 = or(_T_1069, io.in.d.bits.corrupt) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70 node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1075 = or(UInt<1>(0h0), _T_1074) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71 node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1079 : node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(_T_1083, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73 node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74 node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1092 = or(UInt<1>(0h0), _T_1091) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75 node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1096 : node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(source_ok_1, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77 node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1105 = or(_T_1104, io.in.d.bits.corrupt) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78 node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1110 = or(UInt<1>(0h0), _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79 node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1114 : node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(source_ok_1, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81 node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82 node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1143 = eq(a_first, UInt<1>(0h0)) node _T_1144 = and(io.in.a.valid, _T_1143) when _T_1144 : node _T_1145 = eq(io.in.a.bits.opcode, opcode) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87 node _T_1149 = eq(io.in.a.bits.param, param) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88 node _T_1153 = eq(io.in.a.bits.size, size) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89 node _T_1157 = eq(io.in.a.bits.source, source) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90 node _T_1161 = eq(io.in.a.bits.address, address) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91 node _T_1165 = and(io.in.a.ready, io.in.a.valid) node _T_1166 = and(_T_1165, a_first) when _T_1166 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1167 = eq(d_first, UInt<1>(0h0)) node _T_1168 = and(io.in.d.valid, _T_1167) when _T_1168 : node _T_1169 = eq(io.in.d.bits.opcode, opcode_1) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92 node _T_1173 = eq(io.in.d.bits.param, param_1) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93 node _T_1177 = eq(io.in.d.bits.size, size_1) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94 node _T_1181 = eq(io.in.d.bits.source, source_1) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95 node _T_1185 = eq(io.in.d.bits.sink, sink) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96 node _T_1189 = eq(io.in.d.bits.denied, denied) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97 node _T_1193 = and(io.in.d.ready, io.in.d.valid) node _T_1194 = and(_T_1193, d_first) when _T_1194 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1195 = and(io.in.a.valid, a_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) when _T_1196 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1197 = and(io.in.a.ready, io.in.a.valid) node _T_1198 = and(_T_1197, a_first_1) node _T_1199 = and(_T_1198, UInt<1>(0h1)) when _T_1199 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1200 = dshr(inflight, io.in.a.bits.source) node _T_1201 = bits(_T_1200, 0, 0) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1206 = and(io.in.d.valid, d_first_1) node _T_1207 = and(_T_1206, UInt<1>(0h1)) node _T_1208 = eq(d_release_ack, UInt<1>(0h0)) node _T_1209 = and(_T_1207, _T_1208) when _T_1209 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = and(_T_1210, d_first_1) node _T_1212 = and(_T_1211, UInt<1>(0h1)) node _T_1213 = eq(d_release_ack, UInt<1>(0h0)) node _T_1214 = and(_T_1212, _T_1213) when _T_1214 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1215 = and(io.in.d.valid, d_first_1) node _T_1216 = and(_T_1215, UInt<1>(0h1)) node _T_1217 = eq(d_release_ack, UInt<1>(0h0)) node _T_1218 = and(_T_1216, _T_1217) when _T_1218 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1219 = dshr(inflight, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1227 = or(_T_1225, _T_1226) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100 node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101 else : node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1237 = or(_T_1235, _T_1236) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102 node _T_1241 = eq(io.in.d.bits.size, a_size_lookup) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103 node _T_1245 = and(io.in.d.valid, d_first_1) node _T_1246 = and(_T_1245, a_first_1) node _T_1247 = and(_T_1246, io.in.a.valid) node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1249 = and(_T_1247, _T_1248) node _T_1250 = eq(d_release_ack, UInt<1>(0h0)) node _T_1251 = and(_T_1249, _T_1250) when _T_1251 : node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1253 = or(_T_1252, io.in.a.ready) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_130 node _T_1257 = orr(inflight) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1260 = or(_T_1258, _T_1259) node _T_1261 = lt(watchdog, plusarg_reader.out) node _T_1262 = or(_T_1260, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1266 = and(io.in.a.ready, io.in.a.valid) node _T_1267 = and(io.in.d.ready, io.in.d.valid) node _T_1268 = or(_T_1266, _T_1267) when _T_1268 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1269 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1270 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1271 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = and(_T_1269, _T_1272) when _T_1273 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1274 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1275 = and(_T_1274, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1276 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1277 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1275, _T_1278) when _T_1279 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1280 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1281 = bits(_T_1280, 0, 0) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1286 = and(io.in.d.valid, d_first_2) node _T_1287 = and(_T_1286, UInt<1>(0h1)) node _T_1288 = and(_T_1287, d_release_ack_1) when _T_1288 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1289 = and(io.in.d.ready, io.in.d.valid) node _T_1290 = and(_T_1289, d_first_2) node _T_1291 = and(_T_1290, UInt<1>(0h1)) node _T_1292 = and(_T_1291, d_release_ack_1) when _T_1292 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1293 = and(io.in.d.valid, d_first_2) node _T_1294 = and(_T_1293, UInt<1>(0h1)) node _T_1295 = and(_T_1294, d_release_ack_1) when _T_1295 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1296 = dshr(inflight_1, io.in.d.bits.source) node _T_1297 = bits(_T_1296, 0, 0) node _T_1298 = or(_T_1297, same_cycle_resp_1) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1302 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_108 else : node _T_1306 = eq(io.in.d.bits.size, c_size_lookup) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_109 node _T_1310 = and(io.in.d.valid, d_first_2) node _T_1311 = and(_T_1310, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1312 = and(_T_1311, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1313 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1314 = and(_T_1312, _T_1313) node _T_1315 = and(_T_1314, d_release_ack_1) node _T_1316 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1317 = and(_T_1315, _T_1316) when _T_1317 : node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1319 = or(_T_1318, _WIRE_27.ready) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_131 node _T_1323 = orr(inflight_1) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) node _T_1325 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1326 = or(_T_1324, _T_1325) node _T_1327 = lt(watchdog_1, plusarg_reader_1.out) node _T_1328 = or(_T_1326, _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1332 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1333 = and(io.in.d.ready, io.in.d.valid) node _T_1334 = or(_T_1332, _T_1333) when _T_1334 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_58 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_58( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_248 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_504 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_248( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_504 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_89 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_89( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_85 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_85( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<17>(0h10000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = and(_T_192, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_191, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<5>(0h10)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_12) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<5>(0h11)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_13) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<5>(0h12)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_14) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<5>(0h13)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_15) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_231 = shr(io.in.a.bits.source, 4) node _T_232 = eq(_T_231, UInt<1>(0h1)) node _T_233 = leq(UInt<1>(0h0), uncommonBits_16) node _T_234 = and(_T_232, _T_233) node _T_235 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_17) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_236 connect _WIRE[8], _T_242 connect _WIRE[9], _T_243 connect _WIRE[10], _T_244 node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0)) node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = or(_T_246, _T_247) node _T_258 = or(_T_257, _T_248) node _T_259 = or(_T_258, _T_249) node _T_260 = or(_T_259, _T_250) node _T_261 = or(_T_260, _T_251) node _T_262 = or(_T_261, _T_252) node _T_263 = or(_T_262, _T_253) node _T_264 = or(_T_263, _T_254) node _T_265 = or(_T_264, _T_255) node _T_266 = or(_T_265, _T_256) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_266 node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_269 = and(_T_267, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<17>(0h10000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_WIRE_1, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_278, UInt<1>(0h1), "") : assert_3 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_286 = asUInt(reset) node _T_287 = eq(_T_286, UInt<1>(0h0)) when _T_287 : node _T_288 = eq(_T_285, UInt<1>(0h0)) when _T_288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_285, UInt<1>(0h1), "") : assert_5 node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(is_aligned, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_292, UInt<1>(0h1), "") : assert_7 node _T_296 = not(io.in.a.bits.mask) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_297, UInt<1>(0h1), "") : assert_8 node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_301, UInt<1>(0h1), "") : assert_9 node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_305 : node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_310 = shr(io.in.a.bits.source, 2) node _T_311 = eq(_T_310, UInt<5>(0h10)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_18) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_316 = shr(io.in.a.bits.source, 2) node _T_317 = eq(_T_316, UInt<5>(0h11)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_19) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_322 = shr(io.in.a.bits.source, 2) node _T_323 = eq(_T_322, UInt<5>(0h12)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_20) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_327 = and(_T_325, _T_326) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_328 = shr(io.in.a.bits.source, 2) node _T_329 = eq(_T_328, UInt<5>(0h13)) node _T_330 = leq(UInt<1>(0h0), uncommonBits_21) node _T_331 = and(_T_329, _T_330) node _T_332 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_336 = shr(io.in.a.bits.source, 4) node _T_337 = eq(_T_336, UInt<1>(0h1)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_22) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_342 = shr(io.in.a.bits.source, 4) node _T_343 = eq(_T_342, UInt<1>(0h0)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_23) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_350 = or(_T_309, _T_315) node _T_351 = or(_T_350, _T_321) node _T_352 = or(_T_351, _T_327) node _T_353 = or(_T_352, _T_333) node _T_354 = or(_T_353, _T_334) node _T_355 = or(_T_354, _T_335) node _T_356 = or(_T_355, _T_341) node _T_357 = or(_T_356, _T_347) node _T_358 = or(_T_357, _T_348) node _T_359 = or(_T_358, _T_349) node _T_360 = and(_T_308, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_364 = cvt(_T_363) node _T_365 = and(_T_364, asSInt(UInt<17>(0h10000))) node _T_366 = asSInt(_T_365) node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) node _T_368 = and(_T_362, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = and(_T_361, _T_369) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_370, UInt<1>(0h1), "") : assert_10 node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<5>(0h10)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_24) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_381 = shr(io.in.a.bits.source, 2) node _T_382 = eq(_T_381, UInt<5>(0h11)) node _T_383 = leq(UInt<1>(0h0), uncommonBits_25) node _T_384 = and(_T_382, _T_383) node _T_385 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_387 = shr(io.in.a.bits.source, 2) node _T_388 = eq(_T_387, UInt<5>(0h12)) node _T_389 = leq(UInt<1>(0h0), uncommonBits_26) node _T_390 = and(_T_388, _T_389) node _T_391 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_392 = and(_T_390, _T_391) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_393 = shr(io.in.a.bits.source, 2) node _T_394 = eq(_T_393, UInt<5>(0h13)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_27) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_401 = shr(io.in.a.bits.source, 4) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_28) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_407 = shr(io.in.a.bits.source, 4) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_29) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_374 connect _WIRE_2[1], _T_380 connect _WIRE_2[2], _T_386 connect _WIRE_2[3], _T_392 connect _WIRE_2[4], _T_398 connect _WIRE_2[5], _T_399 connect _WIRE_2[6], _T_400 connect _WIRE_2[7], _T_406 connect _WIRE_2[8], _T_412 connect _WIRE_2[9], _T_413 connect _WIRE_2[10], _T_414 node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0)) node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = or(_T_416, _T_417) node _T_428 = or(_T_427, _T_418) node _T_429 = or(_T_428, _T_419) node _T_430 = or(_T_429, _T_420) node _T_431 = or(_T_430, _T_421) node _T_432 = or(_T_431, _T_422) node _T_433 = or(_T_432, _T_423) node _T_434 = or(_T_433, _T_424) node _T_435 = or(_T_434, _T_425) node _T_436 = or(_T_435, _T_426) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_436 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_WIRE_3, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_448, UInt<1>(0h1), "") : assert_11 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_T_455, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_455, UInt<1>(0h1), "") : assert_13 node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(is_aligned, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_462, UInt<1>(0h1), "") : assert_15 node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_466, UInt<1>(0h1), "") : assert_16 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_471, UInt<1>(0h1), "") : assert_17 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_475, UInt<1>(0h1), "") : assert_18 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<5>(0h10)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_30) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<5>(0h11)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_31) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<5>(0h12)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_32) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<5>(0h13)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_33) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_510 = shr(io.in.a.bits.source, 4) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_34) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_516 = shr(io.in.a.bits.source, 4) node _T_517 = eq(_T_516, UInt<1>(0h0)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_35) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_524 = or(_T_483, _T_489) node _T_525 = or(_T_524, _T_495) node _T_526 = or(_T_525, _T_501) node _T_527 = or(_T_526, _T_507) node _T_528 = or(_T_527, _T_508) node _T_529 = or(_T_528, _T_509) node _T_530 = or(_T_529, _T_515) node _T_531 = or(_T_530, _T_521) node _T_532 = or(_T_531, _T_522) node _T_533 = or(_T_532, _T_523) node _T_534 = and(_T_482, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_535, UInt<1>(0h1), "") : assert_19 node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_541 = and(_T_539, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<17>(0h10000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = and(_T_542, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_549, UInt<1>(0h1), "") : assert_20 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(source_ok, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(is_aligned, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_559, UInt<1>(0h1), "") : assert_23 node _T_563 = eq(io.in.a.bits.mask, mask) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_563, UInt<1>(0h1), "") : assert_24 node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_567, UInt<1>(0h1), "") : assert_25 node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_571 : node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<5>(0h10)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_36) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<5>(0h11)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_37) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<5>(0h12)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_38) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<5>(0h13)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_39) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_602 = shr(io.in.a.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_40) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_608 = shr(io.in.a.bits.source, 4) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_41) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_616 = or(_T_575, _T_581) node _T_617 = or(_T_616, _T_587) node _T_618 = or(_T_617, _T_593) node _T_619 = or(_T_618, _T_599) node _T_620 = or(_T_619, _T_600) node _T_621 = or(_T_620, _T_601) node _T_622 = or(_T_621, _T_607) node _T_623 = or(_T_622, _T_613) node _T_624 = or(_T_623, _T_614) node _T_625 = or(_T_624, _T_615) node _T_626 = and(_T_574, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_629 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<17>(0h10000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = and(_T_628, _T_633) node _T_635 = or(UInt<1>(0h0), _T_634) node _T_636 = and(_T_627, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_636, UInt<1>(0h1), "") : assert_26 node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(source_ok, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(is_aligned, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_646 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_646, UInt<1>(0h1), "") : assert_29 node _T_650 = eq(io.in.a.bits.mask, mask) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_650, UInt<1>(0h1), "") : assert_30 node _T_654 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_654 : node _T_655 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_656 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_657 = and(_T_655, _T_656) node _T_658 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_659 = shr(io.in.a.bits.source, 2) node _T_660 = eq(_T_659, UInt<5>(0h10)) node _T_661 = leq(UInt<1>(0h0), uncommonBits_42) node _T_662 = and(_T_660, _T_661) node _T_663 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_664 = and(_T_662, _T_663) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_665 = shr(io.in.a.bits.source, 2) node _T_666 = eq(_T_665, UInt<5>(0h11)) node _T_667 = leq(UInt<1>(0h0), uncommonBits_43) node _T_668 = and(_T_666, _T_667) node _T_669 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_670 = and(_T_668, _T_669) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_671 = shr(io.in.a.bits.source, 2) node _T_672 = eq(_T_671, UInt<5>(0h12)) node _T_673 = leq(UInt<1>(0h0), uncommonBits_44) node _T_674 = and(_T_672, _T_673) node _T_675 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_676 = and(_T_674, _T_675) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_677 = shr(io.in.a.bits.source, 2) node _T_678 = eq(_T_677, UInt<5>(0h13)) node _T_679 = leq(UInt<1>(0h0), uncommonBits_45) node _T_680 = and(_T_678, _T_679) node _T_681 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_682 = and(_T_680, _T_681) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_685 = shr(io.in.a.bits.source, 4) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_46) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_691 = shr(io.in.a.bits.source, 4) node _T_692 = eq(_T_691, UInt<1>(0h0)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_47) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_698 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_699 = or(_T_658, _T_664) node _T_700 = or(_T_699, _T_670) node _T_701 = or(_T_700, _T_676) node _T_702 = or(_T_701, _T_682) node _T_703 = or(_T_702, _T_683) node _T_704 = or(_T_703, _T_684) node _T_705 = or(_T_704, _T_690) node _T_706 = or(_T_705, _T_696) node _T_707 = or(_T_706, _T_697) node _T_708 = or(_T_707, _T_698) node _T_709 = and(_T_657, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_712 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<17>(0h10000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = and(_T_710, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_719, UInt<1>(0h1), "") : assert_31 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(source_ok, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(is_aligned, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_729 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_729, UInt<1>(0h1), "") : assert_34 node _T_733 = not(mask) node _T_734 = and(io.in.a.bits.mask, _T_733) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_735, UInt<1>(0h1), "") : assert_35 node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_739 : node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<5>(0h10)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_48) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<5>(0h11)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_49) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<5>(0h12)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_50) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<5>(0h13)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_51) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_770 = shr(io.in.a.bits.source, 4) node _T_771 = eq(_T_770, UInt<1>(0h1)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_52) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_776 = shr(io.in.a.bits.source, 4) node _T_777 = eq(_T_776, UInt<1>(0h0)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_53) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_784 = or(_T_743, _T_749) node _T_785 = or(_T_784, _T_755) node _T_786 = or(_T_785, _T_761) node _T_787 = or(_T_786, _T_767) node _T_788 = or(_T_787, _T_768) node _T_789 = or(_T_788, _T_769) node _T_790 = or(_T_789, _T_775) node _T_791 = or(_T_790, _T_781) node _T_792 = or(_T_791, _T_782) node _T_793 = or(_T_792, _T_783) node _T_794 = and(_T_742, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<5>(0h10)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_54) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<5>(0h11)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_55) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<5>(0h12)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_56) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<5>(0h13)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_57) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_853 = shr(io.in.a.bits.source, 4) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_58) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_859 = shr(io.in.a.bits.source, 4) node _T_860 = eq(_T_859, UInt<1>(0h0)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_59) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_864 = and(_T_862, _T_863) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_866 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_867 = or(_T_826, _T_832) node _T_868 = or(_T_867, _T_838) node _T_869 = or(_T_868, _T_844) node _T_870 = or(_T_869, _T_850) node _T_871 = or(_T_870, _T_851) node _T_872 = or(_T_871, _T_852) node _T_873 = or(_T_872, _T_858) node _T_874 = or(_T_873, _T_864) node _T_875 = or(_T_874, _T_865) node _T_876 = or(_T_875, _T_866) node _T_877 = and(_T_825, _T_876) node _T_878 = or(UInt<1>(0h0), _T_877) node _T_879 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_880 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<17>(0h10000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = and(_T_879, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = and(_T_878, _T_886) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_887, UInt<1>(0h1), "") : assert_41 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(source_ok, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(is_aligned, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_897 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_897, UInt<1>(0h1), "") : assert_44 node _T_901 = eq(io.in.a.bits.mask, mask) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_901, UInt<1>(0h1), "") : assert_45 node _T_905 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_905 : node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_908 = and(_T_906, _T_907) node _T_909 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_910 = shr(io.in.a.bits.source, 2) node _T_911 = eq(_T_910, UInt<5>(0h10)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_60) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_915 = and(_T_913, _T_914) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_916 = shr(io.in.a.bits.source, 2) node _T_917 = eq(_T_916, UInt<5>(0h11)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_61) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_922 = shr(io.in.a.bits.source, 2) node _T_923 = eq(_T_922, UInt<5>(0h12)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_62) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_928 = shr(io.in.a.bits.source, 2) node _T_929 = eq(_T_928, UInt<5>(0h13)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_63) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_936 = shr(io.in.a.bits.source, 4) node _T_937 = eq(_T_936, UInt<1>(0h1)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_64) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_942 = shr(io.in.a.bits.source, 4) node _T_943 = eq(_T_942, UInt<1>(0h0)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_65) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_947 = and(_T_945, _T_946) node _T_948 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_949 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_950 = or(_T_909, _T_915) node _T_951 = or(_T_950, _T_921) node _T_952 = or(_T_951, _T_927) node _T_953 = or(_T_952, _T_933) node _T_954 = or(_T_953, _T_934) node _T_955 = or(_T_954, _T_935) node _T_956 = or(_T_955, _T_941) node _T_957 = or(_T_956, _T_947) node _T_958 = or(_T_957, _T_948) node _T_959 = or(_T_958, _T_949) node _T_960 = and(_T_908, _T_959) node _T_961 = or(UInt<1>(0h0), _T_960) node _T_962 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_963 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_964 = cvt(_T_963) node _T_965 = and(_T_964, asSInt(UInt<17>(0h10000))) node _T_966 = asSInt(_T_965) node _T_967 = eq(_T_966, asSInt(UInt<1>(0h0))) node _T_968 = and(_T_962, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = and(_T_961, _T_969) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_970, UInt<1>(0h1), "") : assert_46 node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(is_aligned, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_980 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_980, UInt<1>(0h1), "") : assert_49 node _T_984 = eq(io.in.a.bits.mask, mask) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_984, UInt<1>(0h1), "") : assert_50 node _T_988 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_988, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_992 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_T_992, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_992, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_996 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_996 : node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(source_ok_1, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1000 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_54 node _T_1004 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_55 node _T_1008 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_56 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_57 node _T_1016 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1016 : node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(source_ok_1, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(sink_ok, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1023 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_60 node _T_1027 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_61 node _T_1031 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_62 node _T_1035 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_63 node _T_1039 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_64 node _T_1044 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1044 : node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(source_ok_1, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(sink_ok, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1051 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_67 node _T_1055 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_68 node _T_1059 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_69 node _T_1063 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1064 = or(_T_1063, io.in.d.bits.corrupt) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_70 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(UInt<1>(0h0), _T_1068) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_71 node _T_1073 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1073 : node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(source_ok_1, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1077 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_73 node _T_1081 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_74 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h0), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_75 node _T_1090 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_77 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_78 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h0), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_79 node _T_1108 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(source_ok_1, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_81 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_82 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h0), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1125 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1129 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1133 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1137 = eq(a_first, UInt<1>(0h0)) node _T_1138 = and(io.in.a.valid, _T_1137) when _T_1138 : node _T_1139 = eq(io.in.a.bits.opcode, opcode) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_87 node _T_1143 = eq(io.in.a.bits.param, param) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_88 node _T_1147 = eq(io.in.a.bits.size, size) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_89 node _T_1151 = eq(io.in.a.bits.source, source) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_90 node _T_1155 = eq(io.in.a.bits.address, address) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_91 node _T_1159 = and(io.in.a.ready, io.in.a.valid) node _T_1160 = and(_T_1159, a_first) when _T_1160 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1161 = eq(d_first, UInt<1>(0h0)) node _T_1162 = and(io.in.d.valid, _T_1161) when _T_1162 : node _T_1163 = eq(io.in.d.bits.opcode, opcode_1) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_92 node _T_1167 = eq(io.in.d.bits.param, param_1) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_93 node _T_1171 = eq(io.in.d.bits.size, size_1) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_94 node _T_1175 = eq(io.in.d.bits.source, source_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_95 node _T_1179 = eq(io.in.d.bits.sink, sink) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_96 node _T_1183 = eq(io.in.d.bits.denied, denied) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_97 node _T_1187 = and(io.in.d.ready, io.in.d.valid) node _T_1188 = and(_T_1187, d_first) when _T_1188 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1189 = and(io.in.a.valid, a_first_1) node _T_1190 = and(_T_1189, UInt<1>(0h1)) when _T_1190 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1191 = and(io.in.a.ready, io.in.a.valid) node _T_1192 = and(_T_1191, a_first_1) node _T_1193 = and(_T_1192, UInt<1>(0h1)) when _T_1193 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1194 = dshr(inflight, io.in.a.bits.source) node _T_1195 = bits(_T_1194, 0, 0) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1200 = and(io.in.d.valid, d_first_1) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = eq(d_release_ack, UInt<1>(0h0)) node _T_1203 = and(_T_1201, _T_1202) when _T_1203 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1204 = and(io.in.d.ready, io.in.d.valid) node _T_1205 = and(_T_1204, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1209 = and(io.in.d.valid, d_first_1) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = eq(d_release_ack, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) when _T_1212 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1213 = dshr(inflight, io.in.d.bits.source) node _T_1214 = bits(_T_1213, 0, 0) node _T_1215 = or(_T_1214, same_cycle_resp) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_100 node _T_1225 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_101 else : node _T_1229 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1230 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1231 = or(_T_1229, _T_1230) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_102 node _T_1235 = eq(io.in.d.bits.size, a_size_lookup) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_103 node _T_1239 = and(io.in.d.valid, d_first_1) node _T_1240 = and(_T_1239, a_first_1) node _T_1241 = and(_T_1240, io.in.a.valid) node _T_1242 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1243 = and(_T_1241, _T_1242) node _T_1244 = eq(d_release_ack, UInt<1>(0h0)) node _T_1245 = and(_T_1243, _T_1244) when _T_1245 : node _T_1246 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1247 = or(_T_1246, io.in.a.ready) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_56 node _T_1251 = orr(inflight) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) node _T_1253 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1254 = or(_T_1252, _T_1253) node _T_1255 = lt(watchdog, plusarg_reader.out) node _T_1256 = or(_T_1254, _T_1255) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1260 = and(io.in.a.ready, io.in.a.valid) node _T_1261 = and(io.in.d.ready, io.in.d.valid) node _T_1262 = or(_T_1260, _T_1261) when _T_1262 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1263 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1264 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1265 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = and(_T_1263, _T_1266) when _T_1267 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1268 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1269 = and(_T_1268, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1270 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1271 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = and(_T_1269, _T_1272) when _T_1273 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1274 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1275 = bits(_T_1274, 0, 0) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1280 = and(io.in.d.valid, d_first_2) node _T_1281 = and(_T_1280, UInt<1>(0h1)) node _T_1282 = and(_T_1281, d_release_ack_1) when _T_1282 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1283 = and(io.in.d.ready, io.in.d.valid) node _T_1284 = and(_T_1283, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1287 = and(io.in.d.valid, d_first_2) node _T_1288 = and(_T_1287, UInt<1>(0h1)) node _T_1289 = and(_T_1288, d_release_ack_1) when _T_1289 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1290 = dshr(inflight_1, io.in.d.bits.source) node _T_1291 = bits(_T_1290, 0, 0) node _T_1292 = or(_T_1291, same_cycle_resp_1) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1296 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_108 else : node _T_1300 = eq(io.in.d.bits.size, c_size_lookup) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_109 node _T_1304 = and(io.in.d.valid, d_first_2) node _T_1305 = and(_T_1304, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1306 = and(_T_1305, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1307 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = and(_T_1308, d_release_ack_1) node _T_1310 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1311 = and(_T_1309, _T_1310) when _T_1311 : node _T_1312 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1313 = or(_T_1312, _WIRE_27.ready) node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(_T_1313, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1313, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_57 node _T_1317 = orr(inflight_1) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1320 = or(_T_1318, _T_1319) node _T_1321 = lt(watchdog_1, plusarg_reader_1.out) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1326 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1327 = and(io.in.d.ready, io.in.d.valid) node _T_1328 = or(_T_1326, _T_1327) when _T_1328 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_28( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [515:0] _inflight_opcodes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [515:0] _inflight_sizes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [128:0] _inflight_T_4 = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [515:0] d_opcodes_clr_1 = 516'h0; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1 = 516'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [128:0] d_clr_1 = 129'h0; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1 = 129'h0; // @[Monitor.scala:775:34] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1260 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1260; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1260; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1328 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1328; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1328; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1328; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1260 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_4 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1206 = _T_1328 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1206 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1206 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1206 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_33 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_33 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}} wire _in_flight_WIRE : UInt<1>[6] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_138 = and(_T_136, _T_137) node _T_139 = or(_T_12, _T_19) node _T_140 = or(_T_139, _T_26) node _T_141 = or(_T_140, _T_33) node _T_142 = or(_T_141, _T_40) node _T_143 = or(_T_142, _T_47) node _T_144 = or(_T_143, _T_54) node _T_145 = or(_T_144, _T_61) node _T_146 = or(_T_145, _T_68) node _T_147 = or(_T_146, _T_75) node _T_148 = or(_T_147, _T_82) node _T_149 = or(_T_148, _T_89) node _T_150 = or(_T_149, _T_96) node _T_151 = or(_T_150, _T_103) node _T_152 = or(_T_151, _T_110) node _T_153 = or(_T_152, _T_117) node _T_154 = or(_T_153, _T_124) node _T_155 = or(_T_154, _T_131) node _T_156 = or(_T_155, _T_138) node _T_157 = or(_T_5, _T_156) node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(_T_157, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_157, UInt<1>(0h1), "") : assert_1 node _T_161 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(_T_168, _T_175) node _T_191 = or(_T_190, _T_182) node _T_192 = or(_T_191, _T_189) node _T_193 = or(_T_161, _T_192) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_193, UInt<1>(0h1), "") : assert_2 node _T_197 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_199 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_206 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_213 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_214 = and(_T_212, _T_213) node _T_215 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_220 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_221 = and(_T_219, _T_220) node _T_222 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_227 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_234 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_241 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_248 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_249 = and(_T_247, _T_248) node _T_250 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_255 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_258 = and(_T_256, _T_257) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_262 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_263 = and(_T_261, _T_262) node _T_264 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_269 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_276 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_283 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_290 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_297 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_304 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_309 = and(_T_307, _T_308) node _T_310 = or(_T_204, _T_211) node _T_311 = or(_T_310, _T_218) node _T_312 = or(_T_311, _T_225) node _T_313 = or(_T_312, _T_232) node _T_314 = or(_T_313, _T_239) node _T_315 = or(_T_314, _T_246) node _T_316 = or(_T_315, _T_253) node _T_317 = or(_T_316, _T_260) node _T_318 = or(_T_317, _T_267) node _T_319 = or(_T_318, _T_274) node _T_320 = or(_T_319, _T_281) node _T_321 = or(_T_320, _T_288) node _T_322 = or(_T_321, _T_295) node _T_323 = or(_T_322, _T_302) node _T_324 = or(_T_323, _T_309) node _T_325 = or(_T_197, _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_339 = and(_T_337, _T_338) node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_346 = and(_T_344, _T_345) node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_352 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_355 = and(_T_353, _T_354) node _T_356 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_362 = and(_T_360, _T_361) node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_364 = and(_T_362, _T_363) node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_369 = and(_T_367, _T_368) node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_371 = and(_T_369, _T_370) node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_376 = and(_T_374, _T_375) node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_385 = and(_T_383, _T_384) node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_387 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_392 = and(_T_390, _T_391) node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_394 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_399 = and(_T_397, _T_398) node _T_400 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_401 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_406 = and(_T_404, _T_405) node _T_407 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_408 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_411 = and(_T_409, _T_410) node _T_412 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_415 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_420 = and(_T_418, _T_419) node _T_421 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_422 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_425 = and(_T_423, _T_424) node _T_426 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_427 = and(_T_425, _T_426) node _T_428 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_429 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_439 = and(_T_437, _T_438) node _T_440 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_446 = and(_T_444, _T_445) node _T_447 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(_T_336, _T_343) node _T_471 = or(_T_470, _T_350) node _T_472 = or(_T_471, _T_357) node _T_473 = or(_T_472, _T_364) node _T_474 = or(_T_473, _T_371) node _T_475 = or(_T_474, _T_378) node _T_476 = or(_T_475, _T_385) node _T_477 = or(_T_476, _T_392) node _T_478 = or(_T_477, _T_399) node _T_479 = or(_T_478, _T_406) node _T_480 = or(_T_479, _T_413) node _T_481 = or(_T_480, _T_420) node _T_482 = or(_T_481, _T_427) node _T_483 = or(_T_482, _T_434) node _T_484 = or(_T_483, _T_441) node _T_485 = or(_T_484, _T_448) node _T_486 = or(_T_485, _T_455) node _T_487 = or(_T_486, _T_462) node _T_488 = or(_T_487, _T_469) node _T_489 = or(_T_329, _T_488) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_489, UInt<1>(0h1), "") : assert_4 node _T_493 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_494 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_495 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_500 = and(_T_498, _T_499) node _T_501 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_502 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_509 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_512 = and(_T_510, _T_511) node _T_513 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_514 = and(_T_512, _T_513) node _T_515 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_516 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_519 = and(_T_517, _T_518) node _T_520 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_523 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_526 = and(_T_524, _T_525) node _T_527 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_528 = and(_T_526, _T_527) node _T_529 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_530 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_535 = and(_T_533, _T_534) node _T_536 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_537 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_540 = and(_T_538, _T_539) node _T_541 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_542 = and(_T_540, _T_541) node _T_543 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_544 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_551 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_558 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_561 = and(_T_559, _T_560) node _T_562 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_565 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_566 = and(_T_564, _T_565) node _T_567 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_570 = and(_T_568, _T_569) node _T_571 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_572 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_573 = and(_T_571, _T_572) node _T_574 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_575 = and(_T_573, _T_574) node _T_576 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_577 = and(_T_575, _T_576) node _T_578 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_579 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_582 = and(_T_580, _T_581) node _T_583 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_586 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_587 = and(_T_585, _T_586) node _T_588 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_589 = and(_T_587, _T_588) node _T_590 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_593 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_596 = and(_T_594, _T_595) node _T_597 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_600 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_601 = and(_T_599, _T_600) node _T_602 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_607 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_612 = and(_T_610, _T_611) node _T_613 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_614 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) node _T_618 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_621 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_622 = and(_T_620, _T_621) node _T_623 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_624 = and(_T_622, _T_623) node _T_625 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_628 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_629 = and(_T_627, _T_628) node _T_630 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_631 = and(_T_629, _T_630) node _T_632 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(_T_500, _T_507) node _T_635 = or(_T_634, _T_514) node _T_636 = or(_T_635, _T_521) node _T_637 = or(_T_636, _T_528) node _T_638 = or(_T_637, _T_535) node _T_639 = or(_T_638, _T_542) node _T_640 = or(_T_639, _T_549) node _T_641 = or(_T_640, _T_556) node _T_642 = or(_T_641, _T_563) node _T_643 = or(_T_642, _T_570) node _T_644 = or(_T_643, _T_577) node _T_645 = or(_T_644, _T_584) node _T_646 = or(_T_645, _T_591) node _T_647 = or(_T_646, _T_598) node _T_648 = or(_T_647, _T_605) node _T_649 = or(_T_648, _T_612) node _T_650 = or(_T_649, _T_619) node _T_651 = or(_T_650, _T_626) node _T_652 = or(_T_651, _T_633) node _T_653 = or(_T_493, _T_652) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_653, UInt<1>(0h1), "") : assert_5 node _T_657 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_658 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_659 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_662 = and(_T_660, _T_661) node _T_663 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_666 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_671 = and(_T_669, _T_670) node _T_672 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_673 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_674 = and(_T_672, _T_673) node _T_675 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_676 = and(_T_674, _T_675) node _T_677 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_678 = and(_T_676, _T_677) node _T_679 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_680 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_681 = and(_T_679, _T_680) node _T_682 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_687 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_688 = and(_T_686, _T_687) node _T_689 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_690 = and(_T_688, _T_689) node _T_691 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_692 = and(_T_690, _T_691) node _T_693 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_694 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_701 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_702 = and(_T_700, _T_701) node _T_703 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_704 = and(_T_702, _T_703) node _T_705 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_706 = and(_T_704, _T_705) node _T_707 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_708 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_709 = and(_T_707, _T_708) node _T_710 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_715 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_716 = and(_T_714, _T_715) node _T_717 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_718 = and(_T_716, _T_717) node _T_719 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_722 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_727 = and(_T_725, _T_726) node _T_728 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_729 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_730 = and(_T_728, _T_729) node _T_731 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_734 = and(_T_732, _T_733) node _T_735 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_736 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_737 = and(_T_735, _T_736) node _T_738 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_741 = and(_T_739, _T_740) node _T_742 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_743 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_744 = and(_T_742, _T_743) node _T_745 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_746 = and(_T_744, _T_745) node _T_747 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_750 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _T_752 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_753 = and(_T_751, _T_752) node _T_754 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_755 = and(_T_753, _T_754) node _T_756 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_757 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_762 = and(_T_760, _T_761) node _T_763 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_764 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_765 = and(_T_763, _T_764) node _T_766 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_769 = and(_T_767, _T_768) node _T_770 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_771 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_774 = and(_T_772, _T_773) node _T_775 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_776 = and(_T_774, _T_775) node _T_777 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_778 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_779 = and(_T_777, _T_778) node _T_780 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) node _T_784 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_785 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_786 = and(_T_784, _T_785) node _T_787 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_788 = and(_T_786, _T_787) node _T_789 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_790 = and(_T_788, _T_789) node _T_791 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_792 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_797 = and(_T_795, _T_796) node _T_798 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_799 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) node _T_803 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_804 = and(_T_802, _T_803) node _T_805 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_806 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_811 = and(_T_809, _T_810) node _T_812 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_813 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_816 = and(_T_814, _T_815) node _T_817 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_820 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_821 = and(_T_819, _T_820) node _T_822 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_823 = and(_T_821, _T_822) node _T_824 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_825 = and(_T_823, _T_824) node _T_826 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_827 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_830 = and(_T_828, _T_829) node _T_831 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_832 = and(_T_830, _T_831) node _T_833 = or(_T_664, _T_671) node _T_834 = or(_T_833, _T_678) node _T_835 = or(_T_834, _T_685) node _T_836 = or(_T_835, _T_692) node _T_837 = or(_T_836, _T_699) node _T_838 = or(_T_837, _T_706) node _T_839 = or(_T_838, _T_713) node _T_840 = or(_T_839, _T_720) node _T_841 = or(_T_840, _T_727) node _T_842 = or(_T_841, _T_734) node _T_843 = or(_T_842, _T_741) node _T_844 = or(_T_843, _T_748) node _T_845 = or(_T_844, _T_755) node _T_846 = or(_T_845, _T_762) node _T_847 = or(_T_846, _T_769) node _T_848 = or(_T_847, _T_776) node _T_849 = or(_T_848, _T_783) node _T_850 = or(_T_849, _T_790) node _T_851 = or(_T_850, _T_797) node _T_852 = or(_T_851, _T_804) node _T_853 = or(_T_852, _T_811) node _T_854 = or(_T_853, _T_818) node _T_855 = or(_T_854, _T_825) node _T_856 = or(_T_855, _T_832) node _T_857 = or(_T_657, _T_856) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_857, UInt<1>(0h1), "") : assert_6	module NoCMonitor_5( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_41 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} input tick : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst clint of CLINT connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 connect intsource.clock, childClock connect intsource.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn connect intsource.auto.in[0], clint.auto.int_out[0] connect intsource.auto.in[1], clint.auto.int_out[1] connect intInClockXingIn, intsource.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out, intInClockXingOut connect clint.auto.in, auto.clint_in connect clint.io.rtcTick, tick connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_103 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_104 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_sync_1, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input tick, // @[CLINT.scala:115:20] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _clint_auto_int_out_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1; // @[CLINT.scala:112:48] CLINT clint ( // @[CLINT.scala:112:48] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_out_0 (_clint_auto_int_out_0), .auto_int_out_1 (_clint_auto_int_out_1), .auto_in_a_ready (auto_clint_in_a_ready), .auto_in_a_valid (auto_clint_in_a_valid), .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode), .auto_in_a_bits_param (auto_clint_in_a_bits_param), .auto_in_a_bits_size (auto_clint_in_a_bits_size), .auto_in_a_bits_source (auto_clint_in_a_bits_source), .auto_in_a_bits_address (auto_clint_in_a_bits_address), .auto_in_a_bits_mask (auto_clint_in_a_bits_mask), .auto_in_a_bits_data (auto_clint_in_a_bits_data), .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt), .auto_in_d_ready (auto_clint_in_d_ready), .auto_in_d_valid (auto_clint_in_d_valid), .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode), .auto_in_d_bits_size (auto_clint_in_d_bits_size), .auto_in_d_bits_source (auto_clint_in_d_bits_source), .auto_in_d_bits_data (auto_clint_in_d_bits_data), .io_rtcTick (tick) ); // @[CLINT.scala:112:48] IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_clint_auto_int_out_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0), .auto_out_sync_1 (auto_int_in_clock_xing_out_sync_1) ); // @[Crossing.scala:29:31] assign clock = auto_clock_in_clock; // @[ClockDomain.scala:14:9] assign reset = auto_clock_in_reset; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_52 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_52 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}[1], flip in_b : { bits : UInt<32>}[1], flip in_d : { bits : UInt<32>}[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<4>[1], flip in_last : UInt<1>[1], out_a : { bits : UInt<32>}[1], out_c : { bits : UInt<32>}[1], out_b : { bits : UInt<32>}[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<4>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_16 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a.bits, io.in_a[0].bits connect tile_0_0.io.in_b.bits, io.in_b[0].bits connect tile_0_0.io.in_d.bits, io.in_d[0].bits connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [3:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [3:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_16 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7] .io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7] .io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7] .io_out_a_bits (io_out_a_0_bits_0), .io_out_b_bits (io_out_b_0_bits_0), .io_out_c_bits (io_out_c_0_bits_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7] assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7] assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_48 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_48( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready	module TLBuffer_a32d64s2k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [7:0] _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21] wire _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_b_ready (auto_in_b_ready), .io_in_b_valid (_nodeIn_b_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address), // @[Decoupled.scala:362:21] .io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask), // @[Decoupled.scala:362:21] .io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21] .io_in_c_ready (_nodeOut_c_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_c_valid (auto_in_c_valid), .io_in_c_bits_opcode (auto_in_c_bits_opcode), .io_in_c_bits_param (auto_in_c_bits_param), .io_in_c_bits_size (auto_in_c_bits_size), .io_in_c_bits_source (auto_in_c_bits_source), .io_in_c_bits_address (auto_in_c_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21] .io_in_e_ready (_nodeOut_e_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_e_valid (auto_in_e_valid), .io_in_e_bits_sink (auto_in_e_bits_sink) ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_b_ready), .io_enq_valid (auto_out_b_valid), .io_enq_bits_param (auto_out_b_bits_param), .io_enq_bits_address (auto_out_b_bits_address), .io_deq_ready (auto_in_b_ready), .io_deq_valid (_nodeIn_b_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source), .io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address), .io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask), .io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_c_q_io_enq_ready), .io_enq_valid (auto_in_c_valid), .io_enq_bits_opcode (auto_in_c_bits_opcode), .io_enq_bits_param (auto_in_c_bits_param), .io_enq_bits_size (auto_in_c_bits_size), .io_enq_bits_source (auto_in_c_bits_source), .io_enq_bits_address (auto_in_c_bits_address), .io_enq_bits_data (auto_in_c_bits_data), .io_deq_ready (auto_out_c_ready), .io_deq_valid (auto_out_c_valid), .io_deq_bits_opcode (auto_out_c_bits_opcode), .io_deq_bits_param (auto_out_c_bits_param), .io_deq_bits_size (auto_out_c_bits_size), .io_deq_bits_source (auto_out_c_bits_source), .io_deq_bits_address (auto_out_c_bits_address), .io_deq_bits_data (auto_out_c_bits_data), .io_deq_bits_corrupt (auto_out_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_e_q_io_enq_ready), .io_enq_valid (auto_in_e_valid), .io_enq_bits_sink (auto_in_e_bits_sink), .io_deq_valid (auto_out_e_valid), .io_deq_bits_sink (auto_out_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21] assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21] assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<19>(0h40000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_78 = or(UInt<1>(0h0), _T_77) node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = and(_T_78, _T_89) node _T_91 = or(UInt<1>(0h0), _T_76) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_21, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_93, UInt<1>(0h1), "") : assert_2 node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(UInt<1>(0h0), _T_99) node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<19>(0h40000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_105, _T_110) node _T_157 = or(_T_156, _T_115) node _T_158 = or(_T_157, _T_120) node _T_159 = or(_T_158, _T_125) node _T_160 = or(_T_159, _T_130) node _T_161 = or(_T_160, _T_135) node _T_162 = or(_T_161, _T_140) node _T_163 = or(_T_162, _T_145) node _T_164 = or(_T_163, _T_150) node _T_165 = or(_T_164, _T_155) node _T_166 = and(_T_100, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(UInt<1>(0h0), _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_168, UInt<1>(0h1), "") : assert_3 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_175 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_175, UInt<1>(0h1), "") : assert_5 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(is_aligned, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_183 = asUInt(reset) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : node _T_185 = eq(_T_182, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_182, UInt<1>(0h1), "") : assert_7 node _T_186 = not(io.in.a.bits.mask) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_187, UInt<1>(0h1), "") : assert_8 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_191, UInt<1>(0h1), "") : assert_9 node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<19>(0h40000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_207, _T_212) node _T_249 = or(_T_248, _T_217) node _T_250 = or(_T_249, _T_222) node _T_251 = or(_T_250, _T_227) node _T_252 = or(_T_251, _T_232) node _T_253 = or(_T_252, _T_237) node _T_254 = or(_T_253, _T_242) node _T_255 = or(_T_254, _T_247) node _T_256 = and(_T_202, _T_255) node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = or(_T_263, _T_268) node _T_270 = and(_T_258, _T_269) node _T_271 = or(UInt<1>(0h0), _T_256) node _T_272 = or(_T_271, _T_270) node _T_273 = and(_T_201, _T_272) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_273, UInt<1>(0h1), "") : assert_10 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<19>(0h40000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = or(_T_285, _T_290) node _T_337 = or(_T_336, _T_295) node _T_338 = or(_T_337, _T_300) node _T_339 = or(_T_338, _T_305) node _T_340 = or(_T_339, _T_310) node _T_341 = or(_T_340, _T_315) node _T_342 = or(_T_341, _T_320) node _T_343 = or(_T_342, _T_325) node _T_344 = or(_T_343, _T_330) node _T_345 = or(_T_344, _T_335) node _T_346 = and(_T_280, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_348, UInt<1>(0h1), "") : assert_11 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_355, UInt<1>(0h1), "") : assert_13 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_362, UInt<1>(0h1), "") : assert_15 node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_366, UInt<1>(0h1), "") : assert_16 node _T_370 = not(io.in.a.bits.mask) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_371, UInt<1>(0h1), "") : assert_17 node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_375, UInt<1>(0h1), "") : assert_18 node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_379 : node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(UInt<1>(0h0), _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_385, UInt<1>(0h1), "") : assert_19 node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_394 = cvt(_T_393) node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000))) node _T_396 = asSInt(_T_395) node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0))) node _T_398 = and(_T_392, _T_397) node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = or(UInt<1>(0h0), _T_401) node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_404 = cvt(_T_403) node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000))) node _T_406 = asSInt(_T_405) node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0))) node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_419 = cvt(_T_418) node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000))) node _T_421 = asSInt(_T_420) node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0))) node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_424 = cvt(_T_423) node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000))) node _T_426 = asSInt(_T_425) node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0))) node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_434 = cvt(_T_433) node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000))) node _T_436 = asSInt(_T_435) node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0))) node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_439 = cvt(_T_438) node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000))) node _T_441 = asSInt(_T_440) node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0))) node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_444 = cvt(_T_443) node _T_445 = and(_T_444, asSInt(UInt<19>(0h40000))) node _T_446 = asSInt(_T_445) node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0))) node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = or(_T_407, _T_412) node _T_454 = or(_T_453, _T_417) node _T_455 = or(_T_454, _T_422) node _T_456 = or(_T_455, _T_427) node _T_457 = or(_T_456, _T_432) node _T_458 = or(_T_457, _T_437) node _T_459 = or(_T_458, _T_442) node _T_460 = or(_T_459, _T_447) node _T_461 = or(_T_460, _T_452) node _T_462 = and(_T_402, _T_461) node _T_463 = or(UInt<1>(0h0), _T_398) node _T_464 = or(_T_463, _T_462) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_464, UInt<1>(0h1), "") : assert_20 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(is_aligned, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_474, UInt<1>(0h1), "") : assert_23 node _T_478 = eq(io.in.a.bits.mask, mask) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_478, UInt<1>(0h1), "") : assert_24 node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_482, UInt<1>(0h1), "") : assert_25 node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_486 : node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(UInt<1>(0h0), _T_495) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = and(_T_496, _T_501) node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<19>(0h40000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = or(_T_511, _T_516) node _T_553 = or(_T_552, _T_521) node _T_554 = or(_T_553, _T_526) node _T_555 = or(_T_554, _T_531) node _T_556 = or(_T_555, _T_536) node _T_557 = or(_T_556, _T_541) node _T_558 = or(_T_557, _T_546) node _T_559 = or(_T_558, _T_551) node _T_560 = and(_T_506, _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = and(_T_561, _T_566) node _T_568 = or(UInt<1>(0h0), _T_502) node _T_569 = or(_T_568, _T_560) node _T_570 = or(_T_569, _T_567) node _T_571 = and(_T_492, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_571, UInt<1>(0h1), "") : assert_26 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_581, UInt<1>(0h1), "") : assert_29 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_585, UInt<1>(0h1), "") : assert_30 node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) node _T_595 = or(UInt<1>(0h0), _T_594) node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_601 = cvt(_T_600) node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000))) node _T_603 = asSInt(_T_602) node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0))) node _T_605 = and(_T_599, _T_604) node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<19>(0h40000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = or(_T_614, _T_619) node _T_656 = or(_T_655, _T_624) node _T_657 = or(_T_656, _T_629) node _T_658 = or(_T_657, _T_634) node _T_659 = or(_T_658, _T_639) node _T_660 = or(_T_659, _T_644) node _T_661 = or(_T_660, _T_649) node _T_662 = or(_T_661, _T_654) node _T_663 = and(_T_609, _T_662) node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_605) node _T_672 = or(_T_671, _T_663) node _T_673 = or(_T_672, _T_670) node _T_674 = and(_T_595, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_674, UInt<1>(0h1), "") : assert_31 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_684, UInt<1>(0h1), "") : assert_34 node _T_688 = not(mask) node _T_689 = and(io.in.a.bits.mask, _T_688) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_690, UInt<1>(0h1), "") : assert_35 node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = or(UInt<1>(0h0), _T_699) node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<17>(0h10000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<27>(0h4000000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<19>(0h40000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<29>(0h10000000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = or(_T_709, _T_714) node _T_756 = or(_T_755, _T_719) node _T_757 = or(_T_756, _T_724) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_739) node _T_761 = or(_T_760, _T_744) node _T_762 = or(_T_761, _T_749) node _T_763 = or(_T_762, _T_754) node _T_764 = and(_T_704, _T_763) node _T_765 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_764) node _T_773 = or(_T_772, _T_771) node _T_774 = and(_T_700, _T_773) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_774, UInt<1>(0h1), "") : assert_36 node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(is_aligned, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_784 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_784, UInt<1>(0h1), "") : assert_39 node _T_788 = eq(io.in.a.bits.mask, mask) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_788, UInt<1>(0h1), "") : assert_40 node _T_792 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_792 : node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_797 = and(_T_795, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_800 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<14>(0h2000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<13>(0h1000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<18>(0h2f000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<17>(0h10000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<13>(0h1000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<17>(0h10000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<19>(0h40000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<29>(0h10000000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = or(_T_807, _T_812) node _T_854 = or(_T_853, _T_817) node _T_855 = or(_T_854, _T_822) node _T_856 = or(_T_855, _T_827) node _T_857 = or(_T_856, _T_832) node _T_858 = or(_T_857, _T_837) node _T_859 = or(_T_858, _T_842) node _T_860 = or(_T_859, _T_847) node _T_861 = or(_T_860, _T_852) node _T_862 = and(_T_802, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = and(_T_863, _T_868) node _T_870 = or(UInt<1>(0h0), _T_862) node _T_871 = or(_T_870, _T_869) node _T_872 = and(_T_798, _T_871) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_872, UInt<1>(0h1), "") : assert_41 node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(is_aligned, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_882 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_882, UInt<1>(0h1), "") : assert_44 node _T_886 = eq(io.in.a.bits.mask, mask) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_886, UInt<1>(0h1), "") : assert_45 node _T_890 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_890 : node _T_891 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_892 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_893 = and(_T_891, _T_892) node _T_894 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_895 = and(_T_893, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = and(_T_900, _T_905) node _T_907 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_908 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_909 = cvt(_T_908) node _T_910 = and(_T_909, asSInt(UInt<14>(0h2000))) node _T_911 = asSInt(_T_910) node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0))) node _T_913 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<17>(0h10000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<18>(0h2f000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<13>(0h1000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<27>(0h4000000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<19>(0h40000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = or(_T_912, _T_917) node _T_949 = or(_T_948, _T_922) node _T_950 = or(_T_949, _T_927) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_937) node _T_953 = or(_T_952, _T_942) node _T_954 = or(_T_953, _T_947) node _T_955 = and(_T_907, _T_954) node _T_956 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_957 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_958 = and(_T_956, _T_957) node _T_959 = or(UInt<1>(0h0), _T_958) node _T_960 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_961 = cvt(_T_960) node _T_962 = and(_T_961, asSInt(UInt<17>(0h10000))) node _T_963 = asSInt(_T_962) node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0))) node _T_965 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_966 = cvt(_T_965) node _T_967 = and(_T_966, asSInt(UInt<29>(0h10000000))) node _T_968 = asSInt(_T_967) node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0))) node _T_970 = or(_T_964, _T_969) node _T_971 = and(_T_959, _T_970) node _T_972 = or(UInt<1>(0h0), _T_906) node _T_973 = or(_T_972, _T_955) node _T_974 = or(_T_973, _T_971) node _T_975 = and(_T_896, _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_975, UInt<1>(0h1), "") : assert_46 node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(is_aligned, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_985 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_985, UInt<1>(0h1), "") : assert_49 node _T_989 = eq(io.in.a.bits.mask, mask) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_989, UInt<1>(0h1), "") : assert_50 node _T_993 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_993, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_997 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_997, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1001 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1001 : node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_54 node _T_1009 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_55 node _T_1013 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_56 node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_57 node _T_1021 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1021 : node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(sink_ok, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1028 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_60 node _T_1032 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_61 node _T_1036 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_62 node _T_1040 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_63 node _T_1044 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1045 = or(UInt<1>(0h1), _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_64 node _T_1049 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1049 : node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(sink_ok, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1056 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_67 node _T_1060 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_68 node _T_1064 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_69 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(_T_1068, io.in.d.bits.corrupt) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_70 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = or(UInt<1>(0h1), _T_1073) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_71 node _T_1078 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1078 : node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_73 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_74 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = or(UInt<1>(0h1), _T_1090) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_75 node _T_1095 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1095 : node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1099 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_77 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(_T_1103, io.in.d.bits.corrupt) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_78 node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1109 = or(UInt<1>(0h1), _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_79 node _T_1113 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1117 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_81 node _T_1121 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_82 node _T_1125 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1126 = or(UInt<1>(0h1), _T_1125) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1130 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1134 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1138 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1142 = eq(a_first, UInt<1>(0h0)) node _T_1143 = and(io.in.a.valid, _T_1142) when _T_1143 : node _T_1144 = eq(io.in.a.bits.opcode, opcode) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_87 node _T_1148 = eq(io.in.a.bits.param, param) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_88 node _T_1152 = eq(io.in.a.bits.size, size) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_89 node _T_1156 = eq(io.in.a.bits.source, source) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_90 node _T_1160 = eq(io.in.a.bits.address, address) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_91 node _T_1164 = and(io.in.a.ready, io.in.a.valid) node _T_1165 = and(_T_1164, a_first) when _T_1165 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1166 = eq(d_first, UInt<1>(0h0)) node _T_1167 = and(io.in.d.valid, _T_1166) when _T_1167 : node _T_1168 = eq(io.in.d.bits.opcode, opcode_1) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_92 node _T_1172 = eq(io.in.d.bits.param, param_1) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_93 node _T_1176 = eq(io.in.d.bits.size, size_1) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_94 node _T_1180 = eq(io.in.d.bits.source, source_1) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_95 node _T_1184 = eq(io.in.d.bits.sink, sink) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_96 node _T_1188 = eq(io.in.d.bits.denied, denied) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_97 node _T_1192 = and(io.in.d.ready, io.in.d.valid) node _T_1193 = and(_T_1192, d_first) when _T_1193 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1194 = and(io.in.a.valid, a_first_1) node _T_1195 = and(_T_1194, UInt<1>(0h1)) when _T_1195 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1196 = and(io.in.a.ready, io.in.a.valid) node _T_1197 = and(_T_1196, a_first_1) node _T_1198 = and(_T_1197, UInt<1>(0h1)) when _T_1198 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1199 = dshr(inflight, io.in.a.bits.source) node _T_1200 = bits(_T_1199, 0, 0) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1205 = and(io.in.d.valid, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1209 = and(io.in.d.ready, io.in.d.valid) node _T_1210 = and(_T_1209, d_first_1) node _T_1211 = and(_T_1210, UInt<1>(0h1)) node _T_1212 = eq(d_release_ack, UInt<1>(0h0)) node _T_1213 = and(_T_1211, _T_1212) when _T_1213 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1214 = and(io.in.d.valid, d_first_1) node _T_1215 = and(_T_1214, UInt<1>(0h1)) node _T_1216 = eq(d_release_ack, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1218 = dshr(inflight, io.in.d.bits.source) node _T_1219 = bits(_T_1218, 0, 0) node _T_1220 = or(_T_1219, same_cycle_resp) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1224 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1225 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1226 = or(_T_1224, _T_1225) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_100 node _T_1230 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_101 else : node _T_1234 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1236 = or(_T_1234, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_102 node _T_1240 = eq(io.in.d.bits.size, a_size_lookup) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_103 node _T_1244 = and(io.in.d.valid, d_first_1) node _T_1245 = and(_T_1244, a_first_1) node _T_1246 = and(_T_1245, io.in.a.valid) node _T_1247 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = eq(d_release_ack, UInt<1>(0h0)) node _T_1250 = and(_T_1248, _T_1249) when _T_1250 : node _T_1251 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1252 = or(_T_1251, io.in.a.ready) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_104 node _T_1256 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1257 = orr(a_set_wo_ready) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) node _T_1259 = or(_T_1256, _T_1258) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_1263 = orr(inflight) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1266 = or(_T_1264, _T_1265) node _T_1267 = lt(watchdog, plusarg_reader.out) node _T_1268 = or(_T_1266, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1272 = and(io.in.a.ready, io.in.a.valid) node _T_1273 = and(io.in.d.ready, io.in.d.valid) node _T_1274 = or(_T_1272, _T_1273) when _T_1274 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1275 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1276 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1277 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1275, _T_1278) when _T_1279 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1280 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1281 = and(_T_1280, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1282 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1283 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = and(_T_1281, _T_1284) when _T_1285 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1286 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1287 = bits(_T_1286, 0, 0) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1292 = and(io.in.d.valid, d_first_2) node _T_1293 = and(_T_1292, UInt<1>(0h1)) node _T_1294 = and(_T_1293, d_release_ack_1) when _T_1294 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1295 = and(io.in.d.ready, io.in.d.valid) node _T_1296 = and(_T_1295, d_first_2) node _T_1297 = and(_T_1296, UInt<1>(0h1)) node _T_1298 = and(_T_1297, d_release_ack_1) when _T_1298 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1299 = and(io.in.d.valid, d_first_2) node _T_1300 = and(_T_1299, UInt<1>(0h1)) node _T_1301 = and(_T_1300, d_release_ack_1) when _T_1301 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1302 = dshr(inflight_1, io.in.d.bits.source) node _T_1303 = bits(_T_1302, 0, 0) node _T_1304 = or(_T_1303, same_cycle_resp_1) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1308 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_109 else : node _T_1312 = eq(io.in.d.bits.size, c_size_lookup) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110 node _T_1316 = and(io.in.d.valid, d_first_2) node _T_1317 = and(_T_1316, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1318 = and(_T_1317, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1319 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = and(_T_1320, d_release_ack_1) node _T_1322 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1323 = and(_T_1321, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1325 = or(_T_1324, _WIRE_23.ready) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_111 node _T_1329 = orr(c_set_wo_ready) when _T_1329 : node _T_1330 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_1334 = orr(inflight_1) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) node _T_1336 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1337 = or(_T_1335, _T_1336) node _T_1338 = lt(watchdog_1, plusarg_reader_1.out) node _T_1339 = or(_T_1337, _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1343 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1344 = and(io.in.d.ready, io.in.d.valid) node _T_1345 = or(_T_1343, _T_1344) when _T_1345 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_451 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_451( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_116 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_116( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_170 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_170( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_13 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_13 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_30 of InputUnit_13 connect input_unit_0_from_30.clock, clock connect input_unit_0_from_30.reset, reset inst ingress_unit_1_from_24 of IngressUnit_34 connect ingress_unit_1_from_24.clock, clock connect ingress_unit_1_from_24.reset, reset inst ingress_unit_2_from_25 of IngressUnit_35 connect ingress_unit_2_from_25.clock, clock connect ingress_unit_2_from_25.reset, reset inst ingress_unit_3_from_26 of IngressUnit_36 connect ingress_unit_3_from_26.clock, clock connect ingress_unit_3_from_26.reset, reset inst output_unit_0_to_30 of OutputUnit_13 connect output_unit_0_to_30.clock, clock connect output_unit_0_to_30.reset, reset inst egress_unit_1_to_16 of EgressUnit_31 connect egress_unit_1_to_16.clock, clock connect egress_unit_1_to_16.reset, reset inst egress_unit_2_to_17 of EgressUnit_32 connect egress_unit_2_to_17.clock, clock connect egress_unit_2_to_17.reset, reset inst switch of Switch_13 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_13 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_13 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_13 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_30.io.in, destNodesIn connect ingress_unit_1_from_24.io.in, ingressNodesIn.flit connect ingress_unit_2_from_25.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_26.io.in, ingressNodesIn_2.flit connect output_unit_0_to_30.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_30.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_30.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_16.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_16.io.out.valid connect egress_unit_1_to_16.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_17.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_17.io.out.valid connect egress_unit_2_to_17.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_30.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_24.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_25.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_26.io.router_req connect input_unit_0_from_30.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_24.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_25.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_26.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_30.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_24.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_25.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_26.io.vcalloc_req connect input_unit_0_from_30.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_24.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_25.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_26.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_30.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_16.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_17.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_30.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_30.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_30.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_30.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_30.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_30.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_30.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_30.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_30.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_30.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_30.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_30.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_30.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_30.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_30.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_30.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_30.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_30.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_30.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_30.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_30.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_30.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_30.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_30.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_30.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_30.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_30.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_30.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_30.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_30.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_30.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_30.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_30.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_30.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_30.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_30.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_30.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_30.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_30.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_30.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_16.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_16.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_16.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_16.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_16.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_16.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_17.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_17.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_17.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_17.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_17.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_17.io.channel_status[0].occupied connect input_unit_0_from_30.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect input_unit_0_from_30.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect input_unit_0_from_30.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect input_unit_0_from_30.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect input_unit_0_from_30.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect input_unit_0_from_30.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect input_unit_0_from_30.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect input_unit_0_from_30.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect input_unit_0_from_30.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect input_unit_0_from_30.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_1_from_24.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_1_from_24.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_1_from_24.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_1_from_24.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_1_from_24.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_1_from_24.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_1_from_24.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_2_from_25.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_2_from_25.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_2_from_25.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_2_from_25.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_2_from_25.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_2_from_25.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_2_from_25.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_3_from_26.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_3_from_26.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_3_from_26.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_3_from_26.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_3_from_26.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_3_from_26.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_3_from_26.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_30.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_24.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_25.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_26.io.salloc_req[0] connect output_unit_0_to_30.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_30.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_30.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_30.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_30.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_30.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_30.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_30.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_30.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_30.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_30.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_30.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_30.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_30.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_30.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_30.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_16.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_16.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_17.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_17.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_30.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_24.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_25.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_26.io.out[0] connect output_unit_0_to_30.io.in, switch.io.out.`0` connect egress_unit_1_to_16.io.in, switch.io.out.`1` connect egress_unit_2_to_17.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_30.io.block, UInt<1>(0h0) connect ingress_unit_1_from_24.io.block, UInt<1>(0h0) connect ingress_unit_2_from_25.io.block, UInt<1>(0h0) connect ingress_unit_3_from_26.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_30.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_24.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_25.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_26.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_30.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_24.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_25.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_26.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_31 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 30 14 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i24 14 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i25 14 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i26 14 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 14 e16 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 14 e17 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47	module Router_13( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_17_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_17_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_17_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_30_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_26_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_26_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_26_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_25_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_25_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_24_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_24_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_30_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_30_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_30_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_24_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_25_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_26_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module PE_215 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_215( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DTLB_18 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) node memIdx = bits(vpn, 1, 0) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4][4], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[1], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<0>, clock reg r_sectored_repl_addr : UInt<2>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_140 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_18 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_18 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _sector_hits_T_1 = shr(_sector_hits_T, 0) node _sector_hits_T_2 = eq(_sector_hits_T_1, UInt<1>(0h0)) node _sector_hits_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _sector_hits_T_4 = and(_sector_hits_T_2, _sector_hits_T_3) node sector_hits_0 = and(sectored_entries[memIdx][0].valid[0], _sector_hits_T_4) node _sector_hits_T_5 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _sector_hits_T_6 = shr(_sector_hits_T_5, 0) node _sector_hits_T_7 = eq(_sector_hits_T_6, UInt<1>(0h0)) node _sector_hits_T_8 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _sector_hits_T_9 = and(_sector_hits_T_7, _sector_hits_T_8) node sector_hits_1 = and(sectored_entries[memIdx][1].valid[0], _sector_hits_T_9) node _sector_hits_T_10 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _sector_hits_T_11 = shr(_sector_hits_T_10, 0) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _sector_hits_T_14 = and(_sector_hits_T_12, _sector_hits_T_13) node sector_hits_2 = and(sectored_entries[memIdx][2].valid[0], _sector_hits_T_14) node _sector_hits_T_15 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _sector_hits_T_16 = shr(_sector_hits_T_15, 0) node _sector_hits_T_17 = eq(_sector_hits_T_16, UInt<1>(0h0)) node _sector_hits_T_18 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _sector_hits_T_19 = and(_sector_hits_T_17, _sector_hits_T_18) node sector_hits_3 = and(sectored_entries[memIdx][3].valid[0], _sector_hits_T_19) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _hitsVec_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 0) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[memIdx][0].valid[0], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_T_6 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[memIdx][1].valid[0], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node _hitsVec_T_12 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[memIdx][2].valid[0], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node _hitsVec_T_18 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[memIdx][3].valid[0], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_24 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_25 = bits(_hitsVec_T_24, 26, 18) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = or(hitsVec_ignore, _hitsVec_T_26) node _hitsVec_T_28 = and(hitsVec_tagMatch, _hitsVec_T_27) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_29 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_30 = bits(_hitsVec_T_29, 17, 9) node _hitsVec_T_31 = eq(_hitsVec_T_30, UInt<1>(0h0)) node _hitsVec_T_32 = or(hitsVec_ignore_1, _hitsVec_T_31) node _hitsVec_T_33 = and(_hitsVec_T_28, _hitsVec_T_32) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_34 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_35 = bits(_hitsVec_T_34, 8, 0) node _hitsVec_T_36 = eq(_hitsVec_T_35, UInt<1>(0h0)) node _hitsVec_T_37 = or(hitsVec_ignore_2, _hitsVec_T_36) node _hitsVec_T_38 = and(_hitsVec_T_33, _hitsVec_T_37) node hitsVec_4 = and(vm_enabled, _hitsVec_T_38) node _hitsVec_tagMatch_T_1 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_1 = and(special_entry.valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_39 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_40 = bits(_hitsVec_T_39, 26, 18) node _hitsVec_T_41 = eq(_hitsVec_T_40, UInt<1>(0h0)) node _hitsVec_T_42 = or(hitsVec_ignore_3, _hitsVec_T_41) node _hitsVec_T_43 = and(hitsVec_tagMatch_1, _hitsVec_T_42) node _hitsVec_ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_44 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_45 = bits(_hitsVec_T_44, 17, 9) node _hitsVec_T_46 = eq(_hitsVec_T_45, UInt<1>(0h0)) node _hitsVec_T_47 = or(hitsVec_ignore_4, _hitsVec_T_46) node _hitsVec_T_48 = and(_hitsVec_T_43, _hitsVec_T_47) node _hitsVec_ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h0)) node _hitsVec_T_49 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_50 = bits(_hitsVec_T_49, 8, 0) node _hitsVec_T_51 = eq(_hitsVec_T_50, UInt<1>(0h0)) node _hitsVec_T_52 = or(hitsVec_ignore_5, _hitsVec_T_51) node _hitsVec_T_53 = and(_hitsVec_T_48, _hitsVec_T_52) node hitsVec_5 = and(vm_enabled, _hitsVec_T_53) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node r_memIdx = bits(r_refill_tag, 1, 0) node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_4 = eq(waddr_1, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_5 : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][0].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][0].tag_v, refill_v connect sectored_entries[r_memIdx][0].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h1) node sectored_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_0_lo_lo_hi = cat(sectored_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_data_0_lo_lo = cat(sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo) node sectored_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_0_lo_hi_lo = cat(sectored_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_data_0_lo_hi_hi = cat(sectored_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_data_0_lo_hi = cat(sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo) node sectored_entries_0_data_0_lo = cat(sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo) node sectored_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_data_0_hi_lo_lo = cat(sectored_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_data_0_hi_lo_hi = cat(sectored_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_data_0_hi_lo = cat(sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo) node sectored_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_data_0_hi_hi_lo = cat(sectored_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_0_hi_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_data_0_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo) node sectored_entries_0_data_0_hi = cat(sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo) node _sectored_entries_0_data_0_T = cat(sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo) connect sectored_entries[r_memIdx][0].data[0], _sectored_entries_0_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) node _T_6 = eq(waddr_1, UInt<1>(0h1)) when _T_6 : node _T_7 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_7 : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][1].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][1].tag_v, refill_v connect sectored_entries[r_memIdx][1].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h1) node sectored_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_0_lo_lo_hi = cat(sectored_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_1_data_0_lo_lo = cat(sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo) node sectored_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_0_lo_hi_lo = cat(sectored_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_1_data_0_lo_hi_hi = cat(sectored_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_1_data_0_lo_hi = cat(sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo) node sectored_entries_1_data_0_lo = cat(sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo) node sectored_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_1_data_0_hi_lo_lo = cat(sectored_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_1_data_0_hi_lo_hi = cat(sectored_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_1_data_0_hi_lo = cat(sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo) node sectored_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_1_data_0_hi_hi_lo = cat(sectored_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_0_hi_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_1_data_0_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo) node sectored_entries_1_data_0_hi = cat(sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo) node _sectored_entries_1_data_0_T = cat(sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo) connect sectored_entries[r_memIdx][1].data[0], _sectored_entries_1_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) node _T_8 = eq(waddr_1, UInt<2>(0h2)) when _T_8 : node _T_9 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_9 : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][2].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][2].tag_v, refill_v connect sectored_entries[r_memIdx][2].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h1) node sectored_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_0_lo_lo_hi = cat(sectored_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_2_data_0_lo_lo = cat(sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo) node sectored_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_0_lo_hi_lo = cat(sectored_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_2_data_0_lo_hi_hi = cat(sectored_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_2_data_0_lo_hi = cat(sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo) node sectored_entries_2_data_0_lo = cat(sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo) node sectored_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_2_data_0_hi_lo_lo = cat(sectored_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_2_data_0_hi_lo_hi = cat(sectored_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_2_data_0_hi_lo = cat(sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo) node sectored_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_2_data_0_hi_hi_lo = cat(sectored_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_0_hi_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_2_data_0_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo) node sectored_entries_2_data_0_hi = cat(sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo) node _sectored_entries_2_data_0_T = cat(sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo) connect sectored_entries[r_memIdx][2].data[0], _sectored_entries_2_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) node _T_10 = eq(waddr_1, UInt<2>(0h3)) when _T_10 : node _T_11 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_11 : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][3].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][3].tag_v, refill_v connect sectored_entries[r_memIdx][3].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h1) node sectored_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_0_lo_lo_hi = cat(sectored_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_3_data_0_lo_lo = cat(sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo) node sectored_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_0_lo_hi_lo = cat(sectored_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_3_data_0_lo_hi_hi = cat(sectored_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_3_data_0_lo_hi = cat(sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo) node sectored_entries_3_data_0_lo = cat(sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo) node sectored_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_3_data_0_hi_lo_lo = cat(sectored_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_3_data_0_hi_lo_hi = cat(sectored_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_3_data_0_hi_lo = cat(sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo) node sectored_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_3_data_0_hi_hi_lo = cat(sectored_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_0_hi_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_3_data_0_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo) node sectored_entries_3_data_0_hi = cat(sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo) node _sectored_entries_3_data_0_T = cat(sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo) connect sectored_entries[r_memIdx][3].data[0], _sectored_entries_3_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[memIdx][0].data[0] node _entries_T = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T node _entries_T_1 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_22 inst entries_barrier of OptimizationBarrier_TLBEntryData_141 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[memIdx][1].data[0] node _entries_T_23 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_45 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_142 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[memIdx][2].data[0] node _entries_T_46 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_68 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_143 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[memIdx][3].data[0] node _entries_T_69 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_91 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_144 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[0].data[0] node _entries_T_92 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_114 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_145 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_115 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_137 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_146 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_4.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_4.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_5.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h0)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_5.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node _ppn_T_17 = bits(vpn, 19, 0) node _ppn_T_18 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_19 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_20 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_21 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_22 = mux(hitsVec_4, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_23 = mux(hitsVec_5, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_24 = mux(_ppn_T, _ppn_T_17, UInt<1>(0h0)) node _ppn_T_25 = or(_ppn_T_18, _ppn_T_19) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_20) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_21) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_22) node _ppn_T_29 = or(_ppn_T_28, _ppn_T_23) node _ppn_T_30 = or(_ppn_T_29, _ppn_T_24) wire ppn : UInt<20> connect ppn, _ppn_T_30 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<3>, clock, reset, UInt<3>(0h0) wire _state_vec_WIRE : UInt<3>[4] connect _state_vec_WIRE[0], UInt<3>(0h0) connect _state_vec_WIRE[1], UInt<3>(0h0) connect _state_vec_WIRE[2], UInt<3>(0h0) connect _state_vec_WIRE[3], UInt<3>(0h0) regreset state_vec : UInt<3>[4], clock, reset, _state_vec_WIRE reg state_reg_1 : UInt<0>, clock node _T_12 = and(io.req.valid, vm_enabled) when _T_12 : node _T_13 = or(sector_hits_0, sector_hits_1) node _T_14 = or(_T_13, sector_hits_2) node _T_15 = or(_T_14, sector_hits_3) when _T_15 : node lo = cat(sector_hits_1, sector_hits_0) node hi = cat(sector_hits_3, sector_hits_2) node _T_16 = cat(hi, lo) node hi_1 = bits(_T_16, 3, 2) node lo_1 = bits(_T_16, 1, 0) node _T_17 = orr(hi_1) node _T_18 = or(hi_1, lo_1) node _T_19 = bits(_T_18, 1, 1) node _T_20 = cat(_T_17, _T_19) node state_vec_touch_way_sized = bits(_T_20, 1, 0) node _state_vec_set_left_older_T = bits(state_vec_touch_way_sized, 1, 1) node state_vec_set_left_older = eq(_state_vec_set_left_older_T, UInt<1>(0h0)) node state_vec_left_subtree_state = bits(state_vec[memIdx], 1, 1) node state_vec_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _state_vec_T = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_1 = bits(_state_vec_T, 0, 0) node _state_vec_T_2 = eq(_state_vec_T_1, UInt<1>(0h0)) node _state_vec_T_3 = mux(state_vec_set_left_older, state_vec_left_subtree_state, _state_vec_T_2) node _state_vec_T_4 = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_5 = bits(_state_vec_T_4, 0, 0) node _state_vec_T_6 = eq(_state_vec_T_5, UInt<1>(0h0)) node _state_vec_T_7 = mux(state_vec_set_left_older, _state_vec_T_6, state_vec_right_subtree_state) node state_vec_hi = cat(state_vec_set_left_older, _state_vec_T_3) node _state_vec_T_8 = cat(state_vec_hi, _state_vec_T_7) connect state_vec[memIdx], _state_vec_T_8 when superpage_hits_0 : connect state_reg_1, UInt<1>(0h0) node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_21 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_22 = and(_T_21, io.ptw.req.bits.valid) when _T_22 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_23 = and(io.req.ready, io.req.valid) node _T_24 = and(_T_23, tlb_miss) when _T_24 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node _r_superpage_repl_addr_T = andr(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_1 = not(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_2 = bits(_r_superpage_repl_addr_T_1, 0, 0) node _r_superpage_repl_addr_T_3 = mux(_r_superpage_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_3 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[memIdx], 2, 2) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[memIdx], 1, 1) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_valids_lo = cat(sectored_entries[memIdx][1].valid[0], sectored_entries[memIdx][0].valid[0]) node r_sectored_repl_addr_valids_hi = cat(sectored_entries[memIdx][3].valid[0], sectored_entries[memIdx][2].valid[0]) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_4 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_5 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_6 = bits(_r_sectored_repl_addr_T_5, 0, 0) node _r_sectored_repl_addr_T_7 = bits(_r_sectored_repl_addr_T_5, 1, 1) node _r_sectored_repl_addr_T_8 = bits(_r_sectored_repl_addr_T_5, 2, 2) node _r_sectored_repl_addr_T_9 = bits(_r_sectored_repl_addr_T_5, 3, 3) node _r_sectored_repl_addr_T_10 = mux(_r_sectored_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_sectored_repl_addr_T_11 = mux(_r_sectored_repl_addr_T_7, UInt<1>(0h1), _r_sectored_repl_addr_T_10) node _r_sectored_repl_addr_T_12 = mux(_r_sectored_repl_addr_T_6, UInt<1>(0h0), _r_sectored_repl_addr_T_11) node _r_sectored_repl_addr_T_13 = mux(_r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_12) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_13 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_2 node r_sectored_hit_bits_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_hi = cat(sector_hits_3, sector_hits_2) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 3, 2) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 1, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node _r_sectored_hit_bits_T_3 = bits(_r_sectored_hit_bits_T_2, 1, 1) node _r_sectored_hit_bits_T_4 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_4 connect r_superpage_hit.valid, superpage_hits_0 connect r_superpage_hit.bits, UInt<1>(0h0) node _T_25 = eq(state, UInt<2>(0h1)) when _T_25 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_26 = eq(state, UInt<2>(0h2)) node _T_27 = and(_T_26, io.sfence.valid) when _T_27 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_28 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_29 = shr(io.sfence.bits.addr, 12) node _T_30 = eq(_T_29, vpn) node _T_31 = or(_T_28, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_35 = eq(hg, UInt<1>(0h0)) node _T_36 = and(_T_35, io.sfence.bits.rs1) when _T_36 : node _T_37 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_38 = shr(_T_37, 0) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = eq(sectored_entries[0][0].tag_v, hv) node _T_41 = and(_T_39, _T_40) when _T_41 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_42 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_42 node _T_43 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_43 node _T_44 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_44 node _T_45 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_45 node _T_46 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_46 node _T_47 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_47 node _T_48 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_48 node _T_49 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_49 node _T_50 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_50 node _T_51 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_51 node _T_52 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_52 node _T_53 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_53 node _T_54 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_54 node _T_55 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_55 node _T_56 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_56 node _T_57 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_57 node _T_58 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_58 node _T_59 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_59 node _T_60 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_60 node _T_61 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_61 node _T_62 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_62 node _T_63 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_63 node _T_64 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_64 node _T_65 = eq(sectored_entries[0][0].tag_v, hv) node _T_66 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_68 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_69 = shr(_T_68, 18) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[0] node _T_71 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_71 node _T_72 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_72 node _T_73 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_73 node _T_74 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_74 node _T_75 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_75 node _T_76 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_76 node _T_77 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_77 node _T_78 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_78 node _T_79 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_79 node _T_80 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_80 node _T_81 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_81 node _T_82 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_82 node _T_83 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_83 node _T_84 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_84 node _T_85 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_85 node _T_86 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_86 node _T_87 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_87 node _T_88 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_88 node _T_89 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_89 node _T_90 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_90 node _T_91 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_91 node _T_92 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_92 node _T_93 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_93 node _T_94 = eq(sectored_entries[0][0].tag_v, hv) node _T_95 = and(_T_94, _WIRE_2.fragmented_superpage) when _T_95 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_96 = eq(hg, UInt<1>(0h0)) node _T_97 = and(_T_96, io.sfence.bits.rs2) when _T_97 : wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[0] node _T_98 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_98 node _T_99 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_99 node _T_100 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_100 node _T_101 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_101 node _T_102 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_102 node _T_103 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_103 node _T_104 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_104 node _T_105 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_105 node _T_106 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_106 node _T_107 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_107 node _T_108 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_108 node _T_109 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_109 node _T_110 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_110 node _T_111 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_111 node _T_112 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_112 node _T_113 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_113 node _T_114 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_114 node _T_115 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_115 node _T_116 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_116 node _T_117 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_117 node _T_118 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_118 node _T_119 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_119 node _T_120 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_120 node _T_121 = eq(sectored_entries[0][0].tag_v, hv) node _T_122 = eq(_WIRE_4.g, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) when _T_123 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_124 = or(hv, hg) wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[0] node _T_125 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_125 node _T_126 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_126 node _T_127 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_127 node _T_128 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_128 node _T_129 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_129 node _T_130 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_130 node _T_131 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_131 node _T_132 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_132 node _T_133 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_133 node _T_134 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_134 node _T_135 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_135 node _T_136 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_136 node _T_137 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_137 node _T_138 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_138 node _T_139 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_139 node _T_140 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_140 node _T_141 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_141 node _T_142 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_142 node _T_143 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_143 node _T_144 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_144 node _T_145 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_145 node _T_146 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_146 node _T_147 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_147 node _T_148 = eq(sectored_entries[0][0].tag_v, _T_124) when _T_148 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_149 = eq(hg_1, UInt<1>(0h0)) node _T_150 = and(_T_149, io.sfence.bits.rs1) when _T_150 : node _T_151 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_152 = shr(_T_151, 0) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_155 = and(_T_153, _T_154) when _T_155 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][1].data[0] node _T_156 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_156 node _T_157 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_157 node _T_158 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_158 node _T_159 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_159 node _T_160 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_160 node _T_161 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_161 node _T_162 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_162 node _T_163 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_163 node _T_164 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_164 node _T_165 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_165 node _T_166 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_166 node _T_167 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_167 node _T_168 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_168 node _T_169 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_169 node _T_170 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_170 node _T_171 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_171 node _T_172 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_172 node _T_173 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_173 node _T_174 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_174 node _T_175 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_175 node _T_176 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_176 node _T_177 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_177 node _T_178 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_178 node _T_179 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = and(_T_179, _T_180) when _T_181 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_182 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_183 = shr(_T_182, 18) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][1].data[0] node _T_185 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_185 node _T_186 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_186 node _T_187 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_187 node _T_188 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_188 node _T_189 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_189 node _T_190 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_190 node _T_191 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_191 node _T_192 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_192 node _T_193 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_193 node _T_194 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_194 node _T_195 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_195 node _T_196 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_196 node _T_197 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_197 node _T_198 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_198 node _T_199 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_199 node _T_200 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_200 node _T_201 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_201 node _T_202 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_202 node _T_203 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_203 node _T_204 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_204 node _T_205 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_205 node _T_206 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_206 node _T_207 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_207 node _T_208 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_209 = and(_T_208, _WIRE_10.fragmented_superpage) when _T_209 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_210 = eq(hg_1, UInt<1>(0h0)) node _T_211 = and(_T_210, io.sfence.bits.rs2) when _T_211 : wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][1].data[0] node _T_212 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_212 node _T_213 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_213 node _T_214 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_214 node _T_215 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_215 node _T_216 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_216 node _T_217 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_217 node _T_218 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_218 node _T_219 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_219 node _T_220 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_220 node _T_221 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_221 node _T_222 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_222 node _T_223 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_223 node _T_224 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_224 node _T_225 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_225 node _T_226 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_226 node _T_227 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_227 node _T_228 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_228 node _T_229 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_229 node _T_230 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_230 node _T_231 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_231 node _T_232 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_232 node _T_233 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_233 node _T_234 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_234 node _T_235 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_236 = eq(_WIRE_12.g, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) when _T_237 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_238 = or(hv_1, hg_1) wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][1].data[0] node _T_239 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_239 node _T_240 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_240 node _T_241 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_241 node _T_242 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_242 node _T_243 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_243 node _T_244 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_244 node _T_245 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_245 node _T_246 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_246 node _T_247 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_247 node _T_248 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_248 node _T_249 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_249 node _T_250 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_250 node _T_251 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_251 node _T_252 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_252 node _T_253 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_253 node _T_254 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_254 node _T_255 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_255 node _T_256 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_256 node _T_257 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_257 node _T_258 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_258 node _T_259 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_259 node _T_260 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_260 node _T_261 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_261 node _T_262 = eq(sectored_entries[0][1].tag_v, _T_238) when _T_262 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_263 = eq(hg_2, UInt<1>(0h0)) node _T_264 = and(_T_263, io.sfence.bits.rs1) when _T_264 : node _T_265 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_266 = shr(_T_265, 0) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_269 = and(_T_267, _T_268) when _T_269 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][2].data[0] node _T_270 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_270 node _T_271 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_271 node _T_272 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_272 node _T_273 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_273 node _T_274 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_274 node _T_275 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_275 node _T_276 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_276 node _T_277 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_277 node _T_278 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_278 node _T_279 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_279 node _T_280 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_280 node _T_281 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_281 node _T_282 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_282 node _T_283 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_283 node _T_284 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_284 node _T_285 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_285 node _T_286 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_286 node _T_287 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_287 node _T_288 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_288 node _T_289 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_289 node _T_290 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_290 node _T_291 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_291 node _T_292 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_292 node _T_293 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_294 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) when _T_295 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_296 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_297 = shr(_T_296, 18) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][2].data[0] node _T_299 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_299 node _T_300 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_300 node _T_301 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_301 node _T_302 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_302 node _T_303 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_303 node _T_304 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_304 node _T_305 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_305 node _T_306 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_306 node _T_307 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_307 node _T_308 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_308 node _T_309 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_309 node _T_310 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_310 node _T_311 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_311 node _T_312 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_312 node _T_313 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_313 node _T_314 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_314 node _T_315 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_315 node _T_316 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_316 node _T_317 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_317 node _T_318 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_318 node _T_319 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_319 node _T_320 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_320 node _T_321 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_321 node _T_322 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_323 = and(_T_322, _WIRE_18.fragmented_superpage) when _T_323 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_324 = eq(hg_2, UInt<1>(0h0)) node _T_325 = and(_T_324, io.sfence.bits.rs2) when _T_325 : wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][2].data[0] node _T_326 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_326 node _T_327 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_327 node _T_328 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_328 node _T_329 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_329 node _T_330 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_330 node _T_331 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_331 node _T_332 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_332 node _T_333 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_333 node _T_334 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_334 node _T_335 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_335 node _T_336 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_336 node _T_337 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_337 node _T_338 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_338 node _T_339 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_339 node _T_340 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_340 node _T_341 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_341 node _T_342 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_342 node _T_343 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_343 node _T_344 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_344 node _T_345 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_345 node _T_346 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_346 node _T_347 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_347 node _T_348 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_348 node _T_349 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_350 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) when _T_351 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_352 = or(hv_2, hg_2) wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][2].data[0] node _T_353 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_353 node _T_354 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_354 node _T_355 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_355 node _T_356 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_356 node _T_357 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_357 node _T_358 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_358 node _T_359 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_359 node _T_360 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_360 node _T_361 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_361 node _T_362 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_362 node _T_363 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_363 node _T_364 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_364 node _T_365 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_365 node _T_366 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_366 node _T_367 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_367 node _T_368 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_368 node _T_369 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_369 node _T_370 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_370 node _T_371 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_371 node _T_372 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_372 node _T_373 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_373 node _T_374 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_374 node _T_375 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_375 node _T_376 = eq(sectored_entries[0][2].tag_v, _T_352) when _T_376 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_377 = eq(hg_3, UInt<1>(0h0)) node _T_378 = and(_T_377, io.sfence.bits.rs1) when _T_378 : node _T_379 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_380 = shr(_T_379, 0) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_383 = and(_T_381, _T_382) when _T_383 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][3].data[0] node _T_384 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_384 node _T_385 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_385 node _T_386 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_386 node _T_387 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_387 node _T_388 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_388 node _T_389 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_389 node _T_390 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_390 node _T_391 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_391 node _T_392 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_392 node _T_393 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_393 node _T_394 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_394 node _T_395 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_395 node _T_396 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_396 node _T_397 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_397 node _T_398 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_398 node _T_399 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_399 node _T_400 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_400 node _T_401 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_401 node _T_402 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_402 node _T_403 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_403 node _T_404 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_404 node _T_405 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_405 node _T_406 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_406 node _T_407 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_408 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = and(_T_407, _T_408) when _T_409 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_410 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_411 = shr(_T_410, 18) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][3].data[0] node _T_413 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_413 node _T_414 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_414 node _T_415 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_415 node _T_416 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_416 node _T_417 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_417 node _T_418 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_418 node _T_419 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_419 node _T_420 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_420 node _T_421 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_421 node _T_422 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_422 node _T_423 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_423 node _T_424 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_424 node _T_425 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_425 node _T_426 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_426 node _T_427 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_427 node _T_428 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_428 node _T_429 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_429 node _T_430 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_430 node _T_431 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_431 node _T_432 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_432 node _T_433 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_433 node _T_434 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_434 node _T_435 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_435 node _T_436 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_437 = and(_T_436, _WIRE_26.fragmented_superpage) when _T_437 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_438 = eq(hg_3, UInt<1>(0h0)) node _T_439 = and(_T_438, io.sfence.bits.rs2) when _T_439 : wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][3].data[0] node _T_440 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_440 node _T_441 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_441 node _T_442 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_442 node _T_443 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_443 node _T_444 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_444 node _T_445 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_445 node _T_446 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_446 node _T_447 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_447 node _T_448 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_448 node _T_449 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_449 node _T_450 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_450 node _T_451 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_451 node _T_452 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_452 node _T_453 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_453 node _T_454 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_454 node _T_455 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_455 node _T_456 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_456 node _T_457 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_457 node _T_458 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_458 node _T_459 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_459 node _T_460 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_460 node _T_461 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_461 node _T_462 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_462 node _T_463 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_464 = eq(_WIRE_28.g, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) when _T_465 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_466 = or(hv_3, hg_3) wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][3].data[0] node _T_467 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_467 node _T_468 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_468 node _T_469 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_469 node _T_470 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_470 node _T_471 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_471 node _T_472 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_472 node _T_473 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_473 node _T_474 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_474 node _T_475 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_475 node _T_476 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_476 node _T_477 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_477 node _T_478 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_478 node _T_479 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_479 node _T_480 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_480 node _T_481 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_481 node _T_482 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_482 node _T_483 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_483 node _T_484 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_484 node _T_485 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_485 node _T_486 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_486 node _T_487 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_487 node _T_488 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_488 node _T_489 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_489 node _T_490 = eq(sectored_entries[0][3].tag_v, _T_466) when _T_490 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_491 = eq(hg_4, UInt<1>(0h0)) node _T_492 = and(_T_491, io.sfence.bits.rs1) when _T_492 : node _T_493 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_494 = shr(_T_493, 0) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_497 = and(_T_495, _T_496) when _T_497 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[1][0].data[0] node _T_498 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_498 node _T_499 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_499 node _T_500 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_500 node _T_501 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_501 node _T_502 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_502 node _T_503 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_503 node _T_504 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_504 node _T_505 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_505 node _T_506 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_506 node _T_507 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_507 node _T_508 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_508 node _T_509 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_509 node _T_510 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_510 node _T_511 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_511 node _T_512 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_512 node _T_513 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_513 node _T_514 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_514 node _T_515 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_515 node _T_516 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_516 node _T_517 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_517 node _T_518 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_518 node _T_519 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_519 node _T_520 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_520 node _T_521 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) when _T_523 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node _T_524 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_525 = shr(_T_524, 18) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[1][0].data[0] node _T_527 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_528 node _T_529 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_529 node _T_530 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_530 node _T_531 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_531 node _T_532 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_532 node _T_533 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_533 node _T_534 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_534 node _T_535 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_535 node _T_536 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_536 node _T_537 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_537 node _T_538 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_538 node _T_539 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_539 node _T_540 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_540 node _T_541 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_541 node _T_542 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_542 node _T_543 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_543 node _T_544 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_544 node _T_545 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_545 node _T_546 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_546 node _T_547 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_547 node _T_548 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_548 node _T_549 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_549 node _T_550 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_551 = and(_T_550, _WIRE_34.fragmented_superpage) when _T_551 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_552 = eq(hg_4, UInt<1>(0h0)) node _T_553 = and(_T_552, io.sfence.bits.rs2) when _T_553 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[1][0].data[0] node _T_554 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_554 node _T_555 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_555 node _T_556 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_556 node _T_557 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_557 node _T_558 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_558 node _T_559 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_559 node _T_560 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_560 node _T_561 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_561 node _T_562 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_562 node _T_563 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_563 node _T_564 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_564 node _T_565 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_565 node _T_566 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_566 node _T_567 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_567 node _T_568 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_568 node _T_569 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_569 node _T_570 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_570 node _T_571 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_571 node _T_572 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_572 node _T_573 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_573 node _T_574 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_574 node _T_575 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_575 node _T_576 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_576 node _T_577 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_578 = eq(_WIRE_36.g, UInt<1>(0h0)) node _T_579 = and(_T_577, _T_578) when _T_579 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_580 = or(hv_4, hg_4) wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[1][0].data[0] node _T_581 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_581 node _T_582 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_582 node _T_583 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_583 node _T_584 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_584 node _T_585 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_585 node _T_586 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_586 node _T_587 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_587 node _T_588 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_588 node _T_589 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_589 node _T_590 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_590 node _T_591 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_591 node _T_592 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_592 node _T_593 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_593 node _T_594 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_594 node _T_595 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_595 node _T_596 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_596 node _T_597 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_597 node _T_598 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_598 node _T_599 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_599 node _T_600 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_600 node _T_601 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_601 node _T_602 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_602 node _T_603 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_603 node _T_604 = eq(sectored_entries[1][0].tag_v, _T_580) when _T_604 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_605 = eq(hg_5, UInt<1>(0h0)) node _T_606 = and(_T_605, io.sfence.bits.rs1) when _T_606 : node _T_607 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_608 = shr(_T_607, 0) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_611 = and(_T_609, _T_610) when _T_611 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[1][1].data[0] node _T_612 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_612 node _T_613 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_613 node _T_614 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_614 node _T_615 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_615 node _T_616 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_616 node _T_617 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_617 node _T_618 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_618 node _T_619 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_619 node _T_620 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_620 node _T_621 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_621 node _T_622 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_622 node _T_623 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_623 node _T_624 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_624 node _T_625 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_625 node _T_626 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_626 node _T_627 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_627 node _T_628 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_628 node _T_629 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_629 node _T_630 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_630 node _T_631 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_631 node _T_632 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_632 node _T_633 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_633 node _T_634 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_634 node _T_635 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_636 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = and(_T_635, _T_636) when _T_637 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node _T_638 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_639 = shr(_T_638, 18) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[1][1].data[0] node _T_641 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_641 node _T_642 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_642 node _T_643 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_643 node _T_644 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_644 node _T_645 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_645 node _T_646 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_646 node _T_647 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_647 node _T_648 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_648 node _T_649 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_649 node _T_650 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_650 node _T_651 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_651 node _T_652 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_652 node _T_653 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_653 node _T_654 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_654 node _T_655 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_655 node _T_656 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_656 node _T_657 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_657 node _T_658 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_658 node _T_659 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_659 node _T_660 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_660 node _T_661 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_661 node _T_662 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_662 node _T_663 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_663 node _T_664 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_665 = and(_T_664, _WIRE_42.fragmented_superpage) when _T_665 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_666 = eq(hg_5, UInt<1>(0h0)) node _T_667 = and(_T_666, io.sfence.bits.rs2) when _T_667 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[1][1].data[0] node _T_668 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_668 node _T_669 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_669 node _T_670 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_670 node _T_671 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_671 node _T_672 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_672 node _T_673 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_673 node _T_674 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_674 node _T_675 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_675 node _T_676 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_676 node _T_677 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_677 node _T_678 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_678 node _T_679 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_679 node _T_680 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_680 node _T_681 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_681 node _T_682 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_682 node _T_683 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_683 node _T_684 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_684 node _T_685 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_685 node _T_686 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_686 node _T_687 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_687 node _T_688 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_688 node _T_689 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_689 node _T_690 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_690 node _T_691 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_692 = eq(_WIRE_44.g, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) when _T_693 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_694 = or(hv_5, hg_5) wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[1][1].data[0] node _T_695 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_695 node _T_696 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_696 node _T_697 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_697 node _T_698 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_698 node _T_699 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_699 node _T_700 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_700 node _T_701 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_701 node _T_702 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_702 node _T_703 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_703 node _T_704 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_704 node _T_705 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_705 node _T_706 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_706 node _T_707 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_707 node _T_708 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_708 node _T_709 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_709 node _T_710 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_710 node _T_711 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_711 node _T_712 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_712 node _T_713 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_713 node _T_714 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_714 node _T_715 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_715 node _T_716 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_716 node _T_717 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_717 node _T_718 = eq(sectored_entries[1][1].tag_v, _T_694) when _T_718 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_719 = eq(hg_6, UInt<1>(0h0)) node _T_720 = and(_T_719, io.sfence.bits.rs1) when _T_720 : node _T_721 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_722 = shr(_T_721, 0) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_725 = and(_T_723, _T_724) when _T_725 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[1][2].data[0] node _T_726 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_726 node _T_727 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_727 node _T_728 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_728 node _T_729 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_729 node _T_730 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_730 node _T_731 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_731 node _T_732 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_732 node _T_733 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_733 node _T_734 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_734 node _T_735 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_735 node _T_736 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_736 node _T_737 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_737 node _T_738 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_738 node _T_739 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_739 node _T_740 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_740 node _T_741 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_741 node _T_742 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_742 node _T_743 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_743 node _T_744 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_744 node _T_745 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_745 node _T_746 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_746 node _T_747 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_747 node _T_748 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_748 node _T_749 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_750 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = and(_T_749, _T_750) when _T_751 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node _T_752 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_753 = shr(_T_752, 18) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[1][2].data[0] node _T_755 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_755 node _T_756 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_756 node _T_757 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_757 node _T_758 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_758 node _T_759 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_759 node _T_760 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_760 node _T_761 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_761 node _T_762 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_762 node _T_763 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_763 node _T_764 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_764 node _T_765 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_765 node _T_766 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_766 node _T_767 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_767 node _T_768 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_768 node _T_769 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_769 node _T_770 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_770 node _T_771 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_771 node _T_772 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_772 node _T_773 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_773 node _T_774 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_774 node _T_775 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_775 node _T_776 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_776 node _T_777 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_777 node _T_778 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_779 = and(_T_778, _WIRE_50.fragmented_superpage) when _T_779 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_780 = eq(hg_6, UInt<1>(0h0)) node _T_781 = and(_T_780, io.sfence.bits.rs2) when _T_781 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[1][2].data[0] node _T_782 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_782 node _T_783 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_783 node _T_784 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_784 node _T_785 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_785 node _T_786 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_786 node _T_787 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_787 node _T_788 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_788 node _T_789 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_789 node _T_790 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_790 node _T_791 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_791 node _T_792 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_792 node _T_793 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_793 node _T_794 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_794 node _T_795 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_795 node _T_796 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_796 node _T_797 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_797 node _T_798 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_798 node _T_799 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_799 node _T_800 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_800 node _T_801 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_801 node _T_802 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_802 node _T_803 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_803 node _T_804 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_804 node _T_805 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_806 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_807 = and(_T_805, _T_806) when _T_807 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_808 = or(hv_6, hg_6) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[1][2].data[0] node _T_809 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_809 node _T_810 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_810 node _T_811 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_811 node _T_812 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_812 node _T_813 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_813 node _T_814 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_814 node _T_815 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_815 node _T_816 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_816 node _T_817 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_817 node _T_818 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_818 node _T_819 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_819 node _T_820 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_820 node _T_821 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_821 node _T_822 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_822 node _T_823 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_823 node _T_824 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_824 node _T_825 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_825 node _T_826 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_826 node _T_827 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_827 node _T_828 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_828 node _T_829 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_829 node _T_830 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_830 node _T_831 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_831 node _T_832 = eq(sectored_entries[1][2].tag_v, _T_808) when _T_832 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_833 = eq(hg_7, UInt<1>(0h0)) node _T_834 = and(_T_833, io.sfence.bits.rs1) when _T_834 : node _T_835 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_836 = shr(_T_835, 0) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_839 = and(_T_837, _T_838) when _T_839 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[1][3].data[0] node _T_840 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_840 node _T_841 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_841 node _T_842 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_842 node _T_843 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_843 node _T_844 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_844 node _T_845 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_845 node _T_846 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_846 node _T_847 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_847 node _T_848 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_848 node _T_849 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_849 node _T_850 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_850 node _T_851 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_851 node _T_852 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_852 node _T_853 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_853 node _T_854 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_854 node _T_855 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_855 node _T_856 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_856 node _T_857 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_857 node _T_858 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_858 node _T_859 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_859 node _T_860 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_860 node _T_861 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_861 node _T_862 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_862 node _T_863 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_864 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_865 = and(_T_863, _T_864) when _T_865 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node _T_866 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_867 = shr(_T_866, 18) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[1][3].data[0] node _T_869 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_869 node _T_870 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_870 node _T_871 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_871 node _T_872 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_872 node _T_873 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_873 node _T_874 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_874 node _T_875 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_875 node _T_876 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_876 node _T_877 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_877 node _T_878 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_878 node _T_879 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_879 node _T_880 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_880 node _T_881 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_881 node _T_882 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_882 node _T_883 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_883 node _T_884 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_884 node _T_885 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_885 node _T_886 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_886 node _T_887 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_887 node _T_888 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_888 node _T_889 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_889 node _T_890 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_890 node _T_891 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_891 node _T_892 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_893 = and(_T_892, _WIRE_58.fragmented_superpage) when _T_893 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_894 = eq(hg_7, UInt<1>(0h0)) node _T_895 = and(_T_894, io.sfence.bits.rs2) when _T_895 : wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[1][3].data[0] node _T_896 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_896 node _T_897 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_897 node _T_898 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_898 node _T_899 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_899 node _T_900 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_900 node _T_901 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_901 node _T_902 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_902 node _T_903 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_903 node _T_904 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_904 node _T_905 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_905 node _T_906 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_906 node _T_907 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_907 node _T_908 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_908 node _T_909 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_909 node _T_910 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_910 node _T_911 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_911 node _T_912 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_912 node _T_913 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_913 node _T_914 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_914 node _T_915 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_915 node _T_916 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_916 node _T_917 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_917 node _T_918 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_918 node _T_919 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_920 = eq(_WIRE_60.g, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_922 = or(hv_7, hg_7) wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[1][3].data[0] node _T_923 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_923 node _T_924 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_924 node _T_925 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_925 node _T_926 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_926 node _T_927 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_927 node _T_928 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_928 node _T_929 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_929 node _T_930 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_930 node _T_931 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_931 node _T_932 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_932 node _T_933 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_933 node _T_934 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_934 node _T_935 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_935 node _T_936 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_936 node _T_937 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_937 node _T_938 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_938 node _T_939 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_939 node _T_940 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_940 node _T_941 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_941 node _T_942 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_942 node _T_943 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_943 node _T_944 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_944 node _T_945 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_945 node _T_946 = eq(sectored_entries[1][3].tag_v, _T_922) when _T_946 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_947 = eq(hg_8, UInt<1>(0h0)) node _T_948 = and(_T_947, io.sfence.bits.rs1) when _T_948 : node _T_949 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_950 = shr(_T_949, 0) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_953 = and(_T_951, _T_952) when _T_953 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[2][0].data[0] node _T_954 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_954 node _T_955 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_955 node _T_956 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_956 node _T_957 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_957 node _T_958 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_958 node _T_959 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_959 node _T_960 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_960 node _T_961 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_961 node _T_962 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_962 node _T_963 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_963 node _T_964 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_964 node _T_965 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_965 node _T_966 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_966 node _T_967 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_967 node _T_968 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_968 node _T_969 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_969 node _T_970 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_970 node _T_971 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_971 node _T_972 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_972 node _T_973 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_973 node _T_974 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_974 node _T_975 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_975 node _T_976 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_976 node _T_977 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_978 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = and(_T_977, _T_978) when _T_979 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node _T_980 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_981 = shr(_T_980, 18) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[2][0].data[0] node _T_983 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_983 node _T_984 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_984 node _T_985 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_985 node _T_986 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_986 node _T_987 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_987 node _T_988 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_988 node _T_989 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_989 node _T_990 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_990 node _T_991 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_991 node _T_992 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_992 node _T_993 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_993 node _T_994 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_994 node _T_995 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_995 node _T_996 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_996 node _T_997 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_997 node _T_998 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_998 node _T_999 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_999 node _T_1000 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1000 node _T_1001 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1001 node _T_1002 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1002 node _T_1003 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1003 node _T_1004 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1004 node _T_1005 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1005 node _T_1006 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1007 = and(_T_1006, _WIRE_66.fragmented_superpage) when _T_1007 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1008 = eq(hg_8, UInt<1>(0h0)) node _T_1009 = and(_T_1008, io.sfence.bits.rs2) when _T_1009 : wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[2][0].data[0] node _T_1010 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1010 node _T_1011 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1011 node _T_1012 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1012 node _T_1013 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1013 node _T_1014 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1014 node _T_1015 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1015 node _T_1016 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1016 node _T_1017 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1017 node _T_1018 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1018 node _T_1019 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1019 node _T_1020 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1020 node _T_1021 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1021 node _T_1022 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1022 node _T_1023 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1023 node _T_1024 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1024 node _T_1025 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1025 node _T_1026 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1026 node _T_1027 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1027 node _T_1028 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1028 node _T_1029 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1029 node _T_1030 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1030 node _T_1031 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1031 node _T_1032 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1032 node _T_1033 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1034 = eq(_WIRE_68.g, UInt<1>(0h0)) node _T_1035 = and(_T_1033, _T_1034) when _T_1035 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1036 = or(hv_8, hg_8) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[2][0].data[0] node _T_1037 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1037 node _T_1038 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1038 node _T_1039 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1039 node _T_1040 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1040 node _T_1041 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1041 node _T_1042 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1042 node _T_1043 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1043 node _T_1044 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1044 node _T_1045 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1045 node _T_1046 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1046 node _T_1047 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1047 node _T_1048 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1048 node _T_1049 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1049 node _T_1050 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1050 node _T_1051 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1051 node _T_1052 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1052 node _T_1053 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1053 node _T_1054 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1054 node _T_1055 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1055 node _T_1056 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1056 node _T_1057 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1057 node _T_1058 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1058 node _T_1059 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1059 node _T_1060 = eq(sectored_entries[2][0].tag_v, _T_1036) when _T_1060 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1061 = eq(hg_9, UInt<1>(0h0)) node _T_1062 = and(_T_1061, io.sfence.bits.rs1) when _T_1062 : node _T_1063 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1064 = shr(_T_1063, 0) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[2][1].data[0] node _T_1068 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1068 node _T_1069 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1069 node _T_1070 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1070 node _T_1071 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1071 node _T_1072 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1072 node _T_1073 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1073 node _T_1074 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1074 node _T_1075 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1075 node _T_1076 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1076 node _T_1077 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1077 node _T_1078 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1078 node _T_1079 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1079 node _T_1080 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1080 node _T_1081 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1081 node _T_1082 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1082 node _T_1083 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1083 node _T_1084 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1084 node _T_1085 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1085 node _T_1086 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1086 node _T_1087 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1087 node _T_1088 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1088 node _T_1089 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1089 node _T_1090 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1090 node _T_1091 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1092 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = and(_T_1091, _T_1092) when _T_1093 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node _T_1094 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1095 = shr(_T_1094, 18) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[2][1].data[0] node _T_1097 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1097 node _T_1098 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1098 node _T_1099 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1099 node _T_1100 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1100 node _T_1101 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1101 node _T_1102 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1102 node _T_1103 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1103 node _T_1104 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1104 node _T_1105 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1105 node _T_1106 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1106 node _T_1107 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1107 node _T_1108 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1108 node _T_1109 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1109 node _T_1110 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1110 node _T_1111 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1111 node _T_1112 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1112 node _T_1113 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1113 node _T_1114 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1114 node _T_1115 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1115 node _T_1116 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1116 node _T_1117 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1117 node _T_1118 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1118 node _T_1119 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1119 node _T_1120 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1121 = and(_T_1120, _WIRE_74.fragmented_superpage) when _T_1121 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1122 = eq(hg_9, UInt<1>(0h0)) node _T_1123 = and(_T_1122, io.sfence.bits.rs2) when _T_1123 : wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[2][1].data[0] node _T_1124 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1124 node _T_1125 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1125 node _T_1126 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1126 node _T_1127 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1127 node _T_1128 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1128 node _T_1129 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1129 node _T_1130 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1130 node _T_1131 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1131 node _T_1132 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1132 node _T_1133 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1133 node _T_1134 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1134 node _T_1135 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1135 node _T_1136 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1136 node _T_1137 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1137 node _T_1138 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1138 node _T_1139 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1139 node _T_1140 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1140 node _T_1141 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1141 node _T_1142 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1142 node _T_1143 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1143 node _T_1144 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1144 node _T_1145 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1145 node _T_1146 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1146 node _T_1147 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1148 = eq(_WIRE_76.g, UInt<1>(0h0)) node _T_1149 = and(_T_1147, _T_1148) when _T_1149 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1150 = or(hv_9, hg_9) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[2][1].data[0] node _T_1151 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1151 node _T_1152 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1152 node _T_1153 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1153 node _T_1154 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1154 node _T_1155 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1155 node _T_1156 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1156 node _T_1157 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1157 node _T_1158 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1158 node _T_1159 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1159 node _T_1160 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1160 node _T_1161 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1161 node _T_1162 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1162 node _T_1163 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1163 node _T_1164 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1164 node _T_1165 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1165 node _T_1166 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1166 node _T_1167 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1167 node _T_1168 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1168 node _T_1169 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1169 node _T_1170 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1170 node _T_1171 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1171 node _T_1172 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1172 node _T_1173 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1173 node _T_1174 = eq(sectored_entries[2][1].tag_v, _T_1150) when _T_1174 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1175 = eq(hg_10, UInt<1>(0h0)) node _T_1176 = and(_T_1175, io.sfence.bits.rs1) when _T_1176 : node _T_1177 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1178 = shr(_T_1177, 0) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1181 = and(_T_1179, _T_1180) when _T_1181 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[2][2].data[0] node _T_1182 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1182 node _T_1183 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1183 node _T_1184 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1184 node _T_1185 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1185 node _T_1186 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1186 node _T_1187 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1187 node _T_1188 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1188 node _T_1189 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1189 node _T_1190 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1190 node _T_1191 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1191 node _T_1192 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1192 node _T_1193 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1193 node _T_1194 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1194 node _T_1195 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1195 node _T_1196 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1196 node _T_1197 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1197 node _T_1198 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1198 node _T_1199 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1199 node _T_1200 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1200 node _T_1201 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1201 node _T_1202 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1202 node _T_1203 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1203 node _T_1204 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1204 node _T_1205 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1206 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node _T_1208 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1209 = shr(_T_1208, 18) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[2][2].data[0] node _T_1211 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1211 node _T_1212 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1212 node _T_1213 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1213 node _T_1214 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1214 node _T_1215 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1215 node _T_1216 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1216 node _T_1217 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1217 node _T_1218 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1218 node _T_1219 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1219 node _T_1220 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1220 node _T_1221 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1221 node _T_1222 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1222 node _T_1223 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1223 node _T_1224 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1224 node _T_1225 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1225 node _T_1226 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1226 node _T_1227 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1227 node _T_1228 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1228 node _T_1229 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1229 node _T_1230 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1230 node _T_1231 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1231 node _T_1232 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1232 node _T_1233 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1233 node _T_1234 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1235 = and(_T_1234, _WIRE_82.fragmented_superpage) when _T_1235 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1236 = eq(hg_10, UInt<1>(0h0)) node _T_1237 = and(_T_1236, io.sfence.bits.rs2) when _T_1237 : wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[2][2].data[0] node _T_1238 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1238 node _T_1239 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1239 node _T_1240 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1240 node _T_1241 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1241 node _T_1242 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1242 node _T_1243 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1243 node _T_1244 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1244 node _T_1245 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1245 node _T_1246 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1246 node _T_1247 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1247 node _T_1248 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1248 node _T_1249 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1249 node _T_1250 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1250 node _T_1251 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1251 node _T_1252 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1252 node _T_1253 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1253 node _T_1254 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1254 node _T_1255 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1255 node _T_1256 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1256 node _T_1257 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1257 node _T_1258 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1258 node _T_1259 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1259 node _T_1260 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1260 node _T_1261 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1262 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1264 = or(hv_10, hg_10) wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[2][2].data[0] node _T_1265 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1265 node _T_1266 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1266 node _T_1267 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1267 node _T_1268 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1268 node _T_1269 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1269 node _T_1270 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1270 node _T_1271 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1271 node _T_1272 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1272 node _T_1273 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1273 node _T_1274 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1274 node _T_1275 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1275 node _T_1276 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1276 node _T_1277 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1277 node _T_1278 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1278 node _T_1279 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1279 node _T_1280 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1280 node _T_1281 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1281 node _T_1282 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1282 node _T_1283 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1283 node _T_1284 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1284 node _T_1285 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1285 node _T_1286 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1286 node _T_1287 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1287 node _T_1288 = eq(sectored_entries[2][2].tag_v, _T_1264) when _T_1288 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1289 = eq(hg_11, UInt<1>(0h0)) node _T_1290 = and(_T_1289, io.sfence.bits.rs1) when _T_1290 : node _T_1291 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1292 = shr(_T_1291, 0) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) node _T_1294 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1295 = and(_T_1293, _T_1294) when _T_1295 : wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[2][3].data[0] node _T_1296 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1296 node _T_1297 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1297 node _T_1298 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1298 node _T_1299 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1299 node _T_1300 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1300 node _T_1301 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1301 node _T_1302 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1302 node _T_1303 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1303 node _T_1304 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1304 node _T_1305 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1305 node _T_1306 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1306 node _T_1307 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1307 node _T_1308 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1308 node _T_1309 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1309 node _T_1310 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1310 node _T_1311 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1311 node _T_1312 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1312 node _T_1313 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1313 node _T_1314 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1314 node _T_1315 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1315 node _T_1316 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1316 node _T_1317 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1317 node _T_1318 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1318 node _T_1319 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1320 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1321 = and(_T_1319, _T_1320) when _T_1321 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node _T_1322 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1323 = shr(_T_1322, 18) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[2][3].data[0] node _T_1325 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1325 node _T_1326 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1326 node _T_1327 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1327 node _T_1328 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1328 node _T_1329 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1329 node _T_1330 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1330 node _T_1331 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1331 node _T_1332 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1332 node _T_1333 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1333 node _T_1334 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1334 node _T_1335 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1335 node _T_1336 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1336 node _T_1337 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1337 node _T_1338 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1338 node _T_1339 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1339 node _T_1340 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1340 node _T_1341 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1341 node _T_1342 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1342 node _T_1343 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1343 node _T_1344 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1344 node _T_1345 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1345 node _T_1346 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1346 node _T_1347 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1347 node _T_1348 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1349 = and(_T_1348, _WIRE_90.fragmented_superpage) when _T_1349 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1350 = eq(hg_11, UInt<1>(0h0)) node _T_1351 = and(_T_1350, io.sfence.bits.rs2) when _T_1351 : wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[2][3].data[0] node _T_1352 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1352 node _T_1353 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1353 node _T_1354 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1354 node _T_1355 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1355 node _T_1356 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1356 node _T_1357 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1357 node _T_1358 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1358 node _T_1359 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1359 node _T_1360 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1360 node _T_1361 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1361 node _T_1362 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1362 node _T_1363 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1363 node _T_1364 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1364 node _T_1365 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1365 node _T_1366 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1366 node _T_1367 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1367 node _T_1368 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1368 node _T_1369 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1369 node _T_1370 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1370 node _T_1371 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1371 node _T_1372 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1372 node _T_1373 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1373 node _T_1374 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1374 node _T_1375 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1376 = eq(_WIRE_92.g, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1378 = or(hv_11, hg_11) wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[2][3].data[0] node _T_1379 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1379 node _T_1380 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1380 node _T_1381 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1381 node _T_1382 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1382 node _T_1383 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1383 node _T_1384 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1384 node _T_1385 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1385 node _T_1386 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1386 node _T_1387 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1387 node _T_1388 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1388 node _T_1389 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1389 node _T_1390 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1390 node _T_1391 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1391 node _T_1392 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1392 node _T_1393 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1393 node _T_1394 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1394 node _T_1395 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1395 node _T_1396 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1396 node _T_1397 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1397 node _T_1398 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1398 node _T_1399 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1399 node _T_1400 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1400 node _T_1401 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1401 node _T_1402 = eq(sectored_entries[2][3].tag_v, _T_1378) when _T_1402 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1403 = eq(hg_12, UInt<1>(0h0)) node _T_1404 = and(_T_1403, io.sfence.bits.rs1) when _T_1404 : node _T_1405 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1406 = shr(_T_1405, 0) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) node _T_1408 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1409 = and(_T_1407, _T_1408) when _T_1409 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[3][0].data[0] node _T_1410 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1410 node _T_1411 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1411 node _T_1412 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1412 node _T_1413 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1413 node _T_1414 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1414 node _T_1415 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1415 node _T_1416 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1416 node _T_1417 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1417 node _T_1418 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1418 node _T_1419 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1419 node _T_1420 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1420 node _T_1421 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1421 node _T_1422 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1422 node _T_1423 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1423 node _T_1424 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1424 node _T_1425 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1425 node _T_1426 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1426 node _T_1427 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1427 node _T_1428 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1428 node _T_1429 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1429 node _T_1430 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1430 node _T_1431 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1431 node _T_1432 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1432 node _T_1433 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1435 = and(_T_1433, _T_1434) when _T_1435 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node _T_1436 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1437 = shr(_T_1436, 18) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[3][0].data[0] node _T_1439 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1439 node _T_1440 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1440 node _T_1441 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1441 node _T_1442 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1442 node _T_1443 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1443 node _T_1444 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1444 node _T_1445 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1445 node _T_1446 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1446 node _T_1447 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1447 node _T_1448 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1448 node _T_1449 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1449 node _T_1450 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1450 node _T_1451 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1451 node _T_1452 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1452 node _T_1453 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1453 node _T_1454 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1454 node _T_1455 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1455 node _T_1456 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1456 node _T_1457 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1457 node _T_1458 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1458 node _T_1459 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1459 node _T_1460 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1460 node _T_1461 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1461 node _T_1462 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1463 = and(_T_1462, _WIRE_98.fragmented_superpage) when _T_1463 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1464 = eq(hg_12, UInt<1>(0h0)) node _T_1465 = and(_T_1464, io.sfence.bits.rs2) when _T_1465 : wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[3][0].data[0] node _T_1466 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1466 node _T_1467 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1467 node _T_1468 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1468 node _T_1469 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1469 node _T_1470 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1470 node _T_1471 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1471 node _T_1472 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1472 node _T_1473 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1473 node _T_1474 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1474 node _T_1475 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1475 node _T_1476 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1476 node _T_1477 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1477 node _T_1478 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1478 node _T_1479 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1479 node _T_1480 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1480 node _T_1481 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1481 node _T_1482 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1482 node _T_1483 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1483 node _T_1484 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1484 node _T_1485 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1485 node _T_1486 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1486 node _T_1487 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1487 node _T_1488 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1488 node _T_1489 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1490 = eq(_WIRE_100.g, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1492 = or(hv_12, hg_12) wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[3][0].data[0] node _T_1493 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1493 node _T_1494 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1494 node _T_1495 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1495 node _T_1496 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1496 node _T_1497 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1497 node _T_1498 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1498 node _T_1499 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1499 node _T_1500 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1500 node _T_1501 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1501 node _T_1502 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1502 node _T_1503 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1503 node _T_1504 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1504 node _T_1505 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1505 node _T_1506 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1506 node _T_1507 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1507 node _T_1508 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1508 node _T_1509 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1509 node _T_1510 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1510 node _T_1511 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1511 node _T_1512 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1512 node _T_1513 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1513 node _T_1514 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1514 node _T_1515 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1515 node _T_1516 = eq(sectored_entries[3][0].tag_v, _T_1492) when _T_1516 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node hv_13 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_13 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1517 = eq(hg_13, UInt<1>(0h0)) node _T_1518 = and(_T_1517, io.sfence.bits.rs1) when _T_1518 : node _T_1519 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1520 = shr(_T_1519, 0) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1523 = and(_T_1521, _T_1522) when _T_1523 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[3][1].data[0] node _T_1524 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1524 node _T_1525 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1525 node _T_1526 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1526 node _T_1527 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1527 node _T_1528 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1528 node _T_1529 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1529 node _T_1530 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1530 node _T_1531 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1531 node _T_1532 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1532 node _T_1533 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1533 node _T_1534 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1534 node _T_1535 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1535 node _T_1536 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1536 node _T_1537 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1537 node _T_1538 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1538 node _T_1539 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1539 node _T_1540 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1540 node _T_1541 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1541 node _T_1542 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1542 node _T_1543 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1543 node _T_1544 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1544 node _T_1545 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1545 node _T_1546 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1546 node _T_1547 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1548 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1549 = and(_T_1547, _T_1548) when _T_1549 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node _T_1550 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1551 = shr(_T_1550, 18) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[3][1].data[0] node _T_1553 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1553 node _T_1554 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1554 node _T_1555 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1555 node _T_1556 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1556 node _T_1557 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1557 node _T_1558 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1558 node _T_1559 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1559 node _T_1560 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1560 node _T_1561 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1561 node _T_1562 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1562 node _T_1563 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1563 node _T_1564 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1564 node _T_1565 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1565 node _T_1566 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1566 node _T_1567 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1567 node _T_1568 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1568 node _T_1569 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1569 node _T_1570 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1570 node _T_1571 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1571 node _T_1572 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1572 node _T_1573 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1573 node _T_1574 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1574 node _T_1575 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1575 node _T_1576 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1577 = and(_T_1576, _WIRE_106.fragmented_superpage) when _T_1577 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1578 = eq(hg_13, UInt<1>(0h0)) node _T_1579 = and(_T_1578, io.sfence.bits.rs2) when _T_1579 : wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[3][1].data[0] node _T_1580 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1580 node _T_1581 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1581 node _T_1582 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1582 node _T_1583 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1583 node _T_1584 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1584 node _T_1585 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1585 node _T_1586 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1586 node _T_1587 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1587 node _T_1588 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1588 node _T_1589 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1589 node _T_1590 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1590 node _T_1591 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1591 node _T_1592 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1592 node _T_1593 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1593 node _T_1594 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1594 node _T_1595 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1595 node _T_1596 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1596 node _T_1597 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1597 node _T_1598 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1598 node _T_1599 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1599 node _T_1600 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1600 node _T_1601 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1601 node _T_1602 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1602 node _T_1603 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1604 = eq(_WIRE_108.g, UInt<1>(0h0)) node _T_1605 = and(_T_1603, _T_1604) when _T_1605 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1606 = or(hv_13, hg_13) wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[3][1].data[0] node _T_1607 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1607 node _T_1608 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1608 node _T_1609 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1609 node _T_1610 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1610 node _T_1611 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1611 node _T_1612 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1612 node _T_1613 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1613 node _T_1614 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1614 node _T_1615 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1615 node _T_1616 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1616 node _T_1617 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1617 node _T_1618 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1618 node _T_1619 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1619 node _T_1620 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1620 node _T_1621 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1621 node _T_1622 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1622 node _T_1623 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1623 node _T_1624 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1624 node _T_1625 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1625 node _T_1626 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1626 node _T_1627 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1627 node _T_1628 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1628 node _T_1629 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1629 node _T_1630 = eq(sectored_entries[3][1].tag_v, _T_1606) when _T_1630 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node hv_14 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_14 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1631 = eq(hg_14, UInt<1>(0h0)) node _T_1632 = and(_T_1631, io.sfence.bits.rs1) when _T_1632 : node _T_1633 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1634 = shr(_T_1633, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[3][2].data[0] node _T_1638 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1638 node _T_1639 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1639 node _T_1640 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1640 node _T_1641 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1641 node _T_1642 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1642 node _T_1643 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1643 node _T_1644 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1644 node _T_1645 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1645 node _T_1646 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1646 node _T_1647 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1647 node _T_1648 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1648 node _T_1649 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1649 node _T_1650 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1650 node _T_1651 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1651 node _T_1652 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1652 node _T_1653 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1653 node _T_1654 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1654 node _T_1655 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1655 node _T_1656 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1656 node _T_1657 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1657 node _T_1658 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1658 node _T_1659 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1659 node _T_1660 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1660 node _T_1661 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1662 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node _T_1664 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1665 = shr(_T_1664, 18) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[3][2].data[0] node _T_1667 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1667 node _T_1668 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1668 node _T_1669 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1669 node _T_1670 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1670 node _T_1671 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1671 node _T_1672 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1672 node _T_1673 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1673 node _T_1674 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1674 node _T_1675 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1675 node _T_1676 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1676 node _T_1677 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1677 node _T_1678 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1678 node _T_1679 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1679 node _T_1680 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1680 node _T_1681 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1681 node _T_1682 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1682 node _T_1683 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1683 node _T_1684 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1684 node _T_1685 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1685 node _T_1686 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1686 node _T_1687 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1687 node _T_1688 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1688 node _T_1689 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1689 node _T_1690 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1691 = and(_T_1690, _WIRE_114.fragmented_superpage) when _T_1691 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1692 = eq(hg_14, UInt<1>(0h0)) node _T_1693 = and(_T_1692, io.sfence.bits.rs2) when _T_1693 : wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[3][2].data[0] node _T_1694 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1694 node _T_1695 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1695 node _T_1696 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1696 node _T_1697 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1697 node _T_1698 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1698 node _T_1699 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1699 node _T_1700 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1700 node _T_1701 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1701 node _T_1702 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1702 node _T_1703 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1703 node _T_1704 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1704 node _T_1705 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1705 node _T_1706 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1706 node _T_1707 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1707 node _T_1708 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1708 node _T_1709 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1709 node _T_1710 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1710 node _T_1711 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1711 node _T_1712 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1712 node _T_1713 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1713 node _T_1714 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1714 node _T_1715 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1715 node _T_1716 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1716 node _T_1717 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1718 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1719 = and(_T_1717, _T_1718) when _T_1719 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1720 = or(hv_14, hg_14) wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[3][2].data[0] node _T_1721 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1721 node _T_1722 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1722 node _T_1723 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1723 node _T_1724 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1724 node _T_1725 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1725 node _T_1726 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1726 node _T_1727 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1727 node _T_1728 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1728 node _T_1729 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1729 node _T_1730 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1730 node _T_1731 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1731 node _T_1732 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1732 node _T_1733 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1733 node _T_1734 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1734 node _T_1735 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1735 node _T_1736 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1736 node _T_1737 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1737 node _T_1738 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1738 node _T_1739 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1739 node _T_1740 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1740 node _T_1741 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1741 node _T_1742 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1742 node _T_1743 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1743 node _T_1744 = eq(sectored_entries[3][2].tag_v, _T_1720) when _T_1744 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node hv_15 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_15 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_15, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 0) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[3][3].data[0] node _T_1752 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1753 node _T_1754 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1754 node _T_1755 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1755 node _T_1756 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1756 node _T_1757 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1757 node _T_1758 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1758 node _T_1759 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1759 node _T_1760 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1760 node _T_1761 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1761 node _T_1762 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1762 node _T_1763 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1763 node _T_1764 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1764 node _T_1765 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1765 node _T_1766 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1766 node _T_1767 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1767 node _T_1768 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1768 node _T_1769 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1770 node _T_1771 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1772 node _T_1773 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1773 node _T_1774 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1774 node _T_1775 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1776 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node _T_1778 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1779 = shr(_T_1778, 18) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[3][3].data[0] node _T_1781 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1781 node _T_1782 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1782 node _T_1783 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1783 node _T_1784 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1784 node _T_1785 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1785 node _T_1786 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1786 node _T_1787 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1787 node _T_1788 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1788 node _T_1789 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1789 node _T_1790 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1790 node _T_1791 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1791 node _T_1792 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1792 node _T_1793 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1793 node _T_1794 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1794 node _T_1795 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1795 node _T_1796 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1796 node _T_1797 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1797 node _T_1798 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1798 node _T_1799 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1799 node _T_1800 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1800 node _T_1801 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1801 node _T_1802 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1802 node _T_1803 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1803 node _T_1804 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1805 = and(_T_1804, _WIRE_122.fragmented_superpage) when _T_1805 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1806 = eq(hg_15, UInt<1>(0h0)) node _T_1807 = and(_T_1806, io.sfence.bits.rs2) when _T_1807 : wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[3][3].data[0] node _T_1808 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1808 node _T_1809 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1809 node _T_1810 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1810 node _T_1811 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1811 node _T_1812 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1812 node _T_1813 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1813 node _T_1814 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1814 node _T_1815 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1815 node _T_1816 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1816 node _T_1817 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1817 node _T_1818 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1818 node _T_1819 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1819 node _T_1820 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1820 node _T_1821 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1821 node _T_1822 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1822 node _T_1823 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1823 node _T_1824 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1824 node _T_1825 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1825 node _T_1826 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1826 node _T_1827 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1827 node _T_1828 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1828 node _T_1829 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1829 node _T_1830 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1830 node _T_1831 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1832 = eq(_WIRE_124.g, UInt<1>(0h0)) node _T_1833 = and(_T_1831, _T_1832) when _T_1833 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1834 = or(hv_15, hg_15) wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[3][3].data[0] node _T_1835 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1835 node _T_1836 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1836 node _T_1837 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1837 node _T_1838 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1838 node _T_1839 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1839 node _T_1840 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1840 node _T_1841 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1841 node _T_1842 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1842 node _T_1843 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1843 node _T_1844 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1844 node _T_1845 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1845 node _T_1846 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1846 node _T_1847 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1847 node _T_1848 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1848 node _T_1849 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1849 node _T_1850 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1850 node _T_1851 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1851 node _T_1852 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1852 node _T_1853 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1853 node _T_1854 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1854 node _T_1855 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1855 node _T_1856 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1856 node _T_1857 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1857 node _T_1858 = eq(sectored_entries[3][3].tag_v, _T_1834) when _T_1858 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node hv_16 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_16 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1859 = eq(hg_16, UInt<1>(0h0)) node _T_1860 = and(_T_1859, io.sfence.bits.rs1) when _T_1860 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_16) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_1861 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1862 = bits(_T_1861, 26, 18) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(ignore, _T_1863) node _T_1865 = and(tagMatch, _T_1864) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_1866 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1867 = bits(_T_1866, 17, 9) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) node _T_1869 = or(ignore_1, _T_1868) node _T_1870 = and(_T_1865, _T_1869) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_1871 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1872 = bits(_T_1871, 8, 0) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = or(ignore_2, _T_1873) node _T_1875 = and(_T_1870, _T_1874) when _T_1875 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_1876 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1877 = shr(_T_1876, 18) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, superpage_entries[0].data[0] node _T_1879 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1879 node _T_1880 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1880 node _T_1881 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1881 node _T_1882 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1882 node _T_1883 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1883 node _T_1884 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1884 node _T_1885 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1885 node _T_1886 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1886 node _T_1887 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1887 node _T_1888 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1888 node _T_1889 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1889 node _T_1890 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1890 node _T_1891 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1891 node _T_1892 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1892 node _T_1893 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1893 node _T_1894 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1894 node _T_1895 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1895 node _T_1896 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1896 node _T_1897 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1897 node _T_1898 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1898 node _T_1899 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1899 node _T_1900 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1900 node _T_1901 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1901 node _T_1902 = eq(superpage_entries[0].tag_v, hv_16) node _T_1903 = and(_T_1902, _WIRE_128.fragmented_superpage) when _T_1903 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1904 = eq(hg_16, UInt<1>(0h0)) node _T_1905 = and(_T_1904, io.sfence.bits.rs2) when _T_1905 : wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, superpage_entries[0].data[0] node _T_1906 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1906 node _T_1907 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1907 node _T_1908 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1908 node _T_1909 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1909 node _T_1910 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1910 node _T_1911 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1911 node _T_1912 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1912 node _T_1913 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1913 node _T_1914 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1914 node _T_1915 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1915 node _T_1916 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1916 node _T_1917 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1917 node _T_1918 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1918 node _T_1919 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1919 node _T_1920 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1920 node _T_1921 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1921 node _T_1922 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1922 node _T_1923 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1923 node _T_1924 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1924 node _T_1925 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1925 node _T_1926 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1926 node _T_1927 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1927 node _T_1928 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1928 node _T_1929 = eq(superpage_entries[0].tag_v, hv_16) node _T_1930 = eq(_WIRE_130.g, UInt<1>(0h0)) node _T_1931 = and(_T_1929, _T_1930) when _T_1931 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1932 = or(hv_16, hg_16) wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, superpage_entries[0].data[0] node _T_1933 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1933 node _T_1934 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1934 node _T_1935 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1935 node _T_1936 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1936 node _T_1937 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1937 node _T_1938 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1938 node _T_1939 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1939 node _T_1940 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1940 node _T_1941 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1941 node _T_1942 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1942 node _T_1943 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1943 node _T_1944 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1944 node _T_1945 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1945 node _T_1946 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1946 node _T_1947 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1947 node _T_1948 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1948 node _T_1949 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1949 node _T_1950 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1950 node _T_1951 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1951 node _T_1952 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1952 node _T_1953 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1953 node _T_1954 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1954 node _T_1955 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1955 node _T_1956 = eq(superpage_entries[0].tag_v, _T_1932) when _T_1956 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_17 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_17 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1957 = eq(hg_17, UInt<1>(0h0)) node _T_1958 = and(_T_1957, io.sfence.bits.rs1) when _T_1958 : node _tagMatch_T_1 = eq(special_entry.tag_v, hv_17) node tagMatch_1 = and(special_entry.valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_1959 = xor(special_entry.tag_vpn, vpn) node _T_1960 = bits(_T_1959, 26, 18) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) node _T_1962 = or(ignore_3, _T_1961) node _T_1963 = and(tagMatch_1, _T_1962) node _ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_1964 = xor(special_entry.tag_vpn, vpn) node _T_1965 = bits(_T_1964, 17, 9) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = or(ignore_4, _T_1966) node _T_1968 = and(_T_1963, _T_1967) node _ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h0)) node _T_1969 = xor(special_entry.tag_vpn, vpn) node _T_1970 = bits(_T_1969, 8, 0) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(ignore_5, _T_1971) node _T_1973 = and(_T_1968, _T_1972) when _T_1973 : connect special_entry.valid[0], UInt<1>(0h0) node _T_1974 = xor(special_entry.tag_vpn, vpn) node _T_1975 = shr(_T_1974, 18) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, special_entry.data[0] node _T_1977 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1977 node _T_1978 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1978 node _T_1979 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1979 node _T_1980 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1980 node _T_1981 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1981 node _T_1982 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1982 node _T_1983 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1983 node _T_1984 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1984 node _T_1985 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1985 node _T_1986 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1986 node _T_1987 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1987 node _T_1988 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1988 node _T_1989 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1989 node _T_1990 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1990 node _T_1991 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1991 node _T_1992 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1992 node _T_1993 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1993 node _T_1994 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1994 node _T_1995 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1995 node _T_1996 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1996 node _T_1997 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1997 node _T_1998 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1998 node _T_1999 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1999 node _T_2000 = eq(special_entry.tag_v, hv_17) node _T_2001 = and(_T_2000, _WIRE_134.fragmented_superpage) when _T_2001 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2002 = eq(hg_17, UInt<1>(0h0)) node _T_2003 = and(_T_2002, io.sfence.bits.rs2) when _T_2003 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, special_entry.data[0] node _T_2004 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_2004 node _T_2005 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_2005 node _T_2006 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_2006 node _T_2007 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_2007 node _T_2008 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_2008 node _T_2009 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_2009 node _T_2010 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_2010 node _T_2011 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_2011 node _T_2012 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_2012 node _T_2013 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_2013 node _T_2014 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_2014 node _T_2015 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_2015 node _T_2016 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_2016 node _T_2017 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_2017 node _T_2018 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_2018 node _T_2019 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_2019 node _T_2020 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_2020 node _T_2021 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_2021 node _T_2022 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_2022 node _T_2023 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_2023 node _T_2024 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_2024 node _T_2025 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_2025 node _T_2026 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_2026 node _T_2027 = eq(special_entry.tag_v, hv_17) node _T_2028 = eq(_WIRE_136.g, UInt<1>(0h0)) node _T_2029 = and(_T_2027, _T_2028) when _T_2029 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2030 = or(hv_17, hg_17) wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, special_entry.data[0] node _T_2031 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_2031 node _T_2032 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_2032 node _T_2033 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_2033 node _T_2034 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_2034 node _T_2035 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_2035 node _T_2036 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_2036 node _T_2037 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_2037 node _T_2038 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_2038 node _T_2039 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_2039 node _T_2040 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_2040 node _T_2041 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_2041 node _T_2042 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_2042 node _T_2043 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_2043 node _T_2044 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_2044 node _T_2045 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_2045 node _T_2046 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_2046 node _T_2047 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_2047 node _T_2048 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_2048 node _T_2049 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_2049 node _T_2050 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_2050 node _T_2051 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_2051 node _T_2052 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_2052 node _T_2053 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_2053 node _T_2054 = eq(special_entry.tag_v, _T_2030) when _T_2054 : connect special_entry.valid[0], UInt<1>(0h0) node _T_2055 = and(io.req.ready, io.req.valid) node _T_2056 = and(_T_2055, vsatp_mode_mismatch) when _T_2056 : wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][0].data[0] node _T_2057 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_2057 node _T_2058 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_2058 node _T_2059 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_2059 node _T_2060 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_2060 node _T_2061 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_2061 node _T_2062 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_2062 node _T_2063 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_2063 node _T_2064 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_2064 node _T_2065 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_2065 node _T_2066 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_2066 node _T_2067 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_2067 node _T_2068 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_2068 node _T_2069 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_2069 node _T_2070 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_2070 node _T_2071 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_2071 node _T_2072 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_2072 node _T_2073 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_2073 node _T_2074 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_2074 node _T_2075 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_2075 node _T_2076 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_2076 node _T_2077 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_2077 node _T_2078 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_2078 node _T_2079 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_2079 node _T_2080 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_2080 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][1].data[0] node _T_2081 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_2081 node _T_2082 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_2082 node _T_2083 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_2083 node _T_2084 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_2084 node _T_2085 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_2085 node _T_2086 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_2086 node _T_2087 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_2087 node _T_2088 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_2088 node _T_2089 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_2089 node _T_2090 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_2090 node _T_2091 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_2091 node _T_2092 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_2092 node _T_2093 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_2093 node _T_2094 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_2094 node _T_2095 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_2095 node _T_2096 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_2096 node _T_2097 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_2097 node _T_2098 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_2098 node _T_2099 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_2099 node _T_2100 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_2100 node _T_2101 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_2101 node _T_2102 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_2102 node _T_2103 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_2103 node _T_2104 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_2104 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][2].data[0] node _T_2105 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_2105 node _T_2106 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_2106 node _T_2107 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_2107 node _T_2108 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_2108 node _T_2109 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_2109 node _T_2110 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_2110 node _T_2111 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_2111 node _T_2112 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_2112 node _T_2113 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_2113 node _T_2114 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_2114 node _T_2115 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_2115 node _T_2116 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_2116 node _T_2117 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_2117 node _T_2118 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_2118 node _T_2119 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_2119 node _T_2120 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_2120 node _T_2121 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_2121 node _T_2122 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_2122 node _T_2123 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_2123 node _T_2124 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_2124 node _T_2125 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_2125 node _T_2126 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_2126 node _T_2127 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_2127 node _T_2128 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_2128 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][3].data[0] node _T_2129 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_2129 node _T_2130 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_2130 node _T_2131 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_2131 node _T_2132 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_2132 node _T_2133 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_2133 node _T_2134 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_2134 node _T_2135 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_2135 node _T_2136 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_2136 node _T_2137 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_2137 node _T_2138 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_2138 node _T_2139 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_2139 node _T_2140 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_2140 node _T_2141 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2141 node _T_2142 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2142 node _T_2143 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2143 node _T_2144 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2144 node _T_2145 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2145 node _T_2146 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2146 node _T_2147 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2147 node _T_2148 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2148 node _T_2149 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2149 node _T_2150 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2150 node _T_2151 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2151 node _T_2152 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_2152 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[1][0].data[0] node _T_2153 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2153 node _T_2154 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2154 node _T_2155 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2155 node _T_2156 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2156 node _T_2157 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2157 node _T_2158 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2158 node _T_2159 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2159 node _T_2160 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2160 node _T_2161 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2161 node _T_2162 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2162 node _T_2163 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2163 node _T_2164 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2164 node _T_2165 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2165 node _T_2166 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2166 node _T_2167 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2167 node _T_2168 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2168 node _T_2169 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2169 node _T_2170 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2170 node _T_2171 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2171 node _T_2172 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2172 node _T_2173 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2173 node _T_2174 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2174 node _T_2175 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2175 node _T_2176 = eq(sectored_entries[1][0].tag_v, UInt<1>(0h1)) when _T_2176 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[1][1].data[0] node _T_2177 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2177 node _T_2178 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2178 node _T_2179 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2179 node _T_2180 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2180 node _T_2181 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2181 node _T_2182 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2182 node _T_2183 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2183 node _T_2184 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2184 node _T_2185 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2185 node _T_2186 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2186 node _T_2187 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2187 node _T_2188 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2188 node _T_2189 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2189 node _T_2190 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2190 node _T_2191 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2191 node _T_2192 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2192 node _T_2193 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2193 node _T_2194 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2194 node _T_2195 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2195 node _T_2196 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2196 node _T_2197 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2197 node _T_2198 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2198 node _T_2199 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2199 node _T_2200 = eq(sectored_entries[1][1].tag_v, UInt<1>(0h1)) when _T_2200 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[1][2].data[0] node _T_2201 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2201 node _T_2202 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2202 node _T_2203 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2203 node _T_2204 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2204 node _T_2205 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2205 node _T_2206 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2206 node _T_2207 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2207 node _T_2208 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2208 node _T_2209 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2209 node _T_2210 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2210 node _T_2211 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2211 node _T_2212 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2212 node _T_2213 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2213 node _T_2214 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2214 node _T_2215 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2215 node _T_2216 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2216 node _T_2217 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2217 node _T_2218 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2218 node _T_2219 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2219 node _T_2220 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2220 node _T_2221 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2221 node _T_2222 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2222 node _T_2223 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2223 node _T_2224 = eq(sectored_entries[1][2].tag_v, UInt<1>(0h1)) when _T_2224 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[1][3].data[0] node _T_2225 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2225 node _T_2226 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2226 node _T_2227 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2227 node _T_2228 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2228 node _T_2229 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2229 node _T_2230 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2230 node _T_2231 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2231 node _T_2232 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2232 node _T_2233 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2233 node _T_2234 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2234 node _T_2235 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2235 node _T_2236 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2236 node _T_2237 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2237 node _T_2238 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2238 node _T_2239 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2239 node _T_2240 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2240 node _T_2241 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2241 node _T_2242 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2242 node _T_2243 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2243 node _T_2244 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2244 node _T_2245 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2245 node _T_2246 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2246 node _T_2247 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2247 node _T_2248 = eq(sectored_entries[1][3].tag_v, UInt<1>(0h1)) when _T_2248 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[2][0].data[0] node _T_2249 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2249 node _T_2250 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2250 node _T_2251 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2251 node _T_2252 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2252 node _T_2253 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2253 node _T_2254 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2254 node _T_2255 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2255 node _T_2256 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2256 node _T_2257 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2257 node _T_2258 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2258 node _T_2259 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2259 node _T_2260 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2260 node _T_2261 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2261 node _T_2262 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2262 node _T_2263 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2263 node _T_2264 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2264 node _T_2265 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2265 node _T_2266 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2266 node _T_2267 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2267 node _T_2268 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2268 node _T_2269 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2269 node _T_2270 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2270 node _T_2271 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2271 node _T_2272 = eq(sectored_entries[2][0].tag_v, UInt<1>(0h1)) when _T_2272 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[2][1].data[0] node _T_2273 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2273 node _T_2274 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2274 node _T_2275 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2275 node _T_2276 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2276 node _T_2277 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2277 node _T_2278 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2278 node _T_2279 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2279 node _T_2280 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2280 node _T_2281 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2281 node _T_2282 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2282 node _T_2283 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2283 node _T_2284 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2284 node _T_2285 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2285 node _T_2286 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2286 node _T_2287 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2287 node _T_2288 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2288 node _T_2289 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2289 node _T_2290 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2290 node _T_2291 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2291 node _T_2292 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2292 node _T_2293 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2293 node _T_2294 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2294 node _T_2295 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2295 node _T_2296 = eq(sectored_entries[2][1].tag_v, UInt<1>(0h1)) when _T_2296 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[2][2].data[0] node _T_2297 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2297 node _T_2298 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2298 node _T_2299 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2299 node _T_2300 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2300 node _T_2301 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2301 node _T_2302 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2302 node _T_2303 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2303 node _T_2304 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2304 node _T_2305 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2305 node _T_2306 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2306 node _T_2307 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2307 node _T_2308 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2308 node _T_2309 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2309 node _T_2310 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2310 node _T_2311 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2311 node _T_2312 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2312 node _T_2313 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2313 node _T_2314 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2314 node _T_2315 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2315 node _T_2316 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2316 node _T_2317 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2317 node _T_2318 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2318 node _T_2319 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2319 node _T_2320 = eq(sectored_entries[2][2].tag_v, UInt<1>(0h1)) when _T_2320 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[2][3].data[0] node _T_2321 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2321 node _T_2322 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2322 node _T_2323 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2323 node _T_2324 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2324 node _T_2325 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2325 node _T_2326 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2326 node _T_2327 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2327 node _T_2328 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2328 node _T_2329 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2329 node _T_2330 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2330 node _T_2331 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2331 node _T_2332 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2332 node _T_2333 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2333 node _T_2334 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2334 node _T_2335 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2335 node _T_2336 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2336 node _T_2337 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2337 node _T_2338 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2338 node _T_2339 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2339 node _T_2340 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2340 node _T_2341 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2341 node _T_2342 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2342 node _T_2343 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2343 node _T_2344 = eq(sectored_entries[2][3].tag_v, UInt<1>(0h1)) when _T_2344 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[3][0].data[0] node _T_2345 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2345 node _T_2346 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2346 node _T_2347 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2347 node _T_2348 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2348 node _T_2349 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2349 node _T_2350 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2350 node _T_2351 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2351 node _T_2352 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2352 node _T_2353 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2353 node _T_2354 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2354 node _T_2355 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2355 node _T_2356 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2356 node _T_2357 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2357 node _T_2358 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2358 node _T_2359 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2359 node _T_2360 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2360 node _T_2361 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2361 node _T_2362 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2362 node _T_2363 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2363 node _T_2364 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2364 node _T_2365 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2365 node _T_2366 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2366 node _T_2367 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2367 node _T_2368 = eq(sectored_entries[3][0].tag_v, UInt<1>(0h1)) when _T_2368 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[3][1].data[0] node _T_2369 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2369 node _T_2370 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2370 node _T_2371 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2371 node _T_2372 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2372 node _T_2373 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2373 node _T_2374 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2374 node _T_2375 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2375 node _T_2376 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2376 node _T_2377 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2377 node _T_2378 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2378 node _T_2379 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2379 node _T_2380 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2380 node _T_2381 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2381 node _T_2382 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2382 node _T_2383 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2383 node _T_2384 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2384 node _T_2385 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2385 node _T_2386 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2386 node _T_2387 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2387 node _T_2388 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2388 node _T_2389 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2389 node _T_2390 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2390 node _T_2391 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2391 node _T_2392 = eq(sectored_entries[3][1].tag_v, UInt<1>(0h1)) when _T_2392 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[3][2].data[0] node _T_2393 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2393 node _T_2394 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2394 node _T_2395 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2395 node _T_2396 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2396 node _T_2397 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2397 node _T_2398 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2398 node _T_2399 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2399 node _T_2400 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2400 node _T_2401 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2401 node _T_2402 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2402 node _T_2403 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2403 node _T_2404 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2404 node _T_2405 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2405 node _T_2406 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2406 node _T_2407 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2407 node _T_2408 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2408 node _T_2409 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2409 node _T_2410 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2410 node _T_2411 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2411 node _T_2412 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2412 node _T_2413 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2413 node _T_2414 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2414 node _T_2415 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2415 node _T_2416 = eq(sectored_entries[3][2].tag_v, UInt<1>(0h1)) when _T_2416 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[3][3].data[0] node _T_2417 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2417 node _T_2418 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2418 node _T_2419 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2419 node _T_2420 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2420 node _T_2421 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2421 node _T_2422 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2422 node _T_2423 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2423 node _T_2424 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2424 node _T_2425 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2425 node _T_2426 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2426 node _T_2427 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2427 node _T_2428 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2428 node _T_2429 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2429 node _T_2430 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2430 node _T_2431 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2431 node _T_2432 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2432 node _T_2433 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2433 node _T_2434 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2434 node _T_2435 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2435 node _T_2436 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2436 node _T_2437 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2437 node _T_2438 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2438 node _T_2439 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2439 node _T_2440 = eq(sectored_entries[3][3].tag_v, UInt<1>(0h1)) when _T_2440 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, superpage_entries[0].data[0] node _T_2441 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2441 node _T_2442 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2442 node _T_2443 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2443 node _T_2444 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2444 node _T_2445 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2445 node _T_2446 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2446 node _T_2447 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2447 node _T_2448 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2448 node _T_2449 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2449 node _T_2450 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2450 node _T_2451 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2451 node _T_2452 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2452 node _T_2453 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2453 node _T_2454 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2454 node _T_2455 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2455 node _T_2456 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2456 node _T_2457 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2457 node _T_2458 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2458 node _T_2459 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2459 node _T_2460 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2460 node _T_2461 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2461 node _T_2462 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2462 node _T_2463 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2463 node _T_2464 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_2464 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, special_entry.data[0] node _T_2465 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2465 node _T_2466 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2466 node _T_2467 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2467 node _T_2468 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2468 node _T_2469 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2469 node _T_2470 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2470 node _T_2471 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2471 node _T_2472 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2472 node _T_2473 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2473 node _T_2474 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2474 node _T_2475 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2475 node _T_2476 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2476 node _T_2477 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2477 node _T_2478 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2478 node _T_2479 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2479 node _T_2480 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2480 node _T_2481 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2481 node _T_2482 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2482 node _T_2483 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2483 node _T_2484 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2484 node _T_2485 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2485 node _T_2486 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2486 node _T_2487 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2487 node _T_2488 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_2488 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_2489 = asUInt(reset) node _T_2490 = or(multipleHits, _T_2489) when _T_2490 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[1][0].valid[0], UInt<1>(0h0) connect sectored_entries[1][1].valid[0], UInt<1>(0h0) connect sectored_entries[1][2].valid[0], UInt<1>(0h0) connect sectored_entries[1][3].valid[0], UInt<1>(0h0) connect sectored_entries[2][0].valid[0], UInt<1>(0h0) connect sectored_entries[2][1].valid[0], UInt<1>(0h0) connect sectored_entries[2][2].valid[0], UInt<1>(0h0) connect sectored_entries[2][3].valid[0], UInt<1>(0h0) connect sectored_entries[3][0].valid[0], UInt<1>(0h0) connect sectored_entries[3][1].valid[0], UInt<1>(0h0) connect sectored_entries[3][2].valid[0], UInt<1>(0h0) connect sectored_entries[3][3].valid[0], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_2491 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_2492 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_2493 = and(io.ptw.req.valid, _T_2492) node _T_2494 = eq(state, UInt<2>(0h3)) node _T_2495 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2496 = and(io.sfence.valid, _T_2495) node _T_2497 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2498 = and(_T_2496, _T_2497) node _T_2499 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2500 = and(io.sfence.valid, _T_2499) node _T_2501 = and(_T_2500, io.sfence.bits.rs2) node _T_2502 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2503 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2504 = and(_T_2502, _T_2503) node _T_2505 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2506 = and(_T_2505, io.sfence.bits.rs2)	module DTLB_18( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [3:0] _misaligned_T = 4'h2; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = 5'h1; // @[TLB.scala:550:69] wire [3:0] _misaligned_T_2 = 4'h1; // @[TLB.scala:550:69] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _ae_array_T_2 = 7'h0; // @[TLB.scala:583:8] wire [6:0] _ae_st_array_T_2 = 7'h0; // @[TLB.scala:588:8] wire [6:0] _ae_st_array_T_4 = 7'h0; // @[TLB.scala:589:8] wire [6:0] _ae_st_array_T_5 = 7'h0; // @[TLB.scala:588:53] wire [6:0] _ae_st_array_T_7 = 7'h0; // @[TLB.scala:590:8] wire [6:0] _ae_st_array_T_8 = 7'h0; // @[TLB.scala:589:53] wire [6:0] _ae_st_array_T_10 = 7'h0; // @[TLB.scala:591:8] wire [6:0] ae_st_array = 7'h0; // @[TLB.scala:590:53] wire [6:0] _must_alloc_array_T_1 = 7'h0; // @[TLB.scala:593:8] wire [6:0] _must_alloc_array_T_3 = 7'h0; // @[TLB.scala:594:8] wire [6:0] _must_alloc_array_T_4 = 7'h0; // @[TLB.scala:593:43] wire [6:0] _must_alloc_array_T_6 = 7'h0; // @[TLB.scala:595:8] wire [6:0] _must_alloc_array_T_7 = 7'h0; // @[TLB.scala:594:43] wire [6:0] _must_alloc_array_T_9 = 7'h0; // @[TLB.scala:596:8] wire [6:0] must_alloc_array = 7'h0; // @[TLB.scala:595:46] wire [6:0] pf_st_array = 7'h0; // @[TLB.scala:598:24] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_pf_st_T_1 = 7'h0; // @[TLB.scala:634:64] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [6:0] _io_resp_ae_st_T = 7'h0; // @[TLB.scala:642:33] wire [6:0] _io_resp_must_alloc_T = 7'h0; // @[TLB.scala:649:43] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h1; // @[TLB.scala:197:28, :318:7] wire [1:0] io_resp_size = 2'h1; // @[TLB.scala:197:28, :318:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {39'h0, io_req_bits_vaddr_0[0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_42 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_43 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_43; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_43; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_44 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_44[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_44[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_44[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_44[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_44[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_45 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_46 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_47 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_48 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_49 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_50 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_51 = ~do_refill \| _GEN_50 \| ~(_T_4 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_52 = ~do_refill \| _GEN_50 \| ~(_T_4 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_53 = ~do_refill \| _GEN_50 \| ~(_T_4 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_54 = ~do_refill \| _GEN_50 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_55 = invalidate_refill & _GEN_47; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_56 = ~do_refill \| _GEN_50 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_57 = invalidate_refill & _GEN_48; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_58 = invalidate_refill & _GEN_49; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_59 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_60 = ~do_refill \| _GEN_50 \| ~(_T_6 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_61 = ~do_refill \| _GEN_50 \| ~(_T_6 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_62 = ~do_refill \| _GEN_50 \| ~(_T_6 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_63 = ~do_refill \| _GEN_50 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_64 = ~do_refill \| _GEN_50 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_65 = ~do_refill \| _GEN_50 \| ~(_T_8 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_50 \| ~(_T_8 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_50 \| ~(_T_8 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_68 = ~do_refill \| _GEN_50 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_69 = ~do_refill \| _GEN_50 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = ~do_refill \| _GEN_50 \| ~((&waddr_1) & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_71 = ~do_refill \| _GEN_50 \| ~((&waddr_1) & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_72 = ~do_refill \| _GEN_50 \| ~((&waddr_1) & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_73 = ~do_refill \| _GEN_50 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_74 = ~do_refill \| _GEN_50 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_51) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_51 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_51) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_56 ? sectored_entries_0_0_valid_0 : ~_GEN_55 & (_GEN_47 \| ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_60) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_60 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_60) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_64 ? sectored_entries_0_1_valid_0 : ~_GEN_55 & (_GEN_47 \| ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_65 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_69 ? sectored_entries_0_2_valid_0 : ~_GEN_55 & (_GEN_47 \| ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_70) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_70 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_70) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_74 ? sectored_entries_0_3_valid_0 : ~_GEN_55 & (_GEN_47 \| ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_52) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_52 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_52) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_56 ? sectored_entries_1_0_valid_0 : ~_GEN_57 & (_GEN_48 \| ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_61) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_61 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_61) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_64 ? sectored_entries_1_1_valid_0 : ~_GEN_57 & (_GEN_48 \| ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_66 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_69 ? sectored_entries_1_2_valid_0 : ~_GEN_57 & (_GEN_48 \| ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_71) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_71 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_71) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_74 ? sectored_entries_1_3_valid_0 : ~_GEN_57 & (_GEN_48 \| ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_53) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_53 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_53) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_56 ? sectored_entries_2_0_valid_0 : ~_GEN_58 & (_GEN_49 \| ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_62) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_62 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_62) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_64 ? sectored_entries_2_1_valid_0 : ~_GEN_58 & (_GEN_49 \| ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_67 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_69 ? sectored_entries_2_2_valid_0 : ~_GEN_58 & (_GEN_49 \| ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_72) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_72 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_72) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_74 ? sectored_entries_2_3_valid_0 : ~_GEN_58 & (_GEN_49 \| ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_54) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_54 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_54) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_56 ? sectored_entries_3_0_valid_0 : ~_GEN_59 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_63) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_63 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_63) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_64 ? sectored_entries_3_1_valid_0 : ~_GEN_59 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_68) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_68 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_68) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_69 ? sectored_entries_3_2_valid_0 : ~_GEN_59 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_73 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_74 ? sectored_entries_3_3_valid_0 : ~_GEN_59 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_46) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_46 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_46) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_46 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_45) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_45 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_45 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_140 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_18 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_18 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_141 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_142 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_143 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_144 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_145 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_146 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_438 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_438( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_48 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}} regreset mask : UInt<4>, clock, reset, UInt<4>(0h0) wire in_arb_reqs : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}[4] wire in_arb_vals : UInt<1>[4] node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo) node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6) node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_12, UInt<8>(0h80), UInt<8>(0h0)) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_11, UInt<8>(0h40), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_10, UInt<8>(0h20), _in_arb_filter_T_14) node _in_arb_filter_T_16 = mux(_in_arb_filter_T_9, UInt<8>(0h10), _in_arb_filter_T_15) node _in_arb_filter_T_17 = mux(_in_arb_filter_T_8, UInt<8>(0h8), _in_arb_filter_T_16) node _in_arb_filter_T_18 = mux(_in_arb_filter_T_7, UInt<8>(0h4), _in_arb_filter_T_17) node _in_arb_filter_T_19 = mux(_in_arb_filter_T_6, UInt<8>(0h2), _in_arb_filter_T_18) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<8>(0h1), _in_arb_filter_T_19) node _in_arb_sel_T = bits(in_arb_filter, 3, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 4) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) node _T_2 = or(_T_1, in_arb_vals[3]) when _T_2 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = not(UInt<4>(0h0)) node _mask_T_4 = bits(in_arb_sel, 0, 0) node _mask_T_5 = bits(in_arb_sel, 1, 1) node _mask_T_6 = bits(in_arb_sel, 2, 2) node _mask_T_7 = bits(in_arb_sel, 3, 3) node _mask_T_8 = mux(_mask_T_4, _mask_T, UInt<1>(0h0)) node _mask_T_9 = mux(_mask_T_5, _mask_T_1, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_6, _mask_T_2, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_8, _mask_T_9) node _mask_T_13 = or(_mask_T_12, _mask_T_10) node _mask_T_14 = or(_mask_T_13, _mask_T_11) wire _mask_WIRE : UInt<4> connect _mask_WIRE, _mask_T_14 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T) connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1 node _in_arb_reqs_0_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_6_T_1 = and(io.req.`0`.bits.vc_sel.`0`[6], _in_arb_reqs_0_0_6_T) connect in_arb_reqs[0].`0`[6], _in_arb_reqs_0_0_6_T_1 node _in_arb_reqs_0_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_7_T_1 = and(io.req.`0`.bits.vc_sel.`0`[7], _in_arb_reqs_0_0_7_T) connect in_arb_reqs[0].`0`[7], _in_arb_reqs_0_0_7_T_1 node _in_arb_reqs_0_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_8_T_1 = and(io.req.`0`.bits.vc_sel.`0`[8], _in_arb_reqs_0_0_8_T) connect in_arb_reqs[0].`0`[8], _in_arb_reqs_0_0_8_T_1 node _in_arb_reqs_0_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_9_T_1 = and(io.req.`0`.bits.vc_sel.`0`[9], _in_arb_reqs_0_0_9_T) connect in_arb_reqs[0].`0`[9], _in_arb_reqs_0_0_9_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`0`[6]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`0`[7]) node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`0`[8]) node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`0`[9]) node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`1`[0]) node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_11 = and(io.req.`0`.valid, _in_arb_vals_0_T_10) connect in_arb_vals[0], _in_arb_vals_0_T_11 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T) connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1 node _in_arb_reqs_1_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_6_T_1 = and(io.req.`1`.bits.vc_sel.`0`[6], _in_arb_reqs_1_0_6_T) connect in_arb_reqs[1].`0`[6], _in_arb_reqs_1_0_6_T_1 node _in_arb_reqs_1_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_7_T_1 = and(io.req.`1`.bits.vc_sel.`0`[7], _in_arb_reqs_1_0_7_T) connect in_arb_reqs[1].`0`[7], _in_arb_reqs_1_0_7_T_1 node _in_arb_reqs_1_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_8_T_1 = and(io.req.`1`.bits.vc_sel.`0`[8], _in_arb_reqs_1_0_8_T) connect in_arb_reqs[1].`0`[8], _in_arb_reqs_1_0_8_T_1 node _in_arb_reqs_1_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_9_T_1 = and(io.req.`1`.bits.vc_sel.`0`[9], _in_arb_reqs_1_0_9_T) connect in_arb_reqs[1].`0`[9], _in_arb_reqs_1_0_9_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`0`[6]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`0`[7]) node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`0`[8]) node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`0`[9]) node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`1`[0]) node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_11 = and(io.req.`1`.valid, _in_arb_vals_1_T_10) connect in_arb_vals[1], _in_arb_vals_1_T_11 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T) connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1 node _in_arb_reqs_2_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_6_T_1 = and(io.req.`2`.bits.vc_sel.`0`[6], _in_arb_reqs_2_0_6_T) connect in_arb_reqs[2].`0`[6], _in_arb_reqs_2_0_6_T_1 node _in_arb_reqs_2_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_7_T_1 = and(io.req.`2`.bits.vc_sel.`0`[7], _in_arb_reqs_2_0_7_T) connect in_arb_reqs[2].`0`[7], _in_arb_reqs_2_0_7_T_1 node _in_arb_reqs_2_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_8_T_1 = and(io.req.`2`.bits.vc_sel.`0`[8], _in_arb_reqs_2_0_8_T) connect in_arb_reqs[2].`0`[8], _in_arb_reqs_2_0_8_T_1 node _in_arb_reqs_2_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_9_T_1 = and(io.req.`2`.bits.vc_sel.`0`[9], _in_arb_reqs_2_0_9_T) connect in_arb_reqs[2].`0`[9], _in_arb_reqs_2_0_9_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`0`[6]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`0`[7]) node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`0`[8]) node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`0`[9]) node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`1`[0]) node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_11 = and(io.req.`2`.valid, _in_arb_vals_2_T_10) connect in_arb_vals[2], _in_arb_vals_2_T_11 node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T) connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1 node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T) connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1 node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T) connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1 node _in_arb_reqs_3_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_3_T_1 = and(io.req.`3`.bits.vc_sel.`0`[3], _in_arb_reqs_3_0_3_T) connect in_arb_reqs[3].`0`[3], _in_arb_reqs_3_0_3_T_1 node _in_arb_reqs_3_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_4_T_1 = and(io.req.`3`.bits.vc_sel.`0`[4], _in_arb_reqs_3_0_4_T) connect in_arb_reqs[3].`0`[4], _in_arb_reqs_3_0_4_T_1 node _in_arb_reqs_3_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_5_T_1 = and(io.req.`3`.bits.vc_sel.`0`[5], _in_arb_reqs_3_0_5_T) connect in_arb_reqs[3].`0`[5], _in_arb_reqs_3_0_5_T_1 node _in_arb_reqs_3_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_6_T_1 = and(io.req.`3`.bits.vc_sel.`0`[6], _in_arb_reqs_3_0_6_T) connect in_arb_reqs[3].`0`[6], _in_arb_reqs_3_0_6_T_1 node _in_arb_reqs_3_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_7_T_1 = and(io.req.`3`.bits.vc_sel.`0`[7], _in_arb_reqs_3_0_7_T) connect in_arb_reqs[3].`0`[7], _in_arb_reqs_3_0_7_T_1 node _in_arb_reqs_3_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_8_T_1 = and(io.req.`3`.bits.vc_sel.`0`[8], _in_arb_reqs_3_0_8_T) connect in_arb_reqs[3].`0`[8], _in_arb_reqs_3_0_8_T_1 node _in_arb_reqs_3_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_9_T_1 = and(io.req.`3`.bits.vc_sel.`0`[9], _in_arb_reqs_3_0_9_T) connect in_arb_reqs[3].`0`[9], _in_arb_reqs_3_0_9_T_1 node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T) connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1 node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T) connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1 node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1]) node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2]) node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T_1, in_arb_reqs[3].`0`[3]) node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`0`[4]) node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T_3, in_arb_reqs[3].`0`[5]) node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`0`[6]) node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, in_arb_reqs[3].`0`[7]) node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`0`[8]) node _in_arb_vals_3_T_8 = or(_in_arb_vals_3_T_7, in_arb_reqs[3].`0`[9]) node _in_arb_vals_3_T_9 = or(_in_arb_vals_3_T_8, in_arb_reqs[3].`1`[0]) node _in_arb_vals_3_T_10 = or(_in_arb_vals_3_T_9, in_arb_reqs[3].`2`[0]) node _in_arb_vals_3_T_11 = and(io.req.`3`.valid, _in_arb_vals_3_T_10) connect in_arb_vals[3], _in_arb_vals_3_T_11 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) node _in_flow_T_3 = bits(in_arb_sel, 3, 3) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _in_flow_T_4 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_7 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_8 = or(_in_flow_T_4, _in_flow_T_5) node _in_flow_T_9 = or(_in_flow_T_8, _in_flow_T_6) node _in_flow_T_10 = or(_in_flow_T_9, _in_flow_T_7) wire _in_flow_WIRE : UInt<3> connect _in_flow_WIRE, _in_flow_T_10 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_13 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_15 = or(_in_flow_T_11, _in_flow_T_12) node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_13) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_14) wire _in_flow_WIRE_1 : UInt<4> connect _in_flow_WIRE_1, _in_flow_T_17 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_21 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_22 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_23 = or(_in_flow_T_22, _in_flow_T_20) node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_21) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_24 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_25 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_26 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_27 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_28 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_29 = or(_in_flow_T_25, _in_flow_T_26) node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_27) node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_28) wire _in_flow_WIRE_3 : UInt<4> connect _in_flow_WIRE_3, _in_flow_T_31 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_36 = or(_in_flow_T_32, _in_flow_T_33) node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_34) node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_35) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_38 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_T_4 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_7 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_8 = or(_in_vc_T_4, _in_vc_T_5) node _in_vc_T_9 = or(_in_vc_T_8, _in_vc_T_6) node _in_vc_T_10 = or(_in_vc_T_9, _in_vc_T_7) wire in_vc : UInt<4> connect in_vc, _in_vc_T_10 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3) wire in_vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _in_vc_sel_WIRE : UInt<1>[10] node _in_vc_sel_T_4 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_7 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_8 = or(_in_vc_sel_T_4, _in_vc_sel_T_5) node _in_vc_sel_T_9 = or(_in_vc_sel_T_8, _in_vc_sel_T_6) node _in_vc_sel_T_10 = or(_in_vc_sel_T_9, _in_vc_sel_T_7) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_10 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_13 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_15 = or(_in_vc_sel_T_11, _in_vc_sel_T_12) node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_13) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_14) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_21 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_22 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_23 = or(_in_vc_sel_T_22, _in_vc_sel_T_20) node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_21) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_24 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_25 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_26 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_27 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_28 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_29 = or(_in_vc_sel_T_25, _in_vc_sel_T_26) node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_27) node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_28) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_31 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_32, _in_vc_sel_T_33) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_34) node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_38 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 node _in_vc_sel_T_39 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_41 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_42 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_43 = or(_in_vc_sel_T_39, _in_vc_sel_T_40) node _in_vc_sel_T_44 = or(_in_vc_sel_T_43, _in_vc_sel_T_41) node _in_vc_sel_T_45 = or(_in_vc_sel_T_44, _in_vc_sel_T_42) wire _in_vc_sel_WIRE_6 : UInt<1> connect _in_vc_sel_WIRE_6, _in_vc_sel_T_45 connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6 node _in_vc_sel_T_46 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_47 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_48 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_49 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_50 = or(_in_vc_sel_T_46, _in_vc_sel_T_47) node _in_vc_sel_T_51 = or(_in_vc_sel_T_50, _in_vc_sel_T_48) node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_49) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_52 connect _in_vc_sel_WIRE[6], _in_vc_sel_WIRE_7 node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_56 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_57 = or(_in_vc_sel_T_53, _in_vc_sel_T_54) node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_55) node _in_vc_sel_T_59 = or(_in_vc_sel_T_58, _in_vc_sel_T_56) wire _in_vc_sel_WIRE_8 : UInt<1> connect _in_vc_sel_WIRE_8, _in_vc_sel_T_59 connect _in_vc_sel_WIRE[7], _in_vc_sel_WIRE_8 node _in_vc_sel_T_60 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_61 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_62 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_63 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_64 = or(_in_vc_sel_T_60, _in_vc_sel_T_61) node _in_vc_sel_T_65 = or(_in_vc_sel_T_64, _in_vc_sel_T_62) node _in_vc_sel_T_66 = or(_in_vc_sel_T_65, _in_vc_sel_T_63) wire _in_vc_sel_WIRE_9 : UInt<1> connect _in_vc_sel_WIRE_9, _in_vc_sel_T_66 connect _in_vc_sel_WIRE[8], _in_vc_sel_WIRE_9 node _in_vc_sel_T_67 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_68 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_69 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_70 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_71 = or(_in_vc_sel_T_67, _in_vc_sel_T_68) node _in_vc_sel_T_72 = or(_in_vc_sel_T_71, _in_vc_sel_T_69) node _in_vc_sel_T_73 = or(_in_vc_sel_T_72, _in_vc_sel_T_70) wire _in_vc_sel_WIRE_10 : UInt<1> connect _in_vc_sel_WIRE_10, _in_vc_sel_T_73 connect _in_vc_sel_WIRE[9], _in_vc_sel_WIRE_10 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_11 : UInt<1>[1] node _in_vc_sel_T_74 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_75 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_76 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_77 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_78 = or(_in_vc_sel_T_74, _in_vc_sel_T_75) node _in_vc_sel_T_79 = or(_in_vc_sel_T_78, _in_vc_sel_T_76) node _in_vc_sel_T_80 = or(_in_vc_sel_T_79, _in_vc_sel_T_77) wire _in_vc_sel_WIRE_12 : UInt<1> connect _in_vc_sel_WIRE_12, _in_vc_sel_T_80 connect _in_vc_sel_WIRE_11[0], _in_vc_sel_WIRE_12 connect in_vc_sel.`1`, _in_vc_sel_WIRE_11 wire _in_vc_sel_WIRE_13 : UInt<1>[1] node _in_vc_sel_T_81 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_82 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_83 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_84 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_85 = or(_in_vc_sel_T_81, _in_vc_sel_T_82) node _in_vc_sel_T_86 = or(_in_vc_sel_T_85, _in_vc_sel_T_83) node _in_vc_sel_T_87 = or(_in_vc_sel_T_86, _in_vc_sel_T_84) wire _in_vc_sel_WIRE_14 : UInt<1> connect _in_vc_sel_WIRE_14, _in_vc_sel_T_87 connect _in_vc_sel_WIRE_13[0], _in_vc_sel_WIRE_14 connect in_vc_sel.`2`, _in_vc_sel_WIRE_13 node _T_3 = or(in_arb_vals[0], in_arb_vals[1]) node _T_4 = or(_T_3, in_arb_vals[2]) node _T_5 = or(_T_4, in_arb_vals[3]) node hi = bits(in_arb_sel, 3, 2) node lo = bits(in_arb_sel, 1, 0) node _T_6 = orr(hi) node _T_7 = or(hi, lo) node _T_8 = bits(_T_7, 1, 1) node _T_9 = cat(_T_6, _T_8) node _T_10 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_11 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_12 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_13 = and(io.req.`3`.ready, io.req.`3`.valid) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node lo_lo = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node lo_hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3]) node lo_hi = cat(lo_hi_hi, in_vc_sel.`0`[2]) node lo_1 = cat(lo_hi, lo_lo) node hi_lo = cat(in_vc_sel.`0`[6], in_vc_sel.`0`[5]) node hi_hi_hi = cat(in_vc_sel.`0`[9], in_vc_sel.`0`[8]) node hi_hi = cat(hi_hi_hi, in_vc_sel.`0`[7]) node hi_1 = cat(hi_hi, hi_lo) node _T_17 = cat(hi_1, lo_1) node hi_2 = cat(in_vc_sel.`2`[0], in_vc_sel.`1`[0]) node _T_18 = cat(hi_2, _T_17) regreset mask_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_18, _full_T) node full = cat(_T_18, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = bits(full, 16, 16) node _oh_T_17 = bits(full, 17, 17) node _oh_T_18 = bits(full, 18, 18) node _oh_T_19 = bits(full, 19, 19) node _oh_T_20 = bits(full, 20, 20) node _oh_T_21 = bits(full, 21, 21) node _oh_T_22 = bits(full, 22, 22) node _oh_T_23 = bits(full, 23, 23) node _oh_T_24 = mux(_oh_T_23, UInt<24>(0h800000), UInt<24>(0h0)) node _oh_T_25 = mux(_oh_T_22, UInt<24>(0h400000), _oh_T_24) node _oh_T_26 = mux(_oh_T_21, UInt<24>(0h200000), _oh_T_25) node _oh_T_27 = mux(_oh_T_20, UInt<24>(0h100000), _oh_T_26) node _oh_T_28 = mux(_oh_T_19, UInt<24>(0h80000), _oh_T_27) node _oh_T_29 = mux(_oh_T_18, UInt<24>(0h40000), _oh_T_28) node _oh_T_30 = mux(_oh_T_17, UInt<24>(0h20000), _oh_T_29) node _oh_T_31 = mux(_oh_T_16, UInt<24>(0h10000), _oh_T_30) node _oh_T_32 = mux(_oh_T_15, UInt<24>(0h8000), _oh_T_31) node _oh_T_33 = mux(_oh_T_14, UInt<24>(0h4000), _oh_T_32) node _oh_T_34 = mux(_oh_T_13, UInt<24>(0h2000), _oh_T_33) node _oh_T_35 = mux(_oh_T_12, UInt<24>(0h1000), _oh_T_34) node _oh_T_36 = mux(_oh_T_11, UInt<24>(0h800), _oh_T_35) node _oh_T_37 = mux(_oh_T_10, UInt<24>(0h400), _oh_T_36) node _oh_T_38 = mux(_oh_T_9, UInt<24>(0h200), _oh_T_37) node _oh_T_39 = mux(_oh_T_8, UInt<24>(0h100), _oh_T_38) node _oh_T_40 = mux(_oh_T_7, UInt<24>(0h80), _oh_T_39) node _oh_T_41 = mux(_oh_T_6, UInt<24>(0h40), _oh_T_40) node _oh_T_42 = mux(_oh_T_5, UInt<24>(0h20), _oh_T_41) node _oh_T_43 = mux(_oh_T_4, UInt<24>(0h10), _oh_T_42) node _oh_T_44 = mux(_oh_T_3, UInt<24>(0h8), _oh_T_43) node _oh_T_45 = mux(_oh_T_2, UInt<24>(0h4), _oh_T_44) node _oh_T_46 = mux(_oh_T_1, UInt<24>(0h2), _oh_T_45) node oh = mux(_oh_T, UInt<24>(0h1), _oh_T_46) node _sel_T = bits(oh, 11, 0) node _sel_T_1 = shr(oh, 12) node sel = or(_sel_T, _sel_T_1) when _T_16 : node _mask_T_15 = bits(sel, 0, 0) node _mask_T_16 = not(UInt<1>(0h0)) node _mask_T_17 = bits(sel, 1, 1) node _mask_T_18 = not(UInt<2>(0h0)) node _mask_T_19 = bits(sel, 2, 2) node _mask_T_20 = not(UInt<3>(0h0)) node _mask_T_21 = bits(sel, 3, 3) node _mask_T_22 = not(UInt<4>(0h0)) node _mask_T_23 = bits(sel, 4, 4) node _mask_T_24 = not(UInt<5>(0h0)) node _mask_T_25 = bits(sel, 5, 5) node _mask_T_26 = not(UInt<6>(0h0)) node _mask_T_27 = bits(sel, 6, 6) node _mask_T_28 = not(UInt<7>(0h0)) node _mask_T_29 = bits(sel, 7, 7) node _mask_T_30 = not(UInt<8>(0h0)) node _mask_T_31 = bits(sel, 8, 8) node _mask_T_32 = not(UInt<9>(0h0)) node _mask_T_33 = bits(sel, 9, 9) node _mask_T_34 = not(UInt<10>(0h0)) node _mask_T_35 = bits(sel, 10, 10) node _mask_T_36 = not(UInt<11>(0h0)) node _mask_T_37 = bits(sel, 11, 11) node _mask_T_38 = not(UInt<12>(0h0)) node _mask_T_39 = mux(_mask_T_37, _mask_T_38, UInt<1>(0h0)) node _mask_T_40 = mux(_mask_T_35, _mask_T_36, _mask_T_39) node _mask_T_41 = mux(_mask_T_33, _mask_T_34, _mask_T_40) node _mask_T_42 = mux(_mask_T_31, _mask_T_32, _mask_T_41) node _mask_T_43 = mux(_mask_T_29, _mask_T_30, _mask_T_42) node _mask_T_44 = mux(_mask_T_27, _mask_T_28, _mask_T_43) node _mask_T_45 = mux(_mask_T_25, _mask_T_26, _mask_T_44) node _mask_T_46 = mux(_mask_T_23, _mask_T_24, _mask_T_45) node _mask_T_47 = mux(_mask_T_21, _mask_T_22, _mask_T_46) node _mask_T_48 = mux(_mask_T_19, _mask_T_20, _mask_T_47) node _mask_T_49 = mux(_mask_T_17, _mask_T_18, _mask_T_48) node _mask_T_50 = mux(_mask_T_15, _mask_T_16, _mask_T_49) connect mask_1, _mask_T_50 wire _WIRE : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _WIRE_1 : UInt<12> connect _WIRE_1, sel node _T_19 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_19 node _T_20 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_20 node _T_21 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_21 node _T_22 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_22 node _T_23 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_23 node _T_24 = bits(_WIRE_1, 5, 5) connect _WIRE.`0`[5], _T_24 node _T_25 = bits(_WIRE_1, 6, 6) connect _WIRE.`0`[6], _T_25 node _T_26 = bits(_WIRE_1, 7, 7) connect _WIRE.`0`[7], _T_26 node _T_27 = bits(_WIRE_1, 8, 8) connect _WIRE.`0`[8], _T_27 node _T_28 = bits(_WIRE_1, 9, 9) connect _WIRE.`0`[9], _T_28 node _T_29 = bits(_WIRE_1, 10, 10) connect _WIRE.`1`[0], _T_29 node _T_30 = bits(_WIRE_1, 11, 11) connect _WIRE.`2`[0], _T_30 wire _WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`0`[5], UInt<1>(0h0) connect _WIRE_2.`0`[6], UInt<1>(0h0) connect _WIRE_2.`0`[7], UInt<1>(0h0) connect _WIRE_2.`0`[8], UInt<1>(0h0) connect _WIRE_2.`0`[9], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) node _T_31 = mux(_T_5, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_31.`0` connect in_alloc.`1`, _T_31.`1` connect in_alloc.`2`, _T_31.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`0`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`0`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`0`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`0`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_1 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node lo_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3]) node lo_hi_1 = cat(lo_hi_hi_1, io.resp.`0`.vc_sel.`0`[2]) node lo_2 = cat(lo_hi_1, lo_lo_1) node hi_lo_1 = cat(io.resp.`0`.vc_sel.`0`[6], io.resp.`0`.vc_sel.`0`[5]) node hi_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[9], io.resp.`0`.vc_sel.`0`[8]) node hi_hi_1 = cat(hi_hi_hi_1, io.resp.`0`.vc_sel.`0`[7]) node hi_3 = cat(hi_hi_1, hi_lo_1) node _T_32 = cat(hi_3, lo_2) node hi_4 = cat(io.resp.`0`.vc_sel.`2`[0], io.resp.`0`.vc_sel.`1`[0]) node _T_33 = cat(hi_4, _T_32) node _T_34 = bits(_T_33, 0, 0) node _T_35 = bits(_T_33, 1, 1) node _T_36 = bits(_T_33, 2, 2) node _T_37 = bits(_T_33, 3, 3) node _T_38 = bits(_T_33, 4, 4) node _T_39 = bits(_T_33, 5, 5) node _T_40 = bits(_T_33, 6, 6) node _T_41 = bits(_T_33, 7, 7) node _T_42 = bits(_T_33, 8, 8) node _T_43 = bits(_T_33, 9, 9) node _T_44 = bits(_T_33, 10, 10) node _T_45 = bits(_T_33, 11, 11) node _T_46 = add(_T_35, _T_36) node _T_47 = bits(_T_46, 1, 0) node _T_48 = add(_T_34, _T_47) node _T_49 = bits(_T_48, 1, 0) node _T_50 = add(_T_38, _T_39) node _T_51 = bits(_T_50, 1, 0) node _T_52 = add(_T_37, _T_51) node _T_53 = bits(_T_52, 1, 0) node _T_54 = add(_T_49, _T_53) node _T_55 = bits(_T_54, 2, 0) node _T_56 = add(_T_41, _T_42) node _T_57 = bits(_T_56, 1, 0) node _T_58 = add(_T_40, _T_57) node _T_59 = bits(_T_58, 1, 0) node _T_60 = add(_T_44, _T_45) node _T_61 = bits(_T_60, 1, 0) node _T_62 = add(_T_43, _T_61) node _T_63 = bits(_T_62, 1, 0) node _T_64 = add(_T_59, _T_63) node _T_65 = bits(_T_64, 2, 0) node _T_66 = add(_T_55, _T_65) node _T_67 = bits(_T_66, 3, 0) node _T_68 = leq(_T_67, UInt<1>(0h1)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_68, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`1`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`1`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`1`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`1`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_2 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node lo_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3]) node lo_hi_2 = cat(lo_hi_hi_2, io.resp.`1`.vc_sel.`0`[2]) node lo_3 = cat(lo_hi_2, lo_lo_2) node hi_lo_2 = cat(io.resp.`1`.vc_sel.`0`[6], io.resp.`1`.vc_sel.`0`[5]) node hi_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[9], io.resp.`1`.vc_sel.`0`[8]) node hi_hi_2 = cat(hi_hi_hi_2, io.resp.`1`.vc_sel.`0`[7]) node hi_5 = cat(hi_hi_2, hi_lo_2) node _T_72 = cat(hi_5, lo_3) node hi_6 = cat(io.resp.`1`.vc_sel.`2`[0], io.resp.`1`.vc_sel.`1`[0]) node _T_73 = cat(hi_6, _T_72) node _T_74 = bits(_T_73, 0, 0) node _T_75 = bits(_T_73, 1, 1) node _T_76 = bits(_T_73, 2, 2) node _T_77 = bits(_T_73, 3, 3) node _T_78 = bits(_T_73, 4, 4) node _T_79 = bits(_T_73, 5, 5) node _T_80 = bits(_T_73, 6, 6) node _T_81 = bits(_T_73, 7, 7) node _T_82 = bits(_T_73, 8, 8) node _T_83 = bits(_T_73, 9, 9) node _T_84 = bits(_T_73, 10, 10) node _T_85 = bits(_T_73, 11, 11) node _T_86 = add(_T_75, _T_76) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_74, _T_87) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_78, _T_79) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_77, _T_91) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_89, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = add(_T_81, _T_82) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_80, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_84, _T_85) node _T_101 = bits(_T_100, 1, 0) node _T_102 = add(_T_83, _T_101) node _T_103 = bits(_T_102, 1, 0) node _T_104 = add(_T_99, _T_103) node _T_105 = bits(_T_104, 2, 0) node _T_106 = add(_T_95, _T_105) node _T_107 = bits(_T_106, 3, 0) node _T_108 = leq(_T_107, UInt<1>(0h1)) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`2`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`2`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`2`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`2`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_3 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node lo_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3]) node lo_hi_3 = cat(lo_hi_hi_3, io.resp.`2`.vc_sel.`0`[2]) node lo_4 = cat(lo_hi_3, lo_lo_3) node hi_lo_3 = cat(io.resp.`2`.vc_sel.`0`[6], io.resp.`2`.vc_sel.`0`[5]) node hi_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[9], io.resp.`2`.vc_sel.`0`[8]) node hi_hi_3 = cat(hi_hi_hi_3, io.resp.`2`.vc_sel.`0`[7]) node hi_7 = cat(hi_hi_3, hi_lo_3) node _T_112 = cat(hi_7, lo_4) node hi_8 = cat(io.resp.`2`.vc_sel.`2`[0], io.resp.`2`.vc_sel.`1`[0]) node _T_113 = cat(hi_8, _T_112) node _T_114 = bits(_T_113, 0, 0) node _T_115 = bits(_T_113, 1, 1) node _T_116 = bits(_T_113, 2, 2) node _T_117 = bits(_T_113, 3, 3) node _T_118 = bits(_T_113, 4, 4) node _T_119 = bits(_T_113, 5, 5) node _T_120 = bits(_T_113, 6, 6) node _T_121 = bits(_T_113, 7, 7) node _T_122 = bits(_T_113, 8, 8) node _T_123 = bits(_T_113, 9, 9) node _T_124 = bits(_T_113, 10, 10) node _T_125 = bits(_T_113, 11, 11) node _T_126 = add(_T_115, _T_116) node _T_127 = bits(_T_126, 1, 0) node _T_128 = add(_T_114, _T_127) node _T_129 = bits(_T_128, 1, 0) node _T_130 = add(_T_118, _T_119) node _T_131 = bits(_T_130, 1, 0) node _T_132 = add(_T_117, _T_131) node _T_133 = bits(_T_132, 1, 0) node _T_134 = add(_T_129, _T_133) node _T_135 = bits(_T_134, 2, 0) node _T_136 = add(_T_121, _T_122) node _T_137 = bits(_T_136, 1, 0) node _T_138 = add(_T_120, _T_137) node _T_139 = bits(_T_138, 1, 0) node _T_140 = add(_T_124, _T_125) node _T_141 = bits(_T_140, 1, 0) node _T_142 = add(_T_123, _T_141) node _T_143 = bits(_T_142, 1, 0) node _T_144 = add(_T_139, _T_143) node _T_145 = bits(_T_144, 2, 0) node _T_146 = add(_T_135, _T_145) node _T_147 = bits(_T_146, 3, 0) node _T_148 = leq(_T_147, UInt<1>(0h1)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_148, UInt<1>(0h1), "") : assert_2 node _io_req_3_ready_T = bits(in_arb_sel, 3, 3) connect io.req.`3`.ready, _io_req_3_ready_T connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`3`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`3`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`3`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`3`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`3`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`3`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`3`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_4 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0]) node lo_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[4], io.resp.`3`.vc_sel.`0`[3]) node lo_hi_4 = cat(lo_hi_hi_4, io.resp.`3`.vc_sel.`0`[2]) node lo_5 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(io.resp.`3`.vc_sel.`0`[6], io.resp.`3`.vc_sel.`0`[5]) node hi_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[9], io.resp.`3`.vc_sel.`0`[8]) node hi_hi_4 = cat(hi_hi_hi_4, io.resp.`3`.vc_sel.`0`[7]) node hi_9 = cat(hi_hi_4, hi_lo_4) node _T_152 = cat(hi_9, lo_5) node hi_10 = cat(io.resp.`3`.vc_sel.`2`[0], io.resp.`3`.vc_sel.`1`[0]) node _T_153 = cat(hi_10, _T_152) node _T_154 = bits(_T_153, 0, 0) node _T_155 = bits(_T_153, 1, 1) node _T_156 = bits(_T_153, 2, 2) node _T_157 = bits(_T_153, 3, 3) node _T_158 = bits(_T_153, 4, 4) node _T_159 = bits(_T_153, 5, 5) node _T_160 = bits(_T_153, 6, 6) node _T_161 = bits(_T_153, 7, 7) node _T_162 = bits(_T_153, 8, 8) node _T_163 = bits(_T_153, 9, 9) node _T_164 = bits(_T_153, 10, 10) node _T_165 = bits(_T_153, 11, 11) node _T_166 = add(_T_155, _T_156) node _T_167 = bits(_T_166, 1, 0) node _T_168 = add(_T_154, _T_167) node _T_169 = bits(_T_168, 1, 0) node _T_170 = add(_T_158, _T_159) node _T_171 = bits(_T_170, 1, 0) node _T_172 = add(_T_157, _T_171) node _T_173 = bits(_T_172, 1, 0) node _T_174 = add(_T_169, _T_173) node _T_175 = bits(_T_174, 2, 0) node _T_176 = add(_T_161, _T_162) node _T_177 = bits(_T_176, 1, 0) node _T_178 = add(_T_160, _T_177) node _T_179 = bits(_T_178, 1, 0) node _T_180 = add(_T_164, _T_165) node _T_181 = bits(_T_180, 1, 0) node _T_182 = add(_T_163, _T_181) node _T_183 = bits(_T_182, 1, 0) node _T_184 = add(_T_179, _T_183) node _T_185 = bits(_T_184, 2, 0) node _T_186 = add(_T_175, _T_185) node _T_187 = bits(_T_186, 3, 0) node _T_188 = leq(_T_187, UInt<1>(0h1)) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5] connect io.out_allocs.`0`[5].flow, in_flow connect io.out_allocs.`0`[6].alloc, in_alloc.`0`[6] connect io.out_allocs.`0`[6].flow, in_flow connect io.out_allocs.`0`[7].alloc, in_alloc.`0`[7] connect io.out_allocs.`0`[7].flow, in_flow connect io.out_allocs.`0`[8].alloc, in_alloc.`0`[8] connect io.out_allocs.`0`[8].flow, in_flow connect io.out_allocs.`0`[9].alloc, in_alloc.`0`[9] connect io.out_allocs.`0`[9].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow	module RotatingSingleVCAllocator_48( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_8_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_9_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_8_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_9_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {2'h0, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : {2'h0, in_arb_vals_1, 5'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] \| in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 \| in_arb_vals_1; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 \| in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_8 = io_req_1_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_9 = io_req_1_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (io_req_1_bits_vc_sel_0_0 \| io_req_1_bits_vc_sel_0_1 \| io_req_1_bits_vc_sel_0_2 \| io_req_1_bits_vc_sel_0_3 \| io_req_1_bits_vc_sel_0_4 \| io_req_1_bits_vc_sel_0_5 \| io_req_1_bits_vc_sel_0_6 \| io_req_1_bits_vc_sel_0_7 \| in_arb_reqs_1_0_8 \| in_arb_reqs_1_0_9 \| in_arb_reqs_1_1_0 \| in_arb_reqs_1_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_5 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_12 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_19 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_26 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_33 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_40 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_47 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_54 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_61 = in_arb_sel[1] & in_arb_reqs_1_0_8; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_68 = in_arb_sel[1] & in_arb_reqs_1_0_9; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_78 = in_arb_sel[0] & in_arb_reqs_0_1_0 \| in_arb_sel[1] & in_arb_reqs_1_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_2_0 \| in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36] reg [11:0] mask_1; // @[ISLIP.scala:17:25] wire [11:0] _full_T_1 = {_in_vc_sel_T_85, _in_vc_sel_T_78, _in_vc_sel_T_68, _in_vc_sel_T_61, _in_vc_sel_T_54, _in_vc_sel_T_47, _in_vc_sel_T_40, _in_vc_sel_T_33, _in_vc_sel_T_26, _in_vc_sel_T_19, _in_vc_sel_T_12, _in_vc_sel_T_5} & ~mask_1; // @[Mux.scala:30:73] wire [23:0] oh = _full_T_1[0] ? 24'h1 : _full_T_1[1] ? 24'h2 : _full_T_1[2] ? 24'h4 : _full_T_1[3] ? 24'h8 : _full_T_1[4] ? 24'h10 : _full_T_1[5] ? 24'h20 : _full_T_1[6] ? 24'h40 : _full_T_1[7] ? 24'h80 : _full_T_1[8] ? 24'h100 : _full_T_1[9] ? 24'h200 : _full_T_1[10] ? 24'h400 : _full_T_1[11] ? 24'h800 : _in_vc_sel_T_5 ? 24'h1000 : _in_vc_sel_T_12 ? 24'h2000 : _in_vc_sel_T_19 ? 24'h4000 : _in_vc_sel_T_26 ? 24'h8000 : _in_vc_sel_T_33 ? 24'h10000 : _in_vc_sel_T_40 ? 24'h20000 : _in_vc_sel_T_47 ? 24'h40000 : _in_vc_sel_T_54 ? 24'h80000 : _in_vc_sel_T_61 ? 24'h100000 : _in_vc_sel_T_68 ? 24'h200000 : _in_vc_sel_T_78 ? 24'h400000 : {_in_vc_sel_T_85, 23'h0}; // @[OneHot.scala:85:71] wire [11:0] sel = oh[11:0] \| oh[23:12]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[11]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[10]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_0_8 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_0_9 = _GEN & sel[9]; // @[package.scala:81:59]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_35 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_35 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_35( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_35 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_8 : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_17 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_8 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { phit : UInt<32>} wire _io_deq_bits_WIRE_1 : UInt<32> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0) connect _io_deq_bits_WIRE.phit, _io_deq_bits_T connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_92 inst sink_valid_1 of AsyncValidSync_93 inst source_extend of AsyncValidSync_94 inst source_valid of AsyncValidSync_95 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1	module AsyncQueueSink_Phit_8( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T \| _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T \| _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T \| _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w3 : input clock : Clock input reset : Reset output io : { flip d : UInt<3>, q : UInt<3>, flip en : UInt<1>} reg cdc_reg : UInt<3>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg	module ClockCrossingReg_w3( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [2:0] io_d, // @[SynchronizerReg.scala:195:14] output [2:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [2:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [2:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [2:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MemWriter : input clock : Clock input reset : Reset output io : { flip addr : UInt<21>, flip data : UInt<32>, flip size : UInt<2>, flip en : UInt<1>, mem_addr : UInt<19>, mem_data : UInt<8>[4], mem_masks : UInt<1>[4]} node offset = bits(io.addr, 1, 0) node _shiftedVec_T = shl(offset, 3) node _shiftedVec_T_1 = dshl(io.data, _shiftedVec_T) node _shiftedVec_T_2 = bits(_shiftedVec_T_1, 31, 0) node _shiftedVec_T_3 = bits(_shiftedVec_T_2, 0, 0) node _shiftedVec_T_4 = bits(_shiftedVec_T_2, 1, 1) node _shiftedVec_T_5 = bits(_shiftedVec_T_2, 2, 2) node _shiftedVec_T_6 = bits(_shiftedVec_T_2, 3, 3) node _shiftedVec_T_7 = bits(_shiftedVec_T_2, 4, 4) node _shiftedVec_T_8 = bits(_shiftedVec_T_2, 5, 5) node _shiftedVec_T_9 = bits(_shiftedVec_T_2, 6, 6) node _shiftedVec_T_10 = bits(_shiftedVec_T_2, 7, 7) node _shiftedVec_T_11 = bits(_shiftedVec_T_2, 8, 8) node _shiftedVec_T_12 = bits(_shiftedVec_T_2, 9, 9) node _shiftedVec_T_13 = bits(_shiftedVec_T_2, 10, 10) node _shiftedVec_T_14 = bits(_shiftedVec_T_2, 11, 11) node _shiftedVec_T_15 = bits(_shiftedVec_T_2, 12, 12) node _shiftedVec_T_16 = bits(_shiftedVec_T_2, 13, 13) node _shiftedVec_T_17 = bits(_shiftedVec_T_2, 14, 14) node _shiftedVec_T_18 = bits(_shiftedVec_T_2, 15, 15) node _shiftedVec_T_19 = bits(_shiftedVec_T_2, 16, 16) node _shiftedVec_T_20 = bits(_shiftedVec_T_2, 17, 17) node _shiftedVec_T_21 = bits(_shiftedVec_T_2, 18, 18) node _shiftedVec_T_22 = bits(_shiftedVec_T_2, 19, 19) node _shiftedVec_T_23 = bits(_shiftedVec_T_2, 20, 20) node _shiftedVec_T_24 = bits(_shiftedVec_T_2, 21, 21) node _shiftedVec_T_25 = bits(_shiftedVec_T_2, 22, 22) node _shiftedVec_T_26 = bits(_shiftedVec_T_2, 23, 23) node _shiftedVec_T_27 = bits(_shiftedVec_T_2, 24, 24) node _shiftedVec_T_28 = bits(_shiftedVec_T_2, 25, 25) node _shiftedVec_T_29 = bits(_shiftedVec_T_2, 26, 26) node _shiftedVec_T_30 = bits(_shiftedVec_T_2, 27, 27) node _shiftedVec_T_31 = bits(_shiftedVec_T_2, 28, 28) node _shiftedVec_T_32 = bits(_shiftedVec_T_2, 29, 29) node _shiftedVec_T_33 = bits(_shiftedVec_T_2, 30, 30) node _shiftedVec_T_34 = bits(_shiftedVec_T_2, 31, 31) node shiftedVec_lo_lo = cat(_shiftedVec_T_28, _shiftedVec_T_27) node shiftedVec_lo_hi = cat(_shiftedVec_T_30, _shiftedVec_T_29) node shiftedVec_lo = cat(shiftedVec_lo_hi, shiftedVec_lo_lo) node shiftedVec_hi_lo = cat(_shiftedVec_T_32, _shiftedVec_T_31) node shiftedVec_hi_hi = cat(_shiftedVec_T_34, _shiftedVec_T_33) node shiftedVec_hi = cat(shiftedVec_hi_hi, shiftedVec_hi_lo) node _shiftedVec_T_35 = cat(shiftedVec_hi, shiftedVec_lo) node shiftedVec_lo_lo_1 = cat(_shiftedVec_T_20, _shiftedVec_T_19) node shiftedVec_lo_hi_1 = cat(_shiftedVec_T_22, _shiftedVec_T_21) node shiftedVec_lo_1 = cat(shiftedVec_lo_hi_1, shiftedVec_lo_lo_1) node shiftedVec_hi_lo_1 = cat(_shiftedVec_T_24, _shiftedVec_T_23) node shiftedVec_hi_hi_1 = cat(_shiftedVec_T_26, _shiftedVec_T_25) node shiftedVec_hi_1 = cat(shiftedVec_hi_hi_1, shiftedVec_hi_lo_1) node _shiftedVec_T_36 = cat(shiftedVec_hi_1, shiftedVec_lo_1) node shiftedVec_lo_lo_2 = cat(_shiftedVec_T_12, _shiftedVec_T_11) node shiftedVec_lo_hi_2 = cat(_shiftedVec_T_14, _shiftedVec_T_13) node shiftedVec_lo_2 = cat(shiftedVec_lo_hi_2, shiftedVec_lo_lo_2) node shiftedVec_hi_lo_2 = cat(_shiftedVec_T_16, _shiftedVec_T_15) node shiftedVec_hi_hi_2 = cat(_shiftedVec_T_18, _shiftedVec_T_17) node shiftedVec_hi_2 = cat(shiftedVec_hi_hi_2, shiftedVec_hi_lo_2) node _shiftedVec_T_37 = cat(shiftedVec_hi_2, shiftedVec_lo_2) node shiftedVec_lo_lo_3 = cat(_shiftedVec_T_4, _shiftedVec_T_3) node shiftedVec_lo_hi_3 = cat(_shiftedVec_T_6, _shiftedVec_T_5) node shiftedVec_lo_3 = cat(shiftedVec_lo_hi_3, shiftedVec_lo_lo_3) node shiftedVec_hi_lo_3 = cat(_shiftedVec_T_8, _shiftedVec_T_7) node shiftedVec_hi_hi_3 = cat(_shiftedVec_T_10, _shiftedVec_T_9) node shiftedVec_hi_3 = cat(shiftedVec_hi_hi_3, shiftedVec_hi_lo_3) node _shiftedVec_T_38 = cat(shiftedVec_hi_3, shiftedVec_lo_3) wire shiftedVec : UInt<8>[4] connect shiftedVec[0], _shiftedVec_T_35 connect shiftedVec[1], _shiftedVec_T_36 connect shiftedVec[2], _shiftedVec_T_37 connect shiftedVec[3], _shiftedVec_T_38 node _masks_T = eq(UInt<1>(0h0), io.size) node _masks_T_1 = mux(_masks_T, UInt<1>(0h0), UInt<2>(0h3)) node _masks_T_2 = eq(UInt<1>(0h1), io.size) node _masks_T_3 = mux(_masks_T_2, UInt<1>(0h1), _masks_T_1) node _masks_T_4 = eq(UInt<2>(0h2), io.size) node _masks_T_5 = mux(_masks_T_4, UInt<2>(0h3), _masks_T_3) node _masks_mask_T = dshl(UInt<8>(0h1f), _masks_T_5) node masks_mask = bits(_masks_mask_T, 7, 4) node _masks_maskWithOffset_T = dshl(masks_mask, offset) node masks_maskWithOffset = bits(_masks_maskWithOffset_T, 3, 0) node masks_3 = bits(masks_maskWithOffset, 0, 0) node masks_2 = bits(masks_maskWithOffset, 1, 1) node masks_1 = bits(masks_maskWithOffset, 2, 2) node masks_0 = bits(masks_maskWithOffset, 3, 3) node _io_mem_addr_T = bits(io.addr, 20, 2) connect io.mem_addr, _io_mem_addr_T connect io.mem_data, shiftedVec node _T = and(masks_0, io.en) node _T_1 = and(masks_1, io.en) node _T_2 = and(masks_2, io.en) node _T_3 = and(masks_3, io.en) wire _WIRE : UInt<1>[4] connect _WIRE[0], _T connect _WIRE[1], _T_1 connect _WIRE[2], _T_2 connect _WIRE[3], _T_3 connect io.mem_masks, _WIRE	module MemWriter( // @[memory.scala:133:13] input clock, // @[memory.scala:133:13] input reset, // @[memory.scala:133:13] input [20:0] io_addr, // @[memory.scala:134:21] input [31:0] io_data, // @[memory.scala:134:21] input [1:0] io_size, // @[memory.scala:134:21] input io_en, // @[memory.scala:134:21] output [18:0] io_mem_addr, // @[memory.scala:134:21] output [7:0] io_mem_data_0, // @[memory.scala:134:21] output [7:0] io_mem_data_1, // @[memory.scala:134:21] output [7:0] io_mem_data_2, // @[memory.scala:134:21] output [7:0] io_mem_data_3, // @[memory.scala:134:21] output io_mem_masks_0, // @[memory.scala:134:21] output io_mem_masks_1, // @[memory.scala:134:21] output io_mem_masks_2, // @[memory.scala:134:21] output io_mem_masks_3 // @[memory.scala:134:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:133:13] wire [31:0] io_data_0 = io_data; // @[memory.scala:133:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:133:13] wire io_en_0 = io_en; // @[memory.scala:133:13] wire [18:0] _io_mem_addr_T; // @[memory.scala:151:32] wire [7:0] shiftedVec_0; // @[memory.scala:84:47] wire [7:0] shiftedVec_1; // @[memory.scala:84:47] wire [7:0] shiftedVec_2; // @[memory.scala:84:47] wire [7:0] shiftedVec_3; // @[memory.scala:84:47] wire [7:0] io_mem_data_0_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_1_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_2_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_3_0; // @[memory.scala:133:13] wire io_mem_masks_0_0; // @[memory.scala:133:13] wire io_mem_masks_1_0; // @[memory.scala:133:13] wire io_mem_masks_2_0; // @[memory.scala:133:13] wire io_mem_masks_3_0; // @[memory.scala:133:13] wire [18:0] io_mem_addr_0; // @[memory.scala:133:13] wire [1:0] offset = io_addr_0[1:0]; // @[memory.scala:133:13, :146:30] wire [4:0] _shiftedVec_T = {offset, 3'h0}; // @[memory.scala:146:30, :147:56] wire [62:0] _shiftedVec_T_1 = {31'h0, io_data_0} << _shiftedVec_T; // @[memory.scala:133:13, :147:{45,56}] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T_1[31:0]; // @[memory.scala:84:54, :147:45] wire _shiftedVec_T_3 = _shiftedVec_T_2[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_4 = _shiftedVec_T_2[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_2[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_2[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_2[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_2[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_2[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_2[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_2[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_2[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_2[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_2[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_2[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_2[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_2[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_2[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_2[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_2[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_2[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_2[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_2[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_2[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_2[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_2[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_2[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_2[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_2[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_2[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_2[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_2[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_2[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_2[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_28, _shiftedVec_T_27}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_30, _shiftedVec_T_29}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_32, _shiftedVec_T_31}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_34, _shiftedVec_T_33}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_35 = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:84:106] assign shiftedVec_0 = _shiftedVec_T_35; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_20, _shiftedVec_T_19}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_22, _shiftedVec_T_21}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_24, _shiftedVec_T_23}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_26, _shiftedVec_T_25}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] assign shiftedVec_1 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_12, _shiftedVec_T_11}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_14, _shiftedVec_T_13}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_16, _shiftedVec_T_15}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_18, _shiftedVec_T_17}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] assign shiftedVec_2 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_4, _shiftedVec_T_3}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_6, _shiftedVec_T_5}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_8, _shiftedVec_T_7}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_10, _shiftedVec_T_9}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] assign shiftedVec_3 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] assign io_mem_data_0_0 = shiftedVec_0; // @[memory.scala:84:47, :133:13] assign io_mem_data_1_0 = shiftedVec_1; // @[memory.scala:84:47, :133:13] assign io_mem_data_2_0 = shiftedVec_2; // @[memory.scala:84:47, :133:13] assign io_mem_data_3_0 = shiftedVec_3; // @[memory.scala:84:47, :133:13] wire _masks_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_1 = _masks_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _masks_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_3 = _masks_T_2 ? 2'h1 : _masks_T_1; // @[memory.scala:76:62] wire _masks_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_5 = _masks_T_4 ? 2'h3 : _masks_T_3; // @[memory.scala:76:62] wire [10:0] _masks_mask_T = 11'h1F << _masks_T_5; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [6:0] _masks_maskWithOffset_T = {3'h0, masks_mask} << offset; // @[memory.scala:79:53, :80:34, :146:30, :147:56] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:133:13, :151:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:133:13, :151:32] assign io_mem_masks_0_0 = masks_0 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_1_0 = masks_1 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_2_0 = masks_2 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_3_0 = masks_3 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:133:13] assign io_mem_data_0 = io_mem_data_0_0; // @[memory.scala:133:13] assign io_mem_data_1 = io_mem_data_1_0; // @[memory.scala:133:13] assign io_mem_data_2 = io_mem_data_2_0; // @[memory.scala:133:13] assign io_mem_data_3 = io_mem_data_3_0; // @[memory.scala:133:13] assign io_mem_masks_0 = io_mem_masks_0_0; // @[memory.scala:133:13] assign io_mem_masks_1 = io_mem_masks_1_0; // @[memory.scala:133:13] assign io_mem_masks_2 = io_mem_masks_2_0; // @[memory.scala:133:13] assign io_mem_masks_3 = io_mem_masks_3_0; // @[memory.scala:133:13] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_46 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_46( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_16 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1]}, credit_alloc : { `3` : { alloc : UInt<1>, tail : UInt<1>}[1], `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[2]}, switch_sel : { `3` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_116 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_117 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_118 connect arbs_2.clock, clock connect arbs_2.reset, reset inst arbs_3 of SwitchArbiter_119 connect arbs_3.clock, clock connect arbs_3.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) connect arbs_3.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[4] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_1 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _arbs_3_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[0].valid, _arbs_3_io_in_0_valid_T connect arbs_3.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_3.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_3_T = and(arbs_3.io.in[0].ready, arbs_3.io.in[0].valid) connect fires[3], _fires_3_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) node _io_req_0_0_ready_T_2 = or(_io_req_0_0_ready_T_1, fires[3]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_2 wire fires_1 : UInt<1>[4] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_1 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _arbs_3_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[1].valid, _arbs_3_io_in_1_valid_T connect arbs_3.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_3.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_3_T_1 = and(arbs_3.io.in[1].ready, arbs_3.io.in[1].valid) connect fires_1[3], _fires_3_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) node _io_req_1_0_ready_T_2 = or(_io_req_1_0_ready_T_1, fires_1[3]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_2 wire fires_2 : UInt<1>[4] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_1 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _arbs_3_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[2].valid, _arbs_3_io_in_2_valid_T connect arbs_3.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_3.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_3_T_2 = and(arbs_3.io.in[2].ready, arbs_3.io.in[2].valid) connect fires_2[3], _fires_3_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) node _io_req_2_0_ready_T_2 = or(_io_req_2_0_ready_T_1, fires_2[3]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_2 wire fires_3 : UInt<1>[4] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_1 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _arbs_3_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[3].valid, _arbs_3_io_in_3_valid_T connect arbs_3.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_3.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_3_T_3 = and(arbs_3.io.in[3].ready, arbs_3.io.in[3].valid) connect fires_3[3], _fires_3_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) node _io_req_3_0_ready_T_2 = or(_io_req_3_0_ready_T_1, fires_3[3]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_2 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 node _io_switch_sel_3_0_0_0_T = bits(arbs_3.io.chosen_oh[0], 0, 0) node _io_switch_sel_3_0_0_0_T_1 = and(arbs_3.io.in[0].valid, _io_switch_sel_3_0_0_0_T) node _io_switch_sel_3_0_0_0_T_2 = and(_io_switch_sel_3_0_0_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`0`[0], _io_switch_sel_3_0_0_0_T_2 node _io_switch_sel_3_0_1_0_T = bits(arbs_3.io.chosen_oh[0], 1, 1) node _io_switch_sel_3_0_1_0_T_1 = and(arbs_3.io.in[1].valid, _io_switch_sel_3_0_1_0_T) node _io_switch_sel_3_0_1_0_T_2 = and(_io_switch_sel_3_0_1_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`1`[0], _io_switch_sel_3_0_1_0_T_2 node _io_switch_sel_3_0_2_0_T = bits(arbs_3.io.chosen_oh[0], 2, 2) node _io_switch_sel_3_0_2_0_T_1 = and(arbs_3.io.in[2].valid, _io_switch_sel_3_0_2_0_T) node _io_switch_sel_3_0_2_0_T_2 = and(_io_switch_sel_3_0_2_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`2`[0], _io_switch_sel_3_0_2_0_T_2 node _io_switch_sel_3_0_3_0_T = bits(arbs_3.io.chosen_oh[0], 3, 3) node _io_switch_sel_3_0_3_0_T_1 = and(arbs_3.io.in[3].valid, _io_switch_sel_3_0_3_0_T) node _io_switch_sel_3_0_3_0_T_2 = and(_io_switch_sel_3_0_3_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`3`[0], _io_switch_sel_3_0_3_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`3`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_2 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_3 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_3 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail node _T_4 = and(arbs_3.io.out[0].valid, arbs_3.io.out[0].bits.vc_sel.`3`[0]) when _T_4 : connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`3`[0].tail, arbs_3.io.out[0].bits.tail	module SwitchAllocator_16( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 \| io_req_2_0_bits_vc_sel_0_1); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_116 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused /), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0), .io_out_0_bits_tail (/ unused /), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_0 (/ unused /), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/ unused /), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_0 (/ unused /), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_3 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (arbs_3_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_3_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_0 (/ unused */), .io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_3_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid \| _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid \| _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid \| _arbs_3_io_in_2_ready & arbs_3_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid \| _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid \| _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_3_0_2_0 = arbs_3_io_in_2_valid & _arbs_3_io_chosen_oh_0[2] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module StreamWriter : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, data : UInt<512>, len : UInt<7>, block : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, pool_en : UInt<1>, store_en : UInt<1>}}, tlb : { req : { valid : UInt<1>, bits : { tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, flip resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}}, busy : UInt<1>, flip flush : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg req : { vaddr : UInt<40>, data : UInt<512>, len : UInt<7>, block : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, pool_en : UInt<1>, store_en : UInt<1>}, clock reg data_blocks : UInt<128>[4], clock reg data_single_block : UInt<512>, clock node _data_T = eq(req.block, UInt<1>(0h0)) node data_lo = cat(data_blocks[1], data_blocks[0]) node data_hi = cat(data_blocks[3], data_blocks[2]) node _data_T_1 = cat(data_hi, data_lo) node data = mux(_data_T, data_single_block, _data_T_1) reg bytesSent : UInt<7>, clock node _bytesLeft_T = sub(req.len, bytesSent) node bytesLeft = tail(_bytesLeft_T, 1) regreset xactBusy : UInt<16>, clock, reset, UInt<16>(0h0) node _xactOnehot_T = not(xactBusy) node _xactOnehot_T_1 = bits(_xactOnehot_T, 0, 0) node _xactOnehot_T_2 = bits(_xactOnehot_T, 1, 1) node _xactOnehot_T_3 = bits(_xactOnehot_T, 2, 2) node _xactOnehot_T_4 = bits(_xactOnehot_T, 3, 3) node _xactOnehot_T_5 = bits(_xactOnehot_T, 4, 4) node _xactOnehot_T_6 = bits(_xactOnehot_T, 5, 5) node _xactOnehot_T_7 = bits(_xactOnehot_T, 6, 6) node _xactOnehot_T_8 = bits(_xactOnehot_T, 7, 7) node _xactOnehot_T_9 = bits(_xactOnehot_T, 8, 8) node _xactOnehot_T_10 = bits(_xactOnehot_T, 9, 9) node _xactOnehot_T_11 = bits(_xactOnehot_T, 10, 10) node _xactOnehot_T_12 = bits(_xactOnehot_T, 11, 11) node _xactOnehot_T_13 = bits(_xactOnehot_T, 12, 12) node _xactOnehot_T_14 = bits(_xactOnehot_T, 13, 13) node _xactOnehot_T_15 = bits(_xactOnehot_T, 14, 14) node _xactOnehot_T_16 = bits(_xactOnehot_T, 15, 15) node _xactOnehot_T_17 = mux(_xactOnehot_T_16, UInt<16>(0h8000), UInt<16>(0h0)) node _xactOnehot_T_18 = mux(_xactOnehot_T_15, UInt<16>(0h4000), _xactOnehot_T_17) node _xactOnehot_T_19 = mux(_xactOnehot_T_14, UInt<16>(0h2000), _xactOnehot_T_18) node _xactOnehot_T_20 = mux(_xactOnehot_T_13, UInt<16>(0h1000), _xactOnehot_T_19) node _xactOnehot_T_21 = mux(_xactOnehot_T_12, UInt<16>(0h800), _xactOnehot_T_20) node _xactOnehot_T_22 = mux(_xactOnehot_T_11, UInt<16>(0h400), _xactOnehot_T_21) node _xactOnehot_T_23 = mux(_xactOnehot_T_10, UInt<16>(0h200), _xactOnehot_T_22) node _xactOnehot_T_24 = mux(_xactOnehot_T_9, UInt<16>(0h100), _xactOnehot_T_23) node _xactOnehot_T_25 = mux(_xactOnehot_T_8, UInt<16>(0h80), _xactOnehot_T_24) node _xactOnehot_T_26 = mux(_xactOnehot_T_7, UInt<16>(0h40), _xactOnehot_T_25) node _xactOnehot_T_27 = mux(_xactOnehot_T_6, UInt<16>(0h20), _xactOnehot_T_26) node _xactOnehot_T_28 = mux(_xactOnehot_T_5, UInt<16>(0h10), _xactOnehot_T_27) node _xactOnehot_T_29 = mux(_xactOnehot_T_4, UInt<16>(0h8), _xactOnehot_T_28) node _xactOnehot_T_30 = mux(_xactOnehot_T_3, UInt<16>(0h4), _xactOnehot_T_29) node _xactOnehot_T_31 = mux(_xactOnehot_T_2, UInt<16>(0h2), _xactOnehot_T_30) node xactOnehot = mux(_xactOnehot_T_1, UInt<16>(0h1), _xactOnehot_T_31) node xactId_hi = bits(xactOnehot, 15, 8) node xactId_lo = bits(xactOnehot, 7, 0) node _xactId_T = orr(xactId_hi) node _xactId_T_1 = or(xactId_hi, xactId_lo) node xactId_hi_1 = bits(_xactId_T_1, 7, 4) node xactId_lo_1 = bits(_xactId_T_1, 3, 0) node _xactId_T_2 = orr(xactId_hi_1) node _xactId_T_3 = or(xactId_hi_1, xactId_lo_1) node xactId_hi_2 = bits(_xactId_T_3, 3, 2) node xactId_lo_2 = bits(_xactId_T_3, 1, 0) node _xactId_T_4 = orr(xactId_hi_2) node _xactId_T_5 = or(xactId_hi_2, xactId_lo_2) node _xactId_T_6 = bits(_xactId_T_5, 1, 1) node _xactId_T_7 = cat(_xactId_T_4, _xactId_T_6) node _xactId_T_8 = cat(_xactId_T_2, _xactId_T_7) node xactId = cat(_xactId_T, _xactId_T_8) wire xactBusy_fire : UInt<1> connect xactBusy_fire, UInt<1>(0h0) node _xactBusy_add_T = dshl(UInt<1>(0h1), xactId) node xactBusy_add = mux(xactBusy_fire, _xactBusy_add_T, UInt<1>(0h0)) node _xactBusy_remove_T = and(nodeOut.d.ready, nodeOut.d.valid) node _xactBusy_remove_T_1 = dshl(UInt<1>(0h1), nodeOut.d.bits.source) node _xactBusy_remove_T_2 = mux(_xactBusy_remove_T, _xactBusy_remove_T_1, UInt<1>(0h0)) node xactBusy_remove = not(_xactBusy_remove_T_2) node _xactBusy_T = or(xactBusy, xactBusy_add) node _xactBusy_T_1 = and(_xactBusy_T, xactBusy_remove) connect xactBusy, _xactBusy_T_1 node _state_machine_ready_for_req_T = eq(state, UInt<2>(0h0)) wire state_machine_ready_for_req : UInt<1> connect state_machine_ready_for_req, _state_machine_ready_for_req_T connect io.req.ready, state_machine_ready_for_req node _io_busy_T = orr(xactBusy) node _io_busy_T_1 = neq(state, UInt<2>(0h0)) node _io_busy_T_2 = or(_io_busy_T, _io_busy_T_1) connect io.busy, _io_busy_T_2 node _write_packets_vaddr_aligned_to_size_T = bits(req.vaddr, 38, 4) node write_packets_vaddr_aligned_to_size = cat(_write_packets_vaddr_aligned_to_size_T, UInt<4>(0h0)) node write_packets_vaddr_offset = bits(req.vaddr, 3, 0) node _write_packets_mask_T = geq(UInt<1>(0h0), write_packets_vaddr_offset) node _write_packets_mask_T_1 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_2 = lt(UInt<1>(0h0), _write_packets_mask_T_1) node _write_packets_mask_T_3 = and(_write_packets_mask_T, _write_packets_mask_T_2) node write_packets_mask_0 = and(_write_packets_mask_T_3, UInt<1>(0h1)) node _write_packets_mask_T_4 = geq(UInt<1>(0h1), write_packets_vaddr_offset) node _write_packets_mask_T_5 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_6 = lt(UInt<1>(0h1), _write_packets_mask_T_5) node _write_packets_mask_T_7 = and(_write_packets_mask_T_4, _write_packets_mask_T_6) node write_packets_mask_1 = and(_write_packets_mask_T_7, UInt<1>(0h1)) node _write_packets_mask_T_8 = geq(UInt<2>(0h2), write_packets_vaddr_offset) node _write_packets_mask_T_9 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_10 = lt(UInt<2>(0h2), _write_packets_mask_T_9) node _write_packets_mask_T_11 = and(_write_packets_mask_T_8, _write_packets_mask_T_10) node write_packets_mask_2 = and(_write_packets_mask_T_11, UInt<1>(0h1)) node _write_packets_mask_T_12 = geq(UInt<2>(0h3), write_packets_vaddr_offset) node _write_packets_mask_T_13 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_14 = lt(UInt<2>(0h3), _write_packets_mask_T_13) node _write_packets_mask_T_15 = and(_write_packets_mask_T_12, _write_packets_mask_T_14) node write_packets_mask_3 = and(_write_packets_mask_T_15, UInt<1>(0h1)) node _write_packets_mask_T_16 = geq(UInt<3>(0h4), write_packets_vaddr_offset) node _write_packets_mask_T_17 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_18 = lt(UInt<3>(0h4), _write_packets_mask_T_17) node _write_packets_mask_T_19 = and(_write_packets_mask_T_16, _write_packets_mask_T_18) node write_packets_mask_4 = and(_write_packets_mask_T_19, UInt<1>(0h1)) node _write_packets_mask_T_20 = geq(UInt<3>(0h5), write_packets_vaddr_offset) node _write_packets_mask_T_21 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_22 = lt(UInt<3>(0h5), _write_packets_mask_T_21) node _write_packets_mask_T_23 = and(_write_packets_mask_T_20, _write_packets_mask_T_22) node write_packets_mask_5 = and(_write_packets_mask_T_23, UInt<1>(0h1)) node _write_packets_mask_T_24 = geq(UInt<3>(0h6), write_packets_vaddr_offset) node _write_packets_mask_T_25 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_26 = lt(UInt<3>(0h6), _write_packets_mask_T_25) node _write_packets_mask_T_27 = and(_write_packets_mask_T_24, _write_packets_mask_T_26) node write_packets_mask_6 = and(_write_packets_mask_T_27, UInt<1>(0h1)) node _write_packets_mask_T_28 = geq(UInt<3>(0h7), write_packets_vaddr_offset) node _write_packets_mask_T_29 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_30 = lt(UInt<3>(0h7), _write_packets_mask_T_29) node _write_packets_mask_T_31 = and(_write_packets_mask_T_28, _write_packets_mask_T_30) node write_packets_mask_7 = and(_write_packets_mask_T_31, UInt<1>(0h1)) node _write_packets_mask_T_32 = geq(UInt<4>(0h8), write_packets_vaddr_offset) node _write_packets_mask_T_33 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_34 = lt(UInt<4>(0h8), _write_packets_mask_T_33) node _write_packets_mask_T_35 = and(_write_packets_mask_T_32, _write_packets_mask_T_34) node write_packets_mask_8 = and(_write_packets_mask_T_35, UInt<1>(0h1)) node _write_packets_mask_T_36 = geq(UInt<4>(0h9), write_packets_vaddr_offset) node _write_packets_mask_T_37 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_38 = lt(UInt<4>(0h9), _write_packets_mask_T_37) node _write_packets_mask_T_39 = and(_write_packets_mask_T_36, _write_packets_mask_T_38) node write_packets_mask_9 = and(_write_packets_mask_T_39, UInt<1>(0h1)) node _write_packets_mask_T_40 = geq(UInt<4>(0ha), write_packets_vaddr_offset) node _write_packets_mask_T_41 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_42 = lt(UInt<4>(0ha), _write_packets_mask_T_41) node _write_packets_mask_T_43 = and(_write_packets_mask_T_40, _write_packets_mask_T_42) node write_packets_mask_10 = and(_write_packets_mask_T_43, UInt<1>(0h1)) node _write_packets_mask_T_44 = geq(UInt<4>(0hb), write_packets_vaddr_offset) node _write_packets_mask_T_45 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_46 = lt(UInt<4>(0hb), _write_packets_mask_T_45) node _write_packets_mask_T_47 = and(_write_packets_mask_T_44, _write_packets_mask_T_46) node write_packets_mask_11 = and(_write_packets_mask_T_47, UInt<1>(0h1)) node _write_packets_mask_T_48 = geq(UInt<4>(0hc), write_packets_vaddr_offset) node _write_packets_mask_T_49 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_50 = lt(UInt<4>(0hc), _write_packets_mask_T_49) node _write_packets_mask_T_51 = and(_write_packets_mask_T_48, _write_packets_mask_T_50) node write_packets_mask_12 = and(_write_packets_mask_T_51, UInt<1>(0h1)) node _write_packets_mask_T_52 = geq(UInt<4>(0hd), write_packets_vaddr_offset) node _write_packets_mask_T_53 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_54 = lt(UInt<4>(0hd), _write_packets_mask_T_53) node _write_packets_mask_T_55 = and(_write_packets_mask_T_52, _write_packets_mask_T_54) node write_packets_mask_13 = and(_write_packets_mask_T_55, UInt<1>(0h1)) node _write_packets_mask_T_56 = geq(UInt<4>(0he), write_packets_vaddr_offset) node _write_packets_mask_T_57 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_58 = lt(UInt<4>(0he), _write_packets_mask_T_57) node _write_packets_mask_T_59 = and(_write_packets_mask_T_56, _write_packets_mask_T_58) node write_packets_mask_14 = and(_write_packets_mask_T_59, UInt<1>(0h1)) node _write_packets_mask_T_60 = geq(UInt<4>(0hf), write_packets_vaddr_offset) node _write_packets_mask_T_61 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_62 = lt(UInt<4>(0hf), _write_packets_mask_T_61) node _write_packets_mask_T_63 = and(_write_packets_mask_T_60, _write_packets_mask_T_62) node write_packets_mask_15 = and(_write_packets_mask_T_63, UInt<1>(0h1)) node _write_packets_mask_T_64 = geq(UInt<5>(0h10), write_packets_vaddr_offset) node _write_packets_mask_T_65 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_66 = lt(UInt<5>(0h10), _write_packets_mask_T_65) node _write_packets_mask_T_67 = and(_write_packets_mask_T_64, _write_packets_mask_T_66) node write_packets_mask_16 = and(_write_packets_mask_T_67, UInt<1>(0h0)) node _write_packets_mask_T_68 = geq(UInt<5>(0h11), write_packets_vaddr_offset) node _write_packets_mask_T_69 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_70 = lt(UInt<5>(0h11), _write_packets_mask_T_69) node _write_packets_mask_T_71 = and(_write_packets_mask_T_68, _write_packets_mask_T_70) node write_packets_mask_17 = and(_write_packets_mask_T_71, UInt<1>(0h0)) node _write_packets_mask_T_72 = geq(UInt<5>(0h12), write_packets_vaddr_offset) node _write_packets_mask_T_73 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_74 = lt(UInt<5>(0h12), _write_packets_mask_T_73) node _write_packets_mask_T_75 = and(_write_packets_mask_T_72, _write_packets_mask_T_74) node write_packets_mask_18 = and(_write_packets_mask_T_75, UInt<1>(0h0)) node _write_packets_mask_T_76 = geq(UInt<5>(0h13), write_packets_vaddr_offset) node _write_packets_mask_T_77 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_78 = lt(UInt<5>(0h13), _write_packets_mask_T_77) node _write_packets_mask_T_79 = and(_write_packets_mask_T_76, _write_packets_mask_T_78) node write_packets_mask_19 = and(_write_packets_mask_T_79, UInt<1>(0h0)) node _write_packets_mask_T_80 = geq(UInt<5>(0h14), write_packets_vaddr_offset) node _write_packets_mask_T_81 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_82 = lt(UInt<5>(0h14), _write_packets_mask_T_81) node _write_packets_mask_T_83 = and(_write_packets_mask_T_80, _write_packets_mask_T_82) node write_packets_mask_20 = and(_write_packets_mask_T_83, UInt<1>(0h0)) node _write_packets_mask_T_84 = geq(UInt<5>(0h15), write_packets_vaddr_offset) node _write_packets_mask_T_85 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_86 = lt(UInt<5>(0h15), _write_packets_mask_T_85) node _write_packets_mask_T_87 = and(_write_packets_mask_T_84, _write_packets_mask_T_86) node write_packets_mask_21 = and(_write_packets_mask_T_87, UInt<1>(0h0)) node _write_packets_mask_T_88 = geq(UInt<5>(0h16), write_packets_vaddr_offset) node _write_packets_mask_T_89 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_90 = lt(UInt<5>(0h16), _write_packets_mask_T_89) node _write_packets_mask_T_91 = and(_write_packets_mask_T_88, _write_packets_mask_T_90) node write_packets_mask_22 = and(_write_packets_mask_T_91, UInt<1>(0h0)) node _write_packets_mask_T_92 = geq(UInt<5>(0h17), write_packets_vaddr_offset) node _write_packets_mask_T_93 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_94 = lt(UInt<5>(0h17), _write_packets_mask_T_93) node _write_packets_mask_T_95 = and(_write_packets_mask_T_92, _write_packets_mask_T_94) node write_packets_mask_23 = and(_write_packets_mask_T_95, UInt<1>(0h0)) node _write_packets_mask_T_96 = geq(UInt<5>(0h18), write_packets_vaddr_offset) node _write_packets_mask_T_97 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_98 = lt(UInt<5>(0h18), _write_packets_mask_T_97) node _write_packets_mask_T_99 = and(_write_packets_mask_T_96, _write_packets_mask_T_98) node write_packets_mask_24 = and(_write_packets_mask_T_99, UInt<1>(0h0)) node _write_packets_mask_T_100 = geq(UInt<5>(0h19), write_packets_vaddr_offset) node _write_packets_mask_T_101 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_102 = lt(UInt<5>(0h19), _write_packets_mask_T_101) node _write_packets_mask_T_103 = and(_write_packets_mask_T_100, _write_packets_mask_T_102) node write_packets_mask_25 = and(_write_packets_mask_T_103, UInt<1>(0h0)) node _write_packets_mask_T_104 = geq(UInt<5>(0h1a), write_packets_vaddr_offset) node _write_packets_mask_T_105 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_106 = lt(UInt<5>(0h1a), _write_packets_mask_T_105) node _write_packets_mask_T_107 = and(_write_packets_mask_T_104, _write_packets_mask_T_106) node write_packets_mask_26 = and(_write_packets_mask_T_107, UInt<1>(0h0)) node _write_packets_mask_T_108 = geq(UInt<5>(0h1b), write_packets_vaddr_offset) node _write_packets_mask_T_109 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_110 = lt(UInt<5>(0h1b), _write_packets_mask_T_109) node _write_packets_mask_T_111 = and(_write_packets_mask_T_108, _write_packets_mask_T_110) node write_packets_mask_27 = and(_write_packets_mask_T_111, UInt<1>(0h0)) node _write_packets_mask_T_112 = geq(UInt<5>(0h1c), write_packets_vaddr_offset) node _write_packets_mask_T_113 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_114 = lt(UInt<5>(0h1c), _write_packets_mask_T_113) node _write_packets_mask_T_115 = and(_write_packets_mask_T_112, _write_packets_mask_T_114) node write_packets_mask_28 = and(_write_packets_mask_T_115, UInt<1>(0h0)) node _write_packets_mask_T_116 = geq(UInt<5>(0h1d), write_packets_vaddr_offset) node _write_packets_mask_T_117 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_118 = lt(UInt<5>(0h1d), _write_packets_mask_T_117) node _write_packets_mask_T_119 = and(_write_packets_mask_T_116, _write_packets_mask_T_118) node write_packets_mask_29 = and(_write_packets_mask_T_119, UInt<1>(0h0)) node _write_packets_mask_T_120 = geq(UInt<5>(0h1e), write_packets_vaddr_offset) node _write_packets_mask_T_121 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_122 = lt(UInt<5>(0h1e), _write_packets_mask_T_121) node _write_packets_mask_T_123 = and(_write_packets_mask_T_120, _write_packets_mask_T_122) node write_packets_mask_30 = and(_write_packets_mask_T_123, UInt<1>(0h0)) node _write_packets_mask_T_124 = geq(UInt<5>(0h1f), write_packets_vaddr_offset) node _write_packets_mask_T_125 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_126 = lt(UInt<5>(0h1f), _write_packets_mask_T_125) node _write_packets_mask_T_127 = and(_write_packets_mask_T_124, _write_packets_mask_T_126) node write_packets_mask_31 = and(_write_packets_mask_T_127, UInt<1>(0h0)) node _write_packets_mask_T_128 = geq(UInt<6>(0h20), write_packets_vaddr_offset) node _write_packets_mask_T_129 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_130 = lt(UInt<6>(0h20), _write_packets_mask_T_129) node _write_packets_mask_T_131 = and(_write_packets_mask_T_128, _write_packets_mask_T_130) node write_packets_mask_32 = and(_write_packets_mask_T_131, UInt<1>(0h0)) node _write_packets_mask_T_132 = geq(UInt<6>(0h21), write_packets_vaddr_offset) node _write_packets_mask_T_133 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_134 = lt(UInt<6>(0h21), _write_packets_mask_T_133) node _write_packets_mask_T_135 = and(_write_packets_mask_T_132, _write_packets_mask_T_134) node write_packets_mask_33 = and(_write_packets_mask_T_135, UInt<1>(0h0)) node _write_packets_mask_T_136 = geq(UInt<6>(0h22), write_packets_vaddr_offset) node _write_packets_mask_T_137 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_138 = lt(UInt<6>(0h22), _write_packets_mask_T_137) node _write_packets_mask_T_139 = and(_write_packets_mask_T_136, _write_packets_mask_T_138) node write_packets_mask_34 = and(_write_packets_mask_T_139, UInt<1>(0h0)) node _write_packets_mask_T_140 = geq(UInt<6>(0h23), write_packets_vaddr_offset) node _write_packets_mask_T_141 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_142 = lt(UInt<6>(0h23), _write_packets_mask_T_141) node _write_packets_mask_T_143 = and(_write_packets_mask_T_140, _write_packets_mask_T_142) node write_packets_mask_35 = and(_write_packets_mask_T_143, UInt<1>(0h0)) node _write_packets_mask_T_144 = geq(UInt<6>(0h24), write_packets_vaddr_offset) node _write_packets_mask_T_145 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_146 = lt(UInt<6>(0h24), _write_packets_mask_T_145) node _write_packets_mask_T_147 = and(_write_packets_mask_T_144, _write_packets_mask_T_146) node write_packets_mask_36 = and(_write_packets_mask_T_147, UInt<1>(0h0)) node _write_packets_mask_T_148 = geq(UInt<6>(0h25), write_packets_vaddr_offset) node _write_packets_mask_T_149 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_150 = lt(UInt<6>(0h25), _write_packets_mask_T_149) node _write_packets_mask_T_151 = and(_write_packets_mask_T_148, _write_packets_mask_T_150) node write_packets_mask_37 = and(_write_packets_mask_T_151, UInt<1>(0h0)) node _write_packets_mask_T_152 = geq(UInt<6>(0h26), write_packets_vaddr_offset) node _write_packets_mask_T_153 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_154 = lt(UInt<6>(0h26), _write_packets_mask_T_153) node _write_packets_mask_T_155 = and(_write_packets_mask_T_152, _write_packets_mask_T_154) node write_packets_mask_38 = and(_write_packets_mask_T_155, UInt<1>(0h0)) node _write_packets_mask_T_156 = geq(UInt<6>(0h27), write_packets_vaddr_offset) node _write_packets_mask_T_157 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_158 = lt(UInt<6>(0h27), _write_packets_mask_T_157) node _write_packets_mask_T_159 = and(_write_packets_mask_T_156, _write_packets_mask_T_158) node write_packets_mask_39 = and(_write_packets_mask_T_159, UInt<1>(0h0)) node _write_packets_mask_T_160 = geq(UInt<6>(0h28), write_packets_vaddr_offset) node _write_packets_mask_T_161 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_162 = lt(UInt<6>(0h28), _write_packets_mask_T_161) node _write_packets_mask_T_163 = and(_write_packets_mask_T_160, _write_packets_mask_T_162) node write_packets_mask_40 = and(_write_packets_mask_T_163, UInt<1>(0h0)) node _write_packets_mask_T_164 = geq(UInt<6>(0h29), write_packets_vaddr_offset) node _write_packets_mask_T_165 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_166 = lt(UInt<6>(0h29), _write_packets_mask_T_165) node _write_packets_mask_T_167 = and(_write_packets_mask_T_164, _write_packets_mask_T_166) node write_packets_mask_41 = and(_write_packets_mask_T_167, UInt<1>(0h0)) node _write_packets_mask_T_168 = geq(UInt<6>(0h2a), write_packets_vaddr_offset) node _write_packets_mask_T_169 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_170 = lt(UInt<6>(0h2a), _write_packets_mask_T_169) node _write_packets_mask_T_171 = and(_write_packets_mask_T_168, _write_packets_mask_T_170) node write_packets_mask_42 = and(_write_packets_mask_T_171, UInt<1>(0h0)) node _write_packets_mask_T_172 = geq(UInt<6>(0h2b), write_packets_vaddr_offset) node _write_packets_mask_T_173 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_174 = lt(UInt<6>(0h2b), _write_packets_mask_T_173) node _write_packets_mask_T_175 = and(_write_packets_mask_T_172, _write_packets_mask_T_174) node write_packets_mask_43 = and(_write_packets_mask_T_175, UInt<1>(0h0)) node _write_packets_mask_T_176 = geq(UInt<6>(0h2c), write_packets_vaddr_offset) node _write_packets_mask_T_177 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_178 = lt(UInt<6>(0h2c), _write_packets_mask_T_177) node _write_packets_mask_T_179 = and(_write_packets_mask_T_176, _write_packets_mask_T_178) node write_packets_mask_44 = and(_write_packets_mask_T_179, UInt<1>(0h0)) node _write_packets_mask_T_180 = geq(UInt<6>(0h2d), write_packets_vaddr_offset) node _write_packets_mask_T_181 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_182 = lt(UInt<6>(0h2d), _write_packets_mask_T_181) node _write_packets_mask_T_183 = and(_write_packets_mask_T_180, _write_packets_mask_T_182) node write_packets_mask_45 = and(_write_packets_mask_T_183, UInt<1>(0h0)) node _write_packets_mask_T_184 = geq(UInt<6>(0h2e), write_packets_vaddr_offset) node _write_packets_mask_T_185 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_186 = lt(UInt<6>(0h2e), _write_packets_mask_T_185) node _write_packets_mask_T_187 = and(_write_packets_mask_T_184, _write_packets_mask_T_186) node write_packets_mask_46 = and(_write_packets_mask_T_187, UInt<1>(0h0)) node _write_packets_mask_T_188 = geq(UInt<6>(0h2f), write_packets_vaddr_offset) node _write_packets_mask_T_189 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_190 = lt(UInt<6>(0h2f), _write_packets_mask_T_189) node _write_packets_mask_T_191 = and(_write_packets_mask_T_188, _write_packets_mask_T_190) node write_packets_mask_47 = and(_write_packets_mask_T_191, UInt<1>(0h0)) node _write_packets_mask_T_192 = geq(UInt<6>(0h30), write_packets_vaddr_offset) node _write_packets_mask_T_193 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_194 = lt(UInt<6>(0h30), _write_packets_mask_T_193) node _write_packets_mask_T_195 = and(_write_packets_mask_T_192, _write_packets_mask_T_194) node write_packets_mask_48 = and(_write_packets_mask_T_195, UInt<1>(0h0)) node _write_packets_mask_T_196 = geq(UInt<6>(0h31), write_packets_vaddr_offset) node _write_packets_mask_T_197 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_198 = lt(UInt<6>(0h31), _write_packets_mask_T_197) node _write_packets_mask_T_199 = and(_write_packets_mask_T_196, _write_packets_mask_T_198) node write_packets_mask_49 = and(_write_packets_mask_T_199, UInt<1>(0h0)) node _write_packets_mask_T_200 = geq(UInt<6>(0h32), write_packets_vaddr_offset) node _write_packets_mask_T_201 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_202 = lt(UInt<6>(0h32), _write_packets_mask_T_201) node _write_packets_mask_T_203 = and(_write_packets_mask_T_200, _write_packets_mask_T_202) node write_packets_mask_50 = and(_write_packets_mask_T_203, UInt<1>(0h0)) node _write_packets_mask_T_204 = geq(UInt<6>(0h33), write_packets_vaddr_offset) node _write_packets_mask_T_205 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_206 = lt(UInt<6>(0h33), _write_packets_mask_T_205) node _write_packets_mask_T_207 = and(_write_packets_mask_T_204, _write_packets_mask_T_206) node write_packets_mask_51 = and(_write_packets_mask_T_207, UInt<1>(0h0)) node _write_packets_mask_T_208 = geq(UInt<6>(0h34), write_packets_vaddr_offset) node _write_packets_mask_T_209 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_210 = lt(UInt<6>(0h34), _write_packets_mask_T_209) node _write_packets_mask_T_211 = and(_write_packets_mask_T_208, _write_packets_mask_T_210) node write_packets_mask_52 = and(_write_packets_mask_T_211, UInt<1>(0h0)) node _write_packets_mask_T_212 = geq(UInt<6>(0h35), write_packets_vaddr_offset) node _write_packets_mask_T_213 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_214 = lt(UInt<6>(0h35), _write_packets_mask_T_213) node _write_packets_mask_T_215 = and(_write_packets_mask_T_212, _write_packets_mask_T_214) node write_packets_mask_53 = and(_write_packets_mask_T_215, UInt<1>(0h0)) node _write_packets_mask_T_216 = geq(UInt<6>(0h36), write_packets_vaddr_offset) node _write_packets_mask_T_217 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_218 = lt(UInt<6>(0h36), _write_packets_mask_T_217) node _write_packets_mask_T_219 = and(_write_packets_mask_T_216, _write_packets_mask_T_218) node write_packets_mask_54 = and(_write_packets_mask_T_219, UInt<1>(0h0)) node _write_packets_mask_T_220 = geq(UInt<6>(0h37), write_packets_vaddr_offset) node _write_packets_mask_T_221 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_222 = lt(UInt<6>(0h37), _write_packets_mask_T_221) node _write_packets_mask_T_223 = and(_write_packets_mask_T_220, _write_packets_mask_T_222) node write_packets_mask_55 = and(_write_packets_mask_T_223, UInt<1>(0h0)) node _write_packets_mask_T_224 = geq(UInt<6>(0h38), write_packets_vaddr_offset) node _write_packets_mask_T_225 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_226 = lt(UInt<6>(0h38), _write_packets_mask_T_225) node _write_packets_mask_T_227 = and(_write_packets_mask_T_224, _write_packets_mask_T_226) node write_packets_mask_56 = and(_write_packets_mask_T_227, UInt<1>(0h0)) node _write_packets_mask_T_228 = geq(UInt<6>(0h39), write_packets_vaddr_offset) node _write_packets_mask_T_229 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_230 = lt(UInt<6>(0h39), _write_packets_mask_T_229) node _write_packets_mask_T_231 = and(_write_packets_mask_T_228, _write_packets_mask_T_230) node write_packets_mask_57 = and(_write_packets_mask_T_231, UInt<1>(0h0)) node _write_packets_mask_T_232 = geq(UInt<6>(0h3a), write_packets_vaddr_offset) node _write_packets_mask_T_233 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_234 = lt(UInt<6>(0h3a), _write_packets_mask_T_233) node _write_packets_mask_T_235 = and(_write_packets_mask_T_232, _write_packets_mask_T_234) node write_packets_mask_58 = and(_write_packets_mask_T_235, UInt<1>(0h0)) node _write_packets_mask_T_236 = geq(UInt<6>(0h3b), write_packets_vaddr_offset) node _write_packets_mask_T_237 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_238 = lt(UInt<6>(0h3b), _write_packets_mask_T_237) node _write_packets_mask_T_239 = and(_write_packets_mask_T_236, _write_packets_mask_T_238) node write_packets_mask_59 = and(_write_packets_mask_T_239, UInt<1>(0h0)) node _write_packets_mask_T_240 = geq(UInt<6>(0h3c), write_packets_vaddr_offset) node _write_packets_mask_T_241 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_242 = lt(UInt<6>(0h3c), _write_packets_mask_T_241) node _write_packets_mask_T_243 = and(_write_packets_mask_T_240, _write_packets_mask_T_242) node write_packets_mask_60 = and(_write_packets_mask_T_243, UInt<1>(0h0)) node _write_packets_mask_T_244 = geq(UInt<6>(0h3d), write_packets_vaddr_offset) node _write_packets_mask_T_245 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_246 = lt(UInt<6>(0h3d), _write_packets_mask_T_245) node _write_packets_mask_T_247 = and(_write_packets_mask_T_244, _write_packets_mask_T_246) node write_packets_mask_61 = and(_write_packets_mask_T_247, UInt<1>(0h0)) node _write_packets_mask_T_248 = geq(UInt<6>(0h3e), write_packets_vaddr_offset) node _write_packets_mask_T_249 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_250 = lt(UInt<6>(0h3e), _write_packets_mask_T_249) node _write_packets_mask_T_251 = and(_write_packets_mask_T_248, _write_packets_mask_T_250) node write_packets_mask_62 = and(_write_packets_mask_T_251, UInt<1>(0h0)) node _write_packets_mask_T_252 = geq(UInt<6>(0h3f), write_packets_vaddr_offset) node _write_packets_mask_T_253 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_254 = lt(UInt<6>(0h3f), _write_packets_mask_T_253) node _write_packets_mask_T_255 = and(_write_packets_mask_T_252, _write_packets_mask_T_254) node write_packets_mask_63 = and(_write_packets_mask_T_255, UInt<1>(0h0)) node _write_packets_bytes_written_T = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_bytes_written_T_1 = gt(_write_packets_bytes_written_T, UInt<5>(0h10)) node _write_packets_bytes_written_T_2 = sub(UInt<5>(0h10), write_packets_vaddr_offset) node _write_packets_bytes_written_T_3 = tail(_write_packets_bytes_written_T_2, 1) node write_packets_bytes_written = mux(_write_packets_bytes_written_T_1, _write_packets_bytes_written_T_3, bytesLeft) wire write_packets_0 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_0.size, UInt<5>(0h10) connect write_packets_0.lg_size, UInt<3>(0h4) wire _write_packets_WIRE : UInt<1>[16] connect _write_packets_WIRE[0], write_packets_mask_0 connect _write_packets_WIRE[1], write_packets_mask_1 connect _write_packets_WIRE[2], write_packets_mask_2 connect _write_packets_WIRE[3], write_packets_mask_3 connect _write_packets_WIRE[4], write_packets_mask_4 connect _write_packets_WIRE[5], write_packets_mask_5 connect _write_packets_WIRE[6], write_packets_mask_6 connect _write_packets_WIRE[7], write_packets_mask_7 connect _write_packets_WIRE[8], write_packets_mask_8 connect _write_packets_WIRE[9], write_packets_mask_9 connect _write_packets_WIRE[10], write_packets_mask_10 connect _write_packets_WIRE[11], write_packets_mask_11 connect _write_packets_WIRE[12], write_packets_mask_12 connect _write_packets_WIRE[13], write_packets_mask_13 connect _write_packets_WIRE[14], write_packets_mask_14 connect _write_packets_WIRE[15], write_packets_mask_15 wire _write_packets_WIRE_1 : UInt<1>[16] connect _write_packets_WIRE_1[0], write_packets_mask_16 connect _write_packets_WIRE_1[1], write_packets_mask_17 connect _write_packets_WIRE_1[2], write_packets_mask_18 connect _write_packets_WIRE_1[3], write_packets_mask_19 connect _write_packets_WIRE_1[4], write_packets_mask_20 connect _write_packets_WIRE_1[5], write_packets_mask_21 connect _write_packets_WIRE_1[6], write_packets_mask_22 connect _write_packets_WIRE_1[7], write_packets_mask_23 connect _write_packets_WIRE_1[8], write_packets_mask_24 connect _write_packets_WIRE_1[9], write_packets_mask_25 connect _write_packets_WIRE_1[10], write_packets_mask_26 connect _write_packets_WIRE_1[11], write_packets_mask_27 connect _write_packets_WIRE_1[12], write_packets_mask_28 connect _write_packets_WIRE_1[13], write_packets_mask_29 connect _write_packets_WIRE_1[14], write_packets_mask_30 connect _write_packets_WIRE_1[15], write_packets_mask_31 wire _write_packets_WIRE_2 : UInt<1>[16] connect _write_packets_WIRE_2[0], write_packets_mask_32 connect _write_packets_WIRE_2[1], write_packets_mask_33 connect _write_packets_WIRE_2[2], write_packets_mask_34 connect _write_packets_WIRE_2[3], write_packets_mask_35 connect _write_packets_WIRE_2[4], write_packets_mask_36 connect _write_packets_WIRE_2[5], write_packets_mask_37 connect _write_packets_WIRE_2[6], write_packets_mask_38 connect _write_packets_WIRE_2[7], write_packets_mask_39 connect _write_packets_WIRE_2[8], write_packets_mask_40 connect _write_packets_WIRE_2[9], write_packets_mask_41 connect _write_packets_WIRE_2[10], write_packets_mask_42 connect _write_packets_WIRE_2[11], write_packets_mask_43 connect _write_packets_WIRE_2[12], write_packets_mask_44 connect _write_packets_WIRE_2[13], write_packets_mask_45 connect _write_packets_WIRE_2[14], write_packets_mask_46 connect _write_packets_WIRE_2[15], write_packets_mask_47 wire _write_packets_WIRE_3 : UInt<1>[16] connect _write_packets_WIRE_3[0], write_packets_mask_48 connect _write_packets_WIRE_3[1], write_packets_mask_49 connect _write_packets_WIRE_3[2], write_packets_mask_50 connect _write_packets_WIRE_3[3], write_packets_mask_51 connect _write_packets_WIRE_3[4], write_packets_mask_52 connect _write_packets_WIRE_3[5], write_packets_mask_53 connect _write_packets_WIRE_3[6], write_packets_mask_54 connect _write_packets_WIRE_3[7], write_packets_mask_55 connect _write_packets_WIRE_3[8], write_packets_mask_56 connect _write_packets_WIRE_3[9], write_packets_mask_57 connect _write_packets_WIRE_3[10], write_packets_mask_58 connect _write_packets_WIRE_3[11], write_packets_mask_59 connect _write_packets_WIRE_3[12], write_packets_mask_60 connect _write_packets_WIRE_3[13], write_packets_mask_61 connect _write_packets_WIRE_3[14], write_packets_mask_62 connect _write_packets_WIRE_3[15], write_packets_mask_63 wire _write_packets_WIRE_4 : UInt<1>[16][4] connect _write_packets_WIRE_4[0], _write_packets_WIRE connect _write_packets_WIRE_4[1], _write_packets_WIRE_1 connect _write_packets_WIRE_4[2], _write_packets_WIRE_2 connect _write_packets_WIRE_4[3], _write_packets_WIRE_3 connect write_packets_0.mask, _write_packets_WIRE_4 connect write_packets_0.vaddr, write_packets_vaddr_aligned_to_size node _write_packets_packet_is_full_T = and(write_packets_mask_0, write_packets_mask_1) node _write_packets_packet_is_full_T_1 = and(_write_packets_packet_is_full_T, write_packets_mask_2) node _write_packets_packet_is_full_T_2 = and(_write_packets_packet_is_full_T_1, write_packets_mask_3) node _write_packets_packet_is_full_T_3 = and(_write_packets_packet_is_full_T_2, write_packets_mask_4) node _write_packets_packet_is_full_T_4 = and(_write_packets_packet_is_full_T_3, write_packets_mask_5) node _write_packets_packet_is_full_T_5 = and(_write_packets_packet_is_full_T_4, write_packets_mask_6) node _write_packets_packet_is_full_T_6 = and(_write_packets_packet_is_full_T_5, write_packets_mask_7) node _write_packets_packet_is_full_T_7 = and(_write_packets_packet_is_full_T_6, write_packets_mask_8) node _write_packets_packet_is_full_T_8 = and(_write_packets_packet_is_full_T_7, write_packets_mask_9) node _write_packets_packet_is_full_T_9 = and(_write_packets_packet_is_full_T_8, write_packets_mask_10) node _write_packets_packet_is_full_T_10 = and(_write_packets_packet_is_full_T_9, write_packets_mask_11) node _write_packets_packet_is_full_T_11 = and(_write_packets_packet_is_full_T_10, write_packets_mask_12) node _write_packets_packet_is_full_T_12 = and(_write_packets_packet_is_full_T_11, write_packets_mask_13) node _write_packets_packet_is_full_T_13 = and(_write_packets_packet_is_full_T_12, write_packets_mask_14) node _write_packets_packet_is_full_T_14 = and(_write_packets_packet_is_full_T_13, write_packets_mask_15) connect write_packets_0.is_full, _write_packets_packet_is_full_T_14 connect write_packets_0.bytes_written, write_packets_bytes_written node _write_packets_left_shift_T = geq(write_packets_vaddr_offset, UInt<1>(0h0)) node _write_packets_left_shift_T_1 = lt(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_2 = and(_write_packets_left_shift_T, _write_packets_left_shift_T_1) node _write_packets_left_shift_T_3 = sub(write_packets_vaddr_offset, UInt<1>(0h0)) node _write_packets_left_shift_T_4 = tail(_write_packets_left_shift_T_3, 1) node write_packets_left_shift = mux(_write_packets_left_shift_T_2, _write_packets_left_shift_T_4, UInt<1>(0h0)) node _write_packets_right_shift_T = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_1 = geq(_write_packets_right_shift_T, UInt<1>(0h0)) node _write_packets_right_shift_T_2 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_3 = lt(_write_packets_right_shift_T_2, UInt<5>(0h10)) node _write_packets_right_shift_T_4 = and(_write_packets_right_shift_T_1, _write_packets_right_shift_T_3) node _write_packets_right_shift_T_5 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_6 = sub(UInt<5>(0h10), _write_packets_right_shift_T_5) node _write_packets_right_shift_T_7 = tail(_write_packets_right_shift_T_6, 1) node write_packets_right_shift = mux(_write_packets_right_shift_T_4, _write_packets_right_shift_T_7, UInt<1>(0h0)) node write_packets_too_early = geq(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_too_late_T = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late = leq(_write_packets_too_late_T, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T = or(write_packets_too_early, write_packets_too_late) node _write_packets_packet_bytes_written_per_beat_0_T_1 = add(write_packets_left_shift, write_packets_right_shift) node _write_packets_packet_bytes_written_per_beat_0_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_1) node _write_packets_packet_bytes_written_per_beat_0_T_3 = tail(_write_packets_packet_bytes_written_per_beat_0_T_2, 1) node _write_packets_packet_bytes_written_per_beat_0_T_4 = mux(_write_packets_packet_bytes_written_per_beat_0_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_3) connect write_packets_0.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_4 node _write_packets_left_shift_T_5 = geq(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_6 = lt(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_7 = and(_write_packets_left_shift_T_5, _write_packets_left_shift_T_6) node _write_packets_left_shift_T_8 = sub(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_9 = tail(_write_packets_left_shift_T_8, 1) node write_packets_left_shift_1 = mux(_write_packets_left_shift_T_7, _write_packets_left_shift_T_9, UInt<1>(0h0)) node _write_packets_right_shift_T_8 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_9 = geq(_write_packets_right_shift_T_8, UInt<5>(0h10)) node _write_packets_right_shift_T_10 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_11 = lt(_write_packets_right_shift_T_10, UInt<6>(0h20)) node _write_packets_right_shift_T_12 = and(_write_packets_right_shift_T_9, _write_packets_right_shift_T_11) node _write_packets_right_shift_T_13 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_14 = sub(UInt<6>(0h20), _write_packets_right_shift_T_13) node _write_packets_right_shift_T_15 = tail(_write_packets_right_shift_T_14, 1) node write_packets_right_shift_1 = mux(_write_packets_right_shift_T_12, _write_packets_right_shift_T_15, UInt<1>(0h0)) node write_packets_too_early_1 = geq(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_too_late_T_1 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_1 = leq(_write_packets_too_late_T_1, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T = or(write_packets_too_early_1, write_packets_too_late_1) node _write_packets_packet_bytes_written_per_beat_1_T_1 = add(write_packets_left_shift_1, write_packets_right_shift_1) node _write_packets_packet_bytes_written_per_beat_1_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_1) node _write_packets_packet_bytes_written_per_beat_1_T_3 = tail(_write_packets_packet_bytes_written_per_beat_1_T_2, 1) node _write_packets_packet_bytes_written_per_beat_1_T_4 = mux(_write_packets_packet_bytes_written_per_beat_1_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_3) connect write_packets_0.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_4 node _write_packets_left_shift_T_10 = geq(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_11 = lt(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_12 = and(_write_packets_left_shift_T_10, _write_packets_left_shift_T_11) node _write_packets_left_shift_T_13 = sub(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_14 = tail(_write_packets_left_shift_T_13, 1) node write_packets_left_shift_2 = mux(_write_packets_left_shift_T_12, _write_packets_left_shift_T_14, UInt<1>(0h0)) node _write_packets_right_shift_T_16 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_17 = geq(_write_packets_right_shift_T_16, UInt<6>(0h20)) node _write_packets_right_shift_T_18 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_19 = lt(_write_packets_right_shift_T_18, UInt<6>(0h30)) node _write_packets_right_shift_T_20 = and(_write_packets_right_shift_T_17, _write_packets_right_shift_T_19) node _write_packets_right_shift_T_21 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_22 = sub(UInt<6>(0h30), _write_packets_right_shift_T_21) node _write_packets_right_shift_T_23 = tail(_write_packets_right_shift_T_22, 1) node write_packets_right_shift_2 = mux(_write_packets_right_shift_T_20, _write_packets_right_shift_T_23, UInt<1>(0h0)) node write_packets_too_early_2 = geq(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_too_late_T_2 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_2 = leq(_write_packets_too_late_T_2, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T = or(write_packets_too_early_2, write_packets_too_late_2) node _write_packets_packet_bytes_written_per_beat_2_T_1 = add(write_packets_left_shift_2, write_packets_right_shift_2) node _write_packets_packet_bytes_written_per_beat_2_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_1) node _write_packets_packet_bytes_written_per_beat_2_T_3 = tail(_write_packets_packet_bytes_written_per_beat_2_T_2, 1) node _write_packets_packet_bytes_written_per_beat_2_T_4 = mux(_write_packets_packet_bytes_written_per_beat_2_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_3) connect write_packets_0.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_4 node _write_packets_left_shift_T_15 = geq(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_16 = lt(write_packets_vaddr_offset, UInt<7>(0h40)) node _write_packets_left_shift_T_17 = and(_write_packets_left_shift_T_15, _write_packets_left_shift_T_16) node _write_packets_left_shift_T_18 = sub(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_19 = tail(_write_packets_left_shift_T_18, 1) node write_packets_left_shift_3 = mux(_write_packets_left_shift_T_17, _write_packets_left_shift_T_19, UInt<1>(0h0)) node _write_packets_right_shift_T_24 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_25 = geq(_write_packets_right_shift_T_24, UInt<6>(0h30)) node _write_packets_right_shift_T_26 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_27 = lt(_write_packets_right_shift_T_26, UInt<7>(0h40)) node _write_packets_right_shift_T_28 = and(_write_packets_right_shift_T_25, _write_packets_right_shift_T_27) node _write_packets_right_shift_T_29 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_30 = sub(UInt<7>(0h40), _write_packets_right_shift_T_29) node _write_packets_right_shift_T_31 = tail(_write_packets_right_shift_T_30, 1) node write_packets_right_shift_3 = mux(_write_packets_right_shift_T_28, _write_packets_right_shift_T_31, UInt<1>(0h0)) node write_packets_too_early_3 = geq(write_packets_vaddr_offset, UInt<7>(0h40)) node _write_packets_too_late_T_3 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_3 = leq(_write_packets_too_late_T_3, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T = or(write_packets_too_early_3, write_packets_too_late_3) node _write_packets_packet_bytes_written_per_beat_3_T_1 = add(write_packets_left_shift_3, write_packets_right_shift_3) node _write_packets_packet_bytes_written_per_beat_3_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_1) node _write_packets_packet_bytes_written_per_beat_3_T_3 = tail(_write_packets_packet_bytes_written_per_beat_3_T_2, 1) node _write_packets_packet_bytes_written_per_beat_3_T_4 = mux(_write_packets_packet_bytes_written_per_beat_3_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_3) connect write_packets_0.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_4 node _write_packets_vaddr_aligned_to_size_T_1 = bits(req.vaddr, 38, 5) node write_packets_vaddr_aligned_to_size_1 = cat(_write_packets_vaddr_aligned_to_size_T_1, UInt<5>(0h0)) node write_packets_vaddr_offset_1 = bits(req.vaddr, 4, 0) node _write_packets_mask_T_256 = geq(UInt<1>(0h0), write_packets_vaddr_offset_1) node _write_packets_mask_T_257 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_258 = lt(UInt<1>(0h0), _write_packets_mask_T_257) node _write_packets_mask_T_259 = and(_write_packets_mask_T_256, _write_packets_mask_T_258) node write_packets_mask_0_1 = and(_write_packets_mask_T_259, UInt<1>(0h1)) node _write_packets_mask_T_260 = geq(UInt<1>(0h1), write_packets_vaddr_offset_1) node _write_packets_mask_T_261 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_262 = lt(UInt<1>(0h1), _write_packets_mask_T_261) node _write_packets_mask_T_263 = and(_write_packets_mask_T_260, _write_packets_mask_T_262) node write_packets_mask_1_1 = and(_write_packets_mask_T_263, UInt<1>(0h1)) node _write_packets_mask_T_264 = geq(UInt<2>(0h2), write_packets_vaddr_offset_1) node _write_packets_mask_T_265 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_266 = lt(UInt<2>(0h2), _write_packets_mask_T_265) node _write_packets_mask_T_267 = and(_write_packets_mask_T_264, _write_packets_mask_T_266) node write_packets_mask_2_1 = and(_write_packets_mask_T_267, UInt<1>(0h1)) node _write_packets_mask_T_268 = geq(UInt<2>(0h3), write_packets_vaddr_offset_1) node _write_packets_mask_T_269 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_270 = lt(UInt<2>(0h3), _write_packets_mask_T_269) node _write_packets_mask_T_271 = and(_write_packets_mask_T_268, _write_packets_mask_T_270) node write_packets_mask_3_1 = and(_write_packets_mask_T_271, UInt<1>(0h1)) node _write_packets_mask_T_272 = geq(UInt<3>(0h4), write_packets_vaddr_offset_1) node _write_packets_mask_T_273 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_274 = lt(UInt<3>(0h4), _write_packets_mask_T_273) node _write_packets_mask_T_275 = and(_write_packets_mask_T_272, _write_packets_mask_T_274) node write_packets_mask_4_1 = and(_write_packets_mask_T_275, UInt<1>(0h1)) node _write_packets_mask_T_276 = geq(UInt<3>(0h5), write_packets_vaddr_offset_1) node _write_packets_mask_T_277 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_278 = lt(UInt<3>(0h5), _write_packets_mask_T_277) node _write_packets_mask_T_279 = and(_write_packets_mask_T_276, _write_packets_mask_T_278) node write_packets_mask_5_1 = and(_write_packets_mask_T_279, UInt<1>(0h1)) node _write_packets_mask_T_280 = geq(UInt<3>(0h6), write_packets_vaddr_offset_1) node _write_packets_mask_T_281 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_282 = lt(UInt<3>(0h6), _write_packets_mask_T_281) node _write_packets_mask_T_283 = and(_write_packets_mask_T_280, _write_packets_mask_T_282) node write_packets_mask_6_1 = and(_write_packets_mask_T_283, UInt<1>(0h1)) node _write_packets_mask_T_284 = geq(UInt<3>(0h7), write_packets_vaddr_offset_1) node _write_packets_mask_T_285 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_286 = lt(UInt<3>(0h7), _write_packets_mask_T_285) node _write_packets_mask_T_287 = and(_write_packets_mask_T_284, _write_packets_mask_T_286) node write_packets_mask_7_1 = and(_write_packets_mask_T_287, UInt<1>(0h1)) node _write_packets_mask_T_288 = geq(UInt<4>(0h8), write_packets_vaddr_offset_1) node _write_packets_mask_T_289 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_290 = lt(UInt<4>(0h8), _write_packets_mask_T_289) node _write_packets_mask_T_291 = and(_write_packets_mask_T_288, _write_packets_mask_T_290) node write_packets_mask_8_1 = and(_write_packets_mask_T_291, UInt<1>(0h1)) node _write_packets_mask_T_292 = geq(UInt<4>(0h9), write_packets_vaddr_offset_1) node _write_packets_mask_T_293 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_294 = lt(UInt<4>(0h9), _write_packets_mask_T_293) node _write_packets_mask_T_295 = and(_write_packets_mask_T_292, _write_packets_mask_T_294) node write_packets_mask_9_1 = and(_write_packets_mask_T_295, UInt<1>(0h1)) node _write_packets_mask_T_296 = geq(UInt<4>(0ha), write_packets_vaddr_offset_1) node _write_packets_mask_T_297 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_298 = lt(UInt<4>(0ha), _write_packets_mask_T_297) node _write_packets_mask_T_299 = and(_write_packets_mask_T_296, _write_packets_mask_T_298) node write_packets_mask_10_1 = and(_write_packets_mask_T_299, UInt<1>(0h1)) node _write_packets_mask_T_300 = geq(UInt<4>(0hb), write_packets_vaddr_offset_1) node _write_packets_mask_T_301 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_302 = lt(UInt<4>(0hb), _write_packets_mask_T_301) node _write_packets_mask_T_303 = and(_write_packets_mask_T_300, _write_packets_mask_T_302) node write_packets_mask_11_1 = and(_write_packets_mask_T_303, UInt<1>(0h1)) node _write_packets_mask_T_304 = geq(UInt<4>(0hc), write_packets_vaddr_offset_1) node _write_packets_mask_T_305 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_306 = lt(UInt<4>(0hc), _write_packets_mask_T_305) node _write_packets_mask_T_307 = and(_write_packets_mask_T_304, _write_packets_mask_T_306) node write_packets_mask_12_1 = and(_write_packets_mask_T_307, UInt<1>(0h1)) node _write_packets_mask_T_308 = geq(UInt<4>(0hd), write_packets_vaddr_offset_1) node _write_packets_mask_T_309 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_310 = lt(UInt<4>(0hd), _write_packets_mask_T_309) node _write_packets_mask_T_311 = and(_write_packets_mask_T_308, _write_packets_mask_T_310) node write_packets_mask_13_1 = and(_write_packets_mask_T_311, UInt<1>(0h1)) node _write_packets_mask_T_312 = geq(UInt<4>(0he), write_packets_vaddr_offset_1) node _write_packets_mask_T_313 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_314 = lt(UInt<4>(0he), _write_packets_mask_T_313) node _write_packets_mask_T_315 = and(_write_packets_mask_T_312, _write_packets_mask_T_314) node write_packets_mask_14_1 = and(_write_packets_mask_T_315, UInt<1>(0h1)) node _write_packets_mask_T_316 = geq(UInt<4>(0hf), write_packets_vaddr_offset_1) node _write_packets_mask_T_317 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_318 = lt(UInt<4>(0hf), _write_packets_mask_T_317) node _write_packets_mask_T_319 = and(_write_packets_mask_T_316, _write_packets_mask_T_318) node write_packets_mask_15_1 = and(_write_packets_mask_T_319, UInt<1>(0h1)) node _write_packets_mask_T_320 = geq(UInt<5>(0h10), write_packets_vaddr_offset_1) node _write_packets_mask_T_321 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_322 = lt(UInt<5>(0h10), _write_packets_mask_T_321) node _write_packets_mask_T_323 = and(_write_packets_mask_T_320, _write_packets_mask_T_322) node write_packets_mask_16_1 = and(_write_packets_mask_T_323, UInt<1>(0h1)) node _write_packets_mask_T_324 = geq(UInt<5>(0h11), write_packets_vaddr_offset_1) node _write_packets_mask_T_325 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_326 = lt(UInt<5>(0h11), _write_packets_mask_T_325) node _write_packets_mask_T_327 = and(_write_packets_mask_T_324, _write_packets_mask_T_326) node write_packets_mask_17_1 = and(_write_packets_mask_T_327, UInt<1>(0h1)) node _write_packets_mask_T_328 = geq(UInt<5>(0h12), write_packets_vaddr_offset_1) node _write_packets_mask_T_329 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_330 = lt(UInt<5>(0h12), _write_packets_mask_T_329) node _write_packets_mask_T_331 = and(_write_packets_mask_T_328, _write_packets_mask_T_330) node write_packets_mask_18_1 = and(_write_packets_mask_T_331, UInt<1>(0h1)) node _write_packets_mask_T_332 = geq(UInt<5>(0h13), write_packets_vaddr_offset_1) node _write_packets_mask_T_333 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_334 = lt(UInt<5>(0h13), _write_packets_mask_T_333) node _write_packets_mask_T_335 = and(_write_packets_mask_T_332, _write_packets_mask_T_334) node write_packets_mask_19_1 = and(_write_packets_mask_T_335, UInt<1>(0h1)) node _write_packets_mask_T_336 = geq(UInt<5>(0h14), write_packets_vaddr_offset_1) node _write_packets_mask_T_337 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_338 = lt(UInt<5>(0h14), _write_packets_mask_T_337) node _write_packets_mask_T_339 = and(_write_packets_mask_T_336, _write_packets_mask_T_338) node write_packets_mask_20_1 = and(_write_packets_mask_T_339, UInt<1>(0h1)) node _write_packets_mask_T_340 = geq(UInt<5>(0h15), write_packets_vaddr_offset_1) node _write_packets_mask_T_341 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_342 = lt(UInt<5>(0h15), _write_packets_mask_T_341) node _write_packets_mask_T_343 = and(_write_packets_mask_T_340, _write_packets_mask_T_342) node write_packets_mask_21_1 = and(_write_packets_mask_T_343, UInt<1>(0h1)) node _write_packets_mask_T_344 = geq(UInt<5>(0h16), write_packets_vaddr_offset_1) node _write_packets_mask_T_345 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_346 = lt(UInt<5>(0h16), _write_packets_mask_T_345) node _write_packets_mask_T_347 = and(_write_packets_mask_T_344, _write_packets_mask_T_346) node write_packets_mask_22_1 = and(_write_packets_mask_T_347, UInt<1>(0h1)) node _write_packets_mask_T_348 = geq(UInt<5>(0h17), write_packets_vaddr_offset_1) node _write_packets_mask_T_349 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_350 = lt(UInt<5>(0h17), _write_packets_mask_T_349) node _write_packets_mask_T_351 = and(_write_packets_mask_T_348, _write_packets_mask_T_350) node write_packets_mask_23_1 = and(_write_packets_mask_T_351, UInt<1>(0h1)) node _write_packets_mask_T_352 = geq(UInt<5>(0h18), write_packets_vaddr_offset_1) node _write_packets_mask_T_353 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_354 = lt(UInt<5>(0h18), _write_packets_mask_T_353) node _write_packets_mask_T_355 = and(_write_packets_mask_T_352, _write_packets_mask_T_354) node write_packets_mask_24_1 = and(_write_packets_mask_T_355, UInt<1>(0h1)) node _write_packets_mask_T_356 = geq(UInt<5>(0h19), write_packets_vaddr_offset_1) node _write_packets_mask_T_357 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_358 = lt(UInt<5>(0h19), _write_packets_mask_T_357) node _write_packets_mask_T_359 = and(_write_packets_mask_T_356, _write_packets_mask_T_358) node write_packets_mask_25_1 = and(_write_packets_mask_T_359, UInt<1>(0h1)) node _write_packets_mask_T_360 = geq(UInt<5>(0h1a), write_packets_vaddr_offset_1) node _write_packets_mask_T_361 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_362 = lt(UInt<5>(0h1a), _write_packets_mask_T_361) node _write_packets_mask_T_363 = and(_write_packets_mask_T_360, _write_packets_mask_T_362) node write_packets_mask_26_1 = and(_write_packets_mask_T_363, UInt<1>(0h1)) node _write_packets_mask_T_364 = geq(UInt<5>(0h1b), write_packets_vaddr_offset_1) node _write_packets_mask_T_365 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_366 = lt(UInt<5>(0h1b), _write_packets_mask_T_365) node _write_packets_mask_T_367 = and(_write_packets_mask_T_364, _write_packets_mask_T_366) node write_packets_mask_27_1 = and(_write_packets_mask_T_367, UInt<1>(0h1)) node _write_packets_mask_T_368 = geq(UInt<5>(0h1c), write_packets_vaddr_offset_1) node _write_packets_mask_T_369 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_370 = lt(UInt<5>(0h1c), _write_packets_mask_T_369) node _write_packets_mask_T_371 = and(_write_packets_mask_T_368, _write_packets_mask_T_370) node write_packets_mask_28_1 = and(_write_packets_mask_T_371, UInt<1>(0h1)) node _write_packets_mask_T_372 = geq(UInt<5>(0h1d), write_packets_vaddr_offset_1) node _write_packets_mask_T_373 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_374 = lt(UInt<5>(0h1d), _write_packets_mask_T_373) node _write_packets_mask_T_375 = and(_write_packets_mask_T_372, _write_packets_mask_T_374) node write_packets_mask_29_1 = and(_write_packets_mask_T_375, UInt<1>(0h1)) node _write_packets_mask_T_376 = geq(UInt<5>(0h1e), write_packets_vaddr_offset_1) node _write_packets_mask_T_377 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_378 = lt(UInt<5>(0h1e), _write_packets_mask_T_377) node _write_packets_mask_T_379 = and(_write_packets_mask_T_376, _write_packets_mask_T_378) node write_packets_mask_30_1 = and(_write_packets_mask_T_379, UInt<1>(0h1)) node _write_packets_mask_T_380 = geq(UInt<5>(0h1f), write_packets_vaddr_offset_1) node _write_packets_mask_T_381 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_382 = lt(UInt<5>(0h1f), _write_packets_mask_T_381) node _write_packets_mask_T_383 = and(_write_packets_mask_T_380, _write_packets_mask_T_382) node write_packets_mask_31_1 = and(_write_packets_mask_T_383, UInt<1>(0h1)) node _write_packets_mask_T_384 = geq(UInt<6>(0h20), write_packets_vaddr_offset_1) node _write_packets_mask_T_385 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_386 = lt(UInt<6>(0h20), _write_packets_mask_T_385) node _write_packets_mask_T_387 = and(_write_packets_mask_T_384, _write_packets_mask_T_386) node write_packets_mask_32_1 = and(_write_packets_mask_T_387, UInt<1>(0h0)) node _write_packets_mask_T_388 = geq(UInt<6>(0h21), write_packets_vaddr_offset_1) node _write_packets_mask_T_389 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_390 = lt(UInt<6>(0h21), _write_packets_mask_T_389) node _write_packets_mask_T_391 = and(_write_packets_mask_T_388, _write_packets_mask_T_390) node write_packets_mask_33_1 = and(_write_packets_mask_T_391, UInt<1>(0h0)) node _write_packets_mask_T_392 = geq(UInt<6>(0h22), write_packets_vaddr_offset_1) node _write_packets_mask_T_393 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_394 = lt(UInt<6>(0h22), _write_packets_mask_T_393) node _write_packets_mask_T_395 = and(_write_packets_mask_T_392, _write_packets_mask_T_394) node write_packets_mask_34_1 = and(_write_packets_mask_T_395, UInt<1>(0h0)) node _write_packets_mask_T_396 = geq(UInt<6>(0h23), write_packets_vaddr_offset_1) node _write_packets_mask_T_397 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_398 = lt(UInt<6>(0h23), _write_packets_mask_T_397) node _write_packets_mask_T_399 = and(_write_packets_mask_T_396, _write_packets_mask_T_398) node write_packets_mask_35_1 = and(_write_packets_mask_T_399, UInt<1>(0h0)) node _write_packets_mask_T_400 = geq(UInt<6>(0h24), write_packets_vaddr_offset_1) node _write_packets_mask_T_401 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_402 = lt(UInt<6>(0h24), _write_packets_mask_T_401) node _write_packets_mask_T_403 = and(_write_packets_mask_T_400, _write_packets_mask_T_402) node write_packets_mask_36_1 = and(_write_packets_mask_T_403, UInt<1>(0h0)) node _write_packets_mask_T_404 = geq(UInt<6>(0h25), write_packets_vaddr_offset_1) node _write_packets_mask_T_405 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_406 = lt(UInt<6>(0h25), _write_packets_mask_T_405) node _write_packets_mask_T_407 = and(_write_packets_mask_T_404, _write_packets_mask_T_406) node write_packets_mask_37_1 = and(_write_packets_mask_T_407, UInt<1>(0h0)) node _write_packets_mask_T_408 = geq(UInt<6>(0h26), write_packets_vaddr_offset_1) node _write_packets_mask_T_409 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_410 = lt(UInt<6>(0h26), _write_packets_mask_T_409) node _write_packets_mask_T_411 = and(_write_packets_mask_T_408, _write_packets_mask_T_410) node write_packets_mask_38_1 = and(_write_packets_mask_T_411, UInt<1>(0h0)) node _write_packets_mask_T_412 = geq(UInt<6>(0h27), write_packets_vaddr_offset_1) node _write_packets_mask_T_413 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_414 = lt(UInt<6>(0h27), _write_packets_mask_T_413) node _write_packets_mask_T_415 = and(_write_packets_mask_T_412, _write_packets_mask_T_414) node write_packets_mask_39_1 = and(_write_packets_mask_T_415, UInt<1>(0h0)) node _write_packets_mask_T_416 = geq(UInt<6>(0h28), write_packets_vaddr_offset_1) node _write_packets_mask_T_417 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_418 = lt(UInt<6>(0h28), _write_packets_mask_T_417) node _write_packets_mask_T_419 = and(_write_packets_mask_T_416, _write_packets_mask_T_418) node write_packets_mask_40_1 = and(_write_packets_mask_T_419, UInt<1>(0h0)) node _write_packets_mask_T_420 = geq(UInt<6>(0h29), write_packets_vaddr_offset_1) node _write_packets_mask_T_421 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_422 = lt(UInt<6>(0h29), _write_packets_mask_T_421) node _write_packets_mask_T_423 = and(_write_packets_mask_T_420, _write_packets_mask_T_422) node write_packets_mask_41_1 = and(_write_packets_mask_T_423, UInt<1>(0h0)) node _write_packets_mask_T_424 = geq(UInt<6>(0h2a), write_packets_vaddr_offset_1) node _write_packets_mask_T_425 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_426 = lt(UInt<6>(0h2a), _write_packets_mask_T_425) node _write_packets_mask_T_427 = and(_write_packets_mask_T_424, _write_packets_mask_T_426) node write_packets_mask_42_1 = and(_write_packets_mask_T_427, UInt<1>(0h0)) node _write_packets_mask_T_428 = geq(UInt<6>(0h2b), write_packets_vaddr_offset_1) node _write_packets_mask_T_429 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_430 = lt(UInt<6>(0h2b), _write_packets_mask_T_429) node _write_packets_mask_T_431 = and(_write_packets_mask_T_428, _write_packets_mask_T_430) node write_packets_mask_43_1 = and(_write_packets_mask_T_431, UInt<1>(0h0)) node _write_packets_mask_T_432 = geq(UInt<6>(0h2c), write_packets_vaddr_offset_1) node _write_packets_mask_T_433 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_434 = lt(UInt<6>(0h2c), _write_packets_mask_T_433) node _write_packets_mask_T_435 = and(_write_packets_mask_T_432, _write_packets_mask_T_434) node write_packets_mask_44_1 = and(_write_packets_mask_T_435, UInt<1>(0h0)) node _write_packets_mask_T_436 = geq(UInt<6>(0h2d), write_packets_vaddr_offset_1) node _write_packets_mask_T_437 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_438 = lt(UInt<6>(0h2d), _write_packets_mask_T_437) node _write_packets_mask_T_439 = and(_write_packets_mask_T_436, _write_packets_mask_T_438) node write_packets_mask_45_1 = and(_write_packets_mask_T_439, UInt<1>(0h0)) node _write_packets_mask_T_440 = geq(UInt<6>(0h2e), write_packets_vaddr_offset_1) node _write_packets_mask_T_441 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_442 = lt(UInt<6>(0h2e), _write_packets_mask_T_441) node _write_packets_mask_T_443 = and(_write_packets_mask_T_440, _write_packets_mask_T_442) node write_packets_mask_46_1 = and(_write_packets_mask_T_443, UInt<1>(0h0)) node _write_packets_mask_T_444 = geq(UInt<6>(0h2f), write_packets_vaddr_offset_1) node _write_packets_mask_T_445 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_446 = lt(UInt<6>(0h2f), _write_packets_mask_T_445) node _write_packets_mask_T_447 = and(_write_packets_mask_T_444, _write_packets_mask_T_446) node write_packets_mask_47_1 = and(_write_packets_mask_T_447, UInt<1>(0h0)) node _write_packets_mask_T_448 = geq(UInt<6>(0h30), write_packets_vaddr_offset_1) node _write_packets_mask_T_449 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_450 = lt(UInt<6>(0h30), _write_packets_mask_T_449) node _write_packets_mask_T_451 = and(_write_packets_mask_T_448, _write_packets_mask_T_450) node write_packets_mask_48_1 = and(_write_packets_mask_T_451, UInt<1>(0h0)) node _write_packets_mask_T_452 = geq(UInt<6>(0h31), write_packets_vaddr_offset_1) node _write_packets_mask_T_453 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_454 = lt(UInt<6>(0h31), _write_packets_mask_T_453) node _write_packets_mask_T_455 = and(_write_packets_mask_T_452, _write_packets_mask_T_454) node write_packets_mask_49_1 = and(_write_packets_mask_T_455, UInt<1>(0h0)) node _write_packets_mask_T_456 = geq(UInt<6>(0h32), write_packets_vaddr_offset_1) node _write_packets_mask_T_457 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_458 = lt(UInt<6>(0h32), _write_packets_mask_T_457) node _write_packets_mask_T_459 = and(_write_packets_mask_T_456, _write_packets_mask_T_458) node write_packets_mask_50_1 = and(_write_packets_mask_T_459, UInt<1>(0h0)) node _write_packets_mask_T_460 = geq(UInt<6>(0h33), write_packets_vaddr_offset_1) node _write_packets_mask_T_461 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_462 = lt(UInt<6>(0h33), _write_packets_mask_T_461) node _write_packets_mask_T_463 = and(_write_packets_mask_T_460, _write_packets_mask_T_462) node write_packets_mask_51_1 = and(_write_packets_mask_T_463, UInt<1>(0h0)) node _write_packets_mask_T_464 = geq(UInt<6>(0h34), write_packets_vaddr_offset_1) node _write_packets_mask_T_465 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_466 = lt(UInt<6>(0h34), _write_packets_mask_T_465) node _write_packets_mask_T_467 = and(_write_packets_mask_T_464, _write_packets_mask_T_466) node write_packets_mask_52_1 = and(_write_packets_mask_T_467, UInt<1>(0h0)) node _write_packets_mask_T_468 = geq(UInt<6>(0h35), write_packets_vaddr_offset_1) node _write_packets_mask_T_469 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_470 = lt(UInt<6>(0h35), _write_packets_mask_T_469) node _write_packets_mask_T_471 = and(_write_packets_mask_T_468, _write_packets_mask_T_470) node write_packets_mask_53_1 = and(_write_packets_mask_T_471, UInt<1>(0h0)) node _write_packets_mask_T_472 = geq(UInt<6>(0h36), write_packets_vaddr_offset_1) node _write_packets_mask_T_473 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_474 = lt(UInt<6>(0h36), _write_packets_mask_T_473) node _write_packets_mask_T_475 = and(_write_packets_mask_T_472, _write_packets_mask_T_474) node write_packets_mask_54_1 = and(_write_packets_mask_T_475, UInt<1>(0h0)) node _write_packets_mask_T_476 = geq(UInt<6>(0h37), write_packets_vaddr_offset_1) node _write_packets_mask_T_477 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_478 = lt(UInt<6>(0h37), _write_packets_mask_T_477) node _write_packets_mask_T_479 = and(_write_packets_mask_T_476, _write_packets_mask_T_478) node write_packets_mask_55_1 = and(_write_packets_mask_T_479, UInt<1>(0h0)) node _write_packets_mask_T_480 = geq(UInt<6>(0h38), write_packets_vaddr_offset_1) node _write_packets_mask_T_481 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_482 = lt(UInt<6>(0h38), _write_packets_mask_T_481) node _write_packets_mask_T_483 = and(_write_packets_mask_T_480, _write_packets_mask_T_482) node write_packets_mask_56_1 = and(_write_packets_mask_T_483, UInt<1>(0h0)) node _write_packets_mask_T_484 = geq(UInt<6>(0h39), write_packets_vaddr_offset_1) node _write_packets_mask_T_485 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_486 = lt(UInt<6>(0h39), _write_packets_mask_T_485) node _write_packets_mask_T_487 = and(_write_packets_mask_T_484, _write_packets_mask_T_486) node write_packets_mask_57_1 = and(_write_packets_mask_T_487, UInt<1>(0h0)) node _write_packets_mask_T_488 = geq(UInt<6>(0h3a), write_packets_vaddr_offset_1) node _write_packets_mask_T_489 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_490 = lt(UInt<6>(0h3a), _write_packets_mask_T_489) node _write_packets_mask_T_491 = and(_write_packets_mask_T_488, _write_packets_mask_T_490) node write_packets_mask_58_1 = and(_write_packets_mask_T_491, UInt<1>(0h0)) node _write_packets_mask_T_492 = geq(UInt<6>(0h3b), write_packets_vaddr_offset_1) node _write_packets_mask_T_493 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_494 = lt(UInt<6>(0h3b), _write_packets_mask_T_493) node _write_packets_mask_T_495 = and(_write_packets_mask_T_492, _write_packets_mask_T_494) node write_packets_mask_59_1 = and(_write_packets_mask_T_495, UInt<1>(0h0)) node _write_packets_mask_T_496 = geq(UInt<6>(0h3c), write_packets_vaddr_offset_1) node _write_packets_mask_T_497 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_498 = lt(UInt<6>(0h3c), _write_packets_mask_T_497) node _write_packets_mask_T_499 = and(_write_packets_mask_T_496, _write_packets_mask_T_498) node write_packets_mask_60_1 = and(_write_packets_mask_T_499, UInt<1>(0h0)) node _write_packets_mask_T_500 = geq(UInt<6>(0h3d), write_packets_vaddr_offset_1) node _write_packets_mask_T_501 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_502 = lt(UInt<6>(0h3d), _write_packets_mask_T_501) node _write_packets_mask_T_503 = and(_write_packets_mask_T_500, _write_packets_mask_T_502) node write_packets_mask_61_1 = and(_write_packets_mask_T_503, UInt<1>(0h0)) node _write_packets_mask_T_504 = geq(UInt<6>(0h3e), write_packets_vaddr_offset_1) node _write_packets_mask_T_505 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_506 = lt(UInt<6>(0h3e), _write_packets_mask_T_505) node _write_packets_mask_T_507 = and(_write_packets_mask_T_504, _write_packets_mask_T_506) node write_packets_mask_62_1 = and(_write_packets_mask_T_507, UInt<1>(0h0)) node _write_packets_mask_T_508 = geq(UInt<6>(0h3f), write_packets_vaddr_offset_1) node _write_packets_mask_T_509 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_510 = lt(UInt<6>(0h3f), _write_packets_mask_T_509) node _write_packets_mask_T_511 = and(_write_packets_mask_T_508, _write_packets_mask_T_510) node write_packets_mask_63_1 = and(_write_packets_mask_T_511, UInt<1>(0h0)) node _write_packets_bytes_written_T_4 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_bytes_written_T_5 = gt(_write_packets_bytes_written_T_4, UInt<6>(0h20)) node _write_packets_bytes_written_T_6 = sub(UInt<6>(0h20), write_packets_vaddr_offset_1) node _write_packets_bytes_written_T_7 = tail(_write_packets_bytes_written_T_6, 1) node write_packets_bytes_written_1 = mux(_write_packets_bytes_written_T_5, _write_packets_bytes_written_T_7, bytesLeft) wire write_packets_1 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_1.size, UInt<6>(0h20) connect write_packets_1.lg_size, UInt<3>(0h5) wire _write_packets_WIRE_5 : UInt<1>[16] connect _write_packets_WIRE_5[0], write_packets_mask_0_1 connect _write_packets_WIRE_5[1], write_packets_mask_1_1 connect _write_packets_WIRE_5[2], write_packets_mask_2_1 connect _write_packets_WIRE_5[3], write_packets_mask_3_1 connect _write_packets_WIRE_5[4], write_packets_mask_4_1 connect _write_packets_WIRE_5[5], write_packets_mask_5_1 connect _write_packets_WIRE_5[6], write_packets_mask_6_1 connect _write_packets_WIRE_5[7], write_packets_mask_7_1 connect _write_packets_WIRE_5[8], write_packets_mask_8_1 connect _write_packets_WIRE_5[9], write_packets_mask_9_1 connect _write_packets_WIRE_5[10], write_packets_mask_10_1 connect _write_packets_WIRE_5[11], write_packets_mask_11_1 connect _write_packets_WIRE_5[12], write_packets_mask_12_1 connect _write_packets_WIRE_5[13], write_packets_mask_13_1 connect _write_packets_WIRE_5[14], write_packets_mask_14_1 connect _write_packets_WIRE_5[15], write_packets_mask_15_1 wire _write_packets_WIRE_6 : UInt<1>[16] connect _write_packets_WIRE_6[0], write_packets_mask_16_1 connect _write_packets_WIRE_6[1], write_packets_mask_17_1 connect _write_packets_WIRE_6[2], write_packets_mask_18_1 connect _write_packets_WIRE_6[3], write_packets_mask_19_1 connect _write_packets_WIRE_6[4], write_packets_mask_20_1 connect _write_packets_WIRE_6[5], write_packets_mask_21_1 connect _write_packets_WIRE_6[6], write_packets_mask_22_1 connect _write_packets_WIRE_6[7], write_packets_mask_23_1 connect _write_packets_WIRE_6[8], write_packets_mask_24_1 connect _write_packets_WIRE_6[9], write_packets_mask_25_1 connect _write_packets_WIRE_6[10], write_packets_mask_26_1 connect _write_packets_WIRE_6[11], write_packets_mask_27_1 connect _write_packets_WIRE_6[12], write_packets_mask_28_1 connect _write_packets_WIRE_6[13], write_packets_mask_29_1 connect _write_packets_WIRE_6[14], write_packets_mask_30_1 connect _write_packets_WIRE_6[15], write_packets_mask_31_1 wire _write_packets_WIRE_7 : UInt<1>[16] connect _write_packets_WIRE_7[0], write_packets_mask_32_1 connect _write_packets_WIRE_7[1], write_packets_mask_33_1 connect _write_packets_WIRE_7[2], write_packets_mask_34_1 connect _write_packets_WIRE_7[3], write_packets_mask_35_1 connect _write_packets_WIRE_7[4], write_packets_mask_36_1 connect _write_packets_WIRE_7[5], write_packets_mask_37_1 connect _write_packets_WIRE_7[6], write_packets_mask_38_1 connect _write_packets_WIRE_7[7], write_packets_mask_39_1 connect _write_packets_WIRE_7[8], write_packets_mask_40_1 connect _write_packets_WIRE_7[9], write_packets_mask_41_1 connect _write_packets_WIRE_7[10], write_packets_mask_42_1 connect _write_packets_WIRE_7[11], write_packets_mask_43_1 connect _write_packets_WIRE_7[12], write_packets_mask_44_1 connect _write_packets_WIRE_7[13], write_packets_mask_45_1 connect _write_packets_WIRE_7[14], write_packets_mask_46_1 connect _write_packets_WIRE_7[15], write_packets_mask_47_1 wire _write_packets_WIRE_8 : UInt<1>[16] connect _write_packets_WIRE_8[0], write_packets_mask_48_1 connect _write_packets_WIRE_8[1], write_packets_mask_49_1 connect _write_packets_WIRE_8[2], write_packets_mask_50_1 connect _write_packets_WIRE_8[3], write_packets_mask_51_1 connect _write_packets_WIRE_8[4], write_packets_mask_52_1 connect _write_packets_WIRE_8[5], write_packets_mask_53_1 connect _write_packets_WIRE_8[6], write_packets_mask_54_1 connect _write_packets_WIRE_8[7], write_packets_mask_55_1 connect _write_packets_WIRE_8[8], write_packets_mask_56_1 connect _write_packets_WIRE_8[9], write_packets_mask_57_1 connect _write_packets_WIRE_8[10], write_packets_mask_58_1 connect _write_packets_WIRE_8[11], write_packets_mask_59_1 connect _write_packets_WIRE_8[12], write_packets_mask_60_1 connect _write_packets_WIRE_8[13], write_packets_mask_61_1 connect _write_packets_WIRE_8[14], write_packets_mask_62_1 connect _write_packets_WIRE_8[15], write_packets_mask_63_1 wire _write_packets_WIRE_9 : UInt<1>[16][4] connect _write_packets_WIRE_9[0], _write_packets_WIRE_5 connect _write_packets_WIRE_9[1], _write_packets_WIRE_6 connect _write_packets_WIRE_9[2], _write_packets_WIRE_7 connect _write_packets_WIRE_9[3], _write_packets_WIRE_8 connect write_packets_1.mask, _write_packets_WIRE_9 connect write_packets_1.vaddr, write_packets_vaddr_aligned_to_size_1 node _write_packets_packet_is_full_T_15 = and(write_packets_mask_0_1, write_packets_mask_1_1) node _write_packets_packet_is_full_T_16 = and(_write_packets_packet_is_full_T_15, write_packets_mask_2_1) node _write_packets_packet_is_full_T_17 = and(_write_packets_packet_is_full_T_16, write_packets_mask_3_1) node _write_packets_packet_is_full_T_18 = and(_write_packets_packet_is_full_T_17, write_packets_mask_4_1) node _write_packets_packet_is_full_T_19 = and(_write_packets_packet_is_full_T_18, write_packets_mask_5_1) node _write_packets_packet_is_full_T_20 = and(_write_packets_packet_is_full_T_19, write_packets_mask_6_1) node _write_packets_packet_is_full_T_21 = and(_write_packets_packet_is_full_T_20, write_packets_mask_7_1) node _write_packets_packet_is_full_T_22 = and(_write_packets_packet_is_full_T_21, write_packets_mask_8_1) node _write_packets_packet_is_full_T_23 = and(_write_packets_packet_is_full_T_22, write_packets_mask_9_1) node _write_packets_packet_is_full_T_24 = and(_write_packets_packet_is_full_T_23, write_packets_mask_10_1) node _write_packets_packet_is_full_T_25 = and(_write_packets_packet_is_full_T_24, write_packets_mask_11_1) node _write_packets_packet_is_full_T_26 = and(_write_packets_packet_is_full_T_25, write_packets_mask_12_1) node _write_packets_packet_is_full_T_27 = and(_write_packets_packet_is_full_T_26, write_packets_mask_13_1) node _write_packets_packet_is_full_T_28 = and(_write_packets_packet_is_full_T_27, write_packets_mask_14_1) node _write_packets_packet_is_full_T_29 = and(_write_packets_packet_is_full_T_28, write_packets_mask_15_1) node _write_packets_packet_is_full_T_30 = and(_write_packets_packet_is_full_T_29, write_packets_mask_16_1) node _write_packets_packet_is_full_T_31 = and(_write_packets_packet_is_full_T_30, write_packets_mask_17_1) node _write_packets_packet_is_full_T_32 = and(_write_packets_packet_is_full_T_31, write_packets_mask_18_1) node _write_packets_packet_is_full_T_33 = and(_write_packets_packet_is_full_T_32, write_packets_mask_19_1) node _write_packets_packet_is_full_T_34 = and(_write_packets_packet_is_full_T_33, write_packets_mask_20_1) node _write_packets_packet_is_full_T_35 = and(_write_packets_packet_is_full_T_34, write_packets_mask_21_1) node _write_packets_packet_is_full_T_36 = and(_write_packets_packet_is_full_T_35, write_packets_mask_22_1) node _write_packets_packet_is_full_T_37 = and(_write_packets_packet_is_full_T_36, write_packets_mask_23_1) node _write_packets_packet_is_full_T_38 = and(_write_packets_packet_is_full_T_37, write_packets_mask_24_1) node _write_packets_packet_is_full_T_39 = and(_write_packets_packet_is_full_T_38, write_packets_mask_25_1) node _write_packets_packet_is_full_T_40 = and(_write_packets_packet_is_full_T_39, write_packets_mask_26_1) node _write_packets_packet_is_full_T_41 = and(_write_packets_packet_is_full_T_40, write_packets_mask_27_1) node _write_packets_packet_is_full_T_42 = and(_write_packets_packet_is_full_T_41, write_packets_mask_28_1) node _write_packets_packet_is_full_T_43 = and(_write_packets_packet_is_full_T_42, write_packets_mask_29_1) node _write_packets_packet_is_full_T_44 = and(_write_packets_packet_is_full_T_43, write_packets_mask_30_1) node _write_packets_packet_is_full_T_45 = and(_write_packets_packet_is_full_T_44, write_packets_mask_31_1) connect write_packets_1.is_full, _write_packets_packet_is_full_T_45 connect write_packets_1.bytes_written, write_packets_bytes_written_1 node _write_packets_left_shift_T_20 = geq(write_packets_vaddr_offset_1, UInt<1>(0h0)) node _write_packets_left_shift_T_21 = lt(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_22 = and(_write_packets_left_shift_T_20, _write_packets_left_shift_T_21) node _write_packets_left_shift_T_23 = sub(write_packets_vaddr_offset_1, UInt<1>(0h0)) node _write_packets_left_shift_T_24 = tail(_write_packets_left_shift_T_23, 1) node write_packets_left_shift_4 = mux(_write_packets_left_shift_T_22, _write_packets_left_shift_T_24, UInt<1>(0h0)) node _write_packets_right_shift_T_32 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_33 = geq(_write_packets_right_shift_T_32, UInt<1>(0h0)) node _write_packets_right_shift_T_34 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_35 = lt(_write_packets_right_shift_T_34, UInt<5>(0h10)) node _write_packets_right_shift_T_36 = and(_write_packets_right_shift_T_33, _write_packets_right_shift_T_35) node _write_packets_right_shift_T_37 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_38 = sub(UInt<5>(0h10), _write_packets_right_shift_T_37) node _write_packets_right_shift_T_39 = tail(_write_packets_right_shift_T_38, 1) node write_packets_right_shift_4 = mux(_write_packets_right_shift_T_36, _write_packets_right_shift_T_39, UInt<1>(0h0)) node write_packets_too_early_4 = geq(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_too_late_T_4 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_4 = leq(_write_packets_too_late_T_4, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T_5 = or(write_packets_too_early_4, write_packets_too_late_4) node _write_packets_packet_bytes_written_per_beat_0_T_6 = add(write_packets_left_shift_4, write_packets_right_shift_4) node _write_packets_packet_bytes_written_per_beat_0_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_6) node _write_packets_packet_bytes_written_per_beat_0_T_8 = tail(_write_packets_packet_bytes_written_per_beat_0_T_7, 1) node _write_packets_packet_bytes_written_per_beat_0_T_9 = mux(_write_packets_packet_bytes_written_per_beat_0_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_8) connect write_packets_1.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_9 node _write_packets_left_shift_T_25 = geq(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_26 = lt(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_27 = and(_write_packets_left_shift_T_25, _write_packets_left_shift_T_26) node _write_packets_left_shift_T_28 = sub(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_29 = tail(_write_packets_left_shift_T_28, 1) node write_packets_left_shift_5 = mux(_write_packets_left_shift_T_27, _write_packets_left_shift_T_29, UInt<1>(0h0)) node _write_packets_right_shift_T_40 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_41 = geq(_write_packets_right_shift_T_40, UInt<5>(0h10)) node _write_packets_right_shift_T_42 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_43 = lt(_write_packets_right_shift_T_42, UInt<6>(0h20)) node _write_packets_right_shift_T_44 = and(_write_packets_right_shift_T_41, _write_packets_right_shift_T_43) node _write_packets_right_shift_T_45 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_46 = sub(UInt<6>(0h20), _write_packets_right_shift_T_45) node _write_packets_right_shift_T_47 = tail(_write_packets_right_shift_T_46, 1) node write_packets_right_shift_5 = mux(_write_packets_right_shift_T_44, _write_packets_right_shift_T_47, UInt<1>(0h0)) node write_packets_too_early_5 = geq(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_too_late_T_5 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_5 = leq(_write_packets_too_late_T_5, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T_5 = or(write_packets_too_early_5, write_packets_too_late_5) node _write_packets_packet_bytes_written_per_beat_1_T_6 = add(write_packets_left_shift_5, write_packets_right_shift_5) node _write_packets_packet_bytes_written_per_beat_1_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_6) node _write_packets_packet_bytes_written_per_beat_1_T_8 = tail(_write_packets_packet_bytes_written_per_beat_1_T_7, 1) node _write_packets_packet_bytes_written_per_beat_1_T_9 = mux(_write_packets_packet_bytes_written_per_beat_1_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_8) connect write_packets_1.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_9 node _write_packets_left_shift_T_30 = geq(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_31 = lt(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_32 = and(_write_packets_left_shift_T_30, _write_packets_left_shift_T_31) node _write_packets_left_shift_T_33 = sub(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_34 = tail(_write_packets_left_shift_T_33, 1) node write_packets_left_shift_6 = mux(_write_packets_left_shift_T_32, _write_packets_left_shift_T_34, UInt<1>(0h0)) node _write_packets_right_shift_T_48 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_49 = geq(_write_packets_right_shift_T_48, UInt<6>(0h20)) node _write_packets_right_shift_T_50 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_51 = lt(_write_packets_right_shift_T_50, UInt<6>(0h30)) node _write_packets_right_shift_T_52 = and(_write_packets_right_shift_T_49, _write_packets_right_shift_T_51) node _write_packets_right_shift_T_53 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_54 = sub(UInt<6>(0h30), _write_packets_right_shift_T_53) node _write_packets_right_shift_T_55 = tail(_write_packets_right_shift_T_54, 1) node write_packets_right_shift_6 = mux(_write_packets_right_shift_T_52, _write_packets_right_shift_T_55, UInt<1>(0h0)) node write_packets_too_early_6 = geq(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_too_late_T_6 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_6 = leq(_write_packets_too_late_T_6, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T_5 = or(write_packets_too_early_6, write_packets_too_late_6) node _write_packets_packet_bytes_written_per_beat_2_T_6 = add(write_packets_left_shift_6, write_packets_right_shift_6) node _write_packets_packet_bytes_written_per_beat_2_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_6) node _write_packets_packet_bytes_written_per_beat_2_T_8 = tail(_write_packets_packet_bytes_written_per_beat_2_T_7, 1) node _write_packets_packet_bytes_written_per_beat_2_T_9 = mux(_write_packets_packet_bytes_written_per_beat_2_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_8) connect write_packets_1.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_9 node _write_packets_left_shift_T_35 = geq(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_36 = lt(write_packets_vaddr_offset_1, UInt<7>(0h40)) node _write_packets_left_shift_T_37 = and(_write_packets_left_shift_T_35, _write_packets_left_shift_T_36) node _write_packets_left_shift_T_38 = sub(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_39 = tail(_write_packets_left_shift_T_38, 1) node write_packets_left_shift_7 = mux(_write_packets_left_shift_T_37, _write_packets_left_shift_T_39, UInt<1>(0h0)) node _write_packets_right_shift_T_56 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_57 = geq(_write_packets_right_shift_T_56, UInt<6>(0h30)) node _write_packets_right_shift_T_58 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_59 = lt(_write_packets_right_shift_T_58, UInt<7>(0h40)) node _write_packets_right_shift_T_60 = and(_write_packets_right_shift_T_57, _write_packets_right_shift_T_59) node _write_packets_right_shift_T_61 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_62 = sub(UInt<7>(0h40), _write_packets_right_shift_T_61) node _write_packets_right_shift_T_63 = tail(_write_packets_right_shift_T_62, 1) node write_packets_right_shift_7 = mux(_write_packets_right_shift_T_60, _write_packets_right_shift_T_63, UInt<1>(0h0)) node write_packets_too_early_7 = geq(write_packets_vaddr_offset_1, UInt<7>(0h40)) node _write_packets_too_late_T_7 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_7 = leq(_write_packets_too_late_T_7, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T_5 = or(write_packets_too_early_7, write_packets_too_late_7) node _write_packets_packet_bytes_written_per_beat_3_T_6 = add(write_packets_left_shift_7, write_packets_right_shift_7) node _write_packets_packet_bytes_written_per_beat_3_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_6) node _write_packets_packet_bytes_written_per_beat_3_T_8 = tail(_write_packets_packet_bytes_written_per_beat_3_T_7, 1) node _write_packets_packet_bytes_written_per_beat_3_T_9 = mux(_write_packets_packet_bytes_written_per_beat_3_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_8) connect write_packets_1.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_9 node _write_packets_vaddr_aligned_to_size_T_2 = bits(req.vaddr, 38, 6) node write_packets_vaddr_aligned_to_size_2 = cat(_write_packets_vaddr_aligned_to_size_T_2, UInt<6>(0h0)) node write_packets_vaddr_offset_2 = bits(req.vaddr, 5, 0) node _write_packets_mask_T_512 = geq(UInt<1>(0h0), write_packets_vaddr_offset_2) node _write_packets_mask_T_513 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_514 = lt(UInt<1>(0h0), _write_packets_mask_T_513) node _write_packets_mask_T_515 = and(_write_packets_mask_T_512, _write_packets_mask_T_514) node write_packets_mask_0_2 = and(_write_packets_mask_T_515, UInt<1>(0h1)) node _write_packets_mask_T_516 = geq(UInt<1>(0h1), write_packets_vaddr_offset_2) node _write_packets_mask_T_517 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_518 = lt(UInt<1>(0h1), _write_packets_mask_T_517) node _write_packets_mask_T_519 = and(_write_packets_mask_T_516, _write_packets_mask_T_518) node write_packets_mask_1_2 = and(_write_packets_mask_T_519, UInt<1>(0h1)) node _write_packets_mask_T_520 = geq(UInt<2>(0h2), write_packets_vaddr_offset_2) node _write_packets_mask_T_521 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_522 = lt(UInt<2>(0h2), _write_packets_mask_T_521) node _write_packets_mask_T_523 = and(_write_packets_mask_T_520, _write_packets_mask_T_522) node write_packets_mask_2_2 = and(_write_packets_mask_T_523, UInt<1>(0h1)) node _write_packets_mask_T_524 = geq(UInt<2>(0h3), write_packets_vaddr_offset_2) node _write_packets_mask_T_525 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_526 = lt(UInt<2>(0h3), _write_packets_mask_T_525) node _write_packets_mask_T_527 = and(_write_packets_mask_T_524, _write_packets_mask_T_526) node write_packets_mask_3_2 = and(_write_packets_mask_T_527, UInt<1>(0h1)) node _write_packets_mask_T_528 = geq(UInt<3>(0h4), write_packets_vaddr_offset_2) node _write_packets_mask_T_529 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_530 = lt(UInt<3>(0h4), _write_packets_mask_T_529) node _write_packets_mask_T_531 = and(_write_packets_mask_T_528, _write_packets_mask_T_530) node write_packets_mask_4_2 = and(_write_packets_mask_T_531, UInt<1>(0h1)) node _write_packets_mask_T_532 = geq(UInt<3>(0h5), write_packets_vaddr_offset_2) node _write_packets_mask_T_533 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_534 = lt(UInt<3>(0h5), _write_packets_mask_T_533) node _write_packets_mask_T_535 = and(_write_packets_mask_T_532, _write_packets_mask_T_534) node write_packets_mask_5_2 = and(_write_packets_mask_T_535, UInt<1>(0h1)) node _write_packets_mask_T_536 = geq(UInt<3>(0h6), write_packets_vaddr_offset_2) node _write_packets_mask_T_537 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_538 = lt(UInt<3>(0h6), _write_packets_mask_T_537) node _write_packets_mask_T_539 = and(_write_packets_mask_T_536, _write_packets_mask_T_538) node write_packets_mask_6_2 = and(_write_packets_mask_T_539, UInt<1>(0h1)) node _write_packets_mask_T_540 = geq(UInt<3>(0h7), write_packets_vaddr_offset_2) node _write_packets_mask_T_541 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_542 = lt(UInt<3>(0h7), _write_packets_mask_T_541) node _write_packets_mask_T_543 = and(_write_packets_mask_T_540, _write_packets_mask_T_542) node write_packets_mask_7_2 = and(_write_packets_mask_T_543, UInt<1>(0h1)) node _write_packets_mask_T_544 = geq(UInt<4>(0h8), write_packets_vaddr_offset_2) node _write_packets_mask_T_545 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_546 = lt(UInt<4>(0h8), _write_packets_mask_T_545) node _write_packets_mask_T_547 = and(_write_packets_mask_T_544, _write_packets_mask_T_546) node write_packets_mask_8_2 = and(_write_packets_mask_T_547, UInt<1>(0h1)) node _write_packets_mask_T_548 = geq(UInt<4>(0h9), write_packets_vaddr_offset_2) node _write_packets_mask_T_549 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_550 = lt(UInt<4>(0h9), _write_packets_mask_T_549) node _write_packets_mask_T_551 = and(_write_packets_mask_T_548, _write_packets_mask_T_550) node write_packets_mask_9_2 = and(_write_packets_mask_T_551, UInt<1>(0h1)) node _write_packets_mask_T_552 = geq(UInt<4>(0ha), write_packets_vaddr_offset_2) node _write_packets_mask_T_553 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_554 = lt(UInt<4>(0ha), _write_packets_mask_T_553) node _write_packets_mask_T_555 = and(_write_packets_mask_T_552, _write_packets_mask_T_554) node write_packets_mask_10_2 = and(_write_packets_mask_T_555, UInt<1>(0h1)) node _write_packets_mask_T_556 = geq(UInt<4>(0hb), write_packets_vaddr_offset_2) node _write_packets_mask_T_557 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_558 = lt(UInt<4>(0hb), _write_packets_mask_T_557) node _write_packets_mask_T_559 = and(_write_packets_mask_T_556, _write_packets_mask_T_558) node write_packets_mask_11_2 = and(_write_packets_mask_T_559, UInt<1>(0h1)) node _write_packets_mask_T_560 = geq(UInt<4>(0hc), write_packets_vaddr_offset_2) node _write_packets_mask_T_561 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_562 = lt(UInt<4>(0hc), _write_packets_mask_T_561) node _write_packets_mask_T_563 = and(_write_packets_mask_T_560, _write_packets_mask_T_562) node write_packets_mask_12_2 = and(_write_packets_mask_T_563, UInt<1>(0h1)) node _write_packets_mask_T_564 = geq(UInt<4>(0hd), write_packets_vaddr_offset_2) node _write_packets_mask_T_565 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_566 = lt(UInt<4>(0hd), _write_packets_mask_T_565) node _write_packets_mask_T_567 = and(_write_packets_mask_T_564, _write_packets_mask_T_566) node write_packets_mask_13_2 = and(_write_packets_mask_T_567, UInt<1>(0h1)) node _write_packets_mask_T_568 = geq(UInt<4>(0he), write_packets_vaddr_offset_2) node _write_packets_mask_T_569 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_570 = lt(UInt<4>(0he), _write_packets_mask_T_569) node _write_packets_mask_T_571 = and(_write_packets_mask_T_568, _write_packets_mask_T_570) node write_packets_mask_14_2 = and(_write_packets_mask_T_571, UInt<1>(0h1)) node _write_packets_mask_T_572 = geq(UInt<4>(0hf), write_packets_vaddr_offset_2) node _write_packets_mask_T_573 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_574 = lt(UInt<4>(0hf), _write_packets_mask_T_573) node _write_packets_mask_T_575 = and(_write_packets_mask_T_572, _write_packets_mask_T_574) node write_packets_mask_15_2 = and(_write_packets_mask_T_575, UInt<1>(0h1)) node _write_packets_mask_T_576 = geq(UInt<5>(0h10), write_packets_vaddr_offset_2) node _write_packets_mask_T_577 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_578 = lt(UInt<5>(0h10), _write_packets_mask_T_577) node _write_packets_mask_T_579 = and(_write_packets_mask_T_576, _write_packets_mask_T_578) node write_packets_mask_16_2 = and(_write_packets_mask_T_579, UInt<1>(0h1)) node _write_packets_mask_T_580 = geq(UInt<5>(0h11), write_packets_vaddr_offset_2) node _write_packets_mask_T_581 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_582 = lt(UInt<5>(0h11), _write_packets_mask_T_581) node _write_packets_mask_T_583 = and(_write_packets_mask_T_580, _write_packets_mask_T_582) node write_packets_mask_17_2 = and(_write_packets_mask_T_583, UInt<1>(0h1)) node _write_packets_mask_T_584 = geq(UInt<5>(0h12), write_packets_vaddr_offset_2) node _write_packets_mask_T_585 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_586 = lt(UInt<5>(0h12), _write_packets_mask_T_585) node _write_packets_mask_T_587 = and(_write_packets_mask_T_584, _write_packets_mask_T_586) node write_packets_mask_18_2 = and(_write_packets_mask_T_587, UInt<1>(0h1)) node _write_packets_mask_T_588 = geq(UInt<5>(0h13), write_packets_vaddr_offset_2) node _write_packets_mask_T_589 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_590 = lt(UInt<5>(0h13), _write_packets_mask_T_589) node _write_packets_mask_T_591 = and(_write_packets_mask_T_588, _write_packets_mask_T_590) node write_packets_mask_19_2 = and(_write_packets_mask_T_591, UInt<1>(0h1)) node _write_packets_mask_T_592 = geq(UInt<5>(0h14), write_packets_vaddr_offset_2) node _write_packets_mask_T_593 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_594 = lt(UInt<5>(0h14), _write_packets_mask_T_593) node _write_packets_mask_T_595 = and(_write_packets_mask_T_592, _write_packets_mask_T_594) node write_packets_mask_20_2 = and(_write_packets_mask_T_595, UInt<1>(0h1)) node _write_packets_mask_T_596 = geq(UInt<5>(0h15), write_packets_vaddr_offset_2) node _write_packets_mask_T_597 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_598 = lt(UInt<5>(0h15), _write_packets_mask_T_597) node _write_packets_mask_T_599 = and(_write_packets_mask_T_596, _write_packets_mask_T_598) node write_packets_mask_21_2 = and(_write_packets_mask_T_599, UInt<1>(0h1)) node _write_packets_mask_T_600 = geq(UInt<5>(0h16), write_packets_vaddr_offset_2) node _write_packets_mask_T_601 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_602 = lt(UInt<5>(0h16), _write_packets_mask_T_601) node _write_packets_mask_T_603 = and(_write_packets_mask_T_600, _write_packets_mask_T_602) node write_packets_mask_22_2 = and(_write_packets_mask_T_603, UInt<1>(0h1)) node _write_packets_mask_T_604 = geq(UInt<5>(0h17), write_packets_vaddr_offset_2) node _write_packets_mask_T_605 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_606 = lt(UInt<5>(0h17), _write_packets_mask_T_605) node _write_packets_mask_T_607 = and(_write_packets_mask_T_604, _write_packets_mask_T_606) node write_packets_mask_23_2 = and(_write_packets_mask_T_607, UInt<1>(0h1)) node _write_packets_mask_T_608 = geq(UInt<5>(0h18), write_packets_vaddr_offset_2) node _write_packets_mask_T_609 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_610 = lt(UInt<5>(0h18), _write_packets_mask_T_609) node _write_packets_mask_T_611 = and(_write_packets_mask_T_608, _write_packets_mask_T_610) node write_packets_mask_24_2 = and(_write_packets_mask_T_611, UInt<1>(0h1)) node _write_packets_mask_T_612 = geq(UInt<5>(0h19), write_packets_vaddr_offset_2) node _write_packets_mask_T_613 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_614 = lt(UInt<5>(0h19), _write_packets_mask_T_613) node _write_packets_mask_T_615 = and(_write_packets_mask_T_612, _write_packets_mask_T_614) node write_packets_mask_25_2 = and(_write_packets_mask_T_615, UInt<1>(0h1)) node _write_packets_mask_T_616 = geq(UInt<5>(0h1a), write_packets_vaddr_offset_2) node _write_packets_mask_T_617 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_618 = lt(UInt<5>(0h1a), _write_packets_mask_T_617) node _write_packets_mask_T_619 = and(_write_packets_mask_T_616, _write_packets_mask_T_618) node write_packets_mask_26_2 = and(_write_packets_mask_T_619, UInt<1>(0h1)) node _write_packets_mask_T_620 = geq(UInt<5>(0h1b), write_packets_vaddr_offset_2) node _write_packets_mask_T_621 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_622 = lt(UInt<5>(0h1b), _write_packets_mask_T_621) node _write_packets_mask_T_623 = and(_write_packets_mask_T_620, _write_packets_mask_T_622) node write_packets_mask_27_2 = and(_write_packets_mask_T_623, UInt<1>(0h1)) node _write_packets_mask_T_624 = geq(UInt<5>(0h1c), write_packets_vaddr_offset_2) node _write_packets_mask_T_625 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_626 = lt(UInt<5>(0h1c), _write_packets_mask_T_625) node _write_packets_mask_T_627 = and(_write_packets_mask_T_624, _write_packets_mask_T_626) node write_packets_mask_28_2 = and(_write_packets_mask_T_627, UInt<1>(0h1)) node _write_packets_mask_T_628 = geq(UInt<5>(0h1d), write_packets_vaddr_offset_2) node _write_packets_mask_T_629 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_630 = lt(UInt<5>(0h1d), _write_packets_mask_T_629) node _write_packets_mask_T_631 = and(_write_packets_mask_T_628, _write_packets_mask_T_630) node write_packets_mask_29_2 = and(_write_packets_mask_T_631, UInt<1>(0h1)) node _write_packets_mask_T_632 = geq(UInt<5>(0h1e), write_packets_vaddr_offset_2) node _write_packets_mask_T_633 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_634 = lt(UInt<5>(0h1e), _write_packets_mask_T_633) node _write_packets_mask_T_635 = and(_write_packets_mask_T_632, _write_packets_mask_T_634) node write_packets_mask_30_2 = and(_write_packets_mask_T_635, UInt<1>(0h1)) node _write_packets_mask_T_636 = geq(UInt<5>(0h1f), write_packets_vaddr_offset_2) node _write_packets_mask_T_637 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_638 = lt(UInt<5>(0h1f), _write_packets_mask_T_637) node _write_packets_mask_T_639 = and(_write_packets_mask_T_636, _write_packets_mask_T_638) node write_packets_mask_31_2 = and(_write_packets_mask_T_639, UInt<1>(0h1)) node _write_packets_mask_T_640 = geq(UInt<6>(0h20), write_packets_vaddr_offset_2) node _write_packets_mask_T_641 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_642 = lt(UInt<6>(0h20), _write_packets_mask_T_641) node _write_packets_mask_T_643 = and(_write_packets_mask_T_640, _write_packets_mask_T_642) node write_packets_mask_32_2 = and(_write_packets_mask_T_643, UInt<1>(0h1)) node _write_packets_mask_T_644 = geq(UInt<6>(0h21), write_packets_vaddr_offset_2) node _write_packets_mask_T_645 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_646 = lt(UInt<6>(0h21), _write_packets_mask_T_645) node _write_packets_mask_T_647 = and(_write_packets_mask_T_644, _write_packets_mask_T_646) node write_packets_mask_33_2 = and(_write_packets_mask_T_647, UInt<1>(0h1)) node _write_packets_mask_T_648 = geq(UInt<6>(0h22), write_packets_vaddr_offset_2) node _write_packets_mask_T_649 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_650 = lt(UInt<6>(0h22), _write_packets_mask_T_649) node _write_packets_mask_T_651 = and(_write_packets_mask_T_648, _write_packets_mask_T_650) node write_packets_mask_34_2 = and(_write_packets_mask_T_651, UInt<1>(0h1)) node _write_packets_mask_T_652 = geq(UInt<6>(0h23), write_packets_vaddr_offset_2) node _write_packets_mask_T_653 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_654 = lt(UInt<6>(0h23), _write_packets_mask_T_653) node _write_packets_mask_T_655 = and(_write_packets_mask_T_652, _write_packets_mask_T_654) node write_packets_mask_35_2 = and(_write_packets_mask_T_655, UInt<1>(0h1)) node _write_packets_mask_T_656 = geq(UInt<6>(0h24), write_packets_vaddr_offset_2) node _write_packets_mask_T_657 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_658 = lt(UInt<6>(0h24), _write_packets_mask_T_657) node _write_packets_mask_T_659 = and(_write_packets_mask_T_656, _write_packets_mask_T_658) node write_packets_mask_36_2 = and(_write_packets_mask_T_659, UInt<1>(0h1)) node _write_packets_mask_T_660 = geq(UInt<6>(0h25), write_packets_vaddr_offset_2) node _write_packets_mask_T_661 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_662 = lt(UInt<6>(0h25), _write_packets_mask_T_661) node _write_packets_mask_T_663 = and(_write_packets_mask_T_660, _write_packets_mask_T_662) node write_packets_mask_37_2 = and(_write_packets_mask_T_663, UInt<1>(0h1)) node _write_packets_mask_T_664 = geq(UInt<6>(0h26), write_packets_vaddr_offset_2) node _write_packets_mask_T_665 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_666 = lt(UInt<6>(0h26), _write_packets_mask_T_665) node _write_packets_mask_T_667 = and(_write_packets_mask_T_664, _write_packets_mask_T_666) node write_packets_mask_38_2 = and(_write_packets_mask_T_667, UInt<1>(0h1)) node _write_packets_mask_T_668 = geq(UInt<6>(0h27), write_packets_vaddr_offset_2) node _write_packets_mask_T_669 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_670 = lt(UInt<6>(0h27), _write_packets_mask_T_669) node _write_packets_mask_T_671 = and(_write_packets_mask_T_668, _write_packets_mask_T_670) node write_packets_mask_39_2 = and(_write_packets_mask_T_671, UInt<1>(0h1)) node _write_packets_mask_T_672 = geq(UInt<6>(0h28), write_packets_vaddr_offset_2) node _write_packets_mask_T_673 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_674 = lt(UInt<6>(0h28), _write_packets_mask_T_673) node _write_packets_mask_T_675 = and(_write_packets_mask_T_672, _write_packets_mask_T_674) node write_packets_mask_40_2 = and(_write_packets_mask_T_675, UInt<1>(0h1)) node _write_packets_mask_T_676 = geq(UInt<6>(0h29), write_packets_vaddr_offset_2) node _write_packets_mask_T_677 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_678 = lt(UInt<6>(0h29), _write_packets_mask_T_677) node _write_packets_mask_T_679 = and(_write_packets_mask_T_676, _write_packets_mask_T_678) node write_packets_mask_41_2 = and(_write_packets_mask_T_679, UInt<1>(0h1)) node _write_packets_mask_T_680 = geq(UInt<6>(0h2a), write_packets_vaddr_offset_2) node _write_packets_mask_T_681 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_682 = lt(UInt<6>(0h2a), _write_packets_mask_T_681) node _write_packets_mask_T_683 = and(_write_packets_mask_T_680, _write_packets_mask_T_682) node write_packets_mask_42_2 = and(_write_packets_mask_T_683, UInt<1>(0h1)) node _write_packets_mask_T_684 = geq(UInt<6>(0h2b), write_packets_vaddr_offset_2) node _write_packets_mask_T_685 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_686 = lt(UInt<6>(0h2b), _write_packets_mask_T_685) node _write_packets_mask_T_687 = and(_write_packets_mask_T_684, _write_packets_mask_T_686) node write_packets_mask_43_2 = and(_write_packets_mask_T_687, UInt<1>(0h1)) node _write_packets_mask_T_688 = geq(UInt<6>(0h2c), write_packets_vaddr_offset_2) node _write_packets_mask_T_689 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_690 = lt(UInt<6>(0h2c), _write_packets_mask_T_689) node _write_packets_mask_T_691 = and(_write_packets_mask_T_688, _write_packets_mask_T_690) node write_packets_mask_44_2 = and(_write_packets_mask_T_691, UInt<1>(0h1)) node _write_packets_mask_T_692 = geq(UInt<6>(0h2d), write_packets_vaddr_offset_2) node _write_packets_mask_T_693 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_694 = lt(UInt<6>(0h2d), _write_packets_mask_T_693) node _write_packets_mask_T_695 = and(_write_packets_mask_T_692, _write_packets_mask_T_694) node write_packets_mask_45_2 = and(_write_packets_mask_T_695, UInt<1>(0h1)) node _write_packets_mask_T_696 = geq(UInt<6>(0h2e), write_packets_vaddr_offset_2) node _write_packets_mask_T_697 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_698 = lt(UInt<6>(0h2e), _write_packets_mask_T_697) node _write_packets_mask_T_699 = and(_write_packets_mask_T_696, _write_packets_mask_T_698) node write_packets_mask_46_2 = and(_write_packets_mask_T_699, UInt<1>(0h1)) node _write_packets_mask_T_700 = geq(UInt<6>(0h2f), write_packets_vaddr_offset_2) node _write_packets_mask_T_701 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_702 = lt(UInt<6>(0h2f), _write_packets_mask_T_701) node _write_packets_mask_T_703 = and(_write_packets_mask_T_700, _write_packets_mask_T_702) node write_packets_mask_47_2 = and(_write_packets_mask_T_703, UInt<1>(0h1)) node _write_packets_mask_T_704 = geq(UInt<6>(0h30), write_packets_vaddr_offset_2) node _write_packets_mask_T_705 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_706 = lt(UInt<6>(0h30), _write_packets_mask_T_705) node _write_packets_mask_T_707 = and(_write_packets_mask_T_704, _write_packets_mask_T_706) node write_packets_mask_48_2 = and(_write_packets_mask_T_707, UInt<1>(0h1)) node _write_packets_mask_T_708 = geq(UInt<6>(0h31), write_packets_vaddr_offset_2) node _write_packets_mask_T_709 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_710 = lt(UInt<6>(0h31), _write_packets_mask_T_709) node _write_packets_mask_T_711 = and(_write_packets_mask_T_708, _write_packets_mask_T_710) node write_packets_mask_49_2 = and(_write_packets_mask_T_711, UInt<1>(0h1)) node _write_packets_mask_T_712 = geq(UInt<6>(0h32), write_packets_vaddr_offset_2) node _write_packets_mask_T_713 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_714 = lt(UInt<6>(0h32), _write_packets_mask_T_713) node _write_packets_mask_T_715 = and(_write_packets_mask_T_712, _write_packets_mask_T_714) node write_packets_mask_50_2 = and(_write_packets_mask_T_715, UInt<1>(0h1)) node _write_packets_mask_T_716 = geq(UInt<6>(0h33), write_packets_vaddr_offset_2) node _write_packets_mask_T_717 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_718 = lt(UInt<6>(0h33), _write_packets_mask_T_717) node _write_packets_mask_T_719 = and(_write_packets_mask_T_716, _write_packets_mask_T_718) node write_packets_mask_51_2 = and(_write_packets_mask_T_719, UInt<1>(0h1)) node _write_packets_mask_T_720 = geq(UInt<6>(0h34), write_packets_vaddr_offset_2) node _write_packets_mask_T_721 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_722 = lt(UInt<6>(0h34), _write_packets_mask_T_721) node _write_packets_mask_T_723 = and(_write_packets_mask_T_720, _write_packets_mask_T_722) node write_packets_mask_52_2 = and(_write_packets_mask_T_723, UInt<1>(0h1)) node _write_packets_mask_T_724 = geq(UInt<6>(0h35), write_packets_vaddr_offset_2) node _write_packets_mask_T_725 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_726 = lt(UInt<6>(0h35), _write_packets_mask_T_725) node _write_packets_mask_T_727 = and(_write_packets_mask_T_724, _write_packets_mask_T_726) node write_packets_mask_53_2 = and(_write_packets_mask_T_727, UInt<1>(0h1)) node _write_packets_mask_T_728 = geq(UInt<6>(0h36), write_packets_vaddr_offset_2) node _write_packets_mask_T_729 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_730 = lt(UInt<6>(0h36), _write_packets_mask_T_729) node _write_packets_mask_T_731 = and(_write_packets_mask_T_728, _write_packets_mask_T_730) node write_packets_mask_54_2 = and(_write_packets_mask_T_731, UInt<1>(0h1)) node _write_packets_mask_T_732 = geq(UInt<6>(0h37), write_packets_vaddr_offset_2) node _write_packets_mask_T_733 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_734 = lt(UInt<6>(0h37), _write_packets_mask_T_733) node _write_packets_mask_T_735 = and(_write_packets_mask_T_732, _write_packets_mask_T_734) node write_packets_mask_55_2 = and(_write_packets_mask_T_735, UInt<1>(0h1)) node _write_packets_mask_T_736 = geq(UInt<6>(0h38), write_packets_vaddr_offset_2) node _write_packets_mask_T_737 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_738 = lt(UInt<6>(0h38), _write_packets_mask_T_737) node _write_packets_mask_T_739 = and(_write_packets_mask_T_736, _write_packets_mask_T_738) node write_packets_mask_56_2 = and(_write_packets_mask_T_739, UInt<1>(0h1)) node _write_packets_mask_T_740 = geq(UInt<6>(0h39), write_packets_vaddr_offset_2) node _write_packets_mask_T_741 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_742 = lt(UInt<6>(0h39), _write_packets_mask_T_741) node _write_packets_mask_T_743 = and(_write_packets_mask_T_740, _write_packets_mask_T_742) node write_packets_mask_57_2 = and(_write_packets_mask_T_743, UInt<1>(0h1)) node _write_packets_mask_T_744 = geq(UInt<6>(0h3a), write_packets_vaddr_offset_2) node _write_packets_mask_T_745 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_746 = lt(UInt<6>(0h3a), _write_packets_mask_T_745) node _write_packets_mask_T_747 = and(_write_packets_mask_T_744, _write_packets_mask_T_746) node write_packets_mask_58_2 = and(_write_packets_mask_T_747, UInt<1>(0h1)) node _write_packets_mask_T_748 = geq(UInt<6>(0h3b), write_packets_vaddr_offset_2) node _write_packets_mask_T_749 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_750 = lt(UInt<6>(0h3b), _write_packets_mask_T_749) node _write_packets_mask_T_751 = and(_write_packets_mask_T_748, _write_packets_mask_T_750) node write_packets_mask_59_2 = and(_write_packets_mask_T_751, UInt<1>(0h1)) node _write_packets_mask_T_752 = geq(UInt<6>(0h3c), write_packets_vaddr_offset_2) node _write_packets_mask_T_753 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_754 = lt(UInt<6>(0h3c), _write_packets_mask_T_753) node _write_packets_mask_T_755 = and(_write_packets_mask_T_752, _write_packets_mask_T_754) node write_packets_mask_60_2 = and(_write_packets_mask_T_755, UInt<1>(0h1)) node _write_packets_mask_T_756 = geq(UInt<6>(0h3d), write_packets_vaddr_offset_2) node _write_packets_mask_T_757 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_758 = lt(UInt<6>(0h3d), _write_packets_mask_T_757) node _write_packets_mask_T_759 = and(_write_packets_mask_T_756, _write_packets_mask_T_758) node write_packets_mask_61_2 = and(_write_packets_mask_T_759, UInt<1>(0h1)) node _write_packets_mask_T_760 = geq(UInt<6>(0h3e), write_packets_vaddr_offset_2) node _write_packets_mask_T_761 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_762 = lt(UInt<6>(0h3e), _write_packets_mask_T_761) node _write_packets_mask_T_763 = and(_write_packets_mask_T_760, _write_packets_mask_T_762) node write_packets_mask_62_2 = and(_write_packets_mask_T_763, UInt<1>(0h1)) node _write_packets_mask_T_764 = geq(UInt<6>(0h3f), write_packets_vaddr_offset_2) node _write_packets_mask_T_765 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_766 = lt(UInt<6>(0h3f), _write_packets_mask_T_765) node _write_packets_mask_T_767 = and(_write_packets_mask_T_764, _write_packets_mask_T_766) node write_packets_mask_63_2 = and(_write_packets_mask_T_767, UInt<1>(0h1)) node _write_packets_bytes_written_T_8 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_bytes_written_T_9 = gt(_write_packets_bytes_written_T_8, UInt<7>(0h40)) node _write_packets_bytes_written_T_10 = sub(UInt<7>(0h40), write_packets_vaddr_offset_2) node _write_packets_bytes_written_T_11 = tail(_write_packets_bytes_written_T_10, 1) node write_packets_bytes_written_2 = mux(_write_packets_bytes_written_T_9, _write_packets_bytes_written_T_11, bytesLeft) wire write_packets_2 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_2.size, UInt<7>(0h40) connect write_packets_2.lg_size, UInt<3>(0h6) wire _write_packets_WIRE_10 : UInt<1>[16] connect _write_packets_WIRE_10[0], write_packets_mask_0_2 connect _write_packets_WIRE_10[1], write_packets_mask_1_2 connect _write_packets_WIRE_10[2], write_packets_mask_2_2 connect _write_packets_WIRE_10[3], write_packets_mask_3_2 connect _write_packets_WIRE_10[4], write_packets_mask_4_2 connect _write_packets_WIRE_10[5], write_packets_mask_5_2 connect _write_packets_WIRE_10[6], write_packets_mask_6_2 connect _write_packets_WIRE_10[7], write_packets_mask_7_2 connect _write_packets_WIRE_10[8], write_packets_mask_8_2 connect _write_packets_WIRE_10[9], write_packets_mask_9_2 connect _write_packets_WIRE_10[10], write_packets_mask_10_2 connect _write_packets_WIRE_10[11], write_packets_mask_11_2 connect _write_packets_WIRE_10[12], write_packets_mask_12_2 connect _write_packets_WIRE_10[13], write_packets_mask_13_2 connect _write_packets_WIRE_10[14], write_packets_mask_14_2 connect _write_packets_WIRE_10[15], write_packets_mask_15_2 wire _write_packets_WIRE_11 : UInt<1>[16] connect _write_packets_WIRE_11[0], write_packets_mask_16_2 connect _write_packets_WIRE_11[1], write_packets_mask_17_2 connect _write_packets_WIRE_11[2], write_packets_mask_18_2 connect _write_packets_WIRE_11[3], write_packets_mask_19_2 connect _write_packets_WIRE_11[4], write_packets_mask_20_2 connect _write_packets_WIRE_11[5], write_packets_mask_21_2 connect _write_packets_WIRE_11[6], write_packets_mask_22_2 connect _write_packets_WIRE_11[7], write_packets_mask_23_2 connect _write_packets_WIRE_11[8], write_packets_mask_24_2 connect _write_packets_WIRE_11[9], write_packets_mask_25_2 connect _write_packets_WIRE_11[10], write_packets_mask_26_2 connect _write_packets_WIRE_11[11], write_packets_mask_27_2 connect _write_packets_WIRE_11[12], write_packets_mask_28_2 connect _write_packets_WIRE_11[13], write_packets_mask_29_2 connect _write_packets_WIRE_11[14], write_packets_mask_30_2 connect _write_packets_WIRE_11[15], write_packets_mask_31_2 wire _write_packets_WIRE_12 : UInt<1>[16] connect _write_packets_WIRE_12[0], write_packets_mask_32_2 connect _write_packets_WIRE_12[1], write_packets_mask_33_2 connect _write_packets_WIRE_12[2], write_packets_mask_34_2 connect _write_packets_WIRE_12[3], write_packets_mask_35_2 connect _write_packets_WIRE_12[4], write_packets_mask_36_2 connect _write_packets_WIRE_12[5], write_packets_mask_37_2 connect _write_packets_WIRE_12[6], write_packets_mask_38_2 connect _write_packets_WIRE_12[7], write_packets_mask_39_2 connect _write_packets_WIRE_12[8], write_packets_mask_40_2 connect _write_packets_WIRE_12[9], write_packets_mask_41_2 connect _write_packets_WIRE_12[10], write_packets_mask_42_2 connect _write_packets_WIRE_12[11], write_packets_mask_43_2 connect _write_packets_WIRE_12[12], write_packets_mask_44_2 connect _write_packets_WIRE_12[13], write_packets_mask_45_2 connect _write_packets_WIRE_12[14], write_packets_mask_46_2 connect _write_packets_WIRE_12[15], write_packets_mask_47_2 wire _write_packets_WIRE_13 : UInt<1>[16] connect _write_packets_WIRE_13[0], write_packets_mask_48_2 connect _write_packets_WIRE_13[1], write_packets_mask_49_2 connect _write_packets_WIRE_13[2], write_packets_mask_50_2 connect _write_packets_WIRE_13[3], write_packets_mask_51_2 connect _write_packets_WIRE_13[4], write_packets_mask_52_2 connect _write_packets_WIRE_13[5], write_packets_mask_53_2 connect _write_packets_WIRE_13[6], write_packets_mask_54_2 connect _write_packets_WIRE_13[7], write_packets_mask_55_2 connect _write_packets_WIRE_13[8], write_packets_mask_56_2 connect _write_packets_WIRE_13[9], write_packets_mask_57_2 connect _write_packets_WIRE_13[10], write_packets_mask_58_2 connect _write_packets_WIRE_13[11], write_packets_mask_59_2 connect _write_packets_WIRE_13[12], write_packets_mask_60_2 connect _write_packets_WIRE_13[13], write_packets_mask_61_2 connect _write_packets_WIRE_13[14], write_packets_mask_62_2 connect _write_packets_WIRE_13[15], write_packets_mask_63_2 wire _write_packets_WIRE_14 : UInt<1>[16][4] connect _write_packets_WIRE_14[0], _write_packets_WIRE_10 connect _write_packets_WIRE_14[1], _write_packets_WIRE_11 connect _write_packets_WIRE_14[2], _write_packets_WIRE_12 connect _write_packets_WIRE_14[3], _write_packets_WIRE_13 connect write_packets_2.mask, _write_packets_WIRE_14 connect write_packets_2.vaddr, write_packets_vaddr_aligned_to_size_2 node _write_packets_packet_is_full_T_46 = and(write_packets_mask_0_2, write_packets_mask_1_2) node _write_packets_packet_is_full_T_47 = and(_write_packets_packet_is_full_T_46, write_packets_mask_2_2) node _write_packets_packet_is_full_T_48 = and(_write_packets_packet_is_full_T_47, write_packets_mask_3_2) node _write_packets_packet_is_full_T_49 = and(_write_packets_packet_is_full_T_48, write_packets_mask_4_2) node _write_packets_packet_is_full_T_50 = and(_write_packets_packet_is_full_T_49, write_packets_mask_5_2) node _write_packets_packet_is_full_T_51 = and(_write_packets_packet_is_full_T_50, write_packets_mask_6_2) node _write_packets_packet_is_full_T_52 = and(_write_packets_packet_is_full_T_51, write_packets_mask_7_2) node _write_packets_packet_is_full_T_53 = and(_write_packets_packet_is_full_T_52, write_packets_mask_8_2) node _write_packets_packet_is_full_T_54 = and(_write_packets_packet_is_full_T_53, write_packets_mask_9_2) node _write_packets_packet_is_full_T_55 = and(_write_packets_packet_is_full_T_54, write_packets_mask_10_2) node _write_packets_packet_is_full_T_56 = and(_write_packets_packet_is_full_T_55, write_packets_mask_11_2) node _write_packets_packet_is_full_T_57 = and(_write_packets_packet_is_full_T_56, write_packets_mask_12_2) node _write_packets_packet_is_full_T_58 = and(_write_packets_packet_is_full_T_57, write_packets_mask_13_2) node _write_packets_packet_is_full_T_59 = and(_write_packets_packet_is_full_T_58, write_packets_mask_14_2) node _write_packets_packet_is_full_T_60 = and(_write_packets_packet_is_full_T_59, write_packets_mask_15_2) node _write_packets_packet_is_full_T_61 = and(_write_packets_packet_is_full_T_60, write_packets_mask_16_2) node _write_packets_packet_is_full_T_62 = and(_write_packets_packet_is_full_T_61, write_packets_mask_17_2) node _write_packets_packet_is_full_T_63 = and(_write_packets_packet_is_full_T_62, write_packets_mask_18_2) node _write_packets_packet_is_full_T_64 = and(_write_packets_packet_is_full_T_63, write_packets_mask_19_2) node _write_packets_packet_is_full_T_65 = and(_write_packets_packet_is_full_T_64, write_packets_mask_20_2) node _write_packets_packet_is_full_T_66 = and(_write_packets_packet_is_full_T_65, write_packets_mask_21_2) node _write_packets_packet_is_full_T_67 = and(_write_packets_packet_is_full_T_66, write_packets_mask_22_2) node _write_packets_packet_is_full_T_68 = and(_write_packets_packet_is_full_T_67, write_packets_mask_23_2) node _write_packets_packet_is_full_T_69 = and(_write_packets_packet_is_full_T_68, write_packets_mask_24_2) node _write_packets_packet_is_full_T_70 = and(_write_packets_packet_is_full_T_69, write_packets_mask_25_2) node _write_packets_packet_is_full_T_71 = and(_write_packets_packet_is_full_T_70, write_packets_mask_26_2) node _write_packets_packet_is_full_T_72 = and(_write_packets_packet_is_full_T_71, write_packets_mask_27_2) node _write_packets_packet_is_full_T_73 = and(_write_packets_packet_is_full_T_72, write_packets_mask_28_2) node _write_packets_packet_is_full_T_74 = and(_write_packets_packet_is_full_T_73, write_packets_mask_29_2) node _write_packets_packet_is_full_T_75 = and(_write_packets_packet_is_full_T_74, write_packets_mask_30_2) node _write_packets_packet_is_full_T_76 = and(_write_packets_packet_is_full_T_75, write_packets_mask_31_2) node _write_packets_packet_is_full_T_77 = and(_write_packets_packet_is_full_T_76, write_packets_mask_32_2) node _write_packets_packet_is_full_T_78 = and(_write_packets_packet_is_full_T_77, write_packets_mask_33_2) node _write_packets_packet_is_full_T_79 = and(_write_packets_packet_is_full_T_78, write_packets_mask_34_2) node _write_packets_packet_is_full_T_80 = and(_write_packets_packet_is_full_T_79, write_packets_mask_35_2) node _write_packets_packet_is_full_T_81 = and(_write_packets_packet_is_full_T_80, write_packets_mask_36_2) node _write_packets_packet_is_full_T_82 = and(_write_packets_packet_is_full_T_81, write_packets_mask_37_2) node _write_packets_packet_is_full_T_83 = and(_write_packets_packet_is_full_T_82, write_packets_mask_38_2) node _write_packets_packet_is_full_T_84 = and(_write_packets_packet_is_full_T_83, write_packets_mask_39_2) node _write_packets_packet_is_full_T_85 = and(_write_packets_packet_is_full_T_84, write_packets_mask_40_2) node _write_packets_packet_is_full_T_86 = and(_write_packets_packet_is_full_T_85, write_packets_mask_41_2) node _write_packets_packet_is_full_T_87 = and(_write_packets_packet_is_full_T_86, write_packets_mask_42_2) node _write_packets_packet_is_full_T_88 = and(_write_packets_packet_is_full_T_87, write_packets_mask_43_2) node _write_packets_packet_is_full_T_89 = and(_write_packets_packet_is_full_T_88, write_packets_mask_44_2) node _write_packets_packet_is_full_T_90 = and(_write_packets_packet_is_full_T_89, write_packets_mask_45_2) node _write_packets_packet_is_full_T_91 = and(_write_packets_packet_is_full_T_90, write_packets_mask_46_2) node _write_packets_packet_is_full_T_92 = and(_write_packets_packet_is_full_T_91, write_packets_mask_47_2) node _write_packets_packet_is_full_T_93 = and(_write_packets_packet_is_full_T_92, write_packets_mask_48_2) node _write_packets_packet_is_full_T_94 = and(_write_packets_packet_is_full_T_93, write_packets_mask_49_2) node _write_packets_packet_is_full_T_95 = and(_write_packets_packet_is_full_T_94, write_packets_mask_50_2) node _write_packets_packet_is_full_T_96 = and(_write_packets_packet_is_full_T_95, write_packets_mask_51_2) node _write_packets_packet_is_full_T_97 = and(_write_packets_packet_is_full_T_96, write_packets_mask_52_2) node _write_packets_packet_is_full_T_98 = and(_write_packets_packet_is_full_T_97, write_packets_mask_53_2) node _write_packets_packet_is_full_T_99 = and(_write_packets_packet_is_full_T_98, write_packets_mask_54_2) node _write_packets_packet_is_full_T_100 = and(_write_packets_packet_is_full_T_99, write_packets_mask_55_2) node _write_packets_packet_is_full_T_101 = and(_write_packets_packet_is_full_T_100, write_packets_mask_56_2) node _write_packets_packet_is_full_T_102 = and(_write_packets_packet_is_full_T_101, write_packets_mask_57_2) node _write_packets_packet_is_full_T_103 = and(_write_packets_packet_is_full_T_102, write_packets_mask_58_2) node _write_packets_packet_is_full_T_104 = and(_write_packets_packet_is_full_T_103, write_packets_mask_59_2) node _write_packets_packet_is_full_T_105 = and(_write_packets_packet_is_full_T_104, write_packets_mask_60_2) node _write_packets_packet_is_full_T_106 = and(_write_packets_packet_is_full_T_105, write_packets_mask_61_2) node _write_packets_packet_is_full_T_107 = and(_write_packets_packet_is_full_T_106, write_packets_mask_62_2) node _write_packets_packet_is_full_T_108 = and(_write_packets_packet_is_full_T_107, write_packets_mask_63_2) connect write_packets_2.is_full, _write_packets_packet_is_full_T_108 connect write_packets_2.bytes_written, write_packets_bytes_written_2 node _write_packets_left_shift_T_40 = geq(write_packets_vaddr_offset_2, UInt<1>(0h0)) node _write_packets_left_shift_T_41 = lt(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_42 = and(_write_packets_left_shift_T_40, _write_packets_left_shift_T_41) node _write_packets_left_shift_T_43 = sub(write_packets_vaddr_offset_2, UInt<1>(0h0)) node _write_packets_left_shift_T_44 = tail(_write_packets_left_shift_T_43, 1) node write_packets_left_shift_8 = mux(_write_packets_left_shift_T_42, _write_packets_left_shift_T_44, UInt<1>(0h0)) node _write_packets_right_shift_T_64 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_65 = geq(_write_packets_right_shift_T_64, UInt<1>(0h0)) node _write_packets_right_shift_T_66 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_67 = lt(_write_packets_right_shift_T_66, UInt<5>(0h10)) node _write_packets_right_shift_T_68 = and(_write_packets_right_shift_T_65, _write_packets_right_shift_T_67) node _write_packets_right_shift_T_69 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_70 = sub(UInt<5>(0h10), _write_packets_right_shift_T_69) node _write_packets_right_shift_T_71 = tail(_write_packets_right_shift_T_70, 1) node write_packets_right_shift_8 = mux(_write_packets_right_shift_T_68, _write_packets_right_shift_T_71, UInt<1>(0h0)) node write_packets_too_early_8 = geq(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_too_late_T_8 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_8 = leq(_write_packets_too_late_T_8, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T_10 = or(write_packets_too_early_8, write_packets_too_late_8) node _write_packets_packet_bytes_written_per_beat_0_T_11 = add(write_packets_left_shift_8, write_packets_right_shift_8) node _write_packets_packet_bytes_written_per_beat_0_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_11) node _write_packets_packet_bytes_written_per_beat_0_T_13 = tail(_write_packets_packet_bytes_written_per_beat_0_T_12, 1) node _write_packets_packet_bytes_written_per_beat_0_T_14 = mux(_write_packets_packet_bytes_written_per_beat_0_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_13) connect write_packets_2.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_14 node _write_packets_left_shift_T_45 = geq(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_46 = lt(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_47 = and(_write_packets_left_shift_T_45, _write_packets_left_shift_T_46) node _write_packets_left_shift_T_48 = sub(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_49 = tail(_write_packets_left_shift_T_48, 1) node write_packets_left_shift_9 = mux(_write_packets_left_shift_T_47, _write_packets_left_shift_T_49, UInt<1>(0h0)) node _write_packets_right_shift_T_72 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_73 = geq(_write_packets_right_shift_T_72, UInt<5>(0h10)) node _write_packets_right_shift_T_74 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_75 = lt(_write_packets_right_shift_T_74, UInt<6>(0h20)) node _write_packets_right_shift_T_76 = and(_write_packets_right_shift_T_73, _write_packets_right_shift_T_75) node _write_packets_right_shift_T_77 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_78 = sub(UInt<6>(0h20), _write_packets_right_shift_T_77) node _write_packets_right_shift_T_79 = tail(_write_packets_right_shift_T_78, 1) node write_packets_right_shift_9 = mux(_write_packets_right_shift_T_76, _write_packets_right_shift_T_79, UInt<1>(0h0)) node write_packets_too_early_9 = geq(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_too_late_T_9 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_9 = leq(_write_packets_too_late_T_9, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T_10 = or(write_packets_too_early_9, write_packets_too_late_9) node _write_packets_packet_bytes_written_per_beat_1_T_11 = add(write_packets_left_shift_9, write_packets_right_shift_9) node _write_packets_packet_bytes_written_per_beat_1_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_11) node _write_packets_packet_bytes_written_per_beat_1_T_13 = tail(_write_packets_packet_bytes_written_per_beat_1_T_12, 1) node _write_packets_packet_bytes_written_per_beat_1_T_14 = mux(_write_packets_packet_bytes_written_per_beat_1_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_13) connect write_packets_2.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_14 node _write_packets_left_shift_T_50 = geq(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_51 = lt(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_52 = and(_write_packets_left_shift_T_50, _write_packets_left_shift_T_51) node _write_packets_left_shift_T_53 = sub(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_54 = tail(_write_packets_left_shift_T_53, 1) node write_packets_left_shift_10 = mux(_write_packets_left_shift_T_52, _write_packets_left_shift_T_54, UInt<1>(0h0)) node _write_packets_right_shift_T_80 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_81 = geq(_write_packets_right_shift_T_80, UInt<6>(0h20)) node _write_packets_right_shift_T_82 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_83 = lt(_write_packets_right_shift_T_82, UInt<6>(0h30)) node _write_packets_right_shift_T_84 = and(_write_packets_right_shift_T_81, _write_packets_right_shift_T_83) node _write_packets_right_shift_T_85 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_86 = sub(UInt<6>(0h30), _write_packets_right_shift_T_85) node _write_packets_right_shift_T_87 = tail(_write_packets_right_shift_T_86, 1) node write_packets_right_shift_10 = mux(_write_packets_right_shift_T_84, _write_packets_right_shift_T_87, UInt<1>(0h0)) node write_packets_too_early_10 = geq(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_too_late_T_10 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_10 = leq(_write_packets_too_late_T_10, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T_10 = or(write_packets_too_early_10, write_packets_too_late_10) node _write_packets_packet_bytes_written_per_beat_2_T_11 = add(write_packets_left_shift_10, write_packets_right_shift_10) node _write_packets_packet_bytes_written_per_beat_2_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_11) node _write_packets_packet_bytes_written_per_beat_2_T_13 = tail(_write_packets_packet_bytes_written_per_beat_2_T_12, 1) node _write_packets_packet_bytes_written_per_beat_2_T_14 = mux(_write_packets_packet_bytes_written_per_beat_2_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_13) connect write_packets_2.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_14 node _write_packets_left_shift_T_55 = geq(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_56 = lt(write_packets_vaddr_offset_2, UInt<7>(0h40)) node _write_packets_left_shift_T_57 = and(_write_packets_left_shift_T_55, _write_packets_left_shift_T_56) node _write_packets_left_shift_T_58 = sub(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_59 = tail(_write_packets_left_shift_T_58, 1) node write_packets_left_shift_11 = mux(_write_packets_left_shift_T_57, _write_packets_left_shift_T_59, UInt<1>(0h0)) node _write_packets_right_shift_T_88 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_89 = geq(_write_packets_right_shift_T_88, UInt<6>(0h30)) node _write_packets_right_shift_T_90 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_91 = lt(_write_packets_right_shift_T_90, UInt<7>(0h40)) node _write_packets_right_shift_T_92 = and(_write_packets_right_shift_T_89, _write_packets_right_shift_T_91) node _write_packets_right_shift_T_93 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_94 = sub(UInt<7>(0h40), _write_packets_right_shift_T_93) node _write_packets_right_shift_T_95 = tail(_write_packets_right_shift_T_94, 1) node write_packets_right_shift_11 = mux(_write_packets_right_shift_T_92, _write_packets_right_shift_T_95, UInt<1>(0h0)) node write_packets_too_early_11 = geq(write_packets_vaddr_offset_2, UInt<7>(0h40)) node _write_packets_too_late_T_11 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_11 = leq(_write_packets_too_late_T_11, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T_10 = or(write_packets_too_early_11, write_packets_too_late_11) node _write_packets_packet_bytes_written_per_beat_3_T_11 = add(write_packets_left_shift_11, write_packets_right_shift_11) node _write_packets_packet_bytes_written_per_beat_3_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_11) node _write_packets_packet_bytes_written_per_beat_3_T_13 = tail(_write_packets_packet_bytes_written_per_beat_3_T_12, 1) node _write_packets_packet_bytes_written_per_beat_3_T_14 = mux(_write_packets_packet_bytes_written_per_beat_3_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_13) connect write_packets_2.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_14 node _best_write_packet_T = gt(write_packets_1.bytes_written, write_packets_0.bytes_written) node _best_write_packet_T_1 = mux(_best_write_packet_T, write_packets_1, write_packets_0) node _best_write_packet_T_2 = gt(write_packets_2.bytes_written, _best_write_packet_T_1.bytes_written) node best_write_packet = mux(_best_write_packet_T_2, write_packets_2, _best_write_packet_T_1) node _write_packet_T = eq(state, UInt<2>(0h1)) reg write_packet_buf : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]}, clock when _write_packet_T : connect write_packet_buf, best_write_packet node write_packet = mux(_write_packet_T, best_write_packet, write_packet_buf) node _write_beats_T = lt(write_packet.size, UInt<5>(0h10)) node _write_beats_T_1 = div(write_packet.size, UInt<7>(0h10)) node write_beats = mux(_write_beats_T, UInt<1>(0h1), _write_beats_T_1) reg beatsLeft : UInt<6>, clock node _beatsSent_T = eq(state, UInt<2>(0h1)) node _beatsSent_T_1 = sub(write_beats, beatsLeft) node _beatsSent_T_2 = tail(_beatsSent_T_1, 1) node beatsSent = mux(_beatsSent_T, UInt<1>(0h0), _beatsSent_T_2) node _write_mask_T = bits(beatsSent, 1, 0) node _write_shift_T = mux(write_packet.mask[_write_mask_T][14], UInt<4>(0he), UInt<4>(0hf)) node _write_shift_T_1 = mux(write_packet.mask[_write_mask_T][13], UInt<4>(0hd), _write_shift_T) node _write_shift_T_2 = mux(write_packet.mask[_write_mask_T][12], UInt<4>(0hc), _write_shift_T_1) node _write_shift_T_3 = mux(write_packet.mask[_write_mask_T][11], UInt<4>(0hb), _write_shift_T_2) node _write_shift_T_4 = mux(write_packet.mask[_write_mask_T][10], UInt<4>(0ha), _write_shift_T_3) node _write_shift_T_5 = mux(write_packet.mask[_write_mask_T][9], UInt<4>(0h9), _write_shift_T_4) node _write_shift_T_6 = mux(write_packet.mask[_write_mask_T][8], UInt<4>(0h8), _write_shift_T_5) node _write_shift_T_7 = mux(write_packet.mask[_write_mask_T][7], UInt<3>(0h7), _write_shift_T_6) node _write_shift_T_8 = mux(write_packet.mask[_write_mask_T][6], UInt<3>(0h6), _write_shift_T_7) node _write_shift_T_9 = mux(write_packet.mask[_write_mask_T][5], UInt<3>(0h5), _write_shift_T_8) node _write_shift_T_10 = mux(write_packet.mask[_write_mask_T][4], UInt<3>(0h4), _write_shift_T_9) node _write_shift_T_11 = mux(write_packet.mask[_write_mask_T][3], UInt<2>(0h3), _write_shift_T_10) node _write_shift_T_12 = mux(write_packet.mask[_write_mask_T][2], UInt<2>(0h2), _write_shift_T_11) node _write_shift_T_13 = mux(write_packet.mask[_write_mask_T][1], UInt<1>(0h1), _write_shift_T_12) node write_shift = mux(write_packet.mask[_write_mask_T][0], UInt<1>(0h0), _write_shift_T_13) node _bytes_written_this_beat_T = bits(beatsSent, 1, 0) node _putFull_T = eq(state, UInt<2>(0h1)) reg putFull_buf : UInt<4>, clock when _putFull_T : connect putFull_buf, xactId node _putFull_T_1 = mux(_putFull_T, xactId, putFull_buf) node _putFull_T_2 = mul(bytesSent, UInt<4>(0h8)) node _putFull_T_3 = dshr(data, _putFull_T_2) node _putFull_legal_T = leq(UInt<1>(0h0), write_packet.lg_size) node _putFull_legal_T_1 = leq(write_packet.lg_size, UInt<4>(0hc)) node _putFull_legal_T_2 = and(_putFull_legal_T, _putFull_legal_T_1) node _putFull_legal_T_3 = or(UInt<1>(0h0), _putFull_legal_T_2) node _putFull_legal_T_4 = xor(UInt<1>(0h0), UInt<14>(0h3000)) node _putFull_legal_T_5 = cvt(_putFull_legal_T_4) node _putFull_legal_T_6 = and(_putFull_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_7 = asSInt(_putFull_legal_T_6) node _putFull_legal_T_8 = eq(_putFull_legal_T_7, asSInt(UInt<1>(0h0))) node _putFull_legal_T_9 = and(_putFull_legal_T_3, _putFull_legal_T_8) node _putFull_legal_T_10 = leq(UInt<1>(0h0), write_packet.lg_size) node _putFull_legal_T_11 = leq(write_packet.lg_size, UInt<3>(0h6)) node _putFull_legal_T_12 = and(_putFull_legal_T_10, _putFull_legal_T_11) node _putFull_legal_T_13 = or(UInt<1>(0h0), _putFull_legal_T_12) node _putFull_legal_T_14 = xor(UInt<1>(0h0), UInt<1>(0h0)) node _putFull_legal_T_15 = cvt(_putFull_legal_T_14) node _putFull_legal_T_16 = and(_putFull_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _putFull_legal_T_17 = asSInt(_putFull_legal_T_16) node _putFull_legal_T_18 = eq(_putFull_legal_T_17, asSInt(UInt<1>(0h0))) node _putFull_legal_T_19 = xor(UInt<1>(0h0), UInt<21>(0h100000)) node _putFull_legal_T_20 = cvt(_putFull_legal_T_19) node _putFull_legal_T_21 = and(_putFull_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _putFull_legal_T_22 = asSInt(_putFull_legal_T_21) node _putFull_legal_T_23 = eq(_putFull_legal_T_22, asSInt(UInt<1>(0h0))) node _putFull_legal_T_24 = xor(UInt<1>(0h0), UInt<26>(0h2000000)) node _putFull_legal_T_25 = cvt(_putFull_legal_T_24) node _putFull_legal_T_26 = and(_putFull_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_27 = asSInt(_putFull_legal_T_26) node _putFull_legal_T_28 = eq(_putFull_legal_T_27, asSInt(UInt<1>(0h0))) node _putFull_legal_T_29 = xor(UInt<1>(0h0), UInt<26>(0h2010000)) node _putFull_legal_T_30 = cvt(_putFull_legal_T_29) node _putFull_legal_T_31 = and(_putFull_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_32 = asSInt(_putFull_legal_T_31) node _putFull_legal_T_33 = eq(_putFull_legal_T_32, asSInt(UInt<1>(0h0))) node _putFull_legal_T_34 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putFull_legal_T_35 = cvt(_putFull_legal_T_34) node _putFull_legal_T_36 = and(_putFull_legal_T_35, asSInt(UInt<33>(0h98000000))) node _putFull_legal_T_37 = asSInt(_putFull_legal_T_36) node _putFull_legal_T_38 = eq(_putFull_legal_T_37, asSInt(UInt<1>(0h0))) node _putFull_legal_T_39 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putFull_legal_T_40 = cvt(_putFull_legal_T_39) node _putFull_legal_T_41 = and(_putFull_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_42 = asSInt(_putFull_legal_T_41) node _putFull_legal_T_43 = eq(_putFull_legal_T_42, asSInt(UInt<1>(0h0))) node _putFull_legal_T_44 = xor(UInt<1>(0h0), UInt<29>(0h10000000)) node _putFull_legal_T_45 = cvt(_putFull_legal_T_44) node _putFull_legal_T_46 = and(_putFull_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_47 = asSInt(_putFull_legal_T_46) node _putFull_legal_T_48 = eq(_putFull_legal_T_47, asSInt(UInt<1>(0h0))) node _putFull_legal_T_49 = xor(UInt<1>(0h0), UInt<32>(0h80000000)) node _putFull_legal_T_50 = cvt(_putFull_legal_T_49) node _putFull_legal_T_51 = and(_putFull_legal_T_50, asSInt(UInt<33>(0h90000000))) node _putFull_legal_T_52 = asSInt(_putFull_legal_T_51) node _putFull_legal_T_53 = eq(_putFull_legal_T_52, asSInt(UInt<1>(0h0))) node _putFull_legal_T_54 = or(_putFull_legal_T_18, _putFull_legal_T_23) node _putFull_legal_T_55 = or(_putFull_legal_T_54, _putFull_legal_T_28) node _putFull_legal_T_56 = or(_putFull_legal_T_55, _putFull_legal_T_33) node _putFull_legal_T_57 = or(_putFull_legal_T_56, _putFull_legal_T_38) node _putFull_legal_T_58 = or(_putFull_legal_T_57, _putFull_legal_T_43) node _putFull_legal_T_59 = or(_putFull_legal_T_58, _putFull_legal_T_48) node _putFull_legal_T_60 = or(_putFull_legal_T_59, _putFull_legal_T_53) node _putFull_legal_T_61 = and(_putFull_legal_T_13, _putFull_legal_T_60) node _putFull_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _putFull_legal_T_63 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _putFull_legal_T_64 = cvt(_putFull_legal_T_63) node _putFull_legal_T_65 = and(_putFull_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_66 = asSInt(_putFull_legal_T_65) node _putFull_legal_T_67 = eq(_putFull_legal_T_66, asSInt(UInt<1>(0h0))) node _putFull_legal_T_68 = and(_putFull_legal_T_62, _putFull_legal_T_67) node _putFull_legal_T_69 = or(UInt<1>(0h0), _putFull_legal_T_9) node _putFull_legal_T_70 = or(_putFull_legal_T_69, _putFull_legal_T_61) node putFull_legal = or(_putFull_legal_T_70, _putFull_legal_T_68) wire putFull : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect putFull.opcode, UInt<1>(0h0) connect putFull.param, UInt<1>(0h0) connect putFull.size, write_packet.lg_size connect putFull.source, _putFull_T_1 connect putFull.address, UInt<1>(0h0) node _putFull_a_mask_sizeOH_T = or(write_packet.lg_size, UInt<4>(0h0)) node putFull_a_mask_sizeOH_shiftAmount = bits(_putFull_a_mask_sizeOH_T, 1, 0) node _putFull_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), putFull_a_mask_sizeOH_shiftAmount) node _putFull_a_mask_sizeOH_T_2 = bits(_putFull_a_mask_sizeOH_T_1, 3, 0) node putFull_a_mask_sizeOH = or(_putFull_a_mask_sizeOH_T_2, UInt<1>(0h1)) node putFull_a_mask_sub_sub_sub_sub_0_1 = geq(write_packet.lg_size, UInt<3>(0h4)) node putFull_a_mask_sub_sub_sub_size = bits(putFull_a_mask_sizeOH, 3, 3) node putFull_a_mask_sub_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), putFull_a_mask_sub_sub_sub_nbit) node _putFull_a_mask_sub_sub_sub_acc_T = and(putFull_a_mask_sub_sub_sub_size, putFull_a_mask_sub_sub_sub_0_2) node putFull_a_mask_sub_sub_sub_0_1 = or(putFull_a_mask_sub_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_sub_acc_T) node putFull_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node _putFull_a_mask_sub_sub_sub_acc_T_1 = and(putFull_a_mask_sub_sub_sub_size, putFull_a_mask_sub_sub_sub_1_2) node putFull_a_mask_sub_sub_sub_1_1 = or(putFull_a_mask_sub_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_sub_acc_T_1) node putFull_a_mask_sub_sub_size = bits(putFull_a_mask_sizeOH, 2, 2) node putFull_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_sub_0_2 = and(putFull_a_mask_sub_sub_sub_0_2, putFull_a_mask_sub_sub_nbit) node _putFull_a_mask_sub_sub_acc_T = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_0_2) node putFull_a_mask_sub_sub_0_1 = or(putFull_a_mask_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_acc_T) node putFull_a_mask_sub_sub_1_2 = and(putFull_a_mask_sub_sub_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_sub_sub_acc_T_1 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_1_2) node putFull_a_mask_sub_sub_1_1 = or(putFull_a_mask_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_acc_T_1) node putFull_a_mask_sub_sub_2_2 = and(putFull_a_mask_sub_sub_sub_1_2, putFull_a_mask_sub_sub_nbit) node _putFull_a_mask_sub_sub_acc_T_2 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_2_2) node putFull_a_mask_sub_sub_2_1 = or(putFull_a_mask_sub_sub_sub_1_1, _putFull_a_mask_sub_sub_acc_T_2) node putFull_a_mask_sub_sub_3_2 = and(putFull_a_mask_sub_sub_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_sub_sub_acc_T_3 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_3_2) node putFull_a_mask_sub_sub_3_1 = or(putFull_a_mask_sub_sub_sub_1_1, _putFull_a_mask_sub_sub_acc_T_3) node putFull_a_mask_sub_size = bits(putFull_a_mask_sizeOH, 1, 1) node putFull_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_0_2 = and(putFull_a_mask_sub_sub_0_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T = and(putFull_a_mask_sub_size, putFull_a_mask_sub_0_2) node putFull_a_mask_sub_0_1 = or(putFull_a_mask_sub_sub_0_1, _putFull_a_mask_sub_acc_T) node putFull_a_mask_sub_1_2 = and(putFull_a_mask_sub_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_1 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_1_2) node putFull_a_mask_sub_1_1 = or(putFull_a_mask_sub_sub_0_1, _putFull_a_mask_sub_acc_T_1) node putFull_a_mask_sub_2_2 = and(putFull_a_mask_sub_sub_1_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_2 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_2_2) node putFull_a_mask_sub_2_1 = or(putFull_a_mask_sub_sub_1_1, _putFull_a_mask_sub_acc_T_2) node putFull_a_mask_sub_3_2 = and(putFull_a_mask_sub_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_3 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_3_2) node putFull_a_mask_sub_3_1 = or(putFull_a_mask_sub_sub_1_1, _putFull_a_mask_sub_acc_T_3) node putFull_a_mask_sub_4_2 = and(putFull_a_mask_sub_sub_2_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_4 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_4_2) node putFull_a_mask_sub_4_1 = or(putFull_a_mask_sub_sub_2_1, _putFull_a_mask_sub_acc_T_4) node putFull_a_mask_sub_5_2 = and(putFull_a_mask_sub_sub_2_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_5 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_5_2) node putFull_a_mask_sub_5_1 = or(putFull_a_mask_sub_sub_2_1, _putFull_a_mask_sub_acc_T_5) node putFull_a_mask_sub_6_2 = and(putFull_a_mask_sub_sub_3_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_6 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_6_2) node putFull_a_mask_sub_6_1 = or(putFull_a_mask_sub_sub_3_1, _putFull_a_mask_sub_acc_T_6) node putFull_a_mask_sub_7_2 = and(putFull_a_mask_sub_sub_3_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_7 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_7_2) node putFull_a_mask_sub_7_1 = or(putFull_a_mask_sub_sub_3_1, _putFull_a_mask_sub_acc_T_7) node putFull_a_mask_size = bits(putFull_a_mask_sizeOH, 0, 0) node putFull_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_eq = and(putFull_a_mask_sub_0_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T = and(putFull_a_mask_size, putFull_a_mask_eq) node putFull_a_mask_acc = or(putFull_a_mask_sub_0_1, _putFull_a_mask_acc_T) node putFull_a_mask_eq_1 = and(putFull_a_mask_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_1 = and(putFull_a_mask_size, putFull_a_mask_eq_1) node putFull_a_mask_acc_1 = or(putFull_a_mask_sub_0_1, _putFull_a_mask_acc_T_1) node putFull_a_mask_eq_2 = and(putFull_a_mask_sub_1_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_2 = and(putFull_a_mask_size, putFull_a_mask_eq_2) node putFull_a_mask_acc_2 = or(putFull_a_mask_sub_1_1, _putFull_a_mask_acc_T_2) node putFull_a_mask_eq_3 = and(putFull_a_mask_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_3 = and(putFull_a_mask_size, putFull_a_mask_eq_3) node putFull_a_mask_acc_3 = or(putFull_a_mask_sub_1_1, _putFull_a_mask_acc_T_3) node putFull_a_mask_eq_4 = and(putFull_a_mask_sub_2_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_4 = and(putFull_a_mask_size, putFull_a_mask_eq_4) node putFull_a_mask_acc_4 = or(putFull_a_mask_sub_2_1, _putFull_a_mask_acc_T_4) node putFull_a_mask_eq_5 = and(putFull_a_mask_sub_2_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_5 = and(putFull_a_mask_size, putFull_a_mask_eq_5) node putFull_a_mask_acc_5 = or(putFull_a_mask_sub_2_1, _putFull_a_mask_acc_T_5) node putFull_a_mask_eq_6 = and(putFull_a_mask_sub_3_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_6 = and(putFull_a_mask_size, putFull_a_mask_eq_6) node putFull_a_mask_acc_6 = or(putFull_a_mask_sub_3_1, _putFull_a_mask_acc_T_6) node putFull_a_mask_eq_7 = and(putFull_a_mask_sub_3_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_7 = and(putFull_a_mask_size, putFull_a_mask_eq_7) node putFull_a_mask_acc_7 = or(putFull_a_mask_sub_3_1, _putFull_a_mask_acc_T_7) node putFull_a_mask_eq_8 = and(putFull_a_mask_sub_4_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_8 = and(putFull_a_mask_size, putFull_a_mask_eq_8) node putFull_a_mask_acc_8 = or(putFull_a_mask_sub_4_1, _putFull_a_mask_acc_T_8) node putFull_a_mask_eq_9 = and(putFull_a_mask_sub_4_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_9 = and(putFull_a_mask_size, putFull_a_mask_eq_9) node putFull_a_mask_acc_9 = or(putFull_a_mask_sub_4_1, _putFull_a_mask_acc_T_9) node putFull_a_mask_eq_10 = and(putFull_a_mask_sub_5_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_10 = and(putFull_a_mask_size, putFull_a_mask_eq_10) node putFull_a_mask_acc_10 = or(putFull_a_mask_sub_5_1, _putFull_a_mask_acc_T_10) node putFull_a_mask_eq_11 = and(putFull_a_mask_sub_5_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_11 = and(putFull_a_mask_size, putFull_a_mask_eq_11) node putFull_a_mask_acc_11 = or(putFull_a_mask_sub_5_1, _putFull_a_mask_acc_T_11) node putFull_a_mask_eq_12 = and(putFull_a_mask_sub_6_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_12 = and(putFull_a_mask_size, putFull_a_mask_eq_12) node putFull_a_mask_acc_12 = or(putFull_a_mask_sub_6_1, _putFull_a_mask_acc_T_12) node putFull_a_mask_eq_13 = and(putFull_a_mask_sub_6_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_13 = and(putFull_a_mask_size, putFull_a_mask_eq_13) node putFull_a_mask_acc_13 = or(putFull_a_mask_sub_6_1, _putFull_a_mask_acc_T_13) node putFull_a_mask_eq_14 = and(putFull_a_mask_sub_7_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_14 = and(putFull_a_mask_size, putFull_a_mask_eq_14) node putFull_a_mask_acc_14 = or(putFull_a_mask_sub_7_1, _putFull_a_mask_acc_T_14) node putFull_a_mask_eq_15 = and(putFull_a_mask_sub_7_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_15 = and(putFull_a_mask_size, putFull_a_mask_eq_15) node putFull_a_mask_acc_15 = or(putFull_a_mask_sub_7_1, _putFull_a_mask_acc_T_15) node putFull_a_mask_lo_lo_lo = cat(putFull_a_mask_acc_1, putFull_a_mask_acc) node putFull_a_mask_lo_lo_hi = cat(putFull_a_mask_acc_3, putFull_a_mask_acc_2) node putFull_a_mask_lo_lo = cat(putFull_a_mask_lo_lo_hi, putFull_a_mask_lo_lo_lo) node putFull_a_mask_lo_hi_lo = cat(putFull_a_mask_acc_5, putFull_a_mask_acc_4) node putFull_a_mask_lo_hi_hi = cat(putFull_a_mask_acc_7, putFull_a_mask_acc_6) node putFull_a_mask_lo_hi = cat(putFull_a_mask_lo_hi_hi, putFull_a_mask_lo_hi_lo) node putFull_a_mask_lo = cat(putFull_a_mask_lo_hi, putFull_a_mask_lo_lo) node putFull_a_mask_hi_lo_lo = cat(putFull_a_mask_acc_9, putFull_a_mask_acc_8) node putFull_a_mask_hi_lo_hi = cat(putFull_a_mask_acc_11, putFull_a_mask_acc_10) node putFull_a_mask_hi_lo = cat(putFull_a_mask_hi_lo_hi, putFull_a_mask_hi_lo_lo) node putFull_a_mask_hi_hi_lo = cat(putFull_a_mask_acc_13, putFull_a_mask_acc_12) node putFull_a_mask_hi_hi_hi = cat(putFull_a_mask_acc_15, putFull_a_mask_acc_14) node putFull_a_mask_hi_hi = cat(putFull_a_mask_hi_hi_hi, putFull_a_mask_hi_hi_lo) node putFull_a_mask_hi = cat(putFull_a_mask_hi_hi, putFull_a_mask_hi_lo) node _putFull_a_mask_T = cat(putFull_a_mask_hi, putFull_a_mask_lo) connect putFull.mask, _putFull_a_mask_T connect putFull.data, _putFull_T_3 connect putFull.corrupt, UInt<1>(0h0) node _putPartial_T = eq(state, UInt<2>(0h1)) reg putPartial_buf : UInt<4>, clock when _putPartial_T : connect putPartial_buf, xactId node _putPartial_T_1 = mux(_putPartial_T, xactId, putPartial_buf) node _putPartial_T_2 = mul(bytesSent, UInt<4>(0h8)) node _putPartial_T_3 = dshr(data, _putPartial_T_2) node _putPartial_T_4 = mul(write_shift, UInt<4>(0h8)) node _putPartial_T_5 = dshl(_putPartial_T_3, _putPartial_T_4) node putPartial_lo_lo_lo = cat(write_packet.mask[_write_mask_T][1], write_packet.mask[_write_mask_T][0]) node putPartial_lo_lo_hi = cat(write_packet.mask[_write_mask_T][3], write_packet.mask[_write_mask_T][2]) node putPartial_lo_lo = cat(putPartial_lo_lo_hi, putPartial_lo_lo_lo) node putPartial_lo_hi_lo = cat(write_packet.mask[_write_mask_T][5], write_packet.mask[_write_mask_T][4]) node putPartial_lo_hi_hi = cat(write_packet.mask[_write_mask_T][7], write_packet.mask[_write_mask_T][6]) node putPartial_lo_hi = cat(putPartial_lo_hi_hi, putPartial_lo_hi_lo) node putPartial_lo = cat(putPartial_lo_hi, putPartial_lo_lo) node putPartial_hi_lo_lo = cat(write_packet.mask[_write_mask_T][9], write_packet.mask[_write_mask_T][8]) node putPartial_hi_lo_hi = cat(write_packet.mask[_write_mask_T][11], write_packet.mask[_write_mask_T][10]) node putPartial_hi_lo = cat(putPartial_hi_lo_hi, putPartial_hi_lo_lo) node putPartial_hi_hi_lo = cat(write_packet.mask[_write_mask_T][13], write_packet.mask[_write_mask_T][12]) node putPartial_hi_hi_hi = cat(write_packet.mask[_write_mask_T][15], write_packet.mask[_write_mask_T][14]) node putPartial_hi_hi = cat(putPartial_hi_hi_hi, putPartial_hi_hi_lo) node putPartial_hi = cat(putPartial_hi_hi, putPartial_hi_lo) node _putPartial_T_6 = cat(putPartial_hi, putPartial_lo) node _putPartial_legal_T = leq(UInt<1>(0h0), write_packet.lg_size) node _putPartial_legal_T_1 = leq(write_packet.lg_size, UInt<4>(0hc)) node _putPartial_legal_T_2 = and(_putPartial_legal_T, _putPartial_legal_T_1) node _putPartial_legal_T_3 = or(UInt<1>(0h0), _putPartial_legal_T_2) node _putPartial_legal_T_4 = xor(UInt<1>(0h0), UInt<14>(0h3000)) node _putPartial_legal_T_5 = cvt(_putPartial_legal_T_4) node _putPartial_legal_T_6 = and(_putPartial_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_7 = asSInt(_putPartial_legal_T_6) node _putPartial_legal_T_8 = eq(_putPartial_legal_T_7, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_9 = and(_putPartial_legal_T_3, _putPartial_legal_T_8) node _putPartial_legal_T_10 = leq(UInt<1>(0h0), write_packet.lg_size) node _putPartial_legal_T_11 = leq(write_packet.lg_size, UInt<3>(0h6)) node _putPartial_legal_T_12 = and(_putPartial_legal_T_10, _putPartial_legal_T_11) node _putPartial_legal_T_13 = or(UInt<1>(0h0), _putPartial_legal_T_12) node _putPartial_legal_T_14 = xor(UInt<1>(0h0), UInt<1>(0h0)) node _putPartial_legal_T_15 = cvt(_putPartial_legal_T_14) node _putPartial_legal_T_16 = and(_putPartial_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _putPartial_legal_T_17 = asSInt(_putPartial_legal_T_16) node _putPartial_legal_T_18 = eq(_putPartial_legal_T_17, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_19 = xor(UInt<1>(0h0), UInt<21>(0h100000)) node _putPartial_legal_T_20 = cvt(_putPartial_legal_T_19) node _putPartial_legal_T_21 = and(_putPartial_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _putPartial_legal_T_22 = asSInt(_putPartial_legal_T_21) node _putPartial_legal_T_23 = eq(_putPartial_legal_T_22, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_24 = xor(UInt<1>(0h0), UInt<26>(0h2000000)) node _putPartial_legal_T_25 = cvt(_putPartial_legal_T_24) node _putPartial_legal_T_26 = and(_putPartial_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_27 = asSInt(_putPartial_legal_T_26) node _putPartial_legal_T_28 = eq(_putPartial_legal_T_27, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_29 = xor(UInt<1>(0h0), UInt<26>(0h2010000)) node _putPartial_legal_T_30 = cvt(_putPartial_legal_T_29) node _putPartial_legal_T_31 = and(_putPartial_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_32 = asSInt(_putPartial_legal_T_31) node _putPartial_legal_T_33 = eq(_putPartial_legal_T_32, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_34 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putPartial_legal_T_35 = cvt(_putPartial_legal_T_34) node _putPartial_legal_T_36 = and(_putPartial_legal_T_35, asSInt(UInt<33>(0h98000000))) node _putPartial_legal_T_37 = asSInt(_putPartial_legal_T_36) node _putPartial_legal_T_38 = eq(_putPartial_legal_T_37, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_39 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putPartial_legal_T_40 = cvt(_putPartial_legal_T_39) node _putPartial_legal_T_41 = and(_putPartial_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_42 = asSInt(_putPartial_legal_T_41) node _putPartial_legal_T_43 = eq(_putPartial_legal_T_42, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_44 = xor(UInt<1>(0h0), UInt<29>(0h10000000)) node _putPartial_legal_T_45 = cvt(_putPartial_legal_T_44) node _putPartial_legal_T_46 = and(_putPartial_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_47 = asSInt(_putPartial_legal_T_46) node _putPartial_legal_T_48 = eq(_putPartial_legal_T_47, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_49 = xor(UInt<1>(0h0), UInt<32>(0h80000000)) node _putPartial_legal_T_50 = cvt(_putPartial_legal_T_49) node _putPartial_legal_T_51 = and(_putPartial_legal_T_50, asSInt(UInt<33>(0h90000000))) node _putPartial_legal_T_52 = asSInt(_putPartial_legal_T_51) node _putPartial_legal_T_53 = eq(_putPartial_legal_T_52, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_54 = or(_putPartial_legal_T_18, _putPartial_legal_T_23) node _putPartial_legal_T_55 = or(_putPartial_legal_T_54, _putPartial_legal_T_28) node _putPartial_legal_T_56 = or(_putPartial_legal_T_55, _putPartial_legal_T_33) node _putPartial_legal_T_57 = or(_putPartial_legal_T_56, _putPartial_legal_T_38) node _putPartial_legal_T_58 = or(_putPartial_legal_T_57, _putPartial_legal_T_43) node _putPartial_legal_T_59 = or(_putPartial_legal_T_58, _putPartial_legal_T_48) node _putPartial_legal_T_60 = or(_putPartial_legal_T_59, _putPartial_legal_T_53) node _putPartial_legal_T_61 = and(_putPartial_legal_T_13, _putPartial_legal_T_60) node _putPartial_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _putPartial_legal_T_63 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _putPartial_legal_T_64 = cvt(_putPartial_legal_T_63) node _putPartial_legal_T_65 = and(_putPartial_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_66 = asSInt(_putPartial_legal_T_65) node _putPartial_legal_T_67 = eq(_putPartial_legal_T_66, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_68 = and(_putPartial_legal_T_62, _putPartial_legal_T_67) node _putPartial_legal_T_69 = or(UInt<1>(0h0), _putPartial_legal_T_9) node _putPartial_legal_T_70 = or(_putPartial_legal_T_69, _putPartial_legal_T_61) node putPartial_legal = or(_putPartial_legal_T_70, _putPartial_legal_T_68) wire putPartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect putPartial.opcode, UInt<1>(0h1) connect putPartial.param, UInt<1>(0h0) connect putPartial.size, write_packet.lg_size connect putPartial.source, _putPartial_T_1 connect putPartial.address, UInt<1>(0h0) connect putPartial.mask, _putPartial_T_6 connect putPartial.data, _putPartial_T_5 connect putPartial.corrupt, UInt<1>(0h0) wire untranslated_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} node _xactBusy_fire_T = and(untranslated_a.ready, untranslated_a.valid) node _xactBusy_fire_T_1 = eq(state, UInt<2>(0h1)) node _xactBusy_fire_T_2 = and(_xactBusy_fire_T, _xactBusy_fire_T_1) connect xactBusy_fire, _xactBusy_fire_T_2 node _untranslated_a_valid_T = eq(state, UInt<2>(0h1)) node _untranslated_a_valid_T_1 = eq(state, UInt<2>(0h2)) node _untranslated_a_valid_T_2 = or(_untranslated_a_valid_T, _untranslated_a_valid_T_1) node _untranslated_a_valid_T_3 = andr(xactBusy) node _untranslated_a_valid_T_4 = eq(_untranslated_a_valid_T_3, UInt<1>(0h0)) node _untranslated_a_valid_T_5 = and(_untranslated_a_valid_T_2, _untranslated_a_valid_T_4) connect untranslated_a.valid, _untranslated_a_valid_T_5 node _untranslated_a_bits_tl_a_T = mux(write_packet.is_full, putFull, putPartial) connect untranslated_a.bits.tl_a, _untranslated_a_bits_tl_a_T connect untranslated_a.bits.vaddr, write_packet.vaddr connect untranslated_a.bits.status, req.status wire retry_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} inst shadow_retry_a of Queue1_TLBundleAWithInfo_2 connect shadow_retry_a.clock, clock connect shadow_retry_a.reset, reset connect shadow_retry_a.io.enq.valid, UInt<1>(0h0) invalidate shadow_retry_a.io.enq.bits.status.uie invalidate shadow_retry_a.io.enq.bits.status.sie invalidate shadow_retry_a.io.enq.bits.status.hie invalidate shadow_retry_a.io.enq.bits.status.mie invalidate shadow_retry_a.io.enq.bits.status.upie invalidate shadow_retry_a.io.enq.bits.status.spie invalidate shadow_retry_a.io.enq.bits.status.ube invalidate shadow_retry_a.io.enq.bits.status.mpie invalidate shadow_retry_a.io.enq.bits.status.spp invalidate shadow_retry_a.io.enq.bits.status.vs invalidate shadow_retry_a.io.enq.bits.status.mpp invalidate shadow_retry_a.io.enq.bits.status.fs invalidate shadow_retry_a.io.enq.bits.status.xs invalidate shadow_retry_a.io.enq.bits.status.mprv invalidate shadow_retry_a.io.enq.bits.status.sum invalidate shadow_retry_a.io.enq.bits.status.mxr invalidate shadow_retry_a.io.enq.bits.status.tvm invalidate shadow_retry_a.io.enq.bits.status.tw invalidate shadow_retry_a.io.enq.bits.status.tsr invalidate shadow_retry_a.io.enq.bits.status.zero1 invalidate shadow_retry_a.io.enq.bits.status.sd_rv32 invalidate shadow_retry_a.io.enq.bits.status.uxl invalidate shadow_retry_a.io.enq.bits.status.sxl invalidate shadow_retry_a.io.enq.bits.status.sbe invalidate shadow_retry_a.io.enq.bits.status.mbe invalidate shadow_retry_a.io.enq.bits.status.gva invalidate shadow_retry_a.io.enq.bits.status.mpv invalidate shadow_retry_a.io.enq.bits.status.zero2 invalidate shadow_retry_a.io.enq.bits.status.sd invalidate shadow_retry_a.io.enq.bits.status.v invalidate shadow_retry_a.io.enq.bits.status.prv invalidate shadow_retry_a.io.enq.bits.status.dv invalidate shadow_retry_a.io.enq.bits.status.dprv invalidate shadow_retry_a.io.enq.bits.status.isa invalidate shadow_retry_a.io.enq.bits.status.wfi invalidate shadow_retry_a.io.enq.bits.status.cease invalidate shadow_retry_a.io.enq.bits.status.debug invalidate shadow_retry_a.io.enq.bits.vaddr invalidate shadow_retry_a.io.enq.bits.tl_a.corrupt invalidate shadow_retry_a.io.enq.bits.tl_a.data invalidate shadow_retry_a.io.enq.bits.tl_a.mask invalidate shadow_retry_a.io.enq.bits.tl_a.address invalidate shadow_retry_a.io.enq.bits.tl_a.source invalidate shadow_retry_a.io.enq.bits.tl_a.size invalidate shadow_retry_a.io.enq.bits.tl_a.param invalidate shadow_retry_a.io.enq.bits.tl_a.opcode inst tlb_arb of Arbiter3_TLBundleAWithInfo connect tlb_arb.clock, clock connect tlb_arb.reset, reset connect tlb_arb.io.in[0], retry_a connect tlb_arb.io.in[1], shadow_retry_a.io.deq connect tlb_arb.io.in[2], untranslated_a inst tlb_q of Queue1_TLBundleAWithInfo_3 connect tlb_q.clock, clock connect tlb_q.reset, reset connect tlb_q.io.enq, tlb_arb.io.out node _io_tlb_req_valid_T = and(tlb_q.io.deq.ready, tlb_q.io.deq.valid) connect io.tlb.req.valid, _io_tlb_req_valid_T invalidate io.tlb.req.bits.status.uie invalidate io.tlb.req.bits.status.sie invalidate io.tlb.req.bits.status.hie invalidate io.tlb.req.bits.status.mie invalidate io.tlb.req.bits.status.upie invalidate io.tlb.req.bits.status.spie invalidate io.tlb.req.bits.status.ube invalidate io.tlb.req.bits.status.mpie invalidate io.tlb.req.bits.status.spp invalidate io.tlb.req.bits.status.vs invalidate io.tlb.req.bits.status.mpp invalidate io.tlb.req.bits.status.fs invalidate io.tlb.req.bits.status.xs invalidate io.tlb.req.bits.status.mprv invalidate io.tlb.req.bits.status.sum invalidate io.tlb.req.bits.status.mxr invalidate io.tlb.req.bits.status.tvm invalidate io.tlb.req.bits.status.tw invalidate io.tlb.req.bits.status.tsr invalidate io.tlb.req.bits.status.zero1 invalidate io.tlb.req.bits.status.sd_rv32 invalidate io.tlb.req.bits.status.uxl invalidate io.tlb.req.bits.status.sxl invalidate io.tlb.req.bits.status.sbe invalidate io.tlb.req.bits.status.mbe invalidate io.tlb.req.bits.status.gva invalidate io.tlb.req.bits.status.mpv invalidate io.tlb.req.bits.status.zero2 invalidate io.tlb.req.bits.status.sd invalidate io.tlb.req.bits.status.v invalidate io.tlb.req.bits.status.prv invalidate io.tlb.req.bits.status.dv invalidate io.tlb.req.bits.status.dprv invalidate io.tlb.req.bits.status.isa invalidate io.tlb.req.bits.status.wfi invalidate io.tlb.req.bits.status.cease invalidate io.tlb.req.bits.status.debug invalidate io.tlb.req.bits.tlb_req.v invalidate io.tlb.req.bits.tlb_req.prv invalidate io.tlb.req.bits.tlb_req.cmd invalidate io.tlb.req.bits.tlb_req.size invalidate io.tlb.req.bits.tlb_req.passthrough invalidate io.tlb.req.bits.tlb_req.vaddr connect io.tlb.req.bits.tlb_req.vaddr, tlb_q.io.deq.bits.vaddr connect io.tlb.req.bits.tlb_req.passthrough, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.size, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.cmd, UInt<1>(0h1) connect io.tlb.req.bits.status, tlb_q.io.deq.bits.status inst translate_q of Queue1_TLBundleAWithInfo_4 connect translate_q.clock, clock connect translate_q.reset, reset connect translate_q.io.enq, tlb_q.io.deq when retry_a.valid : connect translate_q.io.enq.valid, UInt<1>(0h0) connect shadow_retry_a.io.enq.valid, tlb_q.io.deq.valid connect shadow_retry_a.io.enq.bits.status.uie, tlb_q.io.deq.bits.status.uie connect shadow_retry_a.io.enq.bits.status.sie, tlb_q.io.deq.bits.status.sie connect shadow_retry_a.io.enq.bits.status.hie, tlb_q.io.deq.bits.status.hie connect shadow_retry_a.io.enq.bits.status.mie, tlb_q.io.deq.bits.status.mie connect shadow_retry_a.io.enq.bits.status.upie, tlb_q.io.deq.bits.status.upie connect shadow_retry_a.io.enq.bits.status.spie, tlb_q.io.deq.bits.status.spie connect shadow_retry_a.io.enq.bits.status.ube, tlb_q.io.deq.bits.status.ube connect shadow_retry_a.io.enq.bits.status.mpie, tlb_q.io.deq.bits.status.mpie connect shadow_retry_a.io.enq.bits.status.spp, tlb_q.io.deq.bits.status.spp connect shadow_retry_a.io.enq.bits.status.vs, tlb_q.io.deq.bits.status.vs connect shadow_retry_a.io.enq.bits.status.mpp, tlb_q.io.deq.bits.status.mpp connect shadow_retry_a.io.enq.bits.status.fs, tlb_q.io.deq.bits.status.fs connect shadow_retry_a.io.enq.bits.status.xs, tlb_q.io.deq.bits.status.xs connect shadow_retry_a.io.enq.bits.status.mprv, tlb_q.io.deq.bits.status.mprv connect shadow_retry_a.io.enq.bits.status.sum, tlb_q.io.deq.bits.status.sum connect shadow_retry_a.io.enq.bits.status.mxr, tlb_q.io.deq.bits.status.mxr connect shadow_retry_a.io.enq.bits.status.tvm, tlb_q.io.deq.bits.status.tvm connect shadow_retry_a.io.enq.bits.status.tw, tlb_q.io.deq.bits.status.tw connect shadow_retry_a.io.enq.bits.status.tsr, tlb_q.io.deq.bits.status.tsr connect shadow_retry_a.io.enq.bits.status.zero1, tlb_q.io.deq.bits.status.zero1 connect shadow_retry_a.io.enq.bits.status.sd_rv32, tlb_q.io.deq.bits.status.sd_rv32 connect shadow_retry_a.io.enq.bits.status.uxl, tlb_q.io.deq.bits.status.uxl connect shadow_retry_a.io.enq.bits.status.sxl, tlb_q.io.deq.bits.status.sxl connect shadow_retry_a.io.enq.bits.status.sbe, tlb_q.io.deq.bits.status.sbe connect shadow_retry_a.io.enq.bits.status.mbe, tlb_q.io.deq.bits.status.mbe connect shadow_retry_a.io.enq.bits.status.gva, tlb_q.io.deq.bits.status.gva connect shadow_retry_a.io.enq.bits.status.mpv, tlb_q.io.deq.bits.status.mpv connect shadow_retry_a.io.enq.bits.status.zero2, tlb_q.io.deq.bits.status.zero2 connect shadow_retry_a.io.enq.bits.status.sd, tlb_q.io.deq.bits.status.sd connect shadow_retry_a.io.enq.bits.status.v, tlb_q.io.deq.bits.status.v connect shadow_retry_a.io.enq.bits.status.prv, tlb_q.io.deq.bits.status.prv connect shadow_retry_a.io.enq.bits.status.dv, tlb_q.io.deq.bits.status.dv connect shadow_retry_a.io.enq.bits.status.dprv, tlb_q.io.deq.bits.status.dprv connect shadow_retry_a.io.enq.bits.status.isa, tlb_q.io.deq.bits.status.isa connect shadow_retry_a.io.enq.bits.status.wfi, tlb_q.io.deq.bits.status.wfi connect shadow_retry_a.io.enq.bits.status.cease, tlb_q.io.deq.bits.status.cease connect shadow_retry_a.io.enq.bits.status.debug, tlb_q.io.deq.bits.status.debug connect shadow_retry_a.io.enq.bits.vaddr, tlb_q.io.deq.bits.vaddr connect shadow_retry_a.io.enq.bits.tl_a.corrupt, tlb_q.io.deq.bits.tl_a.corrupt connect shadow_retry_a.io.enq.bits.tl_a.data, tlb_q.io.deq.bits.tl_a.data connect shadow_retry_a.io.enq.bits.tl_a.mask, tlb_q.io.deq.bits.tl_a.mask connect shadow_retry_a.io.enq.bits.tl_a.address, tlb_q.io.deq.bits.tl_a.address connect shadow_retry_a.io.enq.bits.tl_a.source, tlb_q.io.deq.bits.tl_a.source connect shadow_retry_a.io.enq.bits.tl_a.size, tlb_q.io.deq.bits.tl_a.size connect shadow_retry_a.io.enq.bits.tl_a.param, tlb_q.io.deq.bits.tl_a.param connect shadow_retry_a.io.enq.bits.tl_a.opcode, tlb_q.io.deq.bits.tl_a.opcode node _translate_q_io_deq_ready_T = or(nodeOut.a.ready, io.tlb.resp.miss) connect translate_q.io.deq.ready, _translate_q_io_deq_ready_T node _retry_a_valid_T = and(translate_q.io.deq.valid, io.tlb.resp.miss) connect retry_a.valid, _retry_a_valid_T connect retry_a.bits, translate_q.io.deq.bits node _T = eq(retry_a.ready, UInt<1>(0h0)) node _T_1 = and(retry_a.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at DMA.scala:545 assert(!(retry_a.valid && !retry_a.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _nodeOut_a_valid_T = eq(io.tlb.resp.miss, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(translate_q.io.deq.valid, _nodeOut_a_valid_T) connect nodeOut.a.valid, _nodeOut_a_valid_T_1 connect nodeOut.a.bits, translate_q.io.deq.bits.tl_a reg nodeOut_a_bits_address_REG : UInt<1>, clock connect nodeOut_a_bits_address_REG, io.tlb.req.valid reg nodeOut_a_bits_address_buf : UInt<32>, clock when nodeOut_a_bits_address_REG : connect nodeOut_a_bits_address_buf, io.tlb.resp.paddr node _nodeOut_a_bits_address_T = mux(nodeOut_a_bits_address_REG, io.tlb.resp.paddr, nodeOut_a_bits_address_buf) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeOut_d_ready_T = orr(xactBusy) connect nodeOut.d.ready, _nodeOut_d_ready_T node _T_6 = and(untranslated_a.ready, untranslated_a.valid) when _T_6 : node _T_7 = eq(state, UInt<2>(0h1)) when _T_7 : node _beatsLeft_T = sub(write_beats, UInt<1>(0h1)) node _beatsLeft_T_1 = tail(_beatsLeft_T, 1) connect beatsLeft, _beatsLeft_T_1 node _next_vaddr_T = add(req.vaddr, write_packet.bytes_written) node next_vaddr = tail(_next_vaddr_T, 1) connect req.vaddr, next_vaddr node _bytesSent_T = add(bytesSent, write_packet.bytes_written_per_beat[_bytes_written_this_beat_T]) node _bytesSent_T_1 = tail(_bytesSent_T, 1) connect bytesSent, _bytesSent_T_1 node _T_8 = eq(write_beats, UInt<1>(0h1)) when _T_8 : node _T_9 = geq(write_packet.bytes_written_per_beat[_bytes_written_this_beat_T], bytesLeft) when _T_9 : connect state_machine_ready_for_req, UInt<1>(0h1) connect state, UInt<2>(0h0) else : connect state, UInt<2>(0h2) else : node _T_10 = eq(state, UInt<2>(0h2)) when _T_10 : node _beatsLeft_T_2 = sub(beatsLeft, UInt<1>(0h1)) node _beatsLeft_T_3 = tail(_beatsLeft_T_2, 1) connect beatsLeft, _beatsLeft_T_3 node _bytesSent_T_2 = add(bytesSent, write_packet.bytes_written_per_beat[_bytes_written_this_beat_T]) node _bytesSent_T_3 = tail(_bytesSent_T_2, 1) connect bytesSent, _bytesSent_T_3 node _T_11 = gt(beatsLeft, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at DMA.scala:575 assert(beatsLeft > 0.U)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(beatsLeft, UInt<1>(0h1)) when _T_15 : node _T_16 = geq(write_packet.bytes_written_per_beat[_bytes_written_this_beat_T], bytesLeft) when _T_16 : connect state_machine_ready_for_req, UInt<1>(0h1) connect state, UInt<2>(0h0) else : connect state, UInt<2>(0h1) node _T_17 = and(io.req.ready, io.req.valid) when _T_17 : wire pooled_v1 : SInt<8>[64] wire _pooled_v1_WIRE : UInt<512> connect _pooled_v1_WIRE, io.req.bits.data node _pooled_v1_T = bits(_pooled_v1_WIRE, 7, 0) node _pooled_v1_T_1 = asSInt(_pooled_v1_T) connect pooled_v1[0], _pooled_v1_T_1 node _pooled_v1_T_2 = bits(_pooled_v1_WIRE, 15, 8) node _pooled_v1_T_3 = asSInt(_pooled_v1_T_2) connect pooled_v1[1], _pooled_v1_T_3 node _pooled_v1_T_4 = bits(_pooled_v1_WIRE, 23, 16) node _pooled_v1_T_5 = asSInt(_pooled_v1_T_4) connect pooled_v1[2], _pooled_v1_T_5 node _pooled_v1_T_6 = bits(_pooled_v1_WIRE, 31, 24) node _pooled_v1_T_7 = asSInt(_pooled_v1_T_6) connect pooled_v1[3], _pooled_v1_T_7 node _pooled_v1_T_8 = bits(_pooled_v1_WIRE, 39, 32) node _pooled_v1_T_9 = asSInt(_pooled_v1_T_8) connect pooled_v1[4], _pooled_v1_T_9 node _pooled_v1_T_10 = bits(_pooled_v1_WIRE, 47, 40) node _pooled_v1_T_11 = asSInt(_pooled_v1_T_10) connect pooled_v1[5], _pooled_v1_T_11 node _pooled_v1_T_12 = bits(_pooled_v1_WIRE, 55, 48) node _pooled_v1_T_13 = asSInt(_pooled_v1_T_12) connect pooled_v1[6], _pooled_v1_T_13 node _pooled_v1_T_14 = bits(_pooled_v1_WIRE, 63, 56) node _pooled_v1_T_15 = asSInt(_pooled_v1_T_14) connect pooled_v1[7], _pooled_v1_T_15 node _pooled_v1_T_16 = bits(_pooled_v1_WIRE, 71, 64) node _pooled_v1_T_17 = asSInt(_pooled_v1_T_16) connect pooled_v1[8], _pooled_v1_T_17 node _pooled_v1_T_18 = bits(_pooled_v1_WIRE, 79, 72) node _pooled_v1_T_19 = asSInt(_pooled_v1_T_18) connect pooled_v1[9], _pooled_v1_T_19 node _pooled_v1_T_20 = bits(_pooled_v1_WIRE, 87, 80) node _pooled_v1_T_21 = asSInt(_pooled_v1_T_20) connect pooled_v1[10], _pooled_v1_T_21 node _pooled_v1_T_22 = bits(_pooled_v1_WIRE, 95, 88) node _pooled_v1_T_23 = asSInt(_pooled_v1_T_22) connect pooled_v1[11], _pooled_v1_T_23 node _pooled_v1_T_24 = bits(_pooled_v1_WIRE, 103, 96) node _pooled_v1_T_25 = asSInt(_pooled_v1_T_24) connect pooled_v1[12], _pooled_v1_T_25 node _pooled_v1_T_26 = bits(_pooled_v1_WIRE, 111, 104) node _pooled_v1_T_27 = asSInt(_pooled_v1_T_26) connect pooled_v1[13], _pooled_v1_T_27 node _pooled_v1_T_28 = bits(_pooled_v1_WIRE, 119, 112) node _pooled_v1_T_29 = asSInt(_pooled_v1_T_28) connect pooled_v1[14], _pooled_v1_T_29 node _pooled_v1_T_30 = bits(_pooled_v1_WIRE, 127, 120) node _pooled_v1_T_31 = asSInt(_pooled_v1_T_30) connect pooled_v1[15], _pooled_v1_T_31 node _pooled_v1_T_32 = bits(_pooled_v1_WIRE, 135, 128) node _pooled_v1_T_33 = asSInt(_pooled_v1_T_32) connect pooled_v1[16], _pooled_v1_T_33 node _pooled_v1_T_34 = bits(_pooled_v1_WIRE, 143, 136) node _pooled_v1_T_35 = asSInt(_pooled_v1_T_34) connect pooled_v1[17], _pooled_v1_T_35 node _pooled_v1_T_36 = bits(_pooled_v1_WIRE, 151, 144) node _pooled_v1_T_37 = asSInt(_pooled_v1_T_36) connect pooled_v1[18], _pooled_v1_T_37 node _pooled_v1_T_38 = bits(_pooled_v1_WIRE, 159, 152) node _pooled_v1_T_39 = asSInt(_pooled_v1_T_38) connect pooled_v1[19], _pooled_v1_T_39 node _pooled_v1_T_40 = bits(_pooled_v1_WIRE, 167, 160) node _pooled_v1_T_41 = asSInt(_pooled_v1_T_40) connect pooled_v1[20], _pooled_v1_T_41 node _pooled_v1_T_42 = bits(_pooled_v1_WIRE, 175, 168) node _pooled_v1_T_43 = asSInt(_pooled_v1_T_42) connect pooled_v1[21], _pooled_v1_T_43 node _pooled_v1_T_44 = bits(_pooled_v1_WIRE, 183, 176) node _pooled_v1_T_45 = asSInt(_pooled_v1_T_44) connect pooled_v1[22], _pooled_v1_T_45 node _pooled_v1_T_46 = bits(_pooled_v1_WIRE, 191, 184) node _pooled_v1_T_47 = asSInt(_pooled_v1_T_46) connect pooled_v1[23], _pooled_v1_T_47 node _pooled_v1_T_48 = bits(_pooled_v1_WIRE, 199, 192) node _pooled_v1_T_49 = asSInt(_pooled_v1_T_48) connect pooled_v1[24], _pooled_v1_T_49 node _pooled_v1_T_50 = bits(_pooled_v1_WIRE, 207, 200) node _pooled_v1_T_51 = asSInt(_pooled_v1_T_50) connect pooled_v1[25], _pooled_v1_T_51 node _pooled_v1_T_52 = bits(_pooled_v1_WIRE, 215, 208) node _pooled_v1_T_53 = asSInt(_pooled_v1_T_52) connect pooled_v1[26], _pooled_v1_T_53 node _pooled_v1_T_54 = bits(_pooled_v1_WIRE, 223, 216) node _pooled_v1_T_55 = asSInt(_pooled_v1_T_54) connect pooled_v1[27], _pooled_v1_T_55 node _pooled_v1_T_56 = bits(_pooled_v1_WIRE, 231, 224) node _pooled_v1_T_57 = asSInt(_pooled_v1_T_56) connect pooled_v1[28], _pooled_v1_T_57 node _pooled_v1_T_58 = bits(_pooled_v1_WIRE, 239, 232) node _pooled_v1_T_59 = asSInt(_pooled_v1_T_58) connect pooled_v1[29], _pooled_v1_T_59 node _pooled_v1_T_60 = bits(_pooled_v1_WIRE, 247, 240) node _pooled_v1_T_61 = asSInt(_pooled_v1_T_60) connect pooled_v1[30], _pooled_v1_T_61 node _pooled_v1_T_62 = bits(_pooled_v1_WIRE, 255, 248) node _pooled_v1_T_63 = asSInt(_pooled_v1_T_62) connect pooled_v1[31], _pooled_v1_T_63 node _pooled_v1_T_64 = bits(_pooled_v1_WIRE, 263, 256) node _pooled_v1_T_65 = asSInt(_pooled_v1_T_64) connect pooled_v1[32], _pooled_v1_T_65 node _pooled_v1_T_66 = bits(_pooled_v1_WIRE, 271, 264) node _pooled_v1_T_67 = asSInt(_pooled_v1_T_66) connect pooled_v1[33], _pooled_v1_T_67 node _pooled_v1_T_68 = bits(_pooled_v1_WIRE, 279, 272) node _pooled_v1_T_69 = asSInt(_pooled_v1_T_68) connect pooled_v1[34], _pooled_v1_T_69 node _pooled_v1_T_70 = bits(_pooled_v1_WIRE, 287, 280) node _pooled_v1_T_71 = asSInt(_pooled_v1_T_70) connect pooled_v1[35], _pooled_v1_T_71 node _pooled_v1_T_72 = bits(_pooled_v1_WIRE, 295, 288) node _pooled_v1_T_73 = asSInt(_pooled_v1_T_72) connect pooled_v1[36], _pooled_v1_T_73 node _pooled_v1_T_74 = bits(_pooled_v1_WIRE, 303, 296) node _pooled_v1_T_75 = asSInt(_pooled_v1_T_74) connect pooled_v1[37], _pooled_v1_T_75 node _pooled_v1_T_76 = bits(_pooled_v1_WIRE, 311, 304) node _pooled_v1_T_77 = asSInt(_pooled_v1_T_76) connect pooled_v1[38], _pooled_v1_T_77 node _pooled_v1_T_78 = bits(_pooled_v1_WIRE, 319, 312) node _pooled_v1_T_79 = asSInt(_pooled_v1_T_78) connect pooled_v1[39], _pooled_v1_T_79 node _pooled_v1_T_80 = bits(_pooled_v1_WIRE, 327, 320) node _pooled_v1_T_81 = asSInt(_pooled_v1_T_80) connect pooled_v1[40], _pooled_v1_T_81 node _pooled_v1_T_82 = bits(_pooled_v1_WIRE, 335, 328) node _pooled_v1_T_83 = asSInt(_pooled_v1_T_82) connect pooled_v1[41], _pooled_v1_T_83 node _pooled_v1_T_84 = bits(_pooled_v1_WIRE, 343, 336) node _pooled_v1_T_85 = asSInt(_pooled_v1_T_84) connect pooled_v1[42], _pooled_v1_T_85 node _pooled_v1_T_86 = bits(_pooled_v1_WIRE, 351, 344) node _pooled_v1_T_87 = asSInt(_pooled_v1_T_86) connect pooled_v1[43], _pooled_v1_T_87 node _pooled_v1_T_88 = bits(_pooled_v1_WIRE, 359, 352) node _pooled_v1_T_89 = asSInt(_pooled_v1_T_88) connect pooled_v1[44], _pooled_v1_T_89 node _pooled_v1_T_90 = bits(_pooled_v1_WIRE, 367, 360) node _pooled_v1_T_91 = asSInt(_pooled_v1_T_90) connect pooled_v1[45], _pooled_v1_T_91 node _pooled_v1_T_92 = bits(_pooled_v1_WIRE, 375, 368) node _pooled_v1_T_93 = asSInt(_pooled_v1_T_92) connect pooled_v1[46], _pooled_v1_T_93 node _pooled_v1_T_94 = bits(_pooled_v1_WIRE, 383, 376) node _pooled_v1_T_95 = asSInt(_pooled_v1_T_94) connect pooled_v1[47], _pooled_v1_T_95 node _pooled_v1_T_96 = bits(_pooled_v1_WIRE, 391, 384) node _pooled_v1_T_97 = asSInt(_pooled_v1_T_96) connect pooled_v1[48], _pooled_v1_T_97 node _pooled_v1_T_98 = bits(_pooled_v1_WIRE, 399, 392) node _pooled_v1_T_99 = asSInt(_pooled_v1_T_98) connect pooled_v1[49], _pooled_v1_T_99 node _pooled_v1_T_100 = bits(_pooled_v1_WIRE, 407, 400) node _pooled_v1_T_101 = asSInt(_pooled_v1_T_100) connect pooled_v1[50], _pooled_v1_T_101 node _pooled_v1_T_102 = bits(_pooled_v1_WIRE, 415, 408) node _pooled_v1_T_103 = asSInt(_pooled_v1_T_102) connect pooled_v1[51], _pooled_v1_T_103 node _pooled_v1_T_104 = bits(_pooled_v1_WIRE, 423, 416) node _pooled_v1_T_105 = asSInt(_pooled_v1_T_104) connect pooled_v1[52], _pooled_v1_T_105 node _pooled_v1_T_106 = bits(_pooled_v1_WIRE, 431, 424) node _pooled_v1_T_107 = asSInt(_pooled_v1_T_106) connect pooled_v1[53], _pooled_v1_T_107 node _pooled_v1_T_108 = bits(_pooled_v1_WIRE, 439, 432) node _pooled_v1_T_109 = asSInt(_pooled_v1_T_108) connect pooled_v1[54], _pooled_v1_T_109 node _pooled_v1_T_110 = bits(_pooled_v1_WIRE, 447, 440) node _pooled_v1_T_111 = asSInt(_pooled_v1_T_110) connect pooled_v1[55], _pooled_v1_T_111 node _pooled_v1_T_112 = bits(_pooled_v1_WIRE, 455, 448) node _pooled_v1_T_113 = asSInt(_pooled_v1_T_112) connect pooled_v1[56], _pooled_v1_T_113 node _pooled_v1_T_114 = bits(_pooled_v1_WIRE, 463, 456) node _pooled_v1_T_115 = asSInt(_pooled_v1_T_114) connect pooled_v1[57], _pooled_v1_T_115 node _pooled_v1_T_116 = bits(_pooled_v1_WIRE, 471, 464) node _pooled_v1_T_117 = asSInt(_pooled_v1_T_116) connect pooled_v1[58], _pooled_v1_T_117 node _pooled_v1_T_118 = bits(_pooled_v1_WIRE, 479, 472) node _pooled_v1_T_119 = asSInt(_pooled_v1_T_118) connect pooled_v1[59], _pooled_v1_T_119 node _pooled_v1_T_120 = bits(_pooled_v1_WIRE, 487, 480) node _pooled_v1_T_121 = asSInt(_pooled_v1_T_120) connect pooled_v1[60], _pooled_v1_T_121 node _pooled_v1_T_122 = bits(_pooled_v1_WIRE, 495, 488) node _pooled_v1_T_123 = asSInt(_pooled_v1_T_122) connect pooled_v1[61], _pooled_v1_T_123 node _pooled_v1_T_124 = bits(_pooled_v1_WIRE, 503, 496) node _pooled_v1_T_125 = asSInt(_pooled_v1_T_124) connect pooled_v1[62], _pooled_v1_T_125 node _pooled_v1_T_126 = bits(_pooled_v1_WIRE, 511, 504) node _pooled_v1_T_127 = asSInt(_pooled_v1_T_126) connect pooled_v1[63], _pooled_v1_T_127 wire pooled_v2 : SInt<8>[64] wire _pooled_v2_WIRE : UInt<512> connect _pooled_v2_WIRE, data_single_block node _pooled_v2_T = bits(_pooled_v2_WIRE, 7, 0) node _pooled_v2_T_1 = asSInt(_pooled_v2_T) connect pooled_v2[0], _pooled_v2_T_1 node _pooled_v2_T_2 = bits(_pooled_v2_WIRE, 15, 8) node _pooled_v2_T_3 = asSInt(_pooled_v2_T_2) connect pooled_v2[1], _pooled_v2_T_3 node _pooled_v2_T_4 = bits(_pooled_v2_WIRE, 23, 16) node _pooled_v2_T_5 = asSInt(_pooled_v2_T_4) connect pooled_v2[2], _pooled_v2_T_5 node _pooled_v2_T_6 = bits(_pooled_v2_WIRE, 31, 24) node _pooled_v2_T_7 = asSInt(_pooled_v2_T_6) connect pooled_v2[3], _pooled_v2_T_7 node _pooled_v2_T_8 = bits(_pooled_v2_WIRE, 39, 32) node _pooled_v2_T_9 = asSInt(_pooled_v2_T_8) connect pooled_v2[4], _pooled_v2_T_9 node _pooled_v2_T_10 = bits(_pooled_v2_WIRE, 47, 40) node _pooled_v2_T_11 = asSInt(_pooled_v2_T_10) connect pooled_v2[5], _pooled_v2_T_11 node _pooled_v2_T_12 = bits(_pooled_v2_WIRE, 55, 48) node _pooled_v2_T_13 = asSInt(_pooled_v2_T_12) connect pooled_v2[6], _pooled_v2_T_13 node _pooled_v2_T_14 = bits(_pooled_v2_WIRE, 63, 56) node _pooled_v2_T_15 = asSInt(_pooled_v2_T_14) connect pooled_v2[7], _pooled_v2_T_15 node _pooled_v2_T_16 = bits(_pooled_v2_WIRE, 71, 64) node _pooled_v2_T_17 = asSInt(_pooled_v2_T_16) connect pooled_v2[8], _pooled_v2_T_17 node _pooled_v2_T_18 = bits(_pooled_v2_WIRE, 79, 72) node _pooled_v2_T_19 = asSInt(_pooled_v2_T_18) connect pooled_v2[9], _pooled_v2_T_19 node _pooled_v2_T_20 = bits(_pooled_v2_WIRE, 87, 80) node _pooled_v2_T_21 = asSInt(_pooled_v2_T_20) connect pooled_v2[10], _pooled_v2_T_21 node _pooled_v2_T_22 = bits(_pooled_v2_WIRE, 95, 88) node _pooled_v2_T_23 = asSInt(_pooled_v2_T_22) connect pooled_v2[11], _pooled_v2_T_23 node _pooled_v2_T_24 = bits(_pooled_v2_WIRE, 103, 96) node _pooled_v2_T_25 = asSInt(_pooled_v2_T_24) connect pooled_v2[12], _pooled_v2_T_25 node _pooled_v2_T_26 = bits(_pooled_v2_WIRE, 111, 104) node _pooled_v2_T_27 = asSInt(_pooled_v2_T_26) connect pooled_v2[13], _pooled_v2_T_27 node _pooled_v2_T_28 = bits(_pooled_v2_WIRE, 119, 112) node _pooled_v2_T_29 = asSInt(_pooled_v2_T_28) connect pooled_v2[14], _pooled_v2_T_29 node _pooled_v2_T_30 = bits(_pooled_v2_WIRE, 127, 120) node _pooled_v2_T_31 = asSInt(_pooled_v2_T_30) connect pooled_v2[15], _pooled_v2_T_31 node _pooled_v2_T_32 = bits(_pooled_v2_WIRE, 135, 128) node _pooled_v2_T_33 = asSInt(_pooled_v2_T_32) connect pooled_v2[16], _pooled_v2_T_33 node _pooled_v2_T_34 = bits(_pooled_v2_WIRE, 143, 136) node _pooled_v2_T_35 = asSInt(_pooled_v2_T_34) connect pooled_v2[17], _pooled_v2_T_35 node _pooled_v2_T_36 = bits(_pooled_v2_WIRE, 151, 144) node _pooled_v2_T_37 = asSInt(_pooled_v2_T_36) connect pooled_v2[18], _pooled_v2_T_37 node _pooled_v2_T_38 = bits(_pooled_v2_WIRE, 159, 152) node _pooled_v2_T_39 = asSInt(_pooled_v2_T_38) connect pooled_v2[19], _pooled_v2_T_39 node _pooled_v2_T_40 = bits(_pooled_v2_WIRE, 167, 160) node _pooled_v2_T_41 = asSInt(_pooled_v2_T_40) connect pooled_v2[20], _pooled_v2_T_41 node _pooled_v2_T_42 = bits(_pooled_v2_WIRE, 175, 168) node _pooled_v2_T_43 = asSInt(_pooled_v2_T_42) connect pooled_v2[21], _pooled_v2_T_43 node _pooled_v2_T_44 = bits(_pooled_v2_WIRE, 183, 176) node _pooled_v2_T_45 = asSInt(_pooled_v2_T_44) connect pooled_v2[22], _pooled_v2_T_45 node _pooled_v2_T_46 = bits(_pooled_v2_WIRE, 191, 184) node _pooled_v2_T_47 = asSInt(_pooled_v2_T_46) connect pooled_v2[23], _pooled_v2_T_47 node _pooled_v2_T_48 = bits(_pooled_v2_WIRE, 199, 192) node _pooled_v2_T_49 = asSInt(_pooled_v2_T_48) connect pooled_v2[24], _pooled_v2_T_49 node _pooled_v2_T_50 = bits(_pooled_v2_WIRE, 207, 200) node _pooled_v2_T_51 = asSInt(_pooled_v2_T_50) connect pooled_v2[25], _pooled_v2_T_51 node _pooled_v2_T_52 = bits(_pooled_v2_WIRE, 215, 208) node _pooled_v2_T_53 = asSInt(_pooled_v2_T_52) connect pooled_v2[26], _pooled_v2_T_53 node _pooled_v2_T_54 = bits(_pooled_v2_WIRE, 223, 216) node _pooled_v2_T_55 = asSInt(_pooled_v2_T_54) connect pooled_v2[27], _pooled_v2_T_55 node _pooled_v2_T_56 = bits(_pooled_v2_WIRE, 231, 224) node _pooled_v2_T_57 = asSInt(_pooled_v2_T_56) connect pooled_v2[28], _pooled_v2_T_57 node _pooled_v2_T_58 = bits(_pooled_v2_WIRE, 239, 232) node _pooled_v2_T_59 = asSInt(_pooled_v2_T_58) connect pooled_v2[29], _pooled_v2_T_59 node _pooled_v2_T_60 = bits(_pooled_v2_WIRE, 247, 240) node _pooled_v2_T_61 = asSInt(_pooled_v2_T_60) connect pooled_v2[30], _pooled_v2_T_61 node _pooled_v2_T_62 = bits(_pooled_v2_WIRE, 255, 248) node _pooled_v2_T_63 = asSInt(_pooled_v2_T_62) connect pooled_v2[31], _pooled_v2_T_63 node _pooled_v2_T_64 = bits(_pooled_v2_WIRE, 263, 256) node _pooled_v2_T_65 = asSInt(_pooled_v2_T_64) connect pooled_v2[32], _pooled_v2_T_65 node _pooled_v2_T_66 = bits(_pooled_v2_WIRE, 271, 264) node _pooled_v2_T_67 = asSInt(_pooled_v2_T_66) connect pooled_v2[33], _pooled_v2_T_67 node _pooled_v2_T_68 = bits(_pooled_v2_WIRE, 279, 272) node _pooled_v2_T_69 = asSInt(_pooled_v2_T_68) connect pooled_v2[34], _pooled_v2_T_69 node _pooled_v2_T_70 = bits(_pooled_v2_WIRE, 287, 280) node _pooled_v2_T_71 = asSInt(_pooled_v2_T_70) connect pooled_v2[35], _pooled_v2_T_71 node _pooled_v2_T_72 = bits(_pooled_v2_WIRE, 295, 288) node _pooled_v2_T_73 = asSInt(_pooled_v2_T_72) connect pooled_v2[36], _pooled_v2_T_73 node _pooled_v2_T_74 = bits(_pooled_v2_WIRE, 303, 296) node _pooled_v2_T_75 = asSInt(_pooled_v2_T_74) connect pooled_v2[37], _pooled_v2_T_75 node _pooled_v2_T_76 = bits(_pooled_v2_WIRE, 311, 304) node _pooled_v2_T_77 = asSInt(_pooled_v2_T_76) connect pooled_v2[38], _pooled_v2_T_77 node _pooled_v2_T_78 = bits(_pooled_v2_WIRE, 319, 312) node _pooled_v2_T_79 = asSInt(_pooled_v2_T_78) connect pooled_v2[39], _pooled_v2_T_79 node _pooled_v2_T_80 = bits(_pooled_v2_WIRE, 327, 320) node _pooled_v2_T_81 = asSInt(_pooled_v2_T_80) connect pooled_v2[40], _pooled_v2_T_81 node _pooled_v2_T_82 = bits(_pooled_v2_WIRE, 335, 328) node _pooled_v2_T_83 = asSInt(_pooled_v2_T_82) connect pooled_v2[41], _pooled_v2_T_83 node _pooled_v2_T_84 = bits(_pooled_v2_WIRE, 343, 336) node _pooled_v2_T_85 = asSInt(_pooled_v2_T_84) connect pooled_v2[42], _pooled_v2_T_85 node _pooled_v2_T_86 = bits(_pooled_v2_WIRE, 351, 344) node _pooled_v2_T_87 = asSInt(_pooled_v2_T_86) connect pooled_v2[43], _pooled_v2_T_87 node _pooled_v2_T_88 = bits(_pooled_v2_WIRE, 359, 352) node _pooled_v2_T_89 = asSInt(_pooled_v2_T_88) connect pooled_v2[44], _pooled_v2_T_89 node _pooled_v2_T_90 = bits(_pooled_v2_WIRE, 367, 360) node _pooled_v2_T_91 = asSInt(_pooled_v2_T_90) connect pooled_v2[45], _pooled_v2_T_91 node _pooled_v2_T_92 = bits(_pooled_v2_WIRE, 375, 368) node _pooled_v2_T_93 = asSInt(_pooled_v2_T_92) connect pooled_v2[46], _pooled_v2_T_93 node _pooled_v2_T_94 = bits(_pooled_v2_WIRE, 383, 376) node _pooled_v2_T_95 = asSInt(_pooled_v2_T_94) connect pooled_v2[47], _pooled_v2_T_95 node _pooled_v2_T_96 = bits(_pooled_v2_WIRE, 391, 384) node _pooled_v2_T_97 = asSInt(_pooled_v2_T_96) connect pooled_v2[48], _pooled_v2_T_97 node _pooled_v2_T_98 = bits(_pooled_v2_WIRE, 399, 392) node _pooled_v2_T_99 = asSInt(_pooled_v2_T_98) connect pooled_v2[49], _pooled_v2_T_99 node _pooled_v2_T_100 = bits(_pooled_v2_WIRE, 407, 400) node _pooled_v2_T_101 = asSInt(_pooled_v2_T_100) connect pooled_v2[50], _pooled_v2_T_101 node _pooled_v2_T_102 = bits(_pooled_v2_WIRE, 415, 408) node _pooled_v2_T_103 = asSInt(_pooled_v2_T_102) connect pooled_v2[51], _pooled_v2_T_103 node _pooled_v2_T_104 = bits(_pooled_v2_WIRE, 423, 416) node _pooled_v2_T_105 = asSInt(_pooled_v2_T_104) connect pooled_v2[52], _pooled_v2_T_105 node _pooled_v2_T_106 = bits(_pooled_v2_WIRE, 431, 424) node _pooled_v2_T_107 = asSInt(_pooled_v2_T_106) connect pooled_v2[53], _pooled_v2_T_107 node _pooled_v2_T_108 = bits(_pooled_v2_WIRE, 439, 432) node _pooled_v2_T_109 = asSInt(_pooled_v2_T_108) connect pooled_v2[54], _pooled_v2_T_109 node _pooled_v2_T_110 = bits(_pooled_v2_WIRE, 447, 440) node _pooled_v2_T_111 = asSInt(_pooled_v2_T_110) connect pooled_v2[55], _pooled_v2_T_111 node _pooled_v2_T_112 = bits(_pooled_v2_WIRE, 455, 448) node _pooled_v2_T_113 = asSInt(_pooled_v2_T_112) connect pooled_v2[56], _pooled_v2_T_113 node _pooled_v2_T_114 = bits(_pooled_v2_WIRE, 463, 456) node _pooled_v2_T_115 = asSInt(_pooled_v2_T_114) connect pooled_v2[57], _pooled_v2_T_115 node _pooled_v2_T_116 = bits(_pooled_v2_WIRE, 471, 464) node _pooled_v2_T_117 = asSInt(_pooled_v2_T_116) connect pooled_v2[58], _pooled_v2_T_117 node _pooled_v2_T_118 = bits(_pooled_v2_WIRE, 479, 472) node _pooled_v2_T_119 = asSInt(_pooled_v2_T_118) connect pooled_v2[59], _pooled_v2_T_119 node _pooled_v2_T_120 = bits(_pooled_v2_WIRE, 487, 480) node _pooled_v2_T_121 = asSInt(_pooled_v2_T_120) connect pooled_v2[60], _pooled_v2_T_121 node _pooled_v2_T_122 = bits(_pooled_v2_WIRE, 495, 488) node _pooled_v2_T_123 = asSInt(_pooled_v2_T_122) connect pooled_v2[61], _pooled_v2_T_123 node _pooled_v2_T_124 = bits(_pooled_v2_WIRE, 503, 496) node _pooled_v2_T_125 = asSInt(_pooled_v2_T_124) connect pooled_v2[62], _pooled_v2_T_125 node _pooled_v2_T_126 = bits(_pooled_v2_WIRE, 511, 504) node _pooled_v2_T_127 = asSInt(_pooled_v2_T_126) connect pooled_v2[63], _pooled_v2_T_127 node _pooled_T = gt(pooled_v1[0], pooled_v2[0]) node _pooled_T_1 = mux(_pooled_T, pooled_v1[0], pooled_v2[0]) node _pooled_T_2 = gt(pooled_v1[1], pooled_v2[1]) node _pooled_T_3 = mux(_pooled_T_2, pooled_v1[1], pooled_v2[1]) node _pooled_T_4 = gt(pooled_v1[2], pooled_v2[2]) node _pooled_T_5 = mux(_pooled_T_4, pooled_v1[2], pooled_v2[2]) node _pooled_T_6 = gt(pooled_v1[3], pooled_v2[3]) node _pooled_T_7 = mux(_pooled_T_6, pooled_v1[3], pooled_v2[3]) node _pooled_T_8 = gt(pooled_v1[4], pooled_v2[4]) node _pooled_T_9 = mux(_pooled_T_8, pooled_v1[4], pooled_v2[4]) node _pooled_T_10 = gt(pooled_v1[5], pooled_v2[5]) node _pooled_T_11 = mux(_pooled_T_10, pooled_v1[5], pooled_v2[5]) node _pooled_T_12 = gt(pooled_v1[6], pooled_v2[6]) node _pooled_T_13 = mux(_pooled_T_12, pooled_v1[6], pooled_v2[6]) node _pooled_T_14 = gt(pooled_v1[7], pooled_v2[7]) node _pooled_T_15 = mux(_pooled_T_14, pooled_v1[7], pooled_v2[7]) node _pooled_T_16 = gt(pooled_v1[8], pooled_v2[8]) node _pooled_T_17 = mux(_pooled_T_16, pooled_v1[8], pooled_v2[8]) node _pooled_T_18 = gt(pooled_v1[9], pooled_v2[9]) node _pooled_T_19 = mux(_pooled_T_18, pooled_v1[9], pooled_v2[9]) node _pooled_T_20 = gt(pooled_v1[10], pooled_v2[10]) node _pooled_T_21 = mux(_pooled_T_20, pooled_v1[10], pooled_v2[10]) node _pooled_T_22 = gt(pooled_v1[11], pooled_v2[11]) node _pooled_T_23 = mux(_pooled_T_22, pooled_v1[11], pooled_v2[11]) node _pooled_T_24 = gt(pooled_v1[12], pooled_v2[12]) node _pooled_T_25 = mux(_pooled_T_24, pooled_v1[12], pooled_v2[12]) node _pooled_T_26 = gt(pooled_v1[13], pooled_v2[13]) node _pooled_T_27 = mux(_pooled_T_26, pooled_v1[13], pooled_v2[13]) node _pooled_T_28 = gt(pooled_v1[14], pooled_v2[14]) node _pooled_T_29 = mux(_pooled_T_28, pooled_v1[14], pooled_v2[14]) node _pooled_T_30 = gt(pooled_v1[15], pooled_v2[15]) node _pooled_T_31 = mux(_pooled_T_30, pooled_v1[15], pooled_v2[15]) wire _pooled_WIRE : SInt<8>[64] connect _pooled_WIRE[0], _pooled_T_1 connect _pooled_WIRE[1], _pooled_T_3 connect _pooled_WIRE[2], _pooled_T_5 connect _pooled_WIRE[3], _pooled_T_7 connect _pooled_WIRE[4], _pooled_T_9 connect _pooled_WIRE[5], _pooled_T_11 connect _pooled_WIRE[6], _pooled_T_13 connect _pooled_WIRE[7], _pooled_T_15 connect _pooled_WIRE[8], _pooled_T_17 connect _pooled_WIRE[9], _pooled_T_19 connect _pooled_WIRE[10], _pooled_T_21 connect _pooled_WIRE[11], _pooled_T_23 connect _pooled_WIRE[12], _pooled_T_25 connect _pooled_WIRE[13], _pooled_T_27 connect _pooled_WIRE[14], _pooled_T_29 connect _pooled_WIRE[15], _pooled_T_31 connect _pooled_WIRE[16], pooled_v2[16] connect _pooled_WIRE[17], pooled_v2[17] connect _pooled_WIRE[18], pooled_v2[18] connect _pooled_WIRE[19], pooled_v2[19] connect _pooled_WIRE[20], pooled_v2[20] connect _pooled_WIRE[21], pooled_v2[21] connect _pooled_WIRE[22], pooled_v2[22] connect _pooled_WIRE[23], pooled_v2[23] connect _pooled_WIRE[24], pooled_v2[24] connect _pooled_WIRE[25], pooled_v2[25] connect _pooled_WIRE[26], pooled_v2[26] connect _pooled_WIRE[27], pooled_v2[27] connect _pooled_WIRE[28], pooled_v2[28] connect _pooled_WIRE[29], pooled_v2[29] connect _pooled_WIRE[30], pooled_v2[30] connect _pooled_WIRE[31], pooled_v2[31] connect _pooled_WIRE[32], pooled_v2[32] connect _pooled_WIRE[33], pooled_v2[33] connect _pooled_WIRE[34], pooled_v2[34] connect _pooled_WIRE[35], pooled_v2[35] connect _pooled_WIRE[36], pooled_v2[36] connect _pooled_WIRE[37], pooled_v2[37] connect _pooled_WIRE[38], pooled_v2[38] connect _pooled_WIRE[39], pooled_v2[39] connect _pooled_WIRE[40], pooled_v2[40] connect _pooled_WIRE[41], pooled_v2[41] connect _pooled_WIRE[42], pooled_v2[42] connect _pooled_WIRE[43], pooled_v2[43] connect _pooled_WIRE[44], pooled_v2[44] connect _pooled_WIRE[45], pooled_v2[45] connect _pooled_WIRE[46], pooled_v2[46] connect _pooled_WIRE[47], pooled_v2[47] connect _pooled_WIRE[48], pooled_v2[48] connect _pooled_WIRE[49], pooled_v2[49] connect _pooled_WIRE[50], pooled_v2[50] connect _pooled_WIRE[51], pooled_v2[51] connect _pooled_WIRE[52], pooled_v2[52] connect _pooled_WIRE[53], pooled_v2[53] connect _pooled_WIRE[54], pooled_v2[54] connect _pooled_WIRE[55], pooled_v2[55] connect _pooled_WIRE[56], pooled_v2[56] connect _pooled_WIRE[57], pooled_v2[57] connect _pooled_WIRE[58], pooled_v2[58] connect _pooled_WIRE[59], pooled_v2[59] connect _pooled_WIRE[60], pooled_v2[60] connect _pooled_WIRE[61], pooled_v2[61] connect _pooled_WIRE[62], pooled_v2[62] connect _pooled_WIRE[63], pooled_v2[63] node _pooled_T_32 = asUInt(_pooled_WIRE[0]) node _pooled_T_33 = asUInt(_pooled_WIRE[1]) node _pooled_T_34 = asUInt(_pooled_WIRE[2]) node _pooled_T_35 = asUInt(_pooled_WIRE[3]) node _pooled_T_36 = asUInt(_pooled_WIRE[4]) node _pooled_T_37 = asUInt(_pooled_WIRE[5]) node _pooled_T_38 = asUInt(_pooled_WIRE[6]) node _pooled_T_39 = asUInt(_pooled_WIRE[7]) node _pooled_T_40 = asUInt(_pooled_WIRE[8]) node _pooled_T_41 = asUInt(_pooled_WIRE[9]) node _pooled_T_42 = asUInt(_pooled_WIRE[10]) node _pooled_T_43 = asUInt(_pooled_WIRE[11]) node _pooled_T_44 = asUInt(_pooled_WIRE[12]) node _pooled_T_45 = asUInt(_pooled_WIRE[13]) node _pooled_T_46 = asUInt(_pooled_WIRE[14]) node _pooled_T_47 = asUInt(_pooled_WIRE[15]) node _pooled_T_48 = asUInt(_pooled_WIRE[16]) node _pooled_T_49 = asUInt(_pooled_WIRE[17]) node _pooled_T_50 = asUInt(_pooled_WIRE[18]) node _pooled_T_51 = asUInt(_pooled_WIRE[19]) node _pooled_T_52 = asUInt(_pooled_WIRE[20]) node _pooled_T_53 = asUInt(_pooled_WIRE[21]) node _pooled_T_54 = asUInt(_pooled_WIRE[22]) node _pooled_T_55 = asUInt(_pooled_WIRE[23]) node _pooled_T_56 = asUInt(_pooled_WIRE[24]) node _pooled_T_57 = asUInt(_pooled_WIRE[25]) node _pooled_T_58 = asUInt(_pooled_WIRE[26]) node _pooled_T_59 = asUInt(_pooled_WIRE[27]) node _pooled_T_60 = asUInt(_pooled_WIRE[28]) node _pooled_T_61 = asUInt(_pooled_WIRE[29]) node _pooled_T_62 = asUInt(_pooled_WIRE[30]) node _pooled_T_63 = asUInt(_pooled_WIRE[31]) node _pooled_T_64 = asUInt(_pooled_WIRE[32]) node _pooled_T_65 = asUInt(_pooled_WIRE[33]) node _pooled_T_66 = asUInt(_pooled_WIRE[34]) node _pooled_T_67 = asUInt(_pooled_WIRE[35]) node _pooled_T_68 = asUInt(_pooled_WIRE[36]) node _pooled_T_69 = asUInt(_pooled_WIRE[37]) node _pooled_T_70 = asUInt(_pooled_WIRE[38]) node _pooled_T_71 = asUInt(_pooled_WIRE[39]) node _pooled_T_72 = asUInt(_pooled_WIRE[40]) node _pooled_T_73 = asUInt(_pooled_WIRE[41]) node _pooled_T_74 = asUInt(_pooled_WIRE[42]) node _pooled_T_75 = asUInt(_pooled_WIRE[43]) node _pooled_T_76 = asUInt(_pooled_WIRE[44]) node _pooled_T_77 = asUInt(_pooled_WIRE[45]) node _pooled_T_78 = asUInt(_pooled_WIRE[46]) node _pooled_T_79 = asUInt(_pooled_WIRE[47]) node _pooled_T_80 = asUInt(_pooled_WIRE[48]) node _pooled_T_81 = asUInt(_pooled_WIRE[49]) node _pooled_T_82 = asUInt(_pooled_WIRE[50]) node _pooled_T_83 = asUInt(_pooled_WIRE[51]) node _pooled_T_84 = asUInt(_pooled_WIRE[52]) node _pooled_T_85 = asUInt(_pooled_WIRE[53]) node _pooled_T_86 = asUInt(_pooled_WIRE[54]) node _pooled_T_87 = asUInt(_pooled_WIRE[55]) node _pooled_T_88 = asUInt(_pooled_WIRE[56]) node _pooled_T_89 = asUInt(_pooled_WIRE[57]) node _pooled_T_90 = asUInt(_pooled_WIRE[58]) node _pooled_T_91 = asUInt(_pooled_WIRE[59]) node _pooled_T_92 = asUInt(_pooled_WIRE[60]) node _pooled_T_93 = asUInt(_pooled_WIRE[61]) node _pooled_T_94 = asUInt(_pooled_WIRE[62]) node _pooled_T_95 = asUInt(_pooled_WIRE[63]) node pooled_lo_lo_lo_lo_lo = cat(_pooled_T_33, _pooled_T_32) node pooled_lo_lo_lo_lo_hi = cat(_pooled_T_35, _pooled_T_34) node pooled_lo_lo_lo_lo = cat(pooled_lo_lo_lo_lo_hi, pooled_lo_lo_lo_lo_lo) node pooled_lo_lo_lo_hi_lo = cat(_pooled_T_37, _pooled_T_36) node pooled_lo_lo_lo_hi_hi = cat(_pooled_T_39, _pooled_T_38) node pooled_lo_lo_lo_hi = cat(pooled_lo_lo_lo_hi_hi, pooled_lo_lo_lo_hi_lo) node pooled_lo_lo_lo = cat(pooled_lo_lo_lo_hi, pooled_lo_lo_lo_lo) node pooled_lo_lo_hi_lo_lo = cat(_pooled_T_41, _pooled_T_40) node pooled_lo_lo_hi_lo_hi = cat(_pooled_T_43, _pooled_T_42) node pooled_lo_lo_hi_lo = cat(pooled_lo_lo_hi_lo_hi, pooled_lo_lo_hi_lo_lo) node pooled_lo_lo_hi_hi_lo = cat(_pooled_T_45, _pooled_T_44) node pooled_lo_lo_hi_hi_hi = cat(_pooled_T_47, _pooled_T_46) node pooled_lo_lo_hi_hi = cat(pooled_lo_lo_hi_hi_hi, pooled_lo_lo_hi_hi_lo) node pooled_lo_lo_hi = cat(pooled_lo_lo_hi_hi, pooled_lo_lo_hi_lo) node pooled_lo_lo = cat(pooled_lo_lo_hi, pooled_lo_lo_lo) node pooled_lo_hi_lo_lo_lo = cat(_pooled_T_49, _pooled_T_48) node pooled_lo_hi_lo_lo_hi = cat(_pooled_T_51, _pooled_T_50) node pooled_lo_hi_lo_lo = cat(pooled_lo_hi_lo_lo_hi, pooled_lo_hi_lo_lo_lo) node pooled_lo_hi_lo_hi_lo = cat(_pooled_T_53, _pooled_T_52) node pooled_lo_hi_lo_hi_hi = cat(_pooled_T_55, _pooled_T_54) node pooled_lo_hi_lo_hi = cat(pooled_lo_hi_lo_hi_hi, pooled_lo_hi_lo_hi_lo) node pooled_lo_hi_lo = cat(pooled_lo_hi_lo_hi, pooled_lo_hi_lo_lo) node pooled_lo_hi_hi_lo_lo = cat(_pooled_T_57, _pooled_T_56) node pooled_lo_hi_hi_lo_hi = cat(_pooled_T_59, _pooled_T_58) node pooled_lo_hi_hi_lo = cat(pooled_lo_hi_hi_lo_hi, pooled_lo_hi_hi_lo_lo) node pooled_lo_hi_hi_hi_lo = cat(_pooled_T_61, _pooled_T_60) node pooled_lo_hi_hi_hi_hi = cat(_pooled_T_63, _pooled_T_62) node pooled_lo_hi_hi_hi = cat(pooled_lo_hi_hi_hi_hi, pooled_lo_hi_hi_hi_lo) node pooled_lo_hi_hi = cat(pooled_lo_hi_hi_hi, pooled_lo_hi_hi_lo) node pooled_lo_hi = cat(pooled_lo_hi_hi, pooled_lo_hi_lo) node pooled_lo = cat(pooled_lo_hi, pooled_lo_lo) node pooled_hi_lo_lo_lo_lo = cat(_pooled_T_65, _pooled_T_64) node pooled_hi_lo_lo_lo_hi = cat(_pooled_T_67, _pooled_T_66) node pooled_hi_lo_lo_lo = cat(pooled_hi_lo_lo_lo_hi, pooled_hi_lo_lo_lo_lo) node pooled_hi_lo_lo_hi_lo = cat(_pooled_T_69, _pooled_T_68) node pooled_hi_lo_lo_hi_hi = cat(_pooled_T_71, _pooled_T_70) node pooled_hi_lo_lo_hi = cat(pooled_hi_lo_lo_hi_hi, pooled_hi_lo_lo_hi_lo) node pooled_hi_lo_lo = cat(pooled_hi_lo_lo_hi, pooled_hi_lo_lo_lo) node pooled_hi_lo_hi_lo_lo = cat(_pooled_T_73, _pooled_T_72) node pooled_hi_lo_hi_lo_hi = cat(_pooled_T_75, _pooled_T_74) node pooled_hi_lo_hi_lo = cat(pooled_hi_lo_hi_lo_hi, pooled_hi_lo_hi_lo_lo) node pooled_hi_lo_hi_hi_lo = cat(_pooled_T_77, _pooled_T_76) node pooled_hi_lo_hi_hi_hi = cat(_pooled_T_79, _pooled_T_78) node pooled_hi_lo_hi_hi = cat(pooled_hi_lo_hi_hi_hi, pooled_hi_lo_hi_hi_lo) node pooled_hi_lo_hi = cat(pooled_hi_lo_hi_hi, pooled_hi_lo_hi_lo) node pooled_hi_lo = cat(pooled_hi_lo_hi, pooled_hi_lo_lo) node pooled_hi_hi_lo_lo_lo = cat(_pooled_T_81, _pooled_T_80) node pooled_hi_hi_lo_lo_hi = cat(_pooled_T_83, _pooled_T_82) node pooled_hi_hi_lo_lo = cat(pooled_hi_hi_lo_lo_hi, pooled_hi_hi_lo_lo_lo) node pooled_hi_hi_lo_hi_lo = cat(_pooled_T_85, _pooled_T_84) node pooled_hi_hi_lo_hi_hi = cat(_pooled_T_87, _pooled_T_86) node pooled_hi_hi_lo_hi = cat(pooled_hi_hi_lo_hi_hi, pooled_hi_hi_lo_hi_lo) node pooled_hi_hi_lo = cat(pooled_hi_hi_lo_hi, pooled_hi_hi_lo_lo) node pooled_hi_hi_hi_lo_lo = cat(_pooled_T_89, _pooled_T_88) node pooled_hi_hi_hi_lo_hi = cat(_pooled_T_91, _pooled_T_90) node pooled_hi_hi_hi_lo = cat(pooled_hi_hi_hi_lo_hi, pooled_hi_hi_hi_lo_lo) node pooled_hi_hi_hi_hi_lo = cat(_pooled_T_93, _pooled_T_92) node pooled_hi_hi_hi_hi_hi = cat(_pooled_T_95, _pooled_T_94) node pooled_hi_hi_hi_hi = cat(pooled_hi_hi_hi_hi_hi, pooled_hi_hi_hi_hi_lo) node pooled_hi_hi_hi = cat(pooled_hi_hi_hi_hi, pooled_hi_hi_hi_lo) node pooled_hi_hi = cat(pooled_hi_hi_hi, pooled_hi_hi_lo) node pooled_hi = cat(pooled_hi_hi, pooled_hi_lo) node pooled = cat(pooled_hi, pooled_lo) connect req, io.req.bits node _req_len_T = mul(io.req.bits.block, UInt<5>(0h10)) node _req_len_T_1 = add(_req_len_T, io.req.bits.len) node _req_len_T_2 = tail(_req_len_T_1, 1) connect req.len, _req_len_T_2 node _data_single_block_T = mux(io.req.bits.pool_en, pooled, io.req.bits.data) connect data_single_block, _data_single_block_T node _T_18 = bits(io.req.bits.block, 1, 0) connect data_blocks[_T_18], io.req.bits.data connect bytesSent, UInt<1>(0h0) node _state_T = mux(io.req.bits.store_en, UInt<2>(0h1), UInt<2>(0h0)) connect state, _state_T node _T_19 = leq(io.req.bits.len, UInt<5>(0h10)) node _T_20 = eq(io.req.bits.block, UInt<1>(0h0)) node _T_21 = or(_T_19, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed: DMA can't write multiple blocks to main memory when writing full accumulator output\n at DMA.scala:609 assert(io.req.bits.len <= (block_cols * inputType.getWidth / 8).U \|\| io.req.bits.block === 0.U, \"DMA can't write multiple blocks to main memory when writing full accumulator output\")\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2 node _T_25 = eq(io.req.bits.pool_en, UInt<1>(0h0)) node _T_26 = eq(io.req.bits.block, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: Can't pool with block-mvout\n at DMA.scala:610 assert(!io.req.bits.pool_en \|\| io.req.bits.block === 0.U, \"Can't pool with block-mvout\")\n") : printf_3 assert(clock, _T_27, UInt<1>(0h1), "") : assert_3 wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 node _T_31 = neq(state, UInt<2>(0h0)) connect io.counter.event_signal[21], _T_31 connect io.counter.event_signal[22], io.tlb.resp.miss node _T_32 = eq(nodeOut.a.ready, UInt<1>(0h0)) node _T_33 = and(nodeOut.a.valid, _T_32) connect io.counter.event_signal[23], _T_33 regreset total_bytes_sent : UInt<32>, clock, reset, UInt<32>(0h0) node _T_34 = and(nodeOut.d.ready, nodeOut.d.valid) when _T_34 : node _total_bytes_sent_T = dshl(UInt<1>(0h1), nodeOut.d.bits.size) node _total_bytes_sent_T_1 = add(total_bytes_sent, _total_bytes_sent_T) node _total_bytes_sent_T_2 = tail(_total_bytes_sent_T_1, 1) connect total_bytes_sent, _total_bytes_sent_T_2 regreset total_latency : UInt<32>, clock, reset, UInt<32>(0h0) node _total_latency_T = bits(xactBusy, 0, 0) node _total_latency_T_1 = bits(xactBusy, 1, 1) node _total_latency_T_2 = bits(xactBusy, 2, 2) node _total_latency_T_3 = bits(xactBusy, 3, 3) node _total_latency_T_4 = bits(xactBusy, 4, 4) node _total_latency_T_5 = bits(xactBusy, 5, 5) node _total_latency_T_6 = bits(xactBusy, 6, 6) node _total_latency_T_7 = bits(xactBusy, 7, 7) node _total_latency_T_8 = bits(xactBusy, 8, 8) node _total_latency_T_9 = bits(xactBusy, 9, 9) node _total_latency_T_10 = bits(xactBusy, 10, 10) node _total_latency_T_11 = bits(xactBusy, 11, 11) node _total_latency_T_12 = bits(xactBusy, 12, 12) node _total_latency_T_13 = bits(xactBusy, 13, 13) node _total_latency_T_14 = bits(xactBusy, 14, 14) node _total_latency_T_15 = bits(xactBusy, 15, 15) node _total_latency_T_16 = add(_total_latency_T, _total_latency_T_1) node _total_latency_T_17 = bits(_total_latency_T_16, 1, 0) node _total_latency_T_18 = add(_total_latency_T_2, _total_latency_T_3) node _total_latency_T_19 = bits(_total_latency_T_18, 1, 0) node _total_latency_T_20 = add(_total_latency_T_17, _total_latency_T_19) node _total_latency_T_21 = bits(_total_latency_T_20, 2, 0) node _total_latency_T_22 = add(_total_latency_T_4, _total_latency_T_5) node _total_latency_T_23 = bits(_total_latency_T_22, 1, 0) node _total_latency_T_24 = add(_total_latency_T_6, _total_latency_T_7) node _total_latency_T_25 = bits(_total_latency_T_24, 1, 0) node _total_latency_T_26 = add(_total_latency_T_23, _total_latency_T_25) node _total_latency_T_27 = bits(_total_latency_T_26, 2, 0) node _total_latency_T_28 = add(_total_latency_T_21, _total_latency_T_27) node _total_latency_T_29 = bits(_total_latency_T_28, 3, 0) node _total_latency_T_30 = add(_total_latency_T_8, _total_latency_T_9) node _total_latency_T_31 = bits(_total_latency_T_30, 1, 0) node _total_latency_T_32 = add(_total_latency_T_10, _total_latency_T_11) node _total_latency_T_33 = bits(_total_latency_T_32, 1, 0) node _total_latency_T_34 = add(_total_latency_T_31, _total_latency_T_33) node _total_latency_T_35 = bits(_total_latency_T_34, 2, 0) node _total_latency_T_36 = add(_total_latency_T_12, _total_latency_T_13) node _total_latency_T_37 = bits(_total_latency_T_36, 1, 0) node _total_latency_T_38 = add(_total_latency_T_14, _total_latency_T_15) node _total_latency_T_39 = bits(_total_latency_T_38, 1, 0) node _total_latency_T_40 = add(_total_latency_T_37, _total_latency_T_39) node _total_latency_T_41 = bits(_total_latency_T_40, 2, 0) node _total_latency_T_42 = add(_total_latency_T_35, _total_latency_T_41) node _total_latency_T_43 = bits(_total_latency_T_42, 3, 0) node _total_latency_T_44 = add(_total_latency_T_29, _total_latency_T_43) node _total_latency_T_45 = bits(_total_latency_T_44, 4, 0) node _total_latency_T_46 = add(total_latency, _total_latency_T_45) node _total_latency_T_47 = tail(_total_latency_T_46, 1) connect total_latency, _total_latency_T_47 when io.counter.external_reset : connect total_bytes_sent, UInt<1>(0h0) connect total_latency, UInt<1>(0h0) connect io.counter.external_values[5], total_bytes_sent connect io.counter.external_values[7], total_latency extmodule plusarg_reader_90 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_91 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module StreamWriter( // @[DMA.scala:360:9] input clock, // @[DMA.scala:360:9] input reset, // @[DMA.scala:360:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_req_ready, // @[DMA.scala:371:16] input io_req_valid, // @[DMA.scala:371:16] input [39:0] io_req_bits_vaddr, // @[DMA.scala:371:16] input [511:0] io_req_bits_data, // @[DMA.scala:371:16] input [6:0] io_req_bits_len, // @[DMA.scala:371:16] input [7:0] io_req_bits_block, // @[DMA.scala:371:16] input io_req_bits_status_debug, // @[DMA.scala:371:16] input io_req_bits_status_cease, // @[DMA.scala:371:16] input io_req_bits_status_wfi, // @[DMA.scala:371:16] input [31:0] io_req_bits_status_isa, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_dprv, // @[DMA.scala:371:16] input io_req_bits_status_dv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_prv, // @[DMA.scala:371:16] input io_req_bits_status_v, // @[DMA.scala:371:16] input io_req_bits_status_sd, // @[DMA.scala:371:16] input [22:0] io_req_bits_status_zero2, // @[DMA.scala:371:16] input io_req_bits_status_mpv, // @[DMA.scala:371:16] input io_req_bits_status_gva, // @[DMA.scala:371:16] input io_req_bits_status_mbe, // @[DMA.scala:371:16] input io_req_bits_status_sbe, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_sxl, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_uxl, // @[DMA.scala:371:16] input io_req_bits_status_sd_rv32, // @[DMA.scala:371:16] input [7:0] io_req_bits_status_zero1, // @[DMA.scala:371:16] input io_req_bits_status_tsr, // @[DMA.scala:371:16] input io_req_bits_status_tw, // @[DMA.scala:371:16] input io_req_bits_status_tvm, // @[DMA.scala:371:16] input io_req_bits_status_mxr, // @[DMA.scala:371:16] input io_req_bits_status_sum, // @[DMA.scala:371:16] input io_req_bits_status_mprv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_xs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_fs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_mpp, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_vs, // @[DMA.scala:371:16] input io_req_bits_status_spp, // @[DMA.scala:371:16] input io_req_bits_status_mpie, // @[DMA.scala:371:16] input io_req_bits_status_ube, // @[DMA.scala:371:16] input io_req_bits_status_spie, // @[DMA.scala:371:16] input io_req_bits_status_upie, // @[DMA.scala:371:16] input io_req_bits_status_mie, // @[DMA.scala:371:16] input io_req_bits_status_hie, // @[DMA.scala:371:16] input io_req_bits_status_sie, // @[DMA.scala:371:16] input io_req_bits_status_uie, // @[DMA.scala:371:16] input io_req_bits_pool_en, // @[DMA.scala:371:16] input io_req_bits_store_en, // @[DMA.scala:371:16] output io_tlb_req_valid, // @[DMA.scala:371:16] output [39:0] io_tlb_req_bits_tlb_req_vaddr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_debug, // @[DMA.scala:371:16] output io_tlb_req_bits_status_cease, // @[DMA.scala:371:16] output io_tlb_req_bits_status_wfi, // @[DMA.scala:371:16] output [31:0] io_tlb_req_bits_status_isa, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_dprv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_dv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_prv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_v, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd, // @[DMA.scala:371:16] output [22:0] io_tlb_req_bits_status_zero2, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_gva, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mbe, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sbe, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_sxl, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_uxl, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd_rv32, // @[DMA.scala:371:16] output [7:0] io_tlb_req_bits_status_zero1, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tsr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tw, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tvm, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mxr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sum, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mprv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_xs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_fs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_mpp, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_vs, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spp, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_ube, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_upie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_hie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_uie, // @[DMA.scala:371:16] input io_tlb_resp_miss, // @[DMA.scala:371:16] input [31:0] io_tlb_resp_paddr, // @[DMA.scala:371:16] input [39:0] io_tlb_resp_gpa, // @[DMA.scala:371:16] input io_tlb_resp_pf_ld, // @[DMA.scala:371:16] input io_tlb_resp_pf_st, // @[DMA.scala:371:16] input io_tlb_resp_pf_inst, // @[DMA.scala:371:16] input io_tlb_resp_ae_ld, // @[DMA.scala:371:16] input io_tlb_resp_ae_st, // @[DMA.scala:371:16] input io_tlb_resp_ae_inst, // @[DMA.scala:371:16] input io_tlb_resp_cacheable, // @[DMA.scala:371:16] input io_tlb_resp_must_alloc, // @[DMA.scala:371:16] input io_tlb_resp_prefetchable, // @[DMA.scala:371:16] input [4:0] io_tlb_resp_cmd, // @[DMA.scala:371:16] output io_busy, // @[DMA.scala:371:16] input io_flush, // @[DMA.scala:371:16] output io_counter_event_signal_21, // @[DMA.scala:371:16] output io_counter_event_signal_22, // @[DMA.scala:371:16] output io_counter_event_signal_23, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_5, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_7, // @[DMA.scala:371:16] input io_counter_external_reset // @[DMA.scala:371:16] ); wire [7:0] pooled_v2_62; // @[DMA.scala:594:44] wire [7:0] pooled_v2_61; // @[DMA.scala:594:44] wire [7:0] pooled_v2_60; // @[DMA.scala:594:44] wire [7:0] pooled_v2_59; // @[DMA.scala:594:44] wire [7:0] pooled_v2_58; // @[DMA.scala:594:44] wire [7:0] pooled_v2_57; // @[DMA.scala:594:44] wire [7:0] pooled_v2_56; // @[DMA.scala:594:44] wire [7:0] pooled_v2_55; // @[DMA.scala:594:44] wire [7:0] pooled_v2_54; // @[DMA.scala:594:44] wire [7:0] pooled_v2_53; // @[DMA.scala:594:44] wire [7:0] pooled_v2_52; // @[DMA.scala:594:44] wire [7:0] pooled_v2_51; // @[DMA.scala:594:44] wire [7:0] pooled_v2_50; // @[DMA.scala:594:44] wire [7:0] pooled_v2_49; // @[DMA.scala:594:44] wire [7:0] pooled_v2_48; // @[DMA.scala:594:44] wire [7:0] pooled_v2_47; // @[DMA.scala:594:44] wire [7:0] pooled_v2_46; // @[DMA.scala:594:44] wire [7:0] pooled_v2_45; // @[DMA.scala:594:44] wire [7:0] pooled_v2_44; // @[DMA.scala:594:44] wire [7:0] pooled_v2_43; // @[DMA.scala:594:44] wire [7:0] pooled_v2_42; // @[DMA.scala:594:44] wire [7:0] pooled_v2_41; // @[DMA.scala:594:44] wire [7:0] pooled_v2_40; // @[DMA.scala:594:44] wire [7:0] pooled_v2_39; // @[DMA.scala:594:44] wire [7:0] pooled_v2_38; // @[DMA.scala:594:44] wire [7:0] pooled_v2_37; // @[DMA.scala:594:44] wire [7:0] pooled_v2_36; // @[DMA.scala:594:44] wire [7:0] pooled_v2_35; // @[DMA.scala:594:44] wire [7:0] pooled_v2_34; // @[DMA.scala:594:44] wire [7:0] pooled_v2_33; // @[DMA.scala:594:44] wire [7:0] pooled_v2_32; // @[DMA.scala:594:44] wire [7:0] pooled_v2_31; // @[DMA.scala:594:44] wire [7:0] pooled_v2_30; // @[DMA.scala:594:44] wire [7:0] pooled_v2_29; // @[DMA.scala:594:44] wire [7:0] pooled_v2_28; // @[DMA.scala:594:44] wire [7:0] pooled_v2_27; // @[DMA.scala:594:44] wire [7:0] pooled_v2_26; // @[DMA.scala:594:44] wire [7:0] pooled_v2_25; // @[DMA.scala:594:44] wire [7:0] pooled_v2_24; // @[DMA.scala:594:44] wire [7:0] pooled_v2_23; // @[DMA.scala:594:44] wire [7:0] pooled_v2_22; // @[DMA.scala:594:44] wire [7:0] pooled_v2_21; // @[DMA.scala:594:44] wire [7:0] pooled_v2_20; // @[DMA.scala:594:44] wire [7:0] pooled_v2_19; // @[DMA.scala:594:44] wire [7:0] pooled_v2_18; // @[DMA.scala:594:44] wire [7:0] pooled_v2_17; // @[DMA.scala:594:44] wire [7:0] pooled_v2_16; // @[DMA.scala:594:44] reg [1:0] state; // @[DMA.scala:380:24] wire _translate_q_io_enq_ready; // @[DMA.scala:534:29] wire _translate_q_io_deq_valid; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:534:29] wire [3:0] _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:534:29] wire [3:0] _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:534:29] wire [15:0] _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:534:29] wire [127:0] _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:534:29] wire _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:534:29] wire _tlb_q_io_enq_ready; // @[DMA.scala:523:23] wire _tlb_q_io_deq_valid; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_param; // @[DMA.scala:523:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_size; // @[DMA.scala:523:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_source; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_tl_a_address; // @[DMA.scala:523:23] wire [15:0] _tlb_q_io_deq_bits_tl_a_mask; // @[DMA.scala:523:23] wire [127:0] _tlb_q_io_deq_bits_tl_a_data; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:523:23] wire [38:0] _tlb_q_io_deq_bits_vaddr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_v; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:523:23] wire [22:0] _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:523:23] wire [7:0] _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:523:23] wire _tlb_arb_io_in_1_ready; // @[DMA.scala:518:25] wire _tlb_arb_io_out_valid; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_opcode; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_param; // @[DMA.scala:518:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_size; // @[DMA.scala:518:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_source; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_tl_a_address; // @[DMA.scala:518:25] wire [15:0] _tlb_arb_io_out_bits_tl_a_mask; // @[DMA.scala:518:25] wire [127:0] _tlb_arb_io_out_bits_tl_a_data; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_tl_a_corrupt; // @[DMA.scala:518:25] wire [38:0] _tlb_arb_io_out_bits_vaddr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_debug; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_cease; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_wfi; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_status_isa; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_dprv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_dv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_prv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_v; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd; // @[DMA.scala:518:25] wire [22:0] _tlb_arb_io_out_bits_status_zero2; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_gva; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mbe; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sbe; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_sxl; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_uxl; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd_rv32; // @[DMA.scala:518:25] wire [7:0] _tlb_arb_io_out_bits_status_zero1; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tsr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tw; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tvm; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mxr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sum; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mprv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_xs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_fs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_mpp; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_vs; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spp; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_ube; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_upie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_hie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_uie; // @[DMA.scala:518:25] wire _shadow_retry_a_io_deq_valid; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_opcode; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_param; // @[DMA.scala:515:32] wire [3:0] _shadow_retry_a_io_deq_bits_tl_a_size; // @[DMA.scala:515:32] wire [3:0] _shadow_retry_a_io_deq_bits_tl_a_source; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_tl_a_address; // @[DMA.scala:515:32] wire [15:0] _shadow_retry_a_io_deq_bits_tl_a_mask; // @[DMA.scala:515:32] wire [127:0] _shadow_retry_a_io_deq_bits_tl_a_data; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_tl_a_corrupt; // @[DMA.scala:515:32] wire [38:0] _shadow_retry_a_io_deq_bits_vaddr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_debug; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_cease; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_wfi; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_status_isa; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_dprv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_dv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_prv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_v; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd; // @[DMA.scala:515:32] wire [22:0] _shadow_retry_a_io_deq_bits_status_zero2; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_gva; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mbe; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sbe; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_sxl; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_uxl; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd_rv32; // @[DMA.scala:515:32] wire [7:0] _shadow_retry_a_io_deq_bits_status_zero1; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tsr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tw; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tvm; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mxr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sum; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mprv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_xs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_fs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_mpp; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_vs; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spp; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_ube; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_upie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_hie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_uie; // @[DMA.scala:515:32] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:360:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:360:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:360:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:360:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:360:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:360:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:360:9] wire io_req_valid_0 = io_req_valid; // @[DMA.scala:360:9] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[DMA.scala:360:9] wire [511:0] io_req_bits_data_0 = io_req_bits_data; // @[DMA.scala:360:9] wire [6:0] io_req_bits_len_0 = io_req_bits_len; // @[DMA.scala:360:9] wire [7:0] io_req_bits_block_0 = io_req_bits_block; // @[DMA.scala:360:9] wire io_req_bits_status_debug_0 = io_req_bits_status_debug; // @[DMA.scala:360:9] wire io_req_bits_status_cease_0 = io_req_bits_status_cease; // @[DMA.scala:360:9] wire io_req_bits_status_wfi_0 = io_req_bits_status_wfi; // @[DMA.scala:360:9] wire [31:0] io_req_bits_status_isa_0 = io_req_bits_status_isa; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_dprv_0 = io_req_bits_status_dprv; // @[DMA.scala:360:9] wire io_req_bits_status_dv_0 = io_req_bits_status_dv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_prv_0 = io_req_bits_status_prv; // @[DMA.scala:360:9] wire io_req_bits_status_v_0 = io_req_bits_status_v; // @[DMA.scala:360:9] wire io_req_bits_status_sd_0 = io_req_bits_status_sd; // @[DMA.scala:360:9] wire [22:0] io_req_bits_status_zero2_0 = io_req_bits_status_zero2; // @[DMA.scala:360:9] wire io_req_bits_status_mpv_0 = io_req_bits_status_mpv; // @[DMA.scala:360:9] wire io_req_bits_status_gva_0 = io_req_bits_status_gva; // @[DMA.scala:360:9] wire io_req_bits_status_mbe_0 = io_req_bits_status_mbe; // @[DMA.scala:360:9] wire io_req_bits_status_sbe_0 = io_req_bits_status_sbe; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_sxl_0 = io_req_bits_status_sxl; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_uxl_0 = io_req_bits_status_uxl; // @[DMA.scala:360:9] wire io_req_bits_status_sd_rv32_0 = io_req_bits_status_sd_rv32; // @[DMA.scala:360:9] wire [7:0] io_req_bits_status_zero1_0 = io_req_bits_status_zero1; // @[DMA.scala:360:9] wire io_req_bits_status_tsr_0 = io_req_bits_status_tsr; // @[DMA.scala:360:9] wire io_req_bits_status_tw_0 = io_req_bits_status_tw; // @[DMA.scala:360:9] wire io_req_bits_status_tvm_0 = io_req_bits_status_tvm; // @[DMA.scala:360:9] wire io_req_bits_status_mxr_0 = io_req_bits_status_mxr; // @[DMA.scala:360:9] wire io_req_bits_status_sum_0 = io_req_bits_status_sum; // @[DMA.scala:360:9] wire io_req_bits_status_mprv_0 = io_req_bits_status_mprv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_xs_0 = io_req_bits_status_xs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_fs_0 = io_req_bits_status_fs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_mpp_0 = io_req_bits_status_mpp; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_vs_0 = io_req_bits_status_vs; // @[DMA.scala:360:9] wire io_req_bits_status_spp_0 = io_req_bits_status_spp; // @[DMA.scala:360:9] wire io_req_bits_status_mpie_0 = io_req_bits_status_mpie; // @[DMA.scala:360:9] wire io_req_bits_status_ube_0 = io_req_bits_status_ube; // @[DMA.scala:360:9] wire io_req_bits_status_spie_0 = io_req_bits_status_spie; // @[DMA.scala:360:9] wire io_req_bits_status_upie_0 = io_req_bits_status_upie; // @[DMA.scala:360:9] wire io_req_bits_status_mie_0 = io_req_bits_status_mie; // @[DMA.scala:360:9] wire io_req_bits_status_hie_0 = io_req_bits_status_hie; // @[DMA.scala:360:9] wire io_req_bits_status_sie_0 = io_req_bits_status_sie; // @[DMA.scala:360:9] wire io_req_bits_status_uie_0 = io_req_bits_status_uie; // @[DMA.scala:360:9] wire io_req_bits_pool_en_0 = io_req_bits_pool_en; // @[DMA.scala:360:9] wire io_req_bits_store_en_0 = io_req_bits_store_en; // @[DMA.scala:360:9] wire io_tlb_resp_miss_0 = io_tlb_resp_miss; // @[DMA.scala:360:9] wire [31:0] io_tlb_resp_paddr_0 = io_tlb_resp_paddr; // @[DMA.scala:360:9] wire [39:0] io_tlb_resp_gpa_0 = io_tlb_resp_gpa; // @[DMA.scala:360:9] wire io_tlb_resp_pf_ld_0 = io_tlb_resp_pf_ld; // @[DMA.scala:360:9] wire io_tlb_resp_pf_st_0 = io_tlb_resp_pf_st; // @[DMA.scala:360:9] wire io_tlb_resp_pf_inst_0 = io_tlb_resp_pf_inst; // @[DMA.scala:360:9] wire io_tlb_resp_ae_ld_0 = io_tlb_resp_ae_ld; // @[DMA.scala:360:9] wire io_tlb_resp_ae_st_0 = io_tlb_resp_ae_st; // @[DMA.scala:360:9] wire io_tlb_resp_ae_inst_0 = io_tlb_resp_ae_inst; // @[DMA.scala:360:9] wire io_tlb_resp_cacheable_0 = io_tlb_resp_cacheable; // @[DMA.scala:360:9] wire io_tlb_resp_must_alloc_0 = io_tlb_resp_must_alloc; // @[DMA.scala:360:9] wire io_tlb_resp_prefetchable_0 = io_tlb_resp_prefetchable; // @[DMA.scala:360:9] wire [4:0] io_tlb_resp_cmd_0 = io_tlb_resp_cmd; // @[DMA.scala:360:9] wire io_flush_0 = io_flush; // @[DMA.scala:360:9] wire io_counter_external_reset_0 = io_counter_external_reset; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_passthrough = 1'h0; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_v = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gpa_is_pte = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_inst = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_inst = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_0 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_1 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_2 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_3 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_4 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_5 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_6 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_7 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_8 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_9 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_10 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_11 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_12 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_13 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_14 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_15 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_16 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_17 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_18 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_19 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_20 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_24 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_25 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_26 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_27 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_28 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_29 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_30 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_31 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_32 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_33 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_34 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_35 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_36 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_37 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_38 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_39 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_40 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_41 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_42 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_43 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_44 = 1'h0; // @[DMA.scala:360:9] wire write_packets_mask_16 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_17 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_18 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_19 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_20 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_21 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_22 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_23 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_24 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_25 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_26 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_27 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_28 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_29 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_30 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_31 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_32 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63 = 1'h0; // @[DMA.scala:431:103] wire write_packets_0_mask_1_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_1_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_4_1_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_5 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_7 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_1 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_10 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_12 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_2 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_15 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_17 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_3 = 1'h0; // @[DMA.scala:457:38] wire write_packets_mask_32_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_1_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_7_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_9_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early_5 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_30 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_32 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_6 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_35 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_37 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_7 = 1'h0; // @[DMA.scala:457:38] wire write_packets_too_early_11 = 1'h0; // @[DMA.scala:457:38] wire _best_write_packet_T_1_mask_2_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_15 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_15 = 1'h0; // @[DMA.scala:466:10] wire _putFull_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putFull_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putFull_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putFull_corrupt = 1'h0; // @[Edges.scala:480:17] wire putFull_a_mask_sub_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_4_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_5_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_6_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_7_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_8 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _putPartial_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putPartial_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putPartial_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putPartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire untranslated_a_bits_tl_a_corrupt = 1'h0; // @[DMA.scala:506:30] wire _untranslated_a_bits_tl_a_T_corrupt = 1'h0; // @[DMA.scala:509:36] wire [1:0] io_tlb_req_bits_tlb_req_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_tlb_req_prv = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_resp_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] _putFull_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _putPartial_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [4:0] io_tlb_req_bits_tlb_req_cmd = 5'h1; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_0 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_1 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_2 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_3 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_4 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_6 = 32'h0; // @[DMA.scala:360:9] wire [31:0] putFull_address = 32'h0; // @[Edges.scala:480:17] wire [31:0] putPartial_address = 32'h0; // @[Edges.scala:500:17] wire [31:0] untranslated_a_bits_tl_a_address = 32'h0; // @[DMA.scala:506:30] wire [31:0] _untranslated_a_bits_tl_a_T_address = 32'h0; // @[DMA.scala:509:36] wire [2:0] putFull_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] putFull_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putPartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] untranslated_a_bits_tl_a_param = 3'h0; // @[DMA.scala:506:30] wire [2:0] _untranslated_a_bits_tl_a_T_param = 3'h0; // @[DMA.scala:509:36] wire [2:0] putPartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [32:0] _putFull_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _putFull_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _putPartial_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire _write_packets_mask_T_60 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_64 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_68 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_72 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_76 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_80 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_84 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_88 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_92 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_96 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_100 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_104 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_108 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_112 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_116 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_120 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_124 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_128 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_132 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_136 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_140 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_144 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_148 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_152 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_156 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_160 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_164 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_168 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_172 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_176 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_180 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_184 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_188 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_192 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_196 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_200 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_204 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_208 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_212 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_216 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_220 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_224 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_228 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_232 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_236 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_240 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_244 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_248 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_252 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T = 1'h1; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_1 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_2 = 1'h1; // @[DMA.scala:449:62] wire _write_packets_right_shift_T_1 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_6 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_11 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_16 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_380 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_384 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_388 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_392 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_396 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_400 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_404 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_408 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_412 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_416 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_420 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_424 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_428 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_432 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_436 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_440 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_444 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_448 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_452 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_456 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_460 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_464 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_468 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_472 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_476 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_480 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_484 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_488 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_492 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_496 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_500 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_504 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_508 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_20 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_33 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_26 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_31 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_36 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_764 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_40 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_65 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_56 = 1'h1; // @[DMA.scala:449:78] wire _putFull_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putFull_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putFull_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putFull_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putFull_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire putFull_a_mask_sub_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _putPartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putPartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putPartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putPartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putPartial_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire [32:0] _putFull_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putPartial_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [29:0] _putFull_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [29:0] _putPartial_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _putFull_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putFull_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [21:0] _putFull_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [21:0] _putPartial_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [14:0] _putFull_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [14:0] _putPartial_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [2:0] write_packets_2_lg_size = 3'h6; // @[DMA.scala:437:24] wire [6:0] write_packets_2_size = 7'h40; // @[DMA.scala:437:24] wire [5:0] write_packets_left_shift_2 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_3 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_6 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_7 = 6'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_1_lg_size = 3'h5; // @[DMA.scala:437:24] wire [6:0] write_packets_1_size = 7'h20; // @[DMA.scala:437:24] wire [4:0] write_packets_left_shift_1 = 5'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_0_lg_size = 3'h4; // @[DMA.scala:437:24] wire [6:0] write_packets_0_size = 7'h10; // @[DMA.scala:437:24] wire [16:0] _putFull_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _putPartial_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [31:0] _putFull_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _putPartial_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [28:0] _putFull_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [28:0] _putPartial_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [20:0] _putFull_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [20:0] _putPartial_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [13:0] _putFull_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire [13:0] _putPartial_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:360:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:360:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:360:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:360:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:360:9] wire state_machine_ready_for_req; // @[DMA.scala:401:47] wire [511:0] _pooled_v1_WIRE = io_req_bits_data_0; // @[DMA.scala:360:9, :593:43] wire _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] wire io_counter_event_signal_22_0 = io_tlb_resp_miss_0; // @[DMA.scala:360:9] wire _io_busy_T_2; // @[DMA.scala:403:29] wire io_counter_event_signal_21_0 = \|state; // @[DMA.scala:360:9, :380:24, :403:39] wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:360:9] wire [2:0] auto_out_a_bits_param_0; // @[DMA.scala:360:9] wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:360:9] wire [3:0] auto_out_a_bits_source_0; // @[DMA.scala:360:9] wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:360:9] wire [15:0] auto_out_a_bits_mask_0; // @[DMA.scala:360:9] wire [127:0] auto_out_a_bits_data_0; // @[DMA.scala:360:9] wire auto_out_a_bits_corrupt_0; // @[DMA.scala:360:9] wire auto_out_a_valid_0; // @[DMA.scala:360:9] wire auto_out_d_ready_0; // @[DMA.scala:360:9] wire io_req_ready_0; // @[DMA.scala:360:9] wire [39:0] io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_debug_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_cease_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_wfi_0; // @[DMA.scala:360:9] wire [31:0] io_tlb_req_bits_status_isa_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_dprv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_dv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_prv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_v_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_0; // @[DMA.scala:360:9] wire [22:0] io_tlb_req_bits_status_zero2_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_gva_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mbe_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sbe_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_sxl_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_uxl_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:360:9] wire [7:0] io_tlb_req_bits_status_zero1_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tsr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tw_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tvm_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mxr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sum_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mprv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_xs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_fs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_mpp_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_vs_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spp_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_ube_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_upie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_hie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_uie_0; // @[DMA.scala:360:9] wire io_tlb_req_valid_0; // @[DMA.scala:360:9] wire io_counter_event_signal_23_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_5_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_7_0; // @[DMA.scala:360:9] wire io_busy_0; // @[DMA.scala:360:9] wire _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:360:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:360:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DMA.scala:360:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:360:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:360:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:360:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:360:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:360:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[DMA.scala:360:9] wire _nodeOut_d_ready_T; // @[DMA.scala:551:28] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:360:9] reg [39:0] req_vaddr; // @[DMA.scala:382:18] reg [511:0] req_data; // @[DMA.scala:382:18] reg [6:0] req_len; // @[DMA.scala:382:18] reg [7:0] req_block; // @[DMA.scala:382:18] reg req_status_debug; // @[DMA.scala:382:18] wire untranslated_a_bits_status_debug = req_status_debug; // @[DMA.scala:382:18, :506:30] reg req_status_cease; // @[DMA.scala:382:18] wire untranslated_a_bits_status_cease = req_status_cease; // @[DMA.scala:382:18, :506:30] reg req_status_wfi; // @[DMA.scala:382:18] wire untranslated_a_bits_status_wfi = req_status_wfi; // @[DMA.scala:382:18, :506:30] reg [31:0] req_status_isa; // @[DMA.scala:382:18] wire [31:0] untranslated_a_bits_status_isa = req_status_isa; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_dprv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_dprv = req_status_dprv; // @[DMA.scala:382:18, :506:30] reg req_status_dv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_dv = req_status_dv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_prv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_prv = req_status_prv; // @[DMA.scala:382:18, :506:30] reg req_status_v; // @[DMA.scala:382:18] wire untranslated_a_bits_status_v = req_status_v; // @[DMA.scala:382:18, :506:30] reg req_status_sd; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd = req_status_sd; // @[DMA.scala:382:18, :506:30] reg [22:0] req_status_zero2; // @[DMA.scala:382:18] wire [22:0] untranslated_a_bits_status_zero2 = req_status_zero2; // @[DMA.scala:382:18, :506:30] reg req_status_mpv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpv = req_status_mpv; // @[DMA.scala:382:18, :506:30] reg req_status_gva; // @[DMA.scala:382:18] wire untranslated_a_bits_status_gva = req_status_gva; // @[DMA.scala:382:18, :506:30] reg req_status_mbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mbe = req_status_mbe; // @[DMA.scala:382:18, :506:30] reg req_status_sbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sbe = req_status_sbe; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_sxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_sxl = req_status_sxl; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_uxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_uxl = req_status_uxl; // @[DMA.scala:382:18, :506:30] reg req_status_sd_rv32; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd_rv32 = req_status_sd_rv32; // @[DMA.scala:382:18, :506:30] reg [7:0] req_status_zero1; // @[DMA.scala:382:18] wire [7:0] untranslated_a_bits_status_zero1 = req_status_zero1; // @[DMA.scala:382:18, :506:30] reg req_status_tsr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tsr = req_status_tsr; // @[DMA.scala:382:18, :506:30] reg req_status_tw; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tw = req_status_tw; // @[DMA.scala:382:18, :506:30] reg req_status_tvm; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tvm = req_status_tvm; // @[DMA.scala:382:18, :506:30] reg req_status_mxr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mxr = req_status_mxr; // @[DMA.scala:382:18, :506:30] reg req_status_sum; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sum = req_status_sum; // @[DMA.scala:382:18, :506:30] reg req_status_mprv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mprv = req_status_mprv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_xs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_xs = req_status_xs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_fs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_fs = req_status_fs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_mpp; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_mpp = req_status_mpp; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_vs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_vs = req_status_vs; // @[DMA.scala:382:18, :506:30] reg req_status_spp; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spp = req_status_spp; // @[DMA.scala:382:18, :506:30] reg req_status_mpie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpie = req_status_mpie; // @[DMA.scala:382:18, :506:30] reg req_status_ube; // @[DMA.scala:382:18] wire untranslated_a_bits_status_ube = req_status_ube; // @[DMA.scala:382:18, :506:30] reg req_status_spie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spie = req_status_spie; // @[DMA.scala:382:18, :506:30] reg req_status_upie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_upie = req_status_upie; // @[DMA.scala:382:18, :506:30] reg req_status_mie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mie = req_status_mie; // @[DMA.scala:382:18, :506:30] reg req_status_hie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_hie = req_status_hie; // @[DMA.scala:382:18, :506:30] reg req_status_sie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sie = req_status_sie; // @[DMA.scala:382:18, :506:30] reg req_status_uie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_uie = req_status_uie; // @[DMA.scala:382:18, :506:30] reg req_pool_en; // @[DMA.scala:382:18] reg req_store_en; // @[DMA.scala:382:18] reg [127:0] data_blocks_0; // @[DMA.scala:385:26] reg [127:0] data_blocks_1; // @[DMA.scala:385:26] reg [127:0] data_blocks_2; // @[DMA.scala:385:26] reg [127:0] data_blocks_3; // @[DMA.scala:385:26] reg [511:0] data_single_block; // @[DMA.scala:386:32] wire [511:0] _pooled_v2_WIRE = data_single_block; // @[DMA.scala:386:32, :594:44] wire _data_T = req_block == 8'h0; // @[DMA.scala:382:18, :387:30] wire [255:0] data_lo = {data_blocks_1, data_blocks_0}; // @[DMA.scala:385:26, :387:70] wire [255:0] data_hi = {data_blocks_3, data_blocks_2}; // @[DMA.scala:385:26, :387:70] wire [511:0] _data_T_1 = {data_hi, data_lo}; // @[DMA.scala:387:70] wire [511:0] data = _data_T ? data_single_block : _data_T_1; // @[DMA.scala:386:32, :387:{19,30,70}] reg [6:0] bytesSent; // @[DMA.scala:389:24] wire [7:0] _GEN = {1'h0, bytesSent}; // @[DMA.scala:389:24, :390:29] wire [7:0] _bytesLeft_T = {1'h0, req_len} - _GEN; // @[DMA.scala:382:18, :390:29] wire [6:0] bytesLeft = _bytesLeft_T[6:0]; // @[DMA.scala:390:29] reg [15:0] xactBusy; // @[DMA.scala:392:27] wire [15:0] _xactOnehot_T = ~xactBusy; // @[DMA.scala:392:27, :393:40] wire _xactOnehot_T_1 = _xactOnehot_T[0]; // @[OneHot.scala:85:71] wire _xactOnehot_T_2 = _xactOnehot_T[1]; // @[OneHot.scala:85:71] wire _xactOnehot_T_3 = _xactOnehot_T[2]; // @[OneHot.scala:85:71] wire _xactOnehot_T_4 = _xactOnehot_T[3]; // @[OneHot.scala:85:71] wire _xactOnehot_T_5 = _xactOnehot_T[4]; // @[OneHot.scala:85:71] wire _xactOnehot_T_6 = _xactOnehot_T[5]; // @[OneHot.scala:85:71] wire _xactOnehot_T_7 = _xactOnehot_T[6]; // @[OneHot.scala:85:71] wire _xactOnehot_T_8 = _xactOnehot_T[7]; // @[OneHot.scala:85:71] wire _xactOnehot_T_9 = _xactOnehot_T[8]; // @[OneHot.scala:85:71] wire _xactOnehot_T_10 = _xactOnehot_T[9]; // @[OneHot.scala:85:71] wire _xactOnehot_T_11 = _xactOnehot_T[10]; // @[OneHot.scala:85:71] wire _xactOnehot_T_12 = _xactOnehot_T[11]; // @[OneHot.scala:85:71] wire _xactOnehot_T_13 = _xactOnehot_T[12]; // @[OneHot.scala:85:71] wire _xactOnehot_T_14 = _xactOnehot_T[13]; // @[OneHot.scala:85:71] wire _xactOnehot_T_15 = _xactOnehot_T[14]; // @[OneHot.scala:85:71] wire _xactOnehot_T_16 = _xactOnehot_T[15]; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_17 = {_xactOnehot_T_16, 15'h0}; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_18 = _xactOnehot_T_15 ? 16'h4000 : _xactOnehot_T_17; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_19 = _xactOnehot_T_14 ? 16'h2000 : _xactOnehot_T_18; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_20 = _xactOnehot_T_13 ? 16'h1000 : _xactOnehot_T_19; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_21 = _xactOnehot_T_12 ? 16'h800 : _xactOnehot_T_20; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_22 = _xactOnehot_T_11 ? 16'h400 : _xactOnehot_T_21; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_23 = _xactOnehot_T_10 ? 16'h200 : _xactOnehot_T_22; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_24 = _xactOnehot_T_9 ? 16'h100 : _xactOnehot_T_23; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_25 = _xactOnehot_T_8 ? 16'h80 : _xactOnehot_T_24; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_26 = _xactOnehot_T_7 ? 16'h40 : _xactOnehot_T_25; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_27 = _xactOnehot_T_6 ? 16'h20 : _xactOnehot_T_26; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_28 = _xactOnehot_T_5 ? 16'h10 : _xactOnehot_T_27; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_29 = _xactOnehot_T_4 ? 16'h8 : _xactOnehot_T_28; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_30 = _xactOnehot_T_3 ? 16'h4 : _xactOnehot_T_29; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_31 = _xactOnehot_T_2 ? 16'h2 : _xactOnehot_T_30; // @[OneHot.scala:85:71] wire [15:0] xactOnehot = _xactOnehot_T_1 ? 16'h1 : _xactOnehot_T_31; // @[OneHot.scala:85:71] wire [7:0] xactId_hi = xactOnehot[15:8]; // @[OneHot.scala:30:18] wire [7:0] xactId_lo = xactOnehot[7:0]; // @[OneHot.scala:31:18] wire _xactId_T = \|xactId_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _xactId_T_1 = xactId_hi \| xactId_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] xactId_hi_1 = _xactId_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] xactId_lo_1 = _xactId_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_2 = \|xactId_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _xactId_T_3 = xactId_hi_1 \| xactId_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] xactId_hi_2 = _xactId_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] xactId_lo_2 = _xactId_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_4 = \|xactId_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _xactId_T_5 = xactId_hi_2 \| xactId_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _xactId_T_6 = _xactId_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _xactId_T_7 = {_xactId_T_4, _xactId_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _xactId_T_8 = {_xactId_T_2, _xactId_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] xactId = {_xactId_T, _xactId_T_8}; // @[OneHot.scala:32:{10,14}] wire _xactBusy_fire_T_2; // @[DMA.scala:507:42] wire xactBusy_fire; // @[DMA.scala:396:33] wire [15:0] _xactBusy_add_T = 16'h1 << xactId; // @[OneHot.scala:32:10] wire [15:0] xactBusy_add = xactBusy_fire ? _xactBusy_add_T : 16'h0; // @[DMA.scala:396:33, :397:{27,48}] wire _xactBusy_remove_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire [15:0] _xactBusy_remove_T_1 = 16'h1 << nodeOut_d_bits_source; // @[DMA.scala:398:48] wire [15:0] _xactBusy_remove_T_2 = _xactBusy_remove_T ? _xactBusy_remove_T_1 : 16'h0; // @[Decoupled.scala:51:35] wire [15:0] xactBusy_remove = ~_xactBusy_remove_T_2; // @[DMA.scala:398:{27,31}] wire [15:0] _xactBusy_T = xactBusy \| xactBusy_add; // @[DMA.scala:392:27, :397:27, :399:27] wire [15:0] _xactBusy_T_1 = _xactBusy_T & xactBusy_remove; // @[DMA.scala:398:27, :399:{27,43}] wire _state_machine_ready_for_req_T = state == 2'h0; // @[DMA.scala:380:24, :401:54] assign io_req_ready_0 = state_machine_ready_for_req; // @[DMA.scala:360:9, :401:47] wire _io_busy_T = \|xactBusy; // @[DMA.scala:392:27, :403:25] wire _io_busy_T_1 = \|state; // @[DMA.scala:380:24, :403:39] assign _io_busy_T_2 = _io_busy_T \| _io_busy_T_1; // @[DMA.scala:403:{25,29,39}] assign io_busy_0 = _io_busy_T_2; // @[DMA.scala:360:9, :403:29] wire [34:0] _write_packets_vaddr_aligned_to_size_T = req_vaddr[38:4]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size = {_write_packets_vaddr_aligned_to_size_T, 4'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_0_vaddr = write_packets_vaddr_aligned_to_size; // @[DMA.scala:428:61, :437:24] wire [3:0] write_packets_vaddr_offset = req_vaddr[3:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T = write_packets_vaddr_offset == 4'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_0 = {1'h0, bytesLeft}; // @[DMA.scala:390:29, :431:90] wire [7:0] _GEN_1 = {4'h0, write_packets_vaddr_offset} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_1; // @[DMA.scala:431:90] assign _write_packets_mask_T_1 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_5; // @[DMA.scala:431:90] assign _write_packets_mask_T_5 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_9; // @[DMA.scala:431:90] assign _write_packets_mask_T_9 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_13; // @[DMA.scala:431:90] assign _write_packets_mask_T_13 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_17; // @[DMA.scala:431:90] assign _write_packets_mask_T_17 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_21; // @[DMA.scala:431:90] assign _write_packets_mask_T_21 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_25; // @[DMA.scala:431:90] assign _write_packets_mask_T_25 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_29; // @[DMA.scala:431:90] assign _write_packets_mask_T_29 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_33; // @[DMA.scala:431:90] assign _write_packets_mask_T_33 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_37; // @[DMA.scala:431:90] assign _write_packets_mask_T_37 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_41; // @[DMA.scala:431:90] assign _write_packets_mask_T_41 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_45; // @[DMA.scala:431:90] assign _write_packets_mask_T_45 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_49; // @[DMA.scala:431:90] assign _write_packets_mask_T_49 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_53; // @[DMA.scala:431:90] assign _write_packets_mask_T_53 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_57; // @[DMA.scala:431:90] assign _write_packets_mask_T_57 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_61; // @[DMA.scala:431:90] assign _write_packets_mask_T_61 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_65; // @[DMA.scala:431:90] assign _write_packets_mask_T_65 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_69; // @[DMA.scala:431:90] assign _write_packets_mask_T_69 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_73; // @[DMA.scala:431:90] assign _write_packets_mask_T_73 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_77; // @[DMA.scala:431:90] assign _write_packets_mask_T_77 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_81; // @[DMA.scala:431:90] assign _write_packets_mask_T_81 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_85; // @[DMA.scala:431:90] assign _write_packets_mask_T_85 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_89; // @[DMA.scala:431:90] assign _write_packets_mask_T_89 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_93; // @[DMA.scala:431:90] assign _write_packets_mask_T_93 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_97; // @[DMA.scala:431:90] assign _write_packets_mask_T_97 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_101; // @[DMA.scala:431:90] assign _write_packets_mask_T_101 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_105; // @[DMA.scala:431:90] assign _write_packets_mask_T_105 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_109; // @[DMA.scala:431:90] assign _write_packets_mask_T_109 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_113; // @[DMA.scala:431:90] assign _write_packets_mask_T_113 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_117; // @[DMA.scala:431:90] assign _write_packets_mask_T_117 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_121; // @[DMA.scala:431:90] assign _write_packets_mask_T_121 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_125; // @[DMA.scala:431:90] assign _write_packets_mask_T_125 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_129; // @[DMA.scala:431:90] assign _write_packets_mask_T_129 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_133; // @[DMA.scala:431:90] assign _write_packets_mask_T_133 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_137; // @[DMA.scala:431:90] assign _write_packets_mask_T_137 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_141; // @[DMA.scala:431:90] assign _write_packets_mask_T_141 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_145; // @[DMA.scala:431:90] assign _write_packets_mask_T_145 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_149; // @[DMA.scala:431:90] assign _write_packets_mask_T_149 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_153; // @[DMA.scala:431:90] assign _write_packets_mask_T_153 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_157; // @[DMA.scala:431:90] assign _write_packets_mask_T_157 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_161; // @[DMA.scala:431:90] assign _write_packets_mask_T_161 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_165; // @[DMA.scala:431:90] assign _write_packets_mask_T_165 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_169; // @[DMA.scala:431:90] assign _write_packets_mask_T_169 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_173; // @[DMA.scala:431:90] assign _write_packets_mask_T_173 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_177; // @[DMA.scala:431:90] assign _write_packets_mask_T_177 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_181; // @[DMA.scala:431:90] assign _write_packets_mask_T_181 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_185; // @[DMA.scala:431:90] assign _write_packets_mask_T_185 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_189; // @[DMA.scala:431:90] assign _write_packets_mask_T_189 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_193; // @[DMA.scala:431:90] assign _write_packets_mask_T_193 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_197; // @[DMA.scala:431:90] assign _write_packets_mask_T_197 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_201; // @[DMA.scala:431:90] assign _write_packets_mask_T_201 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_205; // @[DMA.scala:431:90] assign _write_packets_mask_T_205 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_209; // @[DMA.scala:431:90] assign _write_packets_mask_T_209 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_213; // @[DMA.scala:431:90] assign _write_packets_mask_T_213 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_217; // @[DMA.scala:431:90] assign _write_packets_mask_T_217 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_221; // @[DMA.scala:431:90] assign _write_packets_mask_T_221 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_225; // @[DMA.scala:431:90] assign _write_packets_mask_T_225 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_229; // @[DMA.scala:431:90] assign _write_packets_mask_T_229 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_233; // @[DMA.scala:431:90] assign _write_packets_mask_T_233 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_237; // @[DMA.scala:431:90] assign _write_packets_mask_T_237 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_241; // @[DMA.scala:431:90] assign _write_packets_mask_T_241 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_245; // @[DMA.scala:431:90] assign _write_packets_mask_T_245 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_249; // @[DMA.scala:431:90] assign _write_packets_mask_T_249 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_253; // @[DMA.scala:431:90] assign _write_packets_mask_T_253 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T = _GEN_1; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T; // @[DMA.scala:453:44] assign _write_packets_right_shift_T = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_2; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_2 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_5; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_5 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T; // @[DMA.scala:458:37] assign _write_packets_too_late_T = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_8; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_8 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_10; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_10 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_13; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_13 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_1; // @[DMA.scala:458:37] assign _write_packets_too_late_T_1 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_16; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_16 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_18; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_18 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_21; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_21 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_2; // @[DMA.scala:458:37] assign _write_packets_too_late_T_2 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_24; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_24 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_26; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_26 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_29; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_29 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_3; // @[DMA.scala:458:37] assign _write_packets_too_late_T_3 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_2 = \|_write_packets_mask_T_1; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_3 = _write_packets_mask_T & _write_packets_mask_T_2; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0 = _write_packets_mask_T_3; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_0 = write_packets_mask_0; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_4 = write_packets_vaddr_offset < 4'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_6 = \|(_write_packets_mask_T_5[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_7 = _write_packets_mask_T_4 & _write_packets_mask_T_6; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1 = _write_packets_mask_T_7; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_1 = write_packets_mask_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_8 = write_packets_vaddr_offset < 4'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_10 = _write_packets_mask_T_9 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_11 = _write_packets_mask_T_8 & _write_packets_mask_T_10; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2 = _write_packets_mask_T_11; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_2 = write_packets_mask_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_12 = write_packets_vaddr_offset < 4'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_14 = \|(_write_packets_mask_T_13[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_15 = _write_packets_mask_T_12 & _write_packets_mask_T_14; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3 = _write_packets_mask_T_15; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_3 = write_packets_mask_3; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_16 = write_packets_vaddr_offset < 4'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_18 = _write_packets_mask_T_17 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_19 = _write_packets_mask_T_16 & _write_packets_mask_T_18; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4 = _write_packets_mask_T_19; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_4 = write_packets_mask_4; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_20 = write_packets_vaddr_offset < 4'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_22 = _write_packets_mask_T_21 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_23 = _write_packets_mask_T_20 & _write_packets_mask_T_22; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5 = _write_packets_mask_T_23; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5 = write_packets_mask_5; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_24 = write_packets_vaddr_offset < 4'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_26 = _write_packets_mask_T_25 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_27 = _write_packets_mask_T_24 & _write_packets_mask_T_26; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6 = _write_packets_mask_T_27; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6 = write_packets_mask_6; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_28 = ~(write_packets_vaddr_offset[3]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_30 = \|(_write_packets_mask_T_29[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_31 = _write_packets_mask_T_28 & _write_packets_mask_T_30; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7 = _write_packets_mask_T_31; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_7 = write_packets_mask_7; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_32 = write_packets_vaddr_offset < 4'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_34 = _write_packets_mask_T_33 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_35 = _write_packets_mask_T_32 & _write_packets_mask_T_34; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8 = _write_packets_mask_T_35; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_8 = write_packets_mask_8; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_36 = write_packets_vaddr_offset < 4'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_38 = _write_packets_mask_T_37 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_39 = _write_packets_mask_T_36 & _write_packets_mask_T_38; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9 = _write_packets_mask_T_39; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_9 = write_packets_mask_9; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_40 = write_packets_vaddr_offset < 4'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_42 = _write_packets_mask_T_41 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_43 = _write_packets_mask_T_40 & _write_packets_mask_T_42; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10 = _write_packets_mask_T_43; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10 = write_packets_mask_10; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_44 = write_packets_vaddr_offset[3:2] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_46 = _write_packets_mask_T_45 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_47 = _write_packets_mask_T_44 & _write_packets_mask_T_46; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11 = _write_packets_mask_T_47; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11 = write_packets_mask_11; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_48 = write_packets_vaddr_offset < 4'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_50 = _write_packets_mask_T_49 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_51 = _write_packets_mask_T_48 & _write_packets_mask_T_50; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12 = _write_packets_mask_T_51; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12 = write_packets_mask_12; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_52 = write_packets_vaddr_offset[3:1] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_54 = _write_packets_mask_T_53 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_55 = _write_packets_mask_T_52 & _write_packets_mask_T_54; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13 = _write_packets_mask_T_55; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13 = write_packets_mask_13; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_56 = write_packets_vaddr_offset != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_58 = _write_packets_mask_T_57 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_59 = _write_packets_mask_T_56 & _write_packets_mask_T_58; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14 = _write_packets_mask_T_59; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_14 = write_packets_mask_14; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_62 = \|(_write_packets_mask_T_61[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_63 = _write_packets_mask_T_62; // @[DMA.scala:431:{68,75}] wire write_packets_mask_15 = _write_packets_mask_T_63; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_15 = write_packets_mask_15; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_66 = _write_packets_mask_T_65 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_67 = _write_packets_mask_T_66; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_70 = _write_packets_mask_T_69 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_71 = _write_packets_mask_T_70; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_74 = _write_packets_mask_T_73 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_75 = _write_packets_mask_T_74; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_78 = _write_packets_mask_T_77 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_79 = _write_packets_mask_T_78; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_82 = _write_packets_mask_T_81 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_83 = _write_packets_mask_T_82; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_86 = _write_packets_mask_T_85 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_87 = _write_packets_mask_T_86; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_90 = _write_packets_mask_T_89 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_91 = _write_packets_mask_T_90; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_94 = _write_packets_mask_T_93 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_95 = _write_packets_mask_T_94; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_98 = _write_packets_mask_T_97 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_99 = _write_packets_mask_T_98; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_102 = _write_packets_mask_T_101 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_103 = _write_packets_mask_T_102; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_106 = _write_packets_mask_T_105 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_107 = _write_packets_mask_T_106; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_110 = _write_packets_mask_T_109 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_111 = _write_packets_mask_T_110; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_114 = _write_packets_mask_T_113 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_115 = _write_packets_mask_T_114; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_118 = _write_packets_mask_T_117 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_119 = _write_packets_mask_T_118; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_122 = _write_packets_mask_T_121 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_123 = _write_packets_mask_T_122; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_126 = \|(_write_packets_mask_T_125[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_127 = _write_packets_mask_T_126; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_130 = _write_packets_mask_T_129 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_131 = _write_packets_mask_T_130; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_134 = _write_packets_mask_T_133 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_135 = _write_packets_mask_T_134; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_138 = _write_packets_mask_T_137 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_139 = _write_packets_mask_T_138; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_142 = _write_packets_mask_T_141 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_143 = _write_packets_mask_T_142; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_146 = _write_packets_mask_T_145 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_147 = _write_packets_mask_T_146; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_150 = _write_packets_mask_T_149 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_151 = _write_packets_mask_T_150; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_154 = _write_packets_mask_T_153 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_155 = _write_packets_mask_T_154; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_158 = _write_packets_mask_T_157 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_159 = _write_packets_mask_T_158; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_162 = _write_packets_mask_T_161 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_163 = _write_packets_mask_T_162; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_166 = _write_packets_mask_T_165 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_167 = _write_packets_mask_T_166; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_170 = _write_packets_mask_T_169 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_171 = _write_packets_mask_T_170; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_174 = _write_packets_mask_T_173 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_175 = _write_packets_mask_T_174; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_178 = _write_packets_mask_T_177 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_179 = _write_packets_mask_T_178; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_182 = _write_packets_mask_T_181 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_183 = _write_packets_mask_T_182; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_186 = _write_packets_mask_T_185 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_187 = _write_packets_mask_T_186; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_190 = _write_packets_mask_T_189 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_191 = _write_packets_mask_T_190; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_194 = _write_packets_mask_T_193 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_195 = _write_packets_mask_T_194; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_198 = _write_packets_mask_T_197 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_199 = _write_packets_mask_T_198; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_202 = _write_packets_mask_T_201 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_203 = _write_packets_mask_T_202; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_206 = _write_packets_mask_T_205 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_207 = _write_packets_mask_T_206; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_210 = _write_packets_mask_T_209 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_211 = _write_packets_mask_T_210; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_214 = _write_packets_mask_T_213 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_215 = _write_packets_mask_T_214; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_218 = _write_packets_mask_T_217 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_219 = _write_packets_mask_T_218; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_222 = _write_packets_mask_T_221 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_223 = _write_packets_mask_T_222; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_226 = _write_packets_mask_T_225 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_227 = _write_packets_mask_T_226; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_230 = _write_packets_mask_T_229 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_231 = _write_packets_mask_T_230; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_234 = _write_packets_mask_T_233 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_235 = _write_packets_mask_T_234; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_238 = _write_packets_mask_T_237 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_239 = _write_packets_mask_T_238; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_242 = _write_packets_mask_T_241 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_243 = _write_packets_mask_T_242; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_246 = _write_packets_mask_T_245 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_247 = _write_packets_mask_T_246; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_250 = _write_packets_mask_T_249 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_251 = _write_packets_mask_T_250; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_254 = \|(_write_packets_mask_T_253[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_255 = _write_packets_mask_T_254; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_1 = _write_packets_bytes_written_T > 8'h10; // @[DMA.scala:434:{26,39}] wire [5:0] _GEN_2 = {2'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :434:50] wire [5:0] _write_packets_bytes_written_T_2 = 6'h10 - _GEN_2; // @[DMA.scala:434:50] wire [4:0] _write_packets_bytes_written_T_3 = _write_packets_bytes_written_T_2[4:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written = _write_packets_bytes_written_T_1 ? {2'h0, _write_packets_bytes_written_T_3} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_0_bytes_written = write_packets_bytes_written; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_4_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_14; // @[DMA.scala:442:47] wire write_packets_0_mask_0_0; // @[DMA.scala:437:24] wire write_packets_0_mask_0_1; // @[DMA.scala:437:24] wire write_packets_0_mask_0_2; // @[DMA.scala:437:24] wire write_packets_0_mask_0_3; // @[DMA.scala:437:24] wire write_packets_0_mask_0_4; // @[DMA.scala:437:24] wire write_packets_0_mask_0_5; // @[DMA.scala:437:24] wire write_packets_0_mask_0_6; // @[DMA.scala:437:24] wire write_packets_0_mask_0_7; // @[DMA.scala:437:24] wire write_packets_0_mask_0_8; // @[DMA.scala:437:24] wire write_packets_0_mask_0_9; // @[DMA.scala:437:24] wire write_packets_0_mask_0_10; // @[DMA.scala:437:24] wire write_packets_0_mask_0_11; // @[DMA.scala:437:24] wire write_packets_0_mask_0_12; // @[DMA.scala:437:24] wire write_packets_0_mask_0_13; // @[DMA.scala:437:24] wire write_packets_0_mask_0_14; // @[DMA.scala:437:24] wire write_packets_0_mask_0_15; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_0_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_4_0_0 = _write_packets_WIRE_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_1 = _write_packets_WIRE_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_2 = _write_packets_WIRE_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_3 = _write_packets_WIRE_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_4 = _write_packets_WIRE_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_5 = _write_packets_WIRE_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_6 = _write_packets_WIRE_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_7 = _write_packets_WIRE_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_8 = _write_packets_WIRE_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_9 = _write_packets_WIRE_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_10 = _write_packets_WIRE_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_11 = _write_packets_WIRE_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_12 = _write_packets_WIRE_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_13 = _write_packets_WIRE_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_14 = _write_packets_WIRE_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_15 = _write_packets_WIRE_15; // @[DMA.scala:440:{29,70}] assign write_packets_0_mask_0_0 = _write_packets_WIRE_4_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_1 = _write_packets_WIRE_4_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_2 = _write_packets_WIRE_4_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_3 = _write_packets_WIRE_4_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_4 = _write_packets_WIRE_4_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_5 = _write_packets_WIRE_4_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_6 = _write_packets_WIRE_4_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_7 = _write_packets_WIRE_4_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_8 = _write_packets_WIRE_4_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_9 = _write_packets_WIRE_4_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_10 = _write_packets_WIRE_4_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_11 = _write_packets_WIRE_4_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_12 = _write_packets_WIRE_4_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_13 = _write_packets_WIRE_4_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_14 = _write_packets_WIRE_4_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_15 = _write_packets_WIRE_4_0_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T = write_packets_mask_0 & write_packets_mask_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_1 = _write_packets_packet_is_full_T & write_packets_mask_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_2 = _write_packets_packet_is_full_T_1 & write_packets_mask_3; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_3 = _write_packets_packet_is_full_T_2 & write_packets_mask_4; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_4 = _write_packets_packet_is_full_T_3 & write_packets_mask_5; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_5 = _write_packets_packet_is_full_T_4 & write_packets_mask_6; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_6 = _write_packets_packet_is_full_T_5 & write_packets_mask_7; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_7 = _write_packets_packet_is_full_T_6 & write_packets_mask_8; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_8 = _write_packets_packet_is_full_T_7 & write_packets_mask_9; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_9 = _write_packets_packet_is_full_T_8 & write_packets_mask_10; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_10 = _write_packets_packet_is_full_T_9 & write_packets_mask_11; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_11 = _write_packets_packet_is_full_T_10 & write_packets_mask_12; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_12 = _write_packets_packet_is_full_T_11 & write_packets_mask_13; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_13 = _write_packets_packet_is_full_T_12 & write_packets_mask_14; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_14 = _write_packets_packet_is_full_T_13 & write_packets_mask_15; // @[DMA.scala:431:103, :442:47] assign write_packets_0_is_full = _write_packets_packet_is_full_T_14; // @[DMA.scala:437:24, :442:47] wire [4:0] _write_packets_left_shift_T_3 = {1'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [3:0] _write_packets_left_shift_T_4 = _write_packets_left_shift_T_3[3:0]; // @[DMA.scala:450:24] wire [3:0] write_packets_left_shift = _write_packets_left_shift_T_4; // @[DMA.scala:449:29, :450:24] wire _write_packets_right_shift_T_3 = _write_packets_right_shift_T_2 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_4 = _write_packets_right_shift_T_3; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_6 = 9'h10 - {1'h0, _write_packets_right_shift_T_5}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_7 = _write_packets_right_shift_T_6[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift = _write_packets_right_shift_T_4 ? _write_packets_right_shift_T_7 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late = _write_packets_too_late_T == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T = write_packets_too_late; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_1 = {5'h0, write_packets_left_shift} + {1'h0, write_packets_right_shift}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_3 = _write_packets_packet_bytes_written_per_beat_0_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_4 = _write_packets_packet_bytes_written_per_beat_0_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [5:0] _write_packets_left_shift_T_8 = _GEN_2 - 6'h10; // @[DMA.scala:434:50, :450:24] wire [4:0] _write_packets_left_shift_T_9 = _write_packets_left_shift_T_8[4:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_9 = \|(_write_packets_right_shift_T_8[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_11 = _write_packets_right_shift_T_10 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_12 = _write_packets_right_shift_T_9 & _write_packets_right_shift_T_11; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_14 = 9'h20 - {1'h0, _write_packets_right_shift_T_13}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_15 = _write_packets_right_shift_T_14[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_1 = _write_packets_right_shift_T_12 ? _write_packets_right_shift_T_15 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_1 = _write_packets_too_late_T_1 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T = write_packets_too_late_1; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_1 = {1'h0, write_packets_right_shift_1}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_3 = _write_packets_packet_bytes_written_per_beat_1_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_4 = _write_packets_packet_bytes_written_per_beat_1_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _GEN_3 = {3'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [6:0] _write_packets_left_shift_T_13 = _GEN_3 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_14 = _write_packets_left_shift_T_13[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_17 = \|(_write_packets_right_shift_T_16[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_19 = _write_packets_right_shift_T_18 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_20 = _write_packets_right_shift_T_17 & _write_packets_right_shift_T_19; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_22 = 9'h30 - {1'h0, _write_packets_right_shift_T_21}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_23 = _write_packets_right_shift_T_22[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_2 = _write_packets_right_shift_T_20 ? _write_packets_right_shift_T_23 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_2 = _write_packets_too_late_T_2 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T = write_packets_too_late_2; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_1 = {1'h0, write_packets_right_shift_2}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_3 = _write_packets_packet_bytes_written_per_beat_2_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_4 = _write_packets_packet_bytes_written_per_beat_2_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_18 = _GEN_3 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_19 = _write_packets_left_shift_T_18[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_25 = _write_packets_right_shift_T_24 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_27 = _write_packets_right_shift_T_26 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_28 = _write_packets_right_shift_T_25 & _write_packets_right_shift_T_27; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_30 = 9'h40 - {1'h0, _write_packets_right_shift_T_29}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_31 = _write_packets_right_shift_T_30[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_3 = _write_packets_right_shift_T_28 ? _write_packets_right_shift_T_31 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_3 = _write_packets_too_late_T_3 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T = write_packets_too_late_3; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_1 = {1'h0, write_packets_right_shift_3}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_3 = _write_packets_packet_bytes_written_per_beat_3_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_4 = _write_packets_packet_bytes_written_per_beat_3_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [33:0] _write_packets_vaddr_aligned_to_size_T_1 = req_vaddr[38:5]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_1 = {_write_packets_vaddr_aligned_to_size_T_1, 5'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_1_vaddr = write_packets_vaddr_aligned_to_size_1; // @[DMA.scala:428:61, :437:24] wire [4:0] write_packets_vaddr_offset_1 = req_vaddr[4:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_256 = write_packets_vaddr_offset_1 == 5'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_4 = {3'h0, write_packets_vaddr_offset_1} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_257; // @[DMA.scala:431:90] assign _write_packets_mask_T_257 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_261; // @[DMA.scala:431:90] assign _write_packets_mask_T_261 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_265; // @[DMA.scala:431:90] assign _write_packets_mask_T_265 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_269; // @[DMA.scala:431:90] assign _write_packets_mask_T_269 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_273; // @[DMA.scala:431:90] assign _write_packets_mask_T_273 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_277; // @[DMA.scala:431:90] assign _write_packets_mask_T_277 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_281; // @[DMA.scala:431:90] assign _write_packets_mask_T_281 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_285; // @[DMA.scala:431:90] assign _write_packets_mask_T_285 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_289; // @[DMA.scala:431:90] assign _write_packets_mask_T_289 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_293; // @[DMA.scala:431:90] assign _write_packets_mask_T_293 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_297; // @[DMA.scala:431:90] assign _write_packets_mask_T_297 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_301; // @[DMA.scala:431:90] assign _write_packets_mask_T_301 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_305; // @[DMA.scala:431:90] assign _write_packets_mask_T_305 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_309; // @[DMA.scala:431:90] assign _write_packets_mask_T_309 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_313; // @[DMA.scala:431:90] assign _write_packets_mask_T_313 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_317; // @[DMA.scala:431:90] assign _write_packets_mask_T_317 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_321; // @[DMA.scala:431:90] assign _write_packets_mask_T_321 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_325; // @[DMA.scala:431:90] assign _write_packets_mask_T_325 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_329; // @[DMA.scala:431:90] assign _write_packets_mask_T_329 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_333; // @[DMA.scala:431:90] assign _write_packets_mask_T_333 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_337; // @[DMA.scala:431:90] assign _write_packets_mask_T_337 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_341; // @[DMA.scala:431:90] assign _write_packets_mask_T_341 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_345; // @[DMA.scala:431:90] assign _write_packets_mask_T_345 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_349; // @[DMA.scala:431:90] assign _write_packets_mask_T_349 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_353; // @[DMA.scala:431:90] assign _write_packets_mask_T_353 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_357; // @[DMA.scala:431:90] assign _write_packets_mask_T_357 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_361; // @[DMA.scala:431:90] assign _write_packets_mask_T_361 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_365; // @[DMA.scala:431:90] assign _write_packets_mask_T_365 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_369; // @[DMA.scala:431:90] assign _write_packets_mask_T_369 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_373; // @[DMA.scala:431:90] assign _write_packets_mask_T_373 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_377; // @[DMA.scala:431:90] assign _write_packets_mask_T_377 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_381; // @[DMA.scala:431:90] assign _write_packets_mask_T_381 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_385; // @[DMA.scala:431:90] assign _write_packets_mask_T_385 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_389; // @[DMA.scala:431:90] assign _write_packets_mask_T_389 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_393; // @[DMA.scala:431:90] assign _write_packets_mask_T_393 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_397; // @[DMA.scala:431:90] assign _write_packets_mask_T_397 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_401; // @[DMA.scala:431:90] assign _write_packets_mask_T_401 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_405; // @[DMA.scala:431:90] assign _write_packets_mask_T_405 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_409; // @[DMA.scala:431:90] assign _write_packets_mask_T_409 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_413; // @[DMA.scala:431:90] assign _write_packets_mask_T_413 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_417; // @[DMA.scala:431:90] assign _write_packets_mask_T_417 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_421; // @[DMA.scala:431:90] assign _write_packets_mask_T_421 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_425; // @[DMA.scala:431:90] assign _write_packets_mask_T_425 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_429; // @[DMA.scala:431:90] assign _write_packets_mask_T_429 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_433; // @[DMA.scala:431:90] assign _write_packets_mask_T_433 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_437; // @[DMA.scala:431:90] assign _write_packets_mask_T_437 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_441; // @[DMA.scala:431:90] assign _write_packets_mask_T_441 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_445; // @[DMA.scala:431:90] assign _write_packets_mask_T_445 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_449; // @[DMA.scala:431:90] assign _write_packets_mask_T_449 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_453; // @[DMA.scala:431:90] assign _write_packets_mask_T_453 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_457; // @[DMA.scala:431:90] assign _write_packets_mask_T_457 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_461; // @[DMA.scala:431:90] assign _write_packets_mask_T_461 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_465; // @[DMA.scala:431:90] assign _write_packets_mask_T_465 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_469; // @[DMA.scala:431:90] assign _write_packets_mask_T_469 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_473; // @[DMA.scala:431:90] assign _write_packets_mask_T_473 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_477; // @[DMA.scala:431:90] assign _write_packets_mask_T_477 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_481; // @[DMA.scala:431:90] assign _write_packets_mask_T_481 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_485; // @[DMA.scala:431:90] assign _write_packets_mask_T_485 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_489; // @[DMA.scala:431:90] assign _write_packets_mask_T_489 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_493; // @[DMA.scala:431:90] assign _write_packets_mask_T_493 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_497; // @[DMA.scala:431:90] assign _write_packets_mask_T_497 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_501; // @[DMA.scala:431:90] assign _write_packets_mask_T_501 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_505; // @[DMA.scala:431:90] assign _write_packets_mask_T_505 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_509; // @[DMA.scala:431:90] assign _write_packets_mask_T_509 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_4; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_4 = _GEN_4; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_32; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_32 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_34; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_34 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_37; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_37 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_4; // @[DMA.scala:458:37] assign _write_packets_too_late_T_4 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_40; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_40 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_42; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_42 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_45; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_45 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_5; // @[DMA.scala:458:37] assign _write_packets_too_late_T_5 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_48; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_48 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_50; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_50 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_53; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_53 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_6; // @[DMA.scala:458:37] assign _write_packets_too_late_T_6 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_56; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_56 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_58; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_58 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_61; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_61 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_7; // @[DMA.scala:458:37] assign _write_packets_too_late_T_7 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_258 = \|_write_packets_mask_T_257; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_259 = _write_packets_mask_T_256 & _write_packets_mask_T_258; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_1 = _write_packets_mask_T_259; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_0 = write_packets_mask_0_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_260 = write_packets_vaddr_offset_1 < 5'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_262 = \|(_write_packets_mask_T_261[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_263 = _write_packets_mask_T_260 & _write_packets_mask_T_262; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_1 = _write_packets_mask_T_263; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_1 = write_packets_mask_1_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_264 = write_packets_vaddr_offset_1 < 5'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_266 = _write_packets_mask_T_265 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_267 = _write_packets_mask_T_264 & _write_packets_mask_T_266; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_1 = _write_packets_mask_T_267; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_2 = write_packets_mask_2_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_268 = write_packets_vaddr_offset_1 < 5'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_270 = \|(_write_packets_mask_T_269[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_271 = _write_packets_mask_T_268 & _write_packets_mask_T_270; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_1 = _write_packets_mask_T_271; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_3 = write_packets_mask_3_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_272 = write_packets_vaddr_offset_1 < 5'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_274 = _write_packets_mask_T_273 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_275 = _write_packets_mask_T_272 & _write_packets_mask_T_274; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_1 = _write_packets_mask_T_275; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_4 = write_packets_mask_4_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_276 = write_packets_vaddr_offset_1 < 5'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_278 = _write_packets_mask_T_277 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_279 = _write_packets_mask_T_276 & _write_packets_mask_T_278; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_1 = _write_packets_mask_T_279; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_5 = write_packets_mask_5_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_280 = write_packets_vaddr_offset_1 < 5'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_282 = _write_packets_mask_T_281 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_283 = _write_packets_mask_T_280 & _write_packets_mask_T_282; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_1 = _write_packets_mask_T_283; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_6 = write_packets_mask_6_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_284 = write_packets_vaddr_offset_1 < 5'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_286 = \|(_write_packets_mask_T_285[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_287 = _write_packets_mask_T_284 & _write_packets_mask_T_286; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_1 = _write_packets_mask_T_287; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_7 = write_packets_mask_7_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_288 = write_packets_vaddr_offset_1 < 5'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_290 = _write_packets_mask_T_289 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_291 = _write_packets_mask_T_288 & _write_packets_mask_T_290; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_1 = _write_packets_mask_T_291; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_8 = write_packets_mask_8_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_292 = write_packets_vaddr_offset_1 < 5'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_294 = _write_packets_mask_T_293 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_295 = _write_packets_mask_T_292 & _write_packets_mask_T_294; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_1 = _write_packets_mask_T_295; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_9 = write_packets_mask_9_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_296 = write_packets_vaddr_offset_1 < 5'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_298 = _write_packets_mask_T_297 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_299 = _write_packets_mask_T_296 & _write_packets_mask_T_298; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_1 = _write_packets_mask_T_299; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_10 = write_packets_mask_10_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_300 = write_packets_vaddr_offset_1 < 5'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_302 = _write_packets_mask_T_301 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_303 = _write_packets_mask_T_300 & _write_packets_mask_T_302; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_1 = _write_packets_mask_T_303; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_11 = write_packets_mask_11_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_304 = write_packets_vaddr_offset_1 < 5'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_306 = _write_packets_mask_T_305 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_307 = _write_packets_mask_T_304 & _write_packets_mask_T_306; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_1 = _write_packets_mask_T_307; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_12 = write_packets_mask_12_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_308 = write_packets_vaddr_offset_1 < 5'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_310 = _write_packets_mask_T_309 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_311 = _write_packets_mask_T_308 & _write_packets_mask_T_310; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_1 = _write_packets_mask_T_311; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_13 = write_packets_mask_13_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_312 = write_packets_vaddr_offset_1 < 5'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_314 = _write_packets_mask_T_313 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_315 = _write_packets_mask_T_312 & _write_packets_mask_T_314; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_1 = _write_packets_mask_T_315; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_14 = write_packets_mask_14_1; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_4 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_25 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_316 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_318 = \|(_write_packets_mask_T_317[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_319 = _write_packets_mask_T_316 & _write_packets_mask_T_318; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_1 = _write_packets_mask_T_319; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_15 = write_packets_mask_15_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_320 = write_packets_vaddr_offset_1 < 5'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_322 = _write_packets_mask_T_321 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_323 = _write_packets_mask_T_320 & _write_packets_mask_T_322; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_1 = _write_packets_mask_T_323; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_0 = write_packets_mask_16_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_324 = write_packets_vaddr_offset_1 < 5'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_326 = _write_packets_mask_T_325 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_327 = _write_packets_mask_T_324 & _write_packets_mask_T_326; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_1 = _write_packets_mask_T_327; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_1 = write_packets_mask_17_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_328 = write_packets_vaddr_offset_1 < 5'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_330 = _write_packets_mask_T_329 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_331 = _write_packets_mask_T_328 & _write_packets_mask_T_330; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_1 = _write_packets_mask_T_331; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_2 = write_packets_mask_18_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_332 = write_packets_vaddr_offset_1 < 5'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_334 = _write_packets_mask_T_333 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_335 = _write_packets_mask_T_332 & _write_packets_mask_T_334; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_1 = _write_packets_mask_T_335; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_3 = write_packets_mask_19_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_336 = write_packets_vaddr_offset_1 < 5'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_338 = _write_packets_mask_T_337 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_339 = _write_packets_mask_T_336 & _write_packets_mask_T_338; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_1 = _write_packets_mask_T_339; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_4 = write_packets_mask_20_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_340 = write_packets_vaddr_offset_1 < 5'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_342 = _write_packets_mask_T_341 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_343 = _write_packets_mask_T_340 & _write_packets_mask_T_342; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_1 = _write_packets_mask_T_343; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_5 = write_packets_mask_21_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_344 = write_packets_vaddr_offset_1 < 5'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_346 = _write_packets_mask_T_345 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_347 = _write_packets_mask_T_344 & _write_packets_mask_T_346; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_1 = _write_packets_mask_T_347; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_6 = write_packets_mask_22_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_348 = write_packets_vaddr_offset_1[4:3] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_350 = _write_packets_mask_T_349 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_351 = _write_packets_mask_T_348 & _write_packets_mask_T_350; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_1 = _write_packets_mask_T_351; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_7 = write_packets_mask_23_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_352 = write_packets_vaddr_offset_1 < 5'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_354 = _write_packets_mask_T_353 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_355 = _write_packets_mask_T_352 & _write_packets_mask_T_354; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_1 = _write_packets_mask_T_355; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_8 = write_packets_mask_24_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_356 = write_packets_vaddr_offset_1 < 5'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_358 = _write_packets_mask_T_357 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_359 = _write_packets_mask_T_356 & _write_packets_mask_T_358; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_1 = _write_packets_mask_T_359; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_9 = write_packets_mask_25_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_360 = write_packets_vaddr_offset_1 < 5'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_362 = _write_packets_mask_T_361 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_363 = _write_packets_mask_T_360 & _write_packets_mask_T_362; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_1 = _write_packets_mask_T_363; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_10 = write_packets_mask_26_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_364 = write_packets_vaddr_offset_1[4:2] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_366 = _write_packets_mask_T_365 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_367 = _write_packets_mask_T_364 & _write_packets_mask_T_366; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_1 = _write_packets_mask_T_367; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_11 = write_packets_mask_27_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_368 = write_packets_vaddr_offset_1 < 5'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_370 = _write_packets_mask_T_369 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_371 = _write_packets_mask_T_368 & _write_packets_mask_T_370; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_1 = _write_packets_mask_T_371; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_12 = write_packets_mask_28_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_372 = write_packets_vaddr_offset_1[4:1] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_374 = _write_packets_mask_T_373 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_375 = _write_packets_mask_T_372 & _write_packets_mask_T_374; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_1 = _write_packets_mask_T_375; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_13 = write_packets_mask_29_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_376 = write_packets_vaddr_offset_1 != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_378 = _write_packets_mask_T_377 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_379 = _write_packets_mask_T_376 & _write_packets_mask_T_378; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_1 = _write_packets_mask_T_379; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_14 = write_packets_mask_30_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_382 = \|(_write_packets_mask_T_381[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_383 = _write_packets_mask_T_382; // @[DMA.scala:431:{68,75}] wire write_packets_mask_31_1 = _write_packets_mask_T_383; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_15 = write_packets_mask_31_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_386 = _write_packets_mask_T_385 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_387 = _write_packets_mask_T_386; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_390 = _write_packets_mask_T_389 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_391 = _write_packets_mask_T_390; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_394 = _write_packets_mask_T_393 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_395 = _write_packets_mask_T_394; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_398 = _write_packets_mask_T_397 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_399 = _write_packets_mask_T_398; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_402 = _write_packets_mask_T_401 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_403 = _write_packets_mask_T_402; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_406 = _write_packets_mask_T_405 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_407 = _write_packets_mask_T_406; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_410 = _write_packets_mask_T_409 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_411 = _write_packets_mask_T_410; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_414 = _write_packets_mask_T_413 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_415 = _write_packets_mask_T_414; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_418 = _write_packets_mask_T_417 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_419 = _write_packets_mask_T_418; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_422 = _write_packets_mask_T_421 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_423 = _write_packets_mask_T_422; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_426 = _write_packets_mask_T_425 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_427 = _write_packets_mask_T_426; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_430 = _write_packets_mask_T_429 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_431 = _write_packets_mask_T_430; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_434 = _write_packets_mask_T_433 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_435 = _write_packets_mask_T_434; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_438 = _write_packets_mask_T_437 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_439 = _write_packets_mask_T_438; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_442 = _write_packets_mask_T_441 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_443 = _write_packets_mask_T_442; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_446 = _write_packets_mask_T_445 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_447 = _write_packets_mask_T_446; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_450 = _write_packets_mask_T_449 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_451 = _write_packets_mask_T_450; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_454 = _write_packets_mask_T_453 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_455 = _write_packets_mask_T_454; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_458 = _write_packets_mask_T_457 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_459 = _write_packets_mask_T_458; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_462 = _write_packets_mask_T_461 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_463 = _write_packets_mask_T_462; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_466 = _write_packets_mask_T_465 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_467 = _write_packets_mask_T_466; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_470 = _write_packets_mask_T_469 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_471 = _write_packets_mask_T_470; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_474 = _write_packets_mask_T_473 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_475 = _write_packets_mask_T_474; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_478 = _write_packets_mask_T_477 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_479 = _write_packets_mask_T_478; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_482 = _write_packets_mask_T_481 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_483 = _write_packets_mask_T_482; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_486 = _write_packets_mask_T_485 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_487 = _write_packets_mask_T_486; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_490 = _write_packets_mask_T_489 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_491 = _write_packets_mask_T_490; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_494 = _write_packets_mask_T_493 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_495 = _write_packets_mask_T_494; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_498 = _write_packets_mask_T_497 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_499 = _write_packets_mask_T_498; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_502 = _write_packets_mask_T_501 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_503 = _write_packets_mask_T_502; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_506 = _write_packets_mask_T_505 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_507 = _write_packets_mask_T_506; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_510 = \|(_write_packets_mask_T_509[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_511 = _write_packets_mask_T_510; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_5 = _write_packets_bytes_written_T_4 > 8'h20; // @[DMA.scala:434:{26,39}] wire [6:0] _GEN_5 = {2'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :434:50] wire [6:0] _write_packets_bytes_written_T_6 = 7'h20 - _GEN_5; // @[DMA.scala:434:50] wire [5:0] _write_packets_bytes_written_T_7 = _write_packets_bytes_written_T_6[5:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_1 = _write_packets_bytes_written_T_5 ? {1'h0, _write_packets_bytes_written_T_7} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_1_bytes_written = write_packets_bytes_written_1; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_9_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_45; // @[DMA.scala:442:47] wire write_packets_1_mask_0_0; // @[DMA.scala:437:24] wire write_packets_1_mask_0_1; // @[DMA.scala:437:24] wire write_packets_1_mask_0_2; // @[DMA.scala:437:24] wire write_packets_1_mask_0_3; // @[DMA.scala:437:24] wire write_packets_1_mask_0_4; // @[DMA.scala:437:24] wire write_packets_1_mask_0_5; // @[DMA.scala:437:24] wire write_packets_1_mask_0_6; // @[DMA.scala:437:24] wire write_packets_1_mask_0_7; // @[DMA.scala:437:24] wire write_packets_1_mask_0_8; // @[DMA.scala:437:24] wire write_packets_1_mask_0_9; // @[DMA.scala:437:24] wire write_packets_1_mask_0_10; // @[DMA.scala:437:24] wire write_packets_1_mask_0_11; // @[DMA.scala:437:24] wire write_packets_1_mask_0_12; // @[DMA.scala:437:24] wire write_packets_1_mask_0_13; // @[DMA.scala:437:24] wire write_packets_1_mask_0_14; // @[DMA.scala:437:24] wire write_packets_1_mask_0_15; // @[DMA.scala:437:24] wire write_packets_1_mask_1_0; // @[DMA.scala:437:24] wire write_packets_1_mask_1_1; // @[DMA.scala:437:24] wire write_packets_1_mask_1_2; // @[DMA.scala:437:24] wire write_packets_1_mask_1_3; // @[DMA.scala:437:24] wire write_packets_1_mask_1_4; // @[DMA.scala:437:24] wire write_packets_1_mask_1_5; // @[DMA.scala:437:24] wire write_packets_1_mask_1_6; // @[DMA.scala:437:24] wire write_packets_1_mask_1_7; // @[DMA.scala:437:24] wire write_packets_1_mask_1_8; // @[DMA.scala:437:24] wire write_packets_1_mask_1_9; // @[DMA.scala:437:24] wire write_packets_1_mask_1_10; // @[DMA.scala:437:24] wire write_packets_1_mask_1_11; // @[DMA.scala:437:24] wire write_packets_1_mask_1_12; // @[DMA.scala:437:24] wire write_packets_1_mask_1_13; // @[DMA.scala:437:24] wire write_packets_1_mask_1_14; // @[DMA.scala:437:24] wire write_packets_1_mask_1_15; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_1_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_9_0_0 = _write_packets_WIRE_5_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_1 = _write_packets_WIRE_5_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_2 = _write_packets_WIRE_5_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_3 = _write_packets_WIRE_5_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_4 = _write_packets_WIRE_5_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_5 = _write_packets_WIRE_5_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_6 = _write_packets_WIRE_5_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_7 = _write_packets_WIRE_5_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_8 = _write_packets_WIRE_5_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_9 = _write_packets_WIRE_5_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_10 = _write_packets_WIRE_5_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_11 = _write_packets_WIRE_5_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_12 = _write_packets_WIRE_5_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_13 = _write_packets_WIRE_5_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_14 = _write_packets_WIRE_5_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_15 = _write_packets_WIRE_5_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_0 = _write_packets_WIRE_6_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_1 = _write_packets_WIRE_6_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_2 = _write_packets_WIRE_6_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_3 = _write_packets_WIRE_6_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_4 = _write_packets_WIRE_6_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_5 = _write_packets_WIRE_6_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_6 = _write_packets_WIRE_6_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_7 = _write_packets_WIRE_6_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_8 = _write_packets_WIRE_6_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_9 = _write_packets_WIRE_6_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_10 = _write_packets_WIRE_6_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_11 = _write_packets_WIRE_6_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_12 = _write_packets_WIRE_6_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_13 = _write_packets_WIRE_6_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_14 = _write_packets_WIRE_6_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_15 = _write_packets_WIRE_6_15; // @[DMA.scala:440:{29,70}] assign write_packets_1_mask_0_0 = _write_packets_WIRE_9_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_1 = _write_packets_WIRE_9_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_2 = _write_packets_WIRE_9_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_3 = _write_packets_WIRE_9_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_4 = _write_packets_WIRE_9_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_5 = _write_packets_WIRE_9_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_6 = _write_packets_WIRE_9_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_7 = _write_packets_WIRE_9_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_8 = _write_packets_WIRE_9_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_9 = _write_packets_WIRE_9_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_10 = _write_packets_WIRE_9_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_11 = _write_packets_WIRE_9_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_12 = _write_packets_WIRE_9_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_13 = _write_packets_WIRE_9_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_14 = _write_packets_WIRE_9_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_15 = _write_packets_WIRE_9_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_0 = _write_packets_WIRE_9_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_1 = _write_packets_WIRE_9_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_2 = _write_packets_WIRE_9_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_3 = _write_packets_WIRE_9_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_4 = _write_packets_WIRE_9_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_5 = _write_packets_WIRE_9_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_6 = _write_packets_WIRE_9_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_7 = _write_packets_WIRE_9_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_8 = _write_packets_WIRE_9_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_9 = _write_packets_WIRE_9_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_10 = _write_packets_WIRE_9_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_11 = _write_packets_WIRE_9_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_12 = _write_packets_WIRE_9_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_13 = _write_packets_WIRE_9_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_14 = _write_packets_WIRE_9_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_15 = _write_packets_WIRE_9_1_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_15 = write_packets_mask_0_1 & write_packets_mask_1_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_16 = _write_packets_packet_is_full_T_15 & write_packets_mask_2_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_17 = _write_packets_packet_is_full_T_16 & write_packets_mask_3_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_18 = _write_packets_packet_is_full_T_17 & write_packets_mask_4_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_19 = _write_packets_packet_is_full_T_18 & write_packets_mask_5_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_20 = _write_packets_packet_is_full_T_19 & write_packets_mask_6_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_21 = _write_packets_packet_is_full_T_20 & write_packets_mask_7_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_22 = _write_packets_packet_is_full_T_21 & write_packets_mask_8_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_23 = _write_packets_packet_is_full_T_22 & write_packets_mask_9_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_24 = _write_packets_packet_is_full_T_23 & write_packets_mask_10_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_25 = _write_packets_packet_is_full_T_24 & write_packets_mask_11_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_26 = _write_packets_packet_is_full_T_25 & write_packets_mask_12_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_27 = _write_packets_packet_is_full_T_26 & write_packets_mask_13_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_28 = _write_packets_packet_is_full_T_27 & write_packets_mask_14_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_29 = _write_packets_packet_is_full_T_28 & write_packets_mask_15_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_30 = _write_packets_packet_is_full_T_29 & write_packets_mask_16_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_31 = _write_packets_packet_is_full_T_30 & write_packets_mask_17_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_32 = _write_packets_packet_is_full_T_31 & write_packets_mask_18_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_33 = _write_packets_packet_is_full_T_32 & write_packets_mask_19_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_34 = _write_packets_packet_is_full_T_33 & write_packets_mask_20_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_35 = _write_packets_packet_is_full_T_34 & write_packets_mask_21_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_36 = _write_packets_packet_is_full_T_35 & write_packets_mask_22_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_37 = _write_packets_packet_is_full_T_36 & write_packets_mask_23_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_38 = _write_packets_packet_is_full_T_37 & write_packets_mask_24_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_39 = _write_packets_packet_is_full_T_38 & write_packets_mask_25_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_40 = _write_packets_packet_is_full_T_39 & write_packets_mask_26_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_41 = _write_packets_packet_is_full_T_40 & write_packets_mask_27_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_42 = _write_packets_packet_is_full_T_41 & write_packets_mask_28_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_43 = _write_packets_packet_is_full_T_42 & write_packets_mask_29_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_44 = _write_packets_packet_is_full_T_43 & write_packets_mask_30_1; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_45 = _write_packets_packet_is_full_T_44 & write_packets_mask_31_1; // @[DMA.scala:431:103, :442:47] assign write_packets_1_is_full = _write_packets_packet_is_full_T_45; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_21 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_22 = _write_packets_left_shift_T_21; // @[DMA.scala:449:{62,78}] wire [5:0] _write_packets_left_shift_T_23 = {1'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :450:24] wire [4:0] _write_packets_left_shift_T_24 = _write_packets_left_shift_T_23[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_4 = _write_packets_left_shift_T_22 ? _write_packets_left_shift_T_24 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_35 = _write_packets_right_shift_T_34 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_36 = _write_packets_right_shift_T_35; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_38 = 9'h10 - {1'h0, _write_packets_right_shift_T_37}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_39 = _write_packets_right_shift_T_38[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_4 = _write_packets_right_shift_T_36 ? _write_packets_right_shift_T_39 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_4 = _write_packets_too_late_T_4 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_5 = write_packets_too_early_4 \| write_packets_too_late_4; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_6 = {4'h0, write_packets_left_shift_4} + {1'h0, write_packets_right_shift_4}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_8 = _write_packets_packet_bytes_written_per_beat_0_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_9 = _write_packets_packet_bytes_written_per_beat_0_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_27 = _write_packets_left_shift_T_25; // @[DMA.scala:449:{43,62}] wire [5:0] _write_packets_left_shift_T_28 = _write_packets_left_shift_T_23 - 6'h10; // @[DMA.scala:450:24] wire [4:0] _write_packets_left_shift_T_29 = _write_packets_left_shift_T_28[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_5 = _write_packets_left_shift_T_27 ? _write_packets_left_shift_T_29 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_41 = \|(_write_packets_right_shift_T_40[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_43 = _write_packets_right_shift_T_42 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_44 = _write_packets_right_shift_T_41 & _write_packets_right_shift_T_43; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_46 = 9'h20 - {1'h0, _write_packets_right_shift_T_45}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_47 = _write_packets_right_shift_T_46[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_5 = _write_packets_right_shift_T_44 ? _write_packets_right_shift_T_47 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_5 = _write_packets_too_late_T_5 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_5 = write_packets_too_late_5; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_6 = {4'h0, write_packets_left_shift_5} + {1'h0, write_packets_right_shift_5}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_8 = _write_packets_packet_bytes_written_per_beat_1_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_9 = _write_packets_packet_bytes_written_per_beat_1_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_33 = _GEN_5 - 7'h20; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_34 = _write_packets_left_shift_T_33[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_49 = \|(_write_packets_right_shift_T_48[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_51 = _write_packets_right_shift_T_50 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_52 = _write_packets_right_shift_T_49 & _write_packets_right_shift_T_51; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_54 = 9'h30 - {1'h0, _write_packets_right_shift_T_53}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_55 = _write_packets_right_shift_T_54[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_6 = _write_packets_right_shift_T_52 ? _write_packets_right_shift_T_55 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_6 = _write_packets_too_late_T_6 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_5 = write_packets_too_late_6; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_6 = {1'h0, write_packets_right_shift_6}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_8 = _write_packets_packet_bytes_written_per_beat_2_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_9 = _write_packets_packet_bytes_written_per_beat_2_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_38 = _GEN_5 - 7'h30; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_39 = _write_packets_left_shift_T_38[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_57 = _write_packets_right_shift_T_56 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_59 = _write_packets_right_shift_T_58 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_60 = _write_packets_right_shift_T_57 & _write_packets_right_shift_T_59; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_62 = 9'h40 - {1'h0, _write_packets_right_shift_T_61}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_63 = _write_packets_right_shift_T_62[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_7 = _write_packets_right_shift_T_60 ? _write_packets_right_shift_T_63 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_7 = _write_packets_too_late_T_7 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_5 = write_packets_too_late_7; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_6 = {1'h0, write_packets_right_shift_7}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_8 = _write_packets_packet_bytes_written_per_beat_3_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_9 = _write_packets_packet_bytes_written_per_beat_3_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [32:0] _write_packets_vaddr_aligned_to_size_T_2 = req_vaddr[38:6]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_2 = {_write_packets_vaddr_aligned_to_size_T_2, 6'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_2_vaddr = write_packets_vaddr_aligned_to_size_2; // @[DMA.scala:428:61, :437:24] wire [5:0] write_packets_vaddr_offset_2 = req_vaddr[5:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_512 = write_packets_vaddr_offset_2 == 6'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_6 = {2'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :431:90] wire [7:0] _GEN_7 = _GEN_6 + _GEN_0; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_513; // @[DMA.scala:431:90] assign _write_packets_mask_T_513 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_517; // @[DMA.scala:431:90] assign _write_packets_mask_T_517 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_521; // @[DMA.scala:431:90] assign _write_packets_mask_T_521 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_525; // @[DMA.scala:431:90] assign _write_packets_mask_T_525 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_529; // @[DMA.scala:431:90] assign _write_packets_mask_T_529 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_533; // @[DMA.scala:431:90] assign _write_packets_mask_T_533 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_537; // @[DMA.scala:431:90] assign _write_packets_mask_T_537 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_541; // @[DMA.scala:431:90] assign _write_packets_mask_T_541 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_545; // @[DMA.scala:431:90] assign _write_packets_mask_T_545 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_549; // @[DMA.scala:431:90] assign _write_packets_mask_T_549 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_553; // @[DMA.scala:431:90] assign _write_packets_mask_T_553 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_557; // @[DMA.scala:431:90] assign _write_packets_mask_T_557 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_561; // @[DMA.scala:431:90] assign _write_packets_mask_T_561 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_565; // @[DMA.scala:431:90] assign _write_packets_mask_T_565 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_569; // @[DMA.scala:431:90] assign _write_packets_mask_T_569 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_573; // @[DMA.scala:431:90] assign _write_packets_mask_T_573 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_577; // @[DMA.scala:431:90] assign _write_packets_mask_T_577 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_581; // @[DMA.scala:431:90] assign _write_packets_mask_T_581 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_585; // @[DMA.scala:431:90] assign _write_packets_mask_T_585 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_589; // @[DMA.scala:431:90] assign _write_packets_mask_T_589 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_593; // @[DMA.scala:431:90] assign _write_packets_mask_T_593 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_597; // @[DMA.scala:431:90] assign _write_packets_mask_T_597 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_601; // @[DMA.scala:431:90] assign _write_packets_mask_T_601 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_605; // @[DMA.scala:431:90] assign _write_packets_mask_T_605 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_609; // @[DMA.scala:431:90] assign _write_packets_mask_T_609 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_613; // @[DMA.scala:431:90] assign _write_packets_mask_T_613 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_617; // @[DMA.scala:431:90] assign _write_packets_mask_T_617 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_621; // @[DMA.scala:431:90] assign _write_packets_mask_T_621 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_625; // @[DMA.scala:431:90] assign _write_packets_mask_T_625 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_629; // @[DMA.scala:431:90] assign _write_packets_mask_T_629 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_633; // @[DMA.scala:431:90] assign _write_packets_mask_T_633 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_637; // @[DMA.scala:431:90] assign _write_packets_mask_T_637 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_641; // @[DMA.scala:431:90] assign _write_packets_mask_T_641 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_645; // @[DMA.scala:431:90] assign _write_packets_mask_T_645 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_649; // @[DMA.scala:431:90] assign _write_packets_mask_T_649 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_653; // @[DMA.scala:431:90] assign _write_packets_mask_T_653 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_657; // @[DMA.scala:431:90] assign _write_packets_mask_T_657 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_661; // @[DMA.scala:431:90] assign _write_packets_mask_T_661 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_665; // @[DMA.scala:431:90] assign _write_packets_mask_T_665 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_669; // @[DMA.scala:431:90] assign _write_packets_mask_T_669 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_673; // @[DMA.scala:431:90] assign _write_packets_mask_T_673 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_677; // @[DMA.scala:431:90] assign _write_packets_mask_T_677 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_681; // @[DMA.scala:431:90] assign _write_packets_mask_T_681 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_685; // @[DMA.scala:431:90] assign _write_packets_mask_T_685 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_689; // @[DMA.scala:431:90] assign _write_packets_mask_T_689 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_693; // @[DMA.scala:431:90] assign _write_packets_mask_T_693 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_697; // @[DMA.scala:431:90] assign _write_packets_mask_T_697 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_701; // @[DMA.scala:431:90] assign _write_packets_mask_T_701 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_705; // @[DMA.scala:431:90] assign _write_packets_mask_T_705 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_709; // @[DMA.scala:431:90] assign _write_packets_mask_T_709 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_713; // @[DMA.scala:431:90] assign _write_packets_mask_T_713 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_717; // @[DMA.scala:431:90] assign _write_packets_mask_T_717 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_721; // @[DMA.scala:431:90] assign _write_packets_mask_T_721 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_725; // @[DMA.scala:431:90] assign _write_packets_mask_T_725 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_729; // @[DMA.scala:431:90] assign _write_packets_mask_T_729 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_733; // @[DMA.scala:431:90] assign _write_packets_mask_T_733 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_737; // @[DMA.scala:431:90] assign _write_packets_mask_T_737 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_741; // @[DMA.scala:431:90] assign _write_packets_mask_T_741 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_745; // @[DMA.scala:431:90] assign _write_packets_mask_T_745 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_749; // @[DMA.scala:431:90] assign _write_packets_mask_T_749 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_753; // @[DMA.scala:431:90] assign _write_packets_mask_T_753 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_757; // @[DMA.scala:431:90] assign _write_packets_mask_T_757 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_761; // @[DMA.scala:431:90] assign _write_packets_mask_T_761 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_765; // @[DMA.scala:431:90] assign _write_packets_mask_T_765 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_8; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_8 = _GEN_7; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_64; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_64 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_66; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_66 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_69; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_69 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_8; // @[DMA.scala:458:37] assign _write_packets_too_late_T_8 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_72; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_72 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_74; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_74 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_77; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_77 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_9; // @[DMA.scala:458:37] assign _write_packets_too_late_T_9 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_80; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_80 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_82; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_82 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_85; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_85 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_10; // @[DMA.scala:458:37] assign _write_packets_too_late_T_10 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_88; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_88 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_90; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_90 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_93; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_93 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_11; // @[DMA.scala:458:37] assign _write_packets_too_late_T_11 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_514 = \|_write_packets_mask_T_513; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_515 = _write_packets_mask_T_512 & _write_packets_mask_T_514; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_2 = _write_packets_mask_T_515; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_0 = write_packets_mask_0_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_516 = write_packets_vaddr_offset_2 < 6'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_518 = \|(_write_packets_mask_T_517[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_519 = _write_packets_mask_T_516 & _write_packets_mask_T_518; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_2 = _write_packets_mask_T_519; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_1 = write_packets_mask_1_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_520 = write_packets_vaddr_offset_2 < 6'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_522 = _write_packets_mask_T_521 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_523 = _write_packets_mask_T_520 & _write_packets_mask_T_522; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_2 = _write_packets_mask_T_523; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_2 = write_packets_mask_2_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_524 = write_packets_vaddr_offset_2 < 6'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_526 = \|(_write_packets_mask_T_525[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_527 = _write_packets_mask_T_524 & _write_packets_mask_T_526; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_2 = _write_packets_mask_T_527; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_3 = write_packets_mask_3_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_528 = write_packets_vaddr_offset_2 < 6'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_530 = _write_packets_mask_T_529 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_531 = _write_packets_mask_T_528 & _write_packets_mask_T_530; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_2 = _write_packets_mask_T_531; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_4 = write_packets_mask_4_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_532 = write_packets_vaddr_offset_2 < 6'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_534 = _write_packets_mask_T_533 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_535 = _write_packets_mask_T_532 & _write_packets_mask_T_534; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_2 = _write_packets_mask_T_535; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_5 = write_packets_mask_5_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_536 = write_packets_vaddr_offset_2 < 6'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_538 = _write_packets_mask_T_537 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_539 = _write_packets_mask_T_536 & _write_packets_mask_T_538; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_2 = _write_packets_mask_T_539; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_6 = write_packets_mask_6_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_540 = write_packets_vaddr_offset_2 < 6'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_542 = \|(_write_packets_mask_T_541[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_543 = _write_packets_mask_T_540 & _write_packets_mask_T_542; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_2 = _write_packets_mask_T_543; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_7 = write_packets_mask_7_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_544 = write_packets_vaddr_offset_2 < 6'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_546 = _write_packets_mask_T_545 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_547 = _write_packets_mask_T_544 & _write_packets_mask_T_546; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_2 = _write_packets_mask_T_547; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_8 = write_packets_mask_8_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_548 = write_packets_vaddr_offset_2 < 6'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_550 = _write_packets_mask_T_549 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_551 = _write_packets_mask_T_548 & _write_packets_mask_T_550; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_2 = _write_packets_mask_T_551; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_9 = write_packets_mask_9_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_552 = write_packets_vaddr_offset_2 < 6'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_554 = _write_packets_mask_T_553 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_555 = _write_packets_mask_T_552 & _write_packets_mask_T_554; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_2 = _write_packets_mask_T_555; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_10 = write_packets_mask_10_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_556 = write_packets_vaddr_offset_2 < 6'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_558 = _write_packets_mask_T_557 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_559 = _write_packets_mask_T_556 & _write_packets_mask_T_558; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_2 = _write_packets_mask_T_559; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_11 = write_packets_mask_11_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_560 = write_packets_vaddr_offset_2 < 6'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_562 = _write_packets_mask_T_561 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_563 = _write_packets_mask_T_560 & _write_packets_mask_T_562; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_2 = _write_packets_mask_T_563; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_12 = write_packets_mask_12_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_564 = write_packets_vaddr_offset_2 < 6'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_566 = _write_packets_mask_T_565 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_567 = _write_packets_mask_T_564 & _write_packets_mask_T_566; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_2 = _write_packets_mask_T_567; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_13 = write_packets_mask_13_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_568 = write_packets_vaddr_offset_2 < 6'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_570 = _write_packets_mask_T_569 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_571 = _write_packets_mask_T_568 & _write_packets_mask_T_570; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_2 = _write_packets_mask_T_571; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_14 = write_packets_mask_14_2; // @[DMA.scala:431:103, :440:70] wire _GEN_8 = write_packets_vaddr_offset_2 < 6'h10; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_572; // @[DMA.scala:431:52] assign _write_packets_mask_T_572 = _GEN_8; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_41; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_41 = _GEN_8; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_574 = \|(_write_packets_mask_T_573[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_575 = _write_packets_mask_T_572 & _write_packets_mask_T_574; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_2 = _write_packets_mask_T_575; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_15 = write_packets_mask_15_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_576 = write_packets_vaddr_offset_2 < 6'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_578 = _write_packets_mask_T_577 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_579 = _write_packets_mask_T_576 & _write_packets_mask_T_578; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_2 = _write_packets_mask_T_579; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_0 = write_packets_mask_16_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_580 = write_packets_vaddr_offset_2 < 6'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_582 = _write_packets_mask_T_581 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_583 = _write_packets_mask_T_580 & _write_packets_mask_T_582; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_2 = _write_packets_mask_T_583; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_1 = write_packets_mask_17_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_584 = write_packets_vaddr_offset_2 < 6'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_586 = _write_packets_mask_T_585 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_587 = _write_packets_mask_T_584 & _write_packets_mask_T_586; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_2 = _write_packets_mask_T_587; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_2 = write_packets_mask_18_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_588 = write_packets_vaddr_offset_2 < 6'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_590 = _write_packets_mask_T_589 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_591 = _write_packets_mask_T_588 & _write_packets_mask_T_590; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_2 = _write_packets_mask_T_591; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_3 = write_packets_mask_19_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_592 = write_packets_vaddr_offset_2 < 6'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_594 = _write_packets_mask_T_593 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_595 = _write_packets_mask_T_592 & _write_packets_mask_T_594; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_2 = _write_packets_mask_T_595; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_4 = write_packets_mask_20_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_596 = write_packets_vaddr_offset_2 < 6'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_598 = _write_packets_mask_T_597 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_599 = _write_packets_mask_T_596 & _write_packets_mask_T_598; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_2 = _write_packets_mask_T_599; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_5 = write_packets_mask_21_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_600 = write_packets_vaddr_offset_2 < 6'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_602 = _write_packets_mask_T_601 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_603 = _write_packets_mask_T_600 & _write_packets_mask_T_602; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_2 = _write_packets_mask_T_603; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_6 = write_packets_mask_22_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_604 = write_packets_vaddr_offset_2 < 6'h18; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_606 = _write_packets_mask_T_605 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_607 = _write_packets_mask_T_604 & _write_packets_mask_T_606; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_2 = _write_packets_mask_T_607; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_7 = write_packets_mask_23_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_608 = write_packets_vaddr_offset_2 < 6'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_610 = _write_packets_mask_T_609 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_611 = _write_packets_mask_T_608 & _write_packets_mask_T_610; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_2 = _write_packets_mask_T_611; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_8 = write_packets_mask_24_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_612 = write_packets_vaddr_offset_2 < 6'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_614 = _write_packets_mask_T_613 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_615 = _write_packets_mask_T_612 & _write_packets_mask_T_614; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_2 = _write_packets_mask_T_615; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_9 = write_packets_mask_25_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_616 = write_packets_vaddr_offset_2 < 6'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_618 = _write_packets_mask_T_617 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_619 = _write_packets_mask_T_616 & _write_packets_mask_T_618; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_2 = _write_packets_mask_T_619; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_10 = write_packets_mask_26_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_620 = write_packets_vaddr_offset_2 < 6'h1C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_622 = _write_packets_mask_T_621 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_623 = _write_packets_mask_T_620 & _write_packets_mask_T_622; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_2 = _write_packets_mask_T_623; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_11 = write_packets_mask_27_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_624 = write_packets_vaddr_offset_2 < 6'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_626 = _write_packets_mask_T_625 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_627 = _write_packets_mask_T_624 & _write_packets_mask_T_626; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_2 = _write_packets_mask_T_627; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_12 = write_packets_mask_28_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_628 = write_packets_vaddr_offset_2 < 6'h1E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_630 = _write_packets_mask_T_629 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_631 = _write_packets_mask_T_628 & _write_packets_mask_T_630; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_2 = _write_packets_mask_T_631; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_13 = write_packets_mask_29_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_632 = write_packets_vaddr_offset_2 < 6'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_634 = _write_packets_mask_T_633 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_635 = _write_packets_mask_T_632 & _write_packets_mask_T_634; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_2 = _write_packets_mask_T_635; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_14 = write_packets_mask_30_2; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_9 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_50 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_636 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_638 = \|(_write_packets_mask_T_637[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_639 = _write_packets_mask_T_636 & _write_packets_mask_T_638; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_31_2 = _write_packets_mask_T_639; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_15 = write_packets_mask_31_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_640 = write_packets_vaddr_offset_2 < 6'h21; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_642 = _write_packets_mask_T_641 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_643 = _write_packets_mask_T_640 & _write_packets_mask_T_642; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_32_2 = _write_packets_mask_T_643; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_0 = write_packets_mask_32_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_644 = write_packets_vaddr_offset_2 < 6'h22; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_646 = _write_packets_mask_T_645 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_647 = _write_packets_mask_T_644 & _write_packets_mask_T_646; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_33_2 = _write_packets_mask_T_647; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_1 = write_packets_mask_33_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_648 = write_packets_vaddr_offset_2 < 6'h23; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_650 = _write_packets_mask_T_649 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_651 = _write_packets_mask_T_648 & _write_packets_mask_T_650; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_34_2 = _write_packets_mask_T_651; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_2 = write_packets_mask_34_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_652 = write_packets_vaddr_offset_2 < 6'h24; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_654 = _write_packets_mask_T_653 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_655 = _write_packets_mask_T_652 & _write_packets_mask_T_654; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_35_2 = _write_packets_mask_T_655; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_3 = write_packets_mask_35_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_656 = write_packets_vaddr_offset_2 < 6'h25; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_658 = _write_packets_mask_T_657 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_659 = _write_packets_mask_T_656 & _write_packets_mask_T_658; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_36_2 = _write_packets_mask_T_659; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_4 = write_packets_mask_36_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_660 = write_packets_vaddr_offset_2 < 6'h26; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_662 = _write_packets_mask_T_661 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_663 = _write_packets_mask_T_660 & _write_packets_mask_T_662; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_37_2 = _write_packets_mask_T_663; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_5 = write_packets_mask_37_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_664 = write_packets_vaddr_offset_2 < 6'h27; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_666 = _write_packets_mask_T_665 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_667 = _write_packets_mask_T_664 & _write_packets_mask_T_666; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_38_2 = _write_packets_mask_T_667; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_6 = write_packets_mask_38_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_668 = write_packets_vaddr_offset_2 < 6'h28; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_670 = _write_packets_mask_T_669 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_671 = _write_packets_mask_T_668 & _write_packets_mask_T_670; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_39_2 = _write_packets_mask_T_671; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_7 = write_packets_mask_39_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_672 = write_packets_vaddr_offset_2 < 6'h29; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_674 = _write_packets_mask_T_673 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_675 = _write_packets_mask_T_672 & _write_packets_mask_T_674; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_40_2 = _write_packets_mask_T_675; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_8 = write_packets_mask_40_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_676 = write_packets_vaddr_offset_2 < 6'h2A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_678 = _write_packets_mask_T_677 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_679 = _write_packets_mask_T_676 & _write_packets_mask_T_678; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_41_2 = _write_packets_mask_T_679; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_9 = write_packets_mask_41_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_680 = write_packets_vaddr_offset_2 < 6'h2B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_682 = _write_packets_mask_T_681 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_683 = _write_packets_mask_T_680 & _write_packets_mask_T_682; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_42_2 = _write_packets_mask_T_683; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_10 = write_packets_mask_42_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_684 = write_packets_vaddr_offset_2 < 6'h2C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_686 = _write_packets_mask_T_685 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_687 = _write_packets_mask_T_684 & _write_packets_mask_T_686; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_43_2 = _write_packets_mask_T_687; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_11 = write_packets_mask_43_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_688 = write_packets_vaddr_offset_2 < 6'h2D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_690 = _write_packets_mask_T_689 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_691 = _write_packets_mask_T_688 & _write_packets_mask_T_690; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_44_2 = _write_packets_mask_T_691; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_12 = write_packets_mask_44_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_692 = write_packets_vaddr_offset_2 < 6'h2E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_694 = _write_packets_mask_T_693 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_695 = _write_packets_mask_T_692 & _write_packets_mask_T_694; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_45_2 = _write_packets_mask_T_695; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_13 = write_packets_mask_45_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_696 = write_packets_vaddr_offset_2 < 6'h2F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_698 = _write_packets_mask_T_697 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_699 = _write_packets_mask_T_696 & _write_packets_mask_T_698; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_46_2 = _write_packets_mask_T_699; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_14 = write_packets_mask_46_2; // @[DMA.scala:431:103, :440:70] wire _GEN_9 = write_packets_vaddr_offset_2[5:4] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_700; // @[DMA.scala:431:52] assign _write_packets_mask_T_700 = _GEN_9; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_51; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_51 = _GEN_9; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_702 = _write_packets_mask_T_701 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_703 = _write_packets_mask_T_700 & _write_packets_mask_T_702; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_47_2 = _write_packets_mask_T_703; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_15 = write_packets_mask_47_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_704 = write_packets_vaddr_offset_2 < 6'h31; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_706 = _write_packets_mask_T_705 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_707 = _write_packets_mask_T_704 & _write_packets_mask_T_706; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_48_2 = _write_packets_mask_T_707; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_0 = write_packets_mask_48_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_708 = write_packets_vaddr_offset_2 < 6'h32; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_710 = _write_packets_mask_T_709 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_711 = _write_packets_mask_T_708 & _write_packets_mask_T_710; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_49_2 = _write_packets_mask_T_711; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_1 = write_packets_mask_49_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_712 = write_packets_vaddr_offset_2 < 6'h33; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_714 = _write_packets_mask_T_713 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_715 = _write_packets_mask_T_712 & _write_packets_mask_T_714; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_50_2 = _write_packets_mask_T_715; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_2 = write_packets_mask_50_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_716 = write_packets_vaddr_offset_2 < 6'h34; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_718 = _write_packets_mask_T_717 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_719 = _write_packets_mask_T_716 & _write_packets_mask_T_718; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_51_2 = _write_packets_mask_T_719; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_3 = write_packets_mask_51_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_720 = write_packets_vaddr_offset_2 < 6'h35; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_722 = _write_packets_mask_T_721 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_723 = _write_packets_mask_T_720 & _write_packets_mask_T_722; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_52_2 = _write_packets_mask_T_723; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_4 = write_packets_mask_52_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_724 = write_packets_vaddr_offset_2 < 6'h36; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_726 = _write_packets_mask_T_725 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_727 = _write_packets_mask_T_724 & _write_packets_mask_T_726; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_53_2 = _write_packets_mask_T_727; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_5 = write_packets_mask_53_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_728 = write_packets_vaddr_offset_2 < 6'h37; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_730 = _write_packets_mask_T_729 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_731 = _write_packets_mask_T_728 & _write_packets_mask_T_730; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_54_2 = _write_packets_mask_T_731; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_6 = write_packets_mask_54_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_732 = write_packets_vaddr_offset_2[5:3] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_734 = _write_packets_mask_T_733 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_735 = _write_packets_mask_T_732 & _write_packets_mask_T_734; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_55_2 = _write_packets_mask_T_735; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_7 = write_packets_mask_55_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_736 = write_packets_vaddr_offset_2 < 6'h39; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_738 = _write_packets_mask_T_737 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_739 = _write_packets_mask_T_736 & _write_packets_mask_T_738; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_56_2 = _write_packets_mask_T_739; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_8 = write_packets_mask_56_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_740 = write_packets_vaddr_offset_2 < 6'h3A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_742 = _write_packets_mask_T_741 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_743 = _write_packets_mask_T_740 & _write_packets_mask_T_742; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_57_2 = _write_packets_mask_T_743; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_9 = write_packets_mask_57_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_744 = write_packets_vaddr_offset_2 < 6'h3B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_746 = _write_packets_mask_T_745 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_747 = _write_packets_mask_T_744 & _write_packets_mask_T_746; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_58_2 = _write_packets_mask_T_747; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_10 = write_packets_mask_58_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_748 = write_packets_vaddr_offset_2[5:2] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_750 = _write_packets_mask_T_749 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_751 = _write_packets_mask_T_748 & _write_packets_mask_T_750; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_59_2 = _write_packets_mask_T_751; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_11 = write_packets_mask_59_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_752 = write_packets_vaddr_offset_2 < 6'h3D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_754 = _write_packets_mask_T_753 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_755 = _write_packets_mask_T_752 & _write_packets_mask_T_754; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_60_2 = _write_packets_mask_T_755; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_12 = write_packets_mask_60_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_756 = write_packets_vaddr_offset_2[5:1] != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_758 = _write_packets_mask_T_757 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_759 = _write_packets_mask_T_756 & _write_packets_mask_T_758; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_61_2 = _write_packets_mask_T_759; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_13 = write_packets_mask_61_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_760 = write_packets_vaddr_offset_2 != 6'h3F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_762 = _write_packets_mask_T_761 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_763 = _write_packets_mask_T_760 & _write_packets_mask_T_762; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_62_2 = _write_packets_mask_T_763; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_14 = write_packets_mask_62_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_766 = \|(_write_packets_mask_T_765[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_767 = _write_packets_mask_T_766; // @[DMA.scala:431:{68,75}] wire write_packets_mask_63_2 = _write_packets_mask_T_767; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_15 = write_packets_mask_63_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_bytes_written_T_9 = _write_packets_bytes_written_T_8 > 8'h40; // @[DMA.scala:434:{26,39}] wire [7:0] _write_packets_bytes_written_T_10 = 8'h40 - _GEN_6; // @[DMA.scala:431:90, :434:50] wire [6:0] _write_packets_bytes_written_T_11 = _write_packets_bytes_written_T_10[6:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_2 = _write_packets_bytes_written_T_9 ? _write_packets_bytes_written_T_11 : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_2_bytes_written = write_packets_bytes_written_2; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_14_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_108; // @[DMA.scala:442:47] wire write_packets_2_mask_0_0; // @[DMA.scala:437:24] wire write_packets_2_mask_0_1; // @[DMA.scala:437:24] wire write_packets_2_mask_0_2; // @[DMA.scala:437:24] wire write_packets_2_mask_0_3; // @[DMA.scala:437:24] wire write_packets_2_mask_0_4; // @[DMA.scala:437:24] wire write_packets_2_mask_0_5; // @[DMA.scala:437:24] wire write_packets_2_mask_0_6; // @[DMA.scala:437:24] wire write_packets_2_mask_0_7; // @[DMA.scala:437:24] wire write_packets_2_mask_0_8; // @[DMA.scala:437:24] wire write_packets_2_mask_0_9; // @[DMA.scala:437:24] wire write_packets_2_mask_0_10; // @[DMA.scala:437:24] wire write_packets_2_mask_0_11; // @[DMA.scala:437:24] wire write_packets_2_mask_0_12; // @[DMA.scala:437:24] wire write_packets_2_mask_0_13; // @[DMA.scala:437:24] wire write_packets_2_mask_0_14; // @[DMA.scala:437:24] wire write_packets_2_mask_0_15; // @[DMA.scala:437:24] wire write_packets_2_mask_1_0; // @[DMA.scala:437:24] wire write_packets_2_mask_1_1; // @[DMA.scala:437:24] wire write_packets_2_mask_1_2; // @[DMA.scala:437:24] wire write_packets_2_mask_1_3; // @[DMA.scala:437:24] wire write_packets_2_mask_1_4; // @[DMA.scala:437:24] wire write_packets_2_mask_1_5; // @[DMA.scala:437:24] wire write_packets_2_mask_1_6; // @[DMA.scala:437:24] wire write_packets_2_mask_1_7; // @[DMA.scala:437:24] wire write_packets_2_mask_1_8; // @[DMA.scala:437:24] wire write_packets_2_mask_1_9; // @[DMA.scala:437:24] wire write_packets_2_mask_1_10; // @[DMA.scala:437:24] wire write_packets_2_mask_1_11; // @[DMA.scala:437:24] wire write_packets_2_mask_1_12; // @[DMA.scala:437:24] wire write_packets_2_mask_1_13; // @[DMA.scala:437:24] wire write_packets_2_mask_1_14; // @[DMA.scala:437:24] wire write_packets_2_mask_1_15; // @[DMA.scala:437:24] wire write_packets_2_mask_2_0; // @[DMA.scala:437:24] wire write_packets_2_mask_2_1; // @[DMA.scala:437:24] wire write_packets_2_mask_2_2; // @[DMA.scala:437:24] wire write_packets_2_mask_2_3; // @[DMA.scala:437:24] wire write_packets_2_mask_2_4; // @[DMA.scala:437:24] wire write_packets_2_mask_2_5; // @[DMA.scala:437:24] wire write_packets_2_mask_2_6; // @[DMA.scala:437:24] wire write_packets_2_mask_2_7; // @[DMA.scala:437:24] wire write_packets_2_mask_2_8; // @[DMA.scala:437:24] wire write_packets_2_mask_2_9; // @[DMA.scala:437:24] wire write_packets_2_mask_2_10; // @[DMA.scala:437:24] wire write_packets_2_mask_2_11; // @[DMA.scala:437:24] wire write_packets_2_mask_2_12; // @[DMA.scala:437:24] wire write_packets_2_mask_2_13; // @[DMA.scala:437:24] wire write_packets_2_mask_2_14; // @[DMA.scala:437:24] wire write_packets_2_mask_2_15; // @[DMA.scala:437:24] wire write_packets_2_mask_3_0; // @[DMA.scala:437:24] wire write_packets_2_mask_3_1; // @[DMA.scala:437:24] wire write_packets_2_mask_3_2; // @[DMA.scala:437:24] wire write_packets_2_mask_3_3; // @[DMA.scala:437:24] wire write_packets_2_mask_3_4; // @[DMA.scala:437:24] wire write_packets_2_mask_3_5; // @[DMA.scala:437:24] wire write_packets_2_mask_3_6; // @[DMA.scala:437:24] wire write_packets_2_mask_3_7; // @[DMA.scala:437:24] wire write_packets_2_mask_3_8; // @[DMA.scala:437:24] wire write_packets_2_mask_3_9; // @[DMA.scala:437:24] wire write_packets_2_mask_3_10; // @[DMA.scala:437:24] wire write_packets_2_mask_3_11; // @[DMA.scala:437:24] wire write_packets_2_mask_3_12; // @[DMA.scala:437:24] wire write_packets_2_mask_3_13; // @[DMA.scala:437:24] wire write_packets_2_mask_3_14; // @[DMA.scala:437:24] wire write_packets_2_mask_3_15; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_2_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_14_0_0 = _write_packets_WIRE_10_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_1 = _write_packets_WIRE_10_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_2 = _write_packets_WIRE_10_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_3 = _write_packets_WIRE_10_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_4 = _write_packets_WIRE_10_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_5 = _write_packets_WIRE_10_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_6 = _write_packets_WIRE_10_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_7 = _write_packets_WIRE_10_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_8 = _write_packets_WIRE_10_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_9 = _write_packets_WIRE_10_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_10 = _write_packets_WIRE_10_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_11 = _write_packets_WIRE_10_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_12 = _write_packets_WIRE_10_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_13 = _write_packets_WIRE_10_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_14 = _write_packets_WIRE_10_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_15 = _write_packets_WIRE_10_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_0 = _write_packets_WIRE_11_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_1 = _write_packets_WIRE_11_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_2 = _write_packets_WIRE_11_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_3 = _write_packets_WIRE_11_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_4 = _write_packets_WIRE_11_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_5 = _write_packets_WIRE_11_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_6 = _write_packets_WIRE_11_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_7 = _write_packets_WIRE_11_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_8 = _write_packets_WIRE_11_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_9 = _write_packets_WIRE_11_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_10 = _write_packets_WIRE_11_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_11 = _write_packets_WIRE_11_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_12 = _write_packets_WIRE_11_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_13 = _write_packets_WIRE_11_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_14 = _write_packets_WIRE_11_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_15 = _write_packets_WIRE_11_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_0 = _write_packets_WIRE_12_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_1 = _write_packets_WIRE_12_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_2 = _write_packets_WIRE_12_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_3 = _write_packets_WIRE_12_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_4 = _write_packets_WIRE_12_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_5 = _write_packets_WIRE_12_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_6 = _write_packets_WIRE_12_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_7 = _write_packets_WIRE_12_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_8 = _write_packets_WIRE_12_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_9 = _write_packets_WIRE_12_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_10 = _write_packets_WIRE_12_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_11 = _write_packets_WIRE_12_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_12 = _write_packets_WIRE_12_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_13 = _write_packets_WIRE_12_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_14 = _write_packets_WIRE_12_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_15 = _write_packets_WIRE_12_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_0 = _write_packets_WIRE_13_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_1 = _write_packets_WIRE_13_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_2 = _write_packets_WIRE_13_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_3 = _write_packets_WIRE_13_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_4 = _write_packets_WIRE_13_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_5 = _write_packets_WIRE_13_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_6 = _write_packets_WIRE_13_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_7 = _write_packets_WIRE_13_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_8 = _write_packets_WIRE_13_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_9 = _write_packets_WIRE_13_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_10 = _write_packets_WIRE_13_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_11 = _write_packets_WIRE_13_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_12 = _write_packets_WIRE_13_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_13 = _write_packets_WIRE_13_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_14 = _write_packets_WIRE_13_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_15 = _write_packets_WIRE_13_15; // @[DMA.scala:440:{29,70}] assign write_packets_2_mask_0_0 = _write_packets_WIRE_14_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_1 = _write_packets_WIRE_14_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_2 = _write_packets_WIRE_14_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_3 = _write_packets_WIRE_14_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_4 = _write_packets_WIRE_14_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_5 = _write_packets_WIRE_14_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_6 = _write_packets_WIRE_14_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_7 = _write_packets_WIRE_14_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_8 = _write_packets_WIRE_14_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_9 = _write_packets_WIRE_14_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_10 = _write_packets_WIRE_14_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_11 = _write_packets_WIRE_14_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_12 = _write_packets_WIRE_14_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_13 = _write_packets_WIRE_14_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_14 = _write_packets_WIRE_14_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_15 = _write_packets_WIRE_14_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_0 = _write_packets_WIRE_14_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_1 = _write_packets_WIRE_14_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_2 = _write_packets_WIRE_14_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_3 = _write_packets_WIRE_14_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_4 = _write_packets_WIRE_14_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_5 = _write_packets_WIRE_14_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_6 = _write_packets_WIRE_14_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_7 = _write_packets_WIRE_14_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_8 = _write_packets_WIRE_14_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_9 = _write_packets_WIRE_14_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_10 = _write_packets_WIRE_14_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_11 = _write_packets_WIRE_14_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_12 = _write_packets_WIRE_14_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_13 = _write_packets_WIRE_14_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_14 = _write_packets_WIRE_14_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_15 = _write_packets_WIRE_14_1_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_0 = _write_packets_WIRE_14_2_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_1 = _write_packets_WIRE_14_2_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_2 = _write_packets_WIRE_14_2_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_3 = _write_packets_WIRE_14_2_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_4 = _write_packets_WIRE_14_2_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_5 = _write_packets_WIRE_14_2_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_6 = _write_packets_WIRE_14_2_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_7 = _write_packets_WIRE_14_2_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_8 = _write_packets_WIRE_14_2_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_9 = _write_packets_WIRE_14_2_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_10 = _write_packets_WIRE_14_2_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_11 = _write_packets_WIRE_14_2_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_12 = _write_packets_WIRE_14_2_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_13 = _write_packets_WIRE_14_2_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_14 = _write_packets_WIRE_14_2_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_15 = _write_packets_WIRE_14_2_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_0 = _write_packets_WIRE_14_3_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_1 = _write_packets_WIRE_14_3_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_2 = _write_packets_WIRE_14_3_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_3 = _write_packets_WIRE_14_3_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_4 = _write_packets_WIRE_14_3_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_5 = _write_packets_WIRE_14_3_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_6 = _write_packets_WIRE_14_3_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_7 = _write_packets_WIRE_14_3_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_8 = _write_packets_WIRE_14_3_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_9 = _write_packets_WIRE_14_3_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_10 = _write_packets_WIRE_14_3_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_11 = _write_packets_WIRE_14_3_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_12 = _write_packets_WIRE_14_3_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_13 = _write_packets_WIRE_14_3_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_14 = _write_packets_WIRE_14_3_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_15 = _write_packets_WIRE_14_3_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_46 = write_packets_mask_0_2 & write_packets_mask_1_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_47 = _write_packets_packet_is_full_T_46 & write_packets_mask_2_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_48 = _write_packets_packet_is_full_T_47 & write_packets_mask_3_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_49 = _write_packets_packet_is_full_T_48 & write_packets_mask_4_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_50 = _write_packets_packet_is_full_T_49 & write_packets_mask_5_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_51 = _write_packets_packet_is_full_T_50 & write_packets_mask_6_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_52 = _write_packets_packet_is_full_T_51 & write_packets_mask_7_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_53 = _write_packets_packet_is_full_T_52 & write_packets_mask_8_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_54 = _write_packets_packet_is_full_T_53 & write_packets_mask_9_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_55 = _write_packets_packet_is_full_T_54 & write_packets_mask_10_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_56 = _write_packets_packet_is_full_T_55 & write_packets_mask_11_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_57 = _write_packets_packet_is_full_T_56 & write_packets_mask_12_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_58 = _write_packets_packet_is_full_T_57 & write_packets_mask_13_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_59 = _write_packets_packet_is_full_T_58 & write_packets_mask_14_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_60 = _write_packets_packet_is_full_T_59 & write_packets_mask_15_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_61 = _write_packets_packet_is_full_T_60 & write_packets_mask_16_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_62 = _write_packets_packet_is_full_T_61 & write_packets_mask_17_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_63 = _write_packets_packet_is_full_T_62 & write_packets_mask_18_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_64 = _write_packets_packet_is_full_T_63 & write_packets_mask_19_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_65 = _write_packets_packet_is_full_T_64 & write_packets_mask_20_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_66 = _write_packets_packet_is_full_T_65 & write_packets_mask_21_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_67 = _write_packets_packet_is_full_T_66 & write_packets_mask_22_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_68 = _write_packets_packet_is_full_T_67 & write_packets_mask_23_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_69 = _write_packets_packet_is_full_T_68 & write_packets_mask_24_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_70 = _write_packets_packet_is_full_T_69 & write_packets_mask_25_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_71 = _write_packets_packet_is_full_T_70 & write_packets_mask_26_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_72 = _write_packets_packet_is_full_T_71 & write_packets_mask_27_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_73 = _write_packets_packet_is_full_T_72 & write_packets_mask_28_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_74 = _write_packets_packet_is_full_T_73 & write_packets_mask_29_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_75 = _write_packets_packet_is_full_T_74 & write_packets_mask_30_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_76 = _write_packets_packet_is_full_T_75 & write_packets_mask_31_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_77 = _write_packets_packet_is_full_T_76 & write_packets_mask_32_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_78 = _write_packets_packet_is_full_T_77 & write_packets_mask_33_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_79 = _write_packets_packet_is_full_T_78 & write_packets_mask_34_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_80 = _write_packets_packet_is_full_T_79 & write_packets_mask_35_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_81 = _write_packets_packet_is_full_T_80 & write_packets_mask_36_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_82 = _write_packets_packet_is_full_T_81 & write_packets_mask_37_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_83 = _write_packets_packet_is_full_T_82 & write_packets_mask_38_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_84 = _write_packets_packet_is_full_T_83 & write_packets_mask_39_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_85 = _write_packets_packet_is_full_T_84 & write_packets_mask_40_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_86 = _write_packets_packet_is_full_T_85 & write_packets_mask_41_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_87 = _write_packets_packet_is_full_T_86 & write_packets_mask_42_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_88 = _write_packets_packet_is_full_T_87 & write_packets_mask_43_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_89 = _write_packets_packet_is_full_T_88 & write_packets_mask_44_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_90 = _write_packets_packet_is_full_T_89 & write_packets_mask_45_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_91 = _write_packets_packet_is_full_T_90 & write_packets_mask_46_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_92 = _write_packets_packet_is_full_T_91 & write_packets_mask_47_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_93 = _write_packets_packet_is_full_T_92 & write_packets_mask_48_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_94 = _write_packets_packet_is_full_T_93 & write_packets_mask_49_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_95 = _write_packets_packet_is_full_T_94 & write_packets_mask_50_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_96 = _write_packets_packet_is_full_T_95 & write_packets_mask_51_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_97 = _write_packets_packet_is_full_T_96 & write_packets_mask_52_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_98 = _write_packets_packet_is_full_T_97 & write_packets_mask_53_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_99 = _write_packets_packet_is_full_T_98 & write_packets_mask_54_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_100 = _write_packets_packet_is_full_T_99 & write_packets_mask_55_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_101 = _write_packets_packet_is_full_T_100 & write_packets_mask_56_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_102 = _write_packets_packet_is_full_T_101 & write_packets_mask_57_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_103 = _write_packets_packet_is_full_T_102 & write_packets_mask_58_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_104 = _write_packets_packet_is_full_T_103 & write_packets_mask_59_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_105 = _write_packets_packet_is_full_T_104 & write_packets_mask_60_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_106 = _write_packets_packet_is_full_T_105 & write_packets_mask_61_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_107 = _write_packets_packet_is_full_T_106 & write_packets_mask_62_2; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_108 = _write_packets_packet_is_full_T_107 & write_packets_mask_63_2; // @[DMA.scala:431:103, :442:47] assign write_packets_2_is_full = _write_packets_packet_is_full_T_108; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_42 = _write_packets_left_shift_T_41; // @[DMA.scala:449:{62,78}] wire [6:0] _write_packets_left_shift_T_43 = {1'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :450:24] wire [5:0] _write_packets_left_shift_T_44 = _write_packets_left_shift_T_43[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_8 = _write_packets_left_shift_T_42 ? _write_packets_left_shift_T_44 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_67 = _write_packets_right_shift_T_66 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_68 = _write_packets_right_shift_T_67; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_70 = 9'h10 - {1'h0, _write_packets_right_shift_T_69}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_71 = _write_packets_right_shift_T_70[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_8 = _write_packets_right_shift_T_68 ? _write_packets_right_shift_T_71 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_early_8 = \|(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :457:38] wire write_packets_too_late_8 = _write_packets_too_late_T_8 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_10 = write_packets_too_early_8 \| write_packets_too_late_8; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_11 = {3'h0, write_packets_left_shift_8} + {1'h0, write_packets_right_shift_8}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_13 = _write_packets_packet_bytes_written_per_beat_0_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_14 = _write_packets_packet_bytes_written_per_beat_0_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_45 = \|(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :449:43, :457:38] wire _write_packets_left_shift_T_46 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_47 = _write_packets_left_shift_T_45 & _write_packets_left_shift_T_46; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_48 = _write_packets_left_shift_T_43 - 7'h10; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_49 = _write_packets_left_shift_T_48[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_9 = _write_packets_left_shift_T_47 ? _write_packets_left_shift_T_49 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_73 = \|(_write_packets_right_shift_T_72[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_75 = _write_packets_right_shift_T_74 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_76 = _write_packets_right_shift_T_73 & _write_packets_right_shift_T_75; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_78 = 9'h20 - {1'h0, _write_packets_right_shift_T_77}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_79 = _write_packets_right_shift_T_78[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_9 = _write_packets_right_shift_T_76 ? _write_packets_right_shift_T_79 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_9 = _write_packets_too_late_T_9 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_10 = write_packets_too_early_9 \| write_packets_too_late_9; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_11 = {3'h0, write_packets_left_shift_9} + {1'h0, write_packets_right_shift_9}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_13 = _write_packets_packet_bytes_written_per_beat_1_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_14 = _write_packets_packet_bytes_written_per_beat_1_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_52 = _write_packets_left_shift_T_50 & _write_packets_left_shift_T_51; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_53 = _write_packets_left_shift_T_43 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_54 = _write_packets_left_shift_T_53[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_10 = _write_packets_left_shift_T_52 ? _write_packets_left_shift_T_54 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_81 = \|(_write_packets_right_shift_T_80[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_83 = _write_packets_right_shift_T_82 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_84 = _write_packets_right_shift_T_81 & _write_packets_right_shift_T_83; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_86 = 9'h30 - {1'h0, _write_packets_right_shift_T_85}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_87 = _write_packets_right_shift_T_86[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_10 = _write_packets_right_shift_T_84 ? _write_packets_right_shift_T_87 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire _GEN_10 = write_packets_vaddr_offset_2 > 6'h2F; // @[DMA.scala:429:42, :457:38] wire write_packets_too_early_10; // @[DMA.scala:457:38] assign write_packets_too_early_10 = _GEN_10; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_55; // @[DMA.scala:449:43] assign _write_packets_left_shift_T_55 = _GEN_10; // @[DMA.scala:449:43, :457:38] wire write_packets_too_late_10 = _write_packets_too_late_T_10 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_10 = write_packets_too_early_10 \| write_packets_too_late_10; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_11 = {3'h0, write_packets_left_shift_10} + {1'h0, write_packets_right_shift_10}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_13 = _write_packets_packet_bytes_written_per_beat_2_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_14 = _write_packets_packet_bytes_written_per_beat_2_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_57 = _write_packets_left_shift_T_55; // @[DMA.scala:449:{43,62}] wire [6:0] _write_packets_left_shift_T_58 = _write_packets_left_shift_T_43 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_59 = _write_packets_left_shift_T_58[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_11 = _write_packets_left_shift_T_57 ? _write_packets_left_shift_T_59 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_89 = _write_packets_right_shift_T_88 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_91 = _write_packets_right_shift_T_90 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_92 = _write_packets_right_shift_T_89 & _write_packets_right_shift_T_91; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_94 = 9'h40 - {1'h0, _write_packets_right_shift_T_93}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_95 = _write_packets_right_shift_T_94[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_11 = _write_packets_right_shift_T_92 ? _write_packets_right_shift_T_95 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_11 = _write_packets_too_late_T_11 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_10 = write_packets_too_late_11; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_11 = {3'h0, write_packets_left_shift_11} + {1'h0, write_packets_right_shift_11}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_13 = _write_packets_packet_bytes_written_per_beat_3_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_14 = _write_packets_packet_bytes_written_per_beat_3_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _best_write_packet_T = write_packets_1_bytes_written > write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:27] wire [6:0] _best_write_packet_T_1_size = _best_write_packet_T ? 7'h20 : 7'h10; // @[DMA.scala:466:{10,27}] wire [2:0] _best_write_packet_T_1_lg_size = {2'h2, _best_write_packet_T}; // @[DMA.scala:466:{10,27}] wire _best_write_packet_T_1_mask_0_0 = _best_write_packet_T ? write_packets_1_mask_0_0 : write_packets_0_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_1 = _best_write_packet_T ? write_packets_1_mask_0_1 : write_packets_0_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_2 = _best_write_packet_T ? write_packets_1_mask_0_2 : write_packets_0_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_3 = _best_write_packet_T ? write_packets_1_mask_0_3 : write_packets_0_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_4 = _best_write_packet_T ? write_packets_1_mask_0_4 : write_packets_0_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_5 = _best_write_packet_T ? write_packets_1_mask_0_5 : write_packets_0_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_6 = _best_write_packet_T ? write_packets_1_mask_0_6 : write_packets_0_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_7 = _best_write_packet_T ? write_packets_1_mask_0_7 : write_packets_0_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_8 = _best_write_packet_T ? write_packets_1_mask_0_8 : write_packets_0_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_9 = _best_write_packet_T ? write_packets_1_mask_0_9 : write_packets_0_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_10 = _best_write_packet_T ? write_packets_1_mask_0_10 : write_packets_0_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_11 = _best_write_packet_T ? write_packets_1_mask_0_11 : write_packets_0_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_12 = _best_write_packet_T ? write_packets_1_mask_0_12 : write_packets_0_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_13 = _best_write_packet_T ? write_packets_1_mask_0_13 : write_packets_0_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_14 = _best_write_packet_T ? write_packets_1_mask_0_14 : write_packets_0_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_15 = _best_write_packet_T ? write_packets_1_mask_0_15 : write_packets_0_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_0 = _best_write_packet_T & write_packets_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_1 = _best_write_packet_T & write_packets_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_2 = _best_write_packet_T & write_packets_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_3 = _best_write_packet_T & write_packets_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_4 = _best_write_packet_T & write_packets_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_5 = _best_write_packet_T & write_packets_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_6 = _best_write_packet_T & write_packets_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_7 = _best_write_packet_T & write_packets_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_8 = _best_write_packet_T & write_packets_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_9 = _best_write_packet_T & write_packets_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_10 = _best_write_packet_T & write_packets_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_11 = _best_write_packet_T & write_packets_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_12 = _best_write_packet_T & write_packets_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_13 = _best_write_packet_T & write_packets_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_14 = _best_write_packet_T & write_packets_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_15 = _best_write_packet_T & write_packets_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] _best_write_packet_T_1_vaddr = _best_write_packet_T ? write_packets_1_vaddr : write_packets_0_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_is_full = _best_write_packet_T ? write_packets_1_is_full : write_packets_0_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] _best_write_packet_T_1_bytes_written = _best_write_packet_T ? write_packets_1_bytes_written : write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_0 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_0 : write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_1 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_1 : write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_2 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_2 : write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_3 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_3 : write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_2 = write_packets_2_bytes_written > _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_size = _best_write_packet_T_2 ? 7'h40 : _best_write_packet_T_1_size; // @[DMA.scala:466:{10,27}] wire [2:0] best_write_packet_lg_size = _best_write_packet_T_2 ? 3'h6 : _best_write_packet_T_1_lg_size; // @[DMA.scala:466:{10,27}] wire best_write_packet_mask_0_0 = _best_write_packet_T_2 ? write_packets_2_mask_0_0 : _best_write_packet_T_1_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_1 = _best_write_packet_T_2 ? write_packets_2_mask_0_1 : _best_write_packet_T_1_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_2 = _best_write_packet_T_2 ? write_packets_2_mask_0_2 : _best_write_packet_T_1_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_3 = _best_write_packet_T_2 ? write_packets_2_mask_0_3 : _best_write_packet_T_1_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_4 = _best_write_packet_T_2 ? write_packets_2_mask_0_4 : _best_write_packet_T_1_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_5 = _best_write_packet_T_2 ? write_packets_2_mask_0_5 : _best_write_packet_T_1_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_6 = _best_write_packet_T_2 ? write_packets_2_mask_0_6 : _best_write_packet_T_1_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_7 = _best_write_packet_T_2 ? write_packets_2_mask_0_7 : _best_write_packet_T_1_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_8 = _best_write_packet_T_2 ? write_packets_2_mask_0_8 : _best_write_packet_T_1_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_9 = _best_write_packet_T_2 ? write_packets_2_mask_0_9 : _best_write_packet_T_1_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_10 = _best_write_packet_T_2 ? write_packets_2_mask_0_10 : _best_write_packet_T_1_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_11 = _best_write_packet_T_2 ? write_packets_2_mask_0_11 : _best_write_packet_T_1_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_12 = _best_write_packet_T_2 ? write_packets_2_mask_0_12 : _best_write_packet_T_1_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_13 = _best_write_packet_T_2 ? write_packets_2_mask_0_13 : _best_write_packet_T_1_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_14 = _best_write_packet_T_2 ? write_packets_2_mask_0_14 : _best_write_packet_T_1_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_15 = _best_write_packet_T_2 ? write_packets_2_mask_0_15 : _best_write_packet_T_1_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_0 = _best_write_packet_T_2 ? write_packets_2_mask_1_0 : _best_write_packet_T_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_1 = _best_write_packet_T_2 ? write_packets_2_mask_1_1 : _best_write_packet_T_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_2 = _best_write_packet_T_2 ? write_packets_2_mask_1_2 : _best_write_packet_T_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_3 = _best_write_packet_T_2 ? write_packets_2_mask_1_3 : _best_write_packet_T_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_4 = _best_write_packet_T_2 ? write_packets_2_mask_1_4 : _best_write_packet_T_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_5 = _best_write_packet_T_2 ? write_packets_2_mask_1_5 : _best_write_packet_T_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_6 = _best_write_packet_T_2 ? write_packets_2_mask_1_6 : _best_write_packet_T_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_7 = _best_write_packet_T_2 ? write_packets_2_mask_1_7 : _best_write_packet_T_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_8 = _best_write_packet_T_2 ? write_packets_2_mask_1_8 : _best_write_packet_T_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_9 = _best_write_packet_T_2 ? write_packets_2_mask_1_9 : _best_write_packet_T_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_10 = _best_write_packet_T_2 ? write_packets_2_mask_1_10 : _best_write_packet_T_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_11 = _best_write_packet_T_2 ? write_packets_2_mask_1_11 : _best_write_packet_T_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_12 = _best_write_packet_T_2 ? write_packets_2_mask_1_12 : _best_write_packet_T_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_13 = _best_write_packet_T_2 ? write_packets_2_mask_1_13 : _best_write_packet_T_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_14 = _best_write_packet_T_2 ? write_packets_2_mask_1_14 : _best_write_packet_T_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_15 = _best_write_packet_T_2 ? write_packets_2_mask_1_15 : _best_write_packet_T_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_0 = _best_write_packet_T_2 & write_packets_2_mask_2_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_1 = _best_write_packet_T_2 & write_packets_2_mask_2_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_2 = _best_write_packet_T_2 & write_packets_2_mask_2_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_3 = _best_write_packet_T_2 & write_packets_2_mask_2_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_4 = _best_write_packet_T_2 & write_packets_2_mask_2_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_5 = _best_write_packet_T_2 & write_packets_2_mask_2_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_6 = _best_write_packet_T_2 & write_packets_2_mask_2_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_7 = _best_write_packet_T_2 & write_packets_2_mask_2_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_8 = _best_write_packet_T_2 & write_packets_2_mask_2_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_9 = _best_write_packet_T_2 & write_packets_2_mask_2_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_10 = _best_write_packet_T_2 & write_packets_2_mask_2_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_11 = _best_write_packet_T_2 & write_packets_2_mask_2_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_12 = _best_write_packet_T_2 & write_packets_2_mask_2_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_13 = _best_write_packet_T_2 & write_packets_2_mask_2_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_14 = _best_write_packet_T_2 & write_packets_2_mask_2_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_15 = _best_write_packet_T_2 & write_packets_2_mask_2_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_0 = _best_write_packet_T_2 & write_packets_2_mask_3_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_1 = _best_write_packet_T_2 & write_packets_2_mask_3_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_2 = _best_write_packet_T_2 & write_packets_2_mask_3_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_3 = _best_write_packet_T_2 & write_packets_2_mask_3_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_4 = _best_write_packet_T_2 & write_packets_2_mask_3_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_5 = _best_write_packet_T_2 & write_packets_2_mask_3_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_6 = _best_write_packet_T_2 & write_packets_2_mask_3_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_7 = _best_write_packet_T_2 & write_packets_2_mask_3_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_8 = _best_write_packet_T_2 & write_packets_2_mask_3_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_9 = _best_write_packet_T_2 & write_packets_2_mask_3_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_10 = _best_write_packet_T_2 & write_packets_2_mask_3_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_11 = _best_write_packet_T_2 & write_packets_2_mask_3_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_12 = _best_write_packet_T_2 & write_packets_2_mask_3_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_13 = _best_write_packet_T_2 & write_packets_2_mask_3_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_14 = _best_write_packet_T_2 & write_packets_2_mask_3_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_15 = _best_write_packet_T_2 & write_packets_2_mask_3_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] best_write_packet_vaddr = _best_write_packet_T_2 ? write_packets_2_vaddr : _best_write_packet_T_1_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_is_full = _best_write_packet_T_2 ? write_packets_2_is_full : _best_write_packet_T_1_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_bytes_written = _best_write_packet_T_2 ? write_packets_2_bytes_written : _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_0 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_0 : _best_write_packet_T_1_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_1 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_1 : _best_write_packet_T_1_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_2 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_2 : _best_write_packet_T_1_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_3 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_3 : _best_write_packet_T_1_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _T_7 = state == 2'h1; // @[DMA.scala:380:24, :468:63] wire _write_packet_T; // @[DMA.scala:468:63] assign _write_packet_T = _T_7; // @[DMA.scala:468:63] wire _beatsSent_T; // @[DMA.scala:477:31] assign _beatsSent_T = _T_7; // @[DMA.scala:468:63, :477:31] wire _putFull_T; // @[DMA.scala:486:48] assign _putFull_T = _T_7; // @[DMA.scala:468:63, :486:48] wire _putPartial_T; // @[DMA.scala:493:48] assign _putPartial_T = _T_7; // @[DMA.scala:468:63, :493:48] wire _xactBusy_fire_T_1; // @[DMA.scala:507:51] assign _xactBusy_fire_T_1 = _T_7; // @[DMA.scala:468:63, :507:51] wire _untranslated_a_valid_T; // @[DMA.scala:508:36] assign _untranslated_a_valid_T = _T_7; // @[DMA.scala:468:63, :508:36] reg [6:0] write_packet_buf_size; // @[Util.scala:90:24] reg [2:0] write_packet_buf_lg_size; // @[Util.scala:90:24] reg write_packet_buf_mask_0_0; // @[Util.scala:90:24] reg write_packet_buf_mask_0_1; // @[Util.scala:90:24] reg write_packet_buf_mask_0_2; // @[Util.scala:90:24] reg write_packet_buf_mask_0_3; // @[Util.scala:90:24] reg write_packet_buf_mask_0_4; // @[Util.scala:90:24] reg write_packet_buf_mask_0_5; // @[Util.scala:90:24] reg write_packet_buf_mask_0_6; // @[Util.scala:90:24] reg write_packet_buf_mask_0_7; // @[Util.scala:90:24] reg write_packet_buf_mask_0_8; // @[Util.scala:90:24] reg write_packet_buf_mask_0_9; // @[Util.scala:90:24] reg write_packet_buf_mask_0_10; // @[Util.scala:90:24] reg write_packet_buf_mask_0_11; // @[Util.scala:90:24] reg write_packet_buf_mask_0_12; // @[Util.scala:90:24] reg write_packet_buf_mask_0_13; // @[Util.scala:90:24] reg write_packet_buf_mask_0_14; // @[Util.scala:90:24] reg write_packet_buf_mask_0_15; // @[Util.scala:90:24] reg write_packet_buf_mask_1_0; // @[Util.scala:90:24] reg write_packet_buf_mask_1_1; // @[Util.scala:90:24] reg write_packet_buf_mask_1_2; // @[Util.scala:90:24] reg write_packet_buf_mask_1_3; // @[Util.scala:90:24] reg write_packet_buf_mask_1_4; // @[Util.scala:90:24] reg write_packet_buf_mask_1_5; // @[Util.scala:90:24] reg write_packet_buf_mask_1_6; // @[Util.scala:90:24] reg write_packet_buf_mask_1_7; // @[Util.scala:90:24] reg write_packet_buf_mask_1_8; // @[Util.scala:90:24] reg write_packet_buf_mask_1_9; // @[Util.scala:90:24] reg write_packet_buf_mask_1_10; // @[Util.scala:90:24] reg write_packet_buf_mask_1_11; // @[Util.scala:90:24] reg write_packet_buf_mask_1_12; // @[Util.scala:90:24] reg write_packet_buf_mask_1_13; // @[Util.scala:90:24] reg write_packet_buf_mask_1_14; // @[Util.scala:90:24] reg write_packet_buf_mask_1_15; // @[Util.scala:90:24] reg write_packet_buf_mask_2_0; // @[Util.scala:90:24] reg write_packet_buf_mask_2_1; // @[Util.scala:90:24] reg write_packet_buf_mask_2_2; // @[Util.scala:90:24] reg write_packet_buf_mask_2_3; // @[Util.scala:90:24] reg write_packet_buf_mask_2_4; // @[Util.scala:90:24] reg write_packet_buf_mask_2_5; // @[Util.scala:90:24] reg write_packet_buf_mask_2_6; // @[Util.scala:90:24] reg write_packet_buf_mask_2_7; // @[Util.scala:90:24] reg write_packet_buf_mask_2_8; // @[Util.scala:90:24] reg write_packet_buf_mask_2_9; // @[Util.scala:90:24] reg write_packet_buf_mask_2_10; // @[Util.scala:90:24] reg write_packet_buf_mask_2_11; // @[Util.scala:90:24] reg write_packet_buf_mask_2_12; // @[Util.scala:90:24] reg write_packet_buf_mask_2_13; // @[Util.scala:90:24] reg write_packet_buf_mask_2_14; // @[Util.scala:90:24] reg write_packet_buf_mask_2_15; // @[Util.scala:90:24] reg write_packet_buf_mask_3_0; // @[Util.scala:90:24] reg write_packet_buf_mask_3_1; // @[Util.scala:90:24] reg write_packet_buf_mask_3_2; // @[Util.scala:90:24] reg write_packet_buf_mask_3_3; // @[Util.scala:90:24] reg write_packet_buf_mask_3_4; // @[Util.scala:90:24] reg write_packet_buf_mask_3_5; // @[Util.scala:90:24] reg write_packet_buf_mask_3_6; // @[Util.scala:90:24] reg write_packet_buf_mask_3_7; // @[Util.scala:90:24] reg write_packet_buf_mask_3_8; // @[Util.scala:90:24] reg write_packet_buf_mask_3_9; // @[Util.scala:90:24] reg write_packet_buf_mask_3_10; // @[Util.scala:90:24] reg write_packet_buf_mask_3_11; // @[Util.scala:90:24] reg write_packet_buf_mask_3_12; // @[Util.scala:90:24] reg write_packet_buf_mask_3_13; // @[Util.scala:90:24] reg write_packet_buf_mask_3_14; // @[Util.scala:90:24] reg write_packet_buf_mask_3_15; // @[Util.scala:90:24] reg [38:0] write_packet_buf_vaddr; // @[Util.scala:90:24] reg write_packet_buf_is_full; // @[Util.scala:90:24] reg [6:0] write_packet_buf_bytes_written; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24] wire [6:0] write_packet_size = _write_packet_T ? best_write_packet_size : write_packet_buf_size; // @[Util.scala:90:24, :91:8] wire [2:0] write_packet_lg_size = _write_packet_T ? best_write_packet_lg_size : write_packet_buf_lg_size; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_0 = _write_packet_T ? best_write_packet_mask_0_0 : write_packet_buf_mask_0_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_1 = _write_packet_T ? best_write_packet_mask_0_1 : write_packet_buf_mask_0_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_2 = _write_packet_T ? best_write_packet_mask_0_2 : write_packet_buf_mask_0_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_3 = _write_packet_T ? best_write_packet_mask_0_3 : write_packet_buf_mask_0_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_4 = _write_packet_T ? best_write_packet_mask_0_4 : write_packet_buf_mask_0_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_5 = _write_packet_T ? best_write_packet_mask_0_5 : write_packet_buf_mask_0_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_6 = _write_packet_T ? best_write_packet_mask_0_6 : write_packet_buf_mask_0_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_7 = _write_packet_T ? best_write_packet_mask_0_7 : write_packet_buf_mask_0_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_8 = _write_packet_T ? best_write_packet_mask_0_8 : write_packet_buf_mask_0_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_9 = _write_packet_T ? best_write_packet_mask_0_9 : write_packet_buf_mask_0_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_10 = _write_packet_T ? best_write_packet_mask_0_10 : write_packet_buf_mask_0_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_11 = _write_packet_T ? best_write_packet_mask_0_11 : write_packet_buf_mask_0_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_12 = _write_packet_T ? best_write_packet_mask_0_12 : write_packet_buf_mask_0_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_13 = _write_packet_T ? best_write_packet_mask_0_13 : write_packet_buf_mask_0_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_14 = _write_packet_T ? best_write_packet_mask_0_14 : write_packet_buf_mask_0_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_15 = _write_packet_T ? best_write_packet_mask_0_15 : write_packet_buf_mask_0_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_0 = _write_packet_T ? best_write_packet_mask_1_0 : write_packet_buf_mask_1_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_1 = _write_packet_T ? best_write_packet_mask_1_1 : write_packet_buf_mask_1_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_2 = _write_packet_T ? best_write_packet_mask_1_2 : write_packet_buf_mask_1_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_3 = _write_packet_T ? best_write_packet_mask_1_3 : write_packet_buf_mask_1_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_4 = _write_packet_T ? best_write_packet_mask_1_4 : write_packet_buf_mask_1_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_5 = _write_packet_T ? best_write_packet_mask_1_5 : write_packet_buf_mask_1_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_6 = _write_packet_T ? best_write_packet_mask_1_6 : write_packet_buf_mask_1_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_7 = _write_packet_T ? best_write_packet_mask_1_7 : write_packet_buf_mask_1_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_8 = _write_packet_T ? best_write_packet_mask_1_8 : write_packet_buf_mask_1_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_9 = _write_packet_T ? best_write_packet_mask_1_9 : write_packet_buf_mask_1_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_10 = _write_packet_T ? best_write_packet_mask_1_10 : write_packet_buf_mask_1_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_11 = _write_packet_T ? best_write_packet_mask_1_11 : write_packet_buf_mask_1_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_12 = _write_packet_T ? best_write_packet_mask_1_12 : write_packet_buf_mask_1_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_13 = _write_packet_T ? best_write_packet_mask_1_13 : write_packet_buf_mask_1_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_14 = _write_packet_T ? best_write_packet_mask_1_14 : write_packet_buf_mask_1_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_15 = _write_packet_T ? best_write_packet_mask_1_15 : write_packet_buf_mask_1_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_0 = _write_packet_T ? best_write_packet_mask_2_0 : write_packet_buf_mask_2_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_1 = _write_packet_T ? best_write_packet_mask_2_1 : write_packet_buf_mask_2_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_2 = _write_packet_T ? best_write_packet_mask_2_2 : write_packet_buf_mask_2_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_3 = _write_packet_T ? best_write_packet_mask_2_3 : write_packet_buf_mask_2_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_4 = _write_packet_T ? best_write_packet_mask_2_4 : write_packet_buf_mask_2_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_5 = _write_packet_T ? best_write_packet_mask_2_5 : write_packet_buf_mask_2_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_6 = _write_packet_T ? best_write_packet_mask_2_6 : write_packet_buf_mask_2_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_7 = _write_packet_T ? best_write_packet_mask_2_7 : write_packet_buf_mask_2_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_8 = _write_packet_T ? best_write_packet_mask_2_8 : write_packet_buf_mask_2_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_9 = _write_packet_T ? best_write_packet_mask_2_9 : write_packet_buf_mask_2_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_10 = _write_packet_T ? best_write_packet_mask_2_10 : write_packet_buf_mask_2_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_11 = _write_packet_T ? best_write_packet_mask_2_11 : write_packet_buf_mask_2_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_12 = _write_packet_T ? best_write_packet_mask_2_12 : write_packet_buf_mask_2_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_13 = _write_packet_T ? best_write_packet_mask_2_13 : write_packet_buf_mask_2_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_14 = _write_packet_T ? best_write_packet_mask_2_14 : write_packet_buf_mask_2_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_15 = _write_packet_T ? best_write_packet_mask_2_15 : write_packet_buf_mask_2_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_0 = _write_packet_T ? best_write_packet_mask_3_0 : write_packet_buf_mask_3_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_1 = _write_packet_T ? best_write_packet_mask_3_1 : write_packet_buf_mask_3_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_2 = _write_packet_T ? best_write_packet_mask_3_2 : write_packet_buf_mask_3_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_3 = _write_packet_T ? best_write_packet_mask_3_3 : write_packet_buf_mask_3_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_4 = _write_packet_T ? best_write_packet_mask_3_4 : write_packet_buf_mask_3_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_5 = _write_packet_T ? best_write_packet_mask_3_5 : write_packet_buf_mask_3_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_6 = _write_packet_T ? best_write_packet_mask_3_6 : write_packet_buf_mask_3_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_7 = _write_packet_T ? best_write_packet_mask_3_7 : write_packet_buf_mask_3_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_8 = _write_packet_T ? best_write_packet_mask_3_8 : write_packet_buf_mask_3_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_9 = _write_packet_T ? best_write_packet_mask_3_9 : write_packet_buf_mask_3_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_10 = _write_packet_T ? best_write_packet_mask_3_10 : write_packet_buf_mask_3_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_11 = _write_packet_T ? best_write_packet_mask_3_11 : write_packet_buf_mask_3_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_12 = _write_packet_T ? best_write_packet_mask_3_12 : write_packet_buf_mask_3_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_13 = _write_packet_T ? best_write_packet_mask_3_13 : write_packet_buf_mask_3_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_14 = _write_packet_T ? best_write_packet_mask_3_14 : write_packet_buf_mask_3_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_15 = _write_packet_T ? best_write_packet_mask_3_15 : write_packet_buf_mask_3_15; // @[Util.scala:90:24, :91:8] wire [38:0] write_packet_vaddr = _write_packet_T ? best_write_packet_vaddr : write_packet_buf_vaddr; // @[Util.scala:90:24, :91:8] wire write_packet_is_full = _write_packet_T ? best_write_packet_is_full : write_packet_buf_is_full; // @[Util.scala:90:24, :91:8] wire [6:0] write_packet_bytes_written = _write_packet_T ? best_write_packet_bytes_written : write_packet_buf_bytes_written; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_0 = _write_packet_T ? best_write_packet_bytes_written_per_beat_0 : write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_1 = _write_packet_T ? best_write_packet_bytes_written_per_beat_1 : write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_2 = _write_packet_T ? best_write_packet_bytes_written_per_beat_2 : write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_3 = _write_packet_T ? best_write_packet_bytes_written_per_beat_3 : write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24, :91:8] wire [38:0] untranslated_a_bits_vaddr = write_packet_vaddr; // @[Util.scala:91:8] wire _write_beats_T = write_packet_size < 7'h10; // @[Util.scala:91:8] wire [6:0] _write_beats_T_1 = write_packet_size / 7'h10; // @[Util.scala:91:8] wire [6:0] write_beats = _write_beats_T ? 7'h1 : _write_beats_T_1; // @[DMA.scala:418:{44,50,75}] reg [5:0] beatsLeft; // @[DMA.scala:476:24] wire [7:0] _GEN_11 = {1'h0, write_beats}; // @[DMA.scala:418:44, :477:73] wire [7:0] _beatsSent_T_1 = _GEN_11 - {2'h0, beatsLeft}; // @[DMA.scala:476:24, :477:73] wire [6:0] _beatsSent_T_2 = _beatsSent_T_1[6:0]; // @[DMA.scala:477:73] wire [6:0] beatsSent = _beatsSent_T ? 7'h0 : _beatsSent_T_2; // @[DMA.scala:477:{24,31,73}] wire [1:0] _write_mask_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [1:0] _bytes_written_this_beat_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [3:0] _GEN_12 = {{write_packet_mask_3_0}, {write_packet_mask_2_0}, {write_packet_mask_1_0}, {write_packet_mask_0_0}}; // @[Mux.scala:50:70] wire [3:0] _GEN_13 = {{write_packet_mask_3_1}, {write_packet_mask_2_1}, {write_packet_mask_1_1}, {write_packet_mask_0_1}}; // @[Mux.scala:50:70] wire [3:0] _GEN_14 = {{write_packet_mask_3_2}, {write_packet_mask_2_2}, {write_packet_mask_1_2}, {write_packet_mask_0_2}}; // @[Mux.scala:50:70] wire [3:0] _GEN_15 = {{write_packet_mask_3_3}, {write_packet_mask_2_3}, {write_packet_mask_1_3}, {write_packet_mask_0_3}}; // @[Mux.scala:50:70] wire [3:0] _GEN_16 = {{write_packet_mask_3_4}, {write_packet_mask_2_4}, {write_packet_mask_1_4}, {write_packet_mask_0_4}}; // @[Mux.scala:50:70] wire [3:0] _GEN_17 = {{write_packet_mask_3_5}, {write_packet_mask_2_5}, {write_packet_mask_1_5}, {write_packet_mask_0_5}}; // @[Mux.scala:50:70] wire [3:0] _GEN_18 = {{write_packet_mask_3_6}, {write_packet_mask_2_6}, {write_packet_mask_1_6}, {write_packet_mask_0_6}}; // @[Mux.scala:50:70] wire [3:0] _GEN_19 = {{write_packet_mask_3_7}, {write_packet_mask_2_7}, {write_packet_mask_1_7}, {write_packet_mask_0_7}}; // @[Mux.scala:50:70] wire [3:0] _GEN_20 = {{write_packet_mask_3_8}, {write_packet_mask_2_8}, {write_packet_mask_1_8}, {write_packet_mask_0_8}}; // @[Mux.scala:50:70] wire [3:0] _GEN_21 = {{write_packet_mask_3_9}, {write_packet_mask_2_9}, {write_packet_mask_1_9}, {write_packet_mask_0_9}}; // @[Mux.scala:50:70] wire [3:0] _GEN_22 = {{write_packet_mask_3_10}, {write_packet_mask_2_10}, {write_packet_mask_1_10}, {write_packet_mask_0_10}}; // @[Mux.scala:50:70] wire [3:0] _GEN_23 = {{write_packet_mask_3_11}, {write_packet_mask_2_11}, {write_packet_mask_1_11}, {write_packet_mask_0_11}}; // @[Mux.scala:50:70] wire [3:0] _GEN_24 = {{write_packet_mask_3_12}, {write_packet_mask_2_12}, {write_packet_mask_1_12}, {write_packet_mask_0_12}}; // @[Mux.scala:50:70] wire [3:0] _GEN_25 = {{write_packet_mask_3_13}, {write_packet_mask_2_13}, {write_packet_mask_1_13}, {write_packet_mask_0_13}}; // @[Mux.scala:50:70] wire [3:0] _GEN_26 = {{write_packet_mask_3_14}, {write_packet_mask_2_14}, {write_packet_mask_1_14}, {write_packet_mask_0_14}}; // @[Mux.scala:50:70] wire [3:0] _GEN_27 = {{write_packet_mask_3_15}, {write_packet_mask_2_15}, {write_packet_mask_1_15}, {write_packet_mask_0_15}}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T = {3'h7, ~_GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_1 = _GEN_25[_write_mask_T] ? 4'hD : _write_shift_T; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_2 = _GEN_24[_write_mask_T] ? 4'hC : _write_shift_T_1; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_3 = _GEN_23[_write_mask_T] ? 4'hB : _write_shift_T_2; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_4 = _GEN_22[_write_mask_T] ? 4'hA : _write_shift_T_3; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_5 = _GEN_21[_write_mask_T] ? 4'h9 : _write_shift_T_4; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_6 = _GEN_20[_write_mask_T] ? 4'h8 : _write_shift_T_5; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_7 = _GEN_19[_write_mask_T] ? 4'h7 : _write_shift_T_6; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_8 = _GEN_18[_write_mask_T] ? 4'h6 : _write_shift_T_7; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_9 = _GEN_17[_write_mask_T] ? 4'h5 : _write_shift_T_8; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_10 = _GEN_16[_write_mask_T] ? 4'h4 : _write_shift_T_9; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_11 = _GEN_15[_write_mask_T] ? 4'h3 : _write_shift_T_10; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_12 = _GEN_14[_write_mask_T] ? 4'h2 : _write_shift_T_11; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_13 = _GEN_13[_write_mask_T] ? 4'h1 : _write_shift_T_12; // @[Mux.scala:50:70] wire [3:0] write_shift = _GEN_12[_write_mask_T] ? 4'h0 : _write_shift_T_13; // @[Mux.scala:50:70] reg [3:0] putFull_buf; // @[Util.scala:90:24] wire [3:0] _putFull_T_1 = _putFull_T ? xactId : putFull_buf; // @[OneHot.scala:32:10] wire [3:0] putFull_source = _putFull_T_1; // @[Edges.scala:480:17] wire [10:0] _GEN_28 = {1'h0, bytesSent, 3'h0}; // @[DMA.scala:389:24, :489:34] wire [10:0] _putFull_T_2; // @[DMA.scala:489:34] assign _putFull_T_2 = _GEN_28; // @[DMA.scala:489:34] wire [10:0] _putPartial_T_2; // @[DMA.scala:496:35] assign _putPartial_T_2 = _GEN_28; // @[DMA.scala:489:34, :496:35] wire [511:0] _putFull_T_3 = data >> _putFull_T_2; // @[DMA.scala:387:19, :489:{20,34}] wire _GEN_29 = write_packet_lg_size != 3'h7; // @[Parameters.scala:92:38] wire _putFull_legal_T_11; // @[Parameters.scala:92:38] assign _putFull_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putPartial_legal_T_11; // @[Parameters.scala:92:38] assign _putPartial_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putFull_legal_T_12 = _putFull_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putFull_legal_T_13 = _putFull_legal_T_12; // @[Parameters.scala:684:29] wire _putFull_legal_T_61 = _putFull_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putFull_legal_T_70 = _putFull_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putFull_legal = _putFull_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _putFull_a_mask_T; // @[Misc.scala:222:10] wire [3:0] putFull_size; // @[Edges.scala:480:17] wire [15:0] putFull_mask; // @[Edges.scala:480:17] wire [127:0] putFull_data; // @[Edges.scala:480:17] wire [3:0] _GEN_30 = {1'h0, write_packet_lg_size}; // @[Edges.scala:483:15] assign putFull_size = _GEN_30; // @[Edges.scala:480:17, :483:15] wire [3:0] _putFull_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _putFull_a_mask_sizeOH_T = _GEN_30; // @[Misc.scala:202:34] wire [3:0] putPartial_size; // @[Edges.scala:500:17] assign putPartial_size = _GEN_30; // @[Edges.scala:483:15, :500:17] wire [1:0] putFull_a_mask_sizeOH_shiftAmount = _putFull_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _putFull_a_mask_sizeOH_T_1 = 4'h1 << putFull_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _putFull_a_mask_sizeOH_T_2 = _putFull_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] putFull_a_mask_sizeOH = {_putFull_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire putFull_a_mask_sub_sub_sub_sub_0_1 = write_packet_lg_size[2]; // @[Misc.scala:206:21] wire putFull_a_mask_sub_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21, :215:29] wire putFull_a_mask_sub_sub_sub_size = putFull_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_sub_acc_T = putFull_a_mask_sub_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_sub_0_1 \| _putFull_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire putFull_a_mask_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_2_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_3_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_size = putFull_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_acc_T = putFull_a_mask_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_0_1 \| _putFull_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_1_1 = putFull_a_mask_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_2_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_3_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_4_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_5_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_6_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_7_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_size = putFull_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_acc_T = putFull_a_mask_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_0_1 = putFull_a_mask_sub_sub_0_1 \| _putFull_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_acc_1 = putFull_a_mask_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_2 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_3 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_4 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_5 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_6 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_7 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_8 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_9 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_10 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_11 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_12 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_13 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_14 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_15 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_size = putFull_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_acc_T = putFull_a_mask_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_acc = putFull_a_mask_sub_0_1 \| _putFull_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire [1:0] putFull_a_mask_lo_lo_lo = {putFull_a_mask_acc_1, putFull_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_lo_hi = {putFull_a_mask_acc_3, putFull_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_lo = {putFull_a_mask_lo_lo_hi, putFull_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_lo_hi_lo = {putFull_a_mask_acc_5, putFull_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_hi_hi = {putFull_a_mask_acc_7, putFull_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_hi = {putFull_a_mask_lo_hi_hi, putFull_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_lo = {putFull_a_mask_lo_hi, putFull_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_lo_lo = {putFull_a_mask_acc_9, putFull_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_lo_hi = {putFull_a_mask_acc_11, putFull_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_lo = {putFull_a_mask_hi_lo_hi, putFull_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_hi_lo = {putFull_a_mask_acc_13, putFull_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_hi_hi = {putFull_a_mask_acc_15, putFull_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_hi = {putFull_a_mask_hi_hi_hi, putFull_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_hi = {putFull_a_mask_hi_hi, putFull_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _putFull_a_mask_T = {putFull_a_mask_hi, putFull_a_mask_lo}; // @[Misc.scala:222:10] assign putFull_mask = _putFull_a_mask_T; // @[Misc.scala:222:10] assign putFull_data = _putFull_T_3[127:0]; // @[Edges.scala:480:17, :489:15] reg [3:0] putPartial_buf; // @[Util.scala:90:24] wire [3:0] _putPartial_T_1 = _putPartial_T ? xactId : putPartial_buf; // @[OneHot.scala:32:10] wire [3:0] putPartial_source = _putPartial_T_1; // @[Edges.scala:500:17] wire [511:0] _putPartial_T_3 = data >> _putPartial_T_2; // @[DMA.scala:387:19, :496:{21,35}] wire [7:0] _putPartial_T_4 = {1'h0, write_shift, 3'h0}; // @[Mux.scala:50:70] wire [766:0] _putPartial_T_5 = {255'h0, _putPartial_T_3} << _putPartial_T_4; // @[DMA.scala:496:{21,43,59}] wire [1:0] putPartial_lo_lo_lo = {_GEN_13[_write_mask_T], _GEN_12[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_lo_hi = {_GEN_15[_write_mask_T], _GEN_14[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_lo = {putPartial_lo_lo_hi, putPartial_lo_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_lo_hi_lo = {_GEN_17[_write_mask_T], _GEN_16[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_hi_hi = {_GEN_19[_write_mask_T], _GEN_18[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_hi = {putPartial_lo_hi_hi, putPartial_lo_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_lo = {putPartial_lo_hi, putPartial_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_lo_lo = {_GEN_21[_write_mask_T], _GEN_20[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_lo_hi = {_GEN_23[_write_mask_T], _GEN_22[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_lo = {putPartial_hi_lo_hi, putPartial_hi_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_hi_lo = {_GEN_25[_write_mask_T], _GEN_24[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_hi_hi = {_GEN_27[_write_mask_T], _GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_hi = {putPartial_hi_hi_hi, putPartial_hi_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_hi = {putPartial_hi_hi, putPartial_hi_lo}; // @[DMA.scala:497:25] wire [15:0] _putPartial_T_6 = {putPartial_hi, putPartial_lo}; // @[DMA.scala:497:25] wire [15:0] putPartial_mask = _putPartial_T_6; // @[Edges.scala:500:17] wire _putPartial_legal_T_12 = _putPartial_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putPartial_legal_T_13 = _putPartial_legal_T_12; // @[Parameters.scala:684:29] wire _putPartial_legal_T_61 = _putPartial_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putPartial_legal_T_70 = _putPartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putPartial_legal = _putPartial_legal_T_70; // @[Parameters.scala:686:26] wire [127:0] putPartial_data; // @[Edges.scala:500:17] assign putPartial_data = _putPartial_T_5[127:0]; // @[Edges.scala:500:17, :509:15] wire _untranslated_a_valid_T_5; // @[DMA.scala:508:90] wire [2:0] _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:509:36] wire [3:0] _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:509:36] wire [3:0] _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:509:36] wire [15:0] _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:509:36] wire [127:0] _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:509:36] wire [2:0] untranslated_a_bits_tl_a_opcode; // @[DMA.scala:506:30] wire [3:0] untranslated_a_bits_tl_a_size; // @[DMA.scala:506:30] wire [3:0] untranslated_a_bits_tl_a_source; // @[DMA.scala:506:30] wire [15:0] untranslated_a_bits_tl_a_mask; // @[DMA.scala:506:30] wire [127:0] untranslated_a_bits_tl_a_data; // @[DMA.scala:506:30] wire untranslated_a_ready; // @[DMA.scala:506:30] wire untranslated_a_valid; // @[DMA.scala:506:30] wire _xactBusy_fire_T = untranslated_a_ready & untranslated_a_valid; // @[Decoupled.scala:51:35] assign _xactBusy_fire_T_2 = _xactBusy_fire_T & _xactBusy_fire_T_1; // @[Decoupled.scala:51:35] assign xactBusy_fire = _xactBusy_fire_T_2; // @[DMA.scala:396:33, :507:42] wire _untranslated_a_valid_T_1 = state == 2'h2; // @[DMA.scala:380:24, :508:69] wire _untranslated_a_valid_T_2 = _untranslated_a_valid_T \| _untranslated_a_valid_T_1; // @[DMA.scala:508:{36,60,69}] wire _untranslated_a_valid_T_3 = &xactBusy; // @[DMA.scala:392:27, :508:103] wire _untranslated_a_valid_T_4 = ~_untranslated_a_valid_T_3; // @[DMA.scala:508:{93,103}] assign _untranslated_a_valid_T_5 = _untranslated_a_valid_T_2 & _untranslated_a_valid_T_4; // @[DMA.scala:508:{60,90,93}] assign untranslated_a_valid = _untranslated_a_valid_T_5; // @[DMA.scala:506:30, :508:90] assign _untranslated_a_bits_tl_a_T_opcode = {2'h0, ~write_packet_is_full}; // @[Util.scala:91:8] assign _untranslated_a_bits_tl_a_T_size = write_packet_is_full ? putFull_size : putPartial_size; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_source = write_packet_is_full ? putFull_source : putPartial_source; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_mask = write_packet_is_full ? putFull_mask : putPartial_mask; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_data = write_packet_is_full ? putFull_data : putPartial_data; // @[Edges.scala:480:17, :500:17] assign untranslated_a_bits_tl_a_opcode = _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_size = _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_source = _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_mask = _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_data = _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:506:30, :509:36] wire _retry_a_valid_T; // @[DMA.scala:543:47] wire [2:0] retry_a_bits_tl_a_opcode; // @[DMA.scala:514:23] wire [2:0] retry_a_bits_tl_a_param; // @[DMA.scala:514:23] wire [3:0] retry_a_bits_tl_a_size; // @[DMA.scala:514:23] wire [3:0] retry_a_bits_tl_a_source; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_tl_a_address; // @[DMA.scala:514:23] wire [15:0] retry_a_bits_tl_a_mask; // @[DMA.scala:514:23] wire [127:0] retry_a_bits_tl_a_data; // @[DMA.scala:514:23] wire retry_a_bits_tl_a_corrupt; // @[DMA.scala:514:23] wire retry_a_bits_status_debug; // @[DMA.scala:514:23] wire retry_a_bits_status_cease; // @[DMA.scala:514:23] wire retry_a_bits_status_wfi; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_status_isa; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_dprv; // @[DMA.scala:514:23] wire retry_a_bits_status_dv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_prv; // @[DMA.scala:514:23] wire retry_a_bits_status_v; // @[DMA.scala:514:23] wire retry_a_bits_status_sd; // @[DMA.scala:514:23] wire [22:0] retry_a_bits_status_zero2; // @[DMA.scala:514:23] wire retry_a_bits_status_mpv; // @[DMA.scala:514:23] wire retry_a_bits_status_gva; // @[DMA.scala:514:23] wire retry_a_bits_status_mbe; // @[DMA.scala:514:23] wire retry_a_bits_status_sbe; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_sxl; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_uxl; // @[DMA.scala:514:23] wire retry_a_bits_status_sd_rv32; // @[DMA.scala:514:23] wire [7:0] retry_a_bits_status_zero1; // @[DMA.scala:514:23] wire retry_a_bits_status_tsr; // @[DMA.scala:514:23] wire retry_a_bits_status_tw; // @[DMA.scala:514:23] wire retry_a_bits_status_tvm; // @[DMA.scala:514:23] wire retry_a_bits_status_mxr; // @[DMA.scala:514:23] wire retry_a_bits_status_sum; // @[DMA.scala:514:23] wire retry_a_bits_status_mprv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_xs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_fs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_mpp; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_vs; // @[DMA.scala:514:23] wire retry_a_bits_status_spp; // @[DMA.scala:514:23] wire retry_a_bits_status_mpie; // @[DMA.scala:514:23] wire retry_a_bits_status_ube; // @[DMA.scala:514:23] wire retry_a_bits_status_spie; // @[DMA.scala:514:23] wire retry_a_bits_status_upie; // @[DMA.scala:514:23] wire retry_a_bits_status_mie; // @[DMA.scala:514:23] wire retry_a_bits_status_hie; // @[DMA.scala:514:23] wire retry_a_bits_status_sie; // @[DMA.scala:514:23] wire retry_a_bits_status_uie; // @[DMA.scala:514:23] wire [38:0] retry_a_bits_vaddr; // @[DMA.scala:514:23] wire retry_a_ready; // @[DMA.scala:514:23] wire retry_a_valid; // @[DMA.scala:514:23] assign _io_tlb_req_valid_T = _translate_q_io_enq_ready & _tlb_q_io_deq_valid; // @[Decoupled.scala:51:35] assign io_tlb_req_valid_0 = _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] assign io_tlb_req_bits_tlb_req_vaddr_0 = {1'h0, _tlb_q_io_deq_bits_vaddr}; // @[DMA.scala:360:9, :523:23, :528:35] wire _translate_q_io_deq_ready_T = nodeOut_a_ready \| io_tlb_resp_miss_0; // @[DMA.scala:360:9, :541:44] assign _retry_a_valid_T = _translate_q_io_deq_valid & io_tlb_resp_miss_0; // @[DMA.scala:360:9, :534:29, :543:47] assign retry_a_valid = _retry_a_valid_T; // @[DMA.scala:514:23, :543:47] wire _nodeOut_a_valid_T = ~io_tlb_resp_miss_0; // @[DMA.scala:360:9, :547:47] assign _nodeOut_a_valid_T_1 = _translate_q_io_deq_valid & _nodeOut_a_valid_T; // @[DMA.scala:534:29, :547:{44,47}] assign nodeOut_a_valid = _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] reg nodeOut_a_bits_address_REG; // @[DMA.scala:549:66] reg [31:0] nodeOut_a_bits_address_buf; // @[Util.scala:90:24] assign _nodeOut_a_bits_address_T = nodeOut_a_bits_address_REG ? io_tlb_resp_paddr_0 : nodeOut_a_bits_address_buf; // @[Util.scala:90:24, :91:8] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign _nodeOut_d_ready_T = \|xactBusy; // @[DMA.scala:392:27, :403:25, :551:28] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[DMA.scala:551:28] wire [7:0] _beatsLeft_T = _GEN_11 - 8'h1; // @[DMA.scala:477:73, :555:34] wire [6:0] _beatsLeft_T_1 = _beatsLeft_T[6:0]; // @[DMA.scala:555:34] wire [40:0] _next_vaddr_T = {1'h0, req_vaddr} + {34'h0, write_packet_bytes_written}; // @[Util.scala:91:8] wire [39:0] next_vaddr = _next_vaddr_T[39:0]; // @[DMA.scala:557:36] wire [3:0][4:0] _GEN_31 = {{write_packet_bytes_written_per_beat_3}, {write_packet_bytes_written_per_beat_2}, {write_packet_bytes_written_per_beat_1}, {write_packet_bytes_written_per_beat_0}}; // @[Util.scala:91:8] wire [7:0] _GEN_32 = _GEN + {3'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:390:29, :560:32] wire [7:0] _bytesSent_T; // @[DMA.scala:560:32] assign _bytesSent_T = _GEN_32; // @[DMA.scala:560:32] wire [7:0] _bytesSent_T_2; // @[DMA.scala:573:32] assign _bytesSent_T_2 = _GEN_32; // @[DMA.scala:560:32, :573:32] wire [6:0] _bytesSent_T_1 = _bytesSent_T[6:0]; // @[DMA.scala:560:32] wire _T_8 = write_beats == 7'h1; // @[DMA.scala:418:44, :562:27] wire [6:0] _GEN_33 = {2'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:560:32, :563:41] wire _T_9 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41] wire [6:0] _beatsLeft_T_2 = {1'h0, beatsLeft} - 7'h1; // @[DMA.scala:476:24, :572:32] wire [5:0] _beatsLeft_T_3 = _beatsLeft_T_2[5:0]; // @[DMA.scala:572:32] wire [6:0] _bytesSent_T_3 = _bytesSent_T_2[6:0]; // @[DMA.scala:573:32] wire _T_15 = beatsLeft == 6'h1; // @[DMA.scala:476:24, :577:25] wire _T_16 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41, :578:41] assign state_machine_ready_for_req = _xactBusy_fire_T ? (_T_7 ? _T_8 & _T_9 \| _state_machine_ready_for_req_T : _untranslated_a_valid_T_1 & _T_15 & _T_16 \| _state_machine_ready_for_req_T) : _state_machine_ready_for_req_T; // @[Decoupled.scala:51:35] wire _T_17 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_33; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_35; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_37; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_39; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_41; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_43; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_45; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_47; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_49; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_51; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_53; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_55; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_57; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_59; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_61; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_65; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_67; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_69; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_71; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_73; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_75; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_77; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_79; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_81; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_83; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_85; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_87; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_89; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_91; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_93; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_95; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_97; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_99; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_101; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_103; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_105; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_107; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_109; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_111; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_113; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_115; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_117; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_119; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_121; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_123; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_125; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_127; // @[DMA.scala:593:43] wire [7:0] pooled_v1_0; // @[DMA.scala:593:43] wire [7:0] pooled_v1_1; // @[DMA.scala:593:43] wire [7:0] pooled_v1_2; // @[DMA.scala:593:43] wire [7:0] pooled_v1_3; // @[DMA.scala:593:43] wire [7:0] pooled_v1_4; // @[DMA.scala:593:43] wire [7:0] pooled_v1_5; // @[DMA.scala:593:43] wire [7:0] pooled_v1_6; // @[DMA.scala:593:43] wire [7:0] pooled_v1_7; // @[DMA.scala:593:43] wire [7:0] pooled_v1_8; // @[DMA.scala:593:43] wire [7:0] pooled_v1_9; // @[DMA.scala:593:43] wire [7:0] pooled_v1_10; // @[DMA.scala:593:43] wire [7:0] pooled_v1_11; // @[DMA.scala:593:43] wire [7:0] pooled_v1_12; // @[DMA.scala:593:43] wire [7:0] pooled_v1_13; // @[DMA.scala:593:43] wire [7:0] pooled_v1_14; // @[DMA.scala:593:43] wire [7:0] pooled_v1_15; // @[DMA.scala:593:43] wire [7:0] pooled_v1_16; // @[DMA.scala:593:43] wire [7:0] pooled_v1_17; // @[DMA.scala:593:43] wire [7:0] pooled_v1_18; // @[DMA.scala:593:43] wire [7:0] pooled_v1_19; // @[DMA.scala:593:43] wire [7:0] pooled_v1_20; // @[DMA.scala:593:43] wire [7:0] pooled_v1_21; // @[DMA.scala:593:43] wire [7:0] pooled_v1_22; // @[DMA.scala:593:43] wire [7:0] pooled_v1_23; // @[DMA.scala:593:43] wire [7:0] pooled_v1_24; // @[DMA.scala:593:43] wire [7:0] pooled_v1_25; // @[DMA.scala:593:43] wire [7:0] pooled_v1_26; // @[DMA.scala:593:43] wire [7:0] pooled_v1_27; // @[DMA.scala:593:43] wire [7:0] pooled_v1_28; // @[DMA.scala:593:43] wire [7:0] pooled_v1_29; // @[DMA.scala:593:43] wire [7:0] pooled_v1_30; // @[DMA.scala:593:43] wire [7:0] pooled_v1_31; // @[DMA.scala:593:43] wire [7:0] pooled_v1_32; // @[DMA.scala:593:43] wire [7:0] pooled_v1_33; // @[DMA.scala:593:43] wire [7:0] pooled_v1_34; // @[DMA.scala:593:43] wire [7:0] pooled_v1_35; // @[DMA.scala:593:43] wire [7:0] pooled_v1_36; // @[DMA.scala:593:43] wire [7:0] pooled_v1_37; // @[DMA.scala:593:43] wire [7:0] pooled_v1_38; // @[DMA.scala:593:43] wire [7:0] pooled_v1_39; // @[DMA.scala:593:43] wire [7:0] pooled_v1_40; // @[DMA.scala:593:43] wire [7:0] pooled_v1_41; // @[DMA.scala:593:43] wire [7:0] pooled_v1_42; // @[DMA.scala:593:43] wire [7:0] pooled_v1_43; // @[DMA.scala:593:43] wire [7:0] pooled_v1_44; // @[DMA.scala:593:43] wire [7:0] pooled_v1_45; // @[DMA.scala:593:43] wire [7:0] pooled_v1_46; // @[DMA.scala:593:43] wire [7:0] pooled_v1_47; // @[DMA.scala:593:43] wire [7:0] pooled_v1_48; // @[DMA.scala:593:43] wire [7:0] pooled_v1_49; // @[DMA.scala:593:43] wire [7:0] pooled_v1_50; // @[DMA.scala:593:43] wire [7:0] pooled_v1_51; // @[DMA.scala:593:43] wire [7:0] pooled_v1_52; // @[DMA.scala:593:43] wire [7:0] pooled_v1_53; // @[DMA.scala:593:43] wire [7:0] pooled_v1_54; // @[DMA.scala:593:43] wire [7:0] pooled_v1_55; // @[DMA.scala:593:43] wire [7:0] pooled_v1_56; // @[DMA.scala:593:43] wire [7:0] pooled_v1_57; // @[DMA.scala:593:43] wire [7:0] pooled_v1_58; // @[DMA.scala:593:43] wire [7:0] pooled_v1_59; // @[DMA.scala:593:43] wire [7:0] pooled_v1_60; // @[DMA.scala:593:43] wire [7:0] pooled_v1_61; // @[DMA.scala:593:43] wire [7:0] pooled_v1_62; // @[DMA.scala:593:43] wire [7:0] pooled_v1_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T = _pooled_v1_WIRE[7:0]; // @[DMA.scala:593:43] assign _pooled_v1_T_1 = _pooled_v1_T; // @[DMA.scala:593:43] assign pooled_v1_0 = _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_2 = _pooled_v1_WIRE[15:8]; // @[DMA.scala:593:43] assign _pooled_v1_T_3 = _pooled_v1_T_2; // @[DMA.scala:593:43] assign pooled_v1_1 = _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_4 = _pooled_v1_WIRE[23:16]; // @[DMA.scala:593:43] assign _pooled_v1_T_5 = _pooled_v1_T_4; // @[DMA.scala:593:43] assign pooled_v1_2 = _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_6 = _pooled_v1_WIRE[31:24]; // @[DMA.scala:593:43] assign _pooled_v1_T_7 = _pooled_v1_T_6; // @[DMA.scala:593:43] assign pooled_v1_3 = _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_8 = _pooled_v1_WIRE[39:32]; // @[DMA.scala:593:43] assign _pooled_v1_T_9 = _pooled_v1_T_8; // @[DMA.scala:593:43] assign pooled_v1_4 = _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_10 = _pooled_v1_WIRE[47:40]; // @[DMA.scala:593:43] assign _pooled_v1_T_11 = _pooled_v1_T_10; // @[DMA.scala:593:43] assign pooled_v1_5 = _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_12 = _pooled_v1_WIRE[55:48]; // @[DMA.scala:593:43] assign _pooled_v1_T_13 = _pooled_v1_T_12; // @[DMA.scala:593:43] assign pooled_v1_6 = _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_14 = _pooled_v1_WIRE[63:56]; // @[DMA.scala:593:43] assign _pooled_v1_T_15 = _pooled_v1_T_14; // @[DMA.scala:593:43] assign pooled_v1_7 = _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_16 = _pooled_v1_WIRE[71:64]; // @[DMA.scala:593:43] assign _pooled_v1_T_17 = _pooled_v1_T_16; // @[DMA.scala:593:43] assign pooled_v1_8 = _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_18 = _pooled_v1_WIRE[79:72]; // @[DMA.scala:593:43] assign _pooled_v1_T_19 = _pooled_v1_T_18; // @[DMA.scala:593:43] assign pooled_v1_9 = _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_20 = _pooled_v1_WIRE[87:80]; // @[DMA.scala:593:43] assign _pooled_v1_T_21 = _pooled_v1_T_20; // @[DMA.scala:593:43] assign pooled_v1_10 = _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_22 = _pooled_v1_WIRE[95:88]; // @[DMA.scala:593:43] assign _pooled_v1_T_23 = _pooled_v1_T_22; // @[DMA.scala:593:43] assign pooled_v1_11 = _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_24 = _pooled_v1_WIRE[103:96]; // @[DMA.scala:593:43] assign _pooled_v1_T_25 = _pooled_v1_T_24; // @[DMA.scala:593:43] assign pooled_v1_12 = _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_26 = _pooled_v1_WIRE[111:104]; // @[DMA.scala:593:43] assign _pooled_v1_T_27 = _pooled_v1_T_26; // @[DMA.scala:593:43] assign pooled_v1_13 = _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_28 = _pooled_v1_WIRE[119:112]; // @[DMA.scala:593:43] assign _pooled_v1_T_29 = _pooled_v1_T_28; // @[DMA.scala:593:43] assign pooled_v1_14 = _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_30 = _pooled_v1_WIRE[127:120]; // @[DMA.scala:593:43] assign _pooled_v1_T_31 = _pooled_v1_T_30; // @[DMA.scala:593:43] assign pooled_v1_15 = _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_32 = _pooled_v1_WIRE[135:128]; // @[DMA.scala:593:43] assign _pooled_v1_T_33 = _pooled_v1_T_32; // @[DMA.scala:593:43] assign pooled_v1_16 = _pooled_v1_T_33; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_34 = _pooled_v1_WIRE[143:136]; // @[DMA.scala:593:43] assign _pooled_v1_T_35 = _pooled_v1_T_34; // @[DMA.scala:593:43] assign pooled_v1_17 = _pooled_v1_T_35; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_36 = _pooled_v1_WIRE[151:144]; // @[DMA.scala:593:43] assign _pooled_v1_T_37 = _pooled_v1_T_36; // @[DMA.scala:593:43] assign pooled_v1_18 = _pooled_v1_T_37; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_38 = _pooled_v1_WIRE[159:152]; // @[DMA.scala:593:43] assign _pooled_v1_T_39 = _pooled_v1_T_38; // @[DMA.scala:593:43] assign pooled_v1_19 = _pooled_v1_T_39; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_40 = _pooled_v1_WIRE[167:160]; // @[DMA.scala:593:43] assign _pooled_v1_T_41 = _pooled_v1_T_40; // @[DMA.scala:593:43] assign pooled_v1_20 = _pooled_v1_T_41; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_42 = _pooled_v1_WIRE[175:168]; // @[DMA.scala:593:43] assign _pooled_v1_T_43 = _pooled_v1_T_42; // @[DMA.scala:593:43] assign pooled_v1_21 = _pooled_v1_T_43; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_44 = _pooled_v1_WIRE[183:176]; // @[DMA.scala:593:43] assign _pooled_v1_T_45 = _pooled_v1_T_44; // @[DMA.scala:593:43] assign pooled_v1_22 = _pooled_v1_T_45; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_46 = _pooled_v1_WIRE[191:184]; // @[DMA.scala:593:43] assign _pooled_v1_T_47 = _pooled_v1_T_46; // @[DMA.scala:593:43] assign pooled_v1_23 = _pooled_v1_T_47; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_48 = _pooled_v1_WIRE[199:192]; // @[DMA.scala:593:43] assign _pooled_v1_T_49 = _pooled_v1_T_48; // @[DMA.scala:593:43] assign pooled_v1_24 = _pooled_v1_T_49; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_50 = _pooled_v1_WIRE[207:200]; // @[DMA.scala:593:43] assign _pooled_v1_T_51 = _pooled_v1_T_50; // @[DMA.scala:593:43] assign pooled_v1_25 = _pooled_v1_T_51; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_52 = _pooled_v1_WIRE[215:208]; // @[DMA.scala:593:43] assign _pooled_v1_T_53 = _pooled_v1_T_52; // @[DMA.scala:593:43] assign pooled_v1_26 = _pooled_v1_T_53; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_54 = _pooled_v1_WIRE[223:216]; // @[DMA.scala:593:43] assign _pooled_v1_T_55 = _pooled_v1_T_54; // @[DMA.scala:593:43] assign pooled_v1_27 = _pooled_v1_T_55; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_56 = _pooled_v1_WIRE[231:224]; // @[DMA.scala:593:43] assign _pooled_v1_T_57 = _pooled_v1_T_56; // @[DMA.scala:593:43] assign pooled_v1_28 = _pooled_v1_T_57; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_58 = _pooled_v1_WIRE[239:232]; // @[DMA.scala:593:43] assign _pooled_v1_T_59 = _pooled_v1_T_58; // @[DMA.scala:593:43] assign pooled_v1_29 = _pooled_v1_T_59; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_60 = _pooled_v1_WIRE[247:240]; // @[DMA.scala:593:43] assign _pooled_v1_T_61 = _pooled_v1_T_60; // @[DMA.scala:593:43] assign pooled_v1_30 = _pooled_v1_T_61; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_62 = _pooled_v1_WIRE[255:248]; // @[DMA.scala:593:43] assign _pooled_v1_T_63 = _pooled_v1_T_62; // @[DMA.scala:593:43] assign pooled_v1_31 = _pooled_v1_T_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_64 = _pooled_v1_WIRE[263:256]; // @[DMA.scala:593:43] assign _pooled_v1_T_65 = _pooled_v1_T_64; // @[DMA.scala:593:43] assign pooled_v1_32 = _pooled_v1_T_65; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_66 = _pooled_v1_WIRE[271:264]; // @[DMA.scala:593:43] assign _pooled_v1_T_67 = _pooled_v1_T_66; // @[DMA.scala:593:43] assign pooled_v1_33 = _pooled_v1_T_67; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_68 = _pooled_v1_WIRE[279:272]; // @[DMA.scala:593:43] assign _pooled_v1_T_69 = _pooled_v1_T_68; // @[DMA.scala:593:43] assign pooled_v1_34 = _pooled_v1_T_69; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_70 = _pooled_v1_WIRE[287:280]; // @[DMA.scala:593:43] assign _pooled_v1_T_71 = _pooled_v1_T_70; // @[DMA.scala:593:43] assign pooled_v1_35 = _pooled_v1_T_71; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_72 = _pooled_v1_WIRE[295:288]; // @[DMA.scala:593:43] assign _pooled_v1_T_73 = _pooled_v1_T_72; // @[DMA.scala:593:43] assign pooled_v1_36 = _pooled_v1_T_73; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_74 = _pooled_v1_WIRE[303:296]; // @[DMA.scala:593:43] assign _pooled_v1_T_75 = _pooled_v1_T_74; // @[DMA.scala:593:43] assign pooled_v1_37 = _pooled_v1_T_75; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_76 = _pooled_v1_WIRE[311:304]; // @[DMA.scala:593:43] assign _pooled_v1_T_77 = _pooled_v1_T_76; // @[DMA.scala:593:43] assign pooled_v1_38 = _pooled_v1_T_77; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_78 = _pooled_v1_WIRE[319:312]; // @[DMA.scala:593:43] assign _pooled_v1_T_79 = _pooled_v1_T_78; // @[DMA.scala:593:43] assign pooled_v1_39 = _pooled_v1_T_79; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_80 = _pooled_v1_WIRE[327:320]; // @[DMA.scala:593:43] assign _pooled_v1_T_81 = _pooled_v1_T_80; // @[DMA.scala:593:43] assign pooled_v1_40 = _pooled_v1_T_81; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_82 = _pooled_v1_WIRE[335:328]; // @[DMA.scala:593:43] assign _pooled_v1_T_83 = _pooled_v1_T_82; // @[DMA.scala:593:43] assign pooled_v1_41 = _pooled_v1_T_83; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_84 = _pooled_v1_WIRE[343:336]; // @[DMA.scala:593:43] assign _pooled_v1_T_85 = _pooled_v1_T_84; // @[DMA.scala:593:43] assign pooled_v1_42 = _pooled_v1_T_85; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_86 = _pooled_v1_WIRE[351:344]; // @[DMA.scala:593:43] assign _pooled_v1_T_87 = _pooled_v1_T_86; // @[DMA.scala:593:43] assign pooled_v1_43 = _pooled_v1_T_87; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_88 = _pooled_v1_WIRE[359:352]; // @[DMA.scala:593:43] assign _pooled_v1_T_89 = _pooled_v1_T_88; // @[DMA.scala:593:43] assign pooled_v1_44 = _pooled_v1_T_89; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_90 = _pooled_v1_WIRE[367:360]; // @[DMA.scala:593:43] assign _pooled_v1_T_91 = _pooled_v1_T_90; // @[DMA.scala:593:43] assign pooled_v1_45 = _pooled_v1_T_91; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_92 = _pooled_v1_WIRE[375:368]; // @[DMA.scala:593:43] assign _pooled_v1_T_93 = _pooled_v1_T_92; // @[DMA.scala:593:43] assign pooled_v1_46 = _pooled_v1_T_93; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_94 = _pooled_v1_WIRE[383:376]; // @[DMA.scala:593:43] assign _pooled_v1_T_95 = _pooled_v1_T_94; // @[DMA.scala:593:43] assign pooled_v1_47 = _pooled_v1_T_95; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_96 = _pooled_v1_WIRE[391:384]; // @[DMA.scala:593:43] assign _pooled_v1_T_97 = _pooled_v1_T_96; // @[DMA.scala:593:43] assign pooled_v1_48 = _pooled_v1_T_97; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_98 = _pooled_v1_WIRE[399:392]; // @[DMA.scala:593:43] assign _pooled_v1_T_99 = _pooled_v1_T_98; // @[DMA.scala:593:43] assign pooled_v1_49 = _pooled_v1_T_99; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_100 = _pooled_v1_WIRE[407:400]; // @[DMA.scala:593:43] assign _pooled_v1_T_101 = _pooled_v1_T_100; // @[DMA.scala:593:43] assign pooled_v1_50 = _pooled_v1_T_101; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_102 = _pooled_v1_WIRE[415:408]; // @[DMA.scala:593:43] assign _pooled_v1_T_103 = _pooled_v1_T_102; // @[DMA.scala:593:43] assign pooled_v1_51 = _pooled_v1_T_103; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_104 = _pooled_v1_WIRE[423:416]; // @[DMA.scala:593:43] assign _pooled_v1_T_105 = _pooled_v1_T_104; // @[DMA.scala:593:43] assign pooled_v1_52 = _pooled_v1_T_105; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_106 = _pooled_v1_WIRE[431:424]; // @[DMA.scala:593:43] assign _pooled_v1_T_107 = _pooled_v1_T_106; // @[DMA.scala:593:43] assign pooled_v1_53 = _pooled_v1_T_107; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_108 = _pooled_v1_WIRE[439:432]; // @[DMA.scala:593:43] assign _pooled_v1_T_109 = _pooled_v1_T_108; // @[DMA.scala:593:43] assign pooled_v1_54 = _pooled_v1_T_109; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_110 = _pooled_v1_WIRE[447:440]; // @[DMA.scala:593:43] assign _pooled_v1_T_111 = _pooled_v1_T_110; // @[DMA.scala:593:43] assign pooled_v1_55 = _pooled_v1_T_111; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_112 = _pooled_v1_WIRE[455:448]; // @[DMA.scala:593:43] assign _pooled_v1_T_113 = _pooled_v1_T_112; // @[DMA.scala:593:43] assign pooled_v1_56 = _pooled_v1_T_113; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_114 = _pooled_v1_WIRE[463:456]; // @[DMA.scala:593:43] assign _pooled_v1_T_115 = _pooled_v1_T_114; // @[DMA.scala:593:43] assign pooled_v1_57 = _pooled_v1_T_115; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_116 = _pooled_v1_WIRE[471:464]; // @[DMA.scala:593:43] assign _pooled_v1_T_117 = _pooled_v1_T_116; // @[DMA.scala:593:43] assign pooled_v1_58 = _pooled_v1_T_117; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_118 = _pooled_v1_WIRE[479:472]; // @[DMA.scala:593:43] assign _pooled_v1_T_119 = _pooled_v1_T_118; // @[DMA.scala:593:43] assign pooled_v1_59 = _pooled_v1_T_119; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_120 = _pooled_v1_WIRE[487:480]; // @[DMA.scala:593:43] assign _pooled_v1_T_121 = _pooled_v1_T_120; // @[DMA.scala:593:43] assign pooled_v1_60 = _pooled_v1_T_121; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_122 = _pooled_v1_WIRE[495:488]; // @[DMA.scala:593:43] assign _pooled_v1_T_123 = _pooled_v1_T_122; // @[DMA.scala:593:43] assign pooled_v1_61 = _pooled_v1_T_123; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_124 = _pooled_v1_WIRE[503:496]; // @[DMA.scala:593:43] assign _pooled_v1_T_125 = _pooled_v1_T_124; // @[DMA.scala:593:43] assign pooled_v1_62 = _pooled_v1_T_125; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_126 = _pooled_v1_WIRE[511:504]; // @[DMA.scala:593:43] assign _pooled_v1_T_127 = _pooled_v1_T_126; // @[DMA.scala:593:43] assign pooled_v1_63 = _pooled_v1_T_127; // @[DMA.scala:593:43] wire [7:0] _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_31; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_33; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_35; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_16 = pooled_v2_16; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_37; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_17 = pooled_v2_17; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_39; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_18 = pooled_v2_18; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_41; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_19 = pooled_v2_19; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_43; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_20 = pooled_v2_20; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_45; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_21 = pooled_v2_21; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_47; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_22 = pooled_v2_22; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_49; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_23 = pooled_v2_23; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_51; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_24 = pooled_v2_24; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_53; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_25 = pooled_v2_25; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_55; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_26 = pooled_v2_26; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_57; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_27 = pooled_v2_27; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_59; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_28 = pooled_v2_28; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_61; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_29 = pooled_v2_29; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_63; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_30 = pooled_v2_30; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_65; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_31 = pooled_v2_31; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_67; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_32 = pooled_v2_32; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_69; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_33 = pooled_v2_33; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_71; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_34 = pooled_v2_34; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_73; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_35 = pooled_v2_35; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_75; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_36 = pooled_v2_36; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_77; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_37 = pooled_v2_37; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_79; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_38 = pooled_v2_38; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_81; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_39 = pooled_v2_39; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_83; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_40 = pooled_v2_40; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_85; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_41 = pooled_v2_41; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_87; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_42 = pooled_v2_42; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_89; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_43 = pooled_v2_43; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_91; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_44 = pooled_v2_44; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_93; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_45 = pooled_v2_45; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_95; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_46 = pooled_v2_46; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_97; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_47 = pooled_v2_47; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_99; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_48 = pooled_v2_48; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_101; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_49 = pooled_v2_49; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_103; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_50 = pooled_v2_50; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_105; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_51 = pooled_v2_51; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_107; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_52 = pooled_v2_52; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_109; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_53 = pooled_v2_53; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_111; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_54 = pooled_v2_54; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_113; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_55 = pooled_v2_55; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_115; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_56 = pooled_v2_56; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_117; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_57 = pooled_v2_57; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_119; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_58 = pooled_v2_58; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_121; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_59 = pooled_v2_59; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_123; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_60 = pooled_v2_60; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_125; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_61 = pooled_v2_61; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_127; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_62 = pooled_v2_62; // @[DMA.scala:594:44, :596:16] wire [7:0] pooled_v2_0; // @[DMA.scala:594:44] wire [7:0] pooled_v2_1; // @[DMA.scala:594:44] wire [7:0] pooled_v2_2; // @[DMA.scala:594:44] wire [7:0] pooled_v2_3; // @[DMA.scala:594:44] wire [7:0] pooled_v2_4; // @[DMA.scala:594:44] wire [7:0] pooled_v2_5; // @[DMA.scala:594:44] wire [7:0] pooled_v2_6; // @[DMA.scala:594:44] wire [7:0] pooled_v2_7; // @[DMA.scala:594:44] wire [7:0] pooled_v2_8; // @[DMA.scala:594:44] wire [7:0] pooled_v2_9; // @[DMA.scala:594:44] wire [7:0] pooled_v2_10; // @[DMA.scala:594:44] wire [7:0] pooled_v2_11; // @[DMA.scala:594:44] wire [7:0] pooled_v2_12; // @[DMA.scala:594:44] wire [7:0] pooled_v2_13; // @[DMA.scala:594:44] wire [7:0] pooled_v2_14; // @[DMA.scala:594:44] wire [7:0] pooled_v2_15; // @[DMA.scala:594:44] wire [7:0] pooled_v2_63; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_63 = pooled_v2_63; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T = _pooled_v2_WIRE[7:0]; // @[DMA.scala:594:44] assign _pooled_v2_T_1 = _pooled_v2_T; // @[DMA.scala:594:44] assign pooled_v2_0 = _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_2 = _pooled_v2_WIRE[15:8]; // @[DMA.scala:594:44] assign _pooled_v2_T_3 = _pooled_v2_T_2; // @[DMA.scala:594:44] assign pooled_v2_1 = _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_4 = _pooled_v2_WIRE[23:16]; // @[DMA.scala:594:44] assign _pooled_v2_T_5 = _pooled_v2_T_4; // @[DMA.scala:594:44] assign pooled_v2_2 = _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_6 = _pooled_v2_WIRE[31:24]; // @[DMA.scala:594:44] assign _pooled_v2_T_7 = _pooled_v2_T_6; // @[DMA.scala:594:44] assign pooled_v2_3 = _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_8 = _pooled_v2_WIRE[39:32]; // @[DMA.scala:594:44] assign _pooled_v2_T_9 = _pooled_v2_T_8; // @[DMA.scala:594:44] assign pooled_v2_4 = _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_10 = _pooled_v2_WIRE[47:40]; // @[DMA.scala:594:44] assign _pooled_v2_T_11 = _pooled_v2_T_10; // @[DMA.scala:594:44] assign pooled_v2_5 = _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_12 = _pooled_v2_WIRE[55:48]; // @[DMA.scala:594:44] assign _pooled_v2_T_13 = _pooled_v2_T_12; // @[DMA.scala:594:44] assign pooled_v2_6 = _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_14 = _pooled_v2_WIRE[63:56]; // @[DMA.scala:594:44] assign _pooled_v2_T_15 = _pooled_v2_T_14; // @[DMA.scala:594:44] assign pooled_v2_7 = _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_16 = _pooled_v2_WIRE[71:64]; // @[DMA.scala:594:44] assign _pooled_v2_T_17 = _pooled_v2_T_16; // @[DMA.scala:594:44] assign pooled_v2_8 = _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_18 = _pooled_v2_WIRE[79:72]; // @[DMA.scala:594:44] assign _pooled_v2_T_19 = _pooled_v2_T_18; // @[DMA.scala:594:44] assign pooled_v2_9 = _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_20 = _pooled_v2_WIRE[87:80]; // @[DMA.scala:594:44] assign _pooled_v2_T_21 = _pooled_v2_T_20; // @[DMA.scala:594:44] assign pooled_v2_10 = _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_22 = _pooled_v2_WIRE[95:88]; // @[DMA.scala:594:44] assign _pooled_v2_T_23 = _pooled_v2_T_22; // @[DMA.scala:594:44] assign pooled_v2_11 = _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_24 = _pooled_v2_WIRE[103:96]; // @[DMA.scala:594:44] assign _pooled_v2_T_25 = _pooled_v2_T_24; // @[DMA.scala:594:44] assign pooled_v2_12 = _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_26 = _pooled_v2_WIRE[111:104]; // @[DMA.scala:594:44] assign _pooled_v2_T_27 = _pooled_v2_T_26; // @[DMA.scala:594:44] assign pooled_v2_13 = _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_28 = _pooled_v2_WIRE[119:112]; // @[DMA.scala:594:44] assign _pooled_v2_T_29 = _pooled_v2_T_28; // @[DMA.scala:594:44] assign pooled_v2_14 = _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_30 = _pooled_v2_WIRE[127:120]; // @[DMA.scala:594:44] assign _pooled_v2_T_31 = _pooled_v2_T_30; // @[DMA.scala:594:44] assign pooled_v2_15 = _pooled_v2_T_31; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_32 = _pooled_v2_WIRE[135:128]; // @[DMA.scala:594:44] assign _pooled_v2_T_33 = _pooled_v2_T_32; // @[DMA.scala:594:44] assign pooled_v2_16 = _pooled_v2_T_33; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_34 = _pooled_v2_WIRE[143:136]; // @[DMA.scala:594:44] assign _pooled_v2_T_35 = _pooled_v2_T_34; // @[DMA.scala:594:44] assign pooled_v2_17 = _pooled_v2_T_35; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_36 = _pooled_v2_WIRE[151:144]; // @[DMA.scala:594:44] assign _pooled_v2_T_37 = _pooled_v2_T_36; // @[DMA.scala:594:44] assign pooled_v2_18 = _pooled_v2_T_37; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_38 = _pooled_v2_WIRE[159:152]; // @[DMA.scala:594:44] assign _pooled_v2_T_39 = _pooled_v2_T_38; // @[DMA.scala:594:44] assign pooled_v2_19 = _pooled_v2_T_39; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_40 = _pooled_v2_WIRE[167:160]; // @[DMA.scala:594:44] assign _pooled_v2_T_41 = _pooled_v2_T_40; // @[DMA.scala:594:44] assign pooled_v2_20 = _pooled_v2_T_41; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_42 = _pooled_v2_WIRE[175:168]; // @[DMA.scala:594:44] assign _pooled_v2_T_43 = _pooled_v2_T_42; // @[DMA.scala:594:44] assign pooled_v2_21 = _pooled_v2_T_43; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_44 = _pooled_v2_WIRE[183:176]; // @[DMA.scala:594:44] assign _pooled_v2_T_45 = _pooled_v2_T_44; // @[DMA.scala:594:44] assign pooled_v2_22 = _pooled_v2_T_45; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_46 = _pooled_v2_WIRE[191:184]; // @[DMA.scala:594:44] assign _pooled_v2_T_47 = _pooled_v2_T_46; // @[DMA.scala:594:44] assign pooled_v2_23 = _pooled_v2_T_47; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_48 = _pooled_v2_WIRE[199:192]; // @[DMA.scala:594:44] assign _pooled_v2_T_49 = _pooled_v2_T_48; // @[DMA.scala:594:44] assign pooled_v2_24 = _pooled_v2_T_49; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_50 = _pooled_v2_WIRE[207:200]; // @[DMA.scala:594:44] assign _pooled_v2_T_51 = _pooled_v2_T_50; // @[DMA.scala:594:44] assign pooled_v2_25 = _pooled_v2_T_51; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_52 = _pooled_v2_WIRE[215:208]; // @[DMA.scala:594:44] assign _pooled_v2_T_53 = _pooled_v2_T_52; // @[DMA.scala:594:44] assign pooled_v2_26 = _pooled_v2_T_53; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_54 = _pooled_v2_WIRE[223:216]; // @[DMA.scala:594:44] assign _pooled_v2_T_55 = _pooled_v2_T_54; // @[DMA.scala:594:44] assign pooled_v2_27 = _pooled_v2_T_55; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_56 = _pooled_v2_WIRE[231:224]; // @[DMA.scala:594:44] assign _pooled_v2_T_57 = _pooled_v2_T_56; // @[DMA.scala:594:44] assign pooled_v2_28 = _pooled_v2_T_57; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_58 = _pooled_v2_WIRE[239:232]; // @[DMA.scala:594:44] assign _pooled_v2_T_59 = _pooled_v2_T_58; // @[DMA.scala:594:44] assign pooled_v2_29 = _pooled_v2_T_59; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_60 = _pooled_v2_WIRE[247:240]; // @[DMA.scala:594:44] assign _pooled_v2_T_61 = _pooled_v2_T_60; // @[DMA.scala:594:44] assign pooled_v2_30 = _pooled_v2_T_61; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_62 = _pooled_v2_WIRE[255:248]; // @[DMA.scala:594:44] assign _pooled_v2_T_63 = _pooled_v2_T_62; // @[DMA.scala:594:44] assign pooled_v2_31 = _pooled_v2_T_63; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_64 = _pooled_v2_WIRE[263:256]; // @[DMA.scala:594:44] assign _pooled_v2_T_65 = _pooled_v2_T_64; // @[DMA.scala:594:44] assign pooled_v2_32 = _pooled_v2_T_65; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_66 = _pooled_v2_WIRE[271:264]; // @[DMA.scala:594:44] assign _pooled_v2_T_67 = _pooled_v2_T_66; // @[DMA.scala:594:44] assign pooled_v2_33 = _pooled_v2_T_67; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_68 = _pooled_v2_WIRE[279:272]; // @[DMA.scala:594:44] assign _pooled_v2_T_69 = _pooled_v2_T_68; // @[DMA.scala:594:44] assign pooled_v2_34 = _pooled_v2_T_69; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_70 = _pooled_v2_WIRE[287:280]; // @[DMA.scala:594:44] assign _pooled_v2_T_71 = _pooled_v2_T_70; // @[DMA.scala:594:44] assign pooled_v2_35 = _pooled_v2_T_71; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_72 = _pooled_v2_WIRE[295:288]; // @[DMA.scala:594:44] assign _pooled_v2_T_73 = _pooled_v2_T_72; // @[DMA.scala:594:44] assign pooled_v2_36 = _pooled_v2_T_73; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_74 = _pooled_v2_WIRE[303:296]; // @[DMA.scala:594:44] assign _pooled_v2_T_75 = _pooled_v2_T_74; // @[DMA.scala:594:44] assign pooled_v2_37 = _pooled_v2_T_75; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_76 = _pooled_v2_WIRE[311:304]; // @[DMA.scala:594:44] assign _pooled_v2_T_77 = _pooled_v2_T_76; // @[DMA.scala:594:44] assign pooled_v2_38 = _pooled_v2_T_77; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_78 = _pooled_v2_WIRE[319:312]; // @[DMA.scala:594:44] assign _pooled_v2_T_79 = _pooled_v2_T_78; // @[DMA.scala:594:44] assign pooled_v2_39 = _pooled_v2_T_79; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_80 = _pooled_v2_WIRE[327:320]; // @[DMA.scala:594:44] assign _pooled_v2_T_81 = _pooled_v2_T_80; // @[DMA.scala:594:44] assign pooled_v2_40 = _pooled_v2_T_81; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_82 = _pooled_v2_WIRE[335:328]; // @[DMA.scala:594:44] assign _pooled_v2_T_83 = _pooled_v2_T_82; // @[DMA.scala:594:44] assign pooled_v2_41 = _pooled_v2_T_83; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_84 = _pooled_v2_WIRE[343:336]; // @[DMA.scala:594:44] assign _pooled_v2_T_85 = _pooled_v2_T_84; // @[DMA.scala:594:44] assign pooled_v2_42 = _pooled_v2_T_85; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_86 = _pooled_v2_WIRE[351:344]; // @[DMA.scala:594:44] assign _pooled_v2_T_87 = _pooled_v2_T_86; // @[DMA.scala:594:44] assign pooled_v2_43 = _pooled_v2_T_87; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_88 = _pooled_v2_WIRE[359:352]; // @[DMA.scala:594:44] assign _pooled_v2_T_89 = _pooled_v2_T_88; // @[DMA.scala:594:44] assign pooled_v2_44 = _pooled_v2_T_89; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_90 = _pooled_v2_WIRE[367:360]; // @[DMA.scala:594:44] assign _pooled_v2_T_91 = _pooled_v2_T_90; // @[DMA.scala:594:44] assign pooled_v2_45 = _pooled_v2_T_91; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_92 = _pooled_v2_WIRE[375:368]; // @[DMA.scala:594:44] assign _pooled_v2_T_93 = _pooled_v2_T_92; // @[DMA.scala:594:44] assign pooled_v2_46 = _pooled_v2_T_93; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_94 = _pooled_v2_WIRE[383:376]; // @[DMA.scala:594:44] assign _pooled_v2_T_95 = _pooled_v2_T_94; // @[DMA.scala:594:44] assign pooled_v2_47 = _pooled_v2_T_95; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_96 = _pooled_v2_WIRE[391:384]; // @[DMA.scala:594:44] assign _pooled_v2_T_97 = _pooled_v2_T_96; // @[DMA.scala:594:44] assign pooled_v2_48 = _pooled_v2_T_97; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_98 = _pooled_v2_WIRE[399:392]; // @[DMA.scala:594:44] assign _pooled_v2_T_99 = _pooled_v2_T_98; // @[DMA.scala:594:44] assign pooled_v2_49 = _pooled_v2_T_99; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_100 = _pooled_v2_WIRE[407:400]; // @[DMA.scala:594:44] assign _pooled_v2_T_101 = _pooled_v2_T_100; // @[DMA.scala:594:44] assign pooled_v2_50 = _pooled_v2_T_101; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_102 = _pooled_v2_WIRE[415:408]; // @[DMA.scala:594:44] assign _pooled_v2_T_103 = _pooled_v2_T_102; // @[DMA.scala:594:44] assign pooled_v2_51 = _pooled_v2_T_103; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_104 = _pooled_v2_WIRE[423:416]; // @[DMA.scala:594:44] assign _pooled_v2_T_105 = _pooled_v2_T_104; // @[DMA.scala:594:44] assign pooled_v2_52 = _pooled_v2_T_105; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_106 = _pooled_v2_WIRE[431:424]; // @[DMA.scala:594:44] assign _pooled_v2_T_107 = _pooled_v2_T_106; // @[DMA.scala:594:44] assign pooled_v2_53 = _pooled_v2_T_107; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_108 = _pooled_v2_WIRE[439:432]; // @[DMA.scala:594:44] assign _pooled_v2_T_109 = _pooled_v2_T_108; // @[DMA.scala:594:44] assign pooled_v2_54 = _pooled_v2_T_109; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_110 = _pooled_v2_WIRE[447:440]; // @[DMA.scala:594:44] assign _pooled_v2_T_111 = _pooled_v2_T_110; // @[DMA.scala:594:44] assign pooled_v2_55 = _pooled_v2_T_111; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_112 = _pooled_v2_WIRE[455:448]; // @[DMA.scala:594:44] assign _pooled_v2_T_113 = _pooled_v2_T_112; // @[DMA.scala:594:44] assign pooled_v2_56 = _pooled_v2_T_113; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_114 = _pooled_v2_WIRE[463:456]; // @[DMA.scala:594:44] assign _pooled_v2_T_115 = _pooled_v2_T_114; // @[DMA.scala:594:44] assign pooled_v2_57 = _pooled_v2_T_115; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_116 = _pooled_v2_WIRE[471:464]; // @[DMA.scala:594:44] assign _pooled_v2_T_117 = _pooled_v2_T_116; // @[DMA.scala:594:44] assign pooled_v2_58 = _pooled_v2_T_117; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_118 = _pooled_v2_WIRE[479:472]; // @[DMA.scala:594:44] assign _pooled_v2_T_119 = _pooled_v2_T_118; // @[DMA.scala:594:44] assign pooled_v2_59 = _pooled_v2_T_119; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_120 = _pooled_v2_WIRE[487:480]; // @[DMA.scala:594:44] assign _pooled_v2_T_121 = _pooled_v2_T_120; // @[DMA.scala:594:44] assign pooled_v2_60 = _pooled_v2_T_121; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_122 = _pooled_v2_WIRE[495:488]; // @[DMA.scala:594:44] assign _pooled_v2_T_123 = _pooled_v2_T_122; // @[DMA.scala:594:44] assign pooled_v2_61 = _pooled_v2_T_123; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_124 = _pooled_v2_WIRE[503:496]; // @[DMA.scala:594:44] assign _pooled_v2_T_125 = _pooled_v2_T_124; // @[DMA.scala:594:44] assign pooled_v2_62 = _pooled_v2_T_125; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_126 = _pooled_v2_WIRE[511:504]; // @[DMA.scala:594:44] assign _pooled_v2_T_127 = _pooled_v2_T_126; // @[DMA.scala:594:44] assign pooled_v2_63 = _pooled_v2_T_127; // @[DMA.scala:594:44] wire _pooled_T = $signed(pooled_v1_0) > $signed(pooled_v2_0); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_1 = _pooled_T ? pooled_v1_0 : pooled_v2_0; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_0 = _pooled_T_1; // @[Util.scala:105:8] wire _pooled_T_2 = $signed(pooled_v1_1) > $signed(pooled_v2_1); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_3 = _pooled_T_2 ? pooled_v1_1 : pooled_v2_1; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_1 = _pooled_T_3; // @[Util.scala:105:8] wire _pooled_T_4 = $signed(pooled_v1_2) > $signed(pooled_v2_2); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_5 = _pooled_T_4 ? pooled_v1_2 : pooled_v2_2; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_2 = _pooled_T_5; // @[Util.scala:105:8] wire _pooled_T_6 = $signed(pooled_v1_3) > $signed(pooled_v2_3); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_7 = _pooled_T_6 ? pooled_v1_3 : pooled_v2_3; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_3 = _pooled_T_7; // @[Util.scala:105:8] wire _pooled_T_8 = $signed(pooled_v1_4) > $signed(pooled_v2_4); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_9 = _pooled_T_8 ? pooled_v1_4 : pooled_v2_4; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_4 = _pooled_T_9; // @[Util.scala:105:8] wire _pooled_T_10 = $signed(pooled_v1_5) > $signed(pooled_v2_5); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_11 = _pooled_T_10 ? pooled_v1_5 : pooled_v2_5; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_5 = _pooled_T_11; // @[Util.scala:105:8] wire _pooled_T_12 = $signed(pooled_v1_6) > $signed(pooled_v2_6); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_13 = _pooled_T_12 ? pooled_v1_6 : pooled_v2_6; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_6 = _pooled_T_13; // @[Util.scala:105:8] wire _pooled_T_14 = $signed(pooled_v1_7) > $signed(pooled_v2_7); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_15 = _pooled_T_14 ? pooled_v1_7 : pooled_v2_7; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_7 = _pooled_T_15; // @[Util.scala:105:8] wire _pooled_T_16 = $signed(pooled_v1_8) > $signed(pooled_v2_8); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_17 = _pooled_T_16 ? pooled_v1_8 : pooled_v2_8; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_8 = _pooled_T_17; // @[Util.scala:105:8] wire _pooled_T_18 = $signed(pooled_v1_9) > $signed(pooled_v2_9); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_19 = _pooled_T_18 ? pooled_v1_9 : pooled_v2_9; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_9 = _pooled_T_19; // @[Util.scala:105:8] wire _pooled_T_20 = $signed(pooled_v1_10) > $signed(pooled_v2_10); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_21 = _pooled_T_20 ? pooled_v1_10 : pooled_v2_10; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_10 = _pooled_T_21; // @[Util.scala:105:8] wire _pooled_T_22 = $signed(pooled_v1_11) > $signed(pooled_v2_11); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_23 = _pooled_T_22 ? pooled_v1_11 : pooled_v2_11; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_11 = _pooled_T_23; // @[Util.scala:105:8] wire _pooled_T_24 = $signed(pooled_v1_12) > $signed(pooled_v2_12); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_25 = _pooled_T_24 ? pooled_v1_12 : pooled_v2_12; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_12 = _pooled_T_25; // @[Util.scala:105:8] wire _pooled_T_26 = $signed(pooled_v1_13) > $signed(pooled_v2_13); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_27 = _pooled_T_26 ? pooled_v1_13 : pooled_v2_13; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_13 = _pooled_T_27; // @[Util.scala:105:8] wire _pooled_T_28 = $signed(pooled_v1_14) > $signed(pooled_v2_14); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_29 = _pooled_T_28 ? pooled_v1_14 : pooled_v2_14; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_14 = _pooled_T_29; // @[Util.scala:105:8] wire _pooled_T_30 = $signed(pooled_v1_15) > $signed(pooled_v2_15); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_31 = _pooled_T_30 ? pooled_v1_15 : pooled_v2_15; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_15 = _pooled_T_31; // @[Util.scala:105:8] wire [7:0] _pooled_T_32 = _pooled_WIRE_0; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_33 = _pooled_WIRE_1; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_34 = _pooled_WIRE_2; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_35 = _pooled_WIRE_3; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_36 = _pooled_WIRE_4; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_37 = _pooled_WIRE_5; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_38 = _pooled_WIRE_6; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_39 = _pooled_WIRE_7; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_40 = _pooled_WIRE_8; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_41 = _pooled_WIRE_9; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_42 = _pooled_WIRE_10; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_43 = _pooled_WIRE_11; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_44 = _pooled_WIRE_12; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_45 = _pooled_WIRE_13; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_46 = _pooled_WIRE_14; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_47 = _pooled_WIRE_15; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_48 = _pooled_WIRE_16; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_49 = _pooled_WIRE_17; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_50 = _pooled_WIRE_18; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_51 = _pooled_WIRE_19; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_52 = _pooled_WIRE_20; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_53 = _pooled_WIRE_21; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_54 = _pooled_WIRE_22; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_55 = _pooled_WIRE_23; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_56 = _pooled_WIRE_24; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_57 = _pooled_WIRE_25; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_58 = _pooled_WIRE_26; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_59 = _pooled_WIRE_27; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_60 = _pooled_WIRE_28; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_61 = _pooled_WIRE_29; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_62 = _pooled_WIRE_30; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_63 = _pooled_WIRE_31; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_64 = _pooled_WIRE_32; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_65 = _pooled_WIRE_33; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_66 = _pooled_WIRE_34; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_67 = _pooled_WIRE_35; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_68 = _pooled_WIRE_36; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_69 = _pooled_WIRE_37; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_70 = _pooled_WIRE_38; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_71 = _pooled_WIRE_39; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_72 = _pooled_WIRE_40; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_73 = _pooled_WIRE_41; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_74 = _pooled_WIRE_42; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_75 = _pooled_WIRE_43; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_76 = _pooled_WIRE_44; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_77 = _pooled_WIRE_45; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_78 = _pooled_WIRE_46; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_79 = _pooled_WIRE_47; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_80 = _pooled_WIRE_48; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_81 = _pooled_WIRE_49; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_82 = _pooled_WIRE_50; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_83 = _pooled_WIRE_51; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_84 = _pooled_WIRE_52; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_85 = _pooled_WIRE_53; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_86 = _pooled_WIRE_54; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_87 = _pooled_WIRE_55; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_88 = _pooled_WIRE_56; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_89 = _pooled_WIRE_57; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_90 = _pooled_WIRE_58; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_91 = _pooled_WIRE_59; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_92 = _pooled_WIRE_60; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_93 = _pooled_WIRE_61; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_94 = _pooled_WIRE_62; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_95 = _pooled_WIRE_63; // @[DMA.scala:596:{16,97}] wire [15:0] pooled_lo_lo_lo_lo_lo = {_pooled_T_33, _pooled_T_32}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_lo_hi = {_pooled_T_35, _pooled_T_34}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_lo_lo = {pooled_lo_lo_lo_lo_hi, pooled_lo_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_hi_lo = {_pooled_T_37, _pooled_T_36}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_hi_hi = {_pooled_T_39, _pooled_T_38}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_lo_hi = {pooled_lo_lo_lo_hi_hi, pooled_lo_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_lo_lo = {pooled_lo_lo_lo_hi, pooled_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_lo_lo = {_pooled_T_41, _pooled_T_40}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_lo_hi = {_pooled_T_43, _pooled_T_42}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_hi_lo = {pooled_lo_lo_hi_lo_hi, pooled_lo_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_hi_lo = {_pooled_T_45, _pooled_T_44}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_hi_hi = {_pooled_T_47, _pooled_T_46}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_hi_hi = {pooled_lo_lo_hi_hi_hi, pooled_lo_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_lo_hi = {pooled_lo_lo_hi_hi, pooled_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_lo_lo = {pooled_lo_lo_hi, pooled_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_lo_lo = {_pooled_T_49, _pooled_T_48}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_lo_hi = {_pooled_T_51, _pooled_T_50}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_lo_lo = {pooled_lo_hi_lo_lo_hi, pooled_lo_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_hi_lo = {_pooled_T_53, _pooled_T_52}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_hi_hi = {_pooled_T_55, _pooled_T_54}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_lo_hi = {pooled_lo_hi_lo_hi_hi, pooled_lo_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_hi_lo = {pooled_lo_hi_lo_hi, pooled_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_lo_lo = {_pooled_T_57, _pooled_T_56}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_lo_hi = {_pooled_T_59, _pooled_T_58}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_hi_lo = {pooled_lo_hi_hi_lo_hi, pooled_lo_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_hi_lo = {_pooled_T_61, _pooled_T_60}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_hi_hi = {_pooled_T_63, _pooled_T_62}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_hi_hi = {pooled_lo_hi_hi_hi_hi, pooled_lo_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_hi_hi = {pooled_lo_hi_hi_hi, pooled_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_lo_hi = {pooled_lo_hi_hi, pooled_lo_hi_lo}; // @[DMA.scala:596:97] wire [255:0] pooled_lo = {pooled_lo_hi, pooled_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_lo_lo = {_pooled_T_65, _pooled_T_64}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_lo_hi = {_pooled_T_67, _pooled_T_66}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_lo_lo = {pooled_hi_lo_lo_lo_hi, pooled_hi_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_hi_lo = {_pooled_T_69, _pooled_T_68}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_hi_hi = {_pooled_T_71, _pooled_T_70}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_lo_hi = {pooled_hi_lo_lo_hi_hi, pooled_hi_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_lo_lo = {pooled_hi_lo_lo_hi, pooled_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_lo_lo = {_pooled_T_73, _pooled_T_72}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_lo_hi = {_pooled_T_75, _pooled_T_74}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_hi_lo = {pooled_hi_lo_hi_lo_hi, pooled_hi_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_hi_lo = {_pooled_T_77, _pooled_T_76}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_hi_hi = {_pooled_T_79, _pooled_T_78}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_hi_hi = {pooled_hi_lo_hi_hi_hi, pooled_hi_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_lo_hi = {pooled_hi_lo_hi_hi, pooled_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_hi_lo = {pooled_hi_lo_hi, pooled_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_lo_lo = {_pooled_T_81, _pooled_T_80}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_lo_hi = {_pooled_T_83, _pooled_T_82}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_lo_lo = {pooled_hi_hi_lo_lo_hi, pooled_hi_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_hi_lo = {_pooled_T_85, _pooled_T_84}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_hi_hi = {_pooled_T_87, _pooled_T_86}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_lo_hi = {pooled_hi_hi_lo_hi_hi, pooled_hi_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_hi_lo = {pooled_hi_hi_lo_hi, pooled_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_lo_lo = {_pooled_T_89, _pooled_T_88}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_lo_hi = {_pooled_T_91, _pooled_T_90}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_hi_lo = {pooled_hi_hi_hi_lo_hi, pooled_hi_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_hi_lo = {_pooled_T_93, _pooled_T_92}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_hi_hi = {_pooled_T_95, _pooled_T_94}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_hi_hi = {pooled_hi_hi_hi_hi_hi, pooled_hi_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_hi_hi = {pooled_hi_hi_hi_hi, pooled_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_hi_hi = {pooled_hi_hi_hi, pooled_hi_hi_lo}; // @[DMA.scala:596:97] wire [255:0] pooled_hi = {pooled_hi_hi, pooled_hi_lo}; // @[DMA.scala:596:97] wire [511:0] pooled = {pooled_hi, pooled_lo}; // @[DMA.scala:596:97] wire [12:0] _req_len_T = {1'h0, io_req_bits_block_0, 4'h0}; // @[DMA.scala:360:9, :600:36] wire [13:0] _req_len_T_1 = {1'h0, _req_len_T} + {7'h0, io_req_bits_len_0}; // @[DMA.scala:360:9, :600:{36,58}] wire [12:0] _req_len_T_2 = _req_len_T_1[12:0]; // @[DMA.scala:600:58] wire [511:0] _data_single_block_T = io_req_bits_pool_en_0 ? pooled : io_req_bits_data_0; // @[DMA.scala:360:9, :596:97, :602:31] wire [1:0] _state_T = {1'h0, io_req_bits_store_en_0}; // @[DMA.scala:360:9, :607:19]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied	module IssueSlot( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module TageBranchPredictorBank_3 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire f3_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} node _T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node lo = cat(_T_1, _T) node hi = cat(_T_3, _T_2) node _T_4 = cat(hi, lo) node lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _T_5 = cat(hi_1, lo_1) node lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _T_6 = cat(hi_2, lo_2) node lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _T_7 = cat(hi_3, lo_3) node _T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node lo_4 = cat(_T_9, _T_8) node hi_4 = cat(_T_11, _T_10) node _T_12 = cat(hi_4, lo_4) node lo_5 = cat(_T_5, _T_4) node hi_hi = cat(_T_12, _T_7) node hi_5 = cat(hi_hi, _T_6) node _T_13 = cat(hi_5, lo_5) inst tt_0_1 of TageTable_18 connect tt_0_1.clock, clock connect tt_0_1.reset, reset reg t_io_f1_req_valid_REG : UInt<1>, clock connect t_io_f1_req_valid_REG, io.f0_valid connect tt_0_1.io.f1_req_valid, t_io_f1_req_valid_REG reg t_io_f1_req_pc_REG : UInt, clock connect t_io_f1_req_pc_REG, io.f0_pc connect tt_0_1.io.f1_req_pc, t_io_f1_req_pc_REG connect tt_0_1.io.f1_req_ghist, io.f1_ghist inst tt_1_1 of TageTable_19 connect tt_1_1.clock, clock connect tt_1_1.reset, reset reg t_io_f1_req_valid_REG_1 : UInt<1>, clock connect t_io_f1_req_valid_REG_1, io.f0_valid connect tt_1_1.io.f1_req_valid, t_io_f1_req_valid_REG_1 reg t_io_f1_req_pc_REG_1 : UInt, clock connect t_io_f1_req_pc_REG_1, io.f0_pc connect tt_1_1.io.f1_req_pc, t_io_f1_req_pc_REG_1 connect tt_1_1.io.f1_req_ghist, io.f1_ghist inst tt_2_1 of TageTable_20 connect tt_2_1.clock, clock connect tt_2_1.reset, reset reg t_io_f1_req_valid_REG_2 : UInt<1>, clock connect t_io_f1_req_valid_REG_2, io.f0_valid connect tt_2_1.io.f1_req_valid, t_io_f1_req_valid_REG_2 reg t_io_f1_req_pc_REG_2 : UInt, clock connect t_io_f1_req_pc_REG_2, io.f0_pc connect tt_2_1.io.f1_req_pc, t_io_f1_req_pc_REG_2 connect tt_2_1.io.f1_req_ghist, io.f1_ghist inst tt_3_1 of TageTable_21 connect tt_3_1.clock, clock connect tt_3_1.reset, reset reg t_io_f1_req_valid_REG_3 : UInt<1>, clock connect t_io_f1_req_valid_REG_3, io.f0_valid connect tt_3_1.io.f1_req_valid, t_io_f1_req_valid_REG_3 reg t_io_f1_req_pc_REG_3 : UInt, clock connect t_io_f1_req_pc_REG_3, io.f0_pc connect tt_3_1.io.f1_req_pc, t_io_f1_req_pc_REG_3 connect tt_3_1.io.f1_req_ghist, io.f1_ghist inst tt_4_1 of TageTable_22 connect tt_4_1.clock, clock connect tt_4_1.reset, reset reg t_io_f1_req_valid_REG_4 : UInt<1>, clock connect t_io_f1_req_valid_REG_4, io.f0_valid connect tt_4_1.io.f1_req_valid, t_io_f1_req_valid_REG_4 reg t_io_f1_req_pc_REG_4 : UInt, clock connect t_io_f1_req_pc_REG_4, io.f0_pc connect tt_4_1.io.f1_req_pc, t_io_f1_req_pc_REG_4 connect tt_4_1.io.f1_req_ghist, io.f1_ghist inst tt_5_1 of TageTable_23 connect tt_5_1.clock, clock connect tt_5_1.reset, reset reg t_io_f1_req_valid_REG_5 : UInt<1>, clock connect t_io_f1_req_valid_REG_5, io.f0_valid connect tt_5_1.io.f1_req_valid, t_io_f1_req_valid_REG_5 reg t_io_f1_req_pc_REG_5 : UInt, clock connect t_io_f1_req_pc_REG_5, io.f0_pc connect tt_5_1.io.f1_req_pc, t_io_f1_req_pc_REG_5 connect tt_5_1.io.f1_req_ghist, io.f1_ghist wire f3_resps : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4][6] connect f3_resps[0], tt_0_1.io.f3_resp connect f3_resps[1], tt_1_1.io.f3_resp connect f3_resps[2], tt_2_1.io.f3_resp connect f3_resps[3], tt_3_1.io.f3_resp connect f3_resps[4], tt_4_1.io.f3_resp connect f3_resps[5], tt_5_1.io.f3_resp wire s1_update_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} wire _s1_update_meta_WIRE : UInt<56> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 2, 0) connect s1_update_meta.allocate[0].bits, _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 3) connect s1_update_meta.allocate[0].valid, _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 6, 4) connect s1_update_meta.allocate[1].bits, _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 7) connect s1_update_meta.allocate[1].valid, _s1_update_meta_T_3 node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 10, 8) connect s1_update_meta.allocate[2].bits, _s1_update_meta_T_4 node _s1_update_meta_T_5 = bits(_s1_update_meta_WIRE, 11, 11) connect s1_update_meta.allocate[2].valid, _s1_update_meta_T_5 node _s1_update_meta_T_6 = bits(_s1_update_meta_WIRE, 14, 12) connect s1_update_meta.allocate[3].bits, _s1_update_meta_T_6 node _s1_update_meta_T_7 = bits(_s1_update_meta_WIRE, 15, 15) connect s1_update_meta.allocate[3].valid, _s1_update_meta_T_7 node _s1_update_meta_T_8 = bits(_s1_update_meta_WIRE, 18, 16) connect s1_update_meta.provider_ctr[0], _s1_update_meta_T_8 node _s1_update_meta_T_9 = bits(_s1_update_meta_WIRE, 21, 19) connect s1_update_meta.provider_ctr[1], _s1_update_meta_T_9 node _s1_update_meta_T_10 = bits(_s1_update_meta_WIRE, 24, 22) connect s1_update_meta.provider_ctr[2], _s1_update_meta_T_10 node _s1_update_meta_T_11 = bits(_s1_update_meta_WIRE, 27, 25) connect s1_update_meta.provider_ctr[3], _s1_update_meta_T_11 node _s1_update_meta_T_12 = bits(_s1_update_meta_WIRE, 29, 28) connect s1_update_meta.provider_u[0], _s1_update_meta_T_12 node _s1_update_meta_T_13 = bits(_s1_update_meta_WIRE, 31, 30) connect s1_update_meta.provider_u[1], _s1_update_meta_T_13 node _s1_update_meta_T_14 = bits(_s1_update_meta_WIRE, 33, 32) connect s1_update_meta.provider_u[2], _s1_update_meta_T_14 node _s1_update_meta_T_15 = bits(_s1_update_meta_WIRE, 35, 34) connect s1_update_meta.provider_u[3], _s1_update_meta_T_15 node _s1_update_meta_T_16 = bits(_s1_update_meta_WIRE, 36, 36) connect s1_update_meta.alt_differs[0], _s1_update_meta_T_16 node _s1_update_meta_T_17 = bits(_s1_update_meta_WIRE, 37, 37) connect s1_update_meta.alt_differs[1], _s1_update_meta_T_17 node _s1_update_meta_T_18 = bits(_s1_update_meta_WIRE, 38, 38) connect s1_update_meta.alt_differs[2], _s1_update_meta_T_18 node _s1_update_meta_T_19 = bits(_s1_update_meta_WIRE, 39, 39) connect s1_update_meta.alt_differs[3], _s1_update_meta_T_19 node _s1_update_meta_T_20 = bits(_s1_update_meta_WIRE, 42, 40) connect s1_update_meta.provider[0].bits, _s1_update_meta_T_20 node _s1_update_meta_T_21 = bits(_s1_update_meta_WIRE, 43, 43) connect s1_update_meta.provider[0].valid, _s1_update_meta_T_21 node _s1_update_meta_T_22 = bits(_s1_update_meta_WIRE, 46, 44) connect s1_update_meta.provider[1].bits, _s1_update_meta_T_22 node _s1_update_meta_T_23 = bits(_s1_update_meta_WIRE, 47, 47) connect s1_update_meta.provider[1].valid, _s1_update_meta_T_23 node _s1_update_meta_T_24 = bits(_s1_update_meta_WIRE, 50, 48) connect s1_update_meta.provider[2].bits, _s1_update_meta_T_24 node _s1_update_meta_T_25 = bits(_s1_update_meta_WIRE, 51, 51) connect s1_update_meta.provider[2].valid, _s1_update_meta_T_25 node _s1_update_meta_T_26 = bits(_s1_update_meta_WIRE, 54, 52) connect s1_update_meta.provider[3].bits, _s1_update_meta_T_26 node _s1_update_meta_T_27 = bits(_s1_update_meta_WIRE, 55, 55) connect s1_update_meta.provider[3].valid, _s1_update_meta_T_27 node _s1_update_mispredict_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_mispredict_mask_T_1 = mux(s1_update.bits.cfi_mispredicted, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_mispredict_mask = and(_s1_update_mispredict_mask_T, _s1_update_mispredict_mask_T_1) wire _s1_update_mask_WIRE : UInt<1>[4][6] connect _s1_update_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_mask : UInt<1>[4][6] connect s1_update_mask, _s1_update_mask_WIRE wire _s1_update_u_mask_WIRE : UInt<1>[4][6] connect _s1_update_u_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_u_mask : UInt<1>[4][6] connect s1_update_u_mask, _s1_update_u_mask_WIRE wire s1_update_taken : UInt<1>[4][6] wire s1_update_old_ctr : UInt<3>[4][6] wire s1_update_alloc : UInt<1>[4][6] wire s1_update_u : UInt<2>[4][6] invalidate s1_update_taken[0][0] invalidate s1_update_taken[0][1] invalidate s1_update_taken[0][2] invalidate s1_update_taken[0][3] invalidate s1_update_taken[1][0] invalidate s1_update_taken[1][1] invalidate s1_update_taken[1][2] invalidate s1_update_taken[1][3] invalidate s1_update_taken[2][0] invalidate s1_update_taken[2][1] invalidate s1_update_taken[2][2] invalidate s1_update_taken[2][3] invalidate s1_update_taken[3][0] invalidate s1_update_taken[3][1] invalidate s1_update_taken[3][2] invalidate s1_update_taken[3][3] invalidate s1_update_taken[4][0] invalidate s1_update_taken[4][1] invalidate s1_update_taken[4][2] invalidate s1_update_taken[4][3] invalidate s1_update_taken[5][0] invalidate s1_update_taken[5][1] invalidate s1_update_taken[5][2] invalidate s1_update_taken[5][3] invalidate s1_update_old_ctr[0][0] invalidate s1_update_old_ctr[0][1] invalidate s1_update_old_ctr[0][2] invalidate s1_update_old_ctr[0][3] invalidate s1_update_old_ctr[1][0] invalidate s1_update_old_ctr[1][1] invalidate s1_update_old_ctr[1][2] invalidate s1_update_old_ctr[1][3] invalidate s1_update_old_ctr[2][0] invalidate s1_update_old_ctr[2][1] invalidate s1_update_old_ctr[2][2] invalidate s1_update_old_ctr[2][3] invalidate s1_update_old_ctr[3][0] invalidate s1_update_old_ctr[3][1] invalidate s1_update_old_ctr[3][2] invalidate s1_update_old_ctr[3][3] invalidate s1_update_old_ctr[4][0] invalidate s1_update_old_ctr[4][1] invalidate s1_update_old_ctr[4][2] invalidate s1_update_old_ctr[4][3] invalidate s1_update_old_ctr[5][0] invalidate s1_update_old_ctr[5][1] invalidate s1_update_old_ctr[5][2] invalidate s1_update_old_ctr[5][3] invalidate s1_update_alloc[0][0] invalidate s1_update_alloc[0][1] invalidate s1_update_alloc[0][2] invalidate s1_update_alloc[0][3] invalidate s1_update_alloc[1][0] invalidate s1_update_alloc[1][1] invalidate s1_update_alloc[1][2] invalidate s1_update_alloc[1][3] invalidate s1_update_alloc[2][0] invalidate s1_update_alloc[2][1] invalidate s1_update_alloc[2][2] invalidate s1_update_alloc[2][3] invalidate s1_update_alloc[3][0] invalidate s1_update_alloc[3][1] invalidate s1_update_alloc[3][2] invalidate s1_update_alloc[3][3] invalidate s1_update_alloc[4][0] invalidate s1_update_alloc[4][1] invalidate s1_update_alloc[4][2] invalidate s1_update_alloc[4][3] invalidate s1_update_alloc[5][0] invalidate s1_update_alloc[5][1] invalidate s1_update_alloc[5][2] invalidate s1_update_alloc[5][3] invalidate s1_update_u[0][0] invalidate s1_update_u[0][1] invalidate s1_update_u[0][2] invalidate s1_update_u[0][3] invalidate s1_update_u[1][0] invalidate s1_update_u[1][1] invalidate s1_update_u[1][2] invalidate s1_update_u[1][3] invalidate s1_update_u[2][0] invalidate s1_update_u[2][1] invalidate s1_update_u[2][2] invalidate s1_update_u[2][3] invalidate s1_update_u[3][0] invalidate s1_update_u[3][1] invalidate s1_update_u[3][2] invalidate s1_update_u[3][3] invalidate s1_update_u[4][0] invalidate s1_update_u[4][1] invalidate s1_update_u[4][2] invalidate s1_update_u[4][3] invalidate s1_update_u[5][0] invalidate s1_update_u[5][1] invalidate s1_update_u[5][2] invalidate s1_update_u[5][3] wire final_altpred : UInt<1> connect final_altpred, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, io.resp_in[0].f3[0].taken when f3_resps[0][0].valid : node _io_resp_f3_0_taken_T = eq(f3_resps[0][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_1 = eq(f3_resps[0][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_2 = or(_io_resp_f3_0_taken_T, _io_resp_f3_0_taken_T_1) node _io_resp_f3_0_taken_T_3 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_4 = mux(_io_resp_f3_0_taken_T_2, io.resp_in[0].f3[0].taken, _io_resp_f3_0_taken_T_3) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_4 connect final_altpred, io.resp_in[0].f3[0].taken node _T_14 = or(UInt<1>(0h0), f3_resps[0][0].valid) node _T_15 = mux(f3_resps[0][0].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_16 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _T_17 = mux(f3_resps[0][0].valid, _T_16, io.resp_in[0].f3[0].taken) when f3_resps[1][0].valid : node _io_resp_f3_0_taken_T_5 = eq(f3_resps[1][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_6 = eq(f3_resps[1][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_7 = or(_io_resp_f3_0_taken_T_5, _io_resp_f3_0_taken_T_6) node _io_resp_f3_0_taken_T_8 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_9 = mux(_io_resp_f3_0_taken_T_7, _T_17, _io_resp_f3_0_taken_T_8) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_9 connect final_altpred, _T_17 node _T_18 = or(_T_14, f3_resps[1][0].valid) node _T_19 = mux(f3_resps[1][0].valid, UInt<1>(0h1), _T_15) node _T_20 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _T_21 = mux(f3_resps[1][0].valid, _T_20, _T_17) when f3_resps[2][0].valid : node _io_resp_f3_0_taken_T_10 = eq(f3_resps[2][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_11 = eq(f3_resps[2][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_12 = or(_io_resp_f3_0_taken_T_10, _io_resp_f3_0_taken_T_11) node _io_resp_f3_0_taken_T_13 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_14 = mux(_io_resp_f3_0_taken_T_12, _T_21, _io_resp_f3_0_taken_T_13) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_14 connect final_altpred, _T_21 node _T_22 = or(_T_18, f3_resps[2][0].valid) node _T_23 = mux(f3_resps[2][0].valid, UInt<2>(0h2), _T_19) node _T_24 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _T_25 = mux(f3_resps[2][0].valid, _T_24, _T_21) when f3_resps[3][0].valid : node _io_resp_f3_0_taken_T_15 = eq(f3_resps[3][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_16 = eq(f3_resps[3][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_17 = or(_io_resp_f3_0_taken_T_15, _io_resp_f3_0_taken_T_16) node _io_resp_f3_0_taken_T_18 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_19 = mux(_io_resp_f3_0_taken_T_17, _T_25, _io_resp_f3_0_taken_T_18) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_19 connect final_altpred, _T_25 node _T_26 = or(_T_22, f3_resps[3][0].valid) node _T_27 = mux(f3_resps[3][0].valid, UInt<2>(0h3), _T_23) node _T_28 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _T_29 = mux(f3_resps[3][0].valid, _T_28, _T_25) when f3_resps[4][0].valid : node _io_resp_f3_0_taken_T_20 = eq(f3_resps[4][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_21 = eq(f3_resps[4][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_22 = or(_io_resp_f3_0_taken_T_20, _io_resp_f3_0_taken_T_21) node _io_resp_f3_0_taken_T_23 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_24 = mux(_io_resp_f3_0_taken_T_22, _T_29, _io_resp_f3_0_taken_T_23) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_24 connect final_altpred, _T_29 node _T_30 = or(_T_26, f3_resps[4][0].valid) node _T_31 = mux(f3_resps[4][0].valid, UInt<3>(0h4), _T_27) node _T_32 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _T_33 = mux(f3_resps[4][0].valid, _T_32, _T_29) when f3_resps[5][0].valid : node _io_resp_f3_0_taken_T_25 = eq(f3_resps[5][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_26 = eq(f3_resps[5][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_27 = or(_io_resp_f3_0_taken_T_25, _io_resp_f3_0_taken_T_26) node _io_resp_f3_0_taken_T_28 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_29 = mux(_io_resp_f3_0_taken_T_27, _T_33, _io_resp_f3_0_taken_T_28) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_29 connect final_altpred, _T_33 node _T_34 = or(_T_30, f3_resps[5][0].valid) node _T_35 = mux(f3_resps[5][0].valid, UInt<3>(0h5), _T_31) node _T_36 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _T_37 = mux(f3_resps[5][0].valid, _T_36, _T_33) connect f3_meta.provider[0].valid, _T_34 connect f3_meta.provider[0].bits, _T_35 node _f3_meta_alt_differs_0_T = neq(final_altpred, io.resp.f3[0].taken) connect f3_meta.alt_differs[0], _f3_meta_alt_differs_0_T connect f3_meta.provider_u[0], f3_resps[_T_35][0].bits.u connect f3_meta.provider_ctr[0], f3_resps[_T_35][0].bits.ctr node _allocatable_slots_T = eq(f3_resps[0][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_1 = eq(f3_resps[0][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_2 = and(_allocatable_slots_T, _allocatable_slots_T_1) node _allocatable_slots_T_3 = eq(f3_resps[1][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_4 = eq(f3_resps[1][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_5 = and(_allocatable_slots_T_3, _allocatable_slots_T_4) node _allocatable_slots_T_6 = eq(f3_resps[2][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_7 = eq(f3_resps[2][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_8 = and(_allocatable_slots_T_6, _allocatable_slots_T_7) node _allocatable_slots_T_9 = eq(f3_resps[3][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_10 = eq(f3_resps[3][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_11 = and(_allocatable_slots_T_9, _allocatable_slots_T_10) node _allocatable_slots_T_12 = eq(f3_resps[4][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_13 = eq(f3_resps[4][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_14 = and(_allocatable_slots_T_12, _allocatable_slots_T_13) node _allocatable_slots_T_15 = eq(f3_resps[5][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_16 = eq(f3_resps[5][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_17 = and(_allocatable_slots_T_15, _allocatable_slots_T_16) wire _allocatable_slots_WIRE : UInt<1>[6] connect _allocatable_slots_WIRE[0], _allocatable_slots_T_2 connect _allocatable_slots_WIRE[1], _allocatable_slots_T_5 connect _allocatable_slots_WIRE[2], _allocatable_slots_T_8 connect _allocatable_slots_WIRE[3], _allocatable_slots_T_11 connect _allocatable_slots_WIRE[4], _allocatable_slots_T_14 connect _allocatable_slots_WIRE[5], _allocatable_slots_T_17 node allocatable_slots_lo_hi = cat(_allocatable_slots_WIRE[2], _allocatable_slots_WIRE[1]) node allocatable_slots_lo = cat(allocatable_slots_lo_hi, _allocatable_slots_WIRE[0]) node allocatable_slots_hi_hi = cat(_allocatable_slots_WIRE[5], _allocatable_slots_WIRE[4]) node allocatable_slots_hi = cat(allocatable_slots_hi_hi, _allocatable_slots_WIRE[3]) node _allocatable_slots_T_18 = cat(allocatable_slots_hi, allocatable_slots_lo) node _allocatable_slots_T_19 = dshl(UInt<1>(0h1), _T_35) node _allocatable_slots_T_20 = dshr(_allocatable_slots_T_19, UInt<1>(0h0)) node _allocatable_slots_T_21 = dshr(_allocatable_slots_T_19, UInt<1>(0h1)) node _allocatable_slots_T_22 = dshr(_allocatable_slots_T_19, UInt<2>(0h2)) node _allocatable_slots_T_23 = dshr(_allocatable_slots_T_19, UInt<2>(0h3)) node _allocatable_slots_T_24 = dshr(_allocatable_slots_T_19, UInt<3>(0h4)) node _allocatable_slots_T_25 = dshr(_allocatable_slots_T_19, UInt<3>(0h5)) node _allocatable_slots_T_26 = dshr(_allocatable_slots_T_19, UInt<3>(0h6)) node _allocatable_slots_T_27 = dshr(_allocatable_slots_T_19, UInt<3>(0h7)) node _allocatable_slots_T_28 = or(_allocatable_slots_T_20, _allocatable_slots_T_21) node _allocatable_slots_T_29 = or(_allocatable_slots_T_28, _allocatable_slots_T_22) node _allocatable_slots_T_30 = or(_allocatable_slots_T_29, _allocatable_slots_T_23) node _allocatable_slots_T_31 = or(_allocatable_slots_T_30, _allocatable_slots_T_24) node _allocatable_slots_T_32 = or(_allocatable_slots_T_31, _allocatable_slots_T_25) node _allocatable_slots_T_33 = or(_allocatable_slots_T_32, _allocatable_slots_T_26) node _allocatable_slots_T_34 = or(_allocatable_slots_T_33, _allocatable_slots_T_27) node _allocatable_slots_T_35 = mux(_T_34, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_36 = and(_allocatable_slots_T_34, _allocatable_slots_T_35) node _allocatable_slots_T_37 = not(_allocatable_slots_T_36) node allocatable_slots = and(_allocatable_slots_T_18, _allocatable_slots_T_37) inst alloc_lfsr_prng of MaxPeriodFibonacciLFSR_21 connect alloc_lfsr_prng.clock, clock connect alloc_lfsr_prng.reset, reset connect alloc_lfsr_prng.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng.io.seed.bits[0] invalidate alloc_lfsr_prng.io.seed.bits[1] invalidate alloc_lfsr_prng.io.seed.bits[2] invalidate alloc_lfsr_prng.io.seed.bits[3] invalidate alloc_lfsr_prng.io.seed.bits[4] invalidate alloc_lfsr_prng.io.seed.bits[5] connect alloc_lfsr_prng.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi = cat(alloc_lfsr_prng.io.out[2], alloc_lfsr_prng.io.out[1]) node alloc_lfsr_lo = cat(alloc_lfsr_lo_hi, alloc_lfsr_prng.io.out[0]) node alloc_lfsr_hi_hi = cat(alloc_lfsr_prng.io.out[5], alloc_lfsr_prng.io.out[4]) node alloc_lfsr_hi = cat(alloc_lfsr_hi_hi, alloc_lfsr_prng.io.out[3]) node alloc_lfsr = cat(alloc_lfsr_hi, alloc_lfsr_lo) node _first_entry_T = bits(allocatable_slots, 0, 0) node _first_entry_T_1 = bits(allocatable_slots, 1, 1) node _first_entry_T_2 = bits(allocatable_slots, 2, 2) node _first_entry_T_3 = bits(allocatable_slots, 3, 3) node _first_entry_T_4 = bits(allocatable_slots, 4, 4) node _first_entry_T_5 = bits(allocatable_slots, 5, 5) node _first_entry_T_6 = bits(allocatable_slots, 6, 6) node _first_entry_T_7 = bits(allocatable_slots, 7, 7) node _first_entry_T_8 = mux(_first_entry_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_9 = mux(_first_entry_T_5, UInt<3>(0h5), _first_entry_T_8) node _first_entry_T_10 = mux(_first_entry_T_4, UInt<3>(0h4), _first_entry_T_9) node _first_entry_T_11 = mux(_first_entry_T_3, UInt<2>(0h3), _first_entry_T_10) node _first_entry_T_12 = mux(_first_entry_T_2, UInt<2>(0h2), _first_entry_T_11) node _first_entry_T_13 = mux(_first_entry_T_1, UInt<1>(0h1), _first_entry_T_12) node first_entry = mux(_first_entry_T, UInt<1>(0h0), _first_entry_T_13) node _masked_entry_T = and(allocatable_slots, alloc_lfsr) node _masked_entry_T_1 = bits(_masked_entry_T, 0, 0) node _masked_entry_T_2 = bits(_masked_entry_T, 1, 1) node _masked_entry_T_3 = bits(_masked_entry_T, 2, 2) node _masked_entry_T_4 = bits(_masked_entry_T, 3, 3) node _masked_entry_T_5 = bits(_masked_entry_T, 4, 4) node _masked_entry_T_6 = bits(_masked_entry_T, 5, 5) node _masked_entry_T_7 = bits(_masked_entry_T, 6, 6) node _masked_entry_T_8 = bits(_masked_entry_T, 7, 7) node _masked_entry_T_9 = mux(_masked_entry_T_7, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_10 = mux(_masked_entry_T_6, UInt<3>(0h5), _masked_entry_T_9) node _masked_entry_T_11 = mux(_masked_entry_T_5, UInt<3>(0h4), _masked_entry_T_10) node _masked_entry_T_12 = mux(_masked_entry_T_4, UInt<2>(0h3), _masked_entry_T_11) node _masked_entry_T_13 = mux(_masked_entry_T_3, UInt<2>(0h2), _masked_entry_T_12) node _masked_entry_T_14 = mux(_masked_entry_T_2, UInt<1>(0h1), _masked_entry_T_13) node masked_entry = mux(_masked_entry_T_1, UInt<1>(0h0), _masked_entry_T_14) node _alloc_entry_T = dshr(allocatable_slots, masked_entry) node _alloc_entry_T_1 = bits(_alloc_entry_T, 0, 0) node alloc_entry = mux(_alloc_entry_T_1, masked_entry, first_entry) node _f3_meta_allocate_0_valid_T = neq(allocatable_slots, UInt<1>(0h0)) connect f3_meta.allocate[0].valid, _f3_meta_allocate_0_valid_T connect f3_meta.allocate[0].bits, alloc_entry node _update_was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _update_was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T) node update_was_taken = and(_update_was_taken_T_1, s1_update.bits.cfi_taken) node _T_38 = bits(s1_update.bits.br_mask, 0, 0) node _T_39 = and(_T_38, s1_update.valid) node _T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = and(_T_39, _T_43) when _T_44 : when s1_update_meta.provider[0].valid : connect s1_update_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) node _new_u_T = bits(s1_update_mispredict_mask, 0, 0) node _new_u_T_1 = eq(s1_update_meta.alt_differs[0], UInt<1>(0h0)) node _new_u_T_2 = eq(s1_update_meta.provider_u[0], UInt<1>(0h0)) node _new_u_T_3 = sub(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_4 = tail(_new_u_T_3, 1) node _new_u_T_5 = mux(_new_u_T_2, UInt<1>(0h0), _new_u_T_4) node _new_u_T_6 = eq(s1_update_meta.provider_u[0], UInt<2>(0h3)) node _new_u_T_7 = add(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_8 = tail(_new_u_T_7, 1) node _new_u_T_9 = mux(_new_u_T_6, UInt<2>(0h3), _new_u_T_8) node _new_u_T_10 = mux(_new_u_T, _new_u_T_5, _new_u_T_9) node new_u = mux(_new_u_T_1, s1_update_meta.provider_u[0], _new_u_T_10) connect s1_update_u[s1_update_meta.provider[0].bits][0], new_u connect s1_update_taken[s1_update_meta.provider[0].bits][0], update_was_taken connect s1_update_old_ctr[s1_update_meta.provider[0].bits][0], s1_update_meta.provider_ctr[0] connect s1_update_alloc[s1_update_meta.provider[0].bits][0], UInt<1>(0h0) wire final_altpred_1 : UInt<1> connect final_altpred_1, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, io.resp_in[0].f3[1].taken when f3_resps[0][1].valid : node _io_resp_f3_1_taken_T = eq(f3_resps[0][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_1 = eq(f3_resps[0][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_2 = or(_io_resp_f3_1_taken_T, _io_resp_f3_1_taken_T_1) node _io_resp_f3_1_taken_T_3 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_4 = mux(_io_resp_f3_1_taken_T_2, io.resp_in[0].f3[1].taken, _io_resp_f3_1_taken_T_3) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_4 connect final_altpred_1, io.resp_in[0].f3[1].taken node _T_45 = or(UInt<1>(0h0), f3_resps[0][1].valid) node _T_46 = mux(f3_resps[0][1].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _T_48 = mux(f3_resps[0][1].valid, _T_47, io.resp_in[0].f3[1].taken) when f3_resps[1][1].valid : node _io_resp_f3_1_taken_T_5 = eq(f3_resps[1][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_6 = eq(f3_resps[1][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_7 = or(_io_resp_f3_1_taken_T_5, _io_resp_f3_1_taken_T_6) node _io_resp_f3_1_taken_T_8 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_9 = mux(_io_resp_f3_1_taken_T_7, _T_48, _io_resp_f3_1_taken_T_8) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_9 connect final_altpred_1, _T_48 node _T_49 = or(_T_45, f3_resps[1][1].valid) node _T_50 = mux(f3_resps[1][1].valid, UInt<1>(0h1), _T_46) node _T_51 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _T_52 = mux(f3_resps[1][1].valid, _T_51, _T_48) when f3_resps[2][1].valid : node _io_resp_f3_1_taken_T_10 = eq(f3_resps[2][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_11 = eq(f3_resps[2][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_12 = or(_io_resp_f3_1_taken_T_10, _io_resp_f3_1_taken_T_11) node _io_resp_f3_1_taken_T_13 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_14 = mux(_io_resp_f3_1_taken_T_12, _T_52, _io_resp_f3_1_taken_T_13) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_14 connect final_altpred_1, _T_52 node _T_53 = or(_T_49, f3_resps[2][1].valid) node _T_54 = mux(f3_resps[2][1].valid, UInt<2>(0h2), _T_50) node _T_55 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _T_56 = mux(f3_resps[2][1].valid, _T_55, _T_52) when f3_resps[3][1].valid : node _io_resp_f3_1_taken_T_15 = eq(f3_resps[3][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_16 = eq(f3_resps[3][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_17 = or(_io_resp_f3_1_taken_T_15, _io_resp_f3_1_taken_T_16) node _io_resp_f3_1_taken_T_18 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_19 = mux(_io_resp_f3_1_taken_T_17, _T_56, _io_resp_f3_1_taken_T_18) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_19 connect final_altpred_1, _T_56 node _T_57 = or(_T_53, f3_resps[3][1].valid) node _T_58 = mux(f3_resps[3][1].valid, UInt<2>(0h3), _T_54) node _T_59 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _T_60 = mux(f3_resps[3][1].valid, _T_59, _T_56) when f3_resps[4][1].valid : node _io_resp_f3_1_taken_T_20 = eq(f3_resps[4][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_21 = eq(f3_resps[4][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_22 = or(_io_resp_f3_1_taken_T_20, _io_resp_f3_1_taken_T_21) node _io_resp_f3_1_taken_T_23 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_24 = mux(_io_resp_f3_1_taken_T_22, _T_60, _io_resp_f3_1_taken_T_23) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_24 connect final_altpred_1, _T_60 node _T_61 = or(_T_57, f3_resps[4][1].valid) node _T_62 = mux(f3_resps[4][1].valid, UInt<3>(0h4), _T_58) node _T_63 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _T_64 = mux(f3_resps[4][1].valid, _T_63, _T_60) when f3_resps[5][1].valid : node _io_resp_f3_1_taken_T_25 = eq(f3_resps[5][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_26 = eq(f3_resps[5][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_27 = or(_io_resp_f3_1_taken_T_25, _io_resp_f3_1_taken_T_26) node _io_resp_f3_1_taken_T_28 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_29 = mux(_io_resp_f3_1_taken_T_27, _T_64, _io_resp_f3_1_taken_T_28) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_29 connect final_altpred_1, _T_64 node _T_65 = or(_T_61, f3_resps[5][1].valid) node _T_66 = mux(f3_resps[5][1].valid, UInt<3>(0h5), _T_62) node _T_67 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _T_68 = mux(f3_resps[5][1].valid, _T_67, _T_64) connect f3_meta.provider[1].valid, _T_65 connect f3_meta.provider[1].bits, _T_66 node _f3_meta_alt_differs_1_T = neq(final_altpred_1, io.resp.f3[1].taken) connect f3_meta.alt_differs[1], _f3_meta_alt_differs_1_T connect f3_meta.provider_u[1], f3_resps[_T_66][1].bits.u connect f3_meta.provider_ctr[1], f3_resps[_T_66][1].bits.ctr node _allocatable_slots_T_38 = eq(f3_resps[0][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_39 = eq(f3_resps[0][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_40 = and(_allocatable_slots_T_38, _allocatable_slots_T_39) node _allocatable_slots_T_41 = eq(f3_resps[1][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_42 = eq(f3_resps[1][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_43 = and(_allocatable_slots_T_41, _allocatable_slots_T_42) node _allocatable_slots_T_44 = eq(f3_resps[2][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_45 = eq(f3_resps[2][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_46 = and(_allocatable_slots_T_44, _allocatable_slots_T_45) node _allocatable_slots_T_47 = eq(f3_resps[3][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_48 = eq(f3_resps[3][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_49 = and(_allocatable_slots_T_47, _allocatable_slots_T_48) node _allocatable_slots_T_50 = eq(f3_resps[4][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_51 = eq(f3_resps[4][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_52 = and(_allocatable_slots_T_50, _allocatable_slots_T_51) node _allocatable_slots_T_53 = eq(f3_resps[5][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_54 = eq(f3_resps[5][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_55 = and(_allocatable_slots_T_53, _allocatable_slots_T_54) wire _allocatable_slots_WIRE_1 : UInt<1>[6] connect _allocatable_slots_WIRE_1[0], _allocatable_slots_T_40 connect _allocatable_slots_WIRE_1[1], _allocatable_slots_T_43 connect _allocatable_slots_WIRE_1[2], _allocatable_slots_T_46 connect _allocatable_slots_WIRE_1[3], _allocatable_slots_T_49 connect _allocatable_slots_WIRE_1[4], _allocatable_slots_T_52 connect _allocatable_slots_WIRE_1[5], _allocatable_slots_T_55 node allocatable_slots_lo_hi_1 = cat(_allocatable_slots_WIRE_1[2], _allocatable_slots_WIRE_1[1]) node allocatable_slots_lo_1 = cat(allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1[0]) node allocatable_slots_hi_hi_1 = cat(_allocatable_slots_WIRE_1[5], _allocatable_slots_WIRE_1[4]) node allocatable_slots_hi_1 = cat(allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1[3]) node _allocatable_slots_T_56 = cat(allocatable_slots_hi_1, allocatable_slots_lo_1) node _allocatable_slots_T_57 = dshl(UInt<1>(0h1), _T_66) node _allocatable_slots_T_58 = dshr(_allocatable_slots_T_57, UInt<1>(0h0)) node _allocatable_slots_T_59 = dshr(_allocatable_slots_T_57, UInt<1>(0h1)) node _allocatable_slots_T_60 = dshr(_allocatable_slots_T_57, UInt<2>(0h2)) node _allocatable_slots_T_61 = dshr(_allocatable_slots_T_57, UInt<2>(0h3)) node _allocatable_slots_T_62 = dshr(_allocatable_slots_T_57, UInt<3>(0h4)) node _allocatable_slots_T_63 = dshr(_allocatable_slots_T_57, UInt<3>(0h5)) node _allocatable_slots_T_64 = dshr(_allocatable_slots_T_57, UInt<3>(0h6)) node _allocatable_slots_T_65 = dshr(_allocatable_slots_T_57, UInt<3>(0h7)) node _allocatable_slots_T_66 = or(_allocatable_slots_T_58, _allocatable_slots_T_59) node _allocatable_slots_T_67 = or(_allocatable_slots_T_66, _allocatable_slots_T_60) node _allocatable_slots_T_68 = or(_allocatable_slots_T_67, _allocatable_slots_T_61) node _allocatable_slots_T_69 = or(_allocatable_slots_T_68, _allocatable_slots_T_62) node _allocatable_slots_T_70 = or(_allocatable_slots_T_69, _allocatable_slots_T_63) node _allocatable_slots_T_71 = or(_allocatable_slots_T_70, _allocatable_slots_T_64) node _allocatable_slots_T_72 = or(_allocatable_slots_T_71, _allocatable_slots_T_65) node _allocatable_slots_T_73 = mux(_T_65, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_74 = and(_allocatable_slots_T_72, _allocatable_slots_T_73) node _allocatable_slots_T_75 = not(_allocatable_slots_T_74) node allocatable_slots_1 = and(_allocatable_slots_T_56, _allocatable_slots_T_75) inst alloc_lfsr_prng_1 of MaxPeriodFibonacciLFSR_22 connect alloc_lfsr_prng_1.clock, clock connect alloc_lfsr_prng_1.reset, reset connect alloc_lfsr_prng_1.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_1.io.seed.bits[0] invalidate alloc_lfsr_prng_1.io.seed.bits[1] invalidate alloc_lfsr_prng_1.io.seed.bits[2] invalidate alloc_lfsr_prng_1.io.seed.bits[3] invalidate alloc_lfsr_prng_1.io.seed.bits[4] invalidate alloc_lfsr_prng_1.io.seed.bits[5] connect alloc_lfsr_prng_1.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_1 = cat(alloc_lfsr_prng_1.io.out[2], alloc_lfsr_prng_1.io.out[1]) node alloc_lfsr_lo_1 = cat(alloc_lfsr_lo_hi_1, alloc_lfsr_prng_1.io.out[0]) node alloc_lfsr_hi_hi_1 = cat(alloc_lfsr_prng_1.io.out[5], alloc_lfsr_prng_1.io.out[4]) node alloc_lfsr_hi_1 = cat(alloc_lfsr_hi_hi_1, alloc_lfsr_prng_1.io.out[3]) node alloc_lfsr_1 = cat(alloc_lfsr_hi_1, alloc_lfsr_lo_1) node _first_entry_T_14 = bits(allocatable_slots_1, 0, 0) node _first_entry_T_15 = bits(allocatable_slots_1, 1, 1) node _first_entry_T_16 = bits(allocatable_slots_1, 2, 2) node _first_entry_T_17 = bits(allocatable_slots_1, 3, 3) node _first_entry_T_18 = bits(allocatable_slots_1, 4, 4) node _first_entry_T_19 = bits(allocatable_slots_1, 5, 5) node _first_entry_T_20 = bits(allocatable_slots_1, 6, 6) node _first_entry_T_21 = bits(allocatable_slots_1, 7, 7) node _first_entry_T_22 = mux(_first_entry_T_20, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_23 = mux(_first_entry_T_19, UInt<3>(0h5), _first_entry_T_22) node _first_entry_T_24 = mux(_first_entry_T_18, UInt<3>(0h4), _first_entry_T_23) node _first_entry_T_25 = mux(_first_entry_T_17, UInt<2>(0h3), _first_entry_T_24) node _first_entry_T_26 = mux(_first_entry_T_16, UInt<2>(0h2), _first_entry_T_25) node _first_entry_T_27 = mux(_first_entry_T_15, UInt<1>(0h1), _first_entry_T_26) node first_entry_1 = mux(_first_entry_T_14, UInt<1>(0h0), _first_entry_T_27) node _masked_entry_T_15 = and(allocatable_slots_1, alloc_lfsr_1) node _masked_entry_T_16 = bits(_masked_entry_T_15, 0, 0) node _masked_entry_T_17 = bits(_masked_entry_T_15, 1, 1) node _masked_entry_T_18 = bits(_masked_entry_T_15, 2, 2) node _masked_entry_T_19 = bits(_masked_entry_T_15, 3, 3) node _masked_entry_T_20 = bits(_masked_entry_T_15, 4, 4) node _masked_entry_T_21 = bits(_masked_entry_T_15, 5, 5) node _masked_entry_T_22 = bits(_masked_entry_T_15, 6, 6) node _masked_entry_T_23 = bits(_masked_entry_T_15, 7, 7) node _masked_entry_T_24 = mux(_masked_entry_T_22, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_25 = mux(_masked_entry_T_21, UInt<3>(0h5), _masked_entry_T_24) node _masked_entry_T_26 = mux(_masked_entry_T_20, UInt<3>(0h4), _masked_entry_T_25) node _masked_entry_T_27 = mux(_masked_entry_T_19, UInt<2>(0h3), _masked_entry_T_26) node _masked_entry_T_28 = mux(_masked_entry_T_18, UInt<2>(0h2), _masked_entry_T_27) node _masked_entry_T_29 = mux(_masked_entry_T_17, UInt<1>(0h1), _masked_entry_T_28) node masked_entry_1 = mux(_masked_entry_T_16, UInt<1>(0h0), _masked_entry_T_29) node _alloc_entry_T_2 = dshr(allocatable_slots_1, masked_entry_1) node _alloc_entry_T_3 = bits(_alloc_entry_T_2, 0, 0) node alloc_entry_1 = mux(_alloc_entry_T_3, masked_entry_1, first_entry_1) node _f3_meta_allocate_1_valid_T = neq(allocatable_slots_1, UInt<1>(0h0)) connect f3_meta.allocate[1].valid, _f3_meta_allocate_1_valid_T connect f3_meta.allocate[1].bits, alloc_entry_1 node _update_was_taken_T_2 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _update_was_taken_T_3 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_2) node update_was_taken_1 = and(_update_was_taken_T_3, s1_update.bits.cfi_taken) node _T_69 = bits(s1_update.bits.br_mask, 1, 1) node _T_70 = and(_T_69, s1_update.valid) node _T_71 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_72 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_73 = or(_T_71, _T_72) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = and(_T_70, _T_74) when _T_75 : when s1_update_meta.provider[1].valid : connect s1_update_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) node _new_u_T_11 = bits(s1_update_mispredict_mask, 1, 1) node _new_u_T_12 = eq(s1_update_meta.alt_differs[1], UInt<1>(0h0)) node _new_u_T_13 = eq(s1_update_meta.provider_u[1], UInt<1>(0h0)) node _new_u_T_14 = sub(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_15 = tail(_new_u_T_14, 1) node _new_u_T_16 = mux(_new_u_T_13, UInt<1>(0h0), _new_u_T_15) node _new_u_T_17 = eq(s1_update_meta.provider_u[1], UInt<2>(0h3)) node _new_u_T_18 = add(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_19 = tail(_new_u_T_18, 1) node _new_u_T_20 = mux(_new_u_T_17, UInt<2>(0h3), _new_u_T_19) node _new_u_T_21 = mux(_new_u_T_11, _new_u_T_16, _new_u_T_20) node new_u_1 = mux(_new_u_T_12, s1_update_meta.provider_u[1], _new_u_T_21) connect s1_update_u[s1_update_meta.provider[1].bits][1], new_u_1 connect s1_update_taken[s1_update_meta.provider[1].bits][1], update_was_taken_1 connect s1_update_old_ctr[s1_update_meta.provider[1].bits][1], s1_update_meta.provider_ctr[1] connect s1_update_alloc[s1_update_meta.provider[1].bits][1], UInt<1>(0h0) wire final_altpred_2 : UInt<1> connect final_altpred_2, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, io.resp_in[0].f3[2].taken when f3_resps[0][2].valid : node _io_resp_f3_2_taken_T = eq(f3_resps[0][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_1 = eq(f3_resps[0][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_2 = or(_io_resp_f3_2_taken_T, _io_resp_f3_2_taken_T_1) node _io_resp_f3_2_taken_T_3 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_4 = mux(_io_resp_f3_2_taken_T_2, io.resp_in[0].f3[2].taken, _io_resp_f3_2_taken_T_3) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_4 connect final_altpred_2, io.resp_in[0].f3[2].taken node _T_76 = or(UInt<1>(0h0), f3_resps[0][2].valid) node _T_77 = mux(f3_resps[0][2].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_78 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _T_79 = mux(f3_resps[0][2].valid, _T_78, io.resp_in[0].f3[2].taken) when f3_resps[1][2].valid : node _io_resp_f3_2_taken_T_5 = eq(f3_resps[1][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_6 = eq(f3_resps[1][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_7 = or(_io_resp_f3_2_taken_T_5, _io_resp_f3_2_taken_T_6) node _io_resp_f3_2_taken_T_8 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_9 = mux(_io_resp_f3_2_taken_T_7, _T_79, _io_resp_f3_2_taken_T_8) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_9 connect final_altpred_2, _T_79 node _T_80 = or(_T_76, f3_resps[1][2].valid) node _T_81 = mux(f3_resps[1][2].valid, UInt<1>(0h1), _T_77) node _T_82 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _T_83 = mux(f3_resps[1][2].valid, _T_82, _T_79) when f3_resps[2][2].valid : node _io_resp_f3_2_taken_T_10 = eq(f3_resps[2][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_11 = eq(f3_resps[2][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_12 = or(_io_resp_f3_2_taken_T_10, _io_resp_f3_2_taken_T_11) node _io_resp_f3_2_taken_T_13 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_14 = mux(_io_resp_f3_2_taken_T_12, _T_83, _io_resp_f3_2_taken_T_13) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_14 connect final_altpred_2, _T_83 node _T_84 = or(_T_80, f3_resps[2][2].valid) node _T_85 = mux(f3_resps[2][2].valid, UInt<2>(0h2), _T_81) node _T_86 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _T_87 = mux(f3_resps[2][2].valid, _T_86, _T_83) when f3_resps[3][2].valid : node _io_resp_f3_2_taken_T_15 = eq(f3_resps[3][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_16 = eq(f3_resps[3][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_17 = or(_io_resp_f3_2_taken_T_15, _io_resp_f3_2_taken_T_16) node _io_resp_f3_2_taken_T_18 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_19 = mux(_io_resp_f3_2_taken_T_17, _T_87, _io_resp_f3_2_taken_T_18) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_19 connect final_altpred_2, _T_87 node _T_88 = or(_T_84, f3_resps[3][2].valid) node _T_89 = mux(f3_resps[3][2].valid, UInt<2>(0h3), _T_85) node _T_90 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _T_91 = mux(f3_resps[3][2].valid, _T_90, _T_87) when f3_resps[4][2].valid : node _io_resp_f3_2_taken_T_20 = eq(f3_resps[4][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_21 = eq(f3_resps[4][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_22 = or(_io_resp_f3_2_taken_T_20, _io_resp_f3_2_taken_T_21) node _io_resp_f3_2_taken_T_23 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_24 = mux(_io_resp_f3_2_taken_T_22, _T_91, _io_resp_f3_2_taken_T_23) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_24 connect final_altpred_2, _T_91 node _T_92 = or(_T_88, f3_resps[4][2].valid) node _T_93 = mux(f3_resps[4][2].valid, UInt<3>(0h4), _T_89) node _T_94 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _T_95 = mux(f3_resps[4][2].valid, _T_94, _T_91) when f3_resps[5][2].valid : node _io_resp_f3_2_taken_T_25 = eq(f3_resps[5][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_26 = eq(f3_resps[5][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_27 = or(_io_resp_f3_2_taken_T_25, _io_resp_f3_2_taken_T_26) node _io_resp_f3_2_taken_T_28 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_29 = mux(_io_resp_f3_2_taken_T_27, _T_95, _io_resp_f3_2_taken_T_28) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_29 connect final_altpred_2, _T_95 node _T_96 = or(_T_92, f3_resps[5][2].valid) node _T_97 = mux(f3_resps[5][2].valid, UInt<3>(0h5), _T_93) node _T_98 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _T_99 = mux(f3_resps[5][2].valid, _T_98, _T_95) connect f3_meta.provider[2].valid, _T_96 connect f3_meta.provider[2].bits, _T_97 node _f3_meta_alt_differs_2_T = neq(final_altpred_2, io.resp.f3[2].taken) connect f3_meta.alt_differs[2], _f3_meta_alt_differs_2_T connect f3_meta.provider_u[2], f3_resps[_T_97][2].bits.u connect f3_meta.provider_ctr[2], f3_resps[_T_97][2].bits.ctr node _allocatable_slots_T_76 = eq(f3_resps[0][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_77 = eq(f3_resps[0][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_78 = and(_allocatable_slots_T_76, _allocatable_slots_T_77) node _allocatable_slots_T_79 = eq(f3_resps[1][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_80 = eq(f3_resps[1][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_81 = and(_allocatable_slots_T_79, _allocatable_slots_T_80) node _allocatable_slots_T_82 = eq(f3_resps[2][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_83 = eq(f3_resps[2][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_84 = and(_allocatable_slots_T_82, _allocatable_slots_T_83) node _allocatable_slots_T_85 = eq(f3_resps[3][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_86 = eq(f3_resps[3][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_87 = and(_allocatable_slots_T_85, _allocatable_slots_T_86) node _allocatable_slots_T_88 = eq(f3_resps[4][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_89 = eq(f3_resps[4][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_90 = and(_allocatable_slots_T_88, _allocatable_slots_T_89) node _allocatable_slots_T_91 = eq(f3_resps[5][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_92 = eq(f3_resps[5][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_93 = and(_allocatable_slots_T_91, _allocatable_slots_T_92) wire _allocatable_slots_WIRE_2 : UInt<1>[6] connect _allocatable_slots_WIRE_2[0], _allocatable_slots_T_78 connect _allocatable_slots_WIRE_2[1], _allocatable_slots_T_81 connect _allocatable_slots_WIRE_2[2], _allocatable_slots_T_84 connect _allocatable_slots_WIRE_2[3], _allocatable_slots_T_87 connect _allocatable_slots_WIRE_2[4], _allocatable_slots_T_90 connect _allocatable_slots_WIRE_2[5], _allocatable_slots_T_93 node allocatable_slots_lo_hi_2 = cat(_allocatable_slots_WIRE_2[2], _allocatable_slots_WIRE_2[1]) node allocatable_slots_lo_2 = cat(allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2[0]) node allocatable_slots_hi_hi_2 = cat(_allocatable_slots_WIRE_2[5], _allocatable_slots_WIRE_2[4]) node allocatable_slots_hi_2 = cat(allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2[3]) node _allocatable_slots_T_94 = cat(allocatable_slots_hi_2, allocatable_slots_lo_2) node _allocatable_slots_T_95 = dshl(UInt<1>(0h1), _T_97) node _allocatable_slots_T_96 = dshr(_allocatable_slots_T_95, UInt<1>(0h0)) node _allocatable_slots_T_97 = dshr(_allocatable_slots_T_95, UInt<1>(0h1)) node _allocatable_slots_T_98 = dshr(_allocatable_slots_T_95, UInt<2>(0h2)) node _allocatable_slots_T_99 = dshr(_allocatable_slots_T_95, UInt<2>(0h3)) node _allocatable_slots_T_100 = dshr(_allocatable_slots_T_95, UInt<3>(0h4)) node _allocatable_slots_T_101 = dshr(_allocatable_slots_T_95, UInt<3>(0h5)) node _allocatable_slots_T_102 = dshr(_allocatable_slots_T_95, UInt<3>(0h6)) node _allocatable_slots_T_103 = dshr(_allocatable_slots_T_95, UInt<3>(0h7)) node _allocatable_slots_T_104 = or(_allocatable_slots_T_96, _allocatable_slots_T_97) node _allocatable_slots_T_105 = or(_allocatable_slots_T_104, _allocatable_slots_T_98) node _allocatable_slots_T_106 = or(_allocatable_slots_T_105, _allocatable_slots_T_99) node _allocatable_slots_T_107 = or(_allocatable_slots_T_106, _allocatable_slots_T_100) node _allocatable_slots_T_108 = or(_allocatable_slots_T_107, _allocatable_slots_T_101) node _allocatable_slots_T_109 = or(_allocatable_slots_T_108, _allocatable_slots_T_102) node _allocatable_slots_T_110 = or(_allocatable_slots_T_109, _allocatable_slots_T_103) node _allocatable_slots_T_111 = mux(_T_96, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_112 = and(_allocatable_slots_T_110, _allocatable_slots_T_111) node _allocatable_slots_T_113 = not(_allocatable_slots_T_112) node allocatable_slots_2 = and(_allocatable_slots_T_94, _allocatable_slots_T_113) inst alloc_lfsr_prng_2 of MaxPeriodFibonacciLFSR_23 connect alloc_lfsr_prng_2.clock, clock connect alloc_lfsr_prng_2.reset, reset connect alloc_lfsr_prng_2.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_2.io.seed.bits[0] invalidate alloc_lfsr_prng_2.io.seed.bits[1] invalidate alloc_lfsr_prng_2.io.seed.bits[2] invalidate alloc_lfsr_prng_2.io.seed.bits[3] invalidate alloc_lfsr_prng_2.io.seed.bits[4] invalidate alloc_lfsr_prng_2.io.seed.bits[5] connect alloc_lfsr_prng_2.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_2 = cat(alloc_lfsr_prng_2.io.out[2], alloc_lfsr_prng_2.io.out[1]) node alloc_lfsr_lo_2 = cat(alloc_lfsr_lo_hi_2, alloc_lfsr_prng_2.io.out[0]) node alloc_lfsr_hi_hi_2 = cat(alloc_lfsr_prng_2.io.out[5], alloc_lfsr_prng_2.io.out[4]) node alloc_lfsr_hi_2 = cat(alloc_lfsr_hi_hi_2, alloc_lfsr_prng_2.io.out[3]) node alloc_lfsr_2 = cat(alloc_lfsr_hi_2, alloc_lfsr_lo_2) node _first_entry_T_28 = bits(allocatable_slots_2, 0, 0) node _first_entry_T_29 = bits(allocatable_slots_2, 1, 1) node _first_entry_T_30 = bits(allocatable_slots_2, 2, 2) node _first_entry_T_31 = bits(allocatable_slots_2, 3, 3) node _first_entry_T_32 = bits(allocatable_slots_2, 4, 4) node _first_entry_T_33 = bits(allocatable_slots_2, 5, 5) node _first_entry_T_34 = bits(allocatable_slots_2, 6, 6) node _first_entry_T_35 = bits(allocatable_slots_2, 7, 7) node _first_entry_T_36 = mux(_first_entry_T_34, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_37 = mux(_first_entry_T_33, UInt<3>(0h5), _first_entry_T_36) node _first_entry_T_38 = mux(_first_entry_T_32, UInt<3>(0h4), _first_entry_T_37) node _first_entry_T_39 = mux(_first_entry_T_31, UInt<2>(0h3), _first_entry_T_38) node _first_entry_T_40 = mux(_first_entry_T_30, UInt<2>(0h2), _first_entry_T_39) node _first_entry_T_41 = mux(_first_entry_T_29, UInt<1>(0h1), _first_entry_T_40) node first_entry_2 = mux(_first_entry_T_28, UInt<1>(0h0), _first_entry_T_41) node _masked_entry_T_30 = and(allocatable_slots_2, alloc_lfsr_2) node _masked_entry_T_31 = bits(_masked_entry_T_30, 0, 0) node _masked_entry_T_32 = bits(_masked_entry_T_30, 1, 1) node _masked_entry_T_33 = bits(_masked_entry_T_30, 2, 2) node _masked_entry_T_34 = bits(_masked_entry_T_30, 3, 3) node _masked_entry_T_35 = bits(_masked_entry_T_30, 4, 4) node _masked_entry_T_36 = bits(_masked_entry_T_30, 5, 5) node _masked_entry_T_37 = bits(_masked_entry_T_30, 6, 6) node _masked_entry_T_38 = bits(_masked_entry_T_30, 7, 7) node _masked_entry_T_39 = mux(_masked_entry_T_37, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_40 = mux(_masked_entry_T_36, UInt<3>(0h5), _masked_entry_T_39) node _masked_entry_T_41 = mux(_masked_entry_T_35, UInt<3>(0h4), _masked_entry_T_40) node _masked_entry_T_42 = mux(_masked_entry_T_34, UInt<2>(0h3), _masked_entry_T_41) node _masked_entry_T_43 = mux(_masked_entry_T_33, UInt<2>(0h2), _masked_entry_T_42) node _masked_entry_T_44 = mux(_masked_entry_T_32, UInt<1>(0h1), _masked_entry_T_43) node masked_entry_2 = mux(_masked_entry_T_31, UInt<1>(0h0), _masked_entry_T_44) node _alloc_entry_T_4 = dshr(allocatable_slots_2, masked_entry_2) node _alloc_entry_T_5 = bits(_alloc_entry_T_4, 0, 0) node alloc_entry_2 = mux(_alloc_entry_T_5, masked_entry_2, first_entry_2) node _f3_meta_allocate_2_valid_T = neq(allocatable_slots_2, UInt<1>(0h0)) connect f3_meta.allocate[2].valid, _f3_meta_allocate_2_valid_T connect f3_meta.allocate[2].bits, alloc_entry_2 node _update_was_taken_T_4 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _update_was_taken_T_5 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_4) node update_was_taken_2 = and(_update_was_taken_T_5, s1_update.bits.cfi_taken) node _T_100 = bits(s1_update.bits.br_mask, 2, 2) node _T_101 = and(_T_100, s1_update.valid) node _T_102 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_103 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = and(_T_101, _T_105) when _T_106 : when s1_update_meta.provider[2].valid : connect s1_update_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) node _new_u_T_22 = bits(s1_update_mispredict_mask, 2, 2) node _new_u_T_23 = eq(s1_update_meta.alt_differs[2], UInt<1>(0h0)) node _new_u_T_24 = eq(s1_update_meta.provider_u[2], UInt<1>(0h0)) node _new_u_T_25 = sub(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_26 = tail(_new_u_T_25, 1) node _new_u_T_27 = mux(_new_u_T_24, UInt<1>(0h0), _new_u_T_26) node _new_u_T_28 = eq(s1_update_meta.provider_u[2], UInt<2>(0h3)) node _new_u_T_29 = add(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_30 = tail(_new_u_T_29, 1) node _new_u_T_31 = mux(_new_u_T_28, UInt<2>(0h3), _new_u_T_30) node _new_u_T_32 = mux(_new_u_T_22, _new_u_T_27, _new_u_T_31) node new_u_2 = mux(_new_u_T_23, s1_update_meta.provider_u[2], _new_u_T_32) connect s1_update_u[s1_update_meta.provider[2].bits][2], new_u_2 connect s1_update_taken[s1_update_meta.provider[2].bits][2], update_was_taken_2 connect s1_update_old_ctr[s1_update_meta.provider[2].bits][2], s1_update_meta.provider_ctr[2] connect s1_update_alloc[s1_update_meta.provider[2].bits][2], UInt<1>(0h0) wire final_altpred_3 : UInt<1> connect final_altpred_3, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, io.resp_in[0].f3[3].taken when f3_resps[0][3].valid : node _io_resp_f3_3_taken_T = eq(f3_resps[0][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_1 = eq(f3_resps[0][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_2 = or(_io_resp_f3_3_taken_T, _io_resp_f3_3_taken_T_1) node _io_resp_f3_3_taken_T_3 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_4 = mux(_io_resp_f3_3_taken_T_2, io.resp_in[0].f3[3].taken, _io_resp_f3_3_taken_T_3) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_4 connect final_altpred_3, io.resp_in[0].f3[3].taken node _T_107 = or(UInt<1>(0h0), f3_resps[0][3].valid) node _T_108 = mux(f3_resps[0][3].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_109 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _T_110 = mux(f3_resps[0][3].valid, _T_109, io.resp_in[0].f3[3].taken) when f3_resps[1][3].valid : node _io_resp_f3_3_taken_T_5 = eq(f3_resps[1][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_6 = eq(f3_resps[1][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_7 = or(_io_resp_f3_3_taken_T_5, _io_resp_f3_3_taken_T_6) node _io_resp_f3_3_taken_T_8 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_9 = mux(_io_resp_f3_3_taken_T_7, _T_110, _io_resp_f3_3_taken_T_8) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_9 connect final_altpred_3, _T_110 node _T_111 = or(_T_107, f3_resps[1][3].valid) node _T_112 = mux(f3_resps[1][3].valid, UInt<1>(0h1), _T_108) node _T_113 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _T_114 = mux(f3_resps[1][3].valid, _T_113, _T_110) when f3_resps[2][3].valid : node _io_resp_f3_3_taken_T_10 = eq(f3_resps[2][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_11 = eq(f3_resps[2][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_12 = or(_io_resp_f3_3_taken_T_10, _io_resp_f3_3_taken_T_11) node _io_resp_f3_3_taken_T_13 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_14 = mux(_io_resp_f3_3_taken_T_12, _T_114, _io_resp_f3_3_taken_T_13) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_14 connect final_altpred_3, _T_114 node _T_115 = or(_T_111, f3_resps[2][3].valid) node _T_116 = mux(f3_resps[2][3].valid, UInt<2>(0h2), _T_112) node _T_117 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _T_118 = mux(f3_resps[2][3].valid, _T_117, _T_114) when f3_resps[3][3].valid : node _io_resp_f3_3_taken_T_15 = eq(f3_resps[3][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_16 = eq(f3_resps[3][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_17 = or(_io_resp_f3_3_taken_T_15, _io_resp_f3_3_taken_T_16) node _io_resp_f3_3_taken_T_18 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_19 = mux(_io_resp_f3_3_taken_T_17, _T_118, _io_resp_f3_3_taken_T_18) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_19 connect final_altpred_3, _T_118 node _T_119 = or(_T_115, f3_resps[3][3].valid) node _T_120 = mux(f3_resps[3][3].valid, UInt<2>(0h3), _T_116) node _T_121 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _T_122 = mux(f3_resps[3][3].valid, _T_121, _T_118) when f3_resps[4][3].valid : node _io_resp_f3_3_taken_T_20 = eq(f3_resps[4][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_21 = eq(f3_resps[4][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_22 = or(_io_resp_f3_3_taken_T_20, _io_resp_f3_3_taken_T_21) node _io_resp_f3_3_taken_T_23 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_24 = mux(_io_resp_f3_3_taken_T_22, _T_122, _io_resp_f3_3_taken_T_23) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_24 connect final_altpred_3, _T_122 node _T_123 = or(_T_119, f3_resps[4][3].valid) node _T_124 = mux(f3_resps[4][3].valid, UInt<3>(0h4), _T_120) node _T_125 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _T_126 = mux(f3_resps[4][3].valid, _T_125, _T_122) when f3_resps[5][3].valid : node _io_resp_f3_3_taken_T_25 = eq(f3_resps[5][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_26 = eq(f3_resps[5][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_27 = or(_io_resp_f3_3_taken_T_25, _io_resp_f3_3_taken_T_26) node _io_resp_f3_3_taken_T_28 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_29 = mux(_io_resp_f3_3_taken_T_27, _T_126, _io_resp_f3_3_taken_T_28) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_29 connect final_altpred_3, _T_126 node _T_127 = or(_T_123, f3_resps[5][3].valid) node _T_128 = mux(f3_resps[5][3].valid, UInt<3>(0h5), _T_124) node _T_129 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _T_130 = mux(f3_resps[5][3].valid, _T_129, _T_126) connect f3_meta.provider[3].valid, _T_127 connect f3_meta.provider[3].bits, _T_128 node _f3_meta_alt_differs_3_T = neq(final_altpred_3, io.resp.f3[3].taken) connect f3_meta.alt_differs[3], _f3_meta_alt_differs_3_T connect f3_meta.provider_u[3], f3_resps[_T_128][3].bits.u connect f3_meta.provider_ctr[3], f3_resps[_T_128][3].bits.ctr node _allocatable_slots_T_114 = eq(f3_resps[0][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_115 = eq(f3_resps[0][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_116 = and(_allocatable_slots_T_114, _allocatable_slots_T_115) node _allocatable_slots_T_117 = eq(f3_resps[1][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_118 = eq(f3_resps[1][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_119 = and(_allocatable_slots_T_117, _allocatable_slots_T_118) node _allocatable_slots_T_120 = eq(f3_resps[2][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_121 = eq(f3_resps[2][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_122 = and(_allocatable_slots_T_120, _allocatable_slots_T_121) node _allocatable_slots_T_123 = eq(f3_resps[3][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_124 = eq(f3_resps[3][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_125 = and(_allocatable_slots_T_123, _allocatable_slots_T_124) node _allocatable_slots_T_126 = eq(f3_resps[4][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_127 = eq(f3_resps[4][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_128 = and(_allocatable_slots_T_126, _allocatable_slots_T_127) node _allocatable_slots_T_129 = eq(f3_resps[5][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_130 = eq(f3_resps[5][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_131 = and(_allocatable_slots_T_129, _allocatable_slots_T_130) wire _allocatable_slots_WIRE_3 : UInt<1>[6] connect _allocatable_slots_WIRE_3[0], _allocatable_slots_T_116 connect _allocatable_slots_WIRE_3[1], _allocatable_slots_T_119 connect _allocatable_slots_WIRE_3[2], _allocatable_slots_T_122 connect _allocatable_slots_WIRE_3[3], _allocatable_slots_T_125 connect _allocatable_slots_WIRE_3[4], _allocatable_slots_T_128 connect _allocatable_slots_WIRE_3[5], _allocatable_slots_T_131 node allocatable_slots_lo_hi_3 = cat(_allocatable_slots_WIRE_3[2], _allocatable_slots_WIRE_3[1]) node allocatable_slots_lo_3 = cat(allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3[0]) node allocatable_slots_hi_hi_3 = cat(_allocatable_slots_WIRE_3[5], _allocatable_slots_WIRE_3[4]) node allocatable_slots_hi_3 = cat(allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3[3]) node _allocatable_slots_T_132 = cat(allocatable_slots_hi_3, allocatable_slots_lo_3) node _allocatable_slots_T_133 = dshl(UInt<1>(0h1), _T_128) node _allocatable_slots_T_134 = dshr(_allocatable_slots_T_133, UInt<1>(0h0)) node _allocatable_slots_T_135 = dshr(_allocatable_slots_T_133, UInt<1>(0h1)) node _allocatable_slots_T_136 = dshr(_allocatable_slots_T_133, UInt<2>(0h2)) node _allocatable_slots_T_137 = dshr(_allocatable_slots_T_133, UInt<2>(0h3)) node _allocatable_slots_T_138 = dshr(_allocatable_slots_T_133, UInt<3>(0h4)) node _allocatable_slots_T_139 = dshr(_allocatable_slots_T_133, UInt<3>(0h5)) node _allocatable_slots_T_140 = dshr(_allocatable_slots_T_133, UInt<3>(0h6)) node _allocatable_slots_T_141 = dshr(_allocatable_slots_T_133, UInt<3>(0h7)) node _allocatable_slots_T_142 = or(_allocatable_slots_T_134, _allocatable_slots_T_135) node _allocatable_slots_T_143 = or(_allocatable_slots_T_142, _allocatable_slots_T_136) node _allocatable_slots_T_144 = or(_allocatable_slots_T_143, _allocatable_slots_T_137) node _allocatable_slots_T_145 = or(_allocatable_slots_T_144, _allocatable_slots_T_138) node _allocatable_slots_T_146 = or(_allocatable_slots_T_145, _allocatable_slots_T_139) node _allocatable_slots_T_147 = or(_allocatable_slots_T_146, _allocatable_slots_T_140) node _allocatable_slots_T_148 = or(_allocatable_slots_T_147, _allocatable_slots_T_141) node _allocatable_slots_T_149 = mux(_T_127, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_150 = and(_allocatable_slots_T_148, _allocatable_slots_T_149) node _allocatable_slots_T_151 = not(_allocatable_slots_T_150) node allocatable_slots_3 = and(_allocatable_slots_T_132, _allocatable_slots_T_151) inst alloc_lfsr_prng_3 of MaxPeriodFibonacciLFSR_24 connect alloc_lfsr_prng_3.clock, clock connect alloc_lfsr_prng_3.reset, reset connect alloc_lfsr_prng_3.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_3.io.seed.bits[0] invalidate alloc_lfsr_prng_3.io.seed.bits[1] invalidate alloc_lfsr_prng_3.io.seed.bits[2] invalidate alloc_lfsr_prng_3.io.seed.bits[3] invalidate alloc_lfsr_prng_3.io.seed.bits[4] invalidate alloc_lfsr_prng_3.io.seed.bits[5] connect alloc_lfsr_prng_3.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_3 = cat(alloc_lfsr_prng_3.io.out[2], alloc_lfsr_prng_3.io.out[1]) node alloc_lfsr_lo_3 = cat(alloc_lfsr_lo_hi_3, alloc_lfsr_prng_3.io.out[0]) node alloc_lfsr_hi_hi_3 = cat(alloc_lfsr_prng_3.io.out[5], alloc_lfsr_prng_3.io.out[4]) node alloc_lfsr_hi_3 = cat(alloc_lfsr_hi_hi_3, alloc_lfsr_prng_3.io.out[3]) node alloc_lfsr_3 = cat(alloc_lfsr_hi_3, alloc_lfsr_lo_3) node _first_entry_T_42 = bits(allocatable_slots_3, 0, 0) node _first_entry_T_43 = bits(allocatable_slots_3, 1, 1) node _first_entry_T_44 = bits(allocatable_slots_3, 2, 2) node _first_entry_T_45 = bits(allocatable_slots_3, 3, 3) node _first_entry_T_46 = bits(allocatable_slots_3, 4, 4) node _first_entry_T_47 = bits(allocatable_slots_3, 5, 5) node _first_entry_T_48 = bits(allocatable_slots_3, 6, 6) node _first_entry_T_49 = bits(allocatable_slots_3, 7, 7) node _first_entry_T_50 = mux(_first_entry_T_48, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_51 = mux(_first_entry_T_47, UInt<3>(0h5), _first_entry_T_50) node _first_entry_T_52 = mux(_first_entry_T_46, UInt<3>(0h4), _first_entry_T_51) node _first_entry_T_53 = mux(_first_entry_T_45, UInt<2>(0h3), _first_entry_T_52) node _first_entry_T_54 = mux(_first_entry_T_44, UInt<2>(0h2), _first_entry_T_53) node _first_entry_T_55 = mux(_first_entry_T_43, UInt<1>(0h1), _first_entry_T_54) node first_entry_3 = mux(_first_entry_T_42, UInt<1>(0h0), _first_entry_T_55) node _masked_entry_T_45 = and(allocatable_slots_3, alloc_lfsr_3) node _masked_entry_T_46 = bits(_masked_entry_T_45, 0, 0) node _masked_entry_T_47 = bits(_masked_entry_T_45, 1, 1) node _masked_entry_T_48 = bits(_masked_entry_T_45, 2, 2) node _masked_entry_T_49 = bits(_masked_entry_T_45, 3, 3) node _masked_entry_T_50 = bits(_masked_entry_T_45, 4, 4) node _masked_entry_T_51 = bits(_masked_entry_T_45, 5, 5) node _masked_entry_T_52 = bits(_masked_entry_T_45, 6, 6) node _masked_entry_T_53 = bits(_masked_entry_T_45, 7, 7) node _masked_entry_T_54 = mux(_masked_entry_T_52, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_55 = mux(_masked_entry_T_51, UInt<3>(0h5), _masked_entry_T_54) node _masked_entry_T_56 = mux(_masked_entry_T_50, UInt<3>(0h4), _masked_entry_T_55) node _masked_entry_T_57 = mux(_masked_entry_T_49, UInt<2>(0h3), _masked_entry_T_56) node _masked_entry_T_58 = mux(_masked_entry_T_48, UInt<2>(0h2), _masked_entry_T_57) node _masked_entry_T_59 = mux(_masked_entry_T_47, UInt<1>(0h1), _masked_entry_T_58) node masked_entry_3 = mux(_masked_entry_T_46, UInt<1>(0h0), _masked_entry_T_59) node _alloc_entry_T_6 = dshr(allocatable_slots_3, masked_entry_3) node _alloc_entry_T_7 = bits(_alloc_entry_T_6, 0, 0) node alloc_entry_3 = mux(_alloc_entry_T_7, masked_entry_3, first_entry_3) node _f3_meta_allocate_3_valid_T = neq(allocatable_slots_3, UInt<1>(0h0)) connect f3_meta.allocate[3].valid, _f3_meta_allocate_3_valid_T connect f3_meta.allocate[3].bits, alloc_entry_3 node _update_was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _update_was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_6) node update_was_taken_3 = and(_update_was_taken_T_7, s1_update.bits.cfi_taken) node _T_131 = bits(s1_update.bits.br_mask, 3, 3) node _T_132 = and(_T_131, s1_update.valid) node _T_133 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_134 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = and(_T_132, _T_136) when _T_137 : when s1_update_meta.provider[3].valid : connect s1_update_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) node _new_u_T_33 = bits(s1_update_mispredict_mask, 3, 3) node _new_u_T_34 = eq(s1_update_meta.alt_differs[3], UInt<1>(0h0)) node _new_u_T_35 = eq(s1_update_meta.provider_u[3], UInt<1>(0h0)) node _new_u_T_36 = sub(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_37 = tail(_new_u_T_36, 1) node _new_u_T_38 = mux(_new_u_T_35, UInt<1>(0h0), _new_u_T_37) node _new_u_T_39 = eq(s1_update_meta.provider_u[3], UInt<2>(0h3)) node _new_u_T_40 = add(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_41 = tail(_new_u_T_40, 1) node _new_u_T_42 = mux(_new_u_T_39, UInt<2>(0h3), _new_u_T_41) node _new_u_T_43 = mux(_new_u_T_33, _new_u_T_38, _new_u_T_42) node new_u_3 = mux(_new_u_T_34, s1_update_meta.provider_u[3], _new_u_T_43) connect s1_update_u[s1_update_meta.provider[3].bits][3], new_u_3 connect s1_update_taken[s1_update_meta.provider[3].bits][3], update_was_taken_3 connect s1_update_old_ctr[s1_update_meta.provider[3].bits][3], s1_update_meta.provider_ctr[3] connect s1_update_alloc[s1_update_meta.provider[3].bits][3], UInt<1>(0h0) node _T_138 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_139 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_140 = or(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = and(s1_update.valid, _T_141) node _T_143 = and(_T_142, s1_update.bits.cfi_mispredicted) node _T_144 = and(_T_143, s1_update.bits.cfi_idx.valid) when _T_144 : when s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].valid : connect s1_update_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_taken[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], s1_update.bits.cfi_taken connect s1_update_alloc[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) else : node _decr_mask_T = dshl(UInt<1>(0h1), s1_update_meta.provider[s1_update.bits.cfi_idx.bits].bits) node _decr_mask_T_1 = dshr(_decr_mask_T, UInt<1>(0h0)) node _decr_mask_T_2 = dshr(_decr_mask_T, UInt<1>(0h1)) node _decr_mask_T_3 = dshr(_decr_mask_T, UInt<2>(0h2)) node _decr_mask_T_4 = dshr(_decr_mask_T, UInt<2>(0h3)) node _decr_mask_T_5 = dshr(_decr_mask_T, UInt<3>(0h4)) node _decr_mask_T_6 = dshr(_decr_mask_T, UInt<3>(0h5)) node _decr_mask_T_7 = dshr(_decr_mask_T, UInt<3>(0h6)) node _decr_mask_T_8 = dshr(_decr_mask_T, UInt<3>(0h7)) node _decr_mask_T_9 = or(_decr_mask_T_1, _decr_mask_T_2) node _decr_mask_T_10 = or(_decr_mask_T_9, _decr_mask_T_3) node _decr_mask_T_11 = or(_decr_mask_T_10, _decr_mask_T_4) node _decr_mask_T_12 = or(_decr_mask_T_11, _decr_mask_T_5) node _decr_mask_T_13 = or(_decr_mask_T_12, _decr_mask_T_6) node _decr_mask_T_14 = or(_decr_mask_T_13, _decr_mask_T_7) node _decr_mask_T_15 = or(_decr_mask_T_14, _decr_mask_T_8) node _decr_mask_T_16 = not(_decr_mask_T_15) node decr_mask = mux(s1_update_meta.provider[s1_update.bits.cfi_idx.bits].valid, _decr_mask_T_16, UInt<1>(0h0)) node _T_145 = bits(decr_mask, 0, 0) when _T_145 : connect s1_update_u_mask[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_146 = bits(decr_mask, 1, 1) when _T_146 : connect s1_update_u_mask[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_147 = bits(decr_mask, 2, 2) when _T_147 : connect s1_update_u_mask[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_148 = bits(decr_mask, 3, 3) when _T_148 : connect s1_update_u_mask[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_149 = bits(decr_mask, 4, 4) when _T_149 : connect s1_update_u_mask[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_150 = bits(decr_mask, 5, 5) when _T_150 : connect s1_update_u_mask[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) reg tt_0_1_io_update_mask_0_REG : UInt<1>, clock connect tt_0_1_io_update_mask_0_REG, s1_update_mask[0][0] connect tt_0_1.io.update_mask[0], tt_0_1_io_update_mask_0_REG reg tt_0_1_io_update_taken_0_REG : UInt<1>, clock connect tt_0_1_io_update_taken_0_REG, s1_update_taken[0][0] connect tt_0_1.io.update_taken[0], tt_0_1_io_update_taken_0_REG reg tt_0_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_0_REG, s1_update_alloc[0][0] connect tt_0_1.io.update_alloc[0], tt_0_1_io_update_alloc_0_REG reg tt_0_1_io_update_old_ctr_0_REG : UInt, clock connect tt_0_1_io_update_old_ctr_0_REG, s1_update_old_ctr[0][0] connect tt_0_1.io.update_old_ctr[0], tt_0_1_io_update_old_ctr_0_REG reg tt_0_1_io_update_u_mask_0_REG : UInt, clock connect tt_0_1_io_update_u_mask_0_REG, s1_update_u_mask[0][0] connect tt_0_1.io.update_u_mask[0], tt_0_1_io_update_u_mask_0_REG reg tt_0_1_io_update_u_0_REG : UInt, clock connect tt_0_1_io_update_u_0_REG, s1_update_u[0][0] connect tt_0_1.io.update_u[0], tt_0_1_io_update_u_0_REG reg tt_0_1_io_update_mask_1_REG : UInt<1>, clock connect tt_0_1_io_update_mask_1_REG, s1_update_mask[0][1] connect tt_0_1.io.update_mask[1], tt_0_1_io_update_mask_1_REG reg tt_0_1_io_update_taken_1_REG : UInt<1>, clock connect tt_0_1_io_update_taken_1_REG, s1_update_taken[0][1] connect tt_0_1.io.update_taken[1], tt_0_1_io_update_taken_1_REG reg tt_0_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_1_REG, s1_update_alloc[0][1] connect tt_0_1.io.update_alloc[1], tt_0_1_io_update_alloc_1_REG reg tt_0_1_io_update_old_ctr_1_REG : UInt, clock connect tt_0_1_io_update_old_ctr_1_REG, s1_update_old_ctr[0][1] connect tt_0_1.io.update_old_ctr[1], tt_0_1_io_update_old_ctr_1_REG reg tt_0_1_io_update_u_mask_1_REG : UInt, clock connect tt_0_1_io_update_u_mask_1_REG, s1_update_u_mask[0][1] connect tt_0_1.io.update_u_mask[1], tt_0_1_io_update_u_mask_1_REG reg tt_0_1_io_update_u_1_REG : UInt, clock connect tt_0_1_io_update_u_1_REG, s1_update_u[0][1] connect tt_0_1.io.update_u[1], tt_0_1_io_update_u_1_REG reg tt_0_1_io_update_mask_2_REG : UInt<1>, clock connect tt_0_1_io_update_mask_2_REG, s1_update_mask[0][2] connect tt_0_1.io.update_mask[2], tt_0_1_io_update_mask_2_REG reg tt_0_1_io_update_taken_2_REG : UInt<1>, clock connect tt_0_1_io_update_taken_2_REG, s1_update_taken[0][2] connect tt_0_1.io.update_taken[2], tt_0_1_io_update_taken_2_REG reg tt_0_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_2_REG, s1_update_alloc[0][2] connect tt_0_1.io.update_alloc[2], tt_0_1_io_update_alloc_2_REG reg tt_0_1_io_update_old_ctr_2_REG : UInt, clock connect tt_0_1_io_update_old_ctr_2_REG, s1_update_old_ctr[0][2] connect tt_0_1.io.update_old_ctr[2], tt_0_1_io_update_old_ctr_2_REG reg tt_0_1_io_update_u_mask_2_REG : UInt, clock connect tt_0_1_io_update_u_mask_2_REG, s1_update_u_mask[0][2] connect tt_0_1.io.update_u_mask[2], tt_0_1_io_update_u_mask_2_REG reg tt_0_1_io_update_u_2_REG : UInt, clock connect tt_0_1_io_update_u_2_REG, s1_update_u[0][2] connect tt_0_1.io.update_u[2], tt_0_1_io_update_u_2_REG reg tt_0_1_io_update_mask_3_REG : UInt<1>, clock connect tt_0_1_io_update_mask_3_REG, s1_update_mask[0][3] connect tt_0_1.io.update_mask[3], tt_0_1_io_update_mask_3_REG reg tt_0_1_io_update_taken_3_REG : UInt<1>, clock connect tt_0_1_io_update_taken_3_REG, s1_update_taken[0][3] connect tt_0_1.io.update_taken[3], tt_0_1_io_update_taken_3_REG reg tt_0_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_3_REG, s1_update_alloc[0][3] connect tt_0_1.io.update_alloc[3], tt_0_1_io_update_alloc_3_REG reg tt_0_1_io_update_old_ctr_3_REG : UInt, clock connect tt_0_1_io_update_old_ctr_3_REG, s1_update_old_ctr[0][3] connect tt_0_1.io.update_old_ctr[3], tt_0_1_io_update_old_ctr_3_REG reg tt_0_1_io_update_u_mask_3_REG : UInt, clock connect tt_0_1_io_update_u_mask_3_REG, s1_update_u_mask[0][3] connect tt_0_1.io.update_u_mask[3], tt_0_1_io_update_u_mask_3_REG reg tt_0_1_io_update_u_3_REG : UInt, clock connect tt_0_1_io_update_u_3_REG, s1_update_u[0][3] connect tt_0_1.io.update_u[3], tt_0_1_io_update_u_3_REG reg tt_0_1_io_update_pc_REG : UInt, clock connect tt_0_1_io_update_pc_REG, s1_update.bits.pc connect tt_0_1.io.update_pc, tt_0_1_io_update_pc_REG reg tt_0_1_io_update_hist_REG : UInt, clock connect tt_0_1_io_update_hist_REG, s1_update.bits.ghist connect tt_0_1.io.update_hist, tt_0_1_io_update_hist_REG reg tt_1_1_io_update_mask_0_REG : UInt<1>, clock connect tt_1_1_io_update_mask_0_REG, s1_update_mask[1][0] connect tt_1_1.io.update_mask[0], tt_1_1_io_update_mask_0_REG reg tt_1_1_io_update_taken_0_REG : UInt<1>, clock connect tt_1_1_io_update_taken_0_REG, s1_update_taken[1][0] connect tt_1_1.io.update_taken[0], tt_1_1_io_update_taken_0_REG reg tt_1_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_0_REG, s1_update_alloc[1][0] connect tt_1_1.io.update_alloc[0], tt_1_1_io_update_alloc_0_REG reg tt_1_1_io_update_old_ctr_0_REG : UInt, clock connect tt_1_1_io_update_old_ctr_0_REG, s1_update_old_ctr[1][0] connect tt_1_1.io.update_old_ctr[0], tt_1_1_io_update_old_ctr_0_REG reg tt_1_1_io_update_u_mask_0_REG : UInt, clock connect tt_1_1_io_update_u_mask_0_REG, s1_update_u_mask[1][0] connect tt_1_1.io.update_u_mask[0], tt_1_1_io_update_u_mask_0_REG reg tt_1_1_io_update_u_0_REG : UInt, clock connect tt_1_1_io_update_u_0_REG, s1_update_u[1][0] connect tt_1_1.io.update_u[0], tt_1_1_io_update_u_0_REG reg tt_1_1_io_update_mask_1_REG : UInt<1>, clock connect tt_1_1_io_update_mask_1_REG, s1_update_mask[1][1] connect tt_1_1.io.update_mask[1], tt_1_1_io_update_mask_1_REG reg tt_1_1_io_update_taken_1_REG : UInt<1>, clock connect tt_1_1_io_update_taken_1_REG, s1_update_taken[1][1] connect tt_1_1.io.update_taken[1], tt_1_1_io_update_taken_1_REG reg tt_1_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_1_REG, s1_update_alloc[1][1] connect tt_1_1.io.update_alloc[1], tt_1_1_io_update_alloc_1_REG reg tt_1_1_io_update_old_ctr_1_REG : UInt, clock connect tt_1_1_io_update_old_ctr_1_REG, s1_update_old_ctr[1][1] connect tt_1_1.io.update_old_ctr[1], tt_1_1_io_update_old_ctr_1_REG reg tt_1_1_io_update_u_mask_1_REG : UInt, clock connect tt_1_1_io_update_u_mask_1_REG, s1_update_u_mask[1][1] connect tt_1_1.io.update_u_mask[1], tt_1_1_io_update_u_mask_1_REG reg tt_1_1_io_update_u_1_REG : UInt, clock connect tt_1_1_io_update_u_1_REG, s1_update_u[1][1] connect tt_1_1.io.update_u[1], tt_1_1_io_update_u_1_REG reg tt_1_1_io_update_mask_2_REG : UInt<1>, clock connect tt_1_1_io_update_mask_2_REG, s1_update_mask[1][2] connect tt_1_1.io.update_mask[2], tt_1_1_io_update_mask_2_REG reg tt_1_1_io_update_taken_2_REG : UInt<1>, clock connect tt_1_1_io_update_taken_2_REG, s1_update_taken[1][2] connect tt_1_1.io.update_taken[2], tt_1_1_io_update_taken_2_REG reg tt_1_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_2_REG, s1_update_alloc[1][2] connect tt_1_1.io.update_alloc[2], tt_1_1_io_update_alloc_2_REG reg tt_1_1_io_update_old_ctr_2_REG : UInt, clock connect tt_1_1_io_update_old_ctr_2_REG, s1_update_old_ctr[1][2] connect tt_1_1.io.update_old_ctr[2], tt_1_1_io_update_old_ctr_2_REG reg tt_1_1_io_update_u_mask_2_REG : UInt, clock connect tt_1_1_io_update_u_mask_2_REG, s1_update_u_mask[1][2] connect tt_1_1.io.update_u_mask[2], tt_1_1_io_update_u_mask_2_REG reg tt_1_1_io_update_u_2_REG : UInt, clock connect tt_1_1_io_update_u_2_REG, s1_update_u[1][2] connect tt_1_1.io.update_u[2], tt_1_1_io_update_u_2_REG reg tt_1_1_io_update_mask_3_REG : UInt<1>, clock connect tt_1_1_io_update_mask_3_REG, s1_update_mask[1][3] connect tt_1_1.io.update_mask[3], tt_1_1_io_update_mask_3_REG reg tt_1_1_io_update_taken_3_REG : UInt<1>, clock connect tt_1_1_io_update_taken_3_REG, s1_update_taken[1][3] connect tt_1_1.io.update_taken[3], tt_1_1_io_update_taken_3_REG reg tt_1_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_3_REG, s1_update_alloc[1][3] connect tt_1_1.io.update_alloc[3], tt_1_1_io_update_alloc_3_REG reg tt_1_1_io_update_old_ctr_3_REG : UInt, clock connect tt_1_1_io_update_old_ctr_3_REG, s1_update_old_ctr[1][3] connect tt_1_1.io.update_old_ctr[3], tt_1_1_io_update_old_ctr_3_REG reg tt_1_1_io_update_u_mask_3_REG : UInt, clock connect tt_1_1_io_update_u_mask_3_REG, s1_update_u_mask[1][3] connect tt_1_1.io.update_u_mask[3], tt_1_1_io_update_u_mask_3_REG reg tt_1_1_io_update_u_3_REG : UInt, clock connect tt_1_1_io_update_u_3_REG, s1_update_u[1][3] connect tt_1_1.io.update_u[3], tt_1_1_io_update_u_3_REG reg tt_1_1_io_update_pc_REG : UInt, clock connect tt_1_1_io_update_pc_REG, s1_update.bits.pc connect tt_1_1.io.update_pc, tt_1_1_io_update_pc_REG reg tt_1_1_io_update_hist_REG : UInt, clock connect tt_1_1_io_update_hist_REG, s1_update.bits.ghist connect tt_1_1.io.update_hist, tt_1_1_io_update_hist_REG reg tt_2_1_io_update_mask_0_REG : UInt<1>, clock connect tt_2_1_io_update_mask_0_REG, s1_update_mask[2][0] connect tt_2_1.io.update_mask[0], tt_2_1_io_update_mask_0_REG reg tt_2_1_io_update_taken_0_REG : UInt<1>, clock connect tt_2_1_io_update_taken_0_REG, s1_update_taken[2][0] connect tt_2_1.io.update_taken[0], tt_2_1_io_update_taken_0_REG reg tt_2_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_0_REG, s1_update_alloc[2][0] connect tt_2_1.io.update_alloc[0], tt_2_1_io_update_alloc_0_REG reg tt_2_1_io_update_old_ctr_0_REG : UInt, clock connect tt_2_1_io_update_old_ctr_0_REG, s1_update_old_ctr[2][0] connect tt_2_1.io.update_old_ctr[0], tt_2_1_io_update_old_ctr_0_REG reg tt_2_1_io_update_u_mask_0_REG : UInt, clock connect tt_2_1_io_update_u_mask_0_REG, s1_update_u_mask[2][0] connect tt_2_1.io.update_u_mask[0], tt_2_1_io_update_u_mask_0_REG reg tt_2_1_io_update_u_0_REG : UInt, clock connect tt_2_1_io_update_u_0_REG, s1_update_u[2][0] connect tt_2_1.io.update_u[0], tt_2_1_io_update_u_0_REG reg tt_2_1_io_update_mask_1_REG : UInt<1>, clock connect tt_2_1_io_update_mask_1_REG, s1_update_mask[2][1] connect tt_2_1.io.update_mask[1], tt_2_1_io_update_mask_1_REG reg tt_2_1_io_update_taken_1_REG : UInt<1>, clock connect tt_2_1_io_update_taken_1_REG, s1_update_taken[2][1] connect tt_2_1.io.update_taken[1], tt_2_1_io_update_taken_1_REG reg tt_2_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_1_REG, s1_update_alloc[2][1] connect tt_2_1.io.update_alloc[1], tt_2_1_io_update_alloc_1_REG reg tt_2_1_io_update_old_ctr_1_REG : UInt, clock connect tt_2_1_io_update_old_ctr_1_REG, s1_update_old_ctr[2][1] connect tt_2_1.io.update_old_ctr[1], tt_2_1_io_update_old_ctr_1_REG reg tt_2_1_io_update_u_mask_1_REG : UInt, clock connect tt_2_1_io_update_u_mask_1_REG, s1_update_u_mask[2][1] connect tt_2_1.io.update_u_mask[1], tt_2_1_io_update_u_mask_1_REG reg tt_2_1_io_update_u_1_REG : UInt, clock connect tt_2_1_io_update_u_1_REG, s1_update_u[2][1] connect tt_2_1.io.update_u[1], tt_2_1_io_update_u_1_REG reg tt_2_1_io_update_mask_2_REG : UInt<1>, clock connect tt_2_1_io_update_mask_2_REG, s1_update_mask[2][2] connect tt_2_1.io.update_mask[2], tt_2_1_io_update_mask_2_REG reg tt_2_1_io_update_taken_2_REG : UInt<1>, clock connect tt_2_1_io_update_taken_2_REG, s1_update_taken[2][2] connect tt_2_1.io.update_taken[2], tt_2_1_io_update_taken_2_REG reg tt_2_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_2_REG, s1_update_alloc[2][2] connect tt_2_1.io.update_alloc[2], tt_2_1_io_update_alloc_2_REG reg tt_2_1_io_update_old_ctr_2_REG : UInt, clock connect tt_2_1_io_update_old_ctr_2_REG, s1_update_old_ctr[2][2] connect tt_2_1.io.update_old_ctr[2], tt_2_1_io_update_old_ctr_2_REG reg tt_2_1_io_update_u_mask_2_REG : UInt, clock connect tt_2_1_io_update_u_mask_2_REG, s1_update_u_mask[2][2] connect tt_2_1.io.update_u_mask[2], tt_2_1_io_update_u_mask_2_REG reg tt_2_1_io_update_u_2_REG : UInt, clock connect tt_2_1_io_update_u_2_REG, s1_update_u[2][2] connect tt_2_1.io.update_u[2], tt_2_1_io_update_u_2_REG reg tt_2_1_io_update_mask_3_REG : UInt<1>, clock connect tt_2_1_io_update_mask_3_REG, s1_update_mask[2][3] connect tt_2_1.io.update_mask[3], tt_2_1_io_update_mask_3_REG reg tt_2_1_io_update_taken_3_REG : UInt<1>, clock connect tt_2_1_io_update_taken_3_REG, s1_update_taken[2][3] connect tt_2_1.io.update_taken[3], tt_2_1_io_update_taken_3_REG reg tt_2_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_3_REG, s1_update_alloc[2][3] connect tt_2_1.io.update_alloc[3], tt_2_1_io_update_alloc_3_REG reg tt_2_1_io_update_old_ctr_3_REG : UInt, clock connect tt_2_1_io_update_old_ctr_3_REG, s1_update_old_ctr[2][3] connect tt_2_1.io.update_old_ctr[3], tt_2_1_io_update_old_ctr_3_REG reg tt_2_1_io_update_u_mask_3_REG : UInt, clock connect tt_2_1_io_update_u_mask_3_REG, s1_update_u_mask[2][3] connect tt_2_1.io.update_u_mask[3], tt_2_1_io_update_u_mask_3_REG reg tt_2_1_io_update_u_3_REG : UInt, clock connect tt_2_1_io_update_u_3_REG, s1_update_u[2][3] connect tt_2_1.io.update_u[3], tt_2_1_io_update_u_3_REG reg tt_2_1_io_update_pc_REG : UInt, clock connect tt_2_1_io_update_pc_REG, s1_update.bits.pc connect tt_2_1.io.update_pc, tt_2_1_io_update_pc_REG reg tt_2_1_io_update_hist_REG : UInt, clock connect tt_2_1_io_update_hist_REG, s1_update.bits.ghist connect tt_2_1.io.update_hist, tt_2_1_io_update_hist_REG reg tt_3_1_io_update_mask_0_REG : UInt<1>, clock connect tt_3_1_io_update_mask_0_REG, s1_update_mask[3][0] connect tt_3_1.io.update_mask[0], tt_3_1_io_update_mask_0_REG reg tt_3_1_io_update_taken_0_REG : UInt<1>, clock connect tt_3_1_io_update_taken_0_REG, s1_update_taken[3][0] connect tt_3_1.io.update_taken[0], tt_3_1_io_update_taken_0_REG reg tt_3_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_0_REG, s1_update_alloc[3][0] connect tt_3_1.io.update_alloc[0], tt_3_1_io_update_alloc_0_REG reg tt_3_1_io_update_old_ctr_0_REG : UInt, clock connect tt_3_1_io_update_old_ctr_0_REG, s1_update_old_ctr[3][0] connect tt_3_1.io.update_old_ctr[0], tt_3_1_io_update_old_ctr_0_REG reg tt_3_1_io_update_u_mask_0_REG : UInt, clock connect tt_3_1_io_update_u_mask_0_REG, s1_update_u_mask[3][0] connect tt_3_1.io.update_u_mask[0], tt_3_1_io_update_u_mask_0_REG reg tt_3_1_io_update_u_0_REG : UInt, clock connect tt_3_1_io_update_u_0_REG, s1_update_u[3][0] connect tt_3_1.io.update_u[0], tt_3_1_io_update_u_0_REG reg tt_3_1_io_update_mask_1_REG : UInt<1>, clock connect tt_3_1_io_update_mask_1_REG, s1_update_mask[3][1] connect tt_3_1.io.update_mask[1], tt_3_1_io_update_mask_1_REG reg tt_3_1_io_update_taken_1_REG : UInt<1>, clock connect tt_3_1_io_update_taken_1_REG, s1_update_taken[3][1] connect tt_3_1.io.update_taken[1], tt_3_1_io_update_taken_1_REG reg tt_3_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_1_REG, s1_update_alloc[3][1] connect tt_3_1.io.update_alloc[1], tt_3_1_io_update_alloc_1_REG reg tt_3_1_io_update_old_ctr_1_REG : UInt, clock connect tt_3_1_io_update_old_ctr_1_REG, s1_update_old_ctr[3][1] connect tt_3_1.io.update_old_ctr[1], tt_3_1_io_update_old_ctr_1_REG reg tt_3_1_io_update_u_mask_1_REG : UInt, clock connect tt_3_1_io_update_u_mask_1_REG, s1_update_u_mask[3][1] connect tt_3_1.io.update_u_mask[1], tt_3_1_io_update_u_mask_1_REG reg tt_3_1_io_update_u_1_REG : UInt, clock connect tt_3_1_io_update_u_1_REG, s1_update_u[3][1] connect tt_3_1.io.update_u[1], tt_3_1_io_update_u_1_REG reg tt_3_1_io_update_mask_2_REG : UInt<1>, clock connect tt_3_1_io_update_mask_2_REG, s1_update_mask[3][2] connect tt_3_1.io.update_mask[2], tt_3_1_io_update_mask_2_REG reg tt_3_1_io_update_taken_2_REG : UInt<1>, clock connect tt_3_1_io_update_taken_2_REG, s1_update_taken[3][2] connect tt_3_1.io.update_taken[2], tt_3_1_io_update_taken_2_REG reg tt_3_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_2_REG, s1_update_alloc[3][2] connect tt_3_1.io.update_alloc[2], tt_3_1_io_update_alloc_2_REG reg tt_3_1_io_update_old_ctr_2_REG : UInt, clock connect tt_3_1_io_update_old_ctr_2_REG, s1_update_old_ctr[3][2] connect tt_3_1.io.update_old_ctr[2], tt_3_1_io_update_old_ctr_2_REG reg tt_3_1_io_update_u_mask_2_REG : UInt, clock connect tt_3_1_io_update_u_mask_2_REG, s1_update_u_mask[3][2] connect tt_3_1.io.update_u_mask[2], tt_3_1_io_update_u_mask_2_REG reg tt_3_1_io_update_u_2_REG : UInt, clock connect tt_3_1_io_update_u_2_REG, s1_update_u[3][2] connect tt_3_1.io.update_u[2], tt_3_1_io_update_u_2_REG reg tt_3_1_io_update_mask_3_REG : UInt<1>, clock connect tt_3_1_io_update_mask_3_REG, s1_update_mask[3][3] connect tt_3_1.io.update_mask[3], tt_3_1_io_update_mask_3_REG reg tt_3_1_io_update_taken_3_REG : UInt<1>, clock connect tt_3_1_io_update_taken_3_REG, s1_update_taken[3][3] connect tt_3_1.io.update_taken[3], tt_3_1_io_update_taken_3_REG reg tt_3_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_3_REG, s1_update_alloc[3][3] connect tt_3_1.io.update_alloc[3], tt_3_1_io_update_alloc_3_REG reg tt_3_1_io_update_old_ctr_3_REG : UInt, clock connect tt_3_1_io_update_old_ctr_3_REG, s1_update_old_ctr[3][3] connect tt_3_1.io.update_old_ctr[3], tt_3_1_io_update_old_ctr_3_REG reg tt_3_1_io_update_u_mask_3_REG : UInt, clock connect tt_3_1_io_update_u_mask_3_REG, s1_update_u_mask[3][3] connect tt_3_1.io.update_u_mask[3], tt_3_1_io_update_u_mask_3_REG reg tt_3_1_io_update_u_3_REG : UInt, clock connect tt_3_1_io_update_u_3_REG, s1_update_u[3][3] connect tt_3_1.io.update_u[3], tt_3_1_io_update_u_3_REG reg tt_3_1_io_update_pc_REG : UInt, clock connect tt_3_1_io_update_pc_REG, s1_update.bits.pc connect tt_3_1.io.update_pc, tt_3_1_io_update_pc_REG reg tt_3_1_io_update_hist_REG : UInt, clock connect tt_3_1_io_update_hist_REG, s1_update.bits.ghist connect tt_3_1.io.update_hist, tt_3_1_io_update_hist_REG reg tt_4_1_io_update_mask_0_REG : UInt<1>, clock connect tt_4_1_io_update_mask_0_REG, s1_update_mask[4][0] connect tt_4_1.io.update_mask[0], tt_4_1_io_update_mask_0_REG reg tt_4_1_io_update_taken_0_REG : UInt<1>, clock connect tt_4_1_io_update_taken_0_REG, s1_update_taken[4][0] connect tt_4_1.io.update_taken[0], tt_4_1_io_update_taken_0_REG reg tt_4_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_0_REG, s1_update_alloc[4][0] connect tt_4_1.io.update_alloc[0], tt_4_1_io_update_alloc_0_REG reg tt_4_1_io_update_old_ctr_0_REG : UInt, clock connect tt_4_1_io_update_old_ctr_0_REG, s1_update_old_ctr[4][0] connect tt_4_1.io.update_old_ctr[0], tt_4_1_io_update_old_ctr_0_REG reg tt_4_1_io_update_u_mask_0_REG : UInt, clock connect tt_4_1_io_update_u_mask_0_REG, s1_update_u_mask[4][0] connect tt_4_1.io.update_u_mask[0], tt_4_1_io_update_u_mask_0_REG reg tt_4_1_io_update_u_0_REG : UInt, clock connect tt_4_1_io_update_u_0_REG, s1_update_u[4][0] connect tt_4_1.io.update_u[0], tt_4_1_io_update_u_0_REG reg tt_4_1_io_update_mask_1_REG : UInt<1>, clock connect tt_4_1_io_update_mask_1_REG, s1_update_mask[4][1] connect tt_4_1.io.update_mask[1], tt_4_1_io_update_mask_1_REG reg tt_4_1_io_update_taken_1_REG : UInt<1>, clock connect tt_4_1_io_update_taken_1_REG, s1_update_taken[4][1] connect tt_4_1.io.update_taken[1], tt_4_1_io_update_taken_1_REG reg tt_4_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_1_REG, s1_update_alloc[4][1] connect tt_4_1.io.update_alloc[1], tt_4_1_io_update_alloc_1_REG reg tt_4_1_io_update_old_ctr_1_REG : UInt, clock connect tt_4_1_io_update_old_ctr_1_REG, s1_update_old_ctr[4][1] connect tt_4_1.io.update_old_ctr[1], tt_4_1_io_update_old_ctr_1_REG reg tt_4_1_io_update_u_mask_1_REG : UInt, clock connect tt_4_1_io_update_u_mask_1_REG, s1_update_u_mask[4][1] connect tt_4_1.io.update_u_mask[1], tt_4_1_io_update_u_mask_1_REG reg tt_4_1_io_update_u_1_REG : UInt, clock connect tt_4_1_io_update_u_1_REG, s1_update_u[4][1] connect tt_4_1.io.update_u[1], tt_4_1_io_update_u_1_REG reg tt_4_1_io_update_mask_2_REG : UInt<1>, clock connect tt_4_1_io_update_mask_2_REG, s1_update_mask[4][2] connect tt_4_1.io.update_mask[2], tt_4_1_io_update_mask_2_REG reg tt_4_1_io_update_taken_2_REG : UInt<1>, clock connect tt_4_1_io_update_taken_2_REG, s1_update_taken[4][2] connect tt_4_1.io.update_taken[2], tt_4_1_io_update_taken_2_REG reg tt_4_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_2_REG, s1_update_alloc[4][2] connect tt_4_1.io.update_alloc[2], tt_4_1_io_update_alloc_2_REG reg tt_4_1_io_update_old_ctr_2_REG : UInt, clock connect tt_4_1_io_update_old_ctr_2_REG, s1_update_old_ctr[4][2] connect tt_4_1.io.update_old_ctr[2], tt_4_1_io_update_old_ctr_2_REG reg tt_4_1_io_update_u_mask_2_REG : UInt, clock connect tt_4_1_io_update_u_mask_2_REG, s1_update_u_mask[4][2] connect tt_4_1.io.update_u_mask[2], tt_4_1_io_update_u_mask_2_REG reg tt_4_1_io_update_u_2_REG : UInt, clock connect tt_4_1_io_update_u_2_REG, s1_update_u[4][2] connect tt_4_1.io.update_u[2], tt_4_1_io_update_u_2_REG reg tt_4_1_io_update_mask_3_REG : UInt<1>, clock connect tt_4_1_io_update_mask_3_REG, s1_update_mask[4][3] connect tt_4_1.io.update_mask[3], tt_4_1_io_update_mask_3_REG reg tt_4_1_io_update_taken_3_REG : UInt<1>, clock connect tt_4_1_io_update_taken_3_REG, s1_update_taken[4][3] connect tt_4_1.io.update_taken[3], tt_4_1_io_update_taken_3_REG reg tt_4_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_3_REG, s1_update_alloc[4][3] connect tt_4_1.io.update_alloc[3], tt_4_1_io_update_alloc_3_REG reg tt_4_1_io_update_old_ctr_3_REG : UInt, clock connect tt_4_1_io_update_old_ctr_3_REG, s1_update_old_ctr[4][3] connect tt_4_1.io.update_old_ctr[3], tt_4_1_io_update_old_ctr_3_REG reg tt_4_1_io_update_u_mask_3_REG : UInt, clock connect tt_4_1_io_update_u_mask_3_REG, s1_update_u_mask[4][3] connect tt_4_1.io.update_u_mask[3], tt_4_1_io_update_u_mask_3_REG reg tt_4_1_io_update_u_3_REG : UInt, clock connect tt_4_1_io_update_u_3_REG, s1_update_u[4][3] connect tt_4_1.io.update_u[3], tt_4_1_io_update_u_3_REG reg tt_4_1_io_update_pc_REG : UInt, clock connect tt_4_1_io_update_pc_REG, s1_update.bits.pc connect tt_4_1.io.update_pc, tt_4_1_io_update_pc_REG reg tt_4_1_io_update_hist_REG : UInt, clock connect tt_4_1_io_update_hist_REG, s1_update.bits.ghist connect tt_4_1.io.update_hist, tt_4_1_io_update_hist_REG reg tt_5_1_io_update_mask_0_REG : UInt<1>, clock connect tt_5_1_io_update_mask_0_REG, s1_update_mask[5][0] connect tt_5_1.io.update_mask[0], tt_5_1_io_update_mask_0_REG reg tt_5_1_io_update_taken_0_REG : UInt<1>, clock connect tt_5_1_io_update_taken_0_REG, s1_update_taken[5][0] connect tt_5_1.io.update_taken[0], tt_5_1_io_update_taken_0_REG reg tt_5_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_0_REG, s1_update_alloc[5][0] connect tt_5_1.io.update_alloc[0], tt_5_1_io_update_alloc_0_REG reg tt_5_1_io_update_old_ctr_0_REG : UInt, clock connect tt_5_1_io_update_old_ctr_0_REG, s1_update_old_ctr[5][0] connect tt_5_1.io.update_old_ctr[0], tt_5_1_io_update_old_ctr_0_REG reg tt_5_1_io_update_u_mask_0_REG : UInt, clock connect tt_5_1_io_update_u_mask_0_REG, s1_update_u_mask[5][0] connect tt_5_1.io.update_u_mask[0], tt_5_1_io_update_u_mask_0_REG reg tt_5_1_io_update_u_0_REG : UInt, clock connect tt_5_1_io_update_u_0_REG, s1_update_u[5][0] connect tt_5_1.io.update_u[0], tt_5_1_io_update_u_0_REG reg tt_5_1_io_update_mask_1_REG : UInt<1>, clock connect tt_5_1_io_update_mask_1_REG, s1_update_mask[5][1] connect tt_5_1.io.update_mask[1], tt_5_1_io_update_mask_1_REG reg tt_5_1_io_update_taken_1_REG : UInt<1>, clock connect tt_5_1_io_update_taken_1_REG, s1_update_taken[5][1] connect tt_5_1.io.update_taken[1], tt_5_1_io_update_taken_1_REG reg tt_5_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_1_REG, s1_update_alloc[5][1] connect tt_5_1.io.update_alloc[1], tt_5_1_io_update_alloc_1_REG reg tt_5_1_io_update_old_ctr_1_REG : UInt, clock connect tt_5_1_io_update_old_ctr_1_REG, s1_update_old_ctr[5][1] connect tt_5_1.io.update_old_ctr[1], tt_5_1_io_update_old_ctr_1_REG reg tt_5_1_io_update_u_mask_1_REG : UInt, clock connect tt_5_1_io_update_u_mask_1_REG, s1_update_u_mask[5][1] connect tt_5_1.io.update_u_mask[1], tt_5_1_io_update_u_mask_1_REG reg tt_5_1_io_update_u_1_REG : UInt, clock connect tt_5_1_io_update_u_1_REG, s1_update_u[5][1] connect tt_5_1.io.update_u[1], tt_5_1_io_update_u_1_REG reg tt_5_1_io_update_mask_2_REG : UInt<1>, clock connect tt_5_1_io_update_mask_2_REG, s1_update_mask[5][2] connect tt_5_1.io.update_mask[2], tt_5_1_io_update_mask_2_REG reg tt_5_1_io_update_taken_2_REG : UInt<1>, clock connect tt_5_1_io_update_taken_2_REG, s1_update_taken[5][2] connect tt_5_1.io.update_taken[2], tt_5_1_io_update_taken_2_REG reg tt_5_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_2_REG, s1_update_alloc[5][2] connect tt_5_1.io.update_alloc[2], tt_5_1_io_update_alloc_2_REG reg tt_5_1_io_update_old_ctr_2_REG : UInt, clock connect tt_5_1_io_update_old_ctr_2_REG, s1_update_old_ctr[5][2] connect tt_5_1.io.update_old_ctr[2], tt_5_1_io_update_old_ctr_2_REG reg tt_5_1_io_update_u_mask_2_REG : UInt, clock connect tt_5_1_io_update_u_mask_2_REG, s1_update_u_mask[5][2] connect tt_5_1.io.update_u_mask[2], tt_5_1_io_update_u_mask_2_REG reg tt_5_1_io_update_u_2_REG : UInt, clock connect tt_5_1_io_update_u_2_REG, s1_update_u[5][2] connect tt_5_1.io.update_u[2], tt_5_1_io_update_u_2_REG reg tt_5_1_io_update_mask_3_REG : UInt<1>, clock connect tt_5_1_io_update_mask_3_REG, s1_update_mask[5][3] connect tt_5_1.io.update_mask[3], tt_5_1_io_update_mask_3_REG reg tt_5_1_io_update_taken_3_REG : UInt<1>, clock connect tt_5_1_io_update_taken_3_REG, s1_update_taken[5][3] connect tt_5_1.io.update_taken[3], tt_5_1_io_update_taken_3_REG reg tt_5_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_3_REG, s1_update_alloc[5][3] connect tt_5_1.io.update_alloc[3], tt_5_1_io_update_alloc_3_REG reg tt_5_1_io_update_old_ctr_3_REG : UInt, clock connect tt_5_1_io_update_old_ctr_3_REG, s1_update_old_ctr[5][3] connect tt_5_1.io.update_old_ctr[3], tt_5_1_io_update_old_ctr_3_REG reg tt_5_1_io_update_u_mask_3_REG : UInt, clock connect tt_5_1_io_update_u_mask_3_REG, s1_update_u_mask[5][3] connect tt_5_1.io.update_u_mask[3], tt_5_1_io_update_u_mask_3_REG reg tt_5_1_io_update_u_3_REG : UInt, clock connect tt_5_1_io_update_u_3_REG, s1_update_u[5][3] connect tt_5_1.io.update_u[3], tt_5_1_io_update_u_3_REG reg tt_5_1_io_update_pc_REG : UInt, clock connect tt_5_1_io_update_pc_REG, s1_update.bits.pc connect tt_5_1.io.update_pc, tt_5_1_io_update_pc_REG reg tt_5_1_io_update_hist_REG : UInt, clock connect tt_5_1_io_update_hist_REG, s1_update.bits.ghist connect tt_5_1.io.update_hist, tt_5_1_io_update_hist_REG node _io_f3_meta_T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _io_f3_meta_T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _io_f3_meta_T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _io_f3_meta_T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node io_f3_meta_lo = cat(_io_f3_meta_T_1, _io_f3_meta_T) node io_f3_meta_hi = cat(_io_f3_meta_T_3, _io_f3_meta_T_2) node _io_f3_meta_T_4 = cat(io_f3_meta_hi, io_f3_meta_lo) node io_f3_meta_lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node io_f3_meta_hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _io_f3_meta_T_5 = cat(io_f3_meta_hi_1, io_f3_meta_lo_1) node io_f3_meta_lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node io_f3_meta_hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _io_f3_meta_T_6 = cat(io_f3_meta_hi_2, io_f3_meta_lo_2) node io_f3_meta_lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node io_f3_meta_hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _io_f3_meta_T_7 = cat(io_f3_meta_hi_3, io_f3_meta_lo_3) node _io_f3_meta_T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _io_f3_meta_T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _io_f3_meta_T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _io_f3_meta_T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node io_f3_meta_lo_4 = cat(_io_f3_meta_T_9, _io_f3_meta_T_8) node io_f3_meta_hi_4 = cat(_io_f3_meta_T_11, _io_f3_meta_T_10) node _io_f3_meta_T_12 = cat(io_f3_meta_hi_4, io_f3_meta_lo_4) node io_f3_meta_lo_5 = cat(_io_f3_meta_T_5, _io_f3_meta_T_4) node io_f3_meta_hi_hi = cat(_io_f3_meta_T_12, _io_f3_meta_T_7) node io_f3_meta_hi_5 = cat(io_f3_meta_hi_hi, _io_f3_meta_T_6) node _io_f3_meta_T_13 = cat(io_f3_meta_hi_5, io_f3_meta_lo_5) connect io.f3_meta, _io_f3_meta_T_13	module TageBranchPredictorBank_3( // @[tage.scala:198:7] input clock, // @[tage.scala:198:7] input reset, // @[tage.scala:198:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [2:0] s1_update_meta_provider_ctr_3; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_2; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_1; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_0; // @[tage.scala:236:52] wire _alloc_lfsr_prng_3_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire io_f0_valid_0 = io_f0_valid; // @[tage.scala:198:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[tage.scala:198:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[tage.scala:198:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_f3_fire_0 = io_f3_fire; // @[tage.scala:198:7] wire io_update_valid_0 = io_update_valid; // @[tage.scala:198:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[tage.scala:198:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[tage.scala:198:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[tage.scala:198:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[tage.scala:198:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[tage.scala:198:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[tage.scala:198:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[tage.scala:198:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[tage.scala:198:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[tage.scala:198:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[tage.scala:198:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[tage.scala:198:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[tage.scala:198:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[tage.scala:198:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[tage.scala:198:7] wire io_f1_lhist = 1'h0; // @[tage.scala:198:7] wire _s1_update_mask_WIRE_0_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_u_mask_WIRE_0_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_3 = 1'h0; // @[tage.scala:241:50] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_taken_0; // @[tage.scala:198:7] wire io_resp_f3_1_taken_0; // @[tage.scala:198:7] wire io_resp_f3_2_taken_0; // @[tage.scala:198:7] wire io_resp_f3_3_taken_0; // @[tage.scala:198:7] wire [119:0] io_f3_meta_0; // @[tage.scala:198:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _f3_meta_alt_differs_0_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_1_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_2_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_3_T; // @[tage.scala:275:48] wire _f3_meta_allocate_0_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry; // @[tage.scala:289:26] wire _f3_meta_allocate_1_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_1; // @[tage.scala:289:26] wire _f3_meta_allocate_2_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_2; // @[tage.scala:289:26] wire _f3_meta_allocate_3_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_3; // @[tage.scala:289:26] wire f3_meta_provider_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_0_bits; // @[tage.scala:212:21] wire f3_meta_provider_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_1_bits; // @[tage.scala:212:21] wire f3_meta_provider_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_2_bits; // @[tage.scala:212:21] wire f3_meta_provider_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_3_bits; // @[tage.scala:212:21] wire f3_meta_alt_differs_0; // @[tage.scala:212:21] wire f3_meta_alt_differs_1; // @[tage.scala:212:21] wire f3_meta_alt_differs_2; // @[tage.scala:212:21] wire f3_meta_alt_differs_3; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_0; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_1; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_2; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_3; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_0; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_1; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_2; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_3; // @[tage.scala:212:21] wire f3_meta_allocate_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_0_bits; // @[tage.scala:212:21] wire f3_meta_allocate_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_1_bits; // @[tage.scala:212:21] wire f3_meta_allocate_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_2_bits; // @[tage.scala:212:21] wire f3_meta_allocate_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_3_bits; // @[tage.scala:212:21] wire [3:0] _io_f3_meta_T = {f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_1 = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_2 = {f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_3 = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits, f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits, f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33] wire [5:0] _GEN = {f3_meta_provider_ctr_1, f3_meta_provider_ctr_0}; // @[tage.scala:212:21, :213:33] wire [5:0] lo_1; // @[tage.scala:213:33] assign lo_1 = _GEN; // @[tage.scala:213:33] wire [5:0] io_f3_meta_lo_1; // @[tage.scala:359:25] assign io_f3_meta_lo_1 = _GEN; // @[tage.scala:213:33, :359:25] wire [5:0] _GEN_0 = {f3_meta_provider_ctr_3, f3_meta_provider_ctr_2}; // @[tage.scala:212:21, :213:33] wire [5:0] hi_1; // @[tage.scala:213:33] assign hi_1 = _GEN_0; // @[tage.scala:213:33] wire [5:0] io_f3_meta_hi_1; // @[tage.scala:359:25] assign io_f3_meta_hi_1 = _GEN_0; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_1 = {f3_meta_provider_u_1, f3_meta_provider_u_0}; // @[tage.scala:212:21, :213:33] wire [3:0] lo_2; // @[tage.scala:213:33] assign lo_2 = _GEN_1; // @[tage.scala:213:33] wire [3:0] io_f3_meta_lo_2; // @[tage.scala:359:25] assign io_f3_meta_lo_2 = _GEN_1; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_2 = {f3_meta_provider_u_3, f3_meta_provider_u_2}; // @[tage.scala:212:21, :213:33] wire [3:0] hi_2; // @[tage.scala:213:33] assign hi_2 = _GEN_2; // @[tage.scala:213:33] wire [3:0] io_f3_meta_hi_2; // @[tage.scala:359:25] assign io_f3_meta_hi_2 = _GEN_2; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_3 = {f3_meta_alt_differs_1, f3_meta_alt_differs_0}; // @[tage.scala:212:21, :213:33] wire [1:0] lo_3; // @[tage.scala:213:33] assign lo_3 = _GEN_3; // @[tage.scala:213:33] wire [1:0] io_f3_meta_lo_3; // @[tage.scala:359:25] assign io_f3_meta_lo_3 = _GEN_3; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_4 = {f3_meta_alt_differs_3, f3_meta_alt_differs_2}; // @[tage.scala:212:21, :213:33] wire [1:0] hi_3; // @[tage.scala:213:33] assign hi_3 = _GEN_4; // @[tage.scala:213:33] wire [1:0] io_f3_meta_hi_3; // @[tage.scala:359:25] assign io_f3_meta_hi_3 = _GEN_4; // @[tage.scala:213:33, :359:25] wire [3:0] _io_f3_meta_T_8 = {f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_9 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_10 = {f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_11 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo_4 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits, f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi_4 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits, f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33] wire [27:0] lo_5 = {hi_1, lo_1, hi, lo}; // @[tage.scala:213:33] wire [19:0] hi_hi = {hi_4, lo_4, hi_3, lo_3}; // @[tage.scala:213:33] wire [27:0] hi_5 = {hi_hi, hi_2, lo_2}; // @[tage.scala:213:33] reg t_io_f1_req_valid_REG; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_1; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_1; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_2; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_2; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_3; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_3; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_4; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_4; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_5; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_5; // @[tage.scala:226:35] wire [2:0] f3_resps_0_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_0_bits_u; // @[tage.scala:234:25] wire f3_resps_0_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_1_bits_u; // @[tage.scala:234:25] wire f3_resps_0_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_2_bits_u; // @[tage.scala:234:25] wire f3_resps_0_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_3_bits_u; // @[tage.scala:234:25] wire f3_resps_0_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_0_bits_u; // @[tage.scala:234:25] wire f3_resps_1_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_1_bits_u; // @[tage.scala:234:25] wire f3_resps_1_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_2_bits_u; // @[tage.scala:234:25] wire f3_resps_1_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_3_bits_u; // @[tage.scala:234:25] wire f3_resps_1_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_0_bits_u; // @[tage.scala:234:25] wire f3_resps_2_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_1_bits_u; // @[tage.scala:234:25] wire f3_resps_2_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_2_bits_u; // @[tage.scala:234:25] wire f3_resps_2_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_3_bits_u; // @[tage.scala:234:25] wire f3_resps_2_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_0_bits_u; // @[tage.scala:234:25] wire f3_resps_3_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_1_bits_u; // @[tage.scala:234:25] wire f3_resps_3_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_2_bits_u; // @[tage.scala:234:25] wire f3_resps_3_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_3_bits_u; // @[tage.scala:234:25] wire f3_resps_3_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_0_bits_u; // @[tage.scala:234:25] wire f3_resps_4_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_1_bits_u; // @[tage.scala:234:25] wire f3_resps_4_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_2_bits_u; // @[tage.scala:234:25] wire f3_resps_4_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_3_bits_u; // @[tage.scala:234:25] wire f3_resps_4_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_0_bits_u; // @[tage.scala:234:25] wire f3_resps_5_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_1_bits_u; // @[tage.scala:234:25] wire f3_resps_5_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_2_bits_u; // @[tage.scala:234:25] wire f3_resps_5_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_3_bits_u; // @[tage.scala:234:25] wire f3_resps_5_3_valid; // @[tage.scala:234:25] wire _s1_update_meta_T_21; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_20; // @[tage.scala:236:52] wire _s1_update_meta_T_23; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_22; // @[tage.scala:236:52] wire _s1_update_meta_T_25; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_24; // @[tage.scala:236:52] wire _s1_update_meta_T_27; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_26; // @[tage.scala:236:52] wire _s1_update_meta_T_16; // @[tage.scala:236:52] wire _s1_update_meta_T_17; // @[tage.scala:236:52] wire _s1_update_meta_T_18; // @[tage.scala:236:52] wire _s1_update_meta_T_19; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_12; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_13; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_14; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_15; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_8; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_9; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_10; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_11; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire _s1_update_meta_T_1; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T; // @[tage.scala:236:52] wire _s1_update_meta_T_3; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_2; // @[tage.scala:236:52] wire _s1_update_meta_T_5; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_4; // @[tage.scala:236:52] wire _s1_update_meta_T_7; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_6; // @[tage.scala:236:52] wire s1_update_meta_provider_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_0_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_1_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_2_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_3_bits; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_0; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_1; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_2; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_3; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_0; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_1; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_2; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_3; // @[tage.scala:236:52] wire s1_update_meta_allocate_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_0_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_1_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_2_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_3_bits; // @[tage.scala:236:52] wire [55:0] _s1_update_meta_WIRE = s1_update_bits_meta[55:0]; // @[tage.scala:236:52] assign _s1_update_meta_T = _s1_update_meta_WIRE[2:0]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_bits = _s1_update_meta_T; // @[tage.scala:236:52] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_valid = _s1_update_meta_T_1; // @[tage.scala:236:52] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[6:4]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_bits = _s1_update_meta_T_2; // @[tage.scala:236:52] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_valid = _s1_update_meta_T_3; // @[tage.scala:236:52] assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[10:8]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_bits = _s1_update_meta_T_4; // @[tage.scala:236:52] assign _s1_update_meta_T_5 = _s1_update_meta_WIRE[11]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_valid = _s1_update_meta_T_5; // @[tage.scala:236:52] assign _s1_update_meta_T_6 = _s1_update_meta_WIRE[14:12]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_bits = _s1_update_meta_T_6; // @[tage.scala:236:52] assign _s1_update_meta_T_7 = _s1_update_meta_WIRE[15]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_valid = _s1_update_meta_T_7; // @[tage.scala:236:52] assign _s1_update_meta_T_8 = _s1_update_meta_WIRE[18:16]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_0 = _s1_update_meta_T_8; // @[tage.scala:236:52] assign _s1_update_meta_T_9 = _s1_update_meta_WIRE[21:19]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_1 = _s1_update_meta_T_9; // @[tage.scala:236:52] assign _s1_update_meta_T_10 = _s1_update_meta_WIRE[24:22]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_2 = _s1_update_meta_T_10; // @[tage.scala:236:52] assign _s1_update_meta_T_11 = _s1_update_meta_WIRE[27:25]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_3 = _s1_update_meta_T_11; // @[tage.scala:236:52] assign _s1_update_meta_T_12 = _s1_update_meta_WIRE[29:28]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_0 = _s1_update_meta_T_12; // @[tage.scala:236:52] assign _s1_update_meta_T_13 = _s1_update_meta_WIRE[31:30]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_1 = _s1_update_meta_T_13; // @[tage.scala:236:52] assign _s1_update_meta_T_14 = _s1_update_meta_WIRE[33:32]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_2 = _s1_update_meta_T_14; // @[tage.scala:236:52] assign _s1_update_meta_T_15 = _s1_update_meta_WIRE[35:34]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_3 = _s1_update_meta_T_15; // @[tage.scala:236:52] assign _s1_update_meta_T_16 = _s1_update_meta_WIRE[36]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_0 = _s1_update_meta_T_16; // @[tage.scala:236:52] assign _s1_update_meta_T_17 = _s1_update_meta_WIRE[37]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_1 = _s1_update_meta_T_17; // @[tage.scala:236:52] assign _s1_update_meta_T_18 = _s1_update_meta_WIRE[38]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_2 = _s1_update_meta_T_18; // @[tage.scala:236:52] assign _s1_update_meta_T_19 = _s1_update_meta_WIRE[39]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_3 = _s1_update_meta_T_19; // @[tage.scala:236:52] assign _s1_update_meta_T_20 = _s1_update_meta_WIRE[42:40]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_bits = _s1_update_meta_T_20; // @[tage.scala:236:52] assign _s1_update_meta_T_21 = _s1_update_meta_WIRE[43]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_valid = _s1_update_meta_T_21; // @[tage.scala:236:52] assign _s1_update_meta_T_22 = _s1_update_meta_WIRE[46:44]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_bits = _s1_update_meta_T_22; // @[tage.scala:236:52] assign _s1_update_meta_T_23 = _s1_update_meta_WIRE[47]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_valid = _s1_update_meta_T_23; // @[tage.scala:236:52] assign _s1_update_meta_T_24 = _s1_update_meta_WIRE[50:48]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_bits = _s1_update_meta_T_24; // @[tage.scala:236:52] assign _s1_update_meta_T_25 = _s1_update_meta_WIRE[51]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_valid = _s1_update_meta_T_25; // @[tage.scala:236:52] assign _s1_update_meta_T_26 = _s1_update_meta_WIRE[54:52]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_bits = _s1_update_meta_T_26; // @[tage.scala:236:52] assign _s1_update_meta_T_27 = _s1_update_meta_WIRE[55]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_valid = _s1_update_meta_T_27; // @[tage.scala:236:52] wire [3:0] _s1_update_mispredict_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire [3:0] _s1_update_mispredict_mask_T_1 = {4{s1_update_bits_cfi_mispredicted}}; // @[tage.scala:238:9] wire [3:0] s1_update_mispredict_mask = _s1_update_mispredict_mask_T & _s1_update_mispredict_mask_T_1; // @[OneHot.scala:58:35] wire s1_update_mask_0_0; // @[tage.scala:240:33] wire s1_update_mask_0_1; // @[tage.scala:240:33] wire s1_update_mask_0_2; // @[tage.scala:240:33] wire s1_update_mask_0_3; // @[tage.scala:240:33] wire s1_update_mask_1_0; // @[tage.scala:240:33] wire s1_update_mask_1_1; // @[tage.scala:240:33] wire s1_update_mask_1_2; // @[tage.scala:240:33] wire s1_update_mask_1_3; // @[tage.scala:240:33] wire s1_update_mask_2_0; // @[tage.scala:240:33] wire s1_update_mask_2_1; // @[tage.scala:240:33] wire s1_update_mask_2_2; // @[tage.scala:240:33] wire s1_update_mask_2_3; // @[tage.scala:240:33] wire s1_update_mask_3_0; // @[tage.scala:240:33] wire s1_update_mask_3_1; // @[tage.scala:240:33] wire s1_update_mask_3_2; // @[tage.scala:240:33] wire s1_update_mask_3_3; // @[tage.scala:240:33] wire s1_update_mask_4_0; // @[tage.scala:240:33] wire s1_update_mask_4_1; // @[tage.scala:240:33] wire s1_update_mask_4_2; // @[tage.scala:240:33] wire s1_update_mask_4_3; // @[tage.scala:240:33] wire s1_update_mask_5_0; // @[tage.scala:240:33] wire s1_update_mask_5_1; // @[tage.scala:240:33] wire s1_update_mask_5_2; // @[tage.scala:240:33] wire s1_update_mask_5_3; // @[tage.scala:240:33] wire s1_update_u_mask_0_0; // @[tage.scala:241:35] wire s1_update_u_mask_0_1; // @[tage.scala:241:35] wire s1_update_u_mask_0_2; // @[tage.scala:241:35] wire s1_update_u_mask_0_3; // @[tage.scala:241:35] wire s1_update_u_mask_1_0; // @[tage.scala:241:35] wire s1_update_u_mask_1_1; // @[tage.scala:241:35] wire s1_update_u_mask_1_2; // @[tage.scala:241:35] wire s1_update_u_mask_1_3; // @[tage.scala:241:35] wire s1_update_u_mask_2_0; // @[tage.scala:241:35] wire s1_update_u_mask_2_1; // @[tage.scala:241:35] wire s1_update_u_mask_2_2; // @[tage.scala:241:35] wire s1_update_u_mask_2_3; // @[tage.scala:241:35] wire s1_update_u_mask_3_0; // @[tage.scala:241:35] wire s1_update_u_mask_3_1; // @[tage.scala:241:35] wire s1_update_u_mask_3_2; // @[tage.scala:241:35] wire s1_update_u_mask_3_3; // @[tage.scala:241:35] wire s1_update_u_mask_4_0; // @[tage.scala:241:35] wire s1_update_u_mask_4_1; // @[tage.scala:241:35] wire s1_update_u_mask_4_2; // @[tage.scala:241:35] wire s1_update_u_mask_4_3; // @[tage.scala:241:35] wire s1_update_u_mask_5_0; // @[tage.scala:241:35] wire s1_update_u_mask_5_1; // @[tage.scala:241:35] wire s1_update_u_mask_5_2; // @[tage.scala:241:35] wire s1_update_u_mask_5_3; // @[tage.scala:241:35] wire s1_update_taken_0_0; // @[tage.scala:243:31] wire s1_update_taken_0_1; // @[tage.scala:243:31] wire s1_update_taken_0_2; // @[tage.scala:243:31] wire s1_update_taken_0_3; // @[tage.scala:243:31] wire s1_update_taken_1_0; // @[tage.scala:243:31] wire s1_update_taken_1_1; // @[tage.scala:243:31] wire s1_update_taken_1_2; // @[tage.scala:243:31] wire s1_update_taken_1_3; // @[tage.scala:243:31] wire s1_update_taken_2_0; // @[tage.scala:243:31] wire s1_update_taken_2_1; // @[tage.scala:243:31] wire s1_update_taken_2_2; // @[tage.scala:243:31] wire s1_update_taken_2_3; // @[tage.scala:243:31] wire s1_update_taken_3_0; // @[tage.scala:243:31] wire s1_update_taken_3_1; // @[tage.scala:243:31] wire s1_update_taken_3_2; // @[tage.scala:243:31] wire s1_update_taken_3_3; // @[tage.scala:243:31] wire s1_update_taken_4_0; // @[tage.scala:243:31] wire s1_update_taken_4_1; // @[tage.scala:243:31] wire s1_update_taken_4_2; // @[tage.scala:243:31] wire s1_update_taken_4_3; // @[tage.scala:243:31] wire s1_update_taken_5_0; // @[tage.scala:243:31] wire s1_update_taken_5_1; // @[tage.scala:243:31] wire s1_update_taken_5_2; // @[tage.scala:243:31] wire s1_update_taken_5_3; // @[tage.scala:243:31] wire s1_update_alloc_0_0; // @[tage.scala:245:31] wire s1_update_alloc_0_1; // @[tage.scala:245:31] wire s1_update_alloc_0_2; // @[tage.scala:245:31] wire s1_update_alloc_0_3; // @[tage.scala:245:31] wire s1_update_alloc_1_0; // @[tage.scala:245:31] wire s1_update_alloc_1_1; // @[tage.scala:245:31] wire s1_update_alloc_1_2; // @[tage.scala:245:31] wire s1_update_alloc_1_3; // @[tage.scala:245:31] wire s1_update_alloc_2_0; // @[tage.scala:245:31] wire s1_update_alloc_2_1; // @[tage.scala:245:31] wire s1_update_alloc_2_2; // @[tage.scala:245:31] wire s1_update_alloc_2_3; // @[tage.scala:245:31] wire s1_update_alloc_3_0; // @[tage.scala:245:31] wire s1_update_alloc_3_1; // @[tage.scala:245:31] wire s1_update_alloc_3_2; // @[tage.scala:245:31] wire s1_update_alloc_3_3; // @[tage.scala:245:31] wire s1_update_alloc_4_0; // @[tage.scala:245:31] wire s1_update_alloc_4_1; // @[tage.scala:245:31] wire s1_update_alloc_4_2; // @[tage.scala:245:31] wire s1_update_alloc_4_3; // @[tage.scala:245:31] wire s1_update_alloc_5_0; // @[tage.scala:245:31] wire s1_update_alloc_5_1; // @[tage.scala:245:31] wire s1_update_alloc_5_2; // @[tage.scala:245:31] wire s1_update_alloc_5_3; // @[tage.scala:245:31] wire [1:0] s1_update_u_0_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_3; // @[tage.scala:246:31] wire final_altpred; // @[tage.scala:256:33] wire _io_resp_f3_0_taken_T = f3_resps_0_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_1 = f3_resps_0_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_2 = _io_resp_f3_0_taken_T \| _io_resp_f3_0_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_3 = f3_resps_0_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_4 = _io_resp_f3_0_taken_T_2 ? io_resp_in_0_f3_0_taken_0 : _io_resp_f3_0_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_17 = f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_5 = f3_resps_1_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_6 = f3_resps_1_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_7 = _io_resp_f3_0_taken_T_5 \| _io_resp_f3_0_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_8 = f3_resps_1_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_9 = _io_resp_f3_0_taken_T_7 ? _T_17 : _io_resp_f3_0_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_21 = f3_resps_1_0_valid ? f3_resps_1_0_bits_ctr[2] : _T_17; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_10 = f3_resps_2_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_11 = f3_resps_2_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_12 = _io_resp_f3_0_taken_T_10 \| _io_resp_f3_0_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_13 = f3_resps_2_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_14 = _io_resp_f3_0_taken_T_12 ? _T_21 : _io_resp_f3_0_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_25 = f3_resps_2_0_valid ? f3_resps_2_0_bits_ctr[2] : _T_21; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_15 = f3_resps_3_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_16 = f3_resps_3_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_17 = _io_resp_f3_0_taken_T_15 \| _io_resp_f3_0_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_18 = f3_resps_3_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_19 = _io_resp_f3_0_taken_T_17 ? _T_25 : _io_resp_f3_0_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_29 = f3_resps_3_0_valid ? f3_resps_3_0_bits_ctr[2] : _T_25; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_20 = f3_resps_4_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_21 = f3_resps_4_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_22 = _io_resp_f3_0_taken_T_20 \| _io_resp_f3_0_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_23 = f3_resps_4_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_24 = _io_resp_f3_0_taken_T_22 ? _T_29 : _io_resp_f3_0_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_33 = f3_resps_4_0_valid ? f3_resps_4_0_bits_ctr[2] : _T_29; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_25 = f3_resps_5_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_26 = f3_resps_5_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_27 = _io_resp_f3_0_taken_T_25 \| _io_resp_f3_0_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_28 = f3_resps_5_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_29 = _io_resp_f3_0_taken_T_27 ? _T_33 : _io_resp_f3_0_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_0_taken_0 = f3_resps_5_0_valid ? _io_resp_f3_0_taken_T_29 : f3_resps_4_0_valid ? _io_resp_f3_0_taken_T_24 : f3_resps_3_0_valid ? _io_resp_f3_0_taken_T_19 : f3_resps_2_0_valid ? _io_resp_f3_0_taken_T_14 : f3_resps_1_0_valid ? _io_resp_f3_0_taken_T_9 : f3_resps_0_0_valid ? _io_resp_f3_0_taken_T_4 : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred = f3_resps_5_0_valid ? _T_33 : f3_resps_4_0_valid ? _T_29 : f3_resps_3_0_valid ? _T_25 : f3_resps_2_0_valid ? _T_21 : f3_resps_1_0_valid & f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_0_valid = f3_resps_0_0_valid \| f3_resps_1_0_valid \| f3_resps_2_0_valid \| f3_resps_3_0_valid \| f3_resps_4_0_valid \| f3_resps_5_0_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_0_bits = f3_resps_5_0_valid ? 3'h5 : f3_resps_4_0_valid ? 3'h4 : {1'h0, f3_resps_3_0_valid ? 2'h3 : f3_resps_2_0_valid ? 2'h2 : {1'h0, f3_resps_1_0_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_0_T = final_altpred != io_resp_f3_0_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_0 = _f3_meta_alt_differs_0_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_5 = {{f3_resps_0_0_bits_ctr}, {f3_resps_0_0_bits_ctr}, {f3_resps_5_0_bits_ctr}, {f3_resps_4_0_bits_ctr}, {f3_resps_3_0_bits_ctr}, {f3_resps_2_0_bits_ctr}, {f3_resps_1_0_bits_ctr}, {f3_resps_0_0_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_0 = _GEN_5[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_6 = {{f3_resps_0_0_bits_u}, {f3_resps_0_0_bits_u}, {f3_resps_5_0_bits_u}, {f3_resps_4_0_bits_u}, {f3_resps_3_0_bits_u}, {f3_resps_2_0_bits_u}, {f3_resps_1_0_bits_u}, {f3_resps_0_0_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_0 = _GEN_6[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T = ~f3_resps_0_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_1 = f3_resps_0_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_2 = _allocatable_slots_T & _allocatable_slots_T_1; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_0 = _allocatable_slots_T_2; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_3 = ~f3_resps_1_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_4 = f3_resps_1_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_5 = _allocatable_slots_T_3 & _allocatable_slots_T_4; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1 = _allocatable_slots_T_5; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_6 = ~f3_resps_2_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_7 = f3_resps_2_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_8 = _allocatable_slots_T_6 & _allocatable_slots_T_7; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2 = _allocatable_slots_T_8; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_9 = ~f3_resps_3_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_10 = f3_resps_3_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_11 = _allocatable_slots_T_9 & _allocatable_slots_T_10; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3 = _allocatable_slots_T_11; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_12 = ~f3_resps_4_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_13 = f3_resps_4_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_14 = _allocatable_slots_T_12 & _allocatable_slots_T_13; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_4 = _allocatable_slots_T_14; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_15 = ~f3_resps_5_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_16 = f3_resps_5_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_17 = _allocatable_slots_T_15 & _allocatable_slots_T_16; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_5 = _allocatable_slots_T_17; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi = {_allocatable_slots_WIRE_2, _allocatable_slots_WIRE_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo = {allocatable_slots_lo_hi, _allocatable_slots_WIRE_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi = {_allocatable_slots_WIRE_5, _allocatable_slots_WIRE_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi = {allocatable_slots_hi_hi, _allocatable_slots_WIRE_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_18 = {allocatable_slots_hi, allocatable_slots_lo}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_19 = 8'h1 << f3_meta_provider_0_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_20 = _allocatable_slots_T_19; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_21 = {1'h0, _allocatable_slots_T_19[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_22 = {2'h0, _allocatable_slots_T_19[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_23 = {3'h0, _allocatable_slots_T_19[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_24 = {4'h0, _allocatable_slots_T_19[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_25 = {5'h0, _allocatable_slots_T_19[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_26 = {6'h0, _allocatable_slots_T_19[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_27 = {7'h0, _allocatable_slots_T_19[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_28 = _allocatable_slots_T_20 \| _allocatable_slots_T_21; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_29 = _allocatable_slots_T_28 \| _allocatable_slots_T_22; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_30 = _allocatable_slots_T_29 \| _allocatable_slots_T_23; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_31 = _allocatable_slots_T_30 \| _allocatable_slots_T_24; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_32 = _allocatable_slots_T_31 \| _allocatable_slots_T_25; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_33 = _allocatable_slots_T_32 \| _allocatable_slots_T_26; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_34 = _allocatable_slots_T_33 \| _allocatable_slots_T_27; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_35 = {6{f3_meta_provider_0_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_36 = {2'h0, _allocatable_slots_T_34[5:0] & _allocatable_slots_T_35}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_37 = ~_allocatable_slots_T_36; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots = {2'h0, _allocatable_slots_T_37[5:0] & _allocatable_slots_T_18}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi = {_alloc_lfsr_prng_io_out_2, _alloc_lfsr_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo = {alloc_lfsr_lo_hi, _alloc_lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi = {_alloc_lfsr_prng_io_out_5, _alloc_lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi = {alloc_lfsr_hi_hi, _alloc_lfsr_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr = {alloc_lfsr_hi, alloc_lfsr_lo}; // @[PRNG.scala:95:17] wire _first_entry_T = allocatable_slots[0]; // @[OneHot.scala:48:45] wire _first_entry_T_1 = allocatable_slots[1]; // @[OneHot.scala:48:45] wire _first_entry_T_2 = allocatable_slots[2]; // @[OneHot.scala:48:45] wire _first_entry_T_3 = allocatable_slots[3]; // @[OneHot.scala:48:45] wire _first_entry_T_4 = allocatable_slots[4]; // @[OneHot.scala:48:45] wire _first_entry_T_5 = allocatable_slots[5]; // @[OneHot.scala:48:45] wire _first_entry_T_6 = allocatable_slots[6]; // @[OneHot.scala:48:45] wire _first_entry_T_7 = allocatable_slots[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_8 = {2'h3, ~_first_entry_T_6}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_9 = _first_entry_T_5 ? 3'h5 : _first_entry_T_8; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_10 = _first_entry_T_4 ? 3'h4 : _first_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_11 = _first_entry_T_3 ? 3'h3 : _first_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_12 = _first_entry_T_2 ? 3'h2 : _first_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_13 = _first_entry_T_1 ? 3'h1 : _first_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] first_entry = _first_entry_T ? 3'h0 : _first_entry_T_13; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T = {2'h0, allocatable_slots[5:0] & alloc_lfsr}; // @[PRNG.scala:95:17] wire _masked_entry_T_1 = _masked_entry_T[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_2 = _masked_entry_T[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_3 = _masked_entry_T[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_4 = _masked_entry_T[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_5 = _masked_entry_T[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_6 = _masked_entry_T[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_7 = _masked_entry_T[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_8 = _masked_entry_T[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_9 = {2'h3, ~_masked_entry_T_7}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_10 = _masked_entry_T_6 ? 3'h5 : _masked_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_11 = _masked_entry_T_5 ? 3'h4 : _masked_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_12 = _masked_entry_T_4 ? 3'h3 : _masked_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_13 = _masked_entry_T_3 ? 3'h2 : _masked_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_14 = _masked_entry_T_2 ? 3'h1 : _masked_entry_T_13; // @[OneHot.scala:48:45] wire [2:0] masked_entry = _masked_entry_T_1 ? 3'h0 : _masked_entry_T_14; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T = allocatable_slots >> masked_entry; // @[Mux.scala:50:70] wire _alloc_entry_T_1 = _alloc_entry_T[0]; // @[tage.scala:289:44] assign alloc_entry = _alloc_entry_T_1 ? masked_entry : first_entry; // @[Mux.scala:50:70] assign f3_meta_allocate_0_bits = alloc_entry; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_0_valid_T = \|allocatable_slots; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_0_valid = _f3_meta_allocate_0_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[tage.scala:297:58] wire _update_was_taken_T_1 = s1_update_bits_cfi_idx_valid & _update_was_taken_T; // @[tage.scala:296:58, :297:58] wire update_was_taken = _update_was_taken_T_1 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire [4:0] _GEN_7 = {s1_update_bits_is_mispredict_update \| s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30] wire _T_44 = s1_update_bits_br_mask[0] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_8 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_9 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_10 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_11 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_12 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_13 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T = s1_update_mispredict_mask[0]; // @[tage.scala:237:73, :308:52] wire _new_u_T_1 = ~s1_update_meta_alt_differs_0; // @[tage.scala:217:9, :236:52] wire _new_u_T_2 = s1_update_meta_provider_u_0 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_14 = {1'h0, s1_update_meta_provider_u_0}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_3 = _GEN_14 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_4 = _new_u_T_3[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_5 = _new_u_T_2 ? 2'h0 : _new_u_T_4; // @[tage.scala:218:{24,27,43}] wire _new_u_T_6 = &s1_update_meta_provider_u_0; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_7 = _GEN_14 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_8 = _new_u_T_7[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_9 = _new_u_T_6 ? 2'h3 : _new_u_T_8; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_10 = _new_u_T ? _new_u_T_5 : _new_u_T_9; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u = _new_u_T_1 ? s1_update_meta_provider_u_0 : _new_u_T_10; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_1; // @[tage.scala:256:33] wire _io_resp_f3_1_taken_T = f3_resps_0_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_1 = f3_resps_0_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_2 = _io_resp_f3_1_taken_T \| _io_resp_f3_1_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_3 = f3_resps_0_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_4 = _io_resp_f3_1_taken_T_2 ? io_resp_in_0_f3_1_taken_0 : _io_resp_f3_1_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_48 = f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_5 = f3_resps_1_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_6 = f3_resps_1_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_7 = _io_resp_f3_1_taken_T_5 \| _io_resp_f3_1_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_8 = f3_resps_1_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_9 = _io_resp_f3_1_taken_T_7 ? _T_48 : _io_resp_f3_1_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_52 = f3_resps_1_1_valid ? f3_resps_1_1_bits_ctr[2] : _T_48; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_10 = f3_resps_2_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_11 = f3_resps_2_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_12 = _io_resp_f3_1_taken_T_10 \| _io_resp_f3_1_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_13 = f3_resps_2_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_14 = _io_resp_f3_1_taken_T_12 ? _T_52 : _io_resp_f3_1_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_56 = f3_resps_2_1_valid ? f3_resps_2_1_bits_ctr[2] : _T_52; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_15 = f3_resps_3_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_16 = f3_resps_3_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_17 = _io_resp_f3_1_taken_T_15 \| _io_resp_f3_1_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_18 = f3_resps_3_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_19 = _io_resp_f3_1_taken_T_17 ? _T_56 : _io_resp_f3_1_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_60 = f3_resps_3_1_valid ? f3_resps_3_1_bits_ctr[2] : _T_56; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_20 = f3_resps_4_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_21 = f3_resps_4_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_22 = _io_resp_f3_1_taken_T_20 \| _io_resp_f3_1_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_23 = f3_resps_4_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_24 = _io_resp_f3_1_taken_T_22 ? _T_60 : _io_resp_f3_1_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_64 = f3_resps_4_1_valid ? f3_resps_4_1_bits_ctr[2] : _T_60; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_25 = f3_resps_5_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_26 = f3_resps_5_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_27 = _io_resp_f3_1_taken_T_25 \| _io_resp_f3_1_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_28 = f3_resps_5_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_29 = _io_resp_f3_1_taken_T_27 ? _T_64 : _io_resp_f3_1_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_1_taken_0 = f3_resps_5_1_valid ? _io_resp_f3_1_taken_T_29 : f3_resps_4_1_valid ? _io_resp_f3_1_taken_T_24 : f3_resps_3_1_valid ? _io_resp_f3_1_taken_T_19 : f3_resps_2_1_valid ? _io_resp_f3_1_taken_T_14 : f3_resps_1_1_valid ? _io_resp_f3_1_taken_T_9 : f3_resps_0_1_valid ? _io_resp_f3_1_taken_T_4 : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_1 = f3_resps_5_1_valid ? _T_64 : f3_resps_4_1_valid ? _T_60 : f3_resps_3_1_valid ? _T_56 : f3_resps_2_1_valid ? _T_52 : f3_resps_1_1_valid & f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_1_valid = f3_resps_0_1_valid \| f3_resps_1_1_valid \| f3_resps_2_1_valid \| f3_resps_3_1_valid \| f3_resps_4_1_valid \| f3_resps_5_1_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_1_bits = f3_resps_5_1_valid ? 3'h5 : f3_resps_4_1_valid ? 3'h4 : {1'h0, f3_resps_3_1_valid ? 2'h3 : f3_resps_2_1_valid ? 2'h2 : {1'h0, f3_resps_1_1_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_1_T = final_altpred_1 != io_resp_f3_1_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_1 = _f3_meta_alt_differs_1_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_15 = {{f3_resps_0_1_bits_ctr}, {f3_resps_0_1_bits_ctr}, {f3_resps_5_1_bits_ctr}, {f3_resps_4_1_bits_ctr}, {f3_resps_3_1_bits_ctr}, {f3_resps_2_1_bits_ctr}, {f3_resps_1_1_bits_ctr}, {f3_resps_0_1_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_1 = _GEN_15[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_16 = {{f3_resps_0_1_bits_u}, {f3_resps_0_1_bits_u}, {f3_resps_5_1_bits_u}, {f3_resps_4_1_bits_u}, {f3_resps_3_1_bits_u}, {f3_resps_2_1_bits_u}, {f3_resps_1_1_bits_u}, {f3_resps_0_1_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_1 = _GEN_16[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_38 = ~f3_resps_0_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_39 = f3_resps_0_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_40 = _allocatable_slots_T_38 & _allocatable_slots_T_39; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_0 = _allocatable_slots_T_40; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_41 = ~f3_resps_1_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_42 = f3_resps_1_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_43 = _allocatable_slots_T_41 & _allocatable_slots_T_42; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_1 = _allocatable_slots_T_43; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_44 = ~f3_resps_2_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_45 = f3_resps_2_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_46 = _allocatable_slots_T_44 & _allocatable_slots_T_45; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_2 = _allocatable_slots_T_46; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_47 = ~f3_resps_3_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_48 = f3_resps_3_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_49 = _allocatable_slots_T_47 & _allocatable_slots_T_48; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_3 = _allocatable_slots_T_49; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_50 = ~f3_resps_4_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_51 = f3_resps_4_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_52 = _allocatable_slots_T_50 & _allocatable_slots_T_51; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_4 = _allocatable_slots_T_52; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_53 = ~f3_resps_5_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_54 = f3_resps_5_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_55 = _allocatable_slots_T_53 & _allocatable_slots_T_54; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_5 = _allocatable_slots_T_55; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_1 = {_allocatable_slots_WIRE_1_2, _allocatable_slots_WIRE_1_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_1 = {allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_1 = {_allocatable_slots_WIRE_1_5, _allocatable_slots_WIRE_1_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_1 = {allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_56 = {allocatable_slots_hi_1, allocatable_slots_lo_1}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_57 = 8'h1 << f3_meta_provider_1_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_58 = _allocatable_slots_T_57; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_59 = {1'h0, _allocatable_slots_T_57[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_60 = {2'h0, _allocatable_slots_T_57[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_61 = {3'h0, _allocatable_slots_T_57[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_62 = {4'h0, _allocatable_slots_T_57[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_63 = {5'h0, _allocatable_slots_T_57[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_64 = {6'h0, _allocatable_slots_T_57[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_65 = {7'h0, _allocatable_slots_T_57[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_66 = _allocatable_slots_T_58 \| _allocatable_slots_T_59; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_67 = _allocatable_slots_T_66 \| _allocatable_slots_T_60; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_68 = _allocatable_slots_T_67 \| _allocatable_slots_T_61; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_69 = _allocatable_slots_T_68 \| _allocatable_slots_T_62; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_70 = _allocatable_slots_T_69 \| _allocatable_slots_T_63; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_71 = _allocatable_slots_T_70 \| _allocatable_slots_T_64; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_72 = _allocatable_slots_T_71 \| _allocatable_slots_T_65; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_73 = {6{f3_meta_provider_1_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_74 = {2'h0, _allocatable_slots_T_72[5:0] & _allocatable_slots_T_73}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_75 = ~_allocatable_slots_T_74; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_1 = {2'h0, _allocatable_slots_T_75[5:0] & _allocatable_slots_T_56}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_1 = {_alloc_lfsr_prng_1_io_out_2, _alloc_lfsr_prng_1_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_1 = {alloc_lfsr_lo_hi_1, _alloc_lfsr_prng_1_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_1 = {_alloc_lfsr_prng_1_io_out_5, _alloc_lfsr_prng_1_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_1 = {alloc_lfsr_hi_hi_1, _alloc_lfsr_prng_1_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_1 = {alloc_lfsr_hi_1, alloc_lfsr_lo_1}; // @[PRNG.scala:95:17] wire _first_entry_T_14 = allocatable_slots_1[0]; // @[OneHot.scala:48:45] wire _first_entry_T_15 = allocatable_slots_1[1]; // @[OneHot.scala:48:45] wire _first_entry_T_16 = allocatable_slots_1[2]; // @[OneHot.scala:48:45] wire _first_entry_T_17 = allocatable_slots_1[3]; // @[OneHot.scala:48:45] wire _first_entry_T_18 = allocatable_slots_1[4]; // @[OneHot.scala:48:45] wire _first_entry_T_19 = allocatable_slots_1[5]; // @[OneHot.scala:48:45] wire _first_entry_T_20 = allocatable_slots_1[6]; // @[OneHot.scala:48:45] wire _first_entry_T_21 = allocatable_slots_1[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_22 = {2'h3, ~_first_entry_T_20}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_23 = _first_entry_T_19 ? 3'h5 : _first_entry_T_22; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_24 = _first_entry_T_18 ? 3'h4 : _first_entry_T_23; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_25 = _first_entry_T_17 ? 3'h3 : _first_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_26 = _first_entry_T_16 ? 3'h2 : _first_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_27 = _first_entry_T_15 ? 3'h1 : _first_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] first_entry_1 = _first_entry_T_14 ? 3'h0 : _first_entry_T_27; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_15 = {2'h0, allocatable_slots_1[5:0] & alloc_lfsr_1}; // @[PRNG.scala:95:17] wire _masked_entry_T_16 = _masked_entry_T_15[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_17 = _masked_entry_T_15[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_18 = _masked_entry_T_15[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_19 = _masked_entry_T_15[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_20 = _masked_entry_T_15[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_21 = _masked_entry_T_15[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_22 = _masked_entry_T_15[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_23 = _masked_entry_T_15[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_24 = {2'h3, ~_masked_entry_T_22}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_25 = _masked_entry_T_21 ? 3'h5 : _masked_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_26 = _masked_entry_T_20 ? 3'h4 : _masked_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_27 = _masked_entry_T_19 ? 3'h3 : _masked_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_28 = _masked_entry_T_18 ? 3'h2 : _masked_entry_T_27; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_29 = _masked_entry_T_17 ? 3'h1 : _masked_entry_T_28; // @[OneHot.scala:48:45] wire [2:0] masked_entry_1 = _masked_entry_T_16 ? 3'h0 : _masked_entry_T_29; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_2 = allocatable_slots_1 >> masked_entry_1; // @[Mux.scala:50:70] wire _alloc_entry_T_3 = _alloc_entry_T_2[0]; // @[tage.scala:289:44] assign alloc_entry_1 = _alloc_entry_T_3 ? masked_entry_1 : first_entry_1; // @[Mux.scala:50:70] assign f3_meta_allocate_1_bits = alloc_entry_1; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_1_valid_T = \|allocatable_slots_1; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_1_valid = _f3_meta_allocate_1_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_2 = s1_update_bits_cfi_idx_bits == 2'h1; // @[tage.scala:297:58] wire _update_was_taken_T_3 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_2; // @[tage.scala:296:58, :297:58] wire update_was_taken_1 = _update_was_taken_T_3 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_75 = s1_update_bits_br_mask[1] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_17 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_18 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_19 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_20 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_21 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_22 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_11 = s1_update_mispredict_mask[1]; // @[tage.scala:237:73, :308:52] wire _new_u_T_12 = ~s1_update_meta_alt_differs_1; // @[tage.scala:217:9, :236:52] wire _new_u_T_13 = s1_update_meta_provider_u_1 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_23 = {1'h0, s1_update_meta_provider_u_1}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_14 = _GEN_23 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_15 = _new_u_T_14[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_16 = _new_u_T_13 ? 2'h0 : _new_u_T_15; // @[tage.scala:218:{24,27,43}] wire _new_u_T_17 = &s1_update_meta_provider_u_1; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_18 = _GEN_23 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_19 = _new_u_T_18[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_20 = _new_u_T_17 ? 2'h3 : _new_u_T_19; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_21 = _new_u_T_11 ? _new_u_T_16 : _new_u_T_20; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_1 = _new_u_T_12 ? s1_update_meta_provider_u_1 : _new_u_T_21; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_2; // @[tage.scala:256:33] wire _io_resp_f3_2_taken_T = f3_resps_0_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_1 = f3_resps_0_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_2 = _io_resp_f3_2_taken_T \| _io_resp_f3_2_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_3 = f3_resps_0_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_4 = _io_resp_f3_2_taken_T_2 ? io_resp_in_0_f3_2_taken_0 : _io_resp_f3_2_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_79 = f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_5 = f3_resps_1_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_6 = f3_resps_1_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_7 = _io_resp_f3_2_taken_T_5 \| _io_resp_f3_2_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_8 = f3_resps_1_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_9 = _io_resp_f3_2_taken_T_7 ? _T_79 : _io_resp_f3_2_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_83 = f3_resps_1_2_valid ? f3_resps_1_2_bits_ctr[2] : _T_79; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_10 = f3_resps_2_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_11 = f3_resps_2_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_12 = _io_resp_f3_2_taken_T_10 \| _io_resp_f3_2_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_13 = f3_resps_2_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_14 = _io_resp_f3_2_taken_T_12 ? _T_83 : _io_resp_f3_2_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_87 = f3_resps_2_2_valid ? f3_resps_2_2_bits_ctr[2] : _T_83; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_15 = f3_resps_3_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_16 = f3_resps_3_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_17 = _io_resp_f3_2_taken_T_15 \| _io_resp_f3_2_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_18 = f3_resps_3_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_19 = _io_resp_f3_2_taken_T_17 ? _T_87 : _io_resp_f3_2_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_91 = f3_resps_3_2_valid ? f3_resps_3_2_bits_ctr[2] : _T_87; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_20 = f3_resps_4_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_21 = f3_resps_4_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_22 = _io_resp_f3_2_taken_T_20 \| _io_resp_f3_2_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_23 = f3_resps_4_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_24 = _io_resp_f3_2_taken_T_22 ? _T_91 : _io_resp_f3_2_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_95 = f3_resps_4_2_valid ? f3_resps_4_2_bits_ctr[2] : _T_91; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_25 = f3_resps_5_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_26 = f3_resps_5_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_27 = _io_resp_f3_2_taken_T_25 \| _io_resp_f3_2_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_28 = f3_resps_5_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_29 = _io_resp_f3_2_taken_T_27 ? _T_95 : _io_resp_f3_2_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_2_taken_0 = f3_resps_5_2_valid ? _io_resp_f3_2_taken_T_29 : f3_resps_4_2_valid ? _io_resp_f3_2_taken_T_24 : f3_resps_3_2_valid ? _io_resp_f3_2_taken_T_19 : f3_resps_2_2_valid ? _io_resp_f3_2_taken_T_14 : f3_resps_1_2_valid ? _io_resp_f3_2_taken_T_9 : f3_resps_0_2_valid ? _io_resp_f3_2_taken_T_4 : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_2 = f3_resps_5_2_valid ? _T_95 : f3_resps_4_2_valid ? _T_91 : f3_resps_3_2_valid ? _T_87 : f3_resps_2_2_valid ? _T_83 : f3_resps_1_2_valid & f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_2_valid = f3_resps_0_2_valid \| f3_resps_1_2_valid \| f3_resps_2_2_valid \| f3_resps_3_2_valid \| f3_resps_4_2_valid \| f3_resps_5_2_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_2_bits = f3_resps_5_2_valid ? 3'h5 : f3_resps_4_2_valid ? 3'h4 : {1'h0, f3_resps_3_2_valid ? 2'h3 : f3_resps_2_2_valid ? 2'h2 : {1'h0, f3_resps_1_2_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_2_T = final_altpred_2 != io_resp_f3_2_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_2 = _f3_meta_alt_differs_2_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_24 = {{f3_resps_0_2_bits_ctr}, {f3_resps_0_2_bits_ctr}, {f3_resps_5_2_bits_ctr}, {f3_resps_4_2_bits_ctr}, {f3_resps_3_2_bits_ctr}, {f3_resps_2_2_bits_ctr}, {f3_resps_1_2_bits_ctr}, {f3_resps_0_2_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_2 = _GEN_24[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_25 = {{f3_resps_0_2_bits_u}, {f3_resps_0_2_bits_u}, {f3_resps_5_2_bits_u}, {f3_resps_4_2_bits_u}, {f3_resps_3_2_bits_u}, {f3_resps_2_2_bits_u}, {f3_resps_1_2_bits_u}, {f3_resps_0_2_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_2 = _GEN_25[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_76 = ~f3_resps_0_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_77 = f3_resps_0_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_78 = _allocatable_slots_T_76 & _allocatable_slots_T_77; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_0 = _allocatable_slots_T_78; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_79 = ~f3_resps_1_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_80 = f3_resps_1_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_81 = _allocatable_slots_T_79 & _allocatable_slots_T_80; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_1 = _allocatable_slots_T_81; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_82 = ~f3_resps_2_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_83 = f3_resps_2_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_84 = _allocatable_slots_T_82 & _allocatable_slots_T_83; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_2 = _allocatable_slots_T_84; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_85 = ~f3_resps_3_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_86 = f3_resps_3_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_87 = _allocatable_slots_T_85 & _allocatable_slots_T_86; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_3 = _allocatable_slots_T_87; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_88 = ~f3_resps_4_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_89 = f3_resps_4_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_90 = _allocatable_slots_T_88 & _allocatable_slots_T_89; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_4 = _allocatable_slots_T_90; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_91 = ~f3_resps_5_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_92 = f3_resps_5_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_93 = _allocatable_slots_T_91 & _allocatable_slots_T_92; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_5 = _allocatable_slots_T_93; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_2 = {_allocatable_slots_WIRE_2_2, _allocatable_slots_WIRE_2_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_2 = {allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_2 = {_allocatable_slots_WIRE_2_5, _allocatable_slots_WIRE_2_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_2 = {allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_94 = {allocatable_slots_hi_2, allocatable_slots_lo_2}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_95 = 8'h1 << f3_meta_provider_2_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_96 = _allocatable_slots_T_95; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_97 = {1'h0, _allocatable_slots_T_95[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_98 = {2'h0, _allocatable_slots_T_95[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_99 = {3'h0, _allocatable_slots_T_95[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_100 = {4'h0, _allocatable_slots_T_95[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_101 = {5'h0, _allocatable_slots_T_95[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_102 = {6'h0, _allocatable_slots_T_95[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_103 = {7'h0, _allocatable_slots_T_95[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_104 = _allocatable_slots_T_96 \| _allocatable_slots_T_97; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_105 = _allocatable_slots_T_104 \| _allocatable_slots_T_98; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_106 = _allocatable_slots_T_105 \| _allocatable_slots_T_99; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_107 = _allocatable_slots_T_106 \| _allocatable_slots_T_100; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_108 = _allocatable_slots_T_107 \| _allocatable_slots_T_101; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_109 = _allocatable_slots_T_108 \| _allocatable_slots_T_102; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_110 = _allocatable_slots_T_109 \| _allocatable_slots_T_103; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_111 = {6{f3_meta_provider_2_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_112 = {2'h0, _allocatable_slots_T_110[5:0] & _allocatable_slots_T_111}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_113 = ~_allocatable_slots_T_112; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_2 = {2'h0, _allocatable_slots_T_113[5:0] & _allocatable_slots_T_94}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_2 = {_alloc_lfsr_prng_2_io_out_2, _alloc_lfsr_prng_2_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_2 = {alloc_lfsr_lo_hi_2, _alloc_lfsr_prng_2_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_2 = {_alloc_lfsr_prng_2_io_out_5, _alloc_lfsr_prng_2_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_2 = {alloc_lfsr_hi_hi_2, _alloc_lfsr_prng_2_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_2 = {alloc_lfsr_hi_2, alloc_lfsr_lo_2}; // @[PRNG.scala:95:17] wire _first_entry_T_28 = allocatable_slots_2[0]; // @[OneHot.scala:48:45] wire _first_entry_T_29 = allocatable_slots_2[1]; // @[OneHot.scala:48:45] wire _first_entry_T_30 = allocatable_slots_2[2]; // @[OneHot.scala:48:45] wire _first_entry_T_31 = allocatable_slots_2[3]; // @[OneHot.scala:48:45] wire _first_entry_T_32 = allocatable_slots_2[4]; // @[OneHot.scala:48:45] wire _first_entry_T_33 = allocatable_slots_2[5]; // @[OneHot.scala:48:45] wire _first_entry_T_34 = allocatable_slots_2[6]; // @[OneHot.scala:48:45] wire _first_entry_T_35 = allocatable_slots_2[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_36 = {2'h3, ~_first_entry_T_34}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_37 = _first_entry_T_33 ? 3'h5 : _first_entry_T_36; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_38 = _first_entry_T_32 ? 3'h4 : _first_entry_T_37; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_39 = _first_entry_T_31 ? 3'h3 : _first_entry_T_38; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_40 = _first_entry_T_30 ? 3'h2 : _first_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_41 = _first_entry_T_29 ? 3'h1 : _first_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] first_entry_2 = _first_entry_T_28 ? 3'h0 : _first_entry_T_41; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_30 = {2'h0, allocatable_slots_2[5:0] & alloc_lfsr_2}; // @[PRNG.scala:95:17] wire _masked_entry_T_31 = _masked_entry_T_30[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_32 = _masked_entry_T_30[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_33 = _masked_entry_T_30[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_34 = _masked_entry_T_30[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_35 = _masked_entry_T_30[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_36 = _masked_entry_T_30[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_37 = _masked_entry_T_30[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_38 = _masked_entry_T_30[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_39 = {2'h3, ~_masked_entry_T_37}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_40 = _masked_entry_T_36 ? 3'h5 : _masked_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_41 = _masked_entry_T_35 ? 3'h4 : _masked_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_42 = _masked_entry_T_34 ? 3'h3 : _masked_entry_T_41; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_43 = _masked_entry_T_33 ? 3'h2 : _masked_entry_T_42; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_44 = _masked_entry_T_32 ? 3'h1 : _masked_entry_T_43; // @[OneHot.scala:48:45] wire [2:0] masked_entry_2 = _masked_entry_T_31 ? 3'h0 : _masked_entry_T_44; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_4 = allocatable_slots_2 >> masked_entry_2; // @[Mux.scala:50:70] wire _alloc_entry_T_5 = _alloc_entry_T_4[0]; // @[tage.scala:289:44] assign alloc_entry_2 = _alloc_entry_T_5 ? masked_entry_2 : first_entry_2; // @[Mux.scala:50:70] assign f3_meta_allocate_2_bits = alloc_entry_2; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_2_valid_T = \|allocatable_slots_2; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_2_valid = _f3_meta_allocate_2_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_4 = s1_update_bits_cfi_idx_bits == 2'h2; // @[tage.scala:297:58] wire _update_was_taken_T_5 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_4; // @[tage.scala:296:58, :297:58] wire update_was_taken_2 = _update_was_taken_T_5 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_106 = s1_update_bits_br_mask[2] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_26 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_27 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_28 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_29 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_30 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_31 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_22 = s1_update_mispredict_mask[2]; // @[tage.scala:237:73, :308:52] wire _new_u_T_23 = ~s1_update_meta_alt_differs_2; // @[tage.scala:217:9, :236:52] wire _new_u_T_24 = s1_update_meta_provider_u_2 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_32 = {1'h0, s1_update_meta_provider_u_2}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_25 = _GEN_32 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_26 = _new_u_T_25[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_27 = _new_u_T_24 ? 2'h0 : _new_u_T_26; // @[tage.scala:218:{24,27,43}] wire _new_u_T_28 = &s1_update_meta_provider_u_2; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_29 = _GEN_32 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_30 = _new_u_T_29[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_31 = _new_u_T_28 ? 2'h3 : _new_u_T_30; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_32 = _new_u_T_22 ? _new_u_T_27 : _new_u_T_31; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_2 = _new_u_T_23 ? s1_update_meta_provider_u_2 : _new_u_T_32; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_3; // @[tage.scala:256:33] wire _io_resp_f3_3_taken_T = f3_resps_0_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_1 = f3_resps_0_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_2 = _io_resp_f3_3_taken_T \| _io_resp_f3_3_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_3 = f3_resps_0_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_4 = _io_resp_f3_3_taken_T_2 ? io_resp_in_0_f3_3_taken_0 : _io_resp_f3_3_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_110 = f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_5 = f3_resps_1_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_6 = f3_resps_1_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_7 = _io_resp_f3_3_taken_T_5 \| _io_resp_f3_3_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_8 = f3_resps_1_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_9 = _io_resp_f3_3_taken_T_7 ? _T_110 : _io_resp_f3_3_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_114 = f3_resps_1_3_valid ? f3_resps_1_3_bits_ctr[2] : _T_110; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_10 = f3_resps_2_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_11 = f3_resps_2_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_12 = _io_resp_f3_3_taken_T_10 \| _io_resp_f3_3_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_13 = f3_resps_2_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_14 = _io_resp_f3_3_taken_T_12 ? _T_114 : _io_resp_f3_3_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_118 = f3_resps_2_3_valid ? f3_resps_2_3_bits_ctr[2] : _T_114; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_15 = f3_resps_3_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_16 = f3_resps_3_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_17 = _io_resp_f3_3_taken_T_15 \| _io_resp_f3_3_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_18 = f3_resps_3_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_19 = _io_resp_f3_3_taken_T_17 ? _T_118 : _io_resp_f3_3_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_122 = f3_resps_3_3_valid ? f3_resps_3_3_bits_ctr[2] : _T_118; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_20 = f3_resps_4_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_21 = f3_resps_4_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_22 = _io_resp_f3_3_taken_T_20 \| _io_resp_f3_3_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_23 = f3_resps_4_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_24 = _io_resp_f3_3_taken_T_22 ? _T_122 : _io_resp_f3_3_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_126 = f3_resps_4_3_valid ? f3_resps_4_3_bits_ctr[2] : _T_122; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_25 = f3_resps_5_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_26 = f3_resps_5_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_27 = _io_resp_f3_3_taken_T_25 \| _io_resp_f3_3_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_28 = f3_resps_5_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_29 = _io_resp_f3_3_taken_T_27 ? _T_126 : _io_resp_f3_3_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_3_taken_0 = f3_resps_5_3_valid ? _io_resp_f3_3_taken_T_29 : f3_resps_4_3_valid ? _io_resp_f3_3_taken_T_24 : f3_resps_3_3_valid ? _io_resp_f3_3_taken_T_19 : f3_resps_2_3_valid ? _io_resp_f3_3_taken_T_14 : f3_resps_1_3_valid ? _io_resp_f3_3_taken_T_9 : f3_resps_0_3_valid ? _io_resp_f3_3_taken_T_4 : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_3 = f3_resps_5_3_valid ? _T_126 : f3_resps_4_3_valid ? _T_122 : f3_resps_3_3_valid ? _T_118 : f3_resps_2_3_valid ? _T_114 : f3_resps_1_3_valid & f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_3_valid = f3_resps_0_3_valid \| f3_resps_1_3_valid \| f3_resps_2_3_valid \| f3_resps_3_3_valid \| f3_resps_4_3_valid \| f3_resps_5_3_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_3_bits = f3_resps_5_3_valid ? 3'h5 : f3_resps_4_3_valid ? 3'h4 : {1'h0, f3_resps_3_3_valid ? 2'h3 : f3_resps_2_3_valid ? 2'h2 : {1'h0, f3_resps_1_3_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_3_T = final_altpred_3 != io_resp_f3_3_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_3 = _f3_meta_alt_differs_3_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_33 = {{f3_resps_0_3_bits_ctr}, {f3_resps_0_3_bits_ctr}, {f3_resps_5_3_bits_ctr}, {f3_resps_4_3_bits_ctr}, {f3_resps_3_3_bits_ctr}, {f3_resps_2_3_bits_ctr}, {f3_resps_1_3_bits_ctr}, {f3_resps_0_3_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_3 = _GEN_33[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_34 = {{f3_resps_0_3_bits_u}, {f3_resps_0_3_bits_u}, {f3_resps_5_3_bits_u}, {f3_resps_4_3_bits_u}, {f3_resps_3_3_bits_u}, {f3_resps_2_3_bits_u}, {f3_resps_1_3_bits_u}, {f3_resps_0_3_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_3 = _GEN_34[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_114 = ~f3_resps_0_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_115 = f3_resps_0_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_116 = _allocatable_slots_T_114 & _allocatable_slots_T_115; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_0 = _allocatable_slots_T_116; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_117 = ~f3_resps_1_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_118 = f3_resps_1_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_119 = _allocatable_slots_T_117 & _allocatable_slots_T_118; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_1 = _allocatable_slots_T_119; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_120 = ~f3_resps_2_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_121 = f3_resps_2_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_122 = _allocatable_slots_T_120 & _allocatable_slots_T_121; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_2 = _allocatable_slots_T_122; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_123 = ~f3_resps_3_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_124 = f3_resps_3_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_125 = _allocatable_slots_T_123 & _allocatable_slots_T_124; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_3 = _allocatable_slots_T_125; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_126 = ~f3_resps_4_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_127 = f3_resps_4_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_128 = _allocatable_slots_T_126 & _allocatable_slots_T_127; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_4 = _allocatable_slots_T_128; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_129 = ~f3_resps_5_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_130 = f3_resps_5_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_131 = _allocatable_slots_T_129 & _allocatable_slots_T_130; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_5 = _allocatable_slots_T_131; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_3 = {_allocatable_slots_WIRE_3_2, _allocatable_slots_WIRE_3_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_3 = {allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_3 = {_allocatable_slots_WIRE_3_5, _allocatable_slots_WIRE_3_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_3 = {allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_132 = {allocatable_slots_hi_3, allocatable_slots_lo_3}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_133 = 8'h1 << f3_meta_provider_3_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_134 = _allocatable_slots_T_133; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_135 = {1'h0, _allocatable_slots_T_133[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_136 = {2'h0, _allocatable_slots_T_133[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_137 = {3'h0, _allocatable_slots_T_133[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_138 = {4'h0, _allocatable_slots_T_133[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_139 = {5'h0, _allocatable_slots_T_133[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_140 = {6'h0, _allocatable_slots_T_133[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_141 = {7'h0, _allocatable_slots_T_133[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_142 = _allocatable_slots_T_134 \| _allocatable_slots_T_135; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_143 = _allocatable_slots_T_142 \| _allocatable_slots_T_136; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_144 = _allocatable_slots_T_143 \| _allocatable_slots_T_137; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_145 = _allocatable_slots_T_144 \| _allocatable_slots_T_138; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_146 = _allocatable_slots_T_145 \| _allocatable_slots_T_139; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_147 = _allocatable_slots_T_146 \| _allocatable_slots_T_140; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_148 = _allocatable_slots_T_147 \| _allocatable_slots_T_141; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_149 = {6{f3_meta_provider_3_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_150 = {2'h0, _allocatable_slots_T_148[5:0] & _allocatable_slots_T_149}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_151 = ~_allocatable_slots_T_150; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_3 = {2'h0, _allocatable_slots_T_151[5:0] & _allocatable_slots_T_132}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_3 = {_alloc_lfsr_prng_3_io_out_2, _alloc_lfsr_prng_3_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_3 = {alloc_lfsr_lo_hi_3, _alloc_lfsr_prng_3_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_3 = {_alloc_lfsr_prng_3_io_out_5, _alloc_lfsr_prng_3_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_3 = {alloc_lfsr_hi_hi_3, _alloc_lfsr_prng_3_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_3 = {alloc_lfsr_hi_3, alloc_lfsr_lo_3}; // @[PRNG.scala:95:17] wire _first_entry_T_42 = allocatable_slots_3[0]; // @[OneHot.scala:48:45] wire _first_entry_T_43 = allocatable_slots_3[1]; // @[OneHot.scala:48:45] wire _first_entry_T_44 = allocatable_slots_3[2]; // @[OneHot.scala:48:45] wire _first_entry_T_45 = allocatable_slots_3[3]; // @[OneHot.scala:48:45] wire _first_entry_T_46 = allocatable_slots_3[4]; // @[OneHot.scala:48:45] wire _first_entry_T_47 = allocatable_slots_3[5]; // @[OneHot.scala:48:45] wire _first_entry_T_48 = allocatable_slots_3[6]; // @[OneHot.scala:48:45] wire _first_entry_T_49 = allocatable_slots_3[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_50 = {2'h3, ~_first_entry_T_48}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_51 = _first_entry_T_47 ? 3'h5 : _first_entry_T_50; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_52 = _first_entry_T_46 ? 3'h4 : _first_entry_T_51; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_53 = _first_entry_T_45 ? 3'h3 : _first_entry_T_52; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_54 = _first_entry_T_44 ? 3'h2 : _first_entry_T_53; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_55 = _first_entry_T_43 ? 3'h1 : _first_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] first_entry_3 = _first_entry_T_42 ? 3'h0 : _first_entry_T_55; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_45 = {2'h0, allocatable_slots_3[5:0] & alloc_lfsr_3}; // @[PRNG.scala:95:17] wire _masked_entry_T_46 = _masked_entry_T_45[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_47 = _masked_entry_T_45[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_48 = _masked_entry_T_45[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_49 = _masked_entry_T_45[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_50 = _masked_entry_T_45[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_51 = _masked_entry_T_45[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_52 = _masked_entry_T_45[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_53 = _masked_entry_T_45[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_54 = {2'h3, ~_masked_entry_T_52}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_55 = _masked_entry_T_51 ? 3'h5 : _masked_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_56 = _masked_entry_T_50 ? 3'h4 : _masked_entry_T_55; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_57 = _masked_entry_T_49 ? 3'h3 : _masked_entry_T_56; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_58 = _masked_entry_T_48 ? 3'h2 : _masked_entry_T_57; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_59 = _masked_entry_T_47 ? 3'h1 : _masked_entry_T_58; // @[OneHot.scala:48:45] wire [2:0] masked_entry_3 = _masked_entry_T_46 ? 3'h0 : _masked_entry_T_59; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_6 = allocatable_slots_3 >> masked_entry_3; // @[Mux.scala:50:70] wire _alloc_entry_T_7 = _alloc_entry_T_6[0]; // @[tage.scala:289:44] assign alloc_entry_3 = _alloc_entry_T_7 ? masked_entry_3 : first_entry_3; // @[Mux.scala:50:70] assign f3_meta_allocate_3_bits = alloc_entry_3; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_3_valid_T = \|allocatable_slots_3; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_3_valid = _f3_meta_allocate_3_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_6 = &s1_update_bits_cfi_idx_bits; // @[tage.scala:297:58] wire _update_was_taken_T_7 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_6; // @[tage.scala:296:58, :297:58] wire update_was_taken_3 = _update_was_taken_T_7 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_137 = s1_update_bits_br_mask[3] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_35 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_36 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_37 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_38 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_39 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_40 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_33 = s1_update_mispredict_mask[3]; // @[tage.scala:237:73, :308:52] wire _new_u_T_34 = ~s1_update_meta_alt_differs_3; // @[tage.scala:217:9, :236:52] wire _new_u_T_35 = s1_update_meta_provider_u_3 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_41 = {1'h0, s1_update_meta_provider_u_3}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_36 = _GEN_41 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_37 = _new_u_T_36[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_38 = _new_u_T_35 ? 2'h0 : _new_u_T_37; // @[tage.scala:218:{24,27,43}] wire _new_u_T_39 = &s1_update_meta_provider_u_3; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_40 = _GEN_41 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_41 = _new_u_T_40[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_42 = _new_u_T_39 ? 2'h3 : _new_u_T_41; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_43 = _new_u_T_33 ? _new_u_T_38 : _new_u_T_42; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_3 = _new_u_T_34 ? s1_update_meta_provider_u_3 : _new_u_T_43; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire _T_144 = s1_update_valid & _GEN_7 == 5'h0 & s1_update_bits_cfi_mispredicted & s1_update_bits_cfi_idx_valid; // @[OneHot.scala:58:35] wire [3:0] _GEN_42 = {{s1_update_meta_allocate_3_valid}, {s1_update_meta_allocate_2_valid}, {s1_update_meta_allocate_1_valid}, {s1_update_meta_allocate_0_valid}}; // @[tage.scala:236:52, :320:27] wire _GEN_43 = _GEN_42[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire [3:0][2:0] _GEN_44 = {{s1_update_meta_allocate_3_bits}, {s1_update_meta_allocate_2_bits}, {s1_update_meta_allocate_1_bits}, {s1_update_meta_allocate_0_bits}}; // @[tage.scala:236:52, :320:27] wire [2:0] _GEN_45 = _GEN_44[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire _GEN_46 = _GEN_45 == 3'h0; // @[tage.scala:320:27, :321:43] wire _GEN_47 = _T_144 & _GEN_43 & _GEN_46; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_0_0 = _GEN_47 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_0 = s1_update_alloc_0_0 \| _GEN_8; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_1 = _GEN_47 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_1 = s1_update_alloc_0_1 \| _GEN_17; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_2 = _GEN_47 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_2 = s1_update_alloc_0_2 \| _GEN_26; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_3 = _GEN_47 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_3 = s1_update_alloc_0_3 \| _GEN_35; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_48 = _GEN_45 == 3'h1; // @[tage.scala:218:43, :320:27, :321:43] wire _GEN_49 = _T_144 & _GEN_43 & _GEN_48; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_1_0 = _GEN_49 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_0 = s1_update_alloc_1_0 \| _GEN_9; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_1 = _GEN_49 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_1 = s1_update_alloc_1_1 \| _GEN_18; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_2 = _GEN_49 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_2 = s1_update_alloc_1_2 \| _GEN_27; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_3 = _GEN_49 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_3 = s1_update_alloc_1_3 \| _GEN_36; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_50 = _GEN_45 == 3'h2; // @[tage.scala:320:27, :321:43] wire _GEN_51 = _T_144 & _GEN_43 & _GEN_50; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_2_0 = _GEN_51 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_0 = s1_update_alloc_2_0 \| _GEN_10; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_1 = _GEN_51 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_1 = s1_update_alloc_2_1 \| _GEN_19; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_2 = _GEN_51 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_2 = s1_update_alloc_2_2 \| _GEN_28; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_3 = _GEN_51 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_3 = s1_update_alloc_2_3 \| _GEN_37; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_52 = _GEN_45 == 3'h3; // @[tage.scala:265:40, :320:27, :321:43] wire _GEN_53 = _T_144 & _GEN_43 & _GEN_52; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_3_0 = _GEN_53 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_0 = s1_update_alloc_3_0 \| _GEN_11; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_1 = _GEN_53 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_1 = s1_update_alloc_3_1 \| _GEN_20; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_2 = _GEN_53 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_2 = s1_update_alloc_3_2 \| _GEN_29; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_3 = _GEN_53 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_3 = s1_update_alloc_3_3 \| _GEN_38; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_54 = _GEN_45 == 3'h4; // @[tage.scala:320:27, :321:43] wire _GEN_55 = _T_144 & _GEN_43 & _GEN_54; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_4_0 = _GEN_55 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_0 = s1_update_alloc_4_0 \| _GEN_12; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_1 = _GEN_55 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_1 = s1_update_alloc_4_1 \| _GEN_21; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_2 = _GEN_55 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_2 = s1_update_alloc_4_2 \| _GEN_30; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_3 = _GEN_55 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_3 = s1_update_alloc_4_3 \| _GEN_39; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_56 = _GEN_45 == 3'h5; // @[tage.scala:320:27, :321:43] wire _GEN_57 = _T_144 & _GEN_43 & _GEN_56; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_5_0 = _GEN_57 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_0 = s1_update_alloc_5_0 \| _GEN_13; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_1 = _GEN_57 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_1 = s1_update_alloc_5_1 \| _GEN_22; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_2 = _GEN_57 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_2 = s1_update_alloc_5_2 \| _GEN_31; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_3 = _GEN_57 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_3 = s1_update_alloc_5_3 \| _GEN_40; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_58 = _GEN_46 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_0 = _T_144 & _GEN_43 & _GEN_58 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_59 = _GEN_46 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_1 = _T_144 & _GEN_43 & _GEN_59 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_60 = _GEN_46 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_2 = _T_144 & _GEN_43 & _GEN_60 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_61 = _GEN_46 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_3 = _T_144 & _GEN_43 & _GEN_61 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_62 = _GEN_48 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_0 = _T_144 & _GEN_43 & _GEN_62 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_63 = _GEN_48 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_1 = _T_144 & _GEN_43 & _GEN_63 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_64 = _GEN_48 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_2 = _T_144 & _GEN_43 & _GEN_64 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_65 = _GEN_48 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_3 = _T_144 & _GEN_43 & _GEN_65 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_66 = _GEN_50 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_0 = _T_144 & _GEN_43 & _GEN_66 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_67 = _GEN_50 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_1 = _T_144 & _GEN_43 & _GEN_67 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_68 = _GEN_50 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_2 = _T_144 & _GEN_43 & _GEN_68 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_69 = _GEN_50 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_3 = _T_144 & _GEN_43 & _GEN_69 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_70 = _GEN_52 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_0 = _T_144 & _GEN_43 & _GEN_70 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_71 = _GEN_52 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_1 = _T_144 & _GEN_43 & _GEN_71 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_72 = _GEN_52 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_2 = _T_144 & _GEN_43 & _GEN_72 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_73 = _GEN_52 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_3 = _T_144 & _GEN_43 & _GEN_73 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_74 = _GEN_54 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_0 = _T_144 & _GEN_43 & _GEN_74 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_75 = _GEN_54 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_1 = _T_144 & _GEN_43 & _GEN_75 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_76 = _GEN_54 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_2 = _T_144 & _GEN_43 & _GEN_76 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_77 = _GEN_54 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_3 = _T_144 & _GEN_43 & _GEN_77 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_78 = _GEN_56 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_0 = _T_144 & _GEN_43 & _GEN_78 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_79 = _GEN_56 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_1 = _T_144 & _GEN_43 & _GEN_79 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_80 = _GEN_56 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_2 = _T_144 & _GEN_43 & _GEN_80 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_81 = _GEN_56 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_3 = _T_144 & _GEN_43 & _GEN_81 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire [3:0] _GEN_82 = {{s1_update_meta_provider_3_valid}, {s1_update_meta_provider_2_valid}, {s1_update_meta_provider_1_valid}, {s1_update_meta_provider_0_valid}}; // @[OneHot.scala:58:35] wire [3:0][2:0] _GEN_83 = {{s1_update_meta_provider_3_bits}, {s1_update_meta_provider_2_bits}, {s1_update_meta_provider_1_bits}, {s1_update_meta_provider_0_bits}}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T = 8'h1 << _GEN_83[s1_update_bits_cfi_idx_bits]; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_1 = _decr_mask_T; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_2 = {1'h0, _decr_mask_T[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_3 = {2'h0, _decr_mask_T[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_4 = {3'h0, _decr_mask_T[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_5 = {4'h0, _decr_mask_T[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_6 = {5'h0, _decr_mask_T[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_7 = {6'h0, _decr_mask_T[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_8 = {7'h0, _decr_mask_T[7]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_9 = _decr_mask_T_1 \| _decr_mask_T_2; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_10 = _decr_mask_T_9 \| _decr_mask_T_3; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_11 = _decr_mask_T_10 \| _decr_mask_T_4; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_12 = _decr_mask_T_11 \| _decr_mask_T_5; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_13 = _decr_mask_T_12 \| _decr_mask_T_6; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_14 = _decr_mask_T_13 \| _decr_mask_T_7; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_15 = _decr_mask_T_14 \| _decr_mask_T_8; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_16 = ~_decr_mask_T_15; // @[util.scala:373:45] wire [7:0] decr_mask = _GEN_82[s1_update_bits_cfi_idx_bits] ? _decr_mask_T_16 : 8'h0; // @[OneHot.scala:58:35] assign s1_update_u_mask_0_0 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T \| _GEN_8 : decr_mask[0] & _update_was_taken_T \| _GEN_8) : _GEN_8; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_1 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_2 \| _GEN_17 : decr_mask[0] & _update_was_taken_T_2 \| _GEN_17) : _GEN_17; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_2 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_4 \| _GEN_26 : decr_mask[0] & _update_was_taken_T_4 \| _GEN_26) : _GEN_26; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_3 = _T_144 ? (_GEN_43 ? _GEN_46 & (&s1_update_bits_cfi_idx_bits) \| _GEN_35 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits) \| _GEN_35) : _GEN_35; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_0_0 = _T_144 & (_GEN_43 ? _GEN_58 : decr_mask[0] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_1 = _T_144 & (_GEN_43 ? _GEN_59 : decr_mask[0] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_2 = _T_144 & (_GEN_43 ? _GEN_60 : decr_mask[0] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_3 = _T_144 & (_GEN_43 ? _GEN_61 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_1_0 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T \| _GEN_9 : decr_mask[1] & _update_was_taken_T \| _GEN_9) : _GEN_9; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_1 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_2 \| _GEN_18 : decr_mask[1] & _update_was_taken_T_2 \| _GEN_18) : _GEN_18; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_2 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_4 \| _GEN_27 : decr_mask[1] & _update_was_taken_T_4 \| _GEN_27) : _GEN_27; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_3 = _T_144 ? (_GEN_43 ? _GEN_48 & (&s1_update_bits_cfi_idx_bits) \| _GEN_36 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits) \| _GEN_36) : _GEN_36; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_1_0 = _T_144 & (_GEN_43 ? _GEN_62 : decr_mask[1] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_1 = _T_144 & (_GEN_43 ? _GEN_63 : decr_mask[1] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_2 = _T_144 & (_GEN_43 ? _GEN_64 : decr_mask[1] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_3 = _T_144 & (_GEN_43 ? _GEN_65 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_2_0 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T \| _GEN_10 : decr_mask[2] & _update_was_taken_T \| _GEN_10) : _GEN_10; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_1 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_2 \| _GEN_19 : decr_mask[2] & _update_was_taken_T_2 \| _GEN_19) : _GEN_19; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_2 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_4 \| _GEN_28 : decr_mask[2] & _update_was_taken_T_4 \| _GEN_28) : _GEN_28; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_3 = _T_144 ? (_GEN_43 ? _GEN_50 & (&s1_update_bits_cfi_idx_bits) \| _GEN_37 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits) \| _GEN_37) : _GEN_37; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_2_0 = _T_144 & (_GEN_43 ? _GEN_66 : decr_mask[2] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_1 = _T_144 & (_GEN_43 ? _GEN_67 : decr_mask[2] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_2 = _T_144 & (_GEN_43 ? _GEN_68 : decr_mask[2] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_3 = _T_144 & (_GEN_43 ? _GEN_69 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_3_0 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T \| _GEN_11 : decr_mask[3] & _update_was_taken_T \| _GEN_11) : _GEN_11; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_1 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_2 \| _GEN_20 : decr_mask[3] & _update_was_taken_T_2 \| _GEN_20) : _GEN_20; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_2 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_4 \| _GEN_29 : decr_mask[3] & _update_was_taken_T_4 \| _GEN_29) : _GEN_29; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_3 = _T_144 ? (_GEN_43 ? _GEN_52 & (&s1_update_bits_cfi_idx_bits) \| _GEN_38 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits) \| _GEN_38) : _GEN_38; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_3_0 = _T_144 & (_GEN_43 ? _GEN_70 : decr_mask[3] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_1 = _T_144 & (_GEN_43 ? _GEN_71 : decr_mask[3] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_2 = _T_144 & (_GEN_43 ? _GEN_72 : decr_mask[3] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_3 = _T_144 & (_GEN_43 ? _GEN_73 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_4_0 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T \| _GEN_12 : decr_mask[4] & _update_was_taken_T \| _GEN_12) : _GEN_12; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_1 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_2 \| _GEN_21 : decr_mask[4] & _update_was_taken_T_2 \| _GEN_21) : _GEN_21; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_2 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_4 \| _GEN_30 : decr_mask[4] & _update_was_taken_T_4 \| _GEN_30) : _GEN_30; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_3 = _T_144 ? (_GEN_43 ? _GEN_54 & (&s1_update_bits_cfi_idx_bits) \| _GEN_39 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits) \| _GEN_39) : _GEN_39; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_4_0 = _T_144 & (_GEN_43 ? _GEN_74 : decr_mask[4] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_1 = _T_144 & (_GEN_43 ? _GEN_75 : decr_mask[4] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_2 = _T_144 & (_GEN_43 ? _GEN_76 : decr_mask[4] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_3 = _T_144 & (_GEN_43 ? _GEN_77 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_5_0 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T \| _GEN_13 : decr_mask[5] & _update_was_taken_T \| _GEN_13) : _GEN_13; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_1 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_2 \| _GEN_22 : decr_mask[5] & _update_was_taken_T_2 \| _GEN_22) : _GEN_22; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_2 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_4 \| _GEN_31 : decr_mask[5] & _update_was_taken_T_4 \| _GEN_31) : _GEN_31; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_3 = _T_144 ? (_GEN_43 ? _GEN_56 & (&s1_update_bits_cfi_idx_bits) \| _GEN_40 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits) \| _GEN_40) : _GEN_40; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_5_0 = _T_144 & (_GEN_43 ? _GEN_78 : decr_mask[5] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_1 = _T_144 & (_GEN_43 ? _GEN_79 : decr_mask[5] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_2 = _T_144 & (_GEN_43 ? _GEN_80 : decr_mask[5] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_3 = _T_144 & (_GEN_43 ? _GEN_81 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] reg tt_0_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_0_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_0_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_1_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_1_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_1_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_2_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_2_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_2_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_3_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_3_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_3_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_4_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_4_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_4_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_5_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_5_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_5_1_io_update_hist_REG; // @[tage.scala:354:41] wire [7:0] io_f3_meta_lo = {_io_f3_meta_T_1, _io_f3_meta_T}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi = {_io_f3_meta_T_3, _io_f3_meta_T_2}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_4 = {io_f3_meta_hi, io_f3_meta_lo}; // @[tage.scala:359:25] wire [11:0] _io_f3_meta_T_5 = {io_f3_meta_hi_1, io_f3_meta_lo_1}; // @[tage.scala:359:25] wire [7:0] _io_f3_meta_T_6 = {io_f3_meta_hi_2, io_f3_meta_lo_2}; // @[tage.scala:359:25] wire [3:0] _io_f3_meta_T_7 = {io_f3_meta_hi_3, io_f3_meta_lo_3}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_lo_4 = {_io_f3_meta_T_9, _io_f3_meta_T_8}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi_4 = {_io_f3_meta_T_11, _io_f3_meta_T_10}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_12 = {io_f3_meta_hi_4, io_f3_meta_lo_4}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_lo_5 = {_io_f3_meta_T_5, _io_f3_meta_T_4}; // @[tage.scala:359:25] wire [19:0] io_f3_meta_hi_hi = {_io_f3_meta_T_12, _io_f3_meta_T_7}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_hi_5 = {io_f3_meta_hi_hi, _io_f3_meta_T_6}; // @[tage.scala:359:25] wire [55:0] _io_f3_meta_T_13 = {io_f3_meta_hi_5, io_f3_meta_lo_5}; // @[tage.scala:359:25] assign io_f3_meta_0 = {64'h0, _io_f3_meta_T_13}; // @[tage.scala:198:7, :359:{14,25}] always @(posedge clock) begin // @[tage.scala:198:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[tage.scala:198:7] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[tage.scala:198:7] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[tage.scala:198:7] s1_update_valid <= io_update_valid_0; // @[tage.scala:198:7] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[tage.scala:198:7] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[tage.scala:198:7] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[tage.scala:198:7] s1_update_bits_pc <= io_update_bits_pc_0; // @[tage.scala:198:7] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[tage.scala:198:7] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[tage.scala:198:7] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[tage.scala:198:7] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[tage.scala:198:7] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[tage.scala:198:7] s1_update_bits_target <= io_update_bits_target_0; // @[tage.scala:198:7] s1_update_bits_meta <= io_update_bits_meta_0; // @[tage.scala:198:7] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[tage.scala:198:7] t_io_f1_req_valid_REG <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_1 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_1 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_2 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_2 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_3 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_3 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_4 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_4 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_5 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_5 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] tt_0_1_io_update_mask_0_REG <= s1_update_mask_0_0; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_0_REG <= s1_update_taken_0_0; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_0_REG <= s1_update_alloc_0_0; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_0_0; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_0_REG <= s1_update_u_mask_0_0; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_0_REG <= s1_update_u_0_0; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_1_REG <= s1_update_mask_0_1; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_1_REG <= s1_update_taken_0_1; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_1_REG <= s1_update_alloc_0_1; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_0_1; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_1_REG <= s1_update_u_mask_0_1; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_1_REG <= s1_update_u_0_1; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_2_REG <= s1_update_mask_0_2; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_2_REG <= s1_update_taken_0_2; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_2_REG <= s1_update_alloc_0_2; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_0_2; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_2_REG <= s1_update_u_mask_0_2; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_2_REG <= s1_update_u_0_2; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_3_REG <= s1_update_mask_0_3; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_3_REG <= s1_update_taken_0_3; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_3_REG <= s1_update_alloc_0_3; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_0_3; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_3_REG <= s1_update_u_mask_0_3; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_3_REG <= s1_update_u_0_3; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_0_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_1_1_io_update_mask_0_REG <= s1_update_mask_1_0; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_0_REG <= s1_update_taken_1_0; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_0_REG <= s1_update_alloc_1_0; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_1_0; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_0_REG <= s1_update_u_mask_1_0; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_0_REG <= s1_update_u_1_0; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_1_REG <= s1_update_mask_1_1; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_1_REG <= s1_update_taken_1_1; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_1_REG <= s1_update_alloc_1_1; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_1_1; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_1_REG <= s1_update_u_mask_1_1; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_1_REG <= s1_update_u_1_1; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_2_REG <= s1_update_mask_1_2; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_2_REG <= s1_update_taken_1_2; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_2_REG <= s1_update_alloc_1_2; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_1_2; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_2_REG <= s1_update_u_mask_1_2; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_2_REG <= s1_update_u_1_2; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_3_REG <= s1_update_mask_1_3; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_3_REG <= s1_update_taken_1_3; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_3_REG <= s1_update_alloc_1_3; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_1_3; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_3_REG <= s1_update_u_mask_1_3; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_3_REG <= s1_update_u_1_3; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_1_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_2_1_io_update_mask_0_REG <= s1_update_mask_2_0; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_0_REG <= s1_update_taken_2_0; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_0_REG <= s1_update_alloc_2_0; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_2_0; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_0_REG <= s1_update_u_mask_2_0; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_0_REG <= s1_update_u_2_0; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_1_REG <= s1_update_mask_2_1; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_1_REG <= s1_update_taken_2_1; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_1_REG <= s1_update_alloc_2_1; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_2_1; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_1_REG <= s1_update_u_mask_2_1; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_1_REG <= s1_update_u_2_1; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_2_REG <= s1_update_mask_2_2; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_2_REG <= s1_update_taken_2_2; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_2_REG <= s1_update_alloc_2_2; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_2_2; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_2_REG <= s1_update_u_mask_2_2; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_2_REG <= s1_update_u_2_2; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_3_REG <= s1_update_mask_2_3; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_3_REG <= s1_update_taken_2_3; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_3_REG <= s1_update_alloc_2_3; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_2_3; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_3_REG <= s1_update_u_mask_2_3; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_3_REG <= s1_update_u_2_3; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_2_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_3_1_io_update_mask_0_REG <= s1_update_mask_3_0; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_0_REG <= s1_update_taken_3_0; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_0_REG <= s1_update_alloc_3_0; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_3_0; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_0_REG <= s1_update_u_mask_3_0; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_0_REG <= s1_update_u_3_0; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_1_REG <= s1_update_mask_3_1; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_1_REG <= s1_update_taken_3_1; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_1_REG <= s1_update_alloc_3_1; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_3_1; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_1_REG <= s1_update_u_mask_3_1; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_1_REG <= s1_update_u_3_1; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_2_REG <= s1_update_mask_3_2; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_2_REG <= s1_update_taken_3_2; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_2_REG <= s1_update_alloc_3_2; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_3_2; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_2_REG <= s1_update_u_mask_3_2; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_2_REG <= s1_update_u_3_2; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_3_REG <= s1_update_mask_3_3; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_3_REG <= s1_update_taken_3_3; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_3_REG <= s1_update_alloc_3_3; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_3_3; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_3_REG <= s1_update_u_mask_3_3; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_3_REG <= s1_update_u_3_3; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_3_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_4_1_io_update_mask_0_REG <= s1_update_mask_4_0; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_0_REG <= s1_update_taken_4_0; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_0_REG <= s1_update_alloc_4_0; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_4_0; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_0_REG <= s1_update_u_mask_4_0; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_0_REG <= s1_update_u_4_0; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_1_REG <= s1_update_mask_4_1; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_1_REG <= s1_update_taken_4_1; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_1_REG <= s1_update_alloc_4_1; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_4_1; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_1_REG <= s1_update_u_mask_4_1; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_1_REG <= s1_update_u_4_1; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_2_REG <= s1_update_mask_4_2; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_2_REG <= s1_update_taken_4_2; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_2_REG <= s1_update_alloc_4_2; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_4_2; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_2_REG <= s1_update_u_mask_4_2; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_2_REG <= s1_update_u_4_2; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_3_REG <= s1_update_mask_4_3; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_3_REG <= s1_update_taken_4_3; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_3_REG <= s1_update_alloc_4_3; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_4_3; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_3_REG <= s1_update_u_mask_4_3; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_3_REG <= s1_update_u_4_3; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_4_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_5_1_io_update_mask_0_REG <= s1_update_mask_5_0; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_0_REG <= s1_update_taken_5_0; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_0_REG <= s1_update_alloc_5_0; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_5_0; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_0_REG <= s1_update_u_mask_5_0; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_0_REG <= s1_update_u_5_0; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_1_REG <= s1_update_mask_5_1; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_1_REG <= s1_update_taken_5_1; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_1_REG <= s1_update_alloc_5_1; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_5_1; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_1_REG <= s1_update_u_mask_5_1; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_1_REG <= s1_update_u_5_1; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_2_REG <= s1_update_mask_5_2; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_2_REG <= s1_update_taken_5_2; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_2_REG <= s1_update_alloc_5_2; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_5_2; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_2_REG <= s1_update_u_mask_5_2; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_2_REG <= s1_update_u_5_2; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_3_REG <= s1_update_mask_5_3; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_3_REG <= s1_update_taken_5_3; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_3_REG <= s1_update_alloc_5_3; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_5_3; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_3_REG <= s1_update_u_mask_5_3; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_3_REG <= s1_update_u_5_3; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_5_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] always @(posedge) TageTable_18 tt_0_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_0_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_0_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_0_0_bits_u), .io_f3_resp_1_valid (f3_resps_0_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_0_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_0_1_bits_u), .io_f3_resp_2_valid (f3_resps_0_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_0_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_0_2_bits_u), .io_f3_resp_3_valid (f3_resps_0_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_0_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_0_3_bits_u), .io_update_mask_0 (tt_0_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_0_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_0_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_0_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_0_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_0_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_0_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_0_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_0_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_0_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_0_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_0_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_0_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_0_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_0_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_0_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_0_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_0_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_0_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_0_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_0_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_0_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_0_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_0_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_0_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_0_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_19 tt_1_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_1), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_1), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_1_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_1_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_1_0_bits_u), .io_f3_resp_1_valid (f3_resps_1_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_1_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_1_1_bits_u), .io_f3_resp_2_valid (f3_resps_1_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_1_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_1_2_bits_u), .io_f3_resp_3_valid (f3_resps_1_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_1_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_1_3_bits_u), .io_update_mask_0 (tt_1_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_1_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_1_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_1_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_1_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_1_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_1_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_1_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_1_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_1_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_1_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_1_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_1_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_1_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_1_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_1_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_1_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_1_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_1_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_1_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_1_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_1_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_1_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_1_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_1_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_1_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_20 tt_2_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_2), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_2), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_2_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_2_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_2_0_bits_u), .io_f3_resp_1_valid (f3_resps_2_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_2_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_2_1_bits_u), .io_f3_resp_2_valid (f3_resps_2_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_2_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_2_2_bits_u), .io_f3_resp_3_valid (f3_resps_2_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_2_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_2_3_bits_u), .io_update_mask_0 (tt_2_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_2_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_2_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_2_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_2_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_2_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_2_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_2_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_2_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_2_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_2_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_2_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_2_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_2_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_2_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_2_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_2_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_2_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_2_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_2_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_2_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_2_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_2_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_2_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_2_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_2_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_21 tt_3_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_3), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_3), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_3_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_3_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_3_0_bits_u), .io_f3_resp_1_valid (f3_resps_3_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_3_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_3_1_bits_u), .io_f3_resp_2_valid (f3_resps_3_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_3_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_3_2_bits_u), .io_f3_resp_3_valid (f3_resps_3_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_3_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_3_3_bits_u), .io_update_mask_0 (tt_3_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_3_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_3_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_3_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_3_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_3_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_3_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_3_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_3_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_3_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_3_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_3_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_3_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_3_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_3_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_3_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_3_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_3_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_3_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_3_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_3_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_3_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_3_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_3_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_3_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_3_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_22 tt_4_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_4), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_4), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_4_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_4_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_4_0_bits_u), .io_f3_resp_1_valid (f3_resps_4_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_4_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_4_1_bits_u), .io_f3_resp_2_valid (f3_resps_4_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_4_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_4_2_bits_u), .io_f3_resp_3_valid (f3_resps_4_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_4_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_4_3_bits_u), .io_update_mask_0 (tt_4_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_4_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_4_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_4_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_4_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_4_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_4_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_4_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_4_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_4_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_4_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_4_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_4_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_4_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_4_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_4_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_4_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_4_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_4_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_4_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_4_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_4_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_4_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_4_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_4_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_4_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_23 tt_5_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_5), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_5), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_5_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_5_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_5_0_bits_u), .io_f3_resp_1_valid (f3_resps_5_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_5_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_5_1_bits_u), .io_f3_resp_2_valid (f3_resps_5_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_5_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_5_2_bits_u), .io_f3_resp_3_valid (f3_resps_5_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_5_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_5_3_bits_u), .io_update_mask_0 (tt_5_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_5_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_5_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_5_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_5_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_5_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_5_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_5_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_5_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_5_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_5_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_5_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_5_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_5_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_5_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_5_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_5_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_5_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_5_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_5_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_5_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_5_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_5_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_5_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_5_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_5_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] MaxPeriodFibonacciLFSR_21 alloc_lfsr_prng ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_io_out_0), .io_out_1 (_alloc_lfsr_prng_io_out_1), .io_out_2 (_alloc_lfsr_prng_io_out_2), .io_out_3 (_alloc_lfsr_prng_io_out_3), .io_out_4 (_alloc_lfsr_prng_io_out_4), .io_out_5 (_alloc_lfsr_prng_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_22 alloc_lfsr_prng_1 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_1_io_out_0), .io_out_1 (_alloc_lfsr_prng_1_io_out_1), .io_out_2 (_alloc_lfsr_prng_1_io_out_2), .io_out_3 (_alloc_lfsr_prng_1_io_out_3), .io_out_4 (_alloc_lfsr_prng_1_io_out_4), .io_out_5 (_alloc_lfsr_prng_1_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_23 alloc_lfsr_prng_2 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_2_io_out_0), .io_out_1 (_alloc_lfsr_prng_2_io_out_1), .io_out_2 (_alloc_lfsr_prng_2_io_out_2), .io_out_3 (_alloc_lfsr_prng_2_io_out_3), .io_out_4 (_alloc_lfsr_prng_2_io_out_4), .io_out_5 (_alloc_lfsr_prng_2_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_24 alloc_lfsr_prng_3 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_3_io_out_0), .io_out_1 (_alloc_lfsr_prng_3_io_out_1), .io_out_2 (_alloc_lfsr_prng_3_io_out_2), .io_out_3 (_alloc_lfsr_prng_3_io_out_3), .io_out_4 (_alloc_lfsr_prng_3_io_out_4), .io_out_5 (_alloc_lfsr_prng_3_io_out_5) ); // @[PRNG.scala:91:22] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_f3_meta = io_f3_meta_0; // @[tage.scala:198:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache : input clock : Clock input reset : Reset output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} inst ctrls of InclusiveCacheControl connect ctrls.clock, clock connect ctrls.reset, reset wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_37 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler connect inclusive_cache_bank_sched.clock, clock connect inclusive_cache_bank_sched.reset, reset connect inclusive_cache_bank_sched.io.in, nodeIn connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready connect inclusive_cache_bank_sched.io.out.d, nodeOut.d connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready connect inclusive_cache_bank_sched.io.out.b, nodeOut.b connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready invalidate inclusive_cache_bank_sched.io.ways[0] invalidate inclusive_cache_bank_sched.io.ways[1] invalidate inclusive_cache_bank_sched.io.ways[2] invalidate inclusive_cache_bank_sched.io.ways[3] invalidate inclusive_cache_bank_sched.io.ways[4] invalidate inclusive_cache_bank_sched.io.ways[5] invalidate inclusive_cache_bank_sched.io.ways[6] invalidate inclusive_cache_bank_sched.io.ways[7] invalidate inclusive_cache_bank_sched.io.ways[8] invalidate inclusive_cache_bank_sched.io.divs[0] invalidate inclusive_cache_bank_sched.io.divs[1] invalidate inclusive_cache_bank_sched.io.divs[2] invalidate inclusive_cache_bank_sched.io.divs[3] invalidate inclusive_cache_bank_sched.io.divs[4] invalidate inclusive_cache_bank_sched.io.divs[5] invalidate inclusive_cache_bank_sched.io.divs[6] invalidate inclusive_cache_bank_sched.io.divs[7] invalidate inclusive_cache_bank_sched.io.divs[8] connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T) node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2) node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T) node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2) node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T) node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2) node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T connect ctrls.io.flush_req.ready, UInt<1>(0h0) connect ctrls.io.flush_resp, UInt<1>(0h0) connect ctrls.io.flush_match, UInt<1>(0h0) node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000)) node _contained_T_1 = cvt(_contained_T) node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h10000000))) node _contained_T_3 = asSInt(_contained_T_2) node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0))) node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000)) node _contained_T_6 = cvt(_contained_T_5) node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h10000))) node _contained_T_8 = asSInt(_contained_T_7) node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0))) node contained = or(_contained_T_4, _contained_T_9) when contained : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits node _T = and(contained, inclusive_cache_bank_sched.io.req.ready) when _T : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1)	module InclusiveCache( // @[InclusiveCache.scala:108:9] input clock, // @[InclusiveCache.scala:108:9] input reset, // @[InclusiveCache.scala:108:9] output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43] wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43] wire auto_ctrls_ctrl_in_a_valid_0 = auto_ctrls_ctrl_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_opcode_0 = auto_ctrls_ctrl_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_param_0 = auto_ctrls_ctrl_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_a_bits_size_0 = auto_ctrls_ctrl_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [12:0] auto_ctrls_ctrl_in_a_bits_source_0 = auto_ctrls_ctrl_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [25:0] auto_ctrls_ctrl_in_a_bits_address_0 = auto_ctrls_ctrl_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [7:0] auto_ctrls_ctrl_in_a_bits_mask_0 = auto_ctrls_ctrl_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_a_bits_data_0 = auto_ctrls_ctrl_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_a_bits_corrupt_0 = auto_ctrls_ctrl_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_ready_0 = auto_ctrls_ctrl_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[InclusiveCache.scala:108:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[InclusiveCache.scala:108:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[InclusiveCache.scala:108:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[InclusiveCache.scala:108:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[InclusiveCache.scala:108:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[InclusiveCache.scala:108:9] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [63:0] auto_out_b_bits_data = 64'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [7:0] auto_out_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [7:0] nodeOut_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] auto_out_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] nodeOut_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [3:0] auto_out_b_bits_source = 4'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [3:0] nodeOut_b_bits_source = 4'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_b_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_b_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_a_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_b_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_c_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire [127:0] auto_in_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeIn_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [15:0] auto_in_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeIn_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_source = 8'hA0; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_source = 8'hA0; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_valid = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_valid = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_ctrls_ctrl_in_d_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] auto_out_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] nodeOut_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[InclusiveCache.scala:108:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [12:0] auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] wire auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [7:0] auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] wire auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_a_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeIn_b_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_1 = {1'h0, _nodeIn_b_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeIn_b_bits_address = _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeOut_c_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_c_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_c_bits_address = _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] wire [63:0] _contained_T = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_1 = {1'h0, _contained_T}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_2 = _contained_T_1 & 65'h1FFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_3 = _contained_T_2; // @[Parameters.scala:137:46] wire _contained_T_4 = _contained_T_3 == 65'h0; // @[Parameters.scala:137:{46,59}] wire [63:0] _contained_T_5 = {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_6 = {1'h0, _contained_T_5}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_7 = _contained_T_6 & 65'h1FFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_8 = _contained_T_7; // @[Parameters.scala:137:46] wire _contained_T_9 = _contained_T_8 == 65'h0; // @[Parameters.scala:137:{46,59}] wire contained = _contained_T_4 \| _contained_T_9; // @[Parameters.scala:137:59] wire _inclusive_cache_bank_sched_io_req_valid_T = contained & _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43, :169:67, :172:41] InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready_0), .auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid_0), .auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size_0), .auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source_0), .auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data_0), .io_flush_match (contained), // @[InclusiveCache.scala:169:67] .io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25] .io_flush_req_valid (_ctrls_io_flush_req_valid), .io_flush_req_bits (_ctrls_io_flush_req_bits), .io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29] ); // @[InclusiveCache.scala:103:43] TLMonitor_37 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), .io_in_b_bits_param (nodeIn_b_bits_param), .io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), .io_in_c_ready (nodeIn_c_ready), .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), .io_in_d_bits_opcode (nodeIn_d_bits_opcode), .io_in_d_bits_param (nodeIn_d_bits_param), .io_in_d_bits_size (nodeIn_d_bits_size), .io_in_d_bits_source (nodeIn_d_bits_source), .io_in_d_bits_sink (nodeIn_d_bits_sink), .io_in_d_bits_denied (nodeIn_d_bits_denied), .io_in_d_bits_data (nodeIn_d_bits_data), .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_out_a_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_out_a_valid (nodeOut_a_valid), .io_out_a_bits_opcode (nodeOut_a_bits_opcode), .io_out_a_bits_param (nodeOut_a_bits_param), .io_out_a_bits_size (nodeOut_a_bits_size), .io_out_a_bits_source (nodeOut_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_io_out_a_bits_address), .io_out_a_bits_mask (nodeOut_a_bits_mask), .io_out_a_bits_data (nodeOut_a_bits_data), .io_out_a_bits_corrupt (nodeOut_a_bits_corrupt), .io_out_c_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_out_c_valid (nodeOut_c_valid), .io_out_c_bits_opcode (nodeOut_c_bits_opcode), .io_out_c_bits_param (nodeOut_c_bits_param), .io_out_c_bits_size (nodeOut_c_bits_size), .io_out_c_bits_source (nodeOut_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_io_out_c_bits_address), .io_out_c_bits_data (nodeOut_c_bits_data), .io_out_c_bits_corrupt (nodeOut_c_bits_corrupt), .io_out_d_ready (nodeOut_d_ready), .io_out_d_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_out_d_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_out_d_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_out_d_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_out_d_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_out_d_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_out_d_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_out_d_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_out_d_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_out_e_valid (nodeOut_e_valid), .io_out_e_bits_sink (nodeOut_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_io_req_ready), .io_req_valid (_inclusive_cache_bank_sched_io_req_valid_T), // @[InclusiveCache.scala:172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid) ); // @[InclusiveCache.scala:137:29] assign _nodeOut_a_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_a_bits_address_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:248:14] assign _nodeIn_b_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:137:31] assign _nodeIn_b_bits_address_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:248:14] assign _nodeOut_c_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_c_bits_address_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:248:14] assign auto_ctrls_ctrl_in_a_ready = auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_valid = auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_opcode = auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_size = auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_source = auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_data = auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = or(_T_144, _T_149) node _T_151 = and(_T_139, _T_150) node _T_152 = or(UInt<1>(0h0), _T_151) node _T_153 = and(_T_138, _T_152) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_153, UInt<1>(0h1), "") : assert_2 node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = or(_T_165, _T_170) node _T_172 = and(_T_160, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = and(UInt<1>(0h0), _T_173) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_174, UInt<1>(0h1), "") : assert_3 node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(source_ok, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_181 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_181, UInt<1>(0h1), "") : assert_5 node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(is_aligned, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_188 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_188, UInt<1>(0h1), "") : assert_7 node _T_192 = not(io.in.a.bits.mask) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_193, UInt<1>(0h1), "") : assert_8 node _T_197 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_197, UInt<1>(0h1), "") : assert_9 node _T_201 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_201 : node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_8) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<1>(0h1)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_9) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_218 = shr(io.in.a.bits.source, 2) node _T_219 = eq(_T_218, UInt<2>(0h2)) node _T_220 = leq(UInt<1>(0h0), uncommonBits_10) node _T_221 = and(_T_219, _T_220) node _T_222 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<2>(0h3)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_11) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_233 = or(_T_205, _T_211) node _T_234 = or(_T_233, _T_217) node _T_235 = or(_T_234, _T_223) node _T_236 = or(_T_235, _T_229) node _T_237 = or(_T_236, _T_230) node _T_238 = or(_T_237, _T_231) node _T_239 = or(_T_238, _T_232) node _T_240 = and(_T_204, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_243 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_249 = cvt(_T_248) node _T_250 = and(_T_249, asSInt(UInt<13>(0h1000))) node _T_251 = asSInt(_T_250) node _T_252 = eq(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = or(_T_247, _T_252) node _T_254 = and(_T_242, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = and(_T_241, _T_255) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_256, UInt<1>(0h1), "") : assert_10 node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _T_263 = or(UInt<1>(0h0), _T_262) node _T_264 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<13>(0h1000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = or(_T_268, _T_273) node _T_275 = and(_T_263, _T_274) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = and(UInt<1>(0h0), _T_276) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_277, UInt<1>(0h1), "") : assert_11 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(source_ok, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_284 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_284, UInt<1>(0h1), "") : assert_13 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(is_aligned, UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_291 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(_T_291, UInt<1>(0h0)) when _T_294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_291, UInt<1>(0h1), "") : assert_15 node _T_295 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_295, UInt<1>(0h1), "") : assert_16 node _T_299 = not(io.in.a.bits.mask) node _T_300 = eq(_T_299, UInt<1>(0h0)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_300, UInt<1>(0h1), "") : assert_17 node _T_304 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_T_304, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_304, UInt<1>(0h1), "") : assert_18 node _T_308 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_308 : node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<1>(0h0)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_12) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h1)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_13) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<2>(0h2)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_14) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h3)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_15) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_339 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_340 = or(_T_312, _T_318) node _T_341 = or(_T_340, _T_324) node _T_342 = or(_T_341, _T_330) node _T_343 = or(_T_342, _T_336) node _T_344 = or(_T_343, _T_337) node _T_345 = or(_T_344, _T_338) node _T_346 = or(_T_345, _T_339) node _T_347 = and(_T_311, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_348, UInt<1>(0h1), "") : assert_19 node _T_352 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_353 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_354 = and(_T_352, _T_353) node _T_355 = or(UInt<1>(0h0), _T_354) node _T_356 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_357 = cvt(_T_356) node _T_358 = and(_T_357, asSInt(UInt<13>(0h1000))) node _T_359 = asSInt(_T_358) node _T_360 = eq(_T_359, asSInt(UInt<1>(0h0))) node _T_361 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<13>(0h1000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = or(_T_360, _T_365) node _T_367 = and(_T_355, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_16) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_17) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_18) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_19) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_422 = or(_T_394, _T_400) node _T_423 = or(_T_422, _T_406) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_424, _T_418) node _T_426 = or(_T_425, _T_419) node _T_427 = or(_T_426, _T_420) node _T_428 = or(_T_427, _T_421) node _T_429 = and(_T_393, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_433 = and(_T_431, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<13>(0h1000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = or(_T_439, _T_444) node _T_446 = and(_T_434, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_T_430, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_448, UInt<1>(0h1), "") : assert_26 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(is_aligned, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_458 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_458, UInt<1>(0h1), "") : assert_29 node _T_462 = eq(io.in.a.bits.mask, mask) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_462, UInt<1>(0h1), "") : assert_30 node _T_466 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_466 : node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_471 = shr(io.in.a.bits.source, 2) node _T_472 = eq(_T_471, UInt<1>(0h0)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_20) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_476 = and(_T_474, _T_475) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_477 = shr(io.in.a.bits.source, 2) node _T_478 = eq(_T_477, UInt<1>(0h1)) node _T_479 = leq(UInt<1>(0h0), uncommonBits_21) node _T_480 = and(_T_478, _T_479) node _T_481 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_482 = and(_T_480, _T_481) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_483 = shr(io.in.a.bits.source, 2) node _T_484 = eq(_T_483, UInt<2>(0h2)) node _T_485 = leq(UInt<1>(0h0), uncommonBits_22) node _T_486 = and(_T_484, _T_485) node _T_487 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_489 = shr(io.in.a.bits.source, 2) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_23) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_497 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_498 = or(_T_470, _T_476) node _T_499 = or(_T_498, _T_482) node _T_500 = or(_T_499, _T_488) node _T_501 = or(_T_500, _T_494) node _T_502 = or(_T_501, _T_495) node _T_503 = or(_T_502, _T_496) node _T_504 = or(_T_503, _T_497) node _T_505 = and(_T_469, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_508 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_509 = and(_T_507, _T_508) node _T_510 = or(UInt<1>(0h0), _T_509) node _T_511 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = or(_T_515, _T_520) node _T_522 = and(_T_510, _T_521) node _T_523 = or(UInt<1>(0h0), _T_522) node _T_524 = and(_T_506, _T_523) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_524, UInt<1>(0h1), "") : assert_31 node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(source_ok, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(is_aligned, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_534 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_534, UInt<1>(0h1), "") : assert_34 node _T_538 = not(mask) node _T_539 = and(io.in.a.bits.mask, _T_538) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_540, UInt<1>(0h1), "") : assert_35 node _T_544 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_549 = shr(io.in.a.bits.source, 2) node _T_550 = eq(_T_549, UInt<1>(0h0)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_24) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_554 = and(_T_552, _T_553) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_555 = shr(io.in.a.bits.source, 2) node _T_556 = eq(_T_555, UInt<1>(0h1)) node _T_557 = leq(UInt<1>(0h0), uncommonBits_25) node _T_558 = and(_T_556, _T_557) node _T_559 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_560 = and(_T_558, _T_559) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_561 = shr(io.in.a.bits.source, 2) node _T_562 = eq(_T_561, UInt<2>(0h2)) node _T_563 = leq(UInt<1>(0h0), uncommonBits_26) node _T_564 = and(_T_562, _T_563) node _T_565 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_566 = and(_T_564, _T_565) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_567 = shr(io.in.a.bits.source, 2) node _T_568 = eq(_T_567, UInt<2>(0h3)) node _T_569 = leq(UInt<1>(0h0), uncommonBits_27) node _T_570 = and(_T_568, _T_569) node _T_571 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_576 = or(_T_548, _T_554) node _T_577 = or(_T_576, _T_560) node _T_578 = or(_T_577, _T_566) node _T_579 = or(_T_578, _T_572) node _T_580 = or(_T_579, _T_573) node _T_581 = or(_T_580, _T_574) node _T_582 = or(_T_581, _T_575) node _T_583 = and(_T_547, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_586 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = or(UInt<1>(0h0), _T_587) node _T_589 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = or(_T_593, _T_598) node _T_600 = and(_T_588, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = and(_T_584, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_602, UInt<1>(0h1), "") : assert_36 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_612 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_612, UInt<1>(0h1), "") : assert_39 node _T_616 = eq(io.in.a.bits.mask, mask) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_616, UInt<1>(0h1), "") : assert_40 node _T_620 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_620 : node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_625 = shr(io.in.a.bits.source, 2) node _T_626 = eq(_T_625, UInt<1>(0h0)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_28) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h1)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_29) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<2>(0h2)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_30) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h3)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_31) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_652 = or(_T_624, _T_630) node _T_653 = or(_T_652, _T_636) node _T_654 = or(_T_653, _T_642) node _T_655 = or(_T_654, _T_648) node _T_656 = or(_T_655, _T_649) node _T_657 = or(_T_656, _T_650) node _T_658 = or(_T_657, _T_651) node _T_659 = and(_T_623, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<13>(0h1000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = or(_T_669, _T_674) node _T_676 = and(_T_664, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = and(_T_660, _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_678, UInt<1>(0h1), "") : assert_41 node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(source_ok, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(is_aligned, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_688 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_688, UInt<1>(0h1), "") : assert_44 node _T_692 = eq(io.in.a.bits.mask, mask) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_692, UInt<1>(0h1), "") : assert_45 node _T_696 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_696 : node _T_697 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_698 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<1>(0h0)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_32) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<1>(0h1)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_33) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_713 = shr(io.in.a.bits.source, 2) node _T_714 = eq(_T_713, UInt<2>(0h2)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_34) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<2>(0h3)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_35) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_700, _T_706) node _T_729 = or(_T_728, _T_712) node _T_730 = or(_T_729, _T_718) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = or(_T_732, _T_726) node _T_734 = or(_T_733, _T_727) node _T_735 = and(_T_699, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_738 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<13>(0h1000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = or(_T_742, _T_747) node _T_749 = and(_T_737, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = and(_T_736, _T_750) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_751, UInt<1>(0h1), "") : assert_46 node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(source_ok, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(is_aligned, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_761 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_761, UInt<1>(0h1), "") : assert_49 node _T_765 = eq(io.in.a.bits.mask, mask) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_765, UInt<1>(0h1), "") : assert_50 node _T_769 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_769, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_773 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_773, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_777 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_777 : node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(source_ok_1, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_781 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_781, UInt<1>(0h1), "") : assert_54 node _T_785 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_785, UInt<1>(0h1), "") : assert_55 node _T_789 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_789, UInt<1>(0h1), "") : assert_56 node _T_793 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_793, UInt<1>(0h1), "") : assert_57 node _T_797 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_797 : node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(source_ok_1, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(sink_ok, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_804 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_804, UInt<1>(0h1), "") : assert_60 node _T_808 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_809 = asUInt(reset) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(_T_808, UInt<1>(0h0)) when _T_811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_808, UInt<1>(0h1), "") : assert_61 node _T_812 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(_T_812, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_812, UInt<1>(0h1), "") : assert_62 node _T_816 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_816, UInt<1>(0h1), "") : assert_63 node _T_820 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_821 = or(UInt<1>(0h0), _T_820) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_821, UInt<1>(0h1), "") : assert_64 node _T_825 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_825 : node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(source_ok_1, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(sink_ok, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_832 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_832, UInt<1>(0h1), "") : assert_67 node _T_836 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_836, UInt<1>(0h1), "") : assert_68 node _T_840 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_840, UInt<1>(0h1), "") : assert_69 node _T_844 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_845 = or(_T_844, io.in.d.bits.corrupt) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_845, UInt<1>(0h1), "") : assert_70 node _T_849 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_850, UInt<1>(0h1), "") : assert_71 node _T_854 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_854 : node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok_1, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_858 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_858, UInt<1>(0h1), "") : assert_73 node _T_862 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_862, UInt<1>(0h1), "") : assert_74 node _T_866 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_867, UInt<1>(0h1), "") : assert_75 node _T_871 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_871 : node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok_1, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_875 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_875, UInt<1>(0h1), "") : assert_77 node _T_879 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_880 = or(_T_879, io.in.d.bits.corrupt) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_880, UInt<1>(0h1), "") : assert_78 node _T_884 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_885, UInt<1>(0h1), "") : assert_79 node _T_889 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_889 : node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(source_ok_1, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_893, UInt<1>(0h1), "") : assert_81 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_897, UInt<1>(0h1), "") : assert_82 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_902, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_906 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_906, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_910 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_910, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_914 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_914, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_918 = eq(a_first, UInt<1>(0h0)) node _T_919 = and(io.in.a.valid, _T_918) when _T_919 : node _T_920 = eq(io.in.a.bits.opcode, opcode) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_920, UInt<1>(0h1), "") : assert_87 node _T_924 = eq(io.in.a.bits.param, param) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_924, UInt<1>(0h1), "") : assert_88 node _T_928 = eq(io.in.a.bits.size, size) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_928, UInt<1>(0h1), "") : assert_89 node _T_932 = eq(io.in.a.bits.source, source) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_932, UInt<1>(0h1), "") : assert_90 node _T_936 = eq(io.in.a.bits.address, address) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_936, UInt<1>(0h1), "") : assert_91 node _T_940 = and(io.in.a.ready, io.in.a.valid) node _T_941 = and(_T_940, a_first) when _T_941 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_942 = eq(d_first, UInt<1>(0h0)) node _T_943 = and(io.in.d.valid, _T_942) when _T_943 : node _T_944 = eq(io.in.d.bits.opcode, opcode_1) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_944, UInt<1>(0h1), "") : assert_92 node _T_948 = eq(io.in.d.bits.param, param_1) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_948, UInt<1>(0h1), "") : assert_93 node _T_952 = eq(io.in.d.bits.size, size_1) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_952, UInt<1>(0h1), "") : assert_94 node _T_956 = eq(io.in.d.bits.source, source_1) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_956, UInt<1>(0h1), "") : assert_95 node _T_960 = eq(io.in.d.bits.sink, sink) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_960, UInt<1>(0h1), "") : assert_96 node _T_964 = eq(io.in.d.bits.denied, denied) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_964, UInt<1>(0h1), "") : assert_97 node _T_968 = and(io.in.d.ready, io.in.d.valid) node _T_969 = and(_T_968, d_first) when _T_969 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_970 = and(io.in.a.valid, a_first_1) node _T_971 = and(_T_970, UInt<1>(0h1)) when _T_971 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_972 = and(io.in.a.ready, io.in.a.valid) node _T_973 = and(_T_972, a_first_1) node _T_974 = and(_T_973, UInt<1>(0h1)) when _T_974 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_975 = dshr(inflight, io.in.a.bits.source) node _T_976 = bits(_T_975, 0, 0) node _T_977 = eq(_T_976, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_977, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_981 = and(io.in.d.valid, d_first_1) node _T_982 = and(_T_981, UInt<1>(0h1)) node _T_983 = eq(d_release_ack, UInt<1>(0h0)) node _T_984 = and(_T_982, _T_983) when _T_984 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_985 = and(io.in.d.ready, io.in.d.valid) node _T_986 = and(_T_985, d_first_1) node _T_987 = and(_T_986, UInt<1>(0h1)) node _T_988 = eq(d_release_ack, UInt<1>(0h0)) node _T_989 = and(_T_987, _T_988) when _T_989 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_990 = and(io.in.d.valid, d_first_1) node _T_991 = and(_T_990, UInt<1>(0h1)) node _T_992 = eq(d_release_ack, UInt<1>(0h0)) node _T_993 = and(_T_991, _T_992) when _T_993 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_994 = dshr(inflight, io.in.d.bits.source) node _T_995 = bits(_T_994, 0, 0) node _T_996 = or(_T_995, same_cycle_resp) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_996, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1000 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1001 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1002 = or(_T_1000, _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_100 node _T_1006 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_101 else : node _T_1010 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1011 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1012 = or(_T_1010, _T_1011) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_102 node _T_1016 = eq(io.in.d.bits.size, a_size_lookup) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_103 node _T_1020 = and(io.in.d.valid, d_first_1) node _T_1021 = and(_T_1020, a_first_1) node _T_1022 = and(_T_1021, io.in.a.valid) node _T_1023 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1024 = and(_T_1022, _T_1023) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.a.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_104 node _T_1032 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1033 = orr(a_set_wo_ready) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) node _T_1035 = or(_T_1032, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_8 node _T_1039 = orr(inflight) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1042 = or(_T_1040, _T_1041) node _T_1043 = lt(watchdog, plusarg_reader.out) node _T_1044 = or(_T_1042, _T_1043) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(io.in.d.ready, io.in.d.valid) node _T_1050 = or(_T_1048, _T_1049) when _T_1050 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1051 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1052 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1053 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = and(_T_1051, _T_1054) when _T_1055 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1056 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1057 = and(_T_1056, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1058 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1059 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = and(_T_1057, _T_1060) when _T_1061 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1062 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1063 = bits(_T_1062, 0, 0) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1068 = and(io.in.d.valid, d_first_2) node _T_1069 = and(_T_1068, UInt<1>(0h1)) node _T_1070 = and(_T_1069, d_release_ack_1) when _T_1070 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1071 = and(io.in.d.ready, io.in.d.valid) node _T_1072 = and(_T_1071, d_first_2) node _T_1073 = and(_T_1072, UInt<1>(0h1)) node _T_1074 = and(_T_1073, d_release_ack_1) when _T_1074 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1075 = and(io.in.d.valid, d_first_2) node _T_1076 = and(_T_1075, UInt<1>(0h1)) node _T_1077 = and(_T_1076, d_release_ack_1) when _T_1077 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1078 = dshr(inflight_1, io.in.d.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = or(_T_1079, same_cycle_resp_1) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1084 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_109 else : node _T_1088 = eq(io.in.d.bits.size, c_size_lookup) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_110 node _T_1092 = and(io.in.d.valid, d_first_2) node _T_1093 = and(_T_1092, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1094 = and(_T_1093, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1095 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = and(_T_1096, d_release_ack_1) node _T_1098 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1099 = and(_T_1097, _T_1098) when _T_1099 : node _T_1100 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1101 = or(_T_1100, _WIRE_23.ready) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_111 node _T_1105 = orr(c_set_wo_ready) when _T_1105 : node _T_1106 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_9 node _T_1110 = orr(inflight_1) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1113 = or(_T_1111, _T_1112) node _T_1114 = lt(watchdog_1, plusarg_reader_1.out) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1119 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1120 = and(io.in.d.ready, io.in.d.valid) node _T_1121 = or(_T_1119, _T_1120) when _T_1121 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1048 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1048; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1048; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1121 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1121; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_974 = _T_1048 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_974 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_974 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_974 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_974 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_974 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1020 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1020 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_989 = _T_1121 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_989 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_989 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_989 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1092 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1092 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1074 = _T_1121 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1074 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1074 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1074 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_175 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_175( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ITLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_28 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s2 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_2 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_29 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_30 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_31 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_32 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_33 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_34 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_35 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_36 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_37 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_38 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_39 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_40 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_41 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gf_inst_array, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)	module ITLB( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output io_ptw_req_bits_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_kill // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_cacheable; // @[TLB.scala:422:19] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] reg [1:0] waddr; // @[TLB.scala:355:34] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_need_gpa; // @[TLB.scala:361:23] wire _vm_enabled_T_1 = io_ptw_ptbr_mode[3] & ~(io_req_bits_prv[1]); // @[TLB.scala:372:27, :374:41, :399:45] wire io_ptw_req_valid_0 = state == 2'h1; // @[package.scala:16:47] wire ignore_13 = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire [27:0] mpu_ppn = io_ptw_resp_valid ? {8'h0, io_ptw_resp_bits_pte_ppn[19:0]} : _vm_enabled_T_1 ? {8'h0, _mpu_ppn_barrier_io_y_ppn[19:18], (ignore_13 ? io_req_bits_vaddr[29:21] : 9'h0) \| _mpu_ppn_barrier_io_y_ppn[17:9], (special_entry_level[1] ? 9'h0 : io_req_bits_vaddr[20:12]) \| _mpu_ppn_barrier_io_y_ppn[8:0]} : io_req_bits_vaddr[39:12]; // @[package.scala:267:25] wire [2:0] mpu_priv = io_ptw_resp_valid ? 3'h1 : {io_ptw_status_debug, io_req_bits_prv}; // @[TLB.scala:415:{27,103}] wire deny_access_to_debug = ~(mpu_priv[2]) & mpu_ppn == 28'h0; // @[TLB.scala:412:20, :415:27, :428:{39,50}] wire prot_x = _pma_io_resp_x & ~deny_access_to_debug & _pmp_io_x; // @[TLB.scala:416:19, :422:19, :428:50, :429:33, :434:{30,55}] wire [24:0] _hitsVec_T = sectored_entries_0_0_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_6 = sectored_entries_0_1_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_12 = sectored_entries_0_2_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_18 = sectored_entries_0_3_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_24 = sectored_entries_0_4_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_30 = sectored_entries_0_5_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_36 = sectored_entries_0_6_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_42 = sectored_entries_0_7_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [17:0] _hitsVec_T_58 = superpage_entries_0_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_1 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_73 = superpage_entries_1_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_4 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_88 = superpage_entries_2_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_7 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_103 = superpage_entries_3_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_10 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [3:0] _GEN = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_0 = _vm_enabled_T_1 & _GEN[io_req_bits_vaddr[13:12]] & _hitsVec_T == 25'h0 & ~sectored_entries_0_0_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_0 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_1 = _vm_enabled_T_1 & _GEN_0[io_req_bits_vaddr[13:12]] & _hitsVec_T_6 == 25'h0 & ~sectored_entries_0_1_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_1 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_2 = _vm_enabled_T_1 & _GEN_1[io_req_bits_vaddr[13:12]] & _hitsVec_T_12 == 25'h0 & ~sectored_entries_0_2_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_2 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_3 = _vm_enabled_T_1 & _GEN_2[io_req_bits_vaddr[13:12]] & _hitsVec_T_18 == 25'h0 & ~sectored_entries_0_3_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_3 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_4 = _vm_enabled_T_1 & _GEN_3[io_req_bits_vaddr[13:12]] & _hitsVec_T_24 == 25'h0 & ~sectored_entries_0_4_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_4 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_5 = _vm_enabled_T_1 & _GEN_4[io_req_bits_vaddr[13:12]] & _hitsVec_T_30 == 25'h0 & ~sectored_entries_0_5_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_5 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_6 = _vm_enabled_T_1 & _GEN_5[io_req_bits_vaddr[13:12]] & _hitsVec_T_36 == 25'h0 & ~sectored_entries_0_6_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_6 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_7 = _vm_enabled_T_1 & _GEN_6[io_req_bits_vaddr[13:12]] & _hitsVec_T_42 == 25'h0 & ~sectored_entries_0_7_tag_v; // @[package.scala:163:13] wire hitsVec_8 = _vm_enabled_T_1 & superpage_entries_0_valid_0 & ~superpage_entries_0_tag_v & _hitsVec_T_58[17:9] == 9'h0 & (ignore_1 \| _hitsVec_T_58[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_9 = _vm_enabled_T_1 & superpage_entries_1_valid_0 & ~superpage_entries_1_tag_v & _hitsVec_T_73[17:9] == 9'h0 & (ignore_4 \| _hitsVec_T_73[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_10 = _vm_enabled_T_1 & superpage_entries_2_valid_0 & ~superpage_entries_2_tag_v & _hitsVec_T_88[17:9] == 9'h0 & (ignore_7 \| _hitsVec_T_88[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_11 = _vm_enabled_T_1 & superpage_entries_3_valid_0 & ~superpage_entries_3_tag_v & _hitsVec_T_103[17:9] == 9'h0 & (ignore_10 \| _hitsVec_T_103[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire [26:0] _hitsVec_T_118 = special_entry_tag_vpn ^ io_req_bits_vaddr[38:12]; // @[TLB.scala:183:52, :335:30, :346:56] wire hitsVec_12 = _vm_enabled_T_1 & special_entry_valid_0 & _hitsVec_T_118[26:18] == 9'h0 & (ignore_13 \| _hitsVec_T_118[17:9] == 9'h0) & (~(special_entry_level[1]) \| _hitsVec_T_118[8:0] == 9'h0); // @[TLB.scala:183:{29,40,52,58,79}, :197:28, :346:56, :399:45, :440:44] wire [12:0] real_hits = {hitsVec_12, hitsVec_11, hitsVec_10, hitsVec_9, hitsVec_8, hitsVec_7, hitsVec_6, hitsVec_5, hitsVec_4, hitsVec_3, hitsVec_2, hitsVec_1, hitsVec_0}; // @[package.scala:45:27] wire [13:0] hits = {~_vm_enabled_T_1, hitsVec_12, hitsVec_11, hitsVec_10, hitsVec_9, hitsVec_8, hitsVec_7, hitsVec_6, hitsVec_5, hitsVec_4, hitsVec_3, hitsVec_2, hitsVec_1, hitsVec_0}; // @[TLB.scala:174:95, :178:33, :183:29, :188:18, :399:45, :440:44, :442:{17,18}] wire [3:0][41:0] _GEN_7 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_7[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_8 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_8[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_9 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_9[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_10 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_10[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_11 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_11[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_12 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_12[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_13 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_13[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_14 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_14[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire bad_va = _vm_enabled_T_1 & ~(io_req_bits_vaddr[39:38] == 2'h0 \| (&(io_req_bits_vaddr[39:38]))); // @[TLB.scala:320:14, :399:45, :559:43, :560:{37,51,59,86}, :568:34] wire tlb_miss = _vm_enabled_T_1 & ~bad_va & real_hits == 13'h0; // @[package.scala:45:27] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire multipleHits_rightOne_1 = hitsVec_1 \| hitsVec_2; // @[Misc.scala:183:16] wire multipleHits_leftOne_2 = hitsVec_0 \| multipleHits_rightOne_1; // @[Misc.scala:183:16] wire multipleHits_rightOne_3 = hitsVec_4 \| hitsVec_5; // @[Misc.scala:183:16] wire multipleHits_rightOne_4 = hitsVec_3 \| multipleHits_rightOne_3; // @[Misc.scala:183:16] wire multipleHits_rightOne_6 = hitsVec_7 \| hitsVec_8; // @[Misc.scala:183:16] wire multipleHits_leftOne_8 = hitsVec_6 \| multipleHits_rightOne_6; // @[Misc.scala:183:16] wire multipleHits_leftOne_10 = hitsVec_9 \| hitsVec_10; // @[Misc.scala:183:16] wire multipleHits_rightOne_9 = hitsVec_11 \| hitsVec_12; // @[Misc.scala:183:16] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 \| multipleHits_rightOne_9; // @[Misc.scala:183:16] wire multipleHits = hitsVec_1 & hitsVec_2 \| hitsVec_0 & multipleHits_rightOne_1 \| hitsVec_4 & hitsVec_5 \| hitsVec_3 & multipleHits_rightOne_3 \| multipleHits_leftOne_2 & multipleHits_rightOne_4 \| hitsVec_7 & hitsVec_8 \| hitsVec_6 & multipleHits_rightOne_6 \| hitsVec_9 & hitsVec_10 \| hitsVec_11 & hitsVec_12 \| multipleHits_leftOne_10 & multipleHits_rightOne_9 \| multipleHits_leftOne_8 & multipleHits_rightOne_10 \| (multipleHits_leftOne_2 \| multipleHits_rightOne_4) & (multipleHits_leftOne_8 \| multipleHits_rightOne_10); // @[Misc.scala:183:{16,37,49,61}]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_4 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_4( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - 12'h2B; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_116 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_137 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_116( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_137 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 : input clock : Clock input reset : Reset output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clientNodeOut.d.bits.corrupt invalidate clientNodeOut.d.bits.data invalidate clientNodeOut.d.bits.denied invalidate clientNodeOut.d.bits.sink invalidate clientNodeOut.d.bits.source invalidate clientNodeOut.d.bits.size invalidate clientNodeOut.d.bits.param invalidate clientNodeOut.d.bits.opcode invalidate clientNodeOut.d.valid invalidate clientNodeOut.d.ready invalidate clientNodeOut.a.bits.corrupt invalidate clientNodeOut.a.bits.data invalidate clientNodeOut.a.bits.mask invalidate clientNodeOut.a.bits.address invalidate clientNodeOut.a.bits.source invalidate clientNodeOut.a.bits.size invalidate clientNodeOut.a.bits.param invalidate clientNodeOut.a.bits.opcode invalidate clientNodeOut.a.valid invalidate clientNodeOut.a.ready connect auto.client_out, clientNodeOut wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect manager_tl.e.bits.sink, UInt<8>(0h0) connect manager_tl.e.valid, UInt<1>(0h0) connect manager_tl.e.ready, UInt<1>(0h0) connect manager_tl.d.bits.corrupt, UInt<1>(0h0) connect manager_tl.d.bits.data, UInt<64>(0h0) connect manager_tl.d.bits.denied, UInt<1>(0h0) connect manager_tl.d.bits.sink, UInt<8>(0h0) connect manager_tl.d.bits.source, UInt<8>(0h0) connect manager_tl.d.bits.size, UInt<8>(0h0) connect manager_tl.d.bits.param, UInt<2>(0h0) connect manager_tl.d.bits.opcode, UInt<3>(0h0) connect manager_tl.d.valid, UInt<1>(0h0) connect manager_tl.d.ready, UInt<1>(0h0) connect manager_tl.c.bits.corrupt, UInt<1>(0h0) connect manager_tl.c.bits.data, UInt<64>(0h0) connect manager_tl.c.bits.address, UInt<64>(0h0) connect manager_tl.c.bits.source, UInt<8>(0h0) connect manager_tl.c.bits.size, UInt<8>(0h0) connect manager_tl.c.bits.param, UInt<3>(0h0) connect manager_tl.c.bits.opcode, UInt<3>(0h0) connect manager_tl.c.valid, UInt<1>(0h0) connect manager_tl.c.ready, UInt<1>(0h0) connect manager_tl.b.bits.corrupt, UInt<1>(0h0) connect manager_tl.b.bits.data, UInt<64>(0h0) connect manager_tl.b.bits.mask, UInt<8>(0h0) connect manager_tl.b.bits.address, UInt<64>(0h0) connect manager_tl.b.bits.source, UInt<8>(0h0) connect manager_tl.b.bits.size, UInt<8>(0h0) connect manager_tl.b.bits.param, UInt<2>(0h0) connect manager_tl.b.bits.opcode, UInt<3>(0h0) connect manager_tl.b.valid, UInt<1>(0h0) connect manager_tl.b.ready, UInt<1>(0h0) connect manager_tl.a.bits.corrupt, UInt<1>(0h0) connect manager_tl.a.bits.data, UInt<64>(0h0) connect manager_tl.a.bits.mask, UInt<8>(0h0) connect manager_tl.a.bits.address, UInt<64>(0h0) connect manager_tl.a.bits.source, UInt<8>(0h0) connect manager_tl.a.bits.size, UInt<8>(0h0) connect manager_tl.a.bits.param, UInt<3>(0h0) connect manager_tl.a.bits.opcode, UInt<3>(0h0) connect manager_tl.a.valid, UInt<1>(0h0) connect manager_tl.a.ready, UInt<1>(0h0) inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_1_2.clock, clock connect out_channels_1_2.reset, reset wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE.bits.data, UInt<64>(0h0) connect _out_channels_WIRE.bits.mask, UInt<8>(0h0) connect _out_channels_WIRE.bits.address, UInt<32>(0h0) connect _out_channels_WIRE.bits.source, UInt<4>(0h0) connect _out_channels_WIRE.bits.size, UInt<4>(0h0) connect _out_channels_WIRE.bits.param, UInt<2>(0h0) connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_3_1.bits, _out_channels_WIRE.bits connect out_channels_3_1.valid, _out_channels_WIRE.valid connect out_channels_3_1.ready, _out_channels_WIRE.ready inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_3_2.clock, clock connect out_channels_3_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_1_2.io.protocol, clientNodeOut.d inst ser_1 of GenericSerializer_TLBeatw67_f32 connect ser_1.clock, clock connect ser_1.reset, reset connect ser_1.io.in, out_channels_1_2.io.beat connect io.ser[1].out.bits, ser_1.io.out.bits connect io.ser[1].out.valid, ser_1.io.out.valid connect ser_1.io.out.ready, io.ser[1].out.ready connect out_channels_3_2.io.protocol, out_channels_3_1 inst ser_3 of GenericSerializer_TLBeatw87_f32 connect ser_3.clock, clock connect ser_3.reset, reset connect ser_3.io.in, out_channels_3_2.io.beat connect io.ser[3].out.bits, ser_3.io.out.bits connect io.ser[3].out.valid, ser_3.io.out.valid connect ser_3.io.out.ready, io.ser[3].out.ready node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _in_channels_WIRE.bits.sink, UInt<1>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect in_channels_0_1.bits, _in_channels_WIRE.bits connect in_channels_0_1.valid, _in_channels_WIRE.valid connect in_channels_0_1.ready, _in_channels_WIRE.ready inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE_1.valid, UInt<1>(0h0) connect _in_channels_WIRE_1.ready, UInt<1>(0h0) wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_2_1.bits, _in_channels_WIRE_1.bits connect in_channels_2_1.valid, _in_channels_WIRE_1.valid connect in_channels_2_1.ready, _in_channels_WIRE_1.ready inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready inst des_0 of GenericDeserializer_TLBeatw10_f32 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready inst des_2 of GenericDeserializer_TLBeatw88_f32 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready inst des_3 of GenericDeserializer_TLBeatw87_f32 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_1 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3	module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_1_out_ready, // @[TLSerdes.scala:40:16] output io_ser_1_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_3_out_ready, // @[TLSerdes.scala:40:16] output io_ser_3_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] output io_debug_ser_busy, // @[TLSerdes.scala:40:16] output io_debug_des_busy // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28] wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_2_2_io_protocol_bits_size; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_2_2_io_protocol_bits_source; // @[TLSerdes.scala:80:28] wire [63:0] _in_channels_2_2_io_protocol_bits_address; // @[TLSerdes.scala:80:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_0_2_io_protocol_bits_sink; // @[TLSerdes.scala:78:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_3_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_3_io_busy; // @[TLSerdes.scala:69:23] wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_1_io_busy; // @[TLSerdes.scala:69:23] wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50] wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50] wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50] wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50] wire auto_client_out_a_ready_0 = auto_client_out_a_ready; // @[TLSerdes.scala:39:9] wire auto_client_out_d_valid_0 = auto_client_out_d_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_d_bits_opcode_0 = auto_client_out_d_bits_opcode; // @[TLSerdes.scala:39:9] wire [1:0] auto_client_out_d_bits_param_0 = auto_client_out_d_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_size_0 = auto_client_out_d_bits_size; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_source_0 = auto_client_out_d_bits_source; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_sink_0 = auto_client_out_d_bits_sink; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_denied_0 = auto_client_out_d_bits_denied; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_d_bits_data_0 = auto_client_out_d_bits_data; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_corrupt_0 = auto_client_out_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_out_ready_0 = io_ser_1_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_out_ready_0 = io_ser_3_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire [1:0] _out_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] out_channels_3_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [7:0] manager_tl_a_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_mask = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_e_bits_sink = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] _out_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] out_channels_3_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [2:0] manager_tl_a_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_a_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] _out_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] out_channels_3_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _in_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _in_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [3:0] _out_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] out_channels_3_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] out_channels_3_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _in_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _in_channels_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [63:0] manager_tl_a_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_a_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] _out_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] out_channels_3_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _in_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [31:0] io_ser_0_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] out_channels_3_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _in_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire manager_tl_a_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_b_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_d_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_valid = 1'h0; // @[TLSerdes.scala:47:72] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire out_channels_3_1_valid = 1'h0; // @[Bundles.scala:264:61] wire out_channels_3_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _in_channels_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_channels_0_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _in_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_channels_2_1_ready = 1'h0; // @[Bundles.scala:265:61] wire io_ser_0_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_2_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_4_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire out_channels_3_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire clientNodeOut_a_ready = auto_client_out_a_ready_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] clientNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] clientNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] clientNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire clientNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire clientNodeOut_d_ready; // @[MixedNode.scala:542:17] wire clientNodeOut_d_valid = auto_client_out_d_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] clientNodeOut_d_bits_opcode = auto_client_out_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] clientNodeOut_d_bits_param = auto_client_out_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_size = auto_client_out_d_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_source = auto_client_out_d_bits_source_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_sink = auto_client_out_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_denied = auto_client_out_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] clientNodeOut_d_bits_data = auto_client_out_d_bits_data_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_corrupt = auto_client_out_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire _io_debug_ser_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire [2:0] auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] wire auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] wire io_debug_des_busy_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_valid_0 = clientNodeOut_a_valid; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode_0 = clientNodeOut_a_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param_0 = clientNodeOut_a_bits_param; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size_0 = clientNodeOut_a_bits_size; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source_0 = clientNodeOut_a_bits_source; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address_0 = clientNodeOut_a_bits_address; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask_0 = clientNodeOut_a_bits_mask; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data_0 = clientNodeOut_a_bits_data; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt_0 = clientNodeOut_a_bits_corrupt; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready_0 = clientNodeOut_d_ready; // @[TLSerdes.scala:39:9] wire [2:0] manager_tl_b_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_b_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_source; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_address; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_mask; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_b_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_b_valid; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_d_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_d_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_source; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_sink; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_denied; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_d_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_d_valid; // @[TLSerdes.scala:47:72] assign _io_debug_ser_busy_T = _ser_1_io_busy \| _ser_3_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy_0 = _io_debug_ser_busy_T; // @[TLSerdes.scala:39:9] wire in_channels_0_1_bits_sink; // @[Bundles.scala:267:61] wire in_channels_0_1_valid; // @[Bundles.scala:267:61] wire [2:0] in_channels_2_1_bits_opcode; // @[Bundles.scala:265:61] wire [2:0] in_channels_2_1_bits_param; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_size; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_source; // @[Bundles.scala:265:61] wire [31:0] in_channels_2_1_bits_address; // @[Bundles.scala:265:61] wire [63:0] in_channels_2_1_bits_data; // @[Bundles.scala:265:61] wire in_channels_2_1_bits_corrupt; // @[Bundles.scala:265:61] wire in_channels_2_1_valid; // @[Bundles.scala:265:61] assign in_channels_0_1_bits_sink = _in_channels_0_2_io_protocol_bits_sink[0]; // @[TLSerdes.scala:78:28, :85:9] assign in_channels_2_1_bits_size = _in_channels_2_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_source = _in_channels_2_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_address = _in_channels_2_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:80:28, :85:9] assign clientNodeOut_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:82:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T \| _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 \| _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 \| _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy_0 = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_d_ready), .io_protocol_valid (clientNodeOut_d_valid), // @[MixedNode.scala:542:17] .io_protocol_bits_opcode (clientNodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_protocol_bits_param (clientNodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_protocol_bits_size ({4'h0, clientNodeOut_d_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({4'h0, clientNodeOut_d_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_sink ({7'h0, clientNodeOut_d_bits_sink}), // @[TLSerdes.scala:68:21] .io_protocol_bits_denied (clientNodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_protocol_bits_data (clientNodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_protocol_bits_corrupt (clientNodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_1_2_io_beat_valid), .io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_1_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail) ); // @[TLSerdes.scala:60:50] TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_3_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_3_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail) ); // @[TLSerdes.scala:62:50] GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_1_io_in_ready), .io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50] .io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50] .io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50] .io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50] .io_out_ready (io_ser_1_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_1_out_valid_0), .io_out_bits_flit (io_ser_1_out_bits_flit_0), .io_busy (_ser_1_io_busy) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_3_io_in_ready), .io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50] .io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50] .io_out_ready (io_ser_3_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_3_out_valid_0), .io_out_bits_flit (io_ser_3_out_bits_flit_0), .io_busy (_ser_3_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_0_1_valid), .io_protocol_bits_sink (_in_channels_0_2_io_protocol_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_d_valid), .io_protocol_bits_opcode (manager_tl_d_bits_opcode), .io_protocol_bits_param (manager_tl_d_bits_param), .io_protocol_bits_size (manager_tl_d_bits_size), .io_protocol_bits_source (manager_tl_d_bits_source), .io_protocol_bits_sink (manager_tl_d_bits_sink), .io_protocol_bits_denied (manager_tl_d_bits_denied), .io_protocol_bits_data (manager_tl_d_bits_data), .io_protocol_bits_corrupt (manager_tl_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_2_1_valid), .io_protocol_bits_opcode (in_channels_2_1_bits_opcode), .io_protocol_bits_param (in_channels_2_1_bits_param), .io_protocol_bits_size (_in_channels_2_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_2_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_2_2_io_protocol_bits_address), .io_protocol_bits_data (in_channels_2_1_bits_data), .io_protocol_bits_corrupt (in_channels_2_1_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_b_valid), .io_protocol_bits_opcode (manager_tl_b_bits_opcode), .io_protocol_bits_param (manager_tl_b_bits_param), .io_protocol_bits_size (manager_tl_b_bits_size), .io_protocol_bits_source (manager_tl_b_bits_source), .io_protocol_bits_address (manager_tl_b_bits_address), .io_protocol_bits_mask (manager_tl_b_bits_mask), .io_protocol_bits_data (manager_tl_b_bits_data), .io_protocol_bits_corrupt (manager_tl_b_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_a_ready), // @[MixedNode.scala:542:17] .io_protocol_valid (clientNodeOut_a_valid), .io_protocol_bits_opcode (clientNodeOut_a_bits_opcode), .io_protocol_bits_param (clientNodeOut_a_bits_param), .io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address), .io_protocol_bits_mask (clientNodeOut_a_bits_mask), .io_protocol_bits_data (clientNodeOut_a_bits_data), .io_protocol_bits_corrupt (clientNodeOut_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_1 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_client_out_a_valid = auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode = auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param = auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size = auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source = auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address = auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask = auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data = auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt = auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready = auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_valid = io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_bits_flit = io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_valid = io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_bits_flit = io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_debug_ser_busy = io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] assign io_debug_des_busy = io_debug_des_busy_0; // @[TLSerdes.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_127 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_137 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_127( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_137 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_51 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_51( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Tile_215 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_471 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_215( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_471 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_7 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_7( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_167 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_423 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_167( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_423 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_68 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_68 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_68 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_100 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFN_e8_s24_68( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_68 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_68 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_100 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_228 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_484 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_228( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_484 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_20 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_20( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_91 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_92 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_to_bus_named_cbus : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst widget of TLWidthWidget16 connect widget.clock, clock connect widget.reset, reset wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect widget.auto.anon_out.d, bus_xingIn.d connect bus_xingIn.a.bits, widget.auto.anon_out.a.bits connect bus_xingIn.a.valid, widget.auto.anon_out.a.valid connect widget.auto.anon_out.a.ready, bus_xingIn.a.ready connect auto.bus_xing_out, bus_xingOut connect widget.auto.anon_in, auto.widget_anon_in extmodule plusarg_reader_8 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_9 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLInterconnectCoupler_sbus_to_bus_named_cbus( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[MixedNode.scala:542:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [7:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] TLWidthWidget16 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_param (auto_widget_anon_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_source (auto_widget_anon_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_mask (auto_widget_anon_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_widget_anon_in_d_bits_source_0), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0), .auto_anon_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (bus_xingIn_a_valid), .auto_anon_out_a_bits_opcode (bus_xingIn_a_bits_opcode), .auto_anon_out_a_bits_param (bus_xingIn_a_bits_param), .auto_anon_out_a_bits_size (bus_xingIn_a_bits_size), .auto_anon_out_a_bits_source (bus_xingIn_a_bits_source), .auto_anon_out_a_bits_address (bus_xingIn_a_bits_address), .auto_anon_out_a_bits_mask (bus_xingIn_a_bits_mask), .auto_anon_out_a_bits_data (bus_xingIn_a_bits_data), .auto_anon_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt), .auto_anon_out_d_ready (bus_xingIn_d_ready), .auto_anon_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[WidthWidget.scala:230:28] assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_54 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_54( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_55 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_55( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module Core : input clock : Clock input reset : Reset output io : { imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip dcpath : { halt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} inst c of CtlPath connect c.clock, clock connect c.reset, reset inst d of DatPath connect d.clock, clock connect d.reset, reset connect d.io.ctl, c.io.ctl connect c.io.dat, d.io.dat connect c.io.imem.resp, io.imem.resp connect io.imem.req.bits, c.io.imem.req.bits connect io.imem.req.valid, c.io.imem.req.valid connect c.io.imem.req.ready, io.imem.req.ready connect d.io.imem.resp, io.imem.resp connect io.imem.req.bits, d.io.imem.req.bits connect io.imem.req.valid, d.io.imem.req.valid connect d.io.imem.req.ready, io.imem.req.ready connect c.io.dmem.resp, io.dmem.resp connect io.dmem.req.bits, c.io.dmem.req.bits connect io.dmem.req.valid, c.io.dmem.req.valid connect c.io.dmem.req.ready, io.dmem.req.ready connect d.io.dmem.resp, io.dmem.resp connect io.dmem.req.bits, d.io.dmem.req.bits connect io.dmem.req.valid, d.io.dmem.req.valid connect d.io.dmem.req.ready, io.dmem.req.ready connect io.dmem.req.valid, c.io.dmem.req.valid connect io.dmem.req.bits.typ, c.io.dmem.req.bits.typ connect io.dmem.req.bits.fcn, c.io.dmem.req.bits.fcn connect d.io.ddpath, io.ddpath connect c.io.dcpath, io.dcpath connect d.io.interrupt.meip, io.interrupt.meip connect d.io.interrupt.msip, io.interrupt.msip connect d.io.interrupt.mtip, io.interrupt.mtip connect d.io.interrupt.debug, io.interrupt.debug connect d.io.hartid, io.hartid connect d.io.reset_vector, io.reset_vector	module Core( // @[core.scala:36:7] input clock, // @[core.scala:36:7] input reset, // @[core.scala:36:7] input io_imem_req_ready, // @[core.scala:38:14] output io_imem_req_valid, // @[core.scala:38:14] output [31:0] io_imem_req_bits_addr, // @[core.scala:38:14] input io_imem_resp_valid, // @[core.scala:38:14] input [31:0] io_imem_resp_bits_data, // @[core.scala:38:14] input io_dmem_req_ready, // @[core.scala:38:14] output io_dmem_req_valid, // @[core.scala:38:14] output [31:0] io_dmem_req_bits_addr, // @[core.scala:38:14] output [31:0] io_dmem_req_bits_data, // @[core.scala:38:14] output io_dmem_req_bits_fcn, // @[core.scala:38:14] output [2:0] io_dmem_req_bits_typ, // @[core.scala:38:14] input io_dmem_resp_valid, // @[core.scala:38:14] input [31:0] io_dmem_resp_bits_data, // @[core.scala:38:14] input io_interrupt_debug, // @[core.scala:38:14] input io_interrupt_mtip, // @[core.scala:38:14] input io_interrupt_msip, // @[core.scala:38:14] input io_interrupt_meip, // @[core.scala:38:14] input io_hartid // @[core.scala:38:14] ); wire _d_io_dat_if_valid_resp; // @[core.scala:40:18] wire [31:0] _d_io_dat_inst; // @[core.scala:40:18] wire _d_io_dat_br_eq; // @[core.scala:40:18] wire _d_io_dat_br_lt; // @[core.scala:40:18] wire _d_io_dat_br_ltu; // @[core.scala:40:18] wire _d_io_dat_inst_misaligned; // @[core.scala:40:18] wire _d_io_dat_data_misaligned; // @[core.scala:40:18] wire _d_io_dat_mem_store; // @[core.scala:40:18] wire _d_io_dat_csr_eret; // @[core.scala:40:18] wire _d_io_dat_csr_interrupt; // @[core.scala:40:18] wire _c_io_ctl_stall; // @[core.scala:39:18] wire _c_io_ctl_if_kill; // @[core.scala:39:18] wire [2:0] _c_io_ctl_pc_sel; // @[core.scala:39:18] wire [1:0] _c_io_ctl_op1_sel; // @[core.scala:39:18] wire [2:0] _c_io_ctl_op2_sel; // @[core.scala:39:18] wire [4:0] _c_io_ctl_alu_fun; // @[core.scala:39:18] wire [1:0] _c_io_ctl_wb_sel; // @[core.scala:39:18] wire _c_io_ctl_rf_wen; // @[core.scala:39:18] wire [2:0] _c_io_ctl_csr_cmd; // @[core.scala:39:18] wire _c_io_ctl_mem_val; // @[core.scala:39:18] wire [1:0] _c_io_ctl_mem_fcn; // @[core.scala:39:18] wire [2:0] _c_io_ctl_mem_typ; // @[core.scala:39:18] wire _c_io_ctl_exception; // @[core.scala:39:18] wire [31:0] _c_io_ctl_exception_cause; // @[core.scala:39:18] wire [2:0] _c_io_ctl_pc_sel_no_xept; // @[core.scala:39:18] wire io_imem_req_ready_0 = io_imem_req_ready; // @[core.scala:36:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[core.scala:36:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[core.scala:36:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[core.scala:36:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[core.scala:36:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[core.scala:36:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[core.scala:36:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[core.scala:36:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[core.scala:36:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[core.scala:36:7] wire io_hartid_0 = io_hartid; // @[core.scala:36:7] wire [31:0] io_reset_vector = 32'h10000; // @[core.scala:36:7, :38:14, :40:18] wire [4:0] io_ddpath_addr = 5'h0; // @[core.scala:36:7, :38:14, :40:18] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[core.scala:36:7, :38:14, :40:18] wire io_imem_req_bits_fcn = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_ddpath_validreq = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_ddpath_resetpc = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_dcpath_halt = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_imem_req_bits_data = 32'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_ddpath_wdata = 32'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_imem_req_bits_addr_0; // @[core.scala:36:7] wire io_imem_req_valid_0; // @[core.scala:36:7] wire [31:0] io_dmem_req_bits_addr_0; // @[core.scala:36:7] wire [31:0] io_dmem_req_bits_data_0; // @[core.scala:36:7] wire io_dmem_req_bits_fcn_0; // @[core.scala:36:7] wire [2:0] io_dmem_req_bits_typ_0; // @[core.scala:36:7] wire io_dmem_req_valid_0; // @[core.scala:36:7] wire [31:0] io_ddpath_rdata; // @[core.scala:36:7] CtlPath c ( // @[core.scala:39:18] .clock (clock), .reset (reset), .io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:36:7] .io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:36:7] .io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:36:7] .io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:36:7] .io_dmem_req_valid (io_dmem_req_valid_0), .io_dmem_req_bits_fcn (io_dmem_req_bits_fcn_0), .io_dmem_req_bits_typ (io_dmem_req_bits_typ_0), .io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:36:7] .io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:36:7] .io_dat_if_valid_resp (_d_io_dat_if_valid_resp), // @[core.scala:40:18] .io_dat_inst (_d_io_dat_inst), // @[core.scala:40:18] .io_dat_br_eq (_d_io_dat_br_eq), // @[core.scala:40:18] .io_dat_br_lt (_d_io_dat_br_lt), // @[core.scala:40:18] .io_dat_br_ltu (_d_io_dat_br_ltu), // @[core.scala:40:18] .io_dat_inst_misaligned (_d_io_dat_inst_misaligned), // @[core.scala:40:18] .io_dat_data_misaligned (_d_io_dat_data_misaligned), // @[core.scala:40:18] .io_dat_mem_store (_d_io_dat_mem_store), // @[core.scala:40:18] .io_dat_csr_eret (_d_io_dat_csr_eret), // @[core.scala:40:18] .io_dat_csr_interrupt (_d_io_dat_csr_interrupt), // @[core.scala:40:18] .io_ctl_stall (_c_io_ctl_stall), .io_ctl_if_kill (_c_io_ctl_if_kill), .io_ctl_pc_sel (_c_io_ctl_pc_sel), .io_ctl_op1_sel (_c_io_ctl_op1_sel), .io_ctl_op2_sel (_c_io_ctl_op2_sel), .io_ctl_alu_fun (_c_io_ctl_alu_fun), .io_ctl_wb_sel (_c_io_ctl_wb_sel), .io_ctl_rf_wen (_c_io_ctl_rf_wen), .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), .io_ctl_mem_val (_c_io_ctl_mem_val), .io_ctl_mem_fcn (_c_io_ctl_mem_fcn), .io_ctl_mem_typ (_c_io_ctl_mem_typ), .io_ctl_exception (_c_io_ctl_exception), .io_ctl_exception_cause (_c_io_ctl_exception_cause), .io_ctl_pc_sel_no_xept (_c_io_ctl_pc_sel_no_xept) ); // @[core.scala:39:18] DatPath d ( // @[core.scala:40:18] .clock (clock), .reset (reset), .io_ddpath_rdata (io_ddpath_rdata), .io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:36:7] .io_imem_req_valid (io_imem_req_valid_0), .io_imem_req_bits_addr (io_imem_req_bits_addr_0), .io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:36:7] .io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:36:7] .io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:36:7] .io_dmem_req_bits_addr (io_dmem_req_bits_addr_0), .io_dmem_req_bits_data (io_dmem_req_bits_data_0), .io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:36:7] .io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:36:7] .io_ctl_stall (_c_io_ctl_stall), // @[core.scala:39:18] .io_ctl_if_kill (_c_io_ctl_if_kill), // @[core.scala:39:18] .io_ctl_pc_sel (_c_io_ctl_pc_sel), // @[core.scala:39:18] .io_ctl_op1_sel (_c_io_ctl_op1_sel), // @[core.scala:39:18] .io_ctl_op2_sel (_c_io_ctl_op2_sel), // @[core.scala:39:18] .io_ctl_alu_fun (_c_io_ctl_alu_fun), // @[core.scala:39:18] .io_ctl_wb_sel (_c_io_ctl_wb_sel), // @[core.scala:39:18] .io_ctl_rf_wen (_c_io_ctl_rf_wen), // @[core.scala:39:18] .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), // @[core.scala:39:18] .io_ctl_mem_val (_c_io_ctl_mem_val), // @[core.scala:39:18] .io_ctl_mem_fcn (_c_io_ctl_mem_fcn), // @[core.scala:39:18] .io_ctl_mem_typ (_c_io_ctl_mem_typ), // @[core.scala:39:18] .io_ctl_exception (_c_io_ctl_exception), // @[core.scala:39:18] .io_ctl_exception_cause (_c_io_ctl_exception_cause), // @[core.scala:39:18] .io_ctl_pc_sel_no_xept (_c_io_ctl_pc_sel_no_xept), // @[core.scala:39:18] .io_dat_if_valid_resp (_d_io_dat_if_valid_resp), .io_dat_inst (_d_io_dat_inst), .io_dat_br_eq (_d_io_dat_br_eq), .io_dat_br_lt (_d_io_dat_br_lt), .io_dat_br_ltu (_d_io_dat_br_ltu), .io_dat_inst_misaligned (_d_io_dat_inst_misaligned), .io_dat_data_misaligned (_d_io_dat_data_misaligned), .io_dat_mem_store (_d_io_dat_mem_store), .io_dat_csr_eret (_d_io_dat_csr_eret), .io_dat_csr_interrupt (_d_io_dat_csr_interrupt), .io_interrupt_debug (io_interrupt_debug_0), // @[core.scala:36:7] .io_interrupt_mtip (io_interrupt_mtip_0), // @[core.scala:36:7] .io_interrupt_msip (io_interrupt_msip_0), // @[core.scala:36:7] .io_interrupt_meip (io_interrupt_meip_0), // @[core.scala:36:7] .io_hartid (io_hartid_0) // @[core.scala:36:7] ); // @[core.scala:40:18] assign io_imem_req_valid = io_imem_req_valid_0; // @[core.scala:36:7] assign io_imem_req_bits_addr = io_imem_req_bits_addr_0; // @[core.scala:36:7] assign io_dmem_req_valid = io_dmem_req_valid_0; // @[core.scala:36:7] assign io_dmem_req_bits_addr = io_dmem_req_bits_addr_0; // @[core.scala:36:7] assign io_dmem_req_bits_data = io_dmem_req_bits_data_0; // @[core.scala:36:7] assign io_dmem_req_bits_fcn = io_dmem_req_bits_fcn_0; // @[core.scala:36:7] assign io_dmem_req_bits_typ = io_dmem_req_bits_typ_0; // @[core.scala:36:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_67 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_67( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper_4 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn	module ReRoCCManagerControlRemapper_4( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_52 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_52 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_131 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulRecFN_52( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_52 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_131 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_507 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_251 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_507( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_251 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_33 = shr(io.in.a.bits.source, 2) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<14>(0h2000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<13>(0h1000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_48, _T_53) node _T_85 = or(_T_84, _T_58) node _T_86 = or(_T_85, _T_63) node _T_87 = or(_T_86, _T_68) node _T_88 = or(_T_87, _T_73) node _T_89 = or(_T_88, _T_78) node _T_90 = or(_T_89, _T_83) node _T_91 = and(_T_43, _T_90) node _T_92 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_95 = cvt(_T_94) node _T_96 = and(_T_95, asSInt(UInt<17>(0h10000))) node _T_97 = asSInt(_T_96) node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0))) node _T_99 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_100 = cvt(_T_99) node _T_101 = and(_T_100, asSInt(UInt<29>(0h10000000))) node _T_102 = asSInt(_T_101) node _T_103 = eq(_T_102, asSInt(UInt<1>(0h0))) node _T_104 = or(_T_98, _T_103) node _T_105 = and(_T_93, _T_104) node _T_106 = or(UInt<1>(0h0), _T_91) node _T_107 = or(_T_106, _T_105) node _T_108 = and(_T_42, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_108, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_2) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_117 connect _WIRE[1], _T_118 node _T_119 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_120 = mux(_WIRE[0], _T_119, UInt<1>(0h0)) node _T_121 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_122 = or(_T_120, _T_121) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_122 node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_125 = and(_T_123, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<14>(0h2000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<18>(0h2f000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<27>(0h4000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<29>(0h10000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_131, _T_136) node _T_178 = or(_T_177, _T_141) node _T_179 = or(_T_178, _T_146) node _T_180 = or(_T_179, _T_151) node _T_181 = or(_T_180, _T_156) node _T_182 = or(_T_181, _T_161) node _T_183 = or(_T_182, _T_166) node _T_184 = or(_T_183, _T_171) node _T_185 = or(_T_184, _T_176) node _T_186 = and(_T_126, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = and(_WIRE_1, _T_187) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(source_ok, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_195 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(_T_195, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_195, UInt<1>(0h1), "") : assert_5 node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(is_aligned, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_202 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_202, UInt<1>(0h1), "") : assert_7 node _T_206 = not(io.in.a.bits.mask) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(_T_207, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_207, UInt<1>(0h1), "") : assert_8 node _T_211 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_211, UInt<1>(0h1), "") : assert_9 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_219 = shr(io.in.a.bits.source, 2) node _T_220 = eq(_T_219, UInt<1>(0h0)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_3) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_226 = or(_T_224, _T_225) node _T_227 = and(_T_218, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<14>(0h2000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<17>(0h10000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<18>(0h2f000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<27>(0h4000000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<13>(0h1000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_234, _T_239) node _T_271 = or(_T_270, _T_244) node _T_272 = or(_T_271, _T_249) node _T_273 = or(_T_272, _T_254) node _T_274 = or(_T_273, _T_259) node _T_275 = or(_T_274, _T_264) node _T_276 = or(_T_275, _T_269) node _T_277 = and(_T_229, _T_276) node _T_278 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_279 = or(UInt<1>(0h0), _T_278) node _T_280 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<29>(0h10000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = or(_T_284, _T_289) node _T_291 = and(_T_279, _T_290) node _T_292 = or(UInt<1>(0h0), _T_277) node _T_293 = or(_T_292, _T_291) node _T_294 = and(_T_228, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_294, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_298 = shr(io.in.a.bits.source, 2) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = leq(UInt<1>(0h0), uncommonBits_4) node _T_301 = and(_T_299, _T_300) node _T_302 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_303 connect _WIRE_2[1], _T_304 node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_306 = mux(_WIRE_2[0], _T_305, UInt<1>(0h0)) node _T_307 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_308 = or(_T_306, _T_307) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<27>(0h4000000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_317, _T_322) node _T_364 = or(_T_363, _T_327) node _T_365 = or(_T_364, _T_332) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_342) node _T_368 = or(_T_367, _T_347) node _T_369 = or(_T_368, _T_352) node _T_370 = or(_T_369, _T_357) node _T_371 = or(_T_370, _T_362) node _T_372 = and(_T_312, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_WIRE_3, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_374, UInt<1>(0h1), "") : assert_11 node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(source_ok, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_381 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_381, UInt<1>(0h1), "") : assert_13 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(is_aligned, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_388 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_388, UInt<1>(0h1), "") : assert_15 node _T_392 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_392, UInt<1>(0h1), "") : assert_16 node _T_396 = not(io.in.a.bits.mask) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_397, UInt<1>(0h1), "") : assert_17 node _T_401 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_401, UInt<1>(0h1), "") : assert_18 node _T_405 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_405 : node _T_406 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_407 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_408 = and(_T_406, _T_407) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_5) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_416 = or(_T_414, _T_415) node _T_417 = and(_T_408, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_418, UInt<1>(0h1), "") : assert_19 node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_424 = and(_T_422, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = and(_T_425, _T_430) node _T_432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_433 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_434 = and(_T_432, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<14>(0h2000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<17>(0h10000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<29>(0h10000000))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_440, _T_445) node _T_482 = or(_T_481, _T_450) node _T_483 = or(_T_482, _T_455) node _T_484 = or(_T_483, _T_460) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_475) node _T_488 = or(_T_487, _T_480) node _T_489 = and(_T_435, _T_488) node _T_490 = or(UInt<1>(0h0), _T_431) node _T_491 = or(_T_490, _T_489) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_491, UInt<1>(0h1), "") : assert_20 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_501, UInt<1>(0h1), "") : assert_23 node _T_505 = eq(io.in.a.bits.mask, mask) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_505, UInt<1>(0h1), "") : assert_24 node _T_509 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_509, UInt<1>(0h1), "") : assert_25 node _T_513 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_513 : node _T_514 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_515 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_517 = shr(io.in.a.bits.source, 2) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_6) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_524 = or(_T_522, _T_523) node _T_525 = and(_T_516, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_528 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_529 = and(_T_527, _T_528) node _T_530 = or(UInt<1>(0h0), _T_529) node _T_531 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = and(_T_530, _T_535) node _T_537 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_538 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_539 = and(_T_537, _T_538) node _T_540 = or(UInt<1>(0h0), _T_539) node _T_541 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<14>(0h2000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<18>(0h2f000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<27>(0h4000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<13>(0h1000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<29>(0h10000000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = or(_T_545, _T_550) node _T_582 = or(_T_581, _T_555) node _T_583 = or(_T_582, _T_560) node _T_584 = or(_T_583, _T_565) node _T_585 = or(_T_584, _T_570) node _T_586 = or(_T_585, _T_575) node _T_587 = or(_T_586, _T_580) node _T_588 = and(_T_540, _T_587) node _T_589 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_590 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_591 = cvt(_T_590) node _T_592 = and(_T_591, asSInt(UInt<17>(0h10000))) node _T_593 = asSInt(_T_592) node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0))) node _T_595 = and(_T_589, _T_594) node _T_596 = or(UInt<1>(0h0), _T_536) node _T_597 = or(_T_596, _T_588) node _T_598 = or(_T_597, _T_595) node _T_599 = and(_T_526, _T_598) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_599, UInt<1>(0h1), "") : assert_26 node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(source_ok, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_609 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_609, UInt<1>(0h1), "") : assert_29 node _T_613 = eq(io.in.a.bits.mask, mask) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_613, UInt<1>(0h1), "") : assert_30 node _T_617 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_617 : node _T_618 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_619 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h0)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_7) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_628 = or(_T_626, _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_703, UInt<1>(0h1), "") : assert_31 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_713, UInt<1>(0h1), "") : assert_34 node _T_717 = not(mask) node _T_718 = and(io.in.a.bits.mask, _T_717) node _T_719 = eq(_T_718, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_719, UInt<1>(0h1), "") : assert_35 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<1>(0h0)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_8) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_734 = or(_T_732, _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<18>(0h2f000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<17>(0h10000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<13>(0h1000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<27>(0h4000000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<29>(0h10000000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_745, _T_750) node _T_787 = or(_T_786, _T_755) node _T_788 = or(_T_787, _T_760) node _T_789 = or(_T_788, _T_765) node _T_790 = or(_T_789, _T_770) node _T_791 = or(_T_790, _T_775) node _T_792 = or(_T_791, _T_780) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_740, _T_793) node _T_795 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_796 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = and(_T_795, _T_800) node _T_802 = or(UInt<1>(0h0), _T_794) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_736, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h0)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_9) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_833 = or(_T_831, _T_832) node _T_834 = and(_T_825, _T_833) node _T_835 = or(UInt<1>(0h0), _T_834) node _T_836 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_837 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _T_839 = or(UInt<1>(0h0), _T_838) node _T_840 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<14>(0h2000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<18>(0h2f000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_856 = cvt(_T_855) node _T_857 = and(_T_856, asSInt(UInt<17>(0h10000))) node _T_858 = asSInt(_T_857) node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0))) node _T_860 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<17>(0h10000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_871 = cvt(_T_870) node _T_872 = and(_T_871, asSInt(UInt<27>(0h4000000))) node _T_873 = asSInt(_T_872) node _T_874 = eq(_T_873, asSInt(UInt<1>(0h0))) node _T_875 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_876 = cvt(_T_875) node _T_877 = and(_T_876, asSInt(UInt<13>(0h1000))) node _T_878 = asSInt(_T_877) node _T_879 = eq(_T_878, asSInt(UInt<1>(0h0))) node _T_880 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<29>(0h10000000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = or(_T_844, _T_849) node _T_886 = or(_T_885, _T_854) node _T_887 = or(_T_886, _T_859) node _T_888 = or(_T_887, _T_864) node _T_889 = or(_T_888, _T_869) node _T_890 = or(_T_889, _T_874) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_884) node _T_893 = and(_T_839, _T_892) node _T_894 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_895 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_896 = cvt(_T_895) node _T_897 = and(_T_896, asSInt(UInt<17>(0h10000))) node _T_898 = asSInt(_T_897) node _T_899 = eq(_T_898, asSInt(UInt<1>(0h0))) node _T_900 = and(_T_894, _T_899) node _T_901 = or(UInt<1>(0h0), _T_893) node _T_902 = or(_T_901, _T_900) node _T_903 = and(_T_835, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_903, UInt<1>(0h1), "") : assert_41 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_913 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_913, UInt<1>(0h1), "") : assert_44 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_917, UInt<1>(0h1), "") : assert_45 node _T_921 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<1>(0h0)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_10) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_930 = and(_T_928, _T_929) node _T_931 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_932 = or(_T_930, _T_931) node _T_933 = and(_T_924, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_936 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_937 = and(_T_935, _T_936) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<14>(0h2000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<17>(0h10000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<18>(0h2f000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<17>(0h10000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = or(_T_950, _T_955) node _T_982 = or(_T_981, _T_960) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_970) node _T_985 = or(_T_984, _T_975) node _T_986 = or(_T_985, _T_980) node _T_987 = and(_T_945, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h10000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_944) node _T_1005 = or(_T_1004, _T_987) node _T_1006 = or(_T_1005, _T_1003) node _T_1007 = and(_T_934, _T_1006) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_46 node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(is_aligned, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1017 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_49 node _T_1021 = eq(io.in.a.bits.mask, mask) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_50 node _T_1025 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1029 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1033 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1033 : node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(source_ok_1, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1037 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_54 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_55 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_56 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_57 node _T_1053 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(source_ok_1, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(sink_ok, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1060 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_60 node _T_1064 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_61 node _T_1068 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_62 node _T_1072 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_63 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(UInt<1>(0h1), _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_64 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(source_ok_1, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_67 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_68 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_69 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(_T_1100, io.in.d.bits.corrupt) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_70 node _T_1105 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1106 = or(UInt<1>(0h1), _T_1105) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_71 node _T_1110 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1110 : node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(source_ok_1, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1114 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_73 node _T_1118 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_74 node _T_1122 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1123 = or(UInt<1>(0h1), _T_1122) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_75 node _T_1127 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1127 : node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(source_ok_1, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1131 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_77 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.d.bits.corrupt) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_78 node _T_1140 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1141 = or(UInt<1>(0h1), _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_79 node _T_1145 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1145 : node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok_1, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1149 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_81 node _T_1153 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_82 node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1158 = or(UInt<1>(0h1), _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1162 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1166 = shr(io.in.b.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = or(_T_1172, _T_1177) node _T_1179 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) node _T_1181 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1182 = cvt(_T_1181) node _T_1183 = and(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = asSInt(_T_1183) node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = or(_T_1180, _T_1185) node _T_1187 = and(_T_1178, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1191 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1191 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1192 = shr(io.in.b.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1197 connect _WIRE_4[1], _T_1198 node _T_1199 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1200 = mux(_WIRE_4[0], _T_1199, UInt<1>(0h0)) node _T_1201 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1202 = or(_T_1200, _T_1201) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1202 node _T_1203 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1204 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<14>(0h2000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<13>(0h1000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<17>(0h10000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<17>(0h10000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<27>(0h4000000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1248 = cvt(_T_1247) node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000))) node _T_1250 = asSInt(_T_1249) node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0))) node _T_1252 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1253 = cvt(_T_1252) node _T_1254 = and(_T_1253, asSInt(UInt<29>(0h10000000))) node _T_1255 = asSInt(_T_1254) node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = or(_T_1211, _T_1216) node _T_1258 = or(_T_1257, _T_1221) node _T_1259 = or(_T_1258, _T_1226) node _T_1260 = or(_T_1259, _T_1231) node _T_1261 = or(_T_1260, _T_1236) node _T_1262 = or(_T_1261, _T_1241) node _T_1263 = or(_T_1262, _T_1246) node _T_1264 = or(_T_1263, _T_1251) node _T_1265 = or(_T_1264, _T_1256) node _T_1266 = and(_T_1206, _T_1265) node _T_1267 = or(UInt<1>(0h0), _T_1266) node _T_1268 = and(_WIRE_5, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_86 node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(address_ok, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(legal_source, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1281 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_90 node _T_1285 = eq(io.in.b.bits.mask, mask_1) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_91 node _T_1289 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_92 node _T_1293 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1293 : node _T_1294 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1295 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1299 = cvt(_T_1298) node _T_1300 = and(_T_1299, asSInt(UInt<14>(0h2000))) node _T_1301 = asSInt(_T_1300) node _T_1302 = eq(_T_1301, asSInt(UInt<1>(0h0))) node _T_1303 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1309 = cvt(_T_1308) node _T_1310 = and(_T_1309, asSInt(UInt<17>(0h10000))) node _T_1311 = asSInt(_T_1310) node _T_1312 = eq(_T_1311, asSInt(UInt<1>(0h0))) node _T_1313 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<18>(0h2f000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<27>(0h4000000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<29>(0h10000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1302, _T_1307) node _T_1349 = or(_T_1348, _T_1312) node _T_1350 = or(_T_1349, _T_1317) node _T_1351 = or(_T_1350, _T_1322) node _T_1352 = or(_T_1351, _T_1327) node _T_1353 = or(_T_1352, _T_1332) node _T_1354 = or(_T_1353, _T_1337) node _T_1355 = or(_T_1354, _T_1342) node _T_1356 = or(_T_1355, _T_1347) node _T_1357 = and(_T_1297, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = and(UInt<1>(0h0), _T_1358) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_93 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(address_ok, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(legal_source, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1372 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_97 node _T_1376 = eq(io.in.b.bits.mask, mask_1) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_98 node _T_1380 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_99 node _T_1384 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1384 : node _T_1385 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1386 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1390 = cvt(_T_1389) node _T_1391 = and(_T_1390, asSInt(UInt<14>(0h2000))) node _T_1392 = asSInt(_T_1391) node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0))) node _T_1394 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<17>(0h10000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<18>(0h2f000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1410 = cvt(_T_1409) node _T_1411 = and(_T_1410, asSInt(UInt<17>(0h10000))) node _T_1412 = asSInt(_T_1411) node _T_1413 = eq(_T_1412, asSInt(UInt<1>(0h0))) node _T_1414 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<13>(0h1000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<27>(0h4000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<13>(0h1000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1435 = cvt(_T_1434) node _T_1436 = and(_T_1435, asSInt(UInt<29>(0h10000000))) node _T_1437 = asSInt(_T_1436) node _T_1438 = eq(_T_1437, asSInt(UInt<1>(0h0))) node _T_1439 = or(_T_1393, _T_1398) node _T_1440 = or(_T_1439, _T_1403) node _T_1441 = or(_T_1440, _T_1408) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1418) node _T_1444 = or(_T_1443, _T_1423) node _T_1445 = or(_T_1444, _T_1428) node _T_1446 = or(_T_1445, _T_1433) node _T_1447 = or(_T_1446, _T_1438) node _T_1448 = and(_T_1388, _T_1447) node _T_1449 = or(UInt<1>(0h0), _T_1448) node _T_1450 = and(UInt<1>(0h0), _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(address_ok, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(legal_source, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1463 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_104 node _T_1467 = eq(io.in.b.bits.mask, mask_1) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_105 node _T_1471 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1471 : node _T_1472 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1473 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1474 = and(_T_1472, _T_1473) node _T_1475 = or(UInt<1>(0h0), _T_1474) node _T_1476 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<14>(0h2000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<13>(0h1000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<18>(0h2f000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<17>(0h10000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<13>(0h1000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<17>(0h10000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1512 = cvt(_T_1511) node _T_1513 = and(_T_1512, asSInt(UInt<27>(0h4000000))) node _T_1514 = asSInt(_T_1513) node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0))) node _T_1516 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1517 = cvt(_T_1516) node _T_1518 = and(_T_1517, asSInt(UInt<13>(0h1000))) node _T_1519 = asSInt(_T_1518) node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0))) node _T_1521 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<29>(0h10000000))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1480, _T_1485) node _T_1527 = or(_T_1526, _T_1490) node _T_1528 = or(_T_1527, _T_1495) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1505) node _T_1531 = or(_T_1530, _T_1510) node _T_1532 = or(_T_1531, _T_1515) node _T_1533 = or(_T_1532, _T_1520) node _T_1534 = or(_T_1533, _T_1525) node _T_1535 = and(_T_1475, _T_1534) node _T_1536 = or(UInt<1>(0h0), _T_1535) node _T_1537 = and(UInt<1>(0h0), _T_1536) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_106 node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(address_ok, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(legal_source, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1550 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_110 node _T_1554 = not(mask_1) node _T_1555 = and(io.in.b.bits.mask, _T_1554) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_111 node _T_1560 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1560 : node _T_1561 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1562 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1566 = cvt(_T_1565) node _T_1567 = and(_T_1566, asSInt(UInt<14>(0h2000))) node _T_1568 = asSInt(_T_1567) node _T_1569 = eq(_T_1568, asSInt(UInt<1>(0h0))) node _T_1570 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<13>(0h1000))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h10000))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<18>(0h2f000))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1586 = cvt(_T_1585) node _T_1587 = and(_T_1586, asSInt(UInt<17>(0h10000))) node _T_1588 = asSInt(_T_1587) node _T_1589 = eq(_T_1588, asSInt(UInt<1>(0h0))) node _T_1590 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1591 = cvt(_T_1590) node _T_1592 = and(_T_1591, asSInt(UInt<13>(0h1000))) node _T_1593 = asSInt(_T_1592) node _T_1594 = eq(_T_1593, asSInt(UInt<1>(0h0))) node _T_1595 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1596 = cvt(_T_1595) node _T_1597 = and(_T_1596, asSInt(UInt<17>(0h10000))) node _T_1598 = asSInt(_T_1597) node _T_1599 = eq(_T_1598, asSInt(UInt<1>(0h0))) node _T_1600 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1601 = cvt(_T_1600) node _T_1602 = and(_T_1601, asSInt(UInt<27>(0h4000000))) node _T_1603 = asSInt(_T_1602) node _T_1604 = eq(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1606 = cvt(_T_1605) node _T_1607 = and(_T_1606, asSInt(UInt<13>(0h1000))) node _T_1608 = asSInt(_T_1607) node _T_1609 = eq(_T_1608, asSInt(UInt<1>(0h0))) node _T_1610 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1611 = cvt(_T_1610) node _T_1612 = and(_T_1611, asSInt(UInt<29>(0h10000000))) node _T_1613 = asSInt(_T_1612) node _T_1614 = eq(_T_1613, asSInt(UInt<1>(0h0))) node _T_1615 = or(_T_1569, _T_1574) node _T_1616 = or(_T_1615, _T_1579) node _T_1617 = or(_T_1616, _T_1584) node _T_1618 = or(_T_1617, _T_1589) node _T_1619 = or(_T_1618, _T_1594) node _T_1620 = or(_T_1619, _T_1599) node _T_1621 = or(_T_1620, _T_1604) node _T_1622 = or(_T_1621, _T_1609) node _T_1623 = or(_T_1622, _T_1614) node _T_1624 = and(_T_1564, _T_1623) node _T_1625 = or(UInt<1>(0h0), _T_1624) node _T_1626 = and(UInt<1>(0h0), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_112 node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(address_ok, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(legal_source, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1639 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_116 node _T_1643 = eq(io.in.b.bits.mask, mask_1) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_117 node _T_1647 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1647 : node _T_1648 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1649 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1650 = and(_T_1648, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1650) node _T_1652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<14>(0h2000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<13>(0h1000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<18>(0h2f000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1673 = cvt(_T_1672) node _T_1674 = and(_T_1673, asSInt(UInt<17>(0h10000))) node _T_1675 = asSInt(_T_1674) node _T_1676 = eq(_T_1675, asSInt(UInt<1>(0h0))) node _T_1677 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1678 = cvt(_T_1677) node _T_1679 = and(_T_1678, asSInt(UInt<13>(0h1000))) node _T_1680 = asSInt(_T_1679) node _T_1681 = eq(_T_1680, asSInt(UInt<1>(0h0))) node _T_1682 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1683 = cvt(_T_1682) node _T_1684 = and(_T_1683, asSInt(UInt<17>(0h10000))) node _T_1685 = asSInt(_T_1684) node _T_1686 = eq(_T_1685, asSInt(UInt<1>(0h0))) node _T_1687 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1688 = cvt(_T_1687) node _T_1689 = and(_T_1688, asSInt(UInt<27>(0h4000000))) node _T_1690 = asSInt(_T_1689) node _T_1691 = eq(_T_1690, asSInt(UInt<1>(0h0))) node _T_1692 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1693 = cvt(_T_1692) node _T_1694 = and(_T_1693, asSInt(UInt<13>(0h1000))) node _T_1695 = asSInt(_T_1694) node _T_1696 = eq(_T_1695, asSInt(UInt<1>(0h0))) node _T_1697 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1698 = cvt(_T_1697) node _T_1699 = and(_T_1698, asSInt(UInt<29>(0h10000000))) node _T_1700 = asSInt(_T_1699) node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = or(_T_1656, _T_1661) node _T_1703 = or(_T_1702, _T_1666) node _T_1704 = or(_T_1703, _T_1671) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1681) node _T_1707 = or(_T_1706, _T_1686) node _T_1708 = or(_T_1707, _T_1691) node _T_1709 = or(_T_1708, _T_1696) node _T_1710 = or(_T_1709, _T_1701) node _T_1711 = and(_T_1651, _T_1710) node _T_1712 = or(UInt<1>(0h0), _T_1711) node _T_1713 = and(UInt<1>(0h0), _T_1712) node _T_1714 = asUInt(reset) node _T_1715 = eq(_T_1714, UInt<1>(0h0)) when _T_1715 : node _T_1716 = eq(_T_1713, UInt<1>(0h0)) when _T_1716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1713, UInt<1>(0h1), "") : assert_118 node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(address_ok, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(legal_source, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1726 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_122 node _T_1730 = eq(io.in.b.bits.mask, mask_1) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_123 node _T_1734 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1734 : node _T_1735 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1736 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1740 = cvt(_T_1739) node _T_1741 = and(_T_1740, asSInt(UInt<14>(0h2000))) node _T_1742 = asSInt(_T_1741) node _T_1743 = eq(_T_1742, asSInt(UInt<1>(0h0))) node _T_1744 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<13>(0h1000))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1750 = cvt(_T_1749) node _T_1751 = and(_T_1750, asSInt(UInt<17>(0h10000))) node _T_1752 = asSInt(_T_1751) node _T_1753 = eq(_T_1752, asSInt(UInt<1>(0h0))) node _T_1754 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<18>(0h2f000))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1760 = cvt(_T_1759) node _T_1761 = and(_T_1760, asSInt(UInt<17>(0h10000))) node _T_1762 = asSInt(_T_1761) node _T_1763 = eq(_T_1762, asSInt(UInt<1>(0h0))) node _T_1764 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1765 = cvt(_T_1764) node _T_1766 = and(_T_1765, asSInt(UInt<13>(0h1000))) node _T_1767 = asSInt(_T_1766) node _T_1768 = eq(_T_1767, asSInt(UInt<1>(0h0))) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h10000))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<27>(0h4000000))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1780 = cvt(_T_1779) node _T_1781 = and(_T_1780, asSInt(UInt<13>(0h1000))) node _T_1782 = asSInt(_T_1781) node _T_1783 = eq(_T_1782, asSInt(UInt<1>(0h0))) node _T_1784 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1785 = cvt(_T_1784) node _T_1786 = and(_T_1785, asSInt(UInt<29>(0h10000000))) node _T_1787 = asSInt(_T_1786) node _T_1788 = eq(_T_1787, asSInt(UInt<1>(0h0))) node _T_1789 = or(_T_1743, _T_1748) node _T_1790 = or(_T_1789, _T_1753) node _T_1791 = or(_T_1790, _T_1758) node _T_1792 = or(_T_1791, _T_1763) node _T_1793 = or(_T_1792, _T_1768) node _T_1794 = or(_T_1793, _T_1773) node _T_1795 = or(_T_1794, _T_1778) node _T_1796 = or(_T_1795, _T_1783) node _T_1797 = or(_T_1796, _T_1788) node _T_1798 = and(_T_1738, _T_1797) node _T_1799 = or(UInt<1>(0h0), _T_1798) node _T_1800 = and(UInt<1>(0h0), _T_1799) node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(_T_1800, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1800, UInt<1>(0h1), "") : assert_124 node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(address_ok, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1807 = asUInt(reset) node _T_1808 = eq(_T_1807, UInt<1>(0h0)) when _T_1808 : node _T_1809 = eq(legal_source, UInt<1>(0h0)) when _T_1809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1813 = eq(io.in.b.bits.mask, mask_1) node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(_T_1813, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1813, UInt<1>(0h1), "") : assert_128 node _T_1817 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1818 = asUInt(reset) node _T_1819 = eq(_T_1818, UInt<1>(0h0)) when _T_1819 : node _T_1820 = eq(_T_1817, UInt<1>(0h0)) when _T_1820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1817, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1821 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1822 = asUInt(reset) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) when _T_1823 : node _T_1824 = eq(_T_1821, UInt<1>(0h0)) when _T_1824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1821, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 2) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1825 = shr(io.in.c.bits.source, 2) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) node _T_1827 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1828 = and(_T_1826, _T_1827) node _T_1829 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1830 = and(_T_1828, _T_1829) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) node _T_1832 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = or(_T_1831, _T_1836) node _T_1838 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1839 = eq(_T_1838, UInt<1>(0h0)) node _T_1840 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = or(_T_1839, _T_1844) node _T_1846 = and(_T_1837, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_131 node _T_1850 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1850 : node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(address_ok_1, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(source_ok_2, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1857 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_134 node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1864 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_136 node _T_1868 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_137 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1872 : node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(address_ok_1, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_2, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1879 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_140 node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1886 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1887 = asUInt(reset) node _T_1888 = eq(_T_1887, UInt<1>(0h0)) when _T_1888 : node _T_1889 = eq(_T_1886, UInt<1>(0h0)) when _T_1889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1886, UInt<1>(0h1), "") : assert_142 node _T_1890 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1890 : node _T_1891 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1892 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1893 = and(_T_1891, _T_1892) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1894 = shr(io.in.c.bits.source, 2) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1897 = and(_T_1895, _T_1896) node _T_1898 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1901 = or(_T_1899, _T_1900) node _T_1902 = and(_T_1893, _T_1901) node _T_1903 = or(UInt<1>(0h0), _T_1902) node _T_1904 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1905 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1906 = cvt(_T_1905) node _T_1907 = and(_T_1906, asSInt(UInt<14>(0h2000))) node _T_1908 = asSInt(_T_1907) node _T_1909 = eq(_T_1908, asSInt(UInt<1>(0h0))) node _T_1910 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1911 = cvt(_T_1910) node _T_1912 = and(_T_1911, asSInt(UInt<13>(0h1000))) node _T_1913 = asSInt(_T_1912) node _T_1914 = eq(_T_1913, asSInt(UInt<1>(0h0))) node _T_1915 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1916 = cvt(_T_1915) node _T_1917 = and(_T_1916, asSInt(UInt<17>(0h10000))) node _T_1918 = asSInt(_T_1917) node _T_1919 = eq(_T_1918, asSInt(UInt<1>(0h0))) node _T_1920 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1921 = cvt(_T_1920) node _T_1922 = and(_T_1921, asSInt(UInt<18>(0h2f000))) node _T_1923 = asSInt(_T_1922) node _T_1924 = eq(_T_1923, asSInt(UInt<1>(0h0))) node _T_1925 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1926 = cvt(_T_1925) node _T_1927 = and(_T_1926, asSInt(UInt<17>(0h10000))) node _T_1928 = asSInt(_T_1927) node _T_1929 = eq(_T_1928, asSInt(UInt<1>(0h0))) node _T_1930 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1931 = cvt(_T_1930) node _T_1932 = and(_T_1931, asSInt(UInt<13>(0h1000))) node _T_1933 = asSInt(_T_1932) node _T_1934 = eq(_T_1933, asSInt(UInt<1>(0h0))) node _T_1935 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1936 = cvt(_T_1935) node _T_1937 = and(_T_1936, asSInt(UInt<27>(0h4000000))) node _T_1938 = asSInt(_T_1937) node _T_1939 = eq(_T_1938, asSInt(UInt<1>(0h0))) node _T_1940 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1941 = cvt(_T_1940) node _T_1942 = and(_T_1941, asSInt(UInt<13>(0h1000))) node _T_1943 = asSInt(_T_1942) node _T_1944 = eq(_T_1943, asSInt(UInt<1>(0h0))) node _T_1945 = or(_T_1909, _T_1914) node _T_1946 = or(_T_1945, _T_1919) node _T_1947 = or(_T_1946, _T_1924) node _T_1948 = or(_T_1947, _T_1929) node _T_1949 = or(_T_1948, _T_1934) node _T_1950 = or(_T_1949, _T_1939) node _T_1951 = or(_T_1950, _T_1944) node _T_1952 = and(_T_1904, _T_1951) node _T_1953 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<17>(0h10000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1961 = cvt(_T_1960) node _T_1962 = and(_T_1961, asSInt(UInt<29>(0h10000000))) node _T_1963 = asSInt(_T_1962) node _T_1964 = eq(_T_1963, asSInt(UInt<1>(0h0))) node _T_1965 = or(_T_1959, _T_1964) node _T_1966 = and(_T_1954, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1952) node _T_1968 = or(_T_1967, _T_1966) node _T_1969 = and(_T_1903, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_1973 = shr(io.in.c.bits.source, 2) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) node _T_1975 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_1978 = and(_T_1976, _T_1977) node _T_1979 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1978 connect _WIRE_6[1], _T_1979 node _T_1980 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1981 = mux(_WIRE_6[0], _T_1980, UInt<1>(0h0)) node _T_1982 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1983 = or(_T_1981, _T_1982) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1983 node _T_1984 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1985 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1986 = and(_T_1984, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1989 = cvt(_T_1988) node _T_1990 = and(_T_1989, asSInt(UInt<14>(0h2000))) node _T_1991 = asSInt(_T_1990) node _T_1992 = eq(_T_1991, asSInt(UInt<1>(0h0))) node _T_1993 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1994 = cvt(_T_1993) node _T_1995 = and(_T_1994, asSInt(UInt<13>(0h1000))) node _T_1996 = asSInt(_T_1995) node _T_1997 = eq(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1999 = cvt(_T_1998) node _T_2000 = and(_T_1999, asSInt(UInt<17>(0h10000))) node _T_2001 = asSInt(_T_2000) node _T_2002 = eq(_T_2001, asSInt(UInt<1>(0h0))) node _T_2003 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<18>(0h2f000))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2009 = cvt(_T_2008) node _T_2010 = and(_T_2009, asSInt(UInt<17>(0h10000))) node _T_2011 = asSInt(_T_2010) node _T_2012 = eq(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2014 = cvt(_T_2013) node _T_2015 = and(_T_2014, asSInt(UInt<13>(0h1000))) node _T_2016 = asSInt(_T_2015) node _T_2017 = eq(_T_2016, asSInt(UInt<1>(0h0))) node _T_2018 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2019 = cvt(_T_2018) node _T_2020 = and(_T_2019, asSInt(UInt<17>(0h10000))) node _T_2021 = asSInt(_T_2020) node _T_2022 = eq(_T_2021, asSInt(UInt<1>(0h0))) node _T_2023 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<27>(0h4000000))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2029 = cvt(_T_2028) node _T_2030 = and(_T_2029, asSInt(UInt<13>(0h1000))) node _T_2031 = asSInt(_T_2030) node _T_2032 = eq(_T_2031, asSInt(UInt<1>(0h0))) node _T_2033 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2034 = cvt(_T_2033) node _T_2035 = and(_T_2034, asSInt(UInt<29>(0h10000000))) node _T_2036 = asSInt(_T_2035) node _T_2037 = eq(_T_2036, asSInt(UInt<1>(0h0))) node _T_2038 = or(_T_1992, _T_1997) node _T_2039 = or(_T_2038, _T_2002) node _T_2040 = or(_T_2039, _T_2007) node _T_2041 = or(_T_2040, _T_2012) node _T_2042 = or(_T_2041, _T_2017) node _T_2043 = or(_T_2042, _T_2022) node _T_2044 = or(_T_2043, _T_2027) node _T_2045 = or(_T_2044, _T_2032) node _T_2046 = or(_T_2045, _T_2037) node _T_2047 = and(_T_1987, _T_2046) node _T_2048 = or(UInt<1>(0h0), _T_2047) node _T_2049 = and(_WIRE_7, _T_2048) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_144 node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_2, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2056 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_146 node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2063 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_148 node _T_2067 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_149 node _T_2071 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2071 : node _T_2072 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2073 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2075 = shr(io.in.c.bits.source, 2) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2082 = or(_T_2080, _T_2081) node _T_2083 = and(_T_2074, _T_2082) node _T_2084 = or(UInt<1>(0h0), _T_2083) node _T_2085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<14>(0h2000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<13>(0h1000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<17>(0h10000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<18>(0h2f000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<17>(0h10000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<27>(0h4000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2122 = cvt(_T_2121) node _T_2123 = and(_T_2122, asSInt(UInt<13>(0h1000))) node _T_2124 = asSInt(_T_2123) node _T_2125 = eq(_T_2124, asSInt(UInt<1>(0h0))) node _T_2126 = or(_T_2090, _T_2095) node _T_2127 = or(_T_2126, _T_2100) node _T_2128 = or(_T_2127, _T_2105) node _T_2129 = or(_T_2128, _T_2110) node _T_2130 = or(_T_2129, _T_2115) node _T_2131 = or(_T_2130, _T_2120) node _T_2132 = or(_T_2131, _T_2125) node _T_2133 = and(_T_2085, _T_2132) node _T_2134 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2135 = or(UInt<1>(0h0), _T_2134) node _T_2136 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2137 = cvt(_T_2136) node _T_2138 = and(_T_2137, asSInt(UInt<17>(0h10000))) node _T_2139 = asSInt(_T_2138) node _T_2140 = eq(_T_2139, asSInt(UInt<1>(0h0))) node _T_2141 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<29>(0h10000000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = or(_T_2140, _T_2145) node _T_2147 = and(_T_2135, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2133) node _T_2149 = or(_T_2148, _T_2147) node _T_2150 = and(_T_2084, _T_2149) node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(_T_2150, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2150, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2154 = shr(io.in.c.bits.source, 2) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2157 = and(_T_2155, _T_2156) node _T_2158 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2159 = and(_T_2157, _T_2158) node _T_2160 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2159 connect _WIRE_8[1], _T_2160 node _T_2161 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2162 = mux(_WIRE_8[0], _T_2161, UInt<1>(0h0)) node _T_2163 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2164 = or(_T_2162, _T_2163) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2164 node _T_2165 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2166 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = or(UInt<1>(0h0), _T_2167) node _T_2169 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<14>(0h2000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<18>(0h2f000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<17>(0h10000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<13>(0h1000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2200 = cvt(_T_2199) node _T_2201 = and(_T_2200, asSInt(UInt<17>(0h10000))) node _T_2202 = asSInt(_T_2201) node _T_2203 = eq(_T_2202, asSInt(UInt<1>(0h0))) node _T_2204 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2205 = cvt(_T_2204) node _T_2206 = and(_T_2205, asSInt(UInt<27>(0h4000000))) node _T_2207 = asSInt(_T_2206) node _T_2208 = eq(_T_2207, asSInt(UInt<1>(0h0))) node _T_2209 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2210 = cvt(_T_2209) node _T_2211 = and(_T_2210, asSInt(UInt<13>(0h1000))) node _T_2212 = asSInt(_T_2211) node _T_2213 = eq(_T_2212, asSInt(UInt<1>(0h0))) node _T_2214 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2215 = cvt(_T_2214) node _T_2216 = and(_T_2215, asSInt(UInt<29>(0h10000000))) node _T_2217 = asSInt(_T_2216) node _T_2218 = eq(_T_2217, asSInt(UInt<1>(0h0))) node _T_2219 = or(_T_2173, _T_2178) node _T_2220 = or(_T_2219, _T_2183) node _T_2221 = or(_T_2220, _T_2188) node _T_2222 = or(_T_2221, _T_2193) node _T_2223 = or(_T_2222, _T_2198) node _T_2224 = or(_T_2223, _T_2203) node _T_2225 = or(_T_2224, _T_2208) node _T_2226 = or(_T_2225, _T_2213) node _T_2227 = or(_T_2226, _T_2218) node _T_2228 = and(_T_2168, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_9, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_151 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_153 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_155 node _T_2248 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2248 : node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(address_ok_1, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(source_ok_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2255 = asUInt(reset) node _T_2256 = eq(_T_2255, UInt<1>(0h0)) when _T_2256 : node _T_2257 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2258 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_159 node _T_2262 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_160 node _T_2266 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2266 : node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(address_ok_1, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(source_ok_2, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2276 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_164 node _T_2280 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2280 : node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(address_ok_1, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(source_ok_2, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2290 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_168 node _T_2294 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2301 = eq(a_first, UInt<1>(0h0)) node _T_2302 = and(io.in.a.valid, _T_2301) when _T_2302 : node _T_2303 = eq(io.in.a.bits.opcode, opcode) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_171 node _T_2307 = eq(io.in.a.bits.param, param) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_172 node _T_2311 = eq(io.in.a.bits.size, size) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_173 node _T_2315 = eq(io.in.a.bits.source, source) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_174 node _T_2319 = eq(io.in.a.bits.address, address) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_175 node _T_2323 = and(io.in.a.ready, io.in.a.valid) node _T_2324 = and(_T_2323, a_first) when _T_2324 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2325 = eq(d_first, UInt<1>(0h0)) node _T_2326 = and(io.in.d.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.d.bits.opcode, opcode_1) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_176 node _T_2331 = eq(io.in.d.bits.param, param_1) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_177 node _T_2335 = eq(io.in.d.bits.size, size_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_178 node _T_2339 = eq(io.in.d.bits.source, source_1) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_179 node _T_2343 = eq(io.in.d.bits.sink, sink) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_180 node _T_2347 = eq(io.in.d.bits.denied, denied) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_181 node _T_2351 = and(io.in.d.ready, io.in.d.valid) node _T_2352 = and(_T_2351, d_first) when _T_2352 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2353 = eq(b_first, UInt<1>(0h0)) node _T_2354 = and(io.in.b.valid, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.b.bits.opcode, opcode_2) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_182 node _T_2359 = eq(io.in.b.bits.param, param_2) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_183 node _T_2363 = eq(io.in.b.bits.size, size_2) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_184 node _T_2367 = eq(io.in.b.bits.source, source_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_185 node _T_2371 = eq(io.in.b.bits.address, address_1) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_186 node _T_2375 = and(io.in.b.ready, io.in.b.valid) node _T_2376 = and(_T_2375, b_first) when _T_2376 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2377 = eq(c_first, UInt<1>(0h0)) node _T_2378 = and(io.in.c.valid, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.c.bits.opcode, opcode_3) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_187 node _T_2383 = eq(io.in.c.bits.param, param_3) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_188 node _T_2387 = eq(io.in.c.bits.size, size_3) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_189 node _T_2391 = eq(io.in.c.bits.source, source_3) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_190 node _T_2395 = eq(io.in.c.bits.address, address_2) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_191 node _T_2399 = and(io.in.c.ready, io.in.c.valid) node _T_2400 = and(_T_2399, c_first) when _T_2400 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2401 = and(io.in.a.valid, a_first_1) node _T_2402 = and(_T_2401, UInt<1>(0h1)) when _T_2402 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2403 = and(io.in.a.ready, io.in.a.valid) node _T_2404 = and(_T_2403, a_first_1) node _T_2405 = and(_T_2404, UInt<1>(0h1)) when _T_2405 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2406 = dshr(inflight, io.in.a.bits.source) node _T_2407 = bits(_T_2406, 0, 0) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) node _T_2409 = asUInt(reset) node _T_2410 = eq(_T_2409, UInt<1>(0h0)) when _T_2410 : node _T_2411 = eq(_T_2408, UInt<1>(0h0)) when _T_2411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2408, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2412 = and(io.in.d.valid, d_first_1) node _T_2413 = and(_T_2412, UInt<1>(0h1)) node _T_2414 = eq(d_release_ack, UInt<1>(0h0)) node _T_2415 = and(_T_2413, _T_2414) when _T_2415 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2416 = and(io.in.d.ready, io.in.d.valid) node _T_2417 = and(_T_2416, d_first_1) node _T_2418 = and(_T_2417, UInt<1>(0h1)) node _T_2419 = eq(d_release_ack, UInt<1>(0h0)) node _T_2420 = and(_T_2418, _T_2419) when _T_2420 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2421 = and(io.in.d.valid, d_first_1) node _T_2422 = and(_T_2421, UInt<1>(0h1)) node _T_2423 = eq(d_release_ack, UInt<1>(0h0)) node _T_2424 = and(_T_2422, _T_2423) when _T_2424 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2425 = dshr(inflight, io.in.d.bits.source) node _T_2426 = bits(_T_2425, 0, 0) node _T_2427 = or(_T_2426, same_cycle_resp) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2431 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2432 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2433 = or(_T_2431, _T_2432) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_194 node _T_2437 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_195 else : node _T_2441 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2442 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2443 = or(_T_2441, _T_2442) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_196 node _T_2447 = eq(io.in.d.bits.size, a_size_lookup) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_197 node _T_2451 = and(io.in.d.valid, d_first_1) node _T_2452 = and(_T_2451, a_first_1) node _T_2453 = and(_T_2452, io.in.a.valid) node _T_2454 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2455 = and(_T_2453, _T_2454) node _T_2456 = eq(d_release_ack, UInt<1>(0h0)) node _T_2457 = and(_T_2455, _T_2456) when _T_2457 : node _T_2458 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2459 = or(_T_2458, io.in.a.ready) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_198 node _T_2463 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2464 = orr(a_set_wo_ready) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) node _T_2466 = or(_T_2463, _T_2465) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_2470 = orr(inflight) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) node _T_2472 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2473 = or(_T_2471, _T_2472) node _T_2474 = lt(watchdog, plusarg_reader.out) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = asUInt(reset) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) when _T_2477 : node _T_2478 = eq(_T_2475, UInt<1>(0h0)) when _T_2478 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2475, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2479 = and(io.in.a.ready, io.in.a.valid) node _T_2480 = and(io.in.d.ready, io.in.d.valid) node _T_2481 = or(_T_2479, _T_2480) when _T_2481 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2482 = and(io.in.c.valid, c_first_1) node _T_2483 = bits(io.in.c.bits.opcode, 2, 2) node _T_2484 = bits(io.in.c.bits.opcode, 1, 1) node _T_2485 = and(_T_2483, _T_2484) node _T_2486 = and(_T_2482, _T_2485) when _T_2486 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2487 = and(io.in.c.ready, io.in.c.valid) node _T_2488 = and(_T_2487, c_first_1) node _T_2489 = bits(io.in.c.bits.opcode, 2, 2) node _T_2490 = bits(io.in.c.bits.opcode, 1, 1) node _T_2491 = and(_T_2489, _T_2490) node _T_2492 = and(_T_2488, _T_2491) when _T_2492 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2493 = dshr(inflight_1, io.in.c.bits.source) node _T_2494 = bits(_T_2493, 0, 0) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2499 = and(io.in.d.valid, d_first_2) node _T_2500 = and(_T_2499, UInt<1>(0h1)) node _T_2501 = and(_T_2500, d_release_ack_1) when _T_2501 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2502 = and(io.in.d.ready, io.in.d.valid) node _T_2503 = and(_T_2502, d_first_2) node _T_2504 = and(_T_2503, UInt<1>(0h1)) node _T_2505 = and(_T_2504, d_release_ack_1) when _T_2505 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2506 = and(io.in.d.valid, d_first_2) node _T_2507 = and(_T_2506, UInt<1>(0h1)) node _T_2508 = and(_T_2507, d_release_ack_1) when _T_2508 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2509 = dshr(inflight_1, io.in.d.bits.source) node _T_2510 = bits(_T_2509, 0, 0) node _T_2511 = or(_T_2510, same_cycle_resp_1) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2515 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_203 else : node _T_2519 = eq(io.in.d.bits.size, c_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_204 node _T_2523 = and(io.in.d.valid, d_first_2) node _T_2524 = and(_T_2523, c_first_1) node _T_2525 = and(_T_2524, io.in.c.valid) node _T_2526 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = and(_T_2527, d_release_ack_1) node _T_2529 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2530 = and(_T_2528, _T_2529) when _T_2530 : node _T_2531 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2532 = or(_T_2531, io.in.c.ready) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_205 node _T_2536 = orr(c_set_wo_ready) when _T_2536 : node _T_2537 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_2541 = orr(inflight_1) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) node _T_2543 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2544 = or(_T_2542, _T_2543) node _T_2545 = lt(watchdog_1, plusarg_reader_1.out) node _T_2546 = or(_T_2544, _T_2545) node _T_2547 = asUInt(reset) node _T_2548 = eq(_T_2547, UInt<1>(0h0)) when _T_2548 : node _T_2549 = eq(_T_2546, UInt<1>(0h0)) when _T_2549 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2546, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2550 = and(io.in.c.ready, io.in.c.valid) node _T_2551 = and(io.in.d.ready, io.in.d.valid) node _T_2552 = or(_T_2550, _T_2551) when _T_2552 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2553 = and(io.in.d.ready, io.in.d.valid) node _T_2554 = and(_T_2553, d_first_3) node _T_2555 = bits(io.in.d.bits.opcode, 2, 2) node _T_2556 = bits(io.in.d.bits.opcode, 1, 1) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = and(_T_2555, _T_2557) node _T_2559 = and(_T_2554, _T_2558) when _T_2559 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2560 = dshr(inflight_2, io.in.d.bits.sink) node _T_2561 = bits(_T_2560, 0, 0) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = asUInt(reset) node _T_2564 = eq(_T_2563, UInt<1>(0h0)) when _T_2564 : node _T_2565 = eq(_T_2562, UInt<1>(0h0)) when _T_2565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2562, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2566 = and(io.in.e.ready, io.in.e.valid) node _T_2567 = and(_T_2566, UInt<1>(0h1)) node _T_2568 = and(_T_2567, UInt<1>(0h1)) when _T_2568 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2569 = or(d_set, inflight_2) node _T_2570 = dshr(_T_2569, io.in.e.bits.sink) node _T_2571 = bits(_T_2570, 0, 0) node _T_2572 = asUInt(reset) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) when _T_2573 : node _T_2574 = eq(_T_2571, UInt<1>(0h0)) when _T_2574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2571, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = &io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = &io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = &io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_8 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = &io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2479 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2479; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2479; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2553 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2553; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2550 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2550; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2550; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_22 = 4'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2405 = _T_2479 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2405 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2405 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2405 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2405 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2405 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2451 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_24 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_25 = 4'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2451 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2420 = _T_2553 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2420 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2420 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2420 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_set; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [15:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [31:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_26 = {2'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_27 = 4'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2550 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2492 ? _c_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2492 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2492 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2492 ? _c_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2492 ? _c_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2523 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2523 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_2505 = _T_2553 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2505 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2505 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2505 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [3:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2559 = _T_2553 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2559 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2568 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2568 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>}}, flip lb_resp : UInt<128>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 4) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock reg refill_ctr : UInt<2>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2) node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2) node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2) node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4) node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2) node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5) node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2) node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6) node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2) node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8) node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8) node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9) node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9) node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10) node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10) node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11) node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11) node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12) node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12) node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13) node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13) node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14) node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14) node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15) node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15) node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo) node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8) node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo) node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12) node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<4>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node word_idx = bits(rp_addr, 3, 3) node _data_word_T = cat(word_idx, UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 4) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<2>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<2>(0h3)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1	module BoomMSHR( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_valid, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [1:0] io_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h0; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:342:30] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire io_lb_write_ready = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [33:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:261:22, :262:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:262:56, :264:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :264:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [35:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :340:59] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :345:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_137 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_137( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_148, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_10) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_11) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_12) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_13) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_193 = shr(io.in.a.bits.source, 3) node _T_194 = eq(_T_193, UInt<3>(0h4)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0)) node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = or(_T_202, _T_203) node _T_211 = or(_T_210, _T_204) node _T_212 = or(_T_211, _T_205) node _T_213 = or(_T_212, _T_206) node _T_214 = or(_T_213, _T_207) node _T_215 = or(_T_214, _T_208) node _T_216 = or(_T_215, _T_209) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_15) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_16) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_17) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_18) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_290 = shr(io.in.a.bits.source, 3) node _T_291 = eq(_T_290, UInt<3>(0h4)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_19) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = or(_T_265, _T_271) node _T_299 = or(_T_298, _T_277) node _T_300 = or(_T_299, _T_283) node _T_301 = or(_T_300, _T_289) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = and(_T_264, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = and(_T_308, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = and(_T_306, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_322, UInt<1>(0h1), "") : assert_10 node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_20) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<1>(0h1)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_21) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h2)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_22) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<2>(0h3)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_23) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<3>(0h4)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_24) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_326 connect _WIRE_2[1], _T_332 connect _WIRE_2[2], _T_338 connect _WIRE_2[3], _T_344 connect _WIRE_2[4], _T_350 connect _WIRE_2[5], _T_356 connect _WIRE_2[6], _T_357 connect _WIRE_2[7], _T_358 node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0)) node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = or(_T_360, _T_361) node _T_369 = or(_T_368, _T_362) node _T_370 = or(_T_369, _T_363) node _T_371 = or(_T_370, _T_364) node _T_372 = or(_T_371, _T_365) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_374 node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_383, _T_388) node _T_390 = and(_T_378, _T_389) node _T_391 = or(UInt<1>(0h0), _T_390) node _T_392 = and(_WIRE_3, _T_391) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_392, UInt<1>(0h1), "") : assert_11 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(source_ok, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_399, UInt<1>(0h1), "") : assert_13 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(is_aligned, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_406, UInt<1>(0h1), "") : assert_15 node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_410, UInt<1>(0h1), "") : assert_16 node _T_414 = not(io.in.a.bits.mask) node _T_415 = eq(_T_414, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_415, UInt<1>(0h1), "") : assert_17 node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_419, UInt<1>(0h1), "") : assert_18 node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_423 : node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_25) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_433 = and(_T_431, _T_432) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_434 = shr(io.in.a.bits.source, 2) node _T_435 = eq(_T_434, UInt<1>(0h1)) node _T_436 = leq(UInt<1>(0h0), uncommonBits_26) node _T_437 = and(_T_435, _T_436) node _T_438 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_439 = and(_T_437, _T_438) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<2>(0h2)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_27) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<2>(0h3)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_28) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<3>(0h4)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_29) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_460 = or(_T_427, _T_433) node _T_461 = or(_T_460, _T_439) node _T_462 = or(_T_461, _T_445) node _T_463 = or(_T_462, _T_451) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = and(_T_426, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_468, UInt<1>(0h1), "") : assert_19 node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_474 = and(_T_472, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = or(_T_480, _T_485) node _T_487 = and(_T_475, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_488, UInt<1>(0h1), "") : assert_20 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(source_ok, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_498, UInt<1>(0h1), "") : assert_23 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_502, UInt<1>(0h1), "") : assert_24 node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_506, UInt<1>(0h1), "") : assert_25 node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_510 : node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_30) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<1>(0h1)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_31) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h2)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_32) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_533 = shr(io.in.a.bits.source, 2) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_33) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<3>(0h4)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_34) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_547 = or(_T_514, _T_520) node _T_548 = or(_T_547, _T_526) node _T_549 = or(_T_548, _T_532) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_544) node _T_552 = or(_T_551, _T_545) node _T_553 = or(_T_552, _T_546) node _T_554 = and(_T_513, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = or(_T_564, _T_569) node _T_571 = and(_T_559, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = and(_T_555, _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_573, UInt<1>(0h1), "") : assert_26 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_583, UInt<1>(0h1), "") : assert_29 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_587, UInt<1>(0h1), "") : assert_30 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_35) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_620 = shr(io.in.a.bits.source, 3) node _T_621 = eq(_T_620, UInt<3>(0h4)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = and(_T_594, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_639 = and(_T_637, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = or(_T_645, _T_650) node _T_652 = and(_T_640, _T_651) node _T_653 = or(UInt<1>(0h0), _T_652) node _T_654 = and(_T_636, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_654, UInt<1>(0h1), "") : assert_31 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(source_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(is_aligned, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_664, UInt<1>(0h1), "") : assert_34 node _T_668 = not(mask) node _T_669 = and(io.in.a.bits.mask, _T_668) node _T_670 = eq(_T_669, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_670, UInt<1>(0h1), "") : assert_35 node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_674 : node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_679 = shr(io.in.a.bits.source, 2) node _T_680 = eq(_T_679, UInt<1>(0h0)) node _T_681 = leq(UInt<1>(0h0), uncommonBits_40) node _T_682 = and(_T_680, _T_681) node _T_683 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_684 = and(_T_682, _T_683) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_41) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<2>(0h2)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_42) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h3)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_43) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_703 = shr(io.in.a.bits.source, 3) node _T_704 = eq(_T_703, UInt<3>(0h4)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_44) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_711 = or(_T_678, _T_684) node _T_712 = or(_T_711, _T_690) node _T_713 = or(_T_712, _T_696) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = and(_T_677, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_722 = and(_T_720, _T_721) node _T_723 = or(UInt<1>(0h0), _T_722) node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = or(_T_728, _T_733) node _T_735 = and(_T_723, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = and(_T_719, _T_736) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_737, UInt<1>(0h1), "") : assert_36 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(source_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(is_aligned, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_747, UInt<1>(0h1), "") : assert_39 node _T_751 = eq(io.in.a.bits.mask, mask) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_751, UInt<1>(0h1), "") : assert_40 node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_755 : node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_45) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<1>(0h1)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_46) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h2)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_47) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<2>(0h3)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_48) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_784 = shr(io.in.a.bits.source, 3) node _T_785 = eq(_T_784, UInt<3>(0h4)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_49) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_792 = or(_T_759, _T_765) node _T_793 = or(_T_792, _T_771) node _T_794 = or(_T_793, _T_777) node _T_795 = or(_T_794, _T_783) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = and(_T_758, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_803 = and(_T_801, _T_802) node _T_804 = or(UInt<1>(0h0), _T_803) node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = or(_T_809, _T_814) node _T_816 = and(_T_804, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = and(_T_800, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(source_ok, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<1>(0h0)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_50) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h1)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_51) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<2>(0h2)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_52) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h3)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_53) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_865 = shr(io.in.a.bits.source, 3) node _T_866 = eq(_T_865, UInt<3>(0h4)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_54) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_873 = or(_T_840, _T_846) node _T_874 = or(_T_873, _T_852) node _T_875 = or(_T_874, _T_858) node _T_876 = or(_T_875, _T_864) node _T_877 = or(_T_876, _T_870) node _T_878 = or(_T_877, _T_871) node _T_879 = or(_T_878, _T_872) node _T_880 = and(_T_839, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_884 = and(_T_882, _T_883) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = or(_T_890, _T_895) node _T_897 = and(_T_885, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_881, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h1), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h1), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h1), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h1), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h1), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1061 = cvt(_T_1060) node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = asSInt(_T_1062) node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0))) node _T_1065 = or(_T_1059, _T_1064) node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1066 = shr(io.in.b.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1072, _T_1077) node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1079 = shr(io.in.b.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h1)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1085, _T_1090) node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1092 = shr(io.in.b.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = or(_T_1098, _T_1103) node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1105 = shr(io.in.b.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = or(_T_1111, _T_1116) node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1118 = shr(io.in.b.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1124, _T_1129) node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = or(_T_1132, _T_1137) node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1065, _T_1078) node _T_1148 = and(_T_1147, _T_1091) node _T_1149 = and(_T_1148, _T_1104) node _T_1150 = and(_T_1149, _T_1117) node _T_1151 = and(_T_1150, _T_1130) node _T_1152 = and(_T_1151, _T_1138) node _T_1153 = and(_T_1152, _T_1146) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 3) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _legal_source_WIRE : UInt<1>[8] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_31 connect _legal_source_WIRE[7], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38) node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_47 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1157 : node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1165 = shr(io.in.b.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1171 = shr(io.in.b.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1177 = shr(io.in.b.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1183 = shr(io.in.b.bits.source, 3) node _T_1184 = eq(_T_1183, UInt<3>(0h4)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _WIRE_4 : UInt<1>[8] connect _WIRE_4[0], _T_1158 connect _WIRE_4[1], _T_1164 connect _WIRE_4[2], _T_1170 connect _WIRE_4[3], _T_1176 connect _WIRE_4[4], _T_1182 connect _WIRE_4[5], _T_1188 connect _WIRE_4[6], _T_1189 connect _WIRE_4[7], _T_1190 node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0)) node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1200 = or(_T_1192, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = or(_T_1205, _T_1199) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1206 node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(UInt<1>(0h0), _T_1209) node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1212 = cvt(_T_1211) node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0))) node _T_1214 = asSInt(_T_1213) node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0))) node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = or(_T_1215, _T_1220) node _T_1222 = and(_T_1210, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = and(_WIRE_5, _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86 node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(address_ok, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(legal_source, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90 node _T_1241 = eq(io.in.b.bits.mask, mask_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91 node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92 node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = or(UInt<1>(0h0), _T_1252) node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = or(_T_1258, _T_1263) node _T_1265 = and(_T_1253, _T_1264) node _T_1266 = or(UInt<1>(0h0), _T_1265) node _T_1267 = and(UInt<1>(0h0), _T_1266) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93 node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(address_ok, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(legal_source, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97 node _T_1284 = eq(io.in.b.bits.mask, mask_1) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98 node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99 node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1292 : node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = or(_T_1301, _T_1306) node _T_1308 = and(_T_1296, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = and(UInt<1>(0h0), _T_1309) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100 node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(address_ok, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(legal_source, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104 node _T_1327 = eq(io.in.b.bits.mask, mask_1) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105 node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1331 : node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1337 = cvt(_T_1336) node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0))) node _T_1339 = asSInt(_T_1338) node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0))) node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = or(_T_1340, _T_1345) node _T_1347 = and(_T_1335, _T_1346) node _T_1348 = or(UInt<1>(0h0), _T_1347) node _T_1349 = and(UInt<1>(0h0), _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106 node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(address_ok, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(legal_source, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110 node _T_1366 = not(mask_1) node _T_1367 = and(io.in.b.bits.mask, _T_1366) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111 node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = or(_T_1381, _T_1386) node _T_1388 = and(_T_1376, _T_1387) node _T_1389 = or(UInt<1>(0h0), _T_1388) node _T_1390 = and(UInt<1>(0h0), _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(address_ok, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(legal_source, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116 node _T_1407 = eq(io.in.b.bits.mask, mask_1) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117 node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1411 : node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = or(UInt<1>(0h0), _T_1414) node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = or(_T_1420, _T_1425) node _T_1427 = and(_T_1415, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1427) node _T_1429 = and(UInt<1>(0h0), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(address_ok, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(legal_source, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122 node _T_1446 = eq(io.in.b.bits.mask, mask_1) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123 node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1450 : node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1456 = cvt(_T_1455) node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0))) node _T_1458 = asSInt(_T_1457) node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0))) node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1461 = cvt(_T_1460) node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0))) node _T_1463 = asSInt(_T_1462) node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0))) node _T_1465 = or(_T_1459, _T_1464) node _T_1466 = and(_T_1454, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1466) node _T_1468 = and(UInt<1>(0h0), _T_1467) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124 node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(address_ok, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(legal_source, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1481 = eq(io.in.b.bits.mask, mask_1) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128 node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130 node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_97 = shr(io.in.c.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0) node _source_ok_T_103 = shr(io.in.c.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_2 : UInt<1>[8] connect _source_ok_WIRE_2[0], _source_ok_T_78 connect _source_ok_WIRE_2[1], _source_ok_T_84 connect _source_ok_WIRE_2[2], _source_ok_T_90 connect _source_ok_WIRE_2[3], _source_ok_T_96 connect _source_ok_WIRE_2[4], _source_ok_T_102 connect _source_ok_WIRE_2[5], _source_ok_T_108 connect _source_ok_WIRE_2[6], _source_ok_T_109 connect _source_ok_WIRE_2[7], _source_ok_T_110 node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6]) node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = or(_T_1494, _T_1499) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1501 = shr(io.in.c.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = or(_T_1507, _T_1512) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1514 = shr(io.in.c.bits.source, 2) node _T_1515 = eq(_T_1514, UInt<1>(0h1)) node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1520, _T_1525) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1527 = shr(io.in.c.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h2)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = or(_T_1533, _T_1538) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1540 = shr(io.in.c.bits.source, 2) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1553 = shr(io.in.c.bits.source, 3) node _T_1554 = eq(_T_1553, UInt<3>(0h4)) node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1556 = and(_T_1554, _T_1555) node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = or(_T_1567, _T_1572) node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1577 = cvt(_T_1576) node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = asSInt(_T_1578) node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = or(_T_1575, _T_1580) node _T_1582 = and(_T_1500, _T_1513) node _T_1583 = and(_T_1582, _T_1526) node _T_1584 = and(_T_1583, _T_1539) node _T_1585 = and(_T_1584, _T_1552) node _T_1586 = and(_T_1585, _T_1565) node _T_1587 = and(_T_1586, _T_1573) node _T_1588 = and(_T_1587, _T_1581) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131 node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1592 : node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(address_ok_1, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(source_ok_2, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136 node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137 node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1614 : node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(address_ok_1, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_2, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140 node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142 node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1632 : node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1637 = shr(io.in.c.bits.source, 2) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1640 = and(_T_1638, _T_1639) node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1642 = and(_T_1640, _T_1641) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1643 = shr(io.in.c.bits.source, 2) node _T_1644 = eq(_T_1643, UInt<1>(0h1)) node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1646 = and(_T_1644, _T_1645) node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1648 = and(_T_1646, _T_1647) node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1649 = shr(io.in.c.bits.source, 2) node _T_1650 = eq(_T_1649, UInt<2>(0h2)) node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1652 = and(_T_1650, _T_1651) node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1654 = and(_T_1652, _T_1653) node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1655 = shr(io.in.c.bits.source, 2) node _T_1656 = eq(_T_1655, UInt<2>(0h3)) node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1660 = and(_T_1658, _T_1659) node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1661 = shr(io.in.c.bits.source, 3) node _T_1662 = eq(_T_1661, UInt<3>(0h4)) node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1664 = and(_T_1662, _T_1663) node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1666 = and(_T_1664, _T_1665) node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1669 = or(_T_1636, _T_1642) node _T_1670 = or(_T_1669, _T_1648) node _T_1671 = or(_T_1670, _T_1654) node _T_1672 = or(_T_1671, _T_1660) node _T_1673 = or(_T_1672, _T_1666) node _T_1674 = or(_T_1673, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = and(_T_1635, _T_1675) node _T_1677 = or(UInt<1>(0h0), _T_1676) node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1679 = or(UInt<1>(0h0), _T_1678) node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1684, _T_1689) node _T_1691 = and(_T_1679, _T_1690) node _T_1692 = or(UInt<1>(0h0), _T_1691) node _T_1693 = and(_T_1677, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143 node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0) node _T_1704 = shr(io.in.c.bits.source, 2) node _T_1705 = eq(_T_1704, UInt<1>(0h1)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0) node _T_1710 = shr(io.in.c.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_1716 = shr(io.in.c.bits.source, 2) node _T_1717 = eq(_T_1716, UInt<2>(0h3)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_1721 = and(_T_1719, _T_1720) node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0) node _T_1722 = shr(io.in.c.bits.source, 3) node _T_1723 = eq(_T_1722, UInt<3>(0h4)) node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7)) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_1697 connect _WIRE_6[1], _T_1703 connect _WIRE_6[2], _T_1709 connect _WIRE_6[3], _T_1715 connect _WIRE_6[4], _T_1721 connect _WIRE_6[5], _T_1727 connect _WIRE_6[6], _T_1728 connect _WIRE_6[7], _T_1729 node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0)) node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1745 node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1748 = and(_T_1746, _T_1747) node _T_1749 = or(UInt<1>(0h0), _T_1748) node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = or(_T_1754, _T_1759) node _T_1761 = and(_T_1749, _T_1760) node _T_1762 = or(UInt<1>(0h0), _T_1761) node _T_1763 = and(_WIRE_7, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144 node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(source_ok_2, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1771 = asUInt(reset) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) when _T_1772 : node _T_1773 = eq(_T_1770, UInt<1>(0h0)) when _T_1773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146 node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148 node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149 node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0) node _T_1790 = shr(io.in.c.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0) node _T_1796 = shr(io.in.c.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<1>(0h1)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0) node _T_1802 = shr(io.in.c.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<2>(0h2)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0) node _T_1808 = shr(io.in.c.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<2>(0h3)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0) node _T_1814 = shr(io.in.c.bits.source, 3) node _T_1815 = eq(_T_1814, UInt<3>(0h4)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7)) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1822 = or(_T_1789, _T_1795) node _T_1823 = or(_T_1822, _T_1801) node _T_1824 = or(_T_1823, _T_1807) node _T_1825 = or(_T_1824, _T_1813) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = and(_T_1788, _T_1828) node _T_1830 = or(UInt<1>(0h0), _T_1829) node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1832 = or(UInt<1>(0h0), _T_1831) node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1834 = cvt(_T_1833) node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0))) node _T_1836 = asSInt(_T_1835) node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0))) node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1839 = cvt(_T_1838) node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0))) node _T_1841 = asSInt(_T_1840) node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = or(_T_1837, _T_1842) node _T_1844 = and(_T_1832, _T_1843) node _T_1845 = or(UInt<1>(0h0), _T_1844) node _T_1846 = and(_T_1830, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150 node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1851 = shr(io.in.c.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1857 = shr(io.in.c.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<1>(0h1)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1863 = shr(io.in.c.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<2>(0h2)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_1869 = shr(io.in.c.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<2>(0h3)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0) node _T_1875 = shr(io.in.c.bits.source, 3) node _T_1876 = eq(_T_1875, UInt<3>(0h4)) node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7)) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_8 : UInt<1>[8] connect _WIRE_8[0], _T_1850 connect _WIRE_8[1], _T_1856 connect _WIRE_8[2], _T_1862 connect _WIRE_8[3], _T_1868 connect _WIRE_8[4], _T_1874 connect _WIRE_8[5], _T_1880 connect _WIRE_8[6], _T_1881 connect _WIRE_8[7], _T_1882 node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0)) node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1892 = or(_T_1884, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) node _T_1896 = or(_T_1895, _T_1889) node _T_1897 = or(_T_1896, _T_1890) node _T_1898 = or(_T_1897, _T_1891) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1898 node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = or(_T_1907, _T_1912) node _T_1914 = and(_T_1902, _T_1913) node _T_1915 = or(UInt<1>(0h0), _T_1914) node _T_1916 = and(_WIRE_9, _T_1915) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151 node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(source_ok_2, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155 node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1941 = asUInt(reset) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) when _T_1942 : node _T_1943 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159 node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160 node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(address_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_2, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164 node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1966 : node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(address_ok_1, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_2, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168 node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1987 = eq(a_first, UInt<1>(0h0)) node _T_1988 = and(io.in.a.valid, _T_1987) when _T_1988 : node _T_1989 = eq(io.in.a.bits.opcode, opcode) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171 node _T_1993 = eq(io.in.a.bits.param, param) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172 node _T_1997 = eq(io.in.a.bits.size, size) node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(_T_1997, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173 node _T_2001 = eq(io.in.a.bits.source, source) node _T_2002 = asUInt(reset) node _T_2003 = eq(_T_2002, UInt<1>(0h0)) when _T_2003 : node _T_2004 = eq(_T_2001, UInt<1>(0h0)) when _T_2004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174 node _T_2005 = eq(io.in.a.bits.address, address) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175 node _T_2009 = and(io.in.a.ready, io.in.a.valid) node _T_2010 = and(_T_2009, a_first) when _T_2010 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2011 = eq(d_first, UInt<1>(0h0)) node _T_2012 = and(io.in.d.valid, _T_2011) when _T_2012 : node _T_2013 = eq(io.in.d.bits.opcode, opcode_1) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176 node _T_2017 = eq(io.in.d.bits.param, param_1) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177 node _T_2021 = eq(io.in.d.bits.size, size_1) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178 node _T_2025 = eq(io.in.d.bits.source, source_1) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179 node _T_2029 = eq(io.in.d.bits.sink, sink) node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(_T_2029, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180 node _T_2033 = eq(io.in.d.bits.denied, denied) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181 node _T_2037 = and(io.in.d.ready, io.in.d.valid) node _T_2038 = and(_T_2037, d_first) when _T_2038 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2039 = eq(b_first, UInt<1>(0h0)) node _T_2040 = and(io.in.b.valid, _T_2039) when _T_2040 : node _T_2041 = eq(io.in.b.bits.opcode, opcode_2) node _T_2042 = asUInt(reset) node _T_2043 = eq(_T_2042, UInt<1>(0h0)) when _T_2043 : node _T_2044 = eq(_T_2041, UInt<1>(0h0)) when _T_2044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182 node _T_2045 = eq(io.in.b.bits.param, param_2) node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(_T_2045, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183 node _T_2049 = eq(io.in.b.bits.size, size_2) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184 node _T_2053 = eq(io.in.b.bits.source, source_2) node _T_2054 = asUInt(reset) node _T_2055 = eq(_T_2054, UInt<1>(0h0)) when _T_2055 : node _T_2056 = eq(_T_2053, UInt<1>(0h0)) when _T_2056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185 node _T_2057 = eq(io.in.b.bits.address, address_1) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186 node _T_2061 = and(io.in.b.ready, io.in.b.valid) node _T_2062 = and(_T_2061, b_first) when _T_2062 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2063 = eq(c_first, UInt<1>(0h0)) node _T_2064 = and(io.in.c.valid, _T_2063) when _T_2064 : node _T_2065 = eq(io.in.c.bits.opcode, opcode_3) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187 node _T_2069 = eq(io.in.c.bits.param, param_3) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188 node _T_2073 = eq(io.in.c.bits.size, size_3) node _T_2074 = asUInt(reset) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) when _T_2075 : node _T_2076 = eq(_T_2073, UInt<1>(0h0)) when _T_2076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189 node _T_2077 = eq(io.in.c.bits.source, source_3) node _T_2078 = asUInt(reset) node _T_2079 = eq(_T_2078, UInt<1>(0h0)) when _T_2079 : node _T_2080 = eq(_T_2077, UInt<1>(0h0)) when _T_2080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190 node _T_2081 = eq(io.in.c.bits.address, address_2) node _T_2082 = asUInt(reset) node _T_2083 = eq(_T_2082, UInt<1>(0h0)) when _T_2083 : node _T_2084 = eq(_T_2081, UInt<1>(0h0)) when _T_2084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191 node _T_2085 = and(io.in.c.ready, io.in.c.valid) node _T_2086 = and(_T_2085, c_first) when _T_2086 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<43> connect a_set, UInt<43>(0h0) wire a_set_wo_ready : UInt<43> connect a_set_wo_ready, UInt<43>(0h0) wire a_opcodes_set : UInt<172> connect a_opcodes_set, UInt<172>(0h0) wire a_sizes_set : UInt<172> connect a_sizes_set, UInt<172>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2087 = and(io.in.a.valid, a_first_1) node _T_2088 = and(_T_2087, UInt<1>(0h1)) when _T_2088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2089 = and(io.in.a.ready, io.in.a.valid) node _T_2090 = and(_T_2089, a_first_1) node _T_2091 = and(_T_2090, UInt<1>(0h1)) when _T_2091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2092 = dshr(inflight, io.in.a.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<43> connect d_clr, UInt<43>(0h0) wire d_clr_wo_ready : UInt<43> connect d_clr_wo_ready, UInt<43>(0h0) wire d_opcodes_clr : UInt<172> connect d_opcodes_clr, UInt<172>(0h0) wire d_sizes_clr : UInt<172> connect d_sizes_clr, UInt<172>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2098 = and(io.in.d.valid, d_first_1) node _T_2099 = and(_T_2098, UInt<1>(0h1)) node _T_2100 = eq(d_release_ack, UInt<1>(0h0)) node _T_2101 = and(_T_2099, _T_2100) when _T_2101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2102 = and(io.in.d.ready, io.in.d.valid) node _T_2103 = and(_T_2102, d_first_1) node _T_2104 = and(_T_2103, UInt<1>(0h1)) node _T_2105 = eq(d_release_ack, UInt<1>(0h0)) node _T_2106 = and(_T_2104, _T_2105) when _T_2106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2107 = and(io.in.d.valid, d_first_1) node _T_2108 = and(_T_2107, UInt<1>(0h1)) node _T_2109 = eq(d_release_ack, UInt<1>(0h0)) node _T_2110 = and(_T_2108, _T_2109) when _T_2110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2111 = dshr(inflight, io.in.d.bits.source) node _T_2112 = bits(_T_2111, 0, 0) node _T_2113 = or(_T_2112, same_cycle_resp) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194 node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195 else : node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196 node _T_2133 = eq(io.in.d.bits.size, a_size_lookup) node _T_2134 = asUInt(reset) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) when _T_2135 : node _T_2136 = eq(_T_2133, UInt<1>(0h0)) when _T_2136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197 node _T_2137 = and(io.in.d.valid, d_first_1) node _T_2138 = and(_T_2137, a_first_1) node _T_2139 = and(_T_2138, io.in.a.valid) node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2141 = and(_T_2139, _T_2140) node _T_2142 = eq(d_release_ack, UInt<1>(0h0)) node _T_2143 = and(_T_2141, _T_2142) when _T_2143 : node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2145 = or(_T_2144, io.in.a.ready) node _T_2146 = asUInt(reset) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) when _T_2147 : node _T_2148 = eq(_T_2145, UInt<1>(0h0)) when _T_2148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198 node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2150 = orr(a_set_wo_ready) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) node _T_2152 = or(_T_2149, _T_2151) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_120 node _T_2156 = orr(inflight) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2159 = or(_T_2157, _T_2158) node _T_2160 = lt(watchdog, plusarg_reader.out) node _T_2161 = or(_T_2159, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2165 = and(io.in.a.ready, io.in.a.valid) node _T_2166 = and(io.in.d.ready, io.in.d.valid) node _T_2167 = or(_T_2165, _T_2166) when _T_2167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<43> connect c_set, UInt<43>(0h0) wire c_set_wo_ready : UInt<43> connect c_set_wo_ready, UInt<43>(0h0) wire c_opcodes_set : UInt<172> connect c_opcodes_set, UInt<172>(0h0) wire c_sizes_set : UInt<172> connect c_sizes_set, UInt<172>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2168 = and(io.in.c.valid, c_first_1) node _T_2169 = bits(io.in.c.bits.opcode, 2, 2) node _T_2170 = bits(io.in.c.bits.opcode, 1, 1) node _T_2171 = and(_T_2169, _T_2170) node _T_2172 = and(_T_2168, _T_2171) when _T_2172 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2173 = and(io.in.c.ready, io.in.c.valid) node _T_2174 = and(_T_2173, c_first_1) node _T_2175 = bits(io.in.c.bits.opcode, 2, 2) node _T_2176 = bits(io.in.c.bits.opcode, 1, 1) node _T_2177 = and(_T_2175, _T_2176) node _T_2178 = and(_T_2174, _T_2177) when _T_2178 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2179 = dshr(inflight_1, io.in.c.bits.source) node _T_2180 = bits(_T_2179, 0, 0) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<43> connect d_clr_1, UInt<43>(0h0) wire d_clr_wo_ready_1 : UInt<43> connect d_clr_wo_ready_1, UInt<43>(0h0) wire d_opcodes_clr_1 : UInt<172> connect d_opcodes_clr_1, UInt<172>(0h0) wire d_sizes_clr_1 : UInt<172> connect d_sizes_clr_1, UInt<172>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2185 = and(io.in.d.valid, d_first_2) node _T_2186 = and(_T_2185, UInt<1>(0h1)) node _T_2187 = and(_T_2186, d_release_ack_1) when _T_2187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2188 = and(io.in.d.ready, io.in.d.valid) node _T_2189 = and(_T_2188, d_first_2) node _T_2190 = and(_T_2189, UInt<1>(0h1)) node _T_2191 = and(_T_2190, d_release_ack_1) when _T_2191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2192 = and(io.in.d.valid, d_first_2) node _T_2193 = and(_T_2192, UInt<1>(0h1)) node _T_2194 = and(_T_2193, d_release_ack_1) when _T_2194 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2195 = dshr(inflight_1, io.in.d.bits.source) node _T_2196 = bits(_T_2195, 0, 0) node _T_2197 = or(_T_2196, same_cycle_resp_1) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203 else : node _T_2205 = eq(io.in.d.bits.size, c_size_lookup) node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(_T_2205, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204 node _T_2209 = and(io.in.d.valid, d_first_2) node _T_2210 = and(_T_2209, c_first_1) node _T_2211 = and(_T_2210, io.in.c.valid) node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = and(_T_2213, d_release_ack_1) node _T_2215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2216 = and(_T_2214, _T_2215) when _T_2216 : node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2218 = or(_T_2217, io.in.c.ready) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(_T_2218, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205 node _T_2222 = orr(c_set_wo_ready) when _T_2222 : node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(_T_2223, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_121 node _T_2227 = orr(inflight_1) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2230 = or(_T_2228, _T_2229) node _T_2231 = lt(watchdog_1, plusarg_reader_1.out) node _T_2232 = or(_T_2230, _T_2231) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2236 = and(io.in.c.ready, io.in.c.valid) node _T_2237 = and(io.in.d.ready, io.in.d.valid) node _T_2238 = or(_T_2236, _T_2237) when _T_2238 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_2239 = and(io.in.d.ready, io.in.d.valid) node _T_2240 = and(_T_2239, d_first_3) node _T_2241 = bits(io.in.d.bits.opcode, 2, 2) node _T_2242 = bits(io.in.d.bits.opcode, 1, 1) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) node _T_2244 = and(_T_2241, _T_2243) node _T_2245 = and(_T_2240, _T_2244) when _T_2245 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2246 = dshr(inflight_2, io.in.d.bits.sink) node _T_2247 = bits(_T_2246, 0, 0) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_2252 = and(io.in.e.ready, io.in.e.valid) node _T_2253 = and(_T_2252, UInt<1>(0h1)) node _T_2254 = and(_T_2253, UInt<1>(0h1)) when _T_2254 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2255 = or(d_set, inflight_2) node _T_2256 = dshr(_T_2255, io.in.e.bits.sink) node _T_2257 = bits(_T_2256, 0, 0) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_122 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_123 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000080; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000080; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 \| _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_116 \| _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000080; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000080; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [42:0] inflight; // @[Monitor.scala:614:27] reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [171:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] a_set; // @[Monitor.scala:626:34] wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [171:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [42:0] d_clr; // @[Monitor.scala:664:34] wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [42:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [171:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [171:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [42:0] inflight_1; // @[Monitor.scala:726:35] reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] c_set; // @[Monitor.scala:738:34] wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [171:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [42:0] d_clr_1; // @[Monitor.scala:774:34] wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [42:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module RocketTile : input clock : Clock input reset : Reset output auto : { buffer_out_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, buffer_out_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt1 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_6 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_7 inst widget of TLWidthWidget8_8 connect widget.clock, clock connect widget.reset, reset inst dcache of DCache connect dcache.clock, clock connect dcache.reset, reset inst zstd_compressor of ZstdCompressor connect zstd_compressor.clock, clock connect zstd_compressor.reset, reset inst frontend of Frontend connect frontend.clock, clock connect frontend.reset, reset inst widget_1 of TLWidthWidget8_9 connect widget_1.clock, clock connect widget_1.reset, reset inst fragmenter of TLFragmenter connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget_2 of TLWidthWidget8_10 connect widget_2.clock, clock connect widget_2.reset, reset inst buffer of TLBuffer_a32d64s2k3z4u connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_1 connect buffer_1.clock, clock connect buffer_1.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire x1_tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut.d.bits.data invalidate x1_tlOtherMastersNodeOut.d.bits.denied invalidate x1_tlOtherMastersNodeOut.d.bits.sink invalidate x1_tlOtherMastersNodeOut.d.bits.source invalidate x1_tlOtherMastersNodeOut.d.bits.size invalidate x1_tlOtherMastersNodeOut.d.bits.param invalidate x1_tlOtherMastersNodeOut.d.bits.opcode invalidate x1_tlOtherMastersNodeOut.d.valid invalidate x1_tlOtherMastersNodeOut.d.ready invalidate x1_tlOtherMastersNodeOut.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut.a.bits.data invalidate x1_tlOtherMastersNodeOut.a.bits.mask invalidate x1_tlOtherMastersNodeOut.a.bits.address invalidate x1_tlOtherMastersNodeOut.a.bits.source invalidate x1_tlOtherMastersNodeOut.a.bits.size invalidate x1_tlOtherMastersNodeOut.a.bits.param invalidate x1_tlOtherMastersNodeOut.a.bits.opcode invalidate x1_tlOtherMastersNodeOut.a.valid invalidate x1_tlOtherMastersNodeOut.a.ready wire x1_tlOtherMastersNodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_1.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_1.d.bits.data invalidate x1_tlOtherMastersNodeOut_1.d.bits.denied invalidate x1_tlOtherMastersNodeOut_1.d.bits.sink invalidate x1_tlOtherMastersNodeOut_1.d.bits.source invalidate x1_tlOtherMastersNodeOut_1.d.bits.size invalidate x1_tlOtherMastersNodeOut_1.d.bits.param invalidate x1_tlOtherMastersNodeOut_1.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_1.d.valid invalidate x1_tlOtherMastersNodeOut_1.d.ready invalidate x1_tlOtherMastersNodeOut_1.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_1.a.bits.data invalidate x1_tlOtherMastersNodeOut_1.a.bits.mask invalidate x1_tlOtherMastersNodeOut_1.a.bits.address invalidate x1_tlOtherMastersNodeOut_1.a.bits.source invalidate x1_tlOtherMastersNodeOut_1.a.bits.size invalidate x1_tlOtherMastersNodeOut_1.a.bits.param invalidate x1_tlOtherMastersNodeOut_1.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_1.a.valid invalidate x1_tlOtherMastersNodeOut_1.a.ready wire x1_tlOtherMastersNodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_2.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_2.d.bits.data invalidate x1_tlOtherMastersNodeOut_2.d.bits.denied invalidate x1_tlOtherMastersNodeOut_2.d.bits.sink invalidate x1_tlOtherMastersNodeOut_2.d.bits.source invalidate x1_tlOtherMastersNodeOut_2.d.bits.size invalidate x1_tlOtherMastersNodeOut_2.d.bits.param invalidate x1_tlOtherMastersNodeOut_2.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_2.d.valid invalidate x1_tlOtherMastersNodeOut_2.d.ready invalidate x1_tlOtherMastersNodeOut_2.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_2.a.bits.data invalidate x1_tlOtherMastersNodeOut_2.a.bits.mask invalidate x1_tlOtherMastersNodeOut_2.a.bits.address invalidate x1_tlOtherMastersNodeOut_2.a.bits.source invalidate x1_tlOtherMastersNodeOut_2.a.bits.size invalidate x1_tlOtherMastersNodeOut_2.a.bits.param invalidate x1_tlOtherMastersNodeOut_2.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_2.a.valid invalidate x1_tlOtherMastersNodeOut_2.a.ready wire x1_tlOtherMastersNodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_3.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_3.d.bits.data invalidate x1_tlOtherMastersNodeOut_3.d.bits.denied invalidate x1_tlOtherMastersNodeOut_3.d.bits.sink invalidate x1_tlOtherMastersNodeOut_3.d.bits.source invalidate x1_tlOtherMastersNodeOut_3.d.bits.size invalidate x1_tlOtherMastersNodeOut_3.d.bits.param invalidate x1_tlOtherMastersNodeOut_3.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_3.d.valid invalidate x1_tlOtherMastersNodeOut_3.d.ready invalidate x1_tlOtherMastersNodeOut_3.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_3.a.bits.data invalidate x1_tlOtherMastersNodeOut_3.a.bits.mask invalidate x1_tlOtherMastersNodeOut_3.a.bits.address invalidate x1_tlOtherMastersNodeOut_3.a.bits.source invalidate x1_tlOtherMastersNodeOut_3.a.bits.size invalidate x1_tlOtherMastersNodeOut_3.a.bits.param invalidate x1_tlOtherMastersNodeOut_3.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_3.a.valid invalidate x1_tlOtherMastersNodeOut_3.a.ready wire x1_tlOtherMastersNodeOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_4.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_4.d.bits.data invalidate x1_tlOtherMastersNodeOut_4.d.bits.denied invalidate x1_tlOtherMastersNodeOut_4.d.bits.sink invalidate x1_tlOtherMastersNodeOut_4.d.bits.source invalidate x1_tlOtherMastersNodeOut_4.d.bits.size invalidate x1_tlOtherMastersNodeOut_4.d.bits.param invalidate x1_tlOtherMastersNodeOut_4.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_4.d.valid invalidate x1_tlOtherMastersNodeOut_4.d.ready invalidate x1_tlOtherMastersNodeOut_4.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_4.a.bits.data invalidate x1_tlOtherMastersNodeOut_4.a.bits.mask invalidate x1_tlOtherMastersNodeOut_4.a.bits.address invalidate x1_tlOtherMastersNodeOut_4.a.bits.source invalidate x1_tlOtherMastersNodeOut_4.a.bits.size invalidate x1_tlOtherMastersNodeOut_4.a.bits.param invalidate x1_tlOtherMastersNodeOut_4.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_4.a.valid invalidate x1_tlOtherMastersNodeOut_4.a.ready wire x1_tlOtherMastersNodeOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_5.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_5.d.bits.data invalidate x1_tlOtherMastersNodeOut_5.d.bits.denied invalidate x1_tlOtherMastersNodeOut_5.d.bits.sink invalidate x1_tlOtherMastersNodeOut_5.d.bits.source invalidate x1_tlOtherMastersNodeOut_5.d.bits.size invalidate x1_tlOtherMastersNodeOut_5.d.bits.param invalidate x1_tlOtherMastersNodeOut_5.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_5.d.valid invalidate x1_tlOtherMastersNodeOut_5.d.ready invalidate x1_tlOtherMastersNodeOut_5.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_5.a.bits.data invalidate x1_tlOtherMastersNodeOut_5.a.bits.mask invalidate x1_tlOtherMastersNodeOut_5.a.bits.address invalidate x1_tlOtherMastersNodeOut_5.a.bits.source invalidate x1_tlOtherMastersNodeOut_5.a.bits.size invalidate x1_tlOtherMastersNodeOut_5.a.bits.param invalidate x1_tlOtherMastersNodeOut_5.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_5.a.valid invalidate x1_tlOtherMastersNodeOut_5.a.ready wire x1_tlOtherMastersNodeOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_6.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_6.d.bits.data invalidate x1_tlOtherMastersNodeOut_6.d.bits.denied invalidate x1_tlOtherMastersNodeOut_6.d.bits.sink invalidate x1_tlOtherMastersNodeOut_6.d.bits.source invalidate x1_tlOtherMastersNodeOut_6.d.bits.size invalidate x1_tlOtherMastersNodeOut_6.d.bits.param invalidate x1_tlOtherMastersNodeOut_6.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_6.d.valid invalidate x1_tlOtherMastersNodeOut_6.d.ready invalidate x1_tlOtherMastersNodeOut_6.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_6.a.bits.data invalidate x1_tlOtherMastersNodeOut_6.a.bits.mask invalidate x1_tlOtherMastersNodeOut_6.a.bits.address invalidate x1_tlOtherMastersNodeOut_6.a.bits.source invalidate x1_tlOtherMastersNodeOut_6.a.bits.size invalidate x1_tlOtherMastersNodeOut_6.a.bits.param invalidate x1_tlOtherMastersNodeOut_6.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_6.a.valid invalidate x1_tlOtherMastersNodeOut_6.a.ready wire x1_tlOtherMastersNodeOut_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_7.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_7.d.bits.data invalidate x1_tlOtherMastersNodeOut_7.d.bits.denied invalidate x1_tlOtherMastersNodeOut_7.d.bits.sink invalidate x1_tlOtherMastersNodeOut_7.d.bits.source invalidate x1_tlOtherMastersNodeOut_7.d.bits.size invalidate x1_tlOtherMastersNodeOut_7.d.bits.param invalidate x1_tlOtherMastersNodeOut_7.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_7.d.valid invalidate x1_tlOtherMastersNodeOut_7.d.ready invalidate x1_tlOtherMastersNodeOut_7.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_7.a.bits.data invalidate x1_tlOtherMastersNodeOut_7.a.bits.mask invalidate x1_tlOtherMastersNodeOut_7.a.bits.address invalidate x1_tlOtherMastersNodeOut_7.a.bits.source invalidate x1_tlOtherMastersNodeOut_7.a.bits.size invalidate x1_tlOtherMastersNodeOut_7.a.bits.param invalidate x1_tlOtherMastersNodeOut_7.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_7.a.valid invalidate x1_tlOtherMastersNodeOut_7.a.ready wire x1_tlOtherMastersNodeOut_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_8.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_8.d.bits.data invalidate x1_tlOtherMastersNodeOut_8.d.bits.denied invalidate x1_tlOtherMastersNodeOut_8.d.bits.sink invalidate x1_tlOtherMastersNodeOut_8.d.bits.source invalidate x1_tlOtherMastersNodeOut_8.d.bits.size invalidate x1_tlOtherMastersNodeOut_8.d.bits.param invalidate x1_tlOtherMastersNodeOut_8.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_8.d.valid invalidate x1_tlOtherMastersNodeOut_8.d.ready invalidate x1_tlOtherMastersNodeOut_8.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_8.a.bits.data invalidate x1_tlOtherMastersNodeOut_8.a.bits.mask invalidate x1_tlOtherMastersNodeOut_8.a.bits.address invalidate x1_tlOtherMastersNodeOut_8.a.bits.source invalidate x1_tlOtherMastersNodeOut_8.a.bits.size invalidate x1_tlOtherMastersNodeOut_8.a.bits.param invalidate x1_tlOtherMastersNodeOut_8.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_8.a.valid invalidate x1_tlOtherMastersNodeOut_8.a.ready wire x1_tlOtherMastersNodeOut_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_9.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_9.d.bits.data invalidate x1_tlOtherMastersNodeOut_9.d.bits.denied invalidate x1_tlOtherMastersNodeOut_9.d.bits.sink invalidate x1_tlOtherMastersNodeOut_9.d.bits.source invalidate x1_tlOtherMastersNodeOut_9.d.bits.size invalidate x1_tlOtherMastersNodeOut_9.d.bits.param invalidate x1_tlOtherMastersNodeOut_9.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_9.d.valid invalidate x1_tlOtherMastersNodeOut_9.d.ready invalidate x1_tlOtherMastersNodeOut_9.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_9.a.bits.data invalidate x1_tlOtherMastersNodeOut_9.a.bits.mask invalidate x1_tlOtherMastersNodeOut_9.a.bits.address invalidate x1_tlOtherMastersNodeOut_9.a.bits.source invalidate x1_tlOtherMastersNodeOut_9.a.bits.size invalidate x1_tlOtherMastersNodeOut_9.a.bits.param invalidate x1_tlOtherMastersNodeOut_9.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_9.a.valid invalidate x1_tlOtherMastersNodeOut_9.a.ready wire x1_tlOtherMastersNodeOut_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_10.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_10.d.bits.data invalidate x1_tlOtherMastersNodeOut_10.d.bits.denied invalidate x1_tlOtherMastersNodeOut_10.d.bits.sink invalidate x1_tlOtherMastersNodeOut_10.d.bits.source invalidate x1_tlOtherMastersNodeOut_10.d.bits.size invalidate x1_tlOtherMastersNodeOut_10.d.bits.param invalidate x1_tlOtherMastersNodeOut_10.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_10.d.valid invalidate x1_tlOtherMastersNodeOut_10.d.ready invalidate x1_tlOtherMastersNodeOut_10.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_10.a.bits.data invalidate x1_tlOtherMastersNodeOut_10.a.bits.mask invalidate x1_tlOtherMastersNodeOut_10.a.bits.address invalidate x1_tlOtherMastersNodeOut_10.a.bits.source invalidate x1_tlOtherMastersNodeOut_10.a.bits.size invalidate x1_tlOtherMastersNodeOut_10.a.bits.param invalidate x1_tlOtherMastersNodeOut_10.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_10.a.valid invalidate x1_tlOtherMastersNodeOut_10.a.ready wire x1_tlOtherMastersNodeOut_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_11.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_11.d.bits.data invalidate x1_tlOtherMastersNodeOut_11.d.bits.denied invalidate x1_tlOtherMastersNodeOut_11.d.bits.sink invalidate x1_tlOtherMastersNodeOut_11.d.bits.source invalidate x1_tlOtherMastersNodeOut_11.d.bits.size invalidate x1_tlOtherMastersNodeOut_11.d.bits.param invalidate x1_tlOtherMastersNodeOut_11.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_11.d.valid invalidate x1_tlOtherMastersNodeOut_11.d.ready invalidate x1_tlOtherMastersNodeOut_11.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_11.a.bits.data invalidate x1_tlOtherMastersNodeOut_11.a.bits.mask invalidate x1_tlOtherMastersNodeOut_11.a.bits.address invalidate x1_tlOtherMastersNodeOut_11.a.bits.source invalidate x1_tlOtherMastersNodeOut_11.a.bits.size invalidate x1_tlOtherMastersNodeOut_11.a.bits.param invalidate x1_tlOtherMastersNodeOut_11.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_11.a.valid invalidate x1_tlOtherMastersNodeOut_11.a.ready wire x1_tlOtherMastersNodeOut_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_12.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_12.d.bits.data invalidate x1_tlOtherMastersNodeOut_12.d.bits.denied invalidate x1_tlOtherMastersNodeOut_12.d.bits.sink invalidate x1_tlOtherMastersNodeOut_12.d.bits.source invalidate x1_tlOtherMastersNodeOut_12.d.bits.size invalidate x1_tlOtherMastersNodeOut_12.d.bits.param invalidate x1_tlOtherMastersNodeOut_12.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_12.d.valid invalidate x1_tlOtherMastersNodeOut_12.d.ready invalidate x1_tlOtherMastersNodeOut_12.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_12.a.bits.data invalidate x1_tlOtherMastersNodeOut_12.a.bits.mask invalidate x1_tlOtherMastersNodeOut_12.a.bits.address invalidate x1_tlOtherMastersNodeOut_12.a.bits.source invalidate x1_tlOtherMastersNodeOut_12.a.bits.size invalidate x1_tlOtherMastersNodeOut_12.a.bits.param invalidate x1_tlOtherMastersNodeOut_12.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_12.a.valid invalidate x1_tlOtherMastersNodeOut_12.a.ready wire x1_tlOtherMastersNodeOut_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_13.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_13.d.bits.data invalidate x1_tlOtherMastersNodeOut_13.d.bits.denied invalidate x1_tlOtherMastersNodeOut_13.d.bits.sink invalidate x1_tlOtherMastersNodeOut_13.d.bits.source invalidate x1_tlOtherMastersNodeOut_13.d.bits.size invalidate x1_tlOtherMastersNodeOut_13.d.bits.param invalidate x1_tlOtherMastersNodeOut_13.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_13.d.valid invalidate x1_tlOtherMastersNodeOut_13.d.ready invalidate x1_tlOtherMastersNodeOut_13.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_13.a.bits.data invalidate x1_tlOtherMastersNodeOut_13.a.bits.mask invalidate x1_tlOtherMastersNodeOut_13.a.bits.address invalidate x1_tlOtherMastersNodeOut_13.a.bits.source invalidate x1_tlOtherMastersNodeOut_13.a.bits.size invalidate x1_tlOtherMastersNodeOut_13.a.bits.param invalidate x1_tlOtherMastersNodeOut_13.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_13.a.valid invalidate x1_tlOtherMastersNodeOut_13.a.ready wire x1_tlOtherMastersNodeOut_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_14.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_14.d.bits.data invalidate x1_tlOtherMastersNodeOut_14.d.bits.denied invalidate x1_tlOtherMastersNodeOut_14.d.bits.sink invalidate x1_tlOtherMastersNodeOut_14.d.bits.source invalidate x1_tlOtherMastersNodeOut_14.d.bits.size invalidate x1_tlOtherMastersNodeOut_14.d.bits.param invalidate x1_tlOtherMastersNodeOut_14.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_14.d.valid invalidate x1_tlOtherMastersNodeOut_14.d.ready invalidate x1_tlOtherMastersNodeOut_14.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_14.a.bits.data invalidate x1_tlOtherMastersNodeOut_14.a.bits.mask invalidate x1_tlOtherMastersNodeOut_14.a.bits.address invalidate x1_tlOtherMastersNodeOut_14.a.bits.source invalidate x1_tlOtherMastersNodeOut_14.a.bits.size invalidate x1_tlOtherMastersNodeOut_14.a.bits.param invalidate x1_tlOtherMastersNodeOut_14.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_14.a.valid invalidate x1_tlOtherMastersNodeOut_14.a.ready wire x1_tlOtherMastersNodeOut_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_15.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_15.d.bits.data invalidate x1_tlOtherMastersNodeOut_15.d.bits.denied invalidate x1_tlOtherMastersNodeOut_15.d.bits.sink invalidate x1_tlOtherMastersNodeOut_15.d.bits.source invalidate x1_tlOtherMastersNodeOut_15.d.bits.size invalidate x1_tlOtherMastersNodeOut_15.d.bits.param invalidate x1_tlOtherMastersNodeOut_15.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_15.d.valid invalidate x1_tlOtherMastersNodeOut_15.d.ready invalidate x1_tlOtherMastersNodeOut_15.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_15.a.bits.data invalidate x1_tlOtherMastersNodeOut_15.a.bits.mask invalidate x1_tlOtherMastersNodeOut_15.a.bits.address invalidate x1_tlOtherMastersNodeOut_15.a.bits.source invalidate x1_tlOtherMastersNodeOut_15.a.bits.size invalidate x1_tlOtherMastersNodeOut_15.a.bits.param invalidate x1_tlOtherMastersNodeOut_15.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_15.a.valid invalidate x1_tlOtherMastersNodeOut_15.a.ready wire x1_tlOtherMastersNodeOut_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_16.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_16.d.bits.data invalidate x1_tlOtherMastersNodeOut_16.d.bits.denied invalidate x1_tlOtherMastersNodeOut_16.d.bits.sink invalidate x1_tlOtherMastersNodeOut_16.d.bits.source invalidate x1_tlOtherMastersNodeOut_16.d.bits.size invalidate x1_tlOtherMastersNodeOut_16.d.bits.param invalidate x1_tlOtherMastersNodeOut_16.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_16.d.valid invalidate x1_tlOtherMastersNodeOut_16.d.ready invalidate x1_tlOtherMastersNodeOut_16.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_16.a.bits.data invalidate x1_tlOtherMastersNodeOut_16.a.bits.mask invalidate x1_tlOtherMastersNodeOut_16.a.bits.address invalidate x1_tlOtherMastersNodeOut_16.a.bits.source invalidate x1_tlOtherMastersNodeOut_16.a.bits.size invalidate x1_tlOtherMastersNodeOut_16.a.bits.param invalidate x1_tlOtherMastersNodeOut_16.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_16.a.valid invalidate x1_tlOtherMastersNodeOut_16.a.ready wire x1_tlOtherMastersNodeOut_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_tlOtherMastersNodeOut_17.e.bits.sink invalidate x1_tlOtherMastersNodeOut_17.e.valid invalidate x1_tlOtherMastersNodeOut_17.e.ready invalidate x1_tlOtherMastersNodeOut_17.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.d.bits.data invalidate x1_tlOtherMastersNodeOut_17.d.bits.denied invalidate x1_tlOtherMastersNodeOut_17.d.bits.sink invalidate x1_tlOtherMastersNodeOut_17.d.bits.source invalidate x1_tlOtherMastersNodeOut_17.d.bits.size invalidate x1_tlOtherMastersNodeOut_17.d.bits.param invalidate x1_tlOtherMastersNodeOut_17.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.d.valid invalidate x1_tlOtherMastersNodeOut_17.d.ready invalidate x1_tlOtherMastersNodeOut_17.c.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.c.bits.data invalidate x1_tlOtherMastersNodeOut_17.c.bits.address invalidate x1_tlOtherMastersNodeOut_17.c.bits.source invalidate x1_tlOtherMastersNodeOut_17.c.bits.size invalidate x1_tlOtherMastersNodeOut_17.c.bits.param invalidate x1_tlOtherMastersNodeOut_17.c.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.c.valid invalidate x1_tlOtherMastersNodeOut_17.c.ready invalidate x1_tlOtherMastersNodeOut_17.b.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.b.bits.data invalidate x1_tlOtherMastersNodeOut_17.b.bits.mask invalidate x1_tlOtherMastersNodeOut_17.b.bits.address invalidate x1_tlOtherMastersNodeOut_17.b.bits.source invalidate x1_tlOtherMastersNodeOut_17.b.bits.size invalidate x1_tlOtherMastersNodeOut_17.b.bits.param invalidate x1_tlOtherMastersNodeOut_17.b.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.b.valid invalidate x1_tlOtherMastersNodeOut_17.b.ready invalidate x1_tlOtherMastersNodeOut_17.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.a.bits.data invalidate x1_tlOtherMastersNodeOut_17.a.bits.mask invalidate x1_tlOtherMastersNodeOut_17.a.bits.address invalidate x1_tlOtherMastersNodeOut_17.a.bits.source invalidate x1_tlOtherMastersNodeOut_17.a.bits.size invalidate x1_tlOtherMastersNodeOut_17.a.bits.param invalidate x1_tlOtherMastersNodeOut_17.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.a.valid invalidate x1_tlOtherMastersNodeOut_17.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready wire x1_tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn.d.bits.data invalidate x1_tlOtherMastersNodeIn.d.bits.denied invalidate x1_tlOtherMastersNodeIn.d.bits.sink invalidate x1_tlOtherMastersNodeIn.d.bits.source invalidate x1_tlOtherMastersNodeIn.d.bits.size invalidate x1_tlOtherMastersNodeIn.d.bits.param invalidate x1_tlOtherMastersNodeIn.d.bits.opcode invalidate x1_tlOtherMastersNodeIn.d.valid invalidate x1_tlOtherMastersNodeIn.d.ready invalidate x1_tlOtherMastersNodeIn.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn.a.bits.data invalidate x1_tlOtherMastersNodeIn.a.bits.mask invalidate x1_tlOtherMastersNodeIn.a.bits.address invalidate x1_tlOtherMastersNodeIn.a.bits.source invalidate x1_tlOtherMastersNodeIn.a.bits.size invalidate x1_tlOtherMastersNodeIn.a.bits.param invalidate x1_tlOtherMastersNodeIn.a.bits.opcode invalidate x1_tlOtherMastersNodeIn.a.valid invalidate x1_tlOtherMastersNodeIn.a.ready wire x1_tlOtherMastersNodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_1.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_1.d.bits.data invalidate x1_tlOtherMastersNodeIn_1.d.bits.denied invalidate x1_tlOtherMastersNodeIn_1.d.bits.sink invalidate x1_tlOtherMastersNodeIn_1.d.bits.source invalidate x1_tlOtherMastersNodeIn_1.d.bits.size invalidate x1_tlOtherMastersNodeIn_1.d.bits.param invalidate x1_tlOtherMastersNodeIn_1.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_1.d.valid invalidate x1_tlOtherMastersNodeIn_1.d.ready invalidate x1_tlOtherMastersNodeIn_1.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_1.a.bits.data invalidate x1_tlOtherMastersNodeIn_1.a.bits.mask invalidate x1_tlOtherMastersNodeIn_1.a.bits.address invalidate x1_tlOtherMastersNodeIn_1.a.bits.source invalidate x1_tlOtherMastersNodeIn_1.a.bits.size invalidate x1_tlOtherMastersNodeIn_1.a.bits.param invalidate x1_tlOtherMastersNodeIn_1.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_1.a.valid invalidate x1_tlOtherMastersNodeIn_1.a.ready wire x1_tlOtherMastersNodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_2.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_2.d.bits.data invalidate x1_tlOtherMastersNodeIn_2.d.bits.denied invalidate x1_tlOtherMastersNodeIn_2.d.bits.sink invalidate x1_tlOtherMastersNodeIn_2.d.bits.source invalidate x1_tlOtherMastersNodeIn_2.d.bits.size invalidate x1_tlOtherMastersNodeIn_2.d.bits.param invalidate x1_tlOtherMastersNodeIn_2.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_2.d.valid invalidate x1_tlOtherMastersNodeIn_2.d.ready invalidate x1_tlOtherMastersNodeIn_2.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_2.a.bits.data invalidate x1_tlOtherMastersNodeIn_2.a.bits.mask invalidate x1_tlOtherMastersNodeIn_2.a.bits.address invalidate x1_tlOtherMastersNodeIn_2.a.bits.source invalidate x1_tlOtherMastersNodeIn_2.a.bits.size invalidate x1_tlOtherMastersNodeIn_2.a.bits.param invalidate x1_tlOtherMastersNodeIn_2.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_2.a.valid invalidate x1_tlOtherMastersNodeIn_2.a.ready wire x1_tlOtherMastersNodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_3.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_3.d.bits.data invalidate x1_tlOtherMastersNodeIn_3.d.bits.denied invalidate x1_tlOtherMastersNodeIn_3.d.bits.sink invalidate x1_tlOtherMastersNodeIn_3.d.bits.source invalidate x1_tlOtherMastersNodeIn_3.d.bits.size invalidate x1_tlOtherMastersNodeIn_3.d.bits.param invalidate x1_tlOtherMastersNodeIn_3.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_3.d.valid invalidate x1_tlOtherMastersNodeIn_3.d.ready invalidate x1_tlOtherMastersNodeIn_3.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_3.a.bits.data invalidate x1_tlOtherMastersNodeIn_3.a.bits.mask invalidate x1_tlOtherMastersNodeIn_3.a.bits.address invalidate x1_tlOtherMastersNodeIn_3.a.bits.source invalidate x1_tlOtherMastersNodeIn_3.a.bits.size invalidate x1_tlOtherMastersNodeIn_3.a.bits.param invalidate x1_tlOtherMastersNodeIn_3.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_3.a.valid invalidate x1_tlOtherMastersNodeIn_3.a.ready wire x1_tlOtherMastersNodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_4.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_4.d.bits.data invalidate x1_tlOtherMastersNodeIn_4.d.bits.denied invalidate x1_tlOtherMastersNodeIn_4.d.bits.sink invalidate x1_tlOtherMastersNodeIn_4.d.bits.source invalidate x1_tlOtherMastersNodeIn_4.d.bits.size invalidate x1_tlOtherMastersNodeIn_4.d.bits.param invalidate x1_tlOtherMastersNodeIn_4.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_4.d.valid invalidate x1_tlOtherMastersNodeIn_4.d.ready invalidate x1_tlOtherMastersNodeIn_4.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_4.a.bits.data invalidate x1_tlOtherMastersNodeIn_4.a.bits.mask invalidate x1_tlOtherMastersNodeIn_4.a.bits.address invalidate x1_tlOtherMastersNodeIn_4.a.bits.source invalidate x1_tlOtherMastersNodeIn_4.a.bits.size invalidate x1_tlOtherMastersNodeIn_4.a.bits.param invalidate x1_tlOtherMastersNodeIn_4.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_4.a.valid invalidate x1_tlOtherMastersNodeIn_4.a.ready wire x1_tlOtherMastersNodeIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_5.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_5.d.bits.data invalidate x1_tlOtherMastersNodeIn_5.d.bits.denied invalidate x1_tlOtherMastersNodeIn_5.d.bits.sink invalidate x1_tlOtherMastersNodeIn_5.d.bits.source invalidate x1_tlOtherMastersNodeIn_5.d.bits.size invalidate x1_tlOtherMastersNodeIn_5.d.bits.param invalidate x1_tlOtherMastersNodeIn_5.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_5.d.valid invalidate x1_tlOtherMastersNodeIn_5.d.ready invalidate x1_tlOtherMastersNodeIn_5.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_5.a.bits.data invalidate x1_tlOtherMastersNodeIn_5.a.bits.mask invalidate x1_tlOtherMastersNodeIn_5.a.bits.address invalidate x1_tlOtherMastersNodeIn_5.a.bits.source invalidate x1_tlOtherMastersNodeIn_5.a.bits.size invalidate x1_tlOtherMastersNodeIn_5.a.bits.param invalidate x1_tlOtherMastersNodeIn_5.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_5.a.valid invalidate x1_tlOtherMastersNodeIn_5.a.ready wire x1_tlOtherMastersNodeIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_6.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_6.d.bits.data invalidate x1_tlOtherMastersNodeIn_6.d.bits.denied invalidate x1_tlOtherMastersNodeIn_6.d.bits.sink invalidate x1_tlOtherMastersNodeIn_6.d.bits.source invalidate x1_tlOtherMastersNodeIn_6.d.bits.size invalidate x1_tlOtherMastersNodeIn_6.d.bits.param invalidate x1_tlOtherMastersNodeIn_6.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_6.d.valid invalidate x1_tlOtherMastersNodeIn_6.d.ready invalidate x1_tlOtherMastersNodeIn_6.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_6.a.bits.data invalidate x1_tlOtherMastersNodeIn_6.a.bits.mask invalidate x1_tlOtherMastersNodeIn_6.a.bits.address invalidate x1_tlOtherMastersNodeIn_6.a.bits.source invalidate x1_tlOtherMastersNodeIn_6.a.bits.size invalidate x1_tlOtherMastersNodeIn_6.a.bits.param invalidate x1_tlOtherMastersNodeIn_6.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_6.a.valid invalidate x1_tlOtherMastersNodeIn_6.a.ready wire x1_tlOtherMastersNodeIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_7.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_7.d.bits.data invalidate x1_tlOtherMastersNodeIn_7.d.bits.denied invalidate x1_tlOtherMastersNodeIn_7.d.bits.sink invalidate x1_tlOtherMastersNodeIn_7.d.bits.source invalidate x1_tlOtherMastersNodeIn_7.d.bits.size invalidate x1_tlOtherMastersNodeIn_7.d.bits.param invalidate x1_tlOtherMastersNodeIn_7.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_7.d.valid invalidate x1_tlOtherMastersNodeIn_7.d.ready invalidate x1_tlOtherMastersNodeIn_7.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_7.a.bits.data invalidate x1_tlOtherMastersNodeIn_7.a.bits.mask invalidate x1_tlOtherMastersNodeIn_7.a.bits.address invalidate x1_tlOtherMastersNodeIn_7.a.bits.source invalidate x1_tlOtherMastersNodeIn_7.a.bits.size invalidate x1_tlOtherMastersNodeIn_7.a.bits.param invalidate x1_tlOtherMastersNodeIn_7.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_7.a.valid invalidate x1_tlOtherMastersNodeIn_7.a.ready wire x1_tlOtherMastersNodeIn_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_8.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_8.d.bits.data invalidate x1_tlOtherMastersNodeIn_8.d.bits.denied invalidate x1_tlOtherMastersNodeIn_8.d.bits.sink invalidate x1_tlOtherMastersNodeIn_8.d.bits.source invalidate x1_tlOtherMastersNodeIn_8.d.bits.size invalidate x1_tlOtherMastersNodeIn_8.d.bits.param invalidate x1_tlOtherMastersNodeIn_8.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_8.d.valid invalidate x1_tlOtherMastersNodeIn_8.d.ready invalidate x1_tlOtherMastersNodeIn_8.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_8.a.bits.data invalidate x1_tlOtherMastersNodeIn_8.a.bits.mask invalidate x1_tlOtherMastersNodeIn_8.a.bits.address invalidate x1_tlOtherMastersNodeIn_8.a.bits.source invalidate x1_tlOtherMastersNodeIn_8.a.bits.size invalidate x1_tlOtherMastersNodeIn_8.a.bits.param invalidate x1_tlOtherMastersNodeIn_8.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_8.a.valid invalidate x1_tlOtherMastersNodeIn_8.a.ready wire x1_tlOtherMastersNodeIn_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_9.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_9.d.bits.data invalidate x1_tlOtherMastersNodeIn_9.d.bits.denied invalidate x1_tlOtherMastersNodeIn_9.d.bits.sink invalidate x1_tlOtherMastersNodeIn_9.d.bits.source invalidate x1_tlOtherMastersNodeIn_9.d.bits.size invalidate x1_tlOtherMastersNodeIn_9.d.bits.param invalidate x1_tlOtherMastersNodeIn_9.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_9.d.valid invalidate x1_tlOtherMastersNodeIn_9.d.ready invalidate x1_tlOtherMastersNodeIn_9.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_9.a.bits.data invalidate x1_tlOtherMastersNodeIn_9.a.bits.mask invalidate x1_tlOtherMastersNodeIn_9.a.bits.address invalidate x1_tlOtherMastersNodeIn_9.a.bits.source invalidate x1_tlOtherMastersNodeIn_9.a.bits.size invalidate x1_tlOtherMastersNodeIn_9.a.bits.param invalidate x1_tlOtherMastersNodeIn_9.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_9.a.valid invalidate x1_tlOtherMastersNodeIn_9.a.ready wire x1_tlOtherMastersNodeIn_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_10.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_10.d.bits.data invalidate x1_tlOtherMastersNodeIn_10.d.bits.denied invalidate x1_tlOtherMastersNodeIn_10.d.bits.sink invalidate x1_tlOtherMastersNodeIn_10.d.bits.source invalidate x1_tlOtherMastersNodeIn_10.d.bits.size invalidate x1_tlOtherMastersNodeIn_10.d.bits.param invalidate x1_tlOtherMastersNodeIn_10.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_10.d.valid invalidate x1_tlOtherMastersNodeIn_10.d.ready invalidate x1_tlOtherMastersNodeIn_10.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_10.a.bits.data invalidate x1_tlOtherMastersNodeIn_10.a.bits.mask invalidate x1_tlOtherMastersNodeIn_10.a.bits.address invalidate x1_tlOtherMastersNodeIn_10.a.bits.source invalidate x1_tlOtherMastersNodeIn_10.a.bits.size invalidate x1_tlOtherMastersNodeIn_10.a.bits.param invalidate x1_tlOtherMastersNodeIn_10.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_10.a.valid invalidate x1_tlOtherMastersNodeIn_10.a.ready wire x1_tlOtherMastersNodeIn_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_11.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_11.d.bits.data invalidate x1_tlOtherMastersNodeIn_11.d.bits.denied invalidate x1_tlOtherMastersNodeIn_11.d.bits.sink invalidate x1_tlOtherMastersNodeIn_11.d.bits.source invalidate x1_tlOtherMastersNodeIn_11.d.bits.size invalidate x1_tlOtherMastersNodeIn_11.d.bits.param invalidate x1_tlOtherMastersNodeIn_11.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_11.d.valid invalidate x1_tlOtherMastersNodeIn_11.d.ready invalidate x1_tlOtherMastersNodeIn_11.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_11.a.bits.data invalidate x1_tlOtherMastersNodeIn_11.a.bits.mask invalidate x1_tlOtherMastersNodeIn_11.a.bits.address invalidate x1_tlOtherMastersNodeIn_11.a.bits.source invalidate x1_tlOtherMastersNodeIn_11.a.bits.size invalidate x1_tlOtherMastersNodeIn_11.a.bits.param invalidate x1_tlOtherMastersNodeIn_11.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_11.a.valid invalidate x1_tlOtherMastersNodeIn_11.a.ready wire x1_tlOtherMastersNodeIn_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_12.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_12.d.bits.data invalidate x1_tlOtherMastersNodeIn_12.d.bits.denied invalidate x1_tlOtherMastersNodeIn_12.d.bits.sink invalidate x1_tlOtherMastersNodeIn_12.d.bits.source invalidate x1_tlOtherMastersNodeIn_12.d.bits.size invalidate x1_tlOtherMastersNodeIn_12.d.bits.param invalidate x1_tlOtherMastersNodeIn_12.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_12.d.valid invalidate x1_tlOtherMastersNodeIn_12.d.ready invalidate x1_tlOtherMastersNodeIn_12.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_12.a.bits.data invalidate x1_tlOtherMastersNodeIn_12.a.bits.mask invalidate x1_tlOtherMastersNodeIn_12.a.bits.address invalidate x1_tlOtherMastersNodeIn_12.a.bits.source invalidate x1_tlOtherMastersNodeIn_12.a.bits.size invalidate x1_tlOtherMastersNodeIn_12.a.bits.param invalidate x1_tlOtherMastersNodeIn_12.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_12.a.valid invalidate x1_tlOtherMastersNodeIn_12.a.ready wire x1_tlOtherMastersNodeIn_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_13.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_13.d.bits.data invalidate x1_tlOtherMastersNodeIn_13.d.bits.denied invalidate x1_tlOtherMastersNodeIn_13.d.bits.sink invalidate x1_tlOtherMastersNodeIn_13.d.bits.source invalidate x1_tlOtherMastersNodeIn_13.d.bits.size invalidate x1_tlOtherMastersNodeIn_13.d.bits.param invalidate x1_tlOtherMastersNodeIn_13.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_13.d.valid invalidate x1_tlOtherMastersNodeIn_13.d.ready invalidate x1_tlOtherMastersNodeIn_13.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_13.a.bits.data invalidate x1_tlOtherMastersNodeIn_13.a.bits.mask invalidate x1_tlOtherMastersNodeIn_13.a.bits.address invalidate x1_tlOtherMastersNodeIn_13.a.bits.source invalidate x1_tlOtherMastersNodeIn_13.a.bits.size invalidate x1_tlOtherMastersNodeIn_13.a.bits.param invalidate x1_tlOtherMastersNodeIn_13.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_13.a.valid invalidate x1_tlOtherMastersNodeIn_13.a.ready wire x1_tlOtherMastersNodeIn_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_14.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_14.d.bits.data invalidate x1_tlOtherMastersNodeIn_14.d.bits.denied invalidate x1_tlOtherMastersNodeIn_14.d.bits.sink invalidate x1_tlOtherMastersNodeIn_14.d.bits.source invalidate x1_tlOtherMastersNodeIn_14.d.bits.size invalidate x1_tlOtherMastersNodeIn_14.d.bits.param invalidate x1_tlOtherMastersNodeIn_14.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_14.d.valid invalidate x1_tlOtherMastersNodeIn_14.d.ready invalidate x1_tlOtherMastersNodeIn_14.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_14.a.bits.data invalidate x1_tlOtherMastersNodeIn_14.a.bits.mask invalidate x1_tlOtherMastersNodeIn_14.a.bits.address invalidate x1_tlOtherMastersNodeIn_14.a.bits.source invalidate x1_tlOtherMastersNodeIn_14.a.bits.size invalidate x1_tlOtherMastersNodeIn_14.a.bits.param invalidate x1_tlOtherMastersNodeIn_14.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_14.a.valid invalidate x1_tlOtherMastersNodeIn_14.a.ready wire x1_tlOtherMastersNodeIn_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_15.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_15.d.bits.data invalidate x1_tlOtherMastersNodeIn_15.d.bits.denied invalidate x1_tlOtherMastersNodeIn_15.d.bits.sink invalidate x1_tlOtherMastersNodeIn_15.d.bits.source invalidate x1_tlOtherMastersNodeIn_15.d.bits.size invalidate x1_tlOtherMastersNodeIn_15.d.bits.param invalidate x1_tlOtherMastersNodeIn_15.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_15.d.valid invalidate x1_tlOtherMastersNodeIn_15.d.ready invalidate x1_tlOtherMastersNodeIn_15.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_15.a.bits.data invalidate x1_tlOtherMastersNodeIn_15.a.bits.mask invalidate x1_tlOtherMastersNodeIn_15.a.bits.address invalidate x1_tlOtherMastersNodeIn_15.a.bits.source invalidate x1_tlOtherMastersNodeIn_15.a.bits.size invalidate x1_tlOtherMastersNodeIn_15.a.bits.param invalidate x1_tlOtherMastersNodeIn_15.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_15.a.valid invalidate x1_tlOtherMastersNodeIn_15.a.ready wire x1_tlOtherMastersNodeIn_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_16.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_16.d.bits.data invalidate x1_tlOtherMastersNodeIn_16.d.bits.denied invalidate x1_tlOtherMastersNodeIn_16.d.bits.sink invalidate x1_tlOtherMastersNodeIn_16.d.bits.source invalidate x1_tlOtherMastersNodeIn_16.d.bits.size invalidate x1_tlOtherMastersNodeIn_16.d.bits.param invalidate x1_tlOtherMastersNodeIn_16.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_16.d.valid invalidate x1_tlOtherMastersNodeIn_16.d.ready invalidate x1_tlOtherMastersNodeIn_16.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_16.a.bits.data invalidate x1_tlOtherMastersNodeIn_16.a.bits.mask invalidate x1_tlOtherMastersNodeIn_16.a.bits.address invalidate x1_tlOtherMastersNodeIn_16.a.bits.source invalidate x1_tlOtherMastersNodeIn_16.a.bits.size invalidate x1_tlOtherMastersNodeIn_16.a.bits.param invalidate x1_tlOtherMastersNodeIn_16.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_16.a.valid invalidate x1_tlOtherMastersNodeIn_16.a.ready wire x1_tlOtherMastersNodeIn_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_tlOtherMastersNodeIn_17.e.bits.sink invalidate x1_tlOtherMastersNodeIn_17.e.valid invalidate x1_tlOtherMastersNodeIn_17.e.ready invalidate x1_tlOtherMastersNodeIn_17.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.d.bits.data invalidate x1_tlOtherMastersNodeIn_17.d.bits.denied invalidate x1_tlOtherMastersNodeIn_17.d.bits.sink invalidate x1_tlOtherMastersNodeIn_17.d.bits.source invalidate x1_tlOtherMastersNodeIn_17.d.bits.size invalidate x1_tlOtherMastersNodeIn_17.d.bits.param invalidate x1_tlOtherMastersNodeIn_17.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.d.valid invalidate x1_tlOtherMastersNodeIn_17.d.ready invalidate x1_tlOtherMastersNodeIn_17.c.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.c.bits.data invalidate x1_tlOtherMastersNodeIn_17.c.bits.address invalidate x1_tlOtherMastersNodeIn_17.c.bits.source invalidate x1_tlOtherMastersNodeIn_17.c.bits.size invalidate x1_tlOtherMastersNodeIn_17.c.bits.param invalidate x1_tlOtherMastersNodeIn_17.c.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.c.valid invalidate x1_tlOtherMastersNodeIn_17.c.ready invalidate x1_tlOtherMastersNodeIn_17.b.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.b.bits.data invalidate x1_tlOtherMastersNodeIn_17.b.bits.mask invalidate x1_tlOtherMastersNodeIn_17.b.bits.address invalidate x1_tlOtherMastersNodeIn_17.b.bits.source invalidate x1_tlOtherMastersNodeIn_17.b.bits.size invalidate x1_tlOtherMastersNodeIn_17.b.bits.param invalidate x1_tlOtherMastersNodeIn_17.b.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.b.valid invalidate x1_tlOtherMastersNodeIn_17.b.ready invalidate x1_tlOtherMastersNodeIn_17.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.a.bits.data invalidate x1_tlOtherMastersNodeIn_17.a.bits.mask invalidate x1_tlOtherMastersNodeIn_17.a.bits.address invalidate x1_tlOtherMastersNodeIn_17.a.bits.source invalidate x1_tlOtherMastersNodeIn_17.a.bits.size invalidate x1_tlOtherMastersNodeIn_17.a.bits.param invalidate x1_tlOtherMastersNodeIn_17.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.a.valid invalidate x1_tlOtherMastersNodeIn_17.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn connect x1_tlOtherMastersNodeOut, x1_tlOtherMastersNodeIn connect x1_tlOtherMastersNodeOut_1, x1_tlOtherMastersNodeIn_1 connect x1_tlOtherMastersNodeOut_2, x1_tlOtherMastersNodeIn_2 connect x1_tlOtherMastersNodeOut_3, x1_tlOtherMastersNodeIn_3 connect x1_tlOtherMastersNodeOut_4, x1_tlOtherMastersNodeIn_4 connect x1_tlOtherMastersNodeOut_5, x1_tlOtherMastersNodeIn_5 connect x1_tlOtherMastersNodeOut_6, x1_tlOtherMastersNodeIn_6 connect x1_tlOtherMastersNodeOut_7, x1_tlOtherMastersNodeIn_7 connect x1_tlOtherMastersNodeOut_8, x1_tlOtherMastersNodeIn_8 connect x1_tlOtherMastersNodeOut_9, x1_tlOtherMastersNodeIn_9 connect x1_tlOtherMastersNodeOut_10, x1_tlOtherMastersNodeIn_10 connect x1_tlOtherMastersNodeOut_11, x1_tlOtherMastersNodeIn_11 connect x1_tlOtherMastersNodeOut_12, x1_tlOtherMastersNodeIn_12 connect x1_tlOtherMastersNodeOut_13, x1_tlOtherMastersNodeIn_13 connect x1_tlOtherMastersNodeOut_14, x1_tlOtherMastersNodeIn_14 connect x1_tlOtherMastersNodeOut_15, x1_tlOtherMastersNodeIn_15 connect x1_tlOtherMastersNodeOut_16, x1_tlOtherMastersNodeIn_16 connect x1_tlOtherMastersNodeOut_17, x1_tlOtherMastersNodeIn_17 wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] connect buffer.auto.in_0, tlOtherMastersNodeOut connect buffer.auto.in_1, x1_tlOtherMastersNodeOut connect buffer.auto.in_2, x1_tlOtherMastersNodeOut_1 connect buffer.auto.in_3, x1_tlOtherMastersNodeOut_2 connect buffer.auto.in_4, x1_tlOtherMastersNodeOut_3 connect buffer.auto.in_5, x1_tlOtherMastersNodeOut_4 connect buffer.auto.in_6, x1_tlOtherMastersNodeOut_5 connect buffer.auto.in_7, x1_tlOtherMastersNodeOut_6 connect buffer.auto.in_8, x1_tlOtherMastersNodeOut_7 connect buffer.auto.in_9, x1_tlOtherMastersNodeOut_8 connect buffer.auto.in_10, x1_tlOtherMastersNodeOut_9 connect buffer.auto.in_11, x1_tlOtherMastersNodeOut_10 connect buffer.auto.in_12, x1_tlOtherMastersNodeOut_11 connect buffer.auto.in_13, x1_tlOtherMastersNodeOut_12 connect buffer.auto.in_14, x1_tlOtherMastersNodeOut_13 connect buffer.auto.in_15, x1_tlOtherMastersNodeOut_14 connect buffer.auto.in_16, x1_tlOtherMastersNodeOut_15 connect buffer.auto.in_17, x1_tlOtherMastersNodeOut_16 connect buffer.auto.in_18, x1_tlOtherMastersNodeOut_17 connect x1_tlOtherMastersNodeIn_17.e.bits, tlMasterXbar.auto.anon_out.e.bits connect x1_tlOtherMastersNodeIn_17.e.valid, tlMasterXbar.auto.anon_out.e.valid connect tlMasterXbar.auto.anon_out.e.ready, x1_tlOtherMastersNodeIn_17.e.ready connect tlMasterXbar.auto.anon_out.d, x1_tlOtherMastersNodeIn_17.d connect x1_tlOtherMastersNodeIn_17.c.bits, tlMasterXbar.auto.anon_out.c.bits connect x1_tlOtherMastersNodeIn_17.c.valid, tlMasterXbar.auto.anon_out.c.valid connect tlMasterXbar.auto.anon_out.c.ready, x1_tlOtherMastersNodeIn_17.c.ready connect tlMasterXbar.auto.anon_out.b, x1_tlOtherMastersNodeIn_17.b connect x1_tlOtherMastersNodeIn_17.a.bits, tlMasterXbar.auto.anon_out.a.bits connect x1_tlOtherMastersNodeIn_17.a.valid, tlMasterXbar.auto.anon_out.a.valid connect tlMasterXbar.auto.anon_out.a.ready, x1_tlOtherMastersNodeIn_17.a.ready connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.out connect zstd_compressor.auto.tl_out_0.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.a.bits, zstd_compressor.auto.tl_out_0.a.bits connect tlOtherMastersNodeIn.a.valid, zstd_compressor.auto.tl_out_0.a.valid connect zstd_compressor.auto.tl_out_0.a.ready, tlOtherMastersNodeIn.a.ready connect zstd_compressor.auto.tl_out_1.d, x1_tlOtherMastersNodeIn.d connect x1_tlOtherMastersNodeIn.a.bits, zstd_compressor.auto.tl_out_1.a.bits connect x1_tlOtherMastersNodeIn.a.valid, zstd_compressor.auto.tl_out_1.a.valid connect zstd_compressor.auto.tl_out_1.a.ready, x1_tlOtherMastersNodeIn.a.ready connect zstd_compressor.auto.tl_out_2.d, x1_tlOtherMastersNodeIn_1.d connect x1_tlOtherMastersNodeIn_1.a.bits, zstd_compressor.auto.tl_out_2.a.bits connect x1_tlOtherMastersNodeIn_1.a.valid, zstd_compressor.auto.tl_out_2.a.valid connect zstd_compressor.auto.tl_out_2.a.ready, x1_tlOtherMastersNodeIn_1.a.ready connect zstd_compressor.auto.tl_out_3.d, x1_tlOtherMastersNodeIn_2.d connect x1_tlOtherMastersNodeIn_2.a.bits, zstd_compressor.auto.tl_out_3.a.bits connect x1_tlOtherMastersNodeIn_2.a.valid, zstd_compressor.auto.tl_out_3.a.valid connect zstd_compressor.auto.tl_out_3.a.ready, x1_tlOtherMastersNodeIn_2.a.ready connect zstd_compressor.auto.tl_out_4.d, x1_tlOtherMastersNodeIn_3.d connect x1_tlOtherMastersNodeIn_3.a.bits, zstd_compressor.auto.tl_out_4.a.bits connect x1_tlOtherMastersNodeIn_3.a.valid, zstd_compressor.auto.tl_out_4.a.valid connect zstd_compressor.auto.tl_out_4.a.ready, x1_tlOtherMastersNodeIn_3.a.ready connect zstd_compressor.auto.tl_out_5.d, x1_tlOtherMastersNodeIn_4.d connect x1_tlOtherMastersNodeIn_4.a.bits, zstd_compressor.auto.tl_out_5.a.bits connect x1_tlOtherMastersNodeIn_4.a.valid, zstd_compressor.auto.tl_out_5.a.valid connect zstd_compressor.auto.tl_out_5.a.ready, x1_tlOtherMastersNodeIn_4.a.ready connect zstd_compressor.auto.tl_out_6.d, x1_tlOtherMastersNodeIn_5.d connect x1_tlOtherMastersNodeIn_5.a.bits, zstd_compressor.auto.tl_out_6.a.bits connect x1_tlOtherMastersNodeIn_5.a.valid, zstd_compressor.auto.tl_out_6.a.valid connect zstd_compressor.auto.tl_out_6.a.ready, x1_tlOtherMastersNodeIn_5.a.ready connect zstd_compressor.auto.tl_out_7.d, x1_tlOtherMastersNodeIn_6.d connect x1_tlOtherMastersNodeIn_6.a.bits, zstd_compressor.auto.tl_out_7.a.bits connect x1_tlOtherMastersNodeIn_6.a.valid, zstd_compressor.auto.tl_out_7.a.valid connect zstd_compressor.auto.tl_out_7.a.ready, x1_tlOtherMastersNodeIn_6.a.ready connect zstd_compressor.auto.tl_out_8.d, x1_tlOtherMastersNodeIn_7.d connect x1_tlOtherMastersNodeIn_7.a.bits, zstd_compressor.auto.tl_out_8.a.bits connect x1_tlOtherMastersNodeIn_7.a.valid, zstd_compressor.auto.tl_out_8.a.valid connect zstd_compressor.auto.tl_out_8.a.ready, x1_tlOtherMastersNodeIn_7.a.ready connect zstd_compressor.auto.tl_out_9.d, x1_tlOtherMastersNodeIn_8.d connect x1_tlOtherMastersNodeIn_8.a.bits, zstd_compressor.auto.tl_out_9.a.bits connect x1_tlOtherMastersNodeIn_8.a.valid, zstd_compressor.auto.tl_out_9.a.valid connect zstd_compressor.auto.tl_out_9.a.ready, x1_tlOtherMastersNodeIn_8.a.ready connect zstd_compressor.auto.tl_out_10.d, x1_tlOtherMastersNodeIn_9.d connect x1_tlOtherMastersNodeIn_9.a.bits, zstd_compressor.auto.tl_out_10.a.bits connect x1_tlOtherMastersNodeIn_9.a.valid, zstd_compressor.auto.tl_out_10.a.valid connect zstd_compressor.auto.tl_out_10.a.ready, x1_tlOtherMastersNodeIn_9.a.ready connect zstd_compressor.auto.tl_out_11.d, x1_tlOtherMastersNodeIn_10.d connect x1_tlOtherMastersNodeIn_10.a.bits, zstd_compressor.auto.tl_out_11.a.bits connect x1_tlOtherMastersNodeIn_10.a.valid, zstd_compressor.auto.tl_out_11.a.valid connect zstd_compressor.auto.tl_out_11.a.ready, x1_tlOtherMastersNodeIn_10.a.ready connect zstd_compressor.auto.tl_out_12.d, x1_tlOtherMastersNodeIn_11.d connect x1_tlOtherMastersNodeIn_11.a.bits, zstd_compressor.auto.tl_out_12.a.bits connect x1_tlOtherMastersNodeIn_11.a.valid, zstd_compressor.auto.tl_out_12.a.valid connect zstd_compressor.auto.tl_out_12.a.ready, x1_tlOtherMastersNodeIn_11.a.ready connect zstd_compressor.auto.tl_out_13.d, x1_tlOtherMastersNodeIn_12.d connect x1_tlOtherMastersNodeIn_12.a.bits, zstd_compressor.auto.tl_out_13.a.bits connect x1_tlOtherMastersNodeIn_12.a.valid, zstd_compressor.auto.tl_out_13.a.valid connect zstd_compressor.auto.tl_out_13.a.ready, x1_tlOtherMastersNodeIn_12.a.ready connect zstd_compressor.auto.tl_out_14.d, x1_tlOtherMastersNodeIn_13.d connect x1_tlOtherMastersNodeIn_13.a.bits, zstd_compressor.auto.tl_out_14.a.bits connect x1_tlOtherMastersNodeIn_13.a.valid, zstd_compressor.auto.tl_out_14.a.valid connect zstd_compressor.auto.tl_out_14.a.ready, x1_tlOtherMastersNodeIn_13.a.ready connect zstd_compressor.auto.tl_out_15.d, x1_tlOtherMastersNodeIn_14.d connect x1_tlOtherMastersNodeIn_14.a.bits, zstd_compressor.auto.tl_out_15.a.bits connect x1_tlOtherMastersNodeIn_14.a.valid, zstd_compressor.auto.tl_out_15.a.valid connect zstd_compressor.auto.tl_out_15.a.ready, x1_tlOtherMastersNodeIn_14.a.ready connect zstd_compressor.auto.tl_out_16.d, x1_tlOtherMastersNodeIn_15.d connect x1_tlOtherMastersNodeIn_15.a.bits, zstd_compressor.auto.tl_out_16.a.bits connect x1_tlOtherMastersNodeIn_15.a.valid, zstd_compressor.auto.tl_out_16.a.valid connect zstd_compressor.auto.tl_out_16.a.ready, x1_tlOtherMastersNodeIn_15.a.ready connect zstd_compressor.auto.tl_out_17.d, x1_tlOtherMastersNodeIn_16.d connect x1_tlOtherMastersNodeIn_16.a.bits, zstd_compressor.auto.tl_out_17.a.bits connect x1_tlOtherMastersNodeIn_16.a.valid, zstd_compressor.auto.tl_out_17.a.valid connect zstd_compressor.auto.tl_out_17.a.ready, x1_tlOtherMastersNodeIn_16.a.ready connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect buffer.auto.out_0.d, auto.buffer_out_0.d connect auto.buffer_out_0.a.bits, buffer.auto.out_0.a.bits connect auto.buffer_out_0.a.valid, buffer.auto.out_0.a.valid connect buffer.auto.out_0.a.ready, auto.buffer_out_0.a.ready connect buffer.auto.out_1.d, auto.buffer_out_1.d connect auto.buffer_out_1.a.bits, buffer.auto.out_1.a.bits connect auto.buffer_out_1.a.valid, buffer.auto.out_1.a.valid connect buffer.auto.out_1.a.ready, auto.buffer_out_1.a.ready connect buffer.auto.out_2.d, auto.buffer_out_2.d connect auto.buffer_out_2.a.bits, buffer.auto.out_2.a.bits connect auto.buffer_out_2.a.valid, buffer.auto.out_2.a.valid connect buffer.auto.out_2.a.ready, auto.buffer_out_2.a.ready connect buffer.auto.out_3.d, auto.buffer_out_3.d connect auto.buffer_out_3.a.bits, buffer.auto.out_3.a.bits connect auto.buffer_out_3.a.valid, buffer.auto.out_3.a.valid connect buffer.auto.out_3.a.ready, auto.buffer_out_3.a.ready connect buffer.auto.out_4.d, auto.buffer_out_4.d connect auto.buffer_out_4.a.bits, buffer.auto.out_4.a.bits connect auto.buffer_out_4.a.valid, buffer.auto.out_4.a.valid connect buffer.auto.out_4.a.ready, auto.buffer_out_4.a.ready connect buffer.auto.out_5.d, auto.buffer_out_5.d connect auto.buffer_out_5.a.bits, buffer.auto.out_5.a.bits connect auto.buffer_out_5.a.valid, buffer.auto.out_5.a.valid connect buffer.auto.out_5.a.ready, auto.buffer_out_5.a.ready connect buffer.auto.out_6.d, auto.buffer_out_6.d connect auto.buffer_out_6.a.bits, buffer.auto.out_6.a.bits connect auto.buffer_out_6.a.valid, buffer.auto.out_6.a.valid connect buffer.auto.out_6.a.ready, auto.buffer_out_6.a.ready connect buffer.auto.out_7.d, auto.buffer_out_7.d connect auto.buffer_out_7.a.bits, buffer.auto.out_7.a.bits connect auto.buffer_out_7.a.valid, buffer.auto.out_7.a.valid connect buffer.auto.out_7.a.ready, auto.buffer_out_7.a.ready connect buffer.auto.out_8.d, auto.buffer_out_8.d connect auto.buffer_out_8.a.bits, buffer.auto.out_8.a.bits connect auto.buffer_out_8.a.valid, buffer.auto.out_8.a.valid connect buffer.auto.out_8.a.ready, auto.buffer_out_8.a.ready connect buffer.auto.out_9.d, auto.buffer_out_9.d connect auto.buffer_out_9.a.bits, buffer.auto.out_9.a.bits connect auto.buffer_out_9.a.valid, buffer.auto.out_9.a.valid connect buffer.auto.out_9.a.ready, auto.buffer_out_9.a.ready connect buffer.auto.out_10.d, auto.buffer_out_10.d connect auto.buffer_out_10.a.bits, buffer.auto.out_10.a.bits connect auto.buffer_out_10.a.valid, buffer.auto.out_10.a.valid connect buffer.auto.out_10.a.ready, auto.buffer_out_10.a.ready connect buffer.auto.out_11.d, auto.buffer_out_11.d connect auto.buffer_out_11.a.bits, buffer.auto.out_11.a.bits connect auto.buffer_out_11.a.valid, buffer.auto.out_11.a.valid connect buffer.auto.out_11.a.ready, auto.buffer_out_11.a.ready connect buffer.auto.out_12.d, auto.buffer_out_12.d connect auto.buffer_out_12.a.bits, buffer.auto.out_12.a.bits connect auto.buffer_out_12.a.valid, buffer.auto.out_12.a.valid connect buffer.auto.out_12.a.ready, auto.buffer_out_12.a.ready connect buffer.auto.out_13.d, auto.buffer_out_13.d connect auto.buffer_out_13.a.bits, buffer.auto.out_13.a.bits connect auto.buffer_out_13.a.valid, buffer.auto.out_13.a.valid connect buffer.auto.out_13.a.ready, auto.buffer_out_13.a.ready connect buffer.auto.out_14.d, auto.buffer_out_14.d connect auto.buffer_out_14.a.bits, buffer.auto.out_14.a.bits connect auto.buffer_out_14.a.valid, buffer.auto.out_14.a.valid connect buffer.auto.out_14.a.ready, auto.buffer_out_14.a.ready connect buffer.auto.out_15.d, auto.buffer_out_15.d connect auto.buffer_out_15.a.bits, buffer.auto.out_15.a.bits connect auto.buffer_out_15.a.valid, buffer.auto.out_15.a.valid connect buffer.auto.out_15.a.ready, auto.buffer_out_15.a.ready connect buffer.auto.out_16.d, auto.buffer_out_16.d connect auto.buffer_out_16.a.bits, buffer.auto.out_16.a.bits connect auto.buffer_out_16.a.valid, buffer.auto.out_16.a.valid connect buffer.auto.out_16.a.ready, auto.buffer_out_16.a.ready connect buffer.auto.out_17.d, auto.buffer_out_17.d connect auto.buffer_out_17.a.bits, buffer.auto.out_17.a.bits connect auto.buffer_out_17.a.valid, buffer.auto.out_17.a.valid connect buffer.auto.out_17.a.ready, auto.buffer_out_17.a.ready connect auto.buffer_out_18.e.bits, buffer.auto.out_18.e.bits connect auto.buffer_out_18.e.valid, buffer.auto.out_18.e.valid connect buffer.auto.out_18.e.ready, auto.buffer_out_18.e.ready connect buffer.auto.out_18.d, auto.buffer_out_18.d connect auto.buffer_out_18.c.bits, buffer.auto.out_18.c.bits connect auto.buffer_out_18.c.valid, buffer.auto.out_18.c.valid connect buffer.auto.out_18.c.ready, auto.buffer_out_18.c.ready connect buffer.auto.out_18.b, auto.buffer_out_18.b connect auto.buffer_out_18.a.bits, buffer.auto.out_18.a.bits connect auto.buffer_out_18.a.valid, buffer.auto.out_18.a.valid connect buffer.auto.out_18.a.ready, auto.buffer_out_18.a.ready invalidate dcache.io.tlb_port.s2_kill invalidate dcache.io.tlb_port.s1_resp.cmd invalidate dcache.io.tlb_port.s1_resp.size invalidate dcache.io.tlb_port.s1_resp.prefetchable invalidate dcache.io.tlb_port.s1_resp.must_alloc invalidate dcache.io.tlb_port.s1_resp.cacheable invalidate dcache.io.tlb_port.s1_resp.ma.inst invalidate dcache.io.tlb_port.s1_resp.ma.st invalidate dcache.io.tlb_port.s1_resp.ma.ld invalidate dcache.io.tlb_port.s1_resp.ae.inst invalidate dcache.io.tlb_port.s1_resp.ae.st invalidate dcache.io.tlb_port.s1_resp.ae.ld invalidate dcache.io.tlb_port.s1_resp.gf.inst invalidate dcache.io.tlb_port.s1_resp.gf.st invalidate dcache.io.tlb_port.s1_resp.gf.ld invalidate dcache.io.tlb_port.s1_resp.pf.inst invalidate dcache.io.tlb_port.s1_resp.pf.st invalidate dcache.io.tlb_port.s1_resp.pf.ld invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte invalidate dcache.io.tlb_port.s1_resp.gpa invalidate dcache.io.tlb_port.s1_resp.paddr invalidate dcache.io.tlb_port.s1_resp.miss invalidate dcache.io.tlb_port.req.bits.v invalidate dcache.io.tlb_port.req.bits.prv invalidate dcache.io.tlb_port.req.bits.cmd invalidate dcache.io.tlb_port.req.bits.size invalidate dcache.io.tlb_port.req.bits.passthrough invalidate dcache.io.tlb_port.req.bits.vaddr invalidate dcache.io.tlb_port.req.valid invalidate dcache.io.tlb_port.req.ready inst fpuOpt of FPU connect fpuOpt.clock, clock connect fpuOpt.reset, reset connect fpuOpt.io.cp_req.valid, UInt<1>(0h0) invalidate fpuOpt.io.cp_req.bits.in3 invalidate fpuOpt.io.cp_req.bits.in2 invalidate fpuOpt.io.cp_req.bits.in1 invalidate fpuOpt.io.cp_req.bits.fmt invalidate fpuOpt.io.cp_req.bits.typ invalidate fpuOpt.io.cp_req.bits.fmaCmd invalidate fpuOpt.io.cp_req.bits.rm invalidate fpuOpt.io.cp_req.bits.vec invalidate fpuOpt.io.cp_req.bits.wflags invalidate fpuOpt.io.cp_req.bits.sqrt invalidate fpuOpt.io.cp_req.bits.div invalidate fpuOpt.io.cp_req.bits.fma invalidate fpuOpt.io.cp_req.bits.fastpipe invalidate fpuOpt.io.cp_req.bits.toint invalidate fpuOpt.io.cp_req.bits.fromint invalidate fpuOpt.io.cp_req.bits.typeTagOut invalidate fpuOpt.io.cp_req.bits.typeTagIn invalidate fpuOpt.io.cp_req.bits.swap23 invalidate fpuOpt.io.cp_req.bits.swap12 invalidate fpuOpt.io.cp_req.bits.ren3 invalidate fpuOpt.io.cp_req.bits.ren2 invalidate fpuOpt.io.cp_req.bits.ren1 invalidate fpuOpt.io.cp_req.bits.wen invalidate fpuOpt.io.cp_req.bits.ldst connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0) inst dcacheArb of HellaCacheArbiter connect dcacheArb.clock, clock connect dcacheArb.reset, reset connect dcache.io.cpu, dcacheArb.io.mem inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.mem.clock_enabled invalidate ptw.io.mem.keep_clock_enabled invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad invalidate ptw.io.mem.perf.canAcceptLoadThenLoad invalidate ptw.io.mem.perf.canAcceptStoreThenRMW invalidate ptw.io.mem.perf.canAcceptStoreThenLoad invalidate ptw.io.mem.perf.blocked invalidate ptw.io.mem.perf.tlbMiss invalidate ptw.io.mem.perf.grant invalidate ptw.io.mem.perf.release invalidate ptw.io.mem.perf.acquire invalidate ptw.io.mem.store_pending invalidate ptw.io.mem.ordered invalidate ptw.io.mem.s2_gpa_is_pte invalidate ptw.io.mem.s2_gpa invalidate ptw.io.mem.s2_xcpt.ae.st invalidate ptw.io.mem.s2_xcpt.ae.ld invalidate ptw.io.mem.s2_xcpt.gf.st invalidate ptw.io.mem.s2_xcpt.gf.ld invalidate ptw.io.mem.s2_xcpt.pf.st invalidate ptw.io.mem.s2_xcpt.pf.ld invalidate ptw.io.mem.s2_xcpt.ma.st invalidate ptw.io.mem.s2_xcpt.ma.ld invalidate ptw.io.mem.replay_next invalidate ptw.io.mem.resp.bits.store_data invalidate ptw.io.mem.resp.bits.data_raw invalidate ptw.io.mem.resp.bits.data_word_bypass invalidate ptw.io.mem.resp.bits.has_data invalidate ptw.io.mem.resp.bits.replay invalidate ptw.io.mem.resp.bits.mask invalidate ptw.io.mem.resp.bits.data invalidate ptw.io.mem.resp.bits.dv invalidate ptw.io.mem.resp.bits.dprv invalidate ptw.io.mem.resp.bits.signed invalidate ptw.io.mem.resp.bits.size invalidate ptw.io.mem.resp.bits.cmd invalidate ptw.io.mem.resp.bits.tag invalidate ptw.io.mem.resp.bits.addr invalidate ptw.io.mem.resp.valid invalidate ptw.io.mem.s2_paddr invalidate ptw.io.mem.s2_uncached invalidate ptw.io.mem.s2_kill invalidate ptw.io.mem.s2_nack_cause_raw invalidate ptw.io.mem.s2_nack invalidate ptw.io.mem.s1_data.mask invalidate ptw.io.mem.s1_data.data invalidate ptw.io.mem.s1_kill invalidate ptw.io.mem.req.bits.mask invalidate ptw.io.mem.req.bits.data invalidate ptw.io.mem.req.bits.no_xcpt invalidate ptw.io.mem.req.bits.no_alloc invalidate ptw.io.mem.req.bits.no_resp invalidate ptw.io.mem.req.bits.phys invalidate ptw.io.mem.req.bits.dv invalidate ptw.io.mem.req.bits.dprv invalidate ptw.io.mem.req.bits.signed invalidate ptw.io.mem.req.bits.size invalidate ptw.io.mem.req.bits.cmd invalidate ptw.io.mem.req.bits.tag invalidate ptw.io.mem.req.bits.addr invalidate ptw.io.mem.req.valid invalidate ptw.io.mem.req.ready inst respArb of RRArbiter connect respArb.clock, clock connect respArb.reset, reset inst cmdRouter of RoccCommandRouter connect cmdRouter.clock, clock connect cmdRouter.reset, reset connect zstd_compressor.io.cmd, cmdRouter.io.out[0] inst dcIF of SimpleHellaCacheIF connect dcIF.clock, clock connect dcIF.reset, reset connect dcIF.io.requestor, zstd_compressor.io.mem inst respArb_io_in_0_q of Queue2_RoCCResponse connect respArb_io_in_0_q.clock, clock connect respArb_io_in_0_q.reset, reset connect respArb_io_in_0_q.io.enq.valid, zstd_compressor.io.resp.valid connect respArb_io_in_0_q.io.enq.bits.data, zstd_compressor.io.resp.bits.data connect respArb_io_in_0_q.io.enq.bits.rd, zstd_compressor.io.resp.bits.rd connect zstd_compressor.io.resp.ready, respArb_io_in_0_q.io.enq.ready connect respArb.io.in[0], respArb_io_in_0_q.io.deq inst core of Rocket connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector connect haltNodeOut[0], UInt<1>(0h0) connect ceaseNodeOut[0], UInt<1>(0h0) regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0) connect wfiNodeOut_0_REG, core.io.wfi connect wfiNodeOut[0], wfiNodeOut_0_REG connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.traceStall, traceAuxSinkNodeIn.stall connect bpwatchSourceNodeOut, core.io.bpwatch connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.imem connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt connect core.io.fpu.dec.div, fpuOpt.io.dec.div connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23 connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12 connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3 connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2 connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1 connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst connect fpuOpt.io.killm, core.io.fpu.killm connect fpuOpt.io.killx, core.io.fpu.killx connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy connect fpuOpt.io.valid, core.io.fpu.valid connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val connect core.io.fpu.toint_data, fpuOpt.io.toint_data connect core.io.fpu.store_data, fpuOpt.io.store_data connect fpuOpt.io.v_sew, core.io.fpu.v_sew connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data connect fpuOpt.io.inst, core.io.fpu.inst connect fpuOpt.io.time, core.io.fpu.time connect fpuOpt.io.hartid, core.io.fpu.hartid connect core.io.ptw, ptw.io.dpath connect cmdRouter.io.in, core.io.rocc.cmd connect zstd_compressor.io.exception, core.io.rocc.exception invalidate zstd_compressor.io.fpu_req.ready invalidate zstd_compressor.io.fpu_resp.valid invalidate zstd_compressor.io.fpu_resp.bits.data invalidate zstd_compressor.io.fpu_resp.bits.exc connect core.io.rocc.resp, respArb.io.out node _core_io_rocc_busy_T = or(cmdRouter.io.busy, zstd_compressor.io.busy) connect core.io.rocc.busy, _core_io_rocc_busy_T connect core.io.rocc.interrupt, zstd_compressor.io.interrupt invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready connect dcacheArb.io.requestor[0], ptw.io.mem connect dcacheArb.io.requestor[1], dcIF.io.cache connect dcacheArb.io.requestor[2], core.io.dmem connect ptw.io.requestor[0], zstd_compressor.io.ptw[0] connect ptw.io.requestor[1], zstd_compressor.io.ptw[1] connect ptw.io.requestor[2], zstd_compressor.io.ptw[2] connect ptw.io.requestor[3], zstd_compressor.io.ptw[3] connect ptw.io.requestor[4], zstd_compressor.io.ptw[4] connect ptw.io.requestor[5], zstd_compressor.io.ptw[5] connect ptw.io.requestor[6], zstd_compressor.io.ptw[6] connect ptw.io.requestor[7], zstd_compressor.io.ptw[7] connect ptw.io.requestor[8], zstd_compressor.io.ptw[8] connect ptw.io.requestor[9], zstd_compressor.io.ptw[9] connect ptw.io.requestor[10], zstd_compressor.io.ptw[10] connect ptw.io.requestor[11], zstd_compressor.io.ptw[11] connect ptw.io.requestor[12], zstd_compressor.io.ptw[12] connect ptw.io.requestor[13], zstd_compressor.io.ptw[13] connect ptw.io.requestor[14], zstd_compressor.io.ptw[14] connect ptw.io.requestor[15], zstd_compressor.io.ptw[15] connect ptw.io.requestor[16], zstd_compressor.io.ptw[16] connect ptw.io.requestor[17], zstd_compressor.io.ptw[17] connect ptw.io.requestor[18], dcache.io.ptw connect ptw.io.requestor[19], frontend.io.ptw	module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_18_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_18_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_18_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_18_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_18_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_18_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_18_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_18_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_18_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_18_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_18_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_18_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_18_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_18_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_18_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_18_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_17_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_17_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_17_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_17_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_17_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_17_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_17_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_17_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_17_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_17_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_17_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_16_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_16_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_16_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_16_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_16_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_16_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_16_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_16_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_16_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_16_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_16_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_15_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_15_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_15_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_15_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_15_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_15_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_15_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_15_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_15_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_15_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_15_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_14_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_14_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_14_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_14_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_14_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_14_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_14_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_14_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_14_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_14_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_14_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_13_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_13_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_13_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_13_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_13_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_13_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_13_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_13_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_13_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_13_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_13_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_12_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_12_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_12_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_12_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_12_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_12_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_12_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_12_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_12_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_12_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_12_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_11_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_11_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_11_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_11_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_11_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_11_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_11_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_11_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_11_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_11_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_11_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_10_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_10_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_10_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_10_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_10_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_10_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_10_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_10_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_10_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_10_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_10_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_9_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_9_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_9_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_9_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_9_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_9_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_9_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_9_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_9_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_9_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_9_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_8_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_8_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_8_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_8_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_8_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_8_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_8_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_8_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_8_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_8_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_8_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire _core_io_rocc_busy_T; // @[RocketTile.scala:213:49] wire buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_2_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_2_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_2_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_2_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_2_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_2_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_2_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_2_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_3_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_3_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_3_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_3_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_3_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_3_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_3_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_3_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_4_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_4_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_4_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_4_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_4_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_4_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_4_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_4_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_5_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_5_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_5_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_5_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_5_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_5_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_5_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_5_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_6_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_6_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_6_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_6_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_6_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_6_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_6_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_6_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_7_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_7_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_7_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_7_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_7_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_7_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_7_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_7_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_8_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_8_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_8_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_8_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_8_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_9_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_9_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_9_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_9_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_9_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_10_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_10_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_10_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_10_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_10_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_10_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_10_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_10_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_11_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_11_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_11_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_11_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_11_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_11_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_11_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_11_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_12_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_12_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_12_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_12_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_12_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_12_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_12_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_12_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_13_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_13_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_13_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_13_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_13_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_13_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_13_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_13_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_14_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_14_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_14_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_14_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_14_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_14_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_14_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_14_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_15_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_15_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_15_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_15_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_15_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_15_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_15_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_15_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_16_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_16_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_16_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_16_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_16_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_16_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_16_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_16_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_17_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_17_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_17_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_17_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_17_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_17_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_17_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_17_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_18_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_18_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [7:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_valid; // @[RocketTile.scala:147:20] wire [6:0] _core_io_rocc_cmd_bits_inst_funct; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rs2; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rs1; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xd; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xs1; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xs2; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rd; // @[RocketTile.scala:147:20] wire [6:0] _core_io_rocc_cmd_bits_inst_opcode; // @[RocketTile.scala:147:20] wire [63:0] _core_io_rocc_cmd_bits_rs1; // @[RocketTile.scala:147:20] wire [63:0] _core_io_rocc_cmd_bits_rs2; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_debug; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_cease; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_rocc_cmd_bits_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_prv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_v; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_gva; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tw; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_sum; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_spp; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_spie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_sie; // @[RocketTile.scala:147:20] wire _core_io_rocc_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_rocc_exception; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _respArb_io_in_0_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _respArb_io_in_0_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [4:0] _respArb_io_in_0_q_io_deq_bits_rd; // @[Decoupled.scala:362:21] wire [63:0] _respArb_io_in_0_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _dcIF_io_requestor_req_ready; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_valid; // @[LazyRoCC.scala:106:24] wire [39:0] _dcIF_io_requestor_resp_bits_addr; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_requestor_resp_bits_tag; // @[LazyRoCC.scala:106:24] wire [4:0] _dcIF_io_requestor_resp_bits_cmd; // @[LazyRoCC.scala:106:24] wire [1:0] _dcIF_io_requestor_resp_bits_size; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_signed; // @[LazyRoCC.scala:106:24] wire [1:0] _dcIF_io_requestor_resp_bits_dprv; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_dv; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_requestor_resp_bits_mask; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_replay; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_has_data; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data_word_bypass; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data_raw; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_store_data; // @[LazyRoCC.scala:106:24] wire _dcIF_io_cache_req_valid; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_cache_s1_data_data; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_cache_s1_data_mask; // @[LazyRoCC.scala:106:24] wire _cmdRouter_io_in_ready; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_valid; // @[LazyRoCC.scala:102:27] wire [6:0] _cmdRouter_io_out_0_bits_inst_funct; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rs2; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rs1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xd; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xs1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xs2; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rd; // @[LazyRoCC.scala:102:27] wire [6:0] _cmdRouter_io_out_0_bits_inst_opcode; // @[LazyRoCC.scala:102:27] wire [63:0] _cmdRouter_io_out_0_bits_rs1; // @[LazyRoCC.scala:102:27] wire [63:0] _cmdRouter_io_out_0_bits_rs2; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_debug; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_cease; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_wfi; // @[LazyRoCC.scala:102:27] wire [31:0] _cmdRouter_io_out_0_bits_status_isa; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_dprv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_dv; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_prv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_v; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sd; // @[LazyRoCC.scala:102:27] wire [22:0] _cmdRouter_io_out_0_bits_status_zero2; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mpv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_gva; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mbe; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sbe; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_sxl; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_uxl; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sd_rv32; // @[LazyRoCC.scala:102:27] wire [7:0] _cmdRouter_io_out_0_bits_status_zero1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tsr; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tw; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tvm; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mxr; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sum; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mprv; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_xs; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_fs; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_mpp; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_vs; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_spp; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mpie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_ube; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_spie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_upie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_hie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_uie; // @[LazyRoCC.scala:102:27] wire _respArb_io_in_0_ready; // @[LazyRoCC.scala:101:25] wire _respArb_io_out_valid; // @[LazyRoCC.scala:101:25] wire [4:0] _respArb_io_out_bits_rd; // @[LazyRoCC.scala:101:25] wire [63:0] _respArb_io_out_bits_data; // @[LazyRoCC.scala:101:25] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_2_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_2_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_3_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_3_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_3_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_3_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_3_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_3_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_3_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_4_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_4_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_4_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_4_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_4_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_4_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_4_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_5_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_5_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_5_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_5_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_5_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_5_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_5_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_6_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_6_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_6_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_6_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_6_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_6_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_6_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_7_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_7_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_7_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_7_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_7_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_7_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_7_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_8_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_8_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_8_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_8_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_8_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_8_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_8_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_9_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_9_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_9_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_9_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_9_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_9_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_9_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_10_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_10_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_10_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_10_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_10_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_10_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_10_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_11_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_11_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_11_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_11_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_11_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_11_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_11_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_12_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_12_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_12_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_12_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_12_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_12_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_12_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_13_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_13_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_13_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_13_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_13_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_13_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_13_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_14_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_14_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_14_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_14_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_14_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_14_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_14_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_15_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_15_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_15_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_15_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_15_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_15_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_15_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_16_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_16_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_16_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_16_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_16_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_16_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_16_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_17_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_17_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_17_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_17_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_17_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_17_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_17_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_18_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_18_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_18_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_18_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_18_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_18_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_18_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_19_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_19_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_19_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_19_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_19_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_19_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_19_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_2_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_2_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_2_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_2_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_2_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_2_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _zstd_compressor_io_cmd_ready; // @[Configs.scala:62:39] wire _zstd_compressor_io_resp_valid; // @[Configs.scala:62:39] wire [4:0] _zstd_compressor_io_resp_bits_rd; // @[Configs.scala:62:39] wire [63:0] _zstd_compressor_io_resp_bits_data; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_0_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_0_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_0_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_1_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_1_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_1_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_2_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_2_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_2_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_3_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_3_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_3_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_4_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_4_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_4_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_5_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_5_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_5_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_6_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_6_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_6_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_7_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_7_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_7_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_8_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_8_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_8_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_9_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_9_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_9_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_10_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_10_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_10_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_11_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_11_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_11_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_12_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_12_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_12_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_13_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_13_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_13_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_14_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_14_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_14_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_15_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_15_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_15_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_16_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_16_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_16_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_17_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_17_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_17_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_18_a_ready_0 = auto_buffer_out_18_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_valid_0 = auto_buffer_out_18_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_b_bits_opcode_0 = auto_buffer_out_18_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_b_bits_param_0 = auto_buffer_out_18_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_b_bits_size_0 = auto_buffer_out_18_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_b_bits_source_0 = auto_buffer_out_18_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_b_bits_address_0 = auto_buffer_out_18_b_bits_address; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_18_b_bits_mask_0 = auto_buffer_out_18_b_bits_mask; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_b_bits_data_0 = auto_buffer_out_18_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_bits_corrupt_0 = auto_buffer_out_18_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_ready_0 = auto_buffer_out_18_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_valid_0 = auto_buffer_out_18_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_d_bits_opcode_0 = auto_buffer_out_18_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_d_bits_param_0 = auto_buffer_out_18_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_d_bits_size_0 = auto_buffer_out_18_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_d_bits_source_0 = auto_buffer_out_18_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_d_bits_sink_0 = auto_buffer_out_18_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_bits_denied_0 = auto_buffer_out_18_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_d_bits_data_0 = auto_buffer_out_18_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_bits_corrupt_0 = auto_buffer_out_18_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_e_ready_0 = auto_buffer_out_18_e_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_ready_0 = auto_buffer_out_17_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_valid_0 = auto_buffer_out_17_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_d_bits_opcode_0 = auto_buffer_out_17_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_17_d_bits_param_0 = auto_buffer_out_17_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_17_d_bits_size_0 = auto_buffer_out_17_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_17_d_bits_source_0 = auto_buffer_out_17_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_d_bits_sink_0 = auto_buffer_out_17_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_bits_denied_0 = auto_buffer_out_17_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_17_d_bits_data_0 = auto_buffer_out_17_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_bits_corrupt_0 = auto_buffer_out_17_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_ready_0 = auto_buffer_out_16_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_valid_0 = auto_buffer_out_16_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_d_bits_opcode_0 = auto_buffer_out_16_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_16_d_bits_param_0 = auto_buffer_out_16_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_16_d_bits_size_0 = auto_buffer_out_16_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_16_d_bits_source_0 = auto_buffer_out_16_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_d_bits_sink_0 = auto_buffer_out_16_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_bits_denied_0 = auto_buffer_out_16_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_16_d_bits_data_0 = auto_buffer_out_16_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_bits_corrupt_0 = auto_buffer_out_16_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_ready_0 = auto_buffer_out_15_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_valid_0 = auto_buffer_out_15_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_d_bits_opcode_0 = auto_buffer_out_15_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_15_d_bits_param_0 = auto_buffer_out_15_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_15_d_bits_size_0 = auto_buffer_out_15_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_15_d_bits_source_0 = auto_buffer_out_15_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_d_bits_sink_0 = auto_buffer_out_15_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_bits_denied_0 = auto_buffer_out_15_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_15_d_bits_data_0 = auto_buffer_out_15_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_bits_corrupt_0 = auto_buffer_out_15_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_ready_0 = auto_buffer_out_14_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_valid_0 = auto_buffer_out_14_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_d_bits_opcode_0 = auto_buffer_out_14_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_14_d_bits_param_0 = auto_buffer_out_14_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_14_d_bits_size_0 = auto_buffer_out_14_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_14_d_bits_source_0 = auto_buffer_out_14_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_d_bits_sink_0 = auto_buffer_out_14_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_bits_denied_0 = auto_buffer_out_14_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_14_d_bits_data_0 = auto_buffer_out_14_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_bits_corrupt_0 = auto_buffer_out_14_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_ready_0 = auto_buffer_out_13_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_valid_0 = auto_buffer_out_13_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_d_bits_opcode_0 = auto_buffer_out_13_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_13_d_bits_param_0 = auto_buffer_out_13_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_13_d_bits_size_0 = auto_buffer_out_13_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_13_d_bits_source_0 = auto_buffer_out_13_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_d_bits_sink_0 = auto_buffer_out_13_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_bits_denied_0 = auto_buffer_out_13_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_13_d_bits_data_0 = auto_buffer_out_13_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_bits_corrupt_0 = auto_buffer_out_13_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_ready_0 = auto_buffer_out_12_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_valid_0 = auto_buffer_out_12_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_d_bits_opcode_0 = auto_buffer_out_12_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_12_d_bits_param_0 = auto_buffer_out_12_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_12_d_bits_size_0 = auto_buffer_out_12_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_12_d_bits_source_0 = auto_buffer_out_12_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_d_bits_sink_0 = auto_buffer_out_12_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_bits_denied_0 = auto_buffer_out_12_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_12_d_bits_data_0 = auto_buffer_out_12_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_bits_corrupt_0 = auto_buffer_out_12_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_ready_0 = auto_buffer_out_11_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_valid_0 = auto_buffer_out_11_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_d_bits_opcode_0 = auto_buffer_out_11_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_11_d_bits_param_0 = auto_buffer_out_11_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_11_d_bits_size_0 = auto_buffer_out_11_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_11_d_bits_source_0 = auto_buffer_out_11_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_d_bits_sink_0 = auto_buffer_out_11_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_bits_denied_0 = auto_buffer_out_11_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_11_d_bits_data_0 = auto_buffer_out_11_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_bits_corrupt_0 = auto_buffer_out_11_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_ready_0 = auto_buffer_out_10_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_valid_0 = auto_buffer_out_10_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_d_bits_opcode_0 = auto_buffer_out_10_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_10_d_bits_param_0 = auto_buffer_out_10_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_10_d_bits_size_0 = auto_buffer_out_10_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_10_d_bits_source_0 = auto_buffer_out_10_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_d_bits_sink_0 = auto_buffer_out_10_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_bits_denied_0 = auto_buffer_out_10_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_10_d_bits_data_0 = auto_buffer_out_10_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_bits_corrupt_0 = auto_buffer_out_10_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_ready_0 = auto_buffer_out_9_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_valid_0 = auto_buffer_out_9_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_d_bits_opcode_0 = auto_buffer_out_9_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_d_bits_param_0 = auto_buffer_out_9_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_9_d_bits_size_0 = auto_buffer_out_9_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_d_bits_source_0 = auto_buffer_out_9_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_d_bits_sink_0 = auto_buffer_out_9_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_bits_denied_0 = auto_buffer_out_9_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_9_d_bits_data_0 = auto_buffer_out_9_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_bits_corrupt_0 = auto_buffer_out_9_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_ready_0 = auto_buffer_out_8_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_valid_0 = auto_buffer_out_8_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_d_bits_opcode_0 = auto_buffer_out_8_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_d_bits_param_0 = auto_buffer_out_8_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_8_d_bits_size_0 = auto_buffer_out_8_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_d_bits_source_0 = auto_buffer_out_8_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_d_bits_sink_0 = auto_buffer_out_8_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_bits_denied_0 = auto_buffer_out_8_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_8_d_bits_data_0 = auto_buffer_out_8_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_bits_corrupt_0 = auto_buffer_out_8_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_ready_0 = auto_buffer_out_7_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_valid_0 = auto_buffer_out_7_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_d_bits_opcode_0 = auto_buffer_out_7_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_7_d_bits_param_0 = auto_buffer_out_7_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_7_d_bits_size_0 = auto_buffer_out_7_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_7_d_bits_source_0 = auto_buffer_out_7_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_d_bits_sink_0 = auto_buffer_out_7_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_bits_denied_0 = auto_buffer_out_7_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_7_d_bits_data_0 = auto_buffer_out_7_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_bits_corrupt_0 = auto_buffer_out_7_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_ready_0 = auto_buffer_out_6_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_valid_0 = auto_buffer_out_6_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_d_bits_opcode_0 = auto_buffer_out_6_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_6_d_bits_param_0 = auto_buffer_out_6_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_6_d_bits_size_0 = auto_buffer_out_6_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_6_d_bits_source_0 = auto_buffer_out_6_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_d_bits_sink_0 = auto_buffer_out_6_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_bits_denied_0 = auto_buffer_out_6_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_6_d_bits_data_0 = auto_buffer_out_6_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_bits_corrupt_0 = auto_buffer_out_6_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_ready_0 = auto_buffer_out_5_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_valid_0 = auto_buffer_out_5_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_d_bits_opcode_0 = auto_buffer_out_5_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_5_d_bits_param_0 = auto_buffer_out_5_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_5_d_bits_size_0 = auto_buffer_out_5_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_5_d_bits_source_0 = auto_buffer_out_5_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_d_bits_sink_0 = auto_buffer_out_5_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_bits_denied_0 = auto_buffer_out_5_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_5_d_bits_data_0 = auto_buffer_out_5_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_bits_corrupt_0 = auto_buffer_out_5_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_ready_0 = auto_buffer_out_4_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_valid_0 = auto_buffer_out_4_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_d_bits_opcode_0 = auto_buffer_out_4_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_4_d_bits_param_0 = auto_buffer_out_4_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_4_d_bits_size_0 = auto_buffer_out_4_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_4_d_bits_source_0 = auto_buffer_out_4_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_d_bits_sink_0 = auto_buffer_out_4_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_bits_denied_0 = auto_buffer_out_4_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_4_d_bits_data_0 = auto_buffer_out_4_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_bits_corrupt_0 = auto_buffer_out_4_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_ready_0 = auto_buffer_out_3_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_valid_0 = auto_buffer_out_3_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_d_bits_opcode_0 = auto_buffer_out_3_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_3_d_bits_param_0 = auto_buffer_out_3_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_3_d_bits_size_0 = auto_buffer_out_3_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_3_d_bits_source_0 = auto_buffer_out_3_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_d_bits_sink_0 = auto_buffer_out_3_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_bits_denied_0 = auto_buffer_out_3_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_3_d_bits_data_0 = auto_buffer_out_3_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_bits_corrupt_0 = auto_buffer_out_3_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_ready_0 = auto_buffer_out_2_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_valid_0 = auto_buffer_out_2_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_d_bits_opcode_0 = auto_buffer_out_2_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_2_d_bits_param_0 = auto_buffer_out_2_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_2_d_bits_size_0 = auto_buffer_out_2_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_2_d_bits_source_0 = auto_buffer_out_2_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_d_bits_sink_0 = auto_buffer_out_2_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_bits_denied_0 = auto_buffer_out_2_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_2_d_bits_data_0 = auto_buffer_out_2_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_bits_corrupt_0 = auto_buffer_out_2_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_ready_0 = auto_buffer_out_1_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_valid_0 = auto_buffer_out_1_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_d_bits_opcode_0 = auto_buffer_out_1_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_d_bits_param_0 = auto_buffer_out_1_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_1_d_bits_size_0 = auto_buffer_out_1_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_d_bits_source_0 = auto_buffer_out_1_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_d_bits_sink_0 = auto_buffer_out_1_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_bits_denied_0 = auto_buffer_out_1_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_1_d_bits_data_0 = auto_buffer_out_1_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_bits_corrupt_0 = auto_buffer_out_1_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_ready_0 = auto_buffer_out_0_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_valid_0 = auto_buffer_out_0_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_d_bits_opcode_0 = auto_buffer_out_0_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_d_bits_param_0 = auto_buffer_out_0_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_0_d_bits_size_0 = auto_buffer_out_0_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_d_bits_source_0 = auto_buffer_out_0_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_d_bits_sink_0 = auto_buffer_out_0_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_bits_denied_0 = auto_buffer_out_0_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_0_d_bits_data_0 = auto_buffer_out_0_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_bits_corrupt_0 = auto_buffer_out_0_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_18_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_x1_nodeOut_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_x1_nodeIn_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_tlOtherMastersNodeOut_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_tlOtherMastersNodeIn_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeIn_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_18_a_ready = auto_buffer_out_18_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_valid = auto_buffer_out_18_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_b_bits_opcode = auto_buffer_out_18_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_b_bits_param = auto_buffer_out_18_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_b_bits_size = auto_buffer_out_18_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_b_bits_source = auto_buffer_out_18_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_b_bits_address = auto_buffer_out_18_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_18_b_bits_mask = auto_buffer_out_18_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_b_bits_data = auto_buffer_out_18_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_bits_corrupt = auto_buffer_out_18_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_ready = auto_buffer_out_18_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_valid = auto_buffer_out_18_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_d_bits_opcode = auto_buffer_out_18_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_d_bits_param = auto_buffer_out_18_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_d_bits_size = auto_buffer_out_18_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_d_bits_source = auto_buffer_out_18_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_d_bits_sink = auto_buffer_out_18_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_bits_denied = auto_buffer_out_18_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_d_bits_data = auto_buffer_out_18_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_bits_corrupt = auto_buffer_out_18_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_e_ready = auto_buffer_out_18_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_ready = auto_buffer_out_17_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_17_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_valid = auto_buffer_out_17_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_d_bits_opcode = auto_buffer_out_17_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_17_d_bits_param = auto_buffer_out_17_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_17_d_bits_size = auto_buffer_out_17_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_17_d_bits_source = auto_buffer_out_17_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_d_bits_sink = auto_buffer_out_17_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_bits_denied = auto_buffer_out_17_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_17_d_bits_data = auto_buffer_out_17_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_bits_corrupt = auto_buffer_out_17_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_ready = auto_buffer_out_16_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_16_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_valid = auto_buffer_out_16_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_d_bits_opcode = auto_buffer_out_16_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_16_d_bits_param = auto_buffer_out_16_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_16_d_bits_size = auto_buffer_out_16_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_16_d_bits_source = auto_buffer_out_16_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_d_bits_sink = auto_buffer_out_16_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_bits_denied = auto_buffer_out_16_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_16_d_bits_data = auto_buffer_out_16_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_bits_corrupt = auto_buffer_out_16_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_ready = auto_buffer_out_15_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_15_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_valid = auto_buffer_out_15_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_d_bits_opcode = auto_buffer_out_15_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_15_d_bits_param = auto_buffer_out_15_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_15_d_bits_size = auto_buffer_out_15_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_15_d_bits_source = auto_buffer_out_15_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_d_bits_sink = auto_buffer_out_15_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_bits_denied = auto_buffer_out_15_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_15_d_bits_data = auto_buffer_out_15_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_bits_corrupt = auto_buffer_out_15_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_ready = auto_buffer_out_14_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_14_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_valid = auto_buffer_out_14_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_d_bits_opcode = auto_buffer_out_14_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_14_d_bits_param = auto_buffer_out_14_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_14_d_bits_size = auto_buffer_out_14_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_14_d_bits_source = auto_buffer_out_14_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_d_bits_sink = auto_buffer_out_14_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_bits_denied = auto_buffer_out_14_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_14_d_bits_data = auto_buffer_out_14_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_bits_corrupt = auto_buffer_out_14_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_ready = auto_buffer_out_13_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_13_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_valid = auto_buffer_out_13_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_d_bits_opcode = auto_buffer_out_13_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_13_d_bits_param = auto_buffer_out_13_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_13_d_bits_size = auto_buffer_out_13_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_13_d_bits_source = auto_buffer_out_13_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_d_bits_sink = auto_buffer_out_13_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_bits_denied = auto_buffer_out_13_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_13_d_bits_data = auto_buffer_out_13_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_bits_corrupt = auto_buffer_out_13_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_ready = auto_buffer_out_12_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_12_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_valid = auto_buffer_out_12_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_d_bits_opcode = auto_buffer_out_12_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_12_d_bits_param = auto_buffer_out_12_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_12_d_bits_size = auto_buffer_out_12_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_12_d_bits_source = auto_buffer_out_12_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_d_bits_sink = auto_buffer_out_12_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_bits_denied = auto_buffer_out_12_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_12_d_bits_data = auto_buffer_out_12_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_bits_corrupt = auto_buffer_out_12_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_ready = auto_buffer_out_11_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_11_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_valid = auto_buffer_out_11_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_d_bits_opcode = auto_buffer_out_11_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_11_d_bits_param = auto_buffer_out_11_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_11_d_bits_size = auto_buffer_out_11_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_11_d_bits_source = auto_buffer_out_11_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_d_bits_sink = auto_buffer_out_11_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_bits_denied = auto_buffer_out_11_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_11_d_bits_data = auto_buffer_out_11_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_bits_corrupt = auto_buffer_out_11_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_ready = auto_buffer_out_10_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_10_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_valid = auto_buffer_out_10_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_d_bits_opcode = auto_buffer_out_10_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_10_d_bits_param = auto_buffer_out_10_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_10_d_bits_size = auto_buffer_out_10_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_10_d_bits_source = auto_buffer_out_10_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_d_bits_sink = auto_buffer_out_10_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_bits_denied = auto_buffer_out_10_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_10_d_bits_data = auto_buffer_out_10_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_bits_corrupt = auto_buffer_out_10_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_ready = auto_buffer_out_9_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_9_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_valid = auto_buffer_out_9_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_d_bits_opcode = auto_buffer_out_9_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_d_bits_param = auto_buffer_out_9_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_9_d_bits_size = auto_buffer_out_9_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_d_bits_source = auto_buffer_out_9_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_d_bits_sink = auto_buffer_out_9_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_bits_denied = auto_buffer_out_9_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_9_d_bits_data = auto_buffer_out_9_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_bits_corrupt = auto_buffer_out_9_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_ready = auto_buffer_out_8_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_8_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_valid = auto_buffer_out_8_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_d_bits_opcode = auto_buffer_out_8_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_d_bits_param = auto_buffer_out_8_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_8_d_bits_size = auto_buffer_out_8_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_d_bits_source = auto_buffer_out_8_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_d_bits_sink = auto_buffer_out_8_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_bits_denied = auto_buffer_out_8_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_8_d_bits_data = auto_buffer_out_8_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_bits_corrupt = auto_buffer_out_8_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_ready = auto_buffer_out_7_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_7_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_valid = auto_buffer_out_7_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_d_bits_opcode = auto_buffer_out_7_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_7_d_bits_param = auto_buffer_out_7_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_7_d_bits_size = auto_buffer_out_7_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_7_d_bits_source = auto_buffer_out_7_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_d_bits_sink = auto_buffer_out_7_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_bits_denied = auto_buffer_out_7_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_7_d_bits_data = auto_buffer_out_7_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_bits_corrupt = auto_buffer_out_7_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_ready = auto_buffer_out_6_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_6_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_valid = auto_buffer_out_6_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_d_bits_opcode = auto_buffer_out_6_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_6_d_bits_param = auto_buffer_out_6_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_6_d_bits_size = auto_buffer_out_6_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_6_d_bits_source = auto_buffer_out_6_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_d_bits_sink = auto_buffer_out_6_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_bits_denied = auto_buffer_out_6_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_6_d_bits_data = auto_buffer_out_6_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_bits_corrupt = auto_buffer_out_6_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_ready = auto_buffer_out_5_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_5_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_valid = auto_buffer_out_5_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_d_bits_opcode = auto_buffer_out_5_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_5_d_bits_param = auto_buffer_out_5_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_5_d_bits_size = auto_buffer_out_5_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_5_d_bits_source = auto_buffer_out_5_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_d_bits_sink = auto_buffer_out_5_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_bits_denied = auto_buffer_out_5_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_5_d_bits_data = auto_buffer_out_5_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_bits_corrupt = auto_buffer_out_5_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_ready = auto_buffer_out_4_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_4_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_valid = auto_buffer_out_4_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_d_bits_opcode = auto_buffer_out_4_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_4_d_bits_param = auto_buffer_out_4_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_4_d_bits_size = auto_buffer_out_4_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_4_d_bits_source = auto_buffer_out_4_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_d_bits_sink = auto_buffer_out_4_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_bits_denied = auto_buffer_out_4_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_4_d_bits_data = auto_buffer_out_4_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_bits_corrupt = auto_buffer_out_4_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_ready = auto_buffer_out_3_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_3_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_valid = auto_buffer_out_3_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_d_bits_opcode = auto_buffer_out_3_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_3_d_bits_param = auto_buffer_out_3_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_3_d_bits_size = auto_buffer_out_3_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_3_d_bits_source = auto_buffer_out_3_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_d_bits_sink = auto_buffer_out_3_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_bits_denied = auto_buffer_out_3_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_3_d_bits_data = auto_buffer_out_3_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_bits_corrupt = auto_buffer_out_3_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_ready = auto_buffer_out_2_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_2_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_valid = auto_buffer_out_2_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_d_bits_opcode = auto_buffer_out_2_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_2_d_bits_param = auto_buffer_out_2_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_2_d_bits_size = auto_buffer_out_2_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_2_d_bits_source = auto_buffer_out_2_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_d_bits_sink = auto_buffer_out_2_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_bits_denied = auto_buffer_out_2_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_2_d_bits_data = auto_buffer_out_2_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_bits_corrupt = auto_buffer_out_2_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_ready = auto_buffer_out_1_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_valid = auto_buffer_out_1_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_d_bits_opcode = auto_buffer_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_d_bits_param = auto_buffer_out_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_1_d_bits_size = auto_buffer_out_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_d_bits_source = auto_buffer_out_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_d_bits_sink = auto_buffer_out_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_bits_denied = auto_buffer_out_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_1_d_bits_data = auto_buffer_out_1_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_bits_corrupt = auto_buffer_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_ready = auto_buffer_out_0_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_valid = auto_buffer_out_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_d_bits_opcode = auto_buffer_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_d_bits_param = auto_buffer_out_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_0_d_bits_size = auto_buffer_out_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_d_bits_source = auto_buffer_out_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_d_bits_sink = auto_buffer_out_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_bits_denied = auto_buffer_out_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_0_d_bits_data = auto_buffer_out_0_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_bits_corrupt = auto_buffer_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_18_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_c_bits_address_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_e_valid_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_17_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_17_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_17_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_17_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_17_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_16_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_16_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_16_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_16_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_16_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_15_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_15_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_15_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_15_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_15_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_14_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_14_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_14_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_14_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_14_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_13_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_13_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_13_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_13_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_13_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_12_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_12_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_12_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_12_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_12_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_11_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_11_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_11_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_11_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_11_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_10_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_10_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_10_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_10_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_10_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_9_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_9_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_9_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_9_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_8_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_8_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_8_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_8_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_7_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_7_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_7_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_7_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_7_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_6_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_6_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_6_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_6_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_6_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_5_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_5_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_5_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_5_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_5_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_4_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_4_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_4_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_4_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_4_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_3_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_3_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_3_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_3_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_3_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_2_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_2_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_2_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_2_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_2_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_x1_nodeIn_17_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_a_ready = buffer_auto_in_18_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_a_valid = buffer_auto_in_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_a_bits_opcode = buffer_auto_in_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_a_bits_param = buffer_auto_in_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_17_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_17_a_bits_size = buffer_auto_in_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_17_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_17_a_bits_source = buffer_auto_in_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_17_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_17_a_bits_address = buffer_auto_in_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_17_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_17_a_bits_mask = buffer_auto_in_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_17_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_17_a_bits_data = buffer_auto_in_18_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_b_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_b_ready = buffer_auto_in_18_b_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_b_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_b_valid = buffer_auto_in_18_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_b_bits_opcode = buffer_auto_in_18_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_17_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_b_bits_param = buffer_auto_in_18_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_17_b_bits_size = buffer_auto_in_18_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeIn_17_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_b_bits_source = buffer_auto_in_18_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeIn_17_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] x1_tlOtherMastersNodeOut_17_b_bits_address = buffer_auto_in_18_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_17_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] x1_tlOtherMastersNodeOut_17_b_bits_mask = buffer_auto_in_18_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_17_b_bits_data = buffer_auto_in_18_b_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_c_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_b_bits_corrupt = buffer_auto_in_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_c_ready = buffer_auto_in_18_c_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_c_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_c_valid = buffer_auto_in_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_c_bits_opcode = buffer_auto_in_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_c_bits_param = buffer_auto_in_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_17_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_17_c_bits_size = buffer_auto_in_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_17_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_17_c_bits_source = buffer_auto_in_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_17_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_17_c_bits_address = buffer_auto_in_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_17_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_17_c_bits_data = buffer_auto_in_18_c_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_d_ready = buffer_auto_in_18_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_valid = buffer_auto_in_18_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_d_bits_opcode = buffer_auto_in_18_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_17_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_d_bits_param = buffer_auto_in_18_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_17_d_bits_size = buffer_auto_in_18_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_17_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_d_bits_source = buffer_auto_in_18_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_d_bits_sink = buffer_auto_in_18_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_17_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_bits_denied = buffer_auto_in_18_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_17_d_bits_data = buffer_auto_in_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_e_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_bits_corrupt = buffer_auto_in_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_e_ready = buffer_auto_in_18_e_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_e_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_e_valid = buffer_auto_in_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_e_bits_sink; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_ready; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_e_bits_sink = buffer_auto_in_18_e_bits_sink; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_ready = buffer_auto_in_17_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_valid = buffer_auto_in_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_16_a_bits_opcode = buffer_auto_in_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_16_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_16_a_bits_param = buffer_auto_in_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_16_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_16_a_bits_size = buffer_auto_in_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_16_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_16_a_bits_source = buffer_auto_in_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_16_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_16_a_bits_address = buffer_auto_in_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_16_a_bits_mask = buffer_auto_in_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_16_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_16_a_bits_data = buffer_auto_in_17_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_bits_corrupt = buffer_auto_in_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_d_ready = buffer_auto_in_17_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_16_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_valid = buffer_auto_in_17_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_16_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_16_d_bits_opcode = buffer_auto_in_17_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_16_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_16_d_bits_param = buffer_auto_in_17_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_16_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_16_d_bits_size = buffer_auto_in_17_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_16_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_16_d_bits_source = buffer_auto_in_17_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_16_d_bits_sink = buffer_auto_in_17_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_16_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_bits_denied = buffer_auto_in_17_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_16_d_bits_data = buffer_auto_in_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_bits_corrupt = buffer_auto_in_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_ready = buffer_auto_in_16_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_a_valid = buffer_auto_in_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_15_a_bits_opcode = buffer_auto_in_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_15_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_15_a_bits_param = buffer_auto_in_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_15_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_15_a_bits_size = buffer_auto_in_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_15_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_15_a_bits_source = buffer_auto_in_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_15_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_15_a_bits_address = buffer_auto_in_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_15_a_bits_mask = buffer_auto_in_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_15_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_15_a_bits_data = buffer_auto_in_16_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_a_bits_corrupt = buffer_auto_in_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_d_ready = buffer_auto_in_16_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_15_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_valid = buffer_auto_in_16_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_15_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_15_d_bits_opcode = buffer_auto_in_16_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_15_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_15_d_bits_param = buffer_auto_in_16_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_15_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_15_d_bits_size = buffer_auto_in_16_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_15_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_15_d_bits_source = buffer_auto_in_16_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_15_d_bits_sink = buffer_auto_in_16_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_15_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_bits_denied = buffer_auto_in_16_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_15_d_bits_data = buffer_auto_in_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_bits_corrupt = buffer_auto_in_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_ready = buffer_auto_in_15_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_a_valid = buffer_auto_in_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_14_a_bits_opcode = buffer_auto_in_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_14_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_14_a_bits_param = buffer_auto_in_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_14_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_14_a_bits_size = buffer_auto_in_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_14_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_14_a_bits_source = buffer_auto_in_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_14_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_14_a_bits_address = buffer_auto_in_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_14_a_bits_mask = buffer_auto_in_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_14_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_14_a_bits_data = buffer_auto_in_15_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_a_bits_corrupt = buffer_auto_in_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_d_ready = buffer_auto_in_15_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_14_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_valid = buffer_auto_in_15_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_14_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_14_d_bits_opcode = buffer_auto_in_15_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_14_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_14_d_bits_param = buffer_auto_in_15_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_14_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_14_d_bits_size = buffer_auto_in_15_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_14_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_14_d_bits_source = buffer_auto_in_15_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_14_d_bits_sink = buffer_auto_in_15_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_14_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_bits_denied = buffer_auto_in_15_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_14_d_bits_data = buffer_auto_in_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_bits_corrupt = buffer_auto_in_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_ready = buffer_auto_in_14_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_a_valid = buffer_auto_in_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_13_a_bits_opcode = buffer_auto_in_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_13_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_13_a_bits_param = buffer_auto_in_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_13_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_13_a_bits_size = buffer_auto_in_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_13_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_13_a_bits_source = buffer_auto_in_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_13_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_13_a_bits_address = buffer_auto_in_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_13_a_bits_mask = buffer_auto_in_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_13_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_13_a_bits_data = buffer_auto_in_14_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_a_bits_corrupt = buffer_auto_in_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_d_ready = buffer_auto_in_14_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_13_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_valid = buffer_auto_in_14_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_13_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_13_d_bits_opcode = buffer_auto_in_14_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_13_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_13_d_bits_param = buffer_auto_in_14_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_13_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_13_d_bits_size = buffer_auto_in_14_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_13_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_13_d_bits_source = buffer_auto_in_14_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_13_d_bits_sink = buffer_auto_in_14_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_13_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_bits_denied = buffer_auto_in_14_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_13_d_bits_data = buffer_auto_in_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_bits_corrupt = buffer_auto_in_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_ready = buffer_auto_in_13_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_a_valid = buffer_auto_in_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_12_a_bits_opcode = buffer_auto_in_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_12_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_12_a_bits_param = buffer_auto_in_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_12_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_12_a_bits_size = buffer_auto_in_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_12_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_12_a_bits_source = buffer_auto_in_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_12_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_12_a_bits_address = buffer_auto_in_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_12_a_bits_mask = buffer_auto_in_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_12_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_12_a_bits_data = buffer_auto_in_13_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_a_bits_corrupt = buffer_auto_in_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_d_ready = buffer_auto_in_13_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_12_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_valid = buffer_auto_in_13_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_12_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_12_d_bits_opcode = buffer_auto_in_13_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_12_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_12_d_bits_param = buffer_auto_in_13_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_12_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_12_d_bits_size = buffer_auto_in_13_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_12_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_12_d_bits_source = buffer_auto_in_13_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_12_d_bits_sink = buffer_auto_in_13_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_12_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_bits_denied = buffer_auto_in_13_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_12_d_bits_data = buffer_auto_in_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_bits_corrupt = buffer_auto_in_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_ready = buffer_auto_in_12_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_a_valid = buffer_auto_in_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_11_a_bits_opcode = buffer_auto_in_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_11_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_11_a_bits_param = buffer_auto_in_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_11_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_11_a_bits_size = buffer_auto_in_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_11_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_11_a_bits_source = buffer_auto_in_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_11_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_11_a_bits_address = buffer_auto_in_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_11_a_bits_mask = buffer_auto_in_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_11_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_11_a_bits_data = buffer_auto_in_12_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_a_bits_corrupt = buffer_auto_in_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_d_ready = buffer_auto_in_12_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_11_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_valid = buffer_auto_in_12_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_11_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_11_d_bits_opcode = buffer_auto_in_12_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_11_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_11_d_bits_param = buffer_auto_in_12_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_11_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_11_d_bits_size = buffer_auto_in_12_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_11_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_11_d_bits_source = buffer_auto_in_12_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_11_d_bits_sink = buffer_auto_in_12_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_11_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_bits_denied = buffer_auto_in_12_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_11_d_bits_data = buffer_auto_in_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_bits_corrupt = buffer_auto_in_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_ready = buffer_auto_in_11_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_a_valid = buffer_auto_in_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_10_a_bits_opcode = buffer_auto_in_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_10_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_10_a_bits_param = buffer_auto_in_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_10_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_10_a_bits_size = buffer_auto_in_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_10_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_10_a_bits_source = buffer_auto_in_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_10_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_10_a_bits_address = buffer_auto_in_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_10_a_bits_mask = buffer_auto_in_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_10_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_10_a_bits_data = buffer_auto_in_11_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_a_bits_corrupt = buffer_auto_in_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_d_ready = buffer_auto_in_11_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_10_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_valid = buffer_auto_in_11_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_10_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_10_d_bits_opcode = buffer_auto_in_11_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_10_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_10_d_bits_param = buffer_auto_in_11_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_10_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_10_d_bits_size = buffer_auto_in_11_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_10_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_10_d_bits_source = buffer_auto_in_11_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_10_d_bits_sink = buffer_auto_in_11_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_10_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_bits_denied = buffer_auto_in_11_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_10_d_bits_data = buffer_auto_in_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_bits_corrupt = buffer_auto_in_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_ready = buffer_auto_in_10_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_a_valid = buffer_auto_in_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_9_a_bits_opcode = buffer_auto_in_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_9_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_9_a_bits_param = buffer_auto_in_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_9_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_9_a_bits_size = buffer_auto_in_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_9_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_9_a_bits_source = buffer_auto_in_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_9_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_9_a_bits_address = buffer_auto_in_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_9_a_bits_mask = buffer_auto_in_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_9_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_9_a_bits_data = buffer_auto_in_10_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_a_bits_corrupt = buffer_auto_in_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_d_ready = buffer_auto_in_10_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_9_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_valid = buffer_auto_in_10_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_9_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_9_d_bits_opcode = buffer_auto_in_10_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_9_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_9_d_bits_param = buffer_auto_in_10_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_9_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_9_d_bits_size = buffer_auto_in_10_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_9_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_9_d_bits_source = buffer_auto_in_10_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_9_d_bits_sink = buffer_auto_in_10_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_9_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_bits_denied = buffer_auto_in_10_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_9_d_bits_data = buffer_auto_in_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_bits_corrupt = buffer_auto_in_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_ready = buffer_auto_in_9_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_a_valid = buffer_auto_in_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_8_a_bits_opcode = buffer_auto_in_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_8_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_8_a_bits_param = buffer_auto_in_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_8_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_8_a_bits_size = buffer_auto_in_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_8_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_8_a_bits_source = buffer_auto_in_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_8_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_8_a_bits_address = buffer_auto_in_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_8_a_bits_mask = buffer_auto_in_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_8_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_8_a_bits_data = buffer_auto_in_9_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_a_bits_corrupt = buffer_auto_in_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_d_ready = buffer_auto_in_9_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_8_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_valid = buffer_auto_in_9_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_8_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_8_d_bits_opcode = buffer_auto_in_9_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_8_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_8_d_bits_param = buffer_auto_in_9_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_8_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_8_d_bits_size = buffer_auto_in_9_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_8_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_8_d_bits_source = buffer_auto_in_9_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_8_d_bits_sink = buffer_auto_in_9_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_8_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_bits_denied = buffer_auto_in_9_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_8_d_bits_data = buffer_auto_in_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_bits_corrupt = buffer_auto_in_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_ready = buffer_auto_in_8_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_a_valid = buffer_auto_in_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_7_a_bits_opcode = buffer_auto_in_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_7_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_7_a_bits_param = buffer_auto_in_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_7_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_7_a_bits_size = buffer_auto_in_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_7_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_7_a_bits_source = buffer_auto_in_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_7_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_7_a_bits_address = buffer_auto_in_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_7_a_bits_mask = buffer_auto_in_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_7_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_7_a_bits_data = buffer_auto_in_8_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_a_bits_corrupt = buffer_auto_in_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_d_ready = buffer_auto_in_8_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_7_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_valid = buffer_auto_in_8_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_7_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_7_d_bits_opcode = buffer_auto_in_8_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_7_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_7_d_bits_param = buffer_auto_in_8_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_7_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_7_d_bits_size = buffer_auto_in_8_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_7_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_7_d_bits_source = buffer_auto_in_8_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_7_d_bits_sink = buffer_auto_in_8_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_7_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_bits_denied = buffer_auto_in_8_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_7_d_bits_data = buffer_auto_in_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_bits_corrupt = buffer_auto_in_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_ready = buffer_auto_in_7_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_a_valid = buffer_auto_in_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_6_a_bits_opcode = buffer_auto_in_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_6_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_6_a_bits_param = buffer_auto_in_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_6_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_6_a_bits_size = buffer_auto_in_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_6_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_6_a_bits_source = buffer_auto_in_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_6_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_6_a_bits_address = buffer_auto_in_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_6_a_bits_mask = buffer_auto_in_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_6_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_6_a_bits_data = buffer_auto_in_7_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_a_bits_corrupt = buffer_auto_in_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_d_ready = buffer_auto_in_7_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_6_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_valid = buffer_auto_in_7_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_6_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_6_d_bits_opcode = buffer_auto_in_7_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_6_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_6_d_bits_param = buffer_auto_in_7_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_6_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_6_d_bits_size = buffer_auto_in_7_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_6_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_6_d_bits_source = buffer_auto_in_7_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_6_d_bits_sink = buffer_auto_in_7_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_6_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_bits_denied = buffer_auto_in_7_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_6_d_bits_data = buffer_auto_in_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_bits_corrupt = buffer_auto_in_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_ready = buffer_auto_in_6_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_a_valid = buffer_auto_in_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_5_a_bits_opcode = buffer_auto_in_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_5_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_5_a_bits_param = buffer_auto_in_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_5_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_5_a_bits_size = buffer_auto_in_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_5_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_5_a_bits_source = buffer_auto_in_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_5_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_5_a_bits_address = buffer_auto_in_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_5_a_bits_mask = buffer_auto_in_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_5_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_5_a_bits_data = buffer_auto_in_6_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_a_bits_corrupt = buffer_auto_in_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_d_ready = buffer_auto_in_6_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_5_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_valid = buffer_auto_in_6_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_5_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_5_d_bits_opcode = buffer_auto_in_6_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_5_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_5_d_bits_param = buffer_auto_in_6_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_5_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_5_d_bits_size = buffer_auto_in_6_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_5_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_5_d_bits_source = buffer_auto_in_6_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_5_d_bits_sink = buffer_auto_in_6_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_5_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_bits_denied = buffer_auto_in_6_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_5_d_bits_data = buffer_auto_in_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_bits_corrupt = buffer_auto_in_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_ready = buffer_auto_in_5_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_a_valid = buffer_auto_in_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_4_a_bits_opcode = buffer_auto_in_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_4_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_4_a_bits_param = buffer_auto_in_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_4_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_4_a_bits_size = buffer_auto_in_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_4_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_4_a_bits_source = buffer_auto_in_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_4_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_4_a_bits_address = buffer_auto_in_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_4_a_bits_mask = buffer_auto_in_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_4_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_4_a_bits_data = buffer_auto_in_5_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_a_bits_corrupt = buffer_auto_in_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_d_ready = buffer_auto_in_5_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_valid = buffer_auto_in_5_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_4_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_4_d_bits_opcode = buffer_auto_in_5_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_4_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_4_d_bits_param = buffer_auto_in_5_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_4_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_4_d_bits_size = buffer_auto_in_5_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_4_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_4_d_bits_source = buffer_auto_in_5_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_4_d_bits_sink = buffer_auto_in_5_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_4_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_bits_denied = buffer_auto_in_5_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_4_d_bits_data = buffer_auto_in_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_bits_corrupt = buffer_auto_in_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_ready = buffer_auto_in_4_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_a_valid = buffer_auto_in_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_3_a_bits_opcode = buffer_auto_in_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_3_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_3_a_bits_param = buffer_auto_in_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_3_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_3_a_bits_size = buffer_auto_in_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_3_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_3_a_bits_source = buffer_auto_in_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_3_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_3_a_bits_address = buffer_auto_in_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_3_a_bits_mask = buffer_auto_in_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_3_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_3_a_bits_data = buffer_auto_in_4_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_a_bits_corrupt = buffer_auto_in_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_d_ready = buffer_auto_in_4_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_valid = buffer_auto_in_4_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_3_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_3_d_bits_opcode = buffer_auto_in_4_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_3_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_3_d_bits_param = buffer_auto_in_4_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_3_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_3_d_bits_size = buffer_auto_in_4_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_3_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_3_d_bits_source = buffer_auto_in_4_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_3_d_bits_sink = buffer_auto_in_4_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_3_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_bits_denied = buffer_auto_in_4_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_3_d_bits_data = buffer_auto_in_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_bits_corrupt = buffer_auto_in_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_ready = buffer_auto_in_3_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_a_valid = buffer_auto_in_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_2_a_bits_opcode = buffer_auto_in_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_2_a_bits_param = buffer_auto_in_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_2_a_bits_size = buffer_auto_in_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_2_a_bits_source = buffer_auto_in_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_2_a_bits_address = buffer_auto_in_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_2_a_bits_mask = buffer_auto_in_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_2_a_bits_data = buffer_auto_in_3_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_a_bits_corrupt = buffer_auto_in_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_d_ready = buffer_auto_in_3_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_valid = buffer_auto_in_3_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_2_d_bits_opcode = buffer_auto_in_3_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_2_d_bits_param = buffer_auto_in_3_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_2_d_bits_size = buffer_auto_in_3_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_2_d_bits_source = buffer_auto_in_3_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_2_d_bits_sink = buffer_auto_in_3_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_bits_denied = buffer_auto_in_3_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_2_d_bits_data = buffer_auto_in_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_bits_corrupt = buffer_auto_in_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_ready = buffer_auto_in_2_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_a_valid = buffer_auto_in_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_1_a_bits_opcode = buffer_auto_in_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_1_a_bits_param = buffer_auto_in_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_1_a_bits_size = buffer_auto_in_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_1_a_bits_source = buffer_auto_in_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_1_a_bits_address = buffer_auto_in_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_1_a_bits_mask = buffer_auto_in_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_1_a_bits_data = buffer_auto_in_2_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_a_bits_corrupt = buffer_auto_in_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_d_ready = buffer_auto_in_2_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_valid = buffer_auto_in_2_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_1_d_bits_opcode = buffer_auto_in_2_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_1_d_bits_param = buffer_auto_in_2_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_1_d_bits_size = buffer_auto_in_2_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_1_d_bits_source = buffer_auto_in_2_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_1_d_bits_sink = buffer_auto_in_2_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_bits_denied = buffer_auto_in_2_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_1_d_bits_data = buffer_auto_in_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_bits_corrupt = buffer_auto_in_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_ready = buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_a_valid = buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_a_bits_opcode = buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_a_bits_param = buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_a_bits_size = buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_a_bits_source = buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_a_bits_address = buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_a_bits_mask = buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_a_bits_data = buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_a_bits_corrupt = buffer_auto_in_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_d_ready = buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_valid = buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_ready = buffer_auto_out_18_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_valid_0 = buffer_auto_out_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_opcode_0 = buffer_auto_out_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_param_0 = buffer_auto_out_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_size_0 = buffer_auto_out_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_source_0 = buffer_auto_out_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_address_0 = buffer_auto_out_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_17_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_mask_0 = buffer_auto_out_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_data_0 = buffer_auto_out_18_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_b_ready_0 = buffer_auto_out_18_b_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_valid = buffer_auto_out_18_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_b_bits_opcode = buffer_auto_out_18_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_b_bits_param = buffer_auto_out_18_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_b_bits_size = buffer_auto_out_18_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_b_bits_source = buffer_auto_out_18_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_b_bits_address = buffer_auto_out_18_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_17_b_bits_mask = buffer_auto_out_18_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_b_bits_data = buffer_auto_out_18_b_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_bits_corrupt = buffer_auto_out_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_c_ready = buffer_auto_out_18_c_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_valid_0 = buffer_auto_out_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_opcode_0 = buffer_auto_out_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_param_0 = buffer_auto_out_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_size_0 = buffer_auto_out_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_source_0 = buffer_auto_out_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_address_0 = buffer_auto_out_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_data_0 = buffer_auto_out_18_c_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_d_ready_0 = buffer_auto_out_18_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_valid = buffer_auto_out_18_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_d_bits_opcode = buffer_auto_out_18_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_d_bits_param = buffer_auto_out_18_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_d_bits_size = buffer_auto_out_18_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_d_bits_source = buffer_auto_out_18_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_d_bits_sink = buffer_auto_out_18_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_bits_denied = buffer_auto_out_18_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_d_bits_data = buffer_auto_out_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_bits_corrupt = buffer_auto_out_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_e_ready = buffer_auto_out_18_e_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_e_valid_0 = buffer_auto_out_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_e_bits_sink_0 = buffer_auto_out_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_ready = buffer_auto_out_17_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_valid_0 = buffer_auto_out_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_opcode_0 = buffer_auto_out_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_param_0 = buffer_auto_out_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_16_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_size_0 = buffer_auto_out_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_16_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_source_0 = buffer_auto_out_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_16_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_address_0 = buffer_auto_out_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_mask_0 = buffer_auto_out_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_16_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_data_0 = buffer_auto_out_17_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_corrupt_0 = buffer_auto_out_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_d_ready_0 = buffer_auto_out_17_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_valid = buffer_auto_out_17_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_d_bits_opcode = buffer_auto_out_17_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_16_d_bits_param = buffer_auto_out_17_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_16_d_bits_size = buffer_auto_out_17_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_16_d_bits_source = buffer_auto_out_17_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_d_bits_sink = buffer_auto_out_17_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_bits_denied = buffer_auto_out_17_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_16_d_bits_data = buffer_auto_out_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_bits_corrupt = buffer_auto_out_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_ready = buffer_auto_out_16_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_valid_0 = buffer_auto_out_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_opcode_0 = buffer_auto_out_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_param_0 = buffer_auto_out_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_15_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_size_0 = buffer_auto_out_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_15_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_source_0 = buffer_auto_out_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_15_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_address_0 = buffer_auto_out_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_mask_0 = buffer_auto_out_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_15_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_data_0 = buffer_auto_out_16_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_corrupt_0 = buffer_auto_out_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_d_ready_0 = buffer_auto_out_16_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_valid = buffer_auto_out_16_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_d_bits_opcode = buffer_auto_out_16_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_15_d_bits_param = buffer_auto_out_16_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_15_d_bits_size = buffer_auto_out_16_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_15_d_bits_source = buffer_auto_out_16_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_d_bits_sink = buffer_auto_out_16_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_bits_denied = buffer_auto_out_16_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_15_d_bits_data = buffer_auto_out_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_bits_corrupt = buffer_auto_out_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_ready = buffer_auto_out_15_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_valid_0 = buffer_auto_out_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_opcode_0 = buffer_auto_out_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_param_0 = buffer_auto_out_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_14_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_size_0 = buffer_auto_out_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_14_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_source_0 = buffer_auto_out_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_14_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_address_0 = buffer_auto_out_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_mask_0 = buffer_auto_out_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_14_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_data_0 = buffer_auto_out_15_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_corrupt_0 = buffer_auto_out_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_d_ready_0 = buffer_auto_out_15_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_valid = buffer_auto_out_15_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_d_bits_opcode = buffer_auto_out_15_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_14_d_bits_param = buffer_auto_out_15_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_14_d_bits_size = buffer_auto_out_15_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_14_d_bits_source = buffer_auto_out_15_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_d_bits_sink = buffer_auto_out_15_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_bits_denied = buffer_auto_out_15_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_14_d_bits_data = buffer_auto_out_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_bits_corrupt = buffer_auto_out_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_ready = buffer_auto_out_14_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_valid_0 = buffer_auto_out_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_opcode_0 = buffer_auto_out_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_param_0 = buffer_auto_out_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_13_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_size_0 = buffer_auto_out_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_13_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_source_0 = buffer_auto_out_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_13_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_address_0 = buffer_auto_out_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_mask_0 = buffer_auto_out_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_13_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_data_0 = buffer_auto_out_14_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_corrupt_0 = buffer_auto_out_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_d_ready_0 = buffer_auto_out_14_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_valid = buffer_auto_out_14_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_d_bits_opcode = buffer_auto_out_14_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_13_d_bits_param = buffer_auto_out_14_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_13_d_bits_size = buffer_auto_out_14_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_13_d_bits_source = buffer_auto_out_14_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_d_bits_sink = buffer_auto_out_14_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_bits_denied = buffer_auto_out_14_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_13_d_bits_data = buffer_auto_out_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_bits_corrupt = buffer_auto_out_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_ready = buffer_auto_out_13_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_valid_0 = buffer_auto_out_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_opcode_0 = buffer_auto_out_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_param_0 = buffer_auto_out_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_12_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_size_0 = buffer_auto_out_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_12_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_source_0 = buffer_auto_out_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_12_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_address_0 = buffer_auto_out_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_mask_0 = buffer_auto_out_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_12_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_data_0 = buffer_auto_out_13_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_corrupt_0 = buffer_auto_out_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_d_ready_0 = buffer_auto_out_13_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_valid = buffer_auto_out_13_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_d_bits_opcode = buffer_auto_out_13_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_12_d_bits_param = buffer_auto_out_13_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_12_d_bits_size = buffer_auto_out_13_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_12_d_bits_source = buffer_auto_out_13_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_d_bits_sink = buffer_auto_out_13_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_bits_denied = buffer_auto_out_13_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_12_d_bits_data = buffer_auto_out_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_bits_corrupt = buffer_auto_out_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_ready = buffer_auto_out_12_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_valid_0 = buffer_auto_out_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_opcode_0 = buffer_auto_out_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_param_0 = buffer_auto_out_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_11_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_size_0 = buffer_auto_out_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_11_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_source_0 = buffer_auto_out_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_11_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_address_0 = buffer_auto_out_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_mask_0 = buffer_auto_out_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_11_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_data_0 = buffer_auto_out_12_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_corrupt_0 = buffer_auto_out_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_d_ready_0 = buffer_auto_out_12_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_valid = buffer_auto_out_12_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_d_bits_opcode = buffer_auto_out_12_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_11_d_bits_param = buffer_auto_out_12_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_11_d_bits_size = buffer_auto_out_12_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_11_d_bits_source = buffer_auto_out_12_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_d_bits_sink = buffer_auto_out_12_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_bits_denied = buffer_auto_out_12_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_11_d_bits_data = buffer_auto_out_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_bits_corrupt = buffer_auto_out_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_ready = buffer_auto_out_11_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_valid_0 = buffer_auto_out_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_opcode_0 = buffer_auto_out_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_param_0 = buffer_auto_out_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_10_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_size_0 = buffer_auto_out_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_10_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_source_0 = buffer_auto_out_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_10_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_address_0 = buffer_auto_out_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_mask_0 = buffer_auto_out_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_10_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_data_0 = buffer_auto_out_11_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_corrupt_0 = buffer_auto_out_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_d_ready_0 = buffer_auto_out_11_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_valid = buffer_auto_out_11_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_d_bits_opcode = buffer_auto_out_11_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_10_d_bits_param = buffer_auto_out_11_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_10_d_bits_size = buffer_auto_out_11_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_10_d_bits_source = buffer_auto_out_11_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_d_bits_sink = buffer_auto_out_11_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_bits_denied = buffer_auto_out_11_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_10_d_bits_data = buffer_auto_out_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_bits_corrupt = buffer_auto_out_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_ready = buffer_auto_out_10_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_valid_0 = buffer_auto_out_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_opcode_0 = buffer_auto_out_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_param_0 = buffer_auto_out_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_9_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_size_0 = buffer_auto_out_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_9_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_source_0 = buffer_auto_out_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_9_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_address_0 = buffer_auto_out_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_mask_0 = buffer_auto_out_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_9_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_data_0 = buffer_auto_out_10_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_corrupt_0 = buffer_auto_out_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_d_ready_0 = buffer_auto_out_10_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_valid = buffer_auto_out_10_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_d_bits_opcode = buffer_auto_out_10_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_9_d_bits_param = buffer_auto_out_10_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_9_d_bits_size = buffer_auto_out_10_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_9_d_bits_source = buffer_auto_out_10_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_d_bits_sink = buffer_auto_out_10_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_bits_denied = buffer_auto_out_10_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_9_d_bits_data = buffer_auto_out_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_bits_corrupt = buffer_auto_out_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_ready = buffer_auto_out_9_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_valid_0 = buffer_auto_out_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_opcode_0 = buffer_auto_out_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_param_0 = buffer_auto_out_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_8_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_size_0 = buffer_auto_out_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_source_0 = buffer_auto_out_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_8_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_address_0 = buffer_auto_out_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_mask_0 = buffer_auto_out_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_8_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_data_0 = buffer_auto_out_9_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_corrupt_0 = buffer_auto_out_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_d_ready_0 = buffer_auto_out_9_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_valid = buffer_auto_out_9_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_d_bits_opcode = buffer_auto_out_9_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_d_bits_param = buffer_auto_out_9_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_8_d_bits_size = buffer_auto_out_9_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_d_bits_source = buffer_auto_out_9_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_d_bits_sink = buffer_auto_out_9_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_bits_denied = buffer_auto_out_9_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_8_d_bits_data = buffer_auto_out_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_bits_corrupt = buffer_auto_out_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_ready = buffer_auto_out_8_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_valid_0 = buffer_auto_out_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_opcode_0 = buffer_auto_out_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_param_0 = buffer_auto_out_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_7_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_size_0 = buffer_auto_out_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_source_0 = buffer_auto_out_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_7_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_address_0 = buffer_auto_out_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_mask_0 = buffer_auto_out_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_7_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_data_0 = buffer_auto_out_8_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_corrupt_0 = buffer_auto_out_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_d_ready_0 = buffer_auto_out_8_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_valid = buffer_auto_out_8_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_d_bits_opcode = buffer_auto_out_8_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_d_bits_param = buffer_auto_out_8_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_7_d_bits_size = buffer_auto_out_8_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_d_bits_source = buffer_auto_out_8_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_d_bits_sink = buffer_auto_out_8_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_bits_denied = buffer_auto_out_8_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_7_d_bits_data = buffer_auto_out_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_bits_corrupt = buffer_auto_out_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_ready = buffer_auto_out_7_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_valid_0 = buffer_auto_out_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_opcode_0 = buffer_auto_out_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_param_0 = buffer_auto_out_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_6_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_size_0 = buffer_auto_out_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_6_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_source_0 = buffer_auto_out_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_6_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_address_0 = buffer_auto_out_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_mask_0 = buffer_auto_out_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_6_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_data_0 = buffer_auto_out_7_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_corrupt_0 = buffer_auto_out_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_d_ready_0 = buffer_auto_out_7_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_valid = buffer_auto_out_7_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_d_bits_opcode = buffer_auto_out_7_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_6_d_bits_param = buffer_auto_out_7_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_6_d_bits_size = buffer_auto_out_7_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_6_d_bits_source = buffer_auto_out_7_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_d_bits_sink = buffer_auto_out_7_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_bits_denied = buffer_auto_out_7_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_6_d_bits_data = buffer_auto_out_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_bits_corrupt = buffer_auto_out_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_ready = buffer_auto_out_6_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_valid_0 = buffer_auto_out_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_opcode_0 = buffer_auto_out_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_param_0 = buffer_auto_out_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_5_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_size_0 = buffer_auto_out_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_5_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_source_0 = buffer_auto_out_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_5_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_address_0 = buffer_auto_out_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_mask_0 = buffer_auto_out_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_5_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_data_0 = buffer_auto_out_6_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_corrupt_0 = buffer_auto_out_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_d_ready_0 = buffer_auto_out_6_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_valid = buffer_auto_out_6_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_d_bits_opcode = buffer_auto_out_6_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_5_d_bits_param = buffer_auto_out_6_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_5_d_bits_size = buffer_auto_out_6_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_5_d_bits_source = buffer_auto_out_6_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_d_bits_sink = buffer_auto_out_6_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_bits_denied = buffer_auto_out_6_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_5_d_bits_data = buffer_auto_out_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_bits_corrupt = buffer_auto_out_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_ready = buffer_auto_out_5_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_valid_0 = buffer_auto_out_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_opcode_0 = buffer_auto_out_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_param_0 = buffer_auto_out_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_4_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_size_0 = buffer_auto_out_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_4_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_source_0 = buffer_auto_out_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_4_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_address_0 = buffer_auto_out_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_mask_0 = buffer_auto_out_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_4_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_data_0 = buffer_auto_out_5_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_corrupt_0 = buffer_auto_out_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_d_ready_0 = buffer_auto_out_5_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_valid = buffer_auto_out_5_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_d_bits_opcode = buffer_auto_out_5_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_4_d_bits_param = buffer_auto_out_5_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_4_d_bits_size = buffer_auto_out_5_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_4_d_bits_source = buffer_auto_out_5_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_d_bits_sink = buffer_auto_out_5_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_bits_denied = buffer_auto_out_5_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_4_d_bits_data = buffer_auto_out_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_bits_corrupt = buffer_auto_out_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_ready = buffer_auto_out_4_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_valid_0 = buffer_auto_out_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_opcode_0 = buffer_auto_out_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_param_0 = buffer_auto_out_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_3_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_size_0 = buffer_auto_out_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_3_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_source_0 = buffer_auto_out_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_3_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_address_0 = buffer_auto_out_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_mask_0 = buffer_auto_out_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_3_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_data_0 = buffer_auto_out_4_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_corrupt_0 = buffer_auto_out_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_d_ready_0 = buffer_auto_out_4_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_valid = buffer_auto_out_4_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_d_bits_opcode = buffer_auto_out_4_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_3_d_bits_param = buffer_auto_out_4_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_3_d_bits_size = buffer_auto_out_4_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_3_d_bits_source = buffer_auto_out_4_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_d_bits_sink = buffer_auto_out_4_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_bits_denied = buffer_auto_out_4_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_3_d_bits_data = buffer_auto_out_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_bits_corrupt = buffer_auto_out_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_ready = buffer_auto_out_3_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_valid_0 = buffer_auto_out_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_opcode_0 = buffer_auto_out_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_param_0 = buffer_auto_out_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_2_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_size_0 = buffer_auto_out_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_2_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_source_0 = buffer_auto_out_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_2_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_address_0 = buffer_auto_out_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_mask_0 = buffer_auto_out_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_2_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_data_0 = buffer_auto_out_3_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_corrupt_0 = buffer_auto_out_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_d_ready_0 = buffer_auto_out_3_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_valid = buffer_auto_out_3_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_d_bits_opcode = buffer_auto_out_3_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_2_d_bits_param = buffer_auto_out_3_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_2_d_bits_size = buffer_auto_out_3_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_2_d_bits_source = buffer_auto_out_3_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_d_bits_sink = buffer_auto_out_3_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_bits_denied = buffer_auto_out_3_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_2_d_bits_data = buffer_auto_out_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_bits_corrupt = buffer_auto_out_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_ready = buffer_auto_out_2_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_valid_0 = buffer_auto_out_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_opcode_0 = buffer_auto_out_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_param_0 = buffer_auto_out_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_1_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_size_0 = buffer_auto_out_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_1_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_source_0 = buffer_auto_out_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_1_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_address_0 = buffer_auto_out_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_mask_0 = buffer_auto_out_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_1_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_data_0 = buffer_auto_out_2_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_corrupt_0 = buffer_auto_out_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_d_ready_0 = buffer_auto_out_2_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_valid = buffer_auto_out_2_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_d_bits_opcode = buffer_auto_out_2_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_1_d_bits_param = buffer_auto_out_2_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_1_d_bits_size = buffer_auto_out_2_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_1_d_bits_source = buffer_auto_out_2_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_d_bits_sink = buffer_auto_out_2_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_bits_denied = buffer_auto_out_2_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_1_d_bits_data = buffer_auto_out_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_bits_corrupt = buffer_auto_out_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_ready = buffer_auto_out_1_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_valid_0 = buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_opcode_0 = buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_param_0 = buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_size_0 = buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_source_0 = buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_address_0 = buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_mask_0 = buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_data_0 = buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_corrupt_0 = buffer_auto_out_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_d_ready_0 = buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_valid = buffer_auto_out_1_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_d_bits_opcode = buffer_auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_d_bits_param = buffer_auto_out_1_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_d_bits_size = buffer_auto_out_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_d_bits_source = buffer_auto_out_1_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_d_bits_sink = buffer_auto_out_1_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_bits_denied = buffer_auto_out_1_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_d_bits_data = buffer_auto_out_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_bits_corrupt = buffer_auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_0_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_valid_0 = buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_opcode_0 = buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_param_0 = buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_size_0 = buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_source_0 = buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_address_0 = buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_mask_0 = buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_data_0 = buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_corrupt_0 = buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_d_ready_0 = buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_0_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_0_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_0_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_0_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_0_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_0_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_0_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_0_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_0_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_a_ready = buffer_x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_1_a_valid = buffer_x1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_opcode = buffer_x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_param = buffer_x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_size = buffer_x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_source = buffer_x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_address = buffer_x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_mask = buffer_x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_data = buffer_x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_corrupt = buffer_x1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_1_d_ready = buffer_x1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_d_valid = buffer_x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_opcode = buffer_x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_param = buffer_x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_size = buffer_x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_source = buffer_x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_sink = buffer_x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_denied = buffer_x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_data = buffer_x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_corrupt = buffer_x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_a_ready = buffer_x1_nodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_2_a_valid = buffer_x1_nodeOut_1_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_opcode = buffer_x1_nodeOut_1_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_param = buffer_x1_nodeOut_1_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_size = buffer_x1_nodeOut_1_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_source = buffer_x1_nodeOut_1_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_address = buffer_x1_nodeOut_1_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_mask = buffer_x1_nodeOut_1_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_data = buffer_x1_nodeOut_1_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_corrupt = buffer_x1_nodeOut_1_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_2_d_ready = buffer_x1_nodeOut_1_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_1_d_valid = buffer_x1_nodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_opcode = buffer_x1_nodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_param = buffer_x1_nodeOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_size = buffer_x1_nodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_source = buffer_x1_nodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_sink = buffer_x1_nodeOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_denied = buffer_x1_nodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_data = buffer_x1_nodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_corrupt = buffer_x1_nodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_a_ready = buffer_x1_nodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_3_a_valid = buffer_x1_nodeOut_2_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_opcode = buffer_x1_nodeOut_2_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_param = buffer_x1_nodeOut_2_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_size = buffer_x1_nodeOut_2_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_source = buffer_x1_nodeOut_2_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_address = buffer_x1_nodeOut_2_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_mask = buffer_x1_nodeOut_2_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_data = buffer_x1_nodeOut_2_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_corrupt = buffer_x1_nodeOut_2_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_3_d_ready = buffer_x1_nodeOut_2_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_2_d_valid = buffer_x1_nodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_opcode = buffer_x1_nodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_param = buffer_x1_nodeOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_size = buffer_x1_nodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_source = buffer_x1_nodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_sink = buffer_x1_nodeOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_denied = buffer_x1_nodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_data = buffer_x1_nodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_corrupt = buffer_x1_nodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_a_ready = buffer_x1_nodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_4_a_valid = buffer_x1_nodeOut_3_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_opcode = buffer_x1_nodeOut_3_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_param = buffer_x1_nodeOut_3_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_size = buffer_x1_nodeOut_3_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_source = buffer_x1_nodeOut_3_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_address = buffer_x1_nodeOut_3_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_mask = buffer_x1_nodeOut_3_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_data = buffer_x1_nodeOut_3_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_corrupt = buffer_x1_nodeOut_3_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_4_d_ready = buffer_x1_nodeOut_3_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_3_d_valid = buffer_x1_nodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_opcode = buffer_x1_nodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_param = buffer_x1_nodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_size = buffer_x1_nodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_source = buffer_x1_nodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_sink = buffer_x1_nodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_denied = buffer_x1_nodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_data = buffer_x1_nodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_corrupt = buffer_x1_nodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_a_ready = buffer_x1_nodeOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_5_a_valid = buffer_x1_nodeOut_4_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_opcode = buffer_x1_nodeOut_4_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_param = buffer_x1_nodeOut_4_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_size = buffer_x1_nodeOut_4_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_source = buffer_x1_nodeOut_4_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_address = buffer_x1_nodeOut_4_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_mask = buffer_x1_nodeOut_4_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_data = buffer_x1_nodeOut_4_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_corrupt = buffer_x1_nodeOut_4_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_5_d_ready = buffer_x1_nodeOut_4_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_4_d_valid = buffer_x1_nodeOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_opcode = buffer_x1_nodeOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_param = buffer_x1_nodeOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_size = buffer_x1_nodeOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_source = buffer_x1_nodeOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_sink = buffer_x1_nodeOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_denied = buffer_x1_nodeOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_data = buffer_x1_nodeOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_corrupt = buffer_x1_nodeOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_a_ready = buffer_x1_nodeOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_6_a_valid = buffer_x1_nodeOut_5_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_opcode = buffer_x1_nodeOut_5_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_param = buffer_x1_nodeOut_5_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_size = buffer_x1_nodeOut_5_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_source = buffer_x1_nodeOut_5_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_address = buffer_x1_nodeOut_5_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_mask = buffer_x1_nodeOut_5_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_data = buffer_x1_nodeOut_5_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_corrupt = buffer_x1_nodeOut_5_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_6_d_ready = buffer_x1_nodeOut_5_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_5_d_valid = buffer_x1_nodeOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_opcode = buffer_x1_nodeOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_param = buffer_x1_nodeOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_size = buffer_x1_nodeOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_source = buffer_x1_nodeOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_sink = buffer_x1_nodeOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_denied = buffer_x1_nodeOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_data = buffer_x1_nodeOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_corrupt = buffer_x1_nodeOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_a_ready = buffer_x1_nodeOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_7_a_valid = buffer_x1_nodeOut_6_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_opcode = buffer_x1_nodeOut_6_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_param = buffer_x1_nodeOut_6_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_size = buffer_x1_nodeOut_6_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_source = buffer_x1_nodeOut_6_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_address = buffer_x1_nodeOut_6_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_mask = buffer_x1_nodeOut_6_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_data = buffer_x1_nodeOut_6_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_corrupt = buffer_x1_nodeOut_6_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_7_d_ready = buffer_x1_nodeOut_6_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_6_d_valid = buffer_x1_nodeOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_opcode = buffer_x1_nodeOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_param = buffer_x1_nodeOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_size = buffer_x1_nodeOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_source = buffer_x1_nodeOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_sink = buffer_x1_nodeOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_denied = buffer_x1_nodeOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_data = buffer_x1_nodeOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_corrupt = buffer_x1_nodeOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_a_ready = buffer_x1_nodeOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_8_a_valid = buffer_x1_nodeOut_7_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_opcode = buffer_x1_nodeOut_7_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_param = buffer_x1_nodeOut_7_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_size = buffer_x1_nodeOut_7_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_source = buffer_x1_nodeOut_7_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_address = buffer_x1_nodeOut_7_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_mask = buffer_x1_nodeOut_7_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_data = buffer_x1_nodeOut_7_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_corrupt = buffer_x1_nodeOut_7_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_8_d_ready = buffer_x1_nodeOut_7_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_7_d_valid = buffer_x1_nodeOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_opcode = buffer_x1_nodeOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_param = buffer_x1_nodeOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_size = buffer_x1_nodeOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_source = buffer_x1_nodeOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_sink = buffer_x1_nodeOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_denied = buffer_x1_nodeOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_data = buffer_x1_nodeOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_corrupt = buffer_x1_nodeOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_a_ready = buffer_x1_nodeOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_9_a_valid = buffer_x1_nodeOut_8_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_opcode = buffer_x1_nodeOut_8_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_param = buffer_x1_nodeOut_8_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_size = buffer_x1_nodeOut_8_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_source = buffer_x1_nodeOut_8_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_address = buffer_x1_nodeOut_8_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_mask = buffer_x1_nodeOut_8_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_data = buffer_x1_nodeOut_8_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_corrupt = buffer_x1_nodeOut_8_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_9_d_ready = buffer_x1_nodeOut_8_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_8_d_valid = buffer_x1_nodeOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_opcode = buffer_x1_nodeOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_param = buffer_x1_nodeOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_size = buffer_x1_nodeOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_source = buffer_x1_nodeOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_sink = buffer_x1_nodeOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_denied = buffer_x1_nodeOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_data = buffer_x1_nodeOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_corrupt = buffer_x1_nodeOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_a_ready = buffer_x1_nodeOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_10_a_valid = buffer_x1_nodeOut_9_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_opcode = buffer_x1_nodeOut_9_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_param = buffer_x1_nodeOut_9_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_size = buffer_x1_nodeOut_9_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_source = buffer_x1_nodeOut_9_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_address = buffer_x1_nodeOut_9_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_mask = buffer_x1_nodeOut_9_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_data = buffer_x1_nodeOut_9_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_corrupt = buffer_x1_nodeOut_9_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_10_d_ready = buffer_x1_nodeOut_9_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_9_d_valid = buffer_x1_nodeOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_opcode = buffer_x1_nodeOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_param = buffer_x1_nodeOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_size = buffer_x1_nodeOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_source = buffer_x1_nodeOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_sink = buffer_x1_nodeOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_denied = buffer_x1_nodeOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_data = buffer_x1_nodeOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_corrupt = buffer_x1_nodeOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_a_ready = buffer_x1_nodeOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_11_a_valid = buffer_x1_nodeOut_10_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_opcode = buffer_x1_nodeOut_10_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_param = buffer_x1_nodeOut_10_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_size = buffer_x1_nodeOut_10_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_source = buffer_x1_nodeOut_10_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_address = buffer_x1_nodeOut_10_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_mask = buffer_x1_nodeOut_10_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_data = buffer_x1_nodeOut_10_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_corrupt = buffer_x1_nodeOut_10_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_11_d_ready = buffer_x1_nodeOut_10_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_10_d_valid = buffer_x1_nodeOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_opcode = buffer_x1_nodeOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_param = buffer_x1_nodeOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_size = buffer_x1_nodeOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_source = buffer_x1_nodeOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_sink = buffer_x1_nodeOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_denied = buffer_x1_nodeOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_data = buffer_x1_nodeOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_corrupt = buffer_x1_nodeOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_a_ready = buffer_x1_nodeOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_12_a_valid = buffer_x1_nodeOut_11_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_opcode = buffer_x1_nodeOut_11_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_param = buffer_x1_nodeOut_11_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_size = buffer_x1_nodeOut_11_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_source = buffer_x1_nodeOut_11_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_address = buffer_x1_nodeOut_11_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_mask = buffer_x1_nodeOut_11_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_data = buffer_x1_nodeOut_11_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_corrupt = buffer_x1_nodeOut_11_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_12_d_ready = buffer_x1_nodeOut_11_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_11_d_valid = buffer_x1_nodeOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_opcode = buffer_x1_nodeOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_param = buffer_x1_nodeOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_size = buffer_x1_nodeOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_source = buffer_x1_nodeOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_sink = buffer_x1_nodeOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_denied = buffer_x1_nodeOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_data = buffer_x1_nodeOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_corrupt = buffer_x1_nodeOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_a_ready = buffer_x1_nodeOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_13_a_valid = buffer_x1_nodeOut_12_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_opcode = buffer_x1_nodeOut_12_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_param = buffer_x1_nodeOut_12_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_size = buffer_x1_nodeOut_12_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_source = buffer_x1_nodeOut_12_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_address = buffer_x1_nodeOut_12_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_mask = buffer_x1_nodeOut_12_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_data = buffer_x1_nodeOut_12_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_corrupt = buffer_x1_nodeOut_12_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_13_d_ready = buffer_x1_nodeOut_12_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_12_d_valid = buffer_x1_nodeOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_opcode = buffer_x1_nodeOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_param = buffer_x1_nodeOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_size = buffer_x1_nodeOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_source = buffer_x1_nodeOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_sink = buffer_x1_nodeOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_denied = buffer_x1_nodeOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_data = buffer_x1_nodeOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_corrupt = buffer_x1_nodeOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_a_ready = buffer_x1_nodeOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_14_a_valid = buffer_x1_nodeOut_13_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_opcode = buffer_x1_nodeOut_13_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_param = buffer_x1_nodeOut_13_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_size = buffer_x1_nodeOut_13_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_source = buffer_x1_nodeOut_13_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_address = buffer_x1_nodeOut_13_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_mask = buffer_x1_nodeOut_13_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_data = buffer_x1_nodeOut_13_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_corrupt = buffer_x1_nodeOut_13_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_14_d_ready = buffer_x1_nodeOut_13_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_13_d_valid = buffer_x1_nodeOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_opcode = buffer_x1_nodeOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_param = buffer_x1_nodeOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_size = buffer_x1_nodeOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_source = buffer_x1_nodeOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_sink = buffer_x1_nodeOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_denied = buffer_x1_nodeOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_data = buffer_x1_nodeOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_corrupt = buffer_x1_nodeOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_a_ready = buffer_x1_nodeOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_15_a_valid = buffer_x1_nodeOut_14_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_opcode = buffer_x1_nodeOut_14_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_param = buffer_x1_nodeOut_14_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_size = buffer_x1_nodeOut_14_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_source = buffer_x1_nodeOut_14_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_address = buffer_x1_nodeOut_14_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_mask = buffer_x1_nodeOut_14_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_data = buffer_x1_nodeOut_14_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_corrupt = buffer_x1_nodeOut_14_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_15_d_ready = buffer_x1_nodeOut_14_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_14_d_valid = buffer_x1_nodeOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_opcode = buffer_x1_nodeOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_param = buffer_x1_nodeOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_size = buffer_x1_nodeOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_source = buffer_x1_nodeOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_sink = buffer_x1_nodeOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_denied = buffer_x1_nodeOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_data = buffer_x1_nodeOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_corrupt = buffer_x1_nodeOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_a_ready = buffer_x1_nodeOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_16_a_valid = buffer_x1_nodeOut_15_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_opcode = buffer_x1_nodeOut_15_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_param = buffer_x1_nodeOut_15_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_size = buffer_x1_nodeOut_15_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_source = buffer_x1_nodeOut_15_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_address = buffer_x1_nodeOut_15_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_mask = buffer_x1_nodeOut_15_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_data = buffer_x1_nodeOut_15_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_corrupt = buffer_x1_nodeOut_15_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_16_d_ready = buffer_x1_nodeOut_15_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_15_d_valid = buffer_x1_nodeOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_opcode = buffer_x1_nodeOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_param = buffer_x1_nodeOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_size = buffer_x1_nodeOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_source = buffer_x1_nodeOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_sink = buffer_x1_nodeOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_denied = buffer_x1_nodeOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_data = buffer_x1_nodeOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_corrupt = buffer_x1_nodeOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_a_ready = buffer_x1_nodeOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_17_a_valid = buffer_x1_nodeOut_16_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_opcode = buffer_x1_nodeOut_16_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_param = buffer_x1_nodeOut_16_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_size = buffer_x1_nodeOut_16_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_source = buffer_x1_nodeOut_16_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_address = buffer_x1_nodeOut_16_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_mask = buffer_x1_nodeOut_16_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_data = buffer_x1_nodeOut_16_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_corrupt = buffer_x1_nodeOut_16_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_17_d_ready = buffer_x1_nodeOut_16_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_16_d_valid = buffer_x1_nodeOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_opcode = buffer_x1_nodeOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_param = buffer_x1_nodeOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_size = buffer_x1_nodeOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_source = buffer_x1_nodeOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_sink = buffer_x1_nodeOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_denied = buffer_x1_nodeOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_data = buffer_x1_nodeOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_corrupt = buffer_x1_nodeOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_a_ready = buffer_x1_nodeOut_17_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_a_valid = buffer_x1_nodeOut_17_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_opcode = buffer_x1_nodeOut_17_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_param = buffer_x1_nodeOut_17_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_size = buffer_x1_nodeOut_17_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_source = buffer_x1_nodeOut_17_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_address = buffer_x1_nodeOut_17_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_mask = buffer_x1_nodeOut_17_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_data = buffer_x1_nodeOut_17_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_18_b_ready = buffer_x1_nodeOut_17_b_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_17_b_valid = buffer_x1_nodeOut_17_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_opcode = buffer_x1_nodeOut_17_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_param = buffer_x1_nodeOut_17_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_size = buffer_x1_nodeOut_17_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_source = buffer_x1_nodeOut_17_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_address = buffer_x1_nodeOut_17_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_mask = buffer_x1_nodeOut_17_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_data = buffer_x1_nodeOut_17_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_corrupt = buffer_x1_nodeOut_17_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_c_ready = buffer_x1_nodeOut_17_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_c_valid = buffer_x1_nodeOut_17_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_opcode = buffer_x1_nodeOut_17_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_param = buffer_x1_nodeOut_17_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_size = buffer_x1_nodeOut_17_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_source = buffer_x1_nodeOut_17_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_address = buffer_x1_nodeOut_17_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_data = buffer_x1_nodeOut_17_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_18_d_ready = buffer_x1_nodeOut_17_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_17_d_valid = buffer_x1_nodeOut_17_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_opcode = buffer_x1_nodeOut_17_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_param = buffer_x1_nodeOut_17_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_size = buffer_x1_nodeOut_17_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_source = buffer_x1_nodeOut_17_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_sink = buffer_x1_nodeOut_17_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_denied = buffer_x1_nodeOut_17_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_data = buffer_x1_nodeOut_17_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_corrupt = buffer_x1_nodeOut_17_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_e_ready = buffer_x1_nodeOut_17_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_e_valid = buffer_x1_nodeOut_17_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_e_bits_sink = buffer_x1_nodeOut_17_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_0_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_0_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_1_a_ready = buffer_x1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_a_valid = buffer_x1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_opcode = buffer_x1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_param = buffer_x1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_size = buffer_x1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_source = buffer_x1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_address = buffer_x1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_mask = buffer_x1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_data = buffer_x1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_corrupt = buffer_x1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_d_ready = buffer_x1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_1_d_valid = buffer_x1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_opcode = buffer_x1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_param = buffer_x1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_size = buffer_x1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_source = buffer_x1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_sink = buffer_x1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_denied = buffer_x1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_data = buffer_x1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_corrupt = buffer_x1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_2_a_ready = buffer_x1_nodeIn_1_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_1_a_valid = buffer_x1_nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_opcode = buffer_x1_nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_param = buffer_x1_nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_size = buffer_x1_nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_source = buffer_x1_nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_address = buffer_x1_nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_mask = buffer_x1_nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_data = buffer_x1_nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_corrupt = buffer_x1_nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_d_ready = buffer_x1_nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_2_d_valid = buffer_x1_nodeIn_1_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_opcode = buffer_x1_nodeIn_1_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_param = buffer_x1_nodeIn_1_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_size = buffer_x1_nodeIn_1_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_source = buffer_x1_nodeIn_1_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_sink = buffer_x1_nodeIn_1_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_denied = buffer_x1_nodeIn_1_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_data = buffer_x1_nodeIn_1_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_corrupt = buffer_x1_nodeIn_1_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_3_a_ready = buffer_x1_nodeIn_2_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_2_a_valid = buffer_x1_nodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_opcode = buffer_x1_nodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_param = buffer_x1_nodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_size = buffer_x1_nodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_source = buffer_x1_nodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_address = buffer_x1_nodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_mask = buffer_x1_nodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_data = buffer_x1_nodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_corrupt = buffer_x1_nodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_d_ready = buffer_x1_nodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_3_d_valid = buffer_x1_nodeIn_2_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_opcode = buffer_x1_nodeIn_2_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_param = buffer_x1_nodeIn_2_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_size = buffer_x1_nodeIn_2_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_source = buffer_x1_nodeIn_2_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_sink = buffer_x1_nodeIn_2_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_denied = buffer_x1_nodeIn_2_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_data = buffer_x1_nodeIn_2_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_corrupt = buffer_x1_nodeIn_2_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_4_a_ready = buffer_x1_nodeIn_3_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_3_a_valid = buffer_x1_nodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_opcode = buffer_x1_nodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_param = buffer_x1_nodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_size = buffer_x1_nodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_source = buffer_x1_nodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_address = buffer_x1_nodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_mask = buffer_x1_nodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_data = buffer_x1_nodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_corrupt = buffer_x1_nodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_d_ready = buffer_x1_nodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_4_d_valid = buffer_x1_nodeIn_3_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_opcode = buffer_x1_nodeIn_3_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_param = buffer_x1_nodeIn_3_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_size = buffer_x1_nodeIn_3_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_source = buffer_x1_nodeIn_3_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_sink = buffer_x1_nodeIn_3_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_denied = buffer_x1_nodeIn_3_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_data = buffer_x1_nodeIn_3_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_corrupt = buffer_x1_nodeIn_3_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_5_a_ready = buffer_x1_nodeIn_4_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_4_a_valid = buffer_x1_nodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_opcode = buffer_x1_nodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_param = buffer_x1_nodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_size = buffer_x1_nodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_source = buffer_x1_nodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_address = buffer_x1_nodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_mask = buffer_x1_nodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_data = buffer_x1_nodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_corrupt = buffer_x1_nodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_d_ready = buffer_x1_nodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_5_d_valid = buffer_x1_nodeIn_4_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_opcode = buffer_x1_nodeIn_4_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_param = buffer_x1_nodeIn_4_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_size = buffer_x1_nodeIn_4_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_source = buffer_x1_nodeIn_4_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_sink = buffer_x1_nodeIn_4_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_denied = buffer_x1_nodeIn_4_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_data = buffer_x1_nodeIn_4_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_corrupt = buffer_x1_nodeIn_4_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_6_a_ready = buffer_x1_nodeIn_5_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_5_a_valid = buffer_x1_nodeIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_opcode = buffer_x1_nodeIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_param = buffer_x1_nodeIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_size = buffer_x1_nodeIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_source = buffer_x1_nodeIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_address = buffer_x1_nodeIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_mask = buffer_x1_nodeIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_data = buffer_x1_nodeIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_corrupt = buffer_x1_nodeIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_d_ready = buffer_x1_nodeIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_6_d_valid = buffer_x1_nodeIn_5_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_opcode = buffer_x1_nodeIn_5_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_param = buffer_x1_nodeIn_5_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_size = buffer_x1_nodeIn_5_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_source = buffer_x1_nodeIn_5_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_sink = buffer_x1_nodeIn_5_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_denied = buffer_x1_nodeIn_5_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_data = buffer_x1_nodeIn_5_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_corrupt = buffer_x1_nodeIn_5_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_7_a_ready = buffer_x1_nodeIn_6_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_6_a_valid = buffer_x1_nodeIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_opcode = buffer_x1_nodeIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_param = buffer_x1_nodeIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_size = buffer_x1_nodeIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_source = buffer_x1_nodeIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_address = buffer_x1_nodeIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_mask = buffer_x1_nodeIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_data = buffer_x1_nodeIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_corrupt = buffer_x1_nodeIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_d_ready = buffer_x1_nodeIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_7_d_valid = buffer_x1_nodeIn_6_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_opcode = buffer_x1_nodeIn_6_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_param = buffer_x1_nodeIn_6_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_size = buffer_x1_nodeIn_6_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_source = buffer_x1_nodeIn_6_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_sink = buffer_x1_nodeIn_6_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_denied = buffer_x1_nodeIn_6_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_data = buffer_x1_nodeIn_6_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_corrupt = buffer_x1_nodeIn_6_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_8_a_ready = buffer_x1_nodeIn_7_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_7_a_valid = buffer_x1_nodeIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_opcode = buffer_x1_nodeIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_param = buffer_x1_nodeIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_size = buffer_x1_nodeIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_source = buffer_x1_nodeIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_address = buffer_x1_nodeIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_mask = buffer_x1_nodeIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_data = buffer_x1_nodeIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_corrupt = buffer_x1_nodeIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_d_ready = buffer_x1_nodeIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_8_d_valid = buffer_x1_nodeIn_7_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_opcode = buffer_x1_nodeIn_7_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_param = buffer_x1_nodeIn_7_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_size = buffer_x1_nodeIn_7_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_source = buffer_x1_nodeIn_7_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_sink = buffer_x1_nodeIn_7_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_denied = buffer_x1_nodeIn_7_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_data = buffer_x1_nodeIn_7_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_corrupt = buffer_x1_nodeIn_7_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_9_a_ready = buffer_x1_nodeIn_8_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_8_a_valid = buffer_x1_nodeIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_opcode = buffer_x1_nodeIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_param = buffer_x1_nodeIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_size = buffer_x1_nodeIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_source = buffer_x1_nodeIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_address = buffer_x1_nodeIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_mask = buffer_x1_nodeIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_data = buffer_x1_nodeIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_corrupt = buffer_x1_nodeIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_d_ready = buffer_x1_nodeIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_9_d_valid = buffer_x1_nodeIn_8_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_opcode = buffer_x1_nodeIn_8_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_param = buffer_x1_nodeIn_8_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_size = buffer_x1_nodeIn_8_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_source = buffer_x1_nodeIn_8_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_sink = buffer_x1_nodeIn_8_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_denied = buffer_x1_nodeIn_8_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_data = buffer_x1_nodeIn_8_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_corrupt = buffer_x1_nodeIn_8_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_10_a_ready = buffer_x1_nodeIn_9_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_9_a_valid = buffer_x1_nodeIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_opcode = buffer_x1_nodeIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_param = buffer_x1_nodeIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_size = buffer_x1_nodeIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_source = buffer_x1_nodeIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_address = buffer_x1_nodeIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_mask = buffer_x1_nodeIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_data = buffer_x1_nodeIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_corrupt = buffer_x1_nodeIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_d_ready = buffer_x1_nodeIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_10_d_valid = buffer_x1_nodeIn_9_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_opcode = buffer_x1_nodeIn_9_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_param = buffer_x1_nodeIn_9_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_size = buffer_x1_nodeIn_9_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_source = buffer_x1_nodeIn_9_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_sink = buffer_x1_nodeIn_9_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_denied = buffer_x1_nodeIn_9_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_data = buffer_x1_nodeIn_9_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_corrupt = buffer_x1_nodeIn_9_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_11_a_ready = buffer_x1_nodeIn_10_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_10_a_valid = buffer_x1_nodeIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_opcode = buffer_x1_nodeIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_param = buffer_x1_nodeIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_size = buffer_x1_nodeIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_source = buffer_x1_nodeIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_address = buffer_x1_nodeIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_mask = buffer_x1_nodeIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_data = buffer_x1_nodeIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_corrupt = buffer_x1_nodeIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_d_ready = buffer_x1_nodeIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_11_d_valid = buffer_x1_nodeIn_10_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_opcode = buffer_x1_nodeIn_10_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_param = buffer_x1_nodeIn_10_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_size = buffer_x1_nodeIn_10_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_source = buffer_x1_nodeIn_10_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_sink = buffer_x1_nodeIn_10_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_denied = buffer_x1_nodeIn_10_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_data = buffer_x1_nodeIn_10_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_corrupt = buffer_x1_nodeIn_10_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_12_a_ready = buffer_x1_nodeIn_11_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_11_a_valid = buffer_x1_nodeIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_opcode = buffer_x1_nodeIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_param = buffer_x1_nodeIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_size = buffer_x1_nodeIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_source = buffer_x1_nodeIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_address = buffer_x1_nodeIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_mask = buffer_x1_nodeIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_data = buffer_x1_nodeIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_corrupt = buffer_x1_nodeIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_d_ready = buffer_x1_nodeIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_12_d_valid = buffer_x1_nodeIn_11_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_opcode = buffer_x1_nodeIn_11_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_param = buffer_x1_nodeIn_11_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_size = buffer_x1_nodeIn_11_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_source = buffer_x1_nodeIn_11_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_sink = buffer_x1_nodeIn_11_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_denied = buffer_x1_nodeIn_11_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_data = buffer_x1_nodeIn_11_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_corrupt = buffer_x1_nodeIn_11_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_13_a_ready = buffer_x1_nodeIn_12_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_12_a_valid = buffer_x1_nodeIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_opcode = buffer_x1_nodeIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_param = buffer_x1_nodeIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_size = buffer_x1_nodeIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_source = buffer_x1_nodeIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_address = buffer_x1_nodeIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_mask = buffer_x1_nodeIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_data = buffer_x1_nodeIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_corrupt = buffer_x1_nodeIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_d_ready = buffer_x1_nodeIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_13_d_valid = buffer_x1_nodeIn_12_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_opcode = buffer_x1_nodeIn_12_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_param = buffer_x1_nodeIn_12_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_size = buffer_x1_nodeIn_12_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_source = buffer_x1_nodeIn_12_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_sink = buffer_x1_nodeIn_12_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_denied = buffer_x1_nodeIn_12_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_data = buffer_x1_nodeIn_12_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_corrupt = buffer_x1_nodeIn_12_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_14_a_ready = buffer_x1_nodeIn_13_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_13_a_valid = buffer_x1_nodeIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_opcode = buffer_x1_nodeIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_param = buffer_x1_nodeIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_size = buffer_x1_nodeIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_source = buffer_x1_nodeIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_address = buffer_x1_nodeIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_mask = buffer_x1_nodeIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_data = buffer_x1_nodeIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_corrupt = buffer_x1_nodeIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_d_ready = buffer_x1_nodeIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_14_d_valid = buffer_x1_nodeIn_13_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_opcode = buffer_x1_nodeIn_13_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_param = buffer_x1_nodeIn_13_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_size = buffer_x1_nodeIn_13_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_source = buffer_x1_nodeIn_13_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_sink = buffer_x1_nodeIn_13_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_denied = buffer_x1_nodeIn_13_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_data = buffer_x1_nodeIn_13_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_corrupt = buffer_x1_nodeIn_13_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_15_a_ready = buffer_x1_nodeIn_14_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_14_a_valid = buffer_x1_nodeIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_opcode = buffer_x1_nodeIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_param = buffer_x1_nodeIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_size = buffer_x1_nodeIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_source = buffer_x1_nodeIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_address = buffer_x1_nodeIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_mask = buffer_x1_nodeIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_data = buffer_x1_nodeIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_corrupt = buffer_x1_nodeIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_d_ready = buffer_x1_nodeIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_15_d_valid = buffer_x1_nodeIn_14_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_opcode = buffer_x1_nodeIn_14_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_param = buffer_x1_nodeIn_14_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_size = buffer_x1_nodeIn_14_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_source = buffer_x1_nodeIn_14_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_sink = buffer_x1_nodeIn_14_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_denied = buffer_x1_nodeIn_14_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_data = buffer_x1_nodeIn_14_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_corrupt = buffer_x1_nodeIn_14_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_16_a_ready = buffer_x1_nodeIn_15_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_15_a_valid = buffer_x1_nodeIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_opcode = buffer_x1_nodeIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_param = buffer_x1_nodeIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_size = buffer_x1_nodeIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_source = buffer_x1_nodeIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_address = buffer_x1_nodeIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_mask = buffer_x1_nodeIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_data = buffer_x1_nodeIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_corrupt = buffer_x1_nodeIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_d_ready = buffer_x1_nodeIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_16_d_valid = buffer_x1_nodeIn_15_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_opcode = buffer_x1_nodeIn_15_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_param = buffer_x1_nodeIn_15_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_size = buffer_x1_nodeIn_15_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_source = buffer_x1_nodeIn_15_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_sink = buffer_x1_nodeIn_15_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_denied = buffer_x1_nodeIn_15_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_data = buffer_x1_nodeIn_15_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_corrupt = buffer_x1_nodeIn_15_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_17_a_ready = buffer_x1_nodeIn_16_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_16_a_valid = buffer_x1_nodeIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_opcode = buffer_x1_nodeIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_param = buffer_x1_nodeIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_size = buffer_x1_nodeIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_source = buffer_x1_nodeIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_address = buffer_x1_nodeIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_mask = buffer_x1_nodeIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_data = buffer_x1_nodeIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_corrupt = buffer_x1_nodeIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_d_ready = buffer_x1_nodeIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_17_d_valid = buffer_x1_nodeIn_16_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_opcode = buffer_x1_nodeIn_16_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_param = buffer_x1_nodeIn_16_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_size = buffer_x1_nodeIn_16_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_source = buffer_x1_nodeIn_16_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_sink = buffer_x1_nodeIn_16_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_denied = buffer_x1_nodeIn_16_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_data = buffer_x1_nodeIn_16_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_corrupt = buffer_x1_nodeIn_16_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_a_ready = buffer_x1_nodeIn_17_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_a_valid = buffer_x1_nodeIn_17_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_opcode = buffer_x1_nodeIn_17_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_param = buffer_x1_nodeIn_17_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_size = buffer_x1_nodeIn_17_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_source = buffer_x1_nodeIn_17_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_address = buffer_x1_nodeIn_17_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_mask = buffer_x1_nodeIn_17_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_data = buffer_x1_nodeIn_17_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_b_ready = buffer_x1_nodeIn_17_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_18_b_valid = buffer_x1_nodeIn_17_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_opcode = buffer_x1_nodeIn_17_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_param = buffer_x1_nodeIn_17_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_size = buffer_x1_nodeIn_17_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_source = buffer_x1_nodeIn_17_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_address = buffer_x1_nodeIn_17_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_mask = buffer_x1_nodeIn_17_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_data = buffer_x1_nodeIn_17_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_corrupt = buffer_x1_nodeIn_17_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_c_ready = buffer_x1_nodeIn_17_c_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_c_valid = buffer_x1_nodeIn_17_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_opcode = buffer_x1_nodeIn_17_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_param = buffer_x1_nodeIn_17_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_size = buffer_x1_nodeIn_17_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_source = buffer_x1_nodeIn_17_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_address = buffer_x1_nodeIn_17_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_data = buffer_x1_nodeIn_17_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_d_ready = buffer_x1_nodeIn_17_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_18_d_valid = buffer_x1_nodeIn_17_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_opcode = buffer_x1_nodeIn_17_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_param = buffer_x1_nodeIn_17_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_size = buffer_x1_nodeIn_17_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_source = buffer_x1_nodeIn_17_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_sink = buffer_x1_nodeIn_17_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_denied = buffer_x1_nodeIn_17_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_data = buffer_x1_nodeIn_17_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_corrupt = buffer_x1_nodeIn_17_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_e_ready = buffer_x1_nodeIn_17_e_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_e_valid = buffer_x1_nodeIn_17_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_e_bits_sink = buffer_x1_nodeIn_17_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_a_ready = x1_tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_valid = x1_tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_opcode = x1_tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_param = x1_tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_size = x1_tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_source = x1_tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_address = x1_tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_mask = x1_tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_data = x1_tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_corrupt = x1_tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_d_ready = x1_tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_d_valid = x1_tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_d_bits_opcode = x1_tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_d_bits_param = x1_tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_d_bits_size = x1_tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_d_bits_source = x1_tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_d_bits_sink = x1_tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_d_bits_denied = x1_tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_d_bits_data = x1_tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_d_bits_corrupt = x1_tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_a_ready = x1_tlOtherMastersNodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_valid = x1_tlOtherMastersNodeOut_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_1_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_opcode = x1_tlOtherMastersNodeOut_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_1_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_param = x1_tlOtherMastersNodeOut_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_1_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_size = x1_tlOtherMastersNodeOut_1_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_1_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_source = x1_tlOtherMastersNodeOut_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_1_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_address = x1_tlOtherMastersNodeOut_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_1_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_mask = x1_tlOtherMastersNodeOut_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_1_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_data = x1_tlOtherMastersNodeOut_1_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_corrupt = x1_tlOtherMastersNodeOut_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_d_ready = x1_tlOtherMastersNodeOut_1_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_d_valid = x1_tlOtherMastersNodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_1_d_bits_opcode = x1_tlOtherMastersNodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_1_d_bits_param = x1_tlOtherMastersNodeOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_1_d_bits_size = x1_tlOtherMastersNodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_1_d_bits_source = x1_tlOtherMastersNodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_1_d_bits_sink = x1_tlOtherMastersNodeOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_d_bits_denied = x1_tlOtherMastersNodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_1_d_bits_data = x1_tlOtherMastersNodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_d_bits_corrupt = x1_tlOtherMastersNodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_a_ready = x1_tlOtherMastersNodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_valid = x1_tlOtherMastersNodeOut_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_2_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_opcode = x1_tlOtherMastersNodeOut_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_2_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_param = x1_tlOtherMastersNodeOut_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_2_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_size = x1_tlOtherMastersNodeOut_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_2_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_source = x1_tlOtherMastersNodeOut_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_2_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_address = x1_tlOtherMastersNodeOut_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_2_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_mask = x1_tlOtherMastersNodeOut_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_2_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_data = x1_tlOtherMastersNodeOut_2_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_corrupt = x1_tlOtherMastersNodeOut_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_d_ready = x1_tlOtherMastersNodeOut_2_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_d_valid = x1_tlOtherMastersNodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_2_d_bits_opcode = x1_tlOtherMastersNodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_2_d_bits_param = x1_tlOtherMastersNodeOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_2_d_bits_size = x1_tlOtherMastersNodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_2_d_bits_source = x1_tlOtherMastersNodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_2_d_bits_sink = x1_tlOtherMastersNodeOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_d_bits_denied = x1_tlOtherMastersNodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_2_d_bits_data = x1_tlOtherMastersNodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_d_bits_corrupt = x1_tlOtherMastersNodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_a_ready = x1_tlOtherMastersNodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_valid = x1_tlOtherMastersNodeOut_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_3_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_opcode = x1_tlOtherMastersNodeOut_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_3_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_param = x1_tlOtherMastersNodeOut_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_3_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_size = x1_tlOtherMastersNodeOut_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_3_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_source = x1_tlOtherMastersNodeOut_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_3_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_address = x1_tlOtherMastersNodeOut_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_3_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_mask = x1_tlOtherMastersNodeOut_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_3_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_data = x1_tlOtherMastersNodeOut_3_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_corrupt = x1_tlOtherMastersNodeOut_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_d_ready = x1_tlOtherMastersNodeOut_3_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_d_valid = x1_tlOtherMastersNodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_3_d_bits_opcode = x1_tlOtherMastersNodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_3_d_bits_param = x1_tlOtherMastersNodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_3_d_bits_size = x1_tlOtherMastersNodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_3_d_bits_source = x1_tlOtherMastersNodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_3_d_bits_sink = x1_tlOtherMastersNodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_d_bits_denied = x1_tlOtherMastersNodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_3_d_bits_data = x1_tlOtherMastersNodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_d_bits_corrupt = x1_tlOtherMastersNodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_a_ready = x1_tlOtherMastersNodeOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_valid = x1_tlOtherMastersNodeOut_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_4_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_opcode = x1_tlOtherMastersNodeOut_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_4_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_param = x1_tlOtherMastersNodeOut_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_4_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_size = x1_tlOtherMastersNodeOut_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_4_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_source = x1_tlOtherMastersNodeOut_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_4_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_address = x1_tlOtherMastersNodeOut_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_4_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_mask = x1_tlOtherMastersNodeOut_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_4_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_data = x1_tlOtherMastersNodeOut_4_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_corrupt = x1_tlOtherMastersNodeOut_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_d_ready = x1_tlOtherMastersNodeOut_4_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_d_valid = x1_tlOtherMastersNodeOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_4_d_bits_opcode = x1_tlOtherMastersNodeOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_4_d_bits_param = x1_tlOtherMastersNodeOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_4_d_bits_size = x1_tlOtherMastersNodeOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_4_d_bits_source = x1_tlOtherMastersNodeOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_4_d_bits_sink = x1_tlOtherMastersNodeOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_d_bits_denied = x1_tlOtherMastersNodeOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_4_d_bits_data = x1_tlOtherMastersNodeOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_d_bits_corrupt = x1_tlOtherMastersNodeOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_a_ready = x1_tlOtherMastersNodeOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_valid = x1_tlOtherMastersNodeOut_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_5_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_opcode = x1_tlOtherMastersNodeOut_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_5_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_param = x1_tlOtherMastersNodeOut_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_5_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_size = x1_tlOtherMastersNodeOut_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_5_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_source = x1_tlOtherMastersNodeOut_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_5_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_address = x1_tlOtherMastersNodeOut_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_5_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_mask = x1_tlOtherMastersNodeOut_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_5_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_data = x1_tlOtherMastersNodeOut_5_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_corrupt = x1_tlOtherMastersNodeOut_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_d_ready = x1_tlOtherMastersNodeOut_5_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_d_valid = x1_tlOtherMastersNodeOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_5_d_bits_opcode = x1_tlOtherMastersNodeOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_5_d_bits_param = x1_tlOtherMastersNodeOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_5_d_bits_size = x1_tlOtherMastersNodeOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_5_d_bits_source = x1_tlOtherMastersNodeOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_5_d_bits_sink = x1_tlOtherMastersNodeOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_d_bits_denied = x1_tlOtherMastersNodeOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_5_d_bits_data = x1_tlOtherMastersNodeOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_d_bits_corrupt = x1_tlOtherMastersNodeOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_a_ready = x1_tlOtherMastersNodeOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_valid = x1_tlOtherMastersNodeOut_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_6_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_opcode = x1_tlOtherMastersNodeOut_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_6_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_param = x1_tlOtherMastersNodeOut_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_6_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_size = x1_tlOtherMastersNodeOut_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_6_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_source = x1_tlOtherMastersNodeOut_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_6_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_address = x1_tlOtherMastersNodeOut_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_6_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_mask = x1_tlOtherMastersNodeOut_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_6_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_data = x1_tlOtherMastersNodeOut_6_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_corrupt = x1_tlOtherMastersNodeOut_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_d_ready = x1_tlOtherMastersNodeOut_6_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_d_valid = x1_tlOtherMastersNodeOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_6_d_bits_opcode = x1_tlOtherMastersNodeOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_6_d_bits_param = x1_tlOtherMastersNodeOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_6_d_bits_size = x1_tlOtherMastersNodeOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_6_d_bits_source = x1_tlOtherMastersNodeOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_6_d_bits_sink = x1_tlOtherMastersNodeOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_d_bits_denied = x1_tlOtherMastersNodeOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_6_d_bits_data = x1_tlOtherMastersNodeOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_d_bits_corrupt = x1_tlOtherMastersNodeOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_a_ready = x1_tlOtherMastersNodeOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_valid = x1_tlOtherMastersNodeOut_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_7_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_opcode = x1_tlOtherMastersNodeOut_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_7_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_param = x1_tlOtherMastersNodeOut_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_7_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_size = x1_tlOtherMastersNodeOut_7_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_7_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_source = x1_tlOtherMastersNodeOut_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_7_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_address = x1_tlOtherMastersNodeOut_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_7_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_mask = x1_tlOtherMastersNodeOut_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_7_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_data = x1_tlOtherMastersNodeOut_7_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_corrupt = x1_tlOtherMastersNodeOut_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_d_ready = x1_tlOtherMastersNodeOut_7_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_d_valid = x1_tlOtherMastersNodeOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_7_d_bits_opcode = x1_tlOtherMastersNodeOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_7_d_bits_param = x1_tlOtherMastersNodeOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_7_d_bits_size = x1_tlOtherMastersNodeOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_7_d_bits_source = x1_tlOtherMastersNodeOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_7_d_bits_sink = x1_tlOtherMastersNodeOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_d_bits_denied = x1_tlOtherMastersNodeOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_7_d_bits_data = x1_tlOtherMastersNodeOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_d_bits_corrupt = x1_tlOtherMastersNodeOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_a_ready = x1_tlOtherMastersNodeOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_valid = x1_tlOtherMastersNodeOut_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_8_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_opcode = x1_tlOtherMastersNodeOut_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_8_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_param = x1_tlOtherMastersNodeOut_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_8_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_size = x1_tlOtherMastersNodeOut_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_8_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_source = x1_tlOtherMastersNodeOut_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_8_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_address = x1_tlOtherMastersNodeOut_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_8_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_mask = x1_tlOtherMastersNodeOut_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_8_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_data = x1_tlOtherMastersNodeOut_8_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_corrupt = x1_tlOtherMastersNodeOut_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_d_ready = x1_tlOtherMastersNodeOut_8_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_d_valid = x1_tlOtherMastersNodeOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_8_d_bits_opcode = x1_tlOtherMastersNodeOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_8_d_bits_param = x1_tlOtherMastersNodeOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_8_d_bits_size = x1_tlOtherMastersNodeOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_8_d_bits_source = x1_tlOtherMastersNodeOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_8_d_bits_sink = x1_tlOtherMastersNodeOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_d_bits_denied = x1_tlOtherMastersNodeOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_8_d_bits_data = x1_tlOtherMastersNodeOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_d_bits_corrupt = x1_tlOtherMastersNodeOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_a_ready = x1_tlOtherMastersNodeOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_valid = x1_tlOtherMastersNodeOut_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_9_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_opcode = x1_tlOtherMastersNodeOut_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_9_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_param = x1_tlOtherMastersNodeOut_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_9_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_size = x1_tlOtherMastersNodeOut_9_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_9_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_source = x1_tlOtherMastersNodeOut_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_9_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_address = x1_tlOtherMastersNodeOut_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_9_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_mask = x1_tlOtherMastersNodeOut_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_9_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_data = x1_tlOtherMastersNodeOut_9_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_corrupt = x1_tlOtherMastersNodeOut_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_d_ready = x1_tlOtherMastersNodeOut_9_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_d_valid = x1_tlOtherMastersNodeOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_9_d_bits_opcode = x1_tlOtherMastersNodeOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_9_d_bits_param = x1_tlOtherMastersNodeOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_9_d_bits_size = x1_tlOtherMastersNodeOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_9_d_bits_source = x1_tlOtherMastersNodeOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_9_d_bits_sink = x1_tlOtherMastersNodeOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_d_bits_denied = x1_tlOtherMastersNodeOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_9_d_bits_data = x1_tlOtherMastersNodeOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_d_bits_corrupt = x1_tlOtherMastersNodeOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_a_ready = x1_tlOtherMastersNodeOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_valid = x1_tlOtherMastersNodeOut_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_10_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_opcode = x1_tlOtherMastersNodeOut_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_10_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_param = x1_tlOtherMastersNodeOut_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_10_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_size = x1_tlOtherMastersNodeOut_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_10_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_source = x1_tlOtherMastersNodeOut_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_10_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_address = x1_tlOtherMastersNodeOut_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_10_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_mask = x1_tlOtherMastersNodeOut_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_10_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_data = x1_tlOtherMastersNodeOut_10_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_corrupt = x1_tlOtherMastersNodeOut_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_d_ready = x1_tlOtherMastersNodeOut_10_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_d_valid = x1_tlOtherMastersNodeOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_10_d_bits_opcode = x1_tlOtherMastersNodeOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_10_d_bits_param = x1_tlOtherMastersNodeOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_10_d_bits_size = x1_tlOtherMastersNodeOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_10_d_bits_source = x1_tlOtherMastersNodeOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_10_d_bits_sink = x1_tlOtherMastersNodeOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_d_bits_denied = x1_tlOtherMastersNodeOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_10_d_bits_data = x1_tlOtherMastersNodeOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_d_bits_corrupt = x1_tlOtherMastersNodeOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_a_ready = x1_tlOtherMastersNodeOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_valid = x1_tlOtherMastersNodeOut_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_11_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_opcode = x1_tlOtherMastersNodeOut_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_11_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_param = x1_tlOtherMastersNodeOut_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_11_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_size = x1_tlOtherMastersNodeOut_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_11_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_source = x1_tlOtherMastersNodeOut_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_11_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_address = x1_tlOtherMastersNodeOut_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_11_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_mask = x1_tlOtherMastersNodeOut_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_11_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_data = x1_tlOtherMastersNodeOut_11_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_corrupt = x1_tlOtherMastersNodeOut_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_d_ready = x1_tlOtherMastersNodeOut_11_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_d_valid = x1_tlOtherMastersNodeOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_11_d_bits_opcode = x1_tlOtherMastersNodeOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_11_d_bits_param = x1_tlOtherMastersNodeOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_11_d_bits_size = x1_tlOtherMastersNodeOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_11_d_bits_source = x1_tlOtherMastersNodeOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_11_d_bits_sink = x1_tlOtherMastersNodeOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_d_bits_denied = x1_tlOtherMastersNodeOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_11_d_bits_data = x1_tlOtherMastersNodeOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_d_bits_corrupt = x1_tlOtherMastersNodeOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_a_ready = x1_tlOtherMastersNodeOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_valid = x1_tlOtherMastersNodeOut_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_12_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_opcode = x1_tlOtherMastersNodeOut_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_12_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_param = x1_tlOtherMastersNodeOut_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_12_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_size = x1_tlOtherMastersNodeOut_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_12_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_source = x1_tlOtherMastersNodeOut_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_12_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_address = x1_tlOtherMastersNodeOut_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_12_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_mask = x1_tlOtherMastersNodeOut_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_12_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_data = x1_tlOtherMastersNodeOut_12_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_corrupt = x1_tlOtherMastersNodeOut_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_d_ready = x1_tlOtherMastersNodeOut_12_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_d_valid = x1_tlOtherMastersNodeOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_12_d_bits_opcode = x1_tlOtherMastersNodeOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_12_d_bits_param = x1_tlOtherMastersNodeOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_12_d_bits_size = x1_tlOtherMastersNodeOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_12_d_bits_source = x1_tlOtherMastersNodeOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_12_d_bits_sink = x1_tlOtherMastersNodeOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_d_bits_denied = x1_tlOtherMastersNodeOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_12_d_bits_data = x1_tlOtherMastersNodeOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_d_bits_corrupt = x1_tlOtherMastersNodeOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_a_ready = x1_tlOtherMastersNodeOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_valid = x1_tlOtherMastersNodeOut_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_13_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_opcode = x1_tlOtherMastersNodeOut_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_13_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_param = x1_tlOtherMastersNodeOut_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_13_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_size = x1_tlOtherMastersNodeOut_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_13_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_source = x1_tlOtherMastersNodeOut_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_13_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_address = x1_tlOtherMastersNodeOut_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_13_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_mask = x1_tlOtherMastersNodeOut_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_13_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_data = x1_tlOtherMastersNodeOut_13_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_corrupt = x1_tlOtherMastersNodeOut_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_d_ready = x1_tlOtherMastersNodeOut_13_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_d_valid = x1_tlOtherMastersNodeOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_13_d_bits_opcode = x1_tlOtherMastersNodeOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_13_d_bits_param = x1_tlOtherMastersNodeOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_13_d_bits_size = x1_tlOtherMastersNodeOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_13_d_bits_source = x1_tlOtherMastersNodeOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_13_d_bits_sink = x1_tlOtherMastersNodeOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_d_bits_denied = x1_tlOtherMastersNodeOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_13_d_bits_data = x1_tlOtherMastersNodeOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_d_bits_corrupt = x1_tlOtherMastersNodeOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_a_ready = x1_tlOtherMastersNodeOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_valid = x1_tlOtherMastersNodeOut_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_14_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_opcode = x1_tlOtherMastersNodeOut_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_14_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_param = x1_tlOtherMastersNodeOut_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_14_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_size = x1_tlOtherMastersNodeOut_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_14_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_source = x1_tlOtherMastersNodeOut_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_14_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_address = x1_tlOtherMastersNodeOut_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_14_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_mask = x1_tlOtherMastersNodeOut_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_14_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_data = x1_tlOtherMastersNodeOut_14_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_corrupt = x1_tlOtherMastersNodeOut_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_d_ready = x1_tlOtherMastersNodeOut_14_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_d_valid = x1_tlOtherMastersNodeOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_14_d_bits_opcode = x1_tlOtherMastersNodeOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_14_d_bits_param = x1_tlOtherMastersNodeOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_14_d_bits_size = x1_tlOtherMastersNodeOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_14_d_bits_source = x1_tlOtherMastersNodeOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_14_d_bits_sink = x1_tlOtherMastersNodeOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_d_bits_denied = x1_tlOtherMastersNodeOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_14_d_bits_data = x1_tlOtherMastersNodeOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_d_bits_corrupt = x1_tlOtherMastersNodeOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_a_ready = x1_tlOtherMastersNodeOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_valid = x1_tlOtherMastersNodeOut_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_15_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_opcode = x1_tlOtherMastersNodeOut_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_15_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_param = x1_tlOtherMastersNodeOut_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_15_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_size = x1_tlOtherMastersNodeOut_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_15_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_source = x1_tlOtherMastersNodeOut_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_15_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_address = x1_tlOtherMastersNodeOut_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_15_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_mask = x1_tlOtherMastersNodeOut_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_15_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_data = x1_tlOtherMastersNodeOut_15_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_corrupt = x1_tlOtherMastersNodeOut_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_d_ready = x1_tlOtherMastersNodeOut_15_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_d_valid = x1_tlOtherMastersNodeOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_15_d_bits_opcode = x1_tlOtherMastersNodeOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_15_d_bits_param = x1_tlOtherMastersNodeOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_15_d_bits_size = x1_tlOtherMastersNodeOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_15_d_bits_source = x1_tlOtherMastersNodeOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_15_d_bits_sink = x1_tlOtherMastersNodeOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_d_bits_denied = x1_tlOtherMastersNodeOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_15_d_bits_data = x1_tlOtherMastersNodeOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_d_bits_corrupt = x1_tlOtherMastersNodeOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_a_ready = x1_tlOtherMastersNodeOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_valid = x1_tlOtherMastersNodeOut_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_16_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_opcode = x1_tlOtherMastersNodeOut_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_16_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_param = x1_tlOtherMastersNodeOut_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_16_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_size = x1_tlOtherMastersNodeOut_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_16_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_source = x1_tlOtherMastersNodeOut_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_16_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_address = x1_tlOtherMastersNodeOut_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_16_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_mask = x1_tlOtherMastersNodeOut_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_16_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_data = x1_tlOtherMastersNodeOut_16_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_corrupt = x1_tlOtherMastersNodeOut_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_d_ready = x1_tlOtherMastersNodeOut_16_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_d_valid = x1_tlOtherMastersNodeOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_16_d_bits_opcode = x1_tlOtherMastersNodeOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_16_d_bits_param = x1_tlOtherMastersNodeOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_16_d_bits_size = x1_tlOtherMastersNodeOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_16_d_bits_source = x1_tlOtherMastersNodeOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_16_d_bits_sink = x1_tlOtherMastersNodeOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_d_bits_denied = x1_tlOtherMastersNodeOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_16_d_bits_data = x1_tlOtherMastersNodeOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_d_bits_corrupt = x1_tlOtherMastersNodeOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_a_ready = x1_tlOtherMastersNodeOut_17_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_valid = x1_tlOtherMastersNodeOut_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_opcode = x1_tlOtherMastersNodeOut_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_param = x1_tlOtherMastersNodeOut_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_17_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_size = x1_tlOtherMastersNodeOut_17_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_17_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_source = x1_tlOtherMastersNodeOut_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_17_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_address = x1_tlOtherMastersNodeOut_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_17_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_mask = x1_tlOtherMastersNodeOut_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_17_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_data = x1_tlOtherMastersNodeOut_17_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_b_ready = x1_tlOtherMastersNodeOut_17_b_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_b_valid = x1_tlOtherMastersNodeOut_17_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_b_bits_opcode = x1_tlOtherMastersNodeOut_17_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_b_bits_param = x1_tlOtherMastersNodeOut_17_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_17_b_bits_size = x1_tlOtherMastersNodeOut_17_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_b_bits_source = x1_tlOtherMastersNodeOut_17_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] x1_tlOtherMastersNodeIn_17_b_bits_address = x1_tlOtherMastersNodeOut_17_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] x1_tlOtherMastersNodeIn_17_b_bits_mask = x1_tlOtherMastersNodeOut_17_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_17_b_bits_data = x1_tlOtherMastersNodeOut_17_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_b_bits_corrupt = x1_tlOtherMastersNodeOut_17_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_c_ready = x1_tlOtherMastersNodeOut_17_c_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_valid = x1_tlOtherMastersNodeOut_17_c_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_opcode = x1_tlOtherMastersNodeOut_17_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_param = x1_tlOtherMastersNodeOut_17_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_17_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_size = x1_tlOtherMastersNodeOut_17_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_17_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_source = x1_tlOtherMastersNodeOut_17_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_17_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_address = x1_tlOtherMastersNodeOut_17_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_17_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_data = x1_tlOtherMastersNodeOut_17_c_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_d_ready = x1_tlOtherMastersNodeOut_17_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_d_valid = x1_tlOtherMastersNodeOut_17_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_d_bits_opcode = x1_tlOtherMastersNodeOut_17_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_d_bits_param = x1_tlOtherMastersNodeOut_17_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_17_d_bits_size = x1_tlOtherMastersNodeOut_17_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_d_bits_source = x1_tlOtherMastersNodeOut_17_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_d_bits_sink = x1_tlOtherMastersNodeOut_17_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_d_bits_denied = x1_tlOtherMastersNodeOut_17_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_17_d_bits_data = x1_tlOtherMastersNodeOut_17_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_d_bits_corrupt = x1_tlOtherMastersNodeOut_17_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_e_ready = x1_tlOtherMastersNodeOut_17_e_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_e_valid = x1_tlOtherMastersNodeOut_17_e_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_e_bits_sink = x1_tlOtherMastersNodeOut_17_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_valid = x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_opcode = x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_param = x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_size = x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_source = x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_address = x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_mask = x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_data = x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_corrupt = x1_tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_d_ready = x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_valid = x1_tlOtherMastersNodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_opcode = x1_tlOtherMastersNodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_param = x1_tlOtherMastersNodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_size = x1_tlOtherMastersNodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_source = x1_tlOtherMastersNodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_address = x1_tlOtherMastersNodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_mask = x1_tlOtherMastersNodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_data = x1_tlOtherMastersNodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_corrupt = x1_tlOtherMastersNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_d_ready = x1_tlOtherMastersNodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_valid = x1_tlOtherMastersNodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_opcode = x1_tlOtherMastersNodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_param = x1_tlOtherMastersNodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_size = x1_tlOtherMastersNodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_source = x1_tlOtherMastersNodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_address = x1_tlOtherMastersNodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_mask = x1_tlOtherMastersNodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_data = x1_tlOtherMastersNodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_corrupt = x1_tlOtherMastersNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_d_ready = x1_tlOtherMastersNodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_valid = x1_tlOtherMastersNodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_opcode = x1_tlOtherMastersNodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_param = x1_tlOtherMastersNodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_size = x1_tlOtherMastersNodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_source = x1_tlOtherMastersNodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_address = x1_tlOtherMastersNodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_mask = x1_tlOtherMastersNodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_data = x1_tlOtherMastersNodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_corrupt = x1_tlOtherMastersNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_d_ready = x1_tlOtherMastersNodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_valid = x1_tlOtherMastersNodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_opcode = x1_tlOtherMastersNodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_param = x1_tlOtherMastersNodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_size = x1_tlOtherMastersNodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_source = x1_tlOtherMastersNodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_address = x1_tlOtherMastersNodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_mask = x1_tlOtherMastersNodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_data = x1_tlOtherMastersNodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_corrupt = x1_tlOtherMastersNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_d_ready = x1_tlOtherMastersNodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_valid = x1_tlOtherMastersNodeIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_opcode = x1_tlOtherMastersNodeIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_param = x1_tlOtherMastersNodeIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_size = x1_tlOtherMastersNodeIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_source = x1_tlOtherMastersNodeIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_address = x1_tlOtherMastersNodeIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_mask = x1_tlOtherMastersNodeIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_data = x1_tlOtherMastersNodeIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_corrupt = x1_tlOtherMastersNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_d_ready = x1_tlOtherMastersNodeIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_valid = x1_tlOtherMastersNodeIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_opcode = x1_tlOtherMastersNodeIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_param = x1_tlOtherMastersNodeIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_size = x1_tlOtherMastersNodeIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_source = x1_tlOtherMastersNodeIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_address = x1_tlOtherMastersNodeIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_mask = x1_tlOtherMastersNodeIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_data = x1_tlOtherMastersNodeIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_corrupt = x1_tlOtherMastersNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_d_ready = x1_tlOtherMastersNodeIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_valid = x1_tlOtherMastersNodeIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_opcode = x1_tlOtherMastersNodeIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_param = x1_tlOtherMastersNodeIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_size = x1_tlOtherMastersNodeIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_source = x1_tlOtherMastersNodeIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_address = x1_tlOtherMastersNodeIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_mask = x1_tlOtherMastersNodeIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_data = x1_tlOtherMastersNodeIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_corrupt = x1_tlOtherMastersNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_d_ready = x1_tlOtherMastersNodeIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_valid = x1_tlOtherMastersNodeIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_opcode = x1_tlOtherMastersNodeIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_param = x1_tlOtherMastersNodeIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_size = x1_tlOtherMastersNodeIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_source = x1_tlOtherMastersNodeIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_address = x1_tlOtherMastersNodeIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_mask = x1_tlOtherMastersNodeIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_data = x1_tlOtherMastersNodeIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_corrupt = x1_tlOtherMastersNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_d_ready = x1_tlOtherMastersNodeIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_valid = x1_tlOtherMastersNodeIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_opcode = x1_tlOtherMastersNodeIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_param = x1_tlOtherMastersNodeIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_size = x1_tlOtherMastersNodeIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_source = x1_tlOtherMastersNodeIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_address = x1_tlOtherMastersNodeIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_mask = x1_tlOtherMastersNodeIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_data = x1_tlOtherMastersNodeIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_corrupt = x1_tlOtherMastersNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_d_ready = x1_tlOtherMastersNodeIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_valid = x1_tlOtherMastersNodeIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_opcode = x1_tlOtherMastersNodeIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_param = x1_tlOtherMastersNodeIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_size = x1_tlOtherMastersNodeIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_source = x1_tlOtherMastersNodeIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_address = x1_tlOtherMastersNodeIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_mask = x1_tlOtherMastersNodeIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_data = x1_tlOtherMastersNodeIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_corrupt = x1_tlOtherMastersNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_d_ready = x1_tlOtherMastersNodeIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_valid = x1_tlOtherMastersNodeIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_opcode = x1_tlOtherMastersNodeIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_param = x1_tlOtherMastersNodeIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_size = x1_tlOtherMastersNodeIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_source = x1_tlOtherMastersNodeIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_address = x1_tlOtherMastersNodeIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_mask = x1_tlOtherMastersNodeIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_data = x1_tlOtherMastersNodeIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_corrupt = x1_tlOtherMastersNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_d_ready = x1_tlOtherMastersNodeIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_valid = x1_tlOtherMastersNodeIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_opcode = x1_tlOtherMastersNodeIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_param = x1_tlOtherMastersNodeIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_size = x1_tlOtherMastersNodeIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_source = x1_tlOtherMastersNodeIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_address = x1_tlOtherMastersNodeIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_mask = x1_tlOtherMastersNodeIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_data = x1_tlOtherMastersNodeIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_corrupt = x1_tlOtherMastersNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_d_ready = x1_tlOtherMastersNodeIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_valid = x1_tlOtherMastersNodeIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_opcode = x1_tlOtherMastersNodeIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_param = x1_tlOtherMastersNodeIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_size = x1_tlOtherMastersNodeIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_source = x1_tlOtherMastersNodeIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_address = x1_tlOtherMastersNodeIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_mask = x1_tlOtherMastersNodeIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_data = x1_tlOtherMastersNodeIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_corrupt = x1_tlOtherMastersNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_d_ready = x1_tlOtherMastersNodeIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_valid = x1_tlOtherMastersNodeIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_opcode = x1_tlOtherMastersNodeIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_param = x1_tlOtherMastersNodeIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_size = x1_tlOtherMastersNodeIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_source = x1_tlOtherMastersNodeIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_address = x1_tlOtherMastersNodeIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_mask = x1_tlOtherMastersNodeIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_data = x1_tlOtherMastersNodeIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_corrupt = x1_tlOtherMastersNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_d_ready = x1_tlOtherMastersNodeIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_valid = x1_tlOtherMastersNodeIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_opcode = x1_tlOtherMastersNodeIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_param = x1_tlOtherMastersNodeIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_size = x1_tlOtherMastersNodeIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_source = x1_tlOtherMastersNodeIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_address = x1_tlOtherMastersNodeIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_mask = x1_tlOtherMastersNodeIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_data = x1_tlOtherMastersNodeIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_corrupt = x1_tlOtherMastersNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_d_ready = x1_tlOtherMastersNodeIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_valid = x1_tlOtherMastersNodeIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_opcode = x1_tlOtherMastersNodeIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_param = x1_tlOtherMastersNodeIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_size = x1_tlOtherMastersNodeIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_source = x1_tlOtherMastersNodeIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_address = x1_tlOtherMastersNodeIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_mask = x1_tlOtherMastersNodeIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_data = x1_tlOtherMastersNodeIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_corrupt = x1_tlOtherMastersNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_d_ready = x1_tlOtherMastersNodeIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_valid = x1_tlOtherMastersNodeIn_17_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_opcode = x1_tlOtherMastersNodeIn_17_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_param = x1_tlOtherMastersNodeIn_17_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_size = x1_tlOtherMastersNodeIn_17_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_source = x1_tlOtherMastersNodeIn_17_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_address = x1_tlOtherMastersNodeIn_17_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_mask = x1_tlOtherMastersNodeIn_17_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_data = x1_tlOtherMastersNodeIn_17_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_b_ready = x1_tlOtherMastersNodeIn_17_b_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_valid = x1_tlOtherMastersNodeIn_17_c_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_opcode = x1_tlOtherMastersNodeIn_17_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_param = x1_tlOtherMastersNodeIn_17_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_size = x1_tlOtherMastersNodeIn_17_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_source = x1_tlOtherMastersNodeIn_17_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_address = x1_tlOtherMastersNodeIn_17_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_data = x1_tlOtherMastersNodeIn_17_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_d_ready = x1_tlOtherMastersNodeIn_17_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_e_valid = x1_tlOtherMastersNodeIn_17_e_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_e_bits_sink = x1_tlOtherMastersNodeIn_17_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (x1_tlOtherMastersNodeIn_17_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (x1_tlOtherMastersNodeIn_17_a_valid), .auto_anon_out_a_bits_opcode (x1_tlOtherMastersNodeIn_17_a_bits_opcode), .auto_anon_out_a_bits_param (x1_tlOtherMastersNodeIn_17_a_bits_param), .auto_anon_out_a_bits_size (x1_tlOtherMastersNodeIn_17_a_bits_size), .auto_anon_out_a_bits_source (x1_tlOtherMastersNodeIn_17_a_bits_source), .auto_anon_out_a_bits_address (x1_tlOtherMastersNodeIn_17_a_bits_address), .auto_anon_out_a_bits_mask (x1_tlOtherMastersNodeIn_17_a_bits_mask), .auto_anon_out_a_bits_data (x1_tlOtherMastersNodeIn_17_a_bits_data), .auto_anon_out_b_ready (x1_tlOtherMastersNodeIn_17_b_ready), .auto_anon_out_b_valid (x1_tlOtherMastersNodeIn_17_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (x1_tlOtherMastersNodeIn_17_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (x1_tlOtherMastersNodeIn_17_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (x1_tlOtherMastersNodeIn_17_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (x1_tlOtherMastersNodeIn_17_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (x1_tlOtherMastersNodeIn_17_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (x1_tlOtherMastersNodeIn_17_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (x1_tlOtherMastersNodeIn_17_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (x1_tlOtherMastersNodeIn_17_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (x1_tlOtherMastersNodeIn_17_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (x1_tlOtherMastersNodeIn_17_c_valid), .auto_anon_out_c_bits_opcode (x1_tlOtherMastersNodeIn_17_c_bits_opcode), .auto_anon_out_c_bits_param (x1_tlOtherMastersNodeIn_17_c_bits_param), .auto_anon_out_c_bits_size (x1_tlOtherMastersNodeIn_17_c_bits_size), .auto_anon_out_c_bits_source (x1_tlOtherMastersNodeIn_17_c_bits_source), .auto_anon_out_c_bits_address (x1_tlOtherMastersNodeIn_17_c_bits_address), .auto_anon_out_c_bits_data (x1_tlOtherMastersNodeIn_17_c_bits_data), .auto_anon_out_d_ready (x1_tlOtherMastersNodeIn_17_d_ready), .auto_anon_out_d_valid (x1_tlOtherMastersNodeIn_17_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (x1_tlOtherMastersNodeIn_17_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (x1_tlOtherMastersNodeIn_17_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (x1_tlOtherMastersNodeIn_17_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (x1_tlOtherMastersNodeIn_17_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (x1_tlOtherMastersNodeIn_17_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (x1_tlOtherMastersNodeIn_17_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (x1_tlOtherMastersNodeIn_17_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (x1_tlOtherMastersNodeIn_17_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (x1_tlOtherMastersNodeIn_17_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (x1_tlOtherMastersNodeIn_17_e_valid), .auto_anon_out_e_bits_sink (x1_tlOtherMastersNodeIn_17_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[HellaCache.scala:292:25] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_18_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_18_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_18_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_18_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_18_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_18_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_18_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_18_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_18_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_18_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_18_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_18_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_18_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_18_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_18_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_18_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_18_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_18_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_18_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_18_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_18_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_18_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_18_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_18_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_18_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_18_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_18_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_18_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_18_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_18_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_18_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_18_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_18_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_18_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_18_status_v), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_18_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_18_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_18_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_18_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_18_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_18_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_18_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_18_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_18_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_18_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_18_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_18_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_18_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_18_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_18_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_18_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_18_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_18_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_18_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_18_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_18_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_18_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_18_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_18_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_18_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_18_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_18_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_18_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_18_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_18_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_18_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_18_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_18_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_18_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_18_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_18_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_18_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_18_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_18_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_18_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_18_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_18_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_18_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_18_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_18_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_18_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_18_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_18_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_18_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_18_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_18_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_18_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_18_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_18_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_18_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_18_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_18_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_18_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_18_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_18_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_18_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_18_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_18_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_18_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_18_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_18_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_18_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_18_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_18_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_18_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_18_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_18_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_18_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_18_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_18_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_18_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_18_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_18_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_18_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_18_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_18_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_18_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_18_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_18_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_18_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_18_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_18_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_18_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_18_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_18_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_18_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_18_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_18_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_18_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_18_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_18_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_18_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_18_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_18_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_18_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_18_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_18_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_18_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_18_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_18_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_18_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_18_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_18_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_18_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_18_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_18_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_18_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_18_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_18_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_18_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_18_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_18_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_18_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_18_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_18_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_18_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_18_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_18_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] ZstdCompressor zstd_compressor ( // @[Configs.scala:62:39] .clock (clock), .reset (reset), .auto_tl_out_17_a_ready (x1_tlOtherMastersNodeIn_16_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_17_a_valid (x1_tlOtherMastersNodeIn_16_a_valid), .auto_tl_out_17_a_bits_opcode (x1_tlOtherMastersNodeIn_16_a_bits_opcode), .auto_tl_out_17_a_bits_param (x1_tlOtherMastersNodeIn_16_a_bits_param), .auto_tl_out_17_a_bits_size (x1_tlOtherMastersNodeIn_16_a_bits_size), .auto_tl_out_17_a_bits_source (x1_tlOtherMastersNodeIn_16_a_bits_source), .auto_tl_out_17_a_bits_address (x1_tlOtherMastersNodeIn_16_a_bits_address), .auto_tl_out_17_a_bits_mask (x1_tlOtherMastersNodeIn_16_a_bits_mask), .auto_tl_out_17_a_bits_data (x1_tlOtherMastersNodeIn_16_a_bits_data), .auto_tl_out_17_a_bits_corrupt (x1_tlOtherMastersNodeIn_16_a_bits_corrupt), .auto_tl_out_17_d_ready (x1_tlOtherMastersNodeIn_16_d_ready), .auto_tl_out_17_d_valid (x1_tlOtherMastersNodeIn_16_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_opcode (x1_tlOtherMastersNodeIn_16_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_param (x1_tlOtherMastersNodeIn_16_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_size (x1_tlOtherMastersNodeIn_16_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_source (x1_tlOtherMastersNodeIn_16_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_sink (x1_tlOtherMastersNodeIn_16_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_denied (x1_tlOtherMastersNodeIn_16_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_data (x1_tlOtherMastersNodeIn_16_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_corrupt (x1_tlOtherMastersNodeIn_16_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_16_a_ready (x1_tlOtherMastersNodeIn_15_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_16_a_valid (x1_tlOtherMastersNodeIn_15_a_valid), .auto_tl_out_16_a_bits_opcode (x1_tlOtherMastersNodeIn_15_a_bits_opcode), .auto_tl_out_16_a_bits_param (x1_tlOtherMastersNodeIn_15_a_bits_param), .auto_tl_out_16_a_bits_size (x1_tlOtherMastersNodeIn_15_a_bits_size), .auto_tl_out_16_a_bits_source (x1_tlOtherMastersNodeIn_15_a_bits_source), .auto_tl_out_16_a_bits_address (x1_tlOtherMastersNodeIn_15_a_bits_address), .auto_tl_out_16_a_bits_mask (x1_tlOtherMastersNodeIn_15_a_bits_mask), .auto_tl_out_16_a_bits_data (x1_tlOtherMastersNodeIn_15_a_bits_data), .auto_tl_out_16_a_bits_corrupt (x1_tlOtherMastersNodeIn_15_a_bits_corrupt), .auto_tl_out_16_d_ready (x1_tlOtherMastersNodeIn_15_d_ready), .auto_tl_out_16_d_valid (x1_tlOtherMastersNodeIn_15_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_opcode (x1_tlOtherMastersNodeIn_15_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_param (x1_tlOtherMastersNodeIn_15_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_size (x1_tlOtherMastersNodeIn_15_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_source (x1_tlOtherMastersNodeIn_15_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_sink (x1_tlOtherMastersNodeIn_15_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_denied (x1_tlOtherMastersNodeIn_15_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_data (x1_tlOtherMastersNodeIn_15_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_corrupt (x1_tlOtherMastersNodeIn_15_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_15_a_ready (x1_tlOtherMastersNodeIn_14_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_15_a_valid (x1_tlOtherMastersNodeIn_14_a_valid), .auto_tl_out_15_a_bits_opcode (x1_tlOtherMastersNodeIn_14_a_bits_opcode), .auto_tl_out_15_a_bits_param (x1_tlOtherMastersNodeIn_14_a_bits_param), .auto_tl_out_15_a_bits_size (x1_tlOtherMastersNodeIn_14_a_bits_size), .auto_tl_out_15_a_bits_source (x1_tlOtherMastersNodeIn_14_a_bits_source), .auto_tl_out_15_a_bits_address (x1_tlOtherMastersNodeIn_14_a_bits_address), .auto_tl_out_15_a_bits_mask (x1_tlOtherMastersNodeIn_14_a_bits_mask), .auto_tl_out_15_a_bits_data (x1_tlOtherMastersNodeIn_14_a_bits_data), .auto_tl_out_15_a_bits_corrupt (x1_tlOtherMastersNodeIn_14_a_bits_corrupt), .auto_tl_out_15_d_ready (x1_tlOtherMastersNodeIn_14_d_ready), .auto_tl_out_15_d_valid (x1_tlOtherMastersNodeIn_14_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_opcode (x1_tlOtherMastersNodeIn_14_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_param (x1_tlOtherMastersNodeIn_14_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_size (x1_tlOtherMastersNodeIn_14_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_source (x1_tlOtherMastersNodeIn_14_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_sink (x1_tlOtherMastersNodeIn_14_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_denied (x1_tlOtherMastersNodeIn_14_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_data (x1_tlOtherMastersNodeIn_14_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_corrupt (x1_tlOtherMastersNodeIn_14_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_14_a_ready (x1_tlOtherMastersNodeIn_13_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_14_a_valid (x1_tlOtherMastersNodeIn_13_a_valid), .auto_tl_out_14_a_bits_opcode (x1_tlOtherMastersNodeIn_13_a_bits_opcode), .auto_tl_out_14_a_bits_param (x1_tlOtherMastersNodeIn_13_a_bits_param), .auto_tl_out_14_a_bits_size (x1_tlOtherMastersNodeIn_13_a_bits_size), .auto_tl_out_14_a_bits_source (x1_tlOtherMastersNodeIn_13_a_bits_source), .auto_tl_out_14_a_bits_address (x1_tlOtherMastersNodeIn_13_a_bits_address), .auto_tl_out_14_a_bits_mask (x1_tlOtherMastersNodeIn_13_a_bits_mask), .auto_tl_out_14_a_bits_data (x1_tlOtherMastersNodeIn_13_a_bits_data), .auto_tl_out_14_a_bits_corrupt (x1_tlOtherMastersNodeIn_13_a_bits_corrupt), .auto_tl_out_14_d_ready (x1_tlOtherMastersNodeIn_13_d_ready), .auto_tl_out_14_d_valid (x1_tlOtherMastersNodeIn_13_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_opcode (x1_tlOtherMastersNodeIn_13_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_param (x1_tlOtherMastersNodeIn_13_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_size (x1_tlOtherMastersNodeIn_13_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_source (x1_tlOtherMastersNodeIn_13_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_sink (x1_tlOtherMastersNodeIn_13_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_denied (x1_tlOtherMastersNodeIn_13_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_data (x1_tlOtherMastersNodeIn_13_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_corrupt (x1_tlOtherMastersNodeIn_13_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_13_a_ready (x1_tlOtherMastersNodeIn_12_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_13_a_valid (x1_tlOtherMastersNodeIn_12_a_valid), .auto_tl_out_13_a_bits_opcode (x1_tlOtherMastersNodeIn_12_a_bits_opcode), .auto_tl_out_13_a_bits_param (x1_tlOtherMastersNodeIn_12_a_bits_param), .auto_tl_out_13_a_bits_size (x1_tlOtherMastersNodeIn_12_a_bits_size), .auto_tl_out_13_a_bits_source (x1_tlOtherMastersNodeIn_12_a_bits_source), .auto_tl_out_13_a_bits_address (x1_tlOtherMastersNodeIn_12_a_bits_address), .auto_tl_out_13_a_bits_mask (x1_tlOtherMastersNodeIn_12_a_bits_mask), .auto_tl_out_13_a_bits_data (x1_tlOtherMastersNodeIn_12_a_bits_data), .auto_tl_out_13_a_bits_corrupt (x1_tlOtherMastersNodeIn_12_a_bits_corrupt), .auto_tl_out_13_d_ready (x1_tlOtherMastersNodeIn_12_d_ready), .auto_tl_out_13_d_valid (x1_tlOtherMastersNodeIn_12_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_opcode (x1_tlOtherMastersNodeIn_12_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_param (x1_tlOtherMastersNodeIn_12_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_size (x1_tlOtherMastersNodeIn_12_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_source (x1_tlOtherMastersNodeIn_12_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_sink (x1_tlOtherMastersNodeIn_12_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_denied (x1_tlOtherMastersNodeIn_12_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_data (x1_tlOtherMastersNodeIn_12_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_corrupt (x1_tlOtherMastersNodeIn_12_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_12_a_ready (x1_tlOtherMastersNodeIn_11_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_12_a_valid (x1_tlOtherMastersNodeIn_11_a_valid), .auto_tl_out_12_a_bits_opcode (x1_tlOtherMastersNodeIn_11_a_bits_opcode), .auto_tl_out_12_a_bits_param (x1_tlOtherMastersNodeIn_11_a_bits_param), .auto_tl_out_12_a_bits_size (x1_tlOtherMastersNodeIn_11_a_bits_size), .auto_tl_out_12_a_bits_source (x1_tlOtherMastersNodeIn_11_a_bits_source), .auto_tl_out_12_a_bits_address (x1_tlOtherMastersNodeIn_11_a_bits_address), .auto_tl_out_12_a_bits_mask (x1_tlOtherMastersNodeIn_11_a_bits_mask), .auto_tl_out_12_a_bits_data (x1_tlOtherMastersNodeIn_11_a_bits_data), .auto_tl_out_12_a_bits_corrupt (x1_tlOtherMastersNodeIn_11_a_bits_corrupt), .auto_tl_out_12_d_ready (x1_tlOtherMastersNodeIn_11_d_ready), .auto_tl_out_12_d_valid (x1_tlOtherMastersNodeIn_11_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_opcode (x1_tlOtherMastersNodeIn_11_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_param (x1_tlOtherMastersNodeIn_11_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_size (x1_tlOtherMastersNodeIn_11_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_source (x1_tlOtherMastersNodeIn_11_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_sink (x1_tlOtherMastersNodeIn_11_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_denied (x1_tlOtherMastersNodeIn_11_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_data (x1_tlOtherMastersNodeIn_11_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_corrupt (x1_tlOtherMastersNodeIn_11_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_11_a_ready (x1_tlOtherMastersNodeIn_10_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_11_a_valid (x1_tlOtherMastersNodeIn_10_a_valid), .auto_tl_out_11_a_bits_opcode (x1_tlOtherMastersNodeIn_10_a_bits_opcode), .auto_tl_out_11_a_bits_param (x1_tlOtherMastersNodeIn_10_a_bits_param), .auto_tl_out_11_a_bits_size (x1_tlOtherMastersNodeIn_10_a_bits_size), .auto_tl_out_11_a_bits_source (x1_tlOtherMastersNodeIn_10_a_bits_source), .auto_tl_out_11_a_bits_address (x1_tlOtherMastersNodeIn_10_a_bits_address), .auto_tl_out_11_a_bits_mask (x1_tlOtherMastersNodeIn_10_a_bits_mask), .auto_tl_out_11_a_bits_data (x1_tlOtherMastersNodeIn_10_a_bits_data), .auto_tl_out_11_a_bits_corrupt (x1_tlOtherMastersNodeIn_10_a_bits_corrupt), .auto_tl_out_11_d_ready (x1_tlOtherMastersNodeIn_10_d_ready), .auto_tl_out_11_d_valid (x1_tlOtherMastersNodeIn_10_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_opcode (x1_tlOtherMastersNodeIn_10_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_param (x1_tlOtherMastersNodeIn_10_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_size (x1_tlOtherMastersNodeIn_10_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_source (x1_tlOtherMastersNodeIn_10_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_sink (x1_tlOtherMastersNodeIn_10_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_denied (x1_tlOtherMastersNodeIn_10_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_data (x1_tlOtherMastersNodeIn_10_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_corrupt (x1_tlOtherMastersNodeIn_10_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_10_a_ready (x1_tlOtherMastersNodeIn_9_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_10_a_valid (x1_tlOtherMastersNodeIn_9_a_valid), .auto_tl_out_10_a_bits_opcode (x1_tlOtherMastersNodeIn_9_a_bits_opcode), .auto_tl_out_10_a_bits_param (x1_tlOtherMastersNodeIn_9_a_bits_param), .auto_tl_out_10_a_bits_size (x1_tlOtherMastersNodeIn_9_a_bits_size), .auto_tl_out_10_a_bits_source (x1_tlOtherMastersNodeIn_9_a_bits_source), .auto_tl_out_10_a_bits_address (x1_tlOtherMastersNodeIn_9_a_bits_address), .auto_tl_out_10_a_bits_mask (x1_tlOtherMastersNodeIn_9_a_bits_mask), .auto_tl_out_10_a_bits_data (x1_tlOtherMastersNodeIn_9_a_bits_data), .auto_tl_out_10_a_bits_corrupt (x1_tlOtherMastersNodeIn_9_a_bits_corrupt), .auto_tl_out_10_d_ready (x1_tlOtherMastersNodeIn_9_d_ready), .auto_tl_out_10_d_valid (x1_tlOtherMastersNodeIn_9_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_opcode (x1_tlOtherMastersNodeIn_9_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_param (x1_tlOtherMastersNodeIn_9_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_size (x1_tlOtherMastersNodeIn_9_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_source (x1_tlOtherMastersNodeIn_9_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_sink (x1_tlOtherMastersNodeIn_9_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_denied (x1_tlOtherMastersNodeIn_9_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_data (x1_tlOtherMastersNodeIn_9_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_corrupt (x1_tlOtherMastersNodeIn_9_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_9_a_ready (x1_tlOtherMastersNodeIn_8_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_9_a_valid (x1_tlOtherMastersNodeIn_8_a_valid), .auto_tl_out_9_a_bits_opcode (x1_tlOtherMastersNodeIn_8_a_bits_opcode), .auto_tl_out_9_a_bits_param (x1_tlOtherMastersNodeIn_8_a_bits_param), .auto_tl_out_9_a_bits_size (x1_tlOtherMastersNodeIn_8_a_bits_size), .auto_tl_out_9_a_bits_source (x1_tlOtherMastersNodeIn_8_a_bits_source), .auto_tl_out_9_a_bits_address (x1_tlOtherMastersNodeIn_8_a_bits_address), .auto_tl_out_9_a_bits_mask (x1_tlOtherMastersNodeIn_8_a_bits_mask), .auto_tl_out_9_a_bits_data (x1_tlOtherMastersNodeIn_8_a_bits_data), .auto_tl_out_9_a_bits_corrupt (x1_tlOtherMastersNodeIn_8_a_bits_corrupt), .auto_tl_out_9_d_ready (x1_tlOtherMastersNodeIn_8_d_ready), .auto_tl_out_9_d_valid (x1_tlOtherMastersNodeIn_8_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_opcode (x1_tlOtherMastersNodeIn_8_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_param (x1_tlOtherMastersNodeIn_8_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_size (x1_tlOtherMastersNodeIn_8_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_source (x1_tlOtherMastersNodeIn_8_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_sink (x1_tlOtherMastersNodeIn_8_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_denied (x1_tlOtherMastersNodeIn_8_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_data (x1_tlOtherMastersNodeIn_8_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_corrupt (x1_tlOtherMastersNodeIn_8_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_8_a_ready (x1_tlOtherMastersNodeIn_7_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_8_a_valid (x1_tlOtherMastersNodeIn_7_a_valid), .auto_tl_out_8_a_bits_opcode (x1_tlOtherMastersNodeIn_7_a_bits_opcode), .auto_tl_out_8_a_bits_param (x1_tlOtherMastersNodeIn_7_a_bits_param), .auto_tl_out_8_a_bits_size (x1_tlOtherMastersNodeIn_7_a_bits_size), .auto_tl_out_8_a_bits_source (x1_tlOtherMastersNodeIn_7_a_bits_source), .auto_tl_out_8_a_bits_address (x1_tlOtherMastersNodeIn_7_a_bits_address), .auto_tl_out_8_a_bits_mask (x1_tlOtherMastersNodeIn_7_a_bits_mask), .auto_tl_out_8_a_bits_data (x1_tlOtherMastersNodeIn_7_a_bits_data), .auto_tl_out_8_a_bits_corrupt (x1_tlOtherMastersNodeIn_7_a_bits_corrupt), .auto_tl_out_8_d_ready (x1_tlOtherMastersNodeIn_7_d_ready), .auto_tl_out_8_d_valid (x1_tlOtherMastersNodeIn_7_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_opcode (x1_tlOtherMastersNodeIn_7_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_param (x1_tlOtherMastersNodeIn_7_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_size (x1_tlOtherMastersNodeIn_7_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_source (x1_tlOtherMastersNodeIn_7_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_sink (x1_tlOtherMastersNodeIn_7_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_denied (x1_tlOtherMastersNodeIn_7_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_data (x1_tlOtherMastersNodeIn_7_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_corrupt (x1_tlOtherMastersNodeIn_7_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_7_a_ready (x1_tlOtherMastersNodeIn_6_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_7_a_valid (x1_tlOtherMastersNodeIn_6_a_valid), .auto_tl_out_7_a_bits_opcode (x1_tlOtherMastersNodeIn_6_a_bits_opcode), .auto_tl_out_7_a_bits_param (x1_tlOtherMastersNodeIn_6_a_bits_param), .auto_tl_out_7_a_bits_size (x1_tlOtherMastersNodeIn_6_a_bits_size), .auto_tl_out_7_a_bits_source (x1_tlOtherMastersNodeIn_6_a_bits_source), .auto_tl_out_7_a_bits_address (x1_tlOtherMastersNodeIn_6_a_bits_address), .auto_tl_out_7_a_bits_mask (x1_tlOtherMastersNodeIn_6_a_bits_mask), .auto_tl_out_7_a_bits_data (x1_tlOtherMastersNodeIn_6_a_bits_data), .auto_tl_out_7_a_bits_corrupt (x1_tlOtherMastersNodeIn_6_a_bits_corrupt), .auto_tl_out_7_d_ready (x1_tlOtherMastersNodeIn_6_d_ready), .auto_tl_out_7_d_valid (x1_tlOtherMastersNodeIn_6_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_opcode (x1_tlOtherMastersNodeIn_6_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_param (x1_tlOtherMastersNodeIn_6_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_size (x1_tlOtherMastersNodeIn_6_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_source (x1_tlOtherMastersNodeIn_6_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_sink (x1_tlOtherMastersNodeIn_6_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_denied (x1_tlOtherMastersNodeIn_6_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_data (x1_tlOtherMastersNodeIn_6_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_corrupt (x1_tlOtherMastersNodeIn_6_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_6_a_ready (x1_tlOtherMastersNodeIn_5_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_6_a_valid (x1_tlOtherMastersNodeIn_5_a_valid), .auto_tl_out_6_a_bits_opcode (x1_tlOtherMastersNodeIn_5_a_bits_opcode), .auto_tl_out_6_a_bits_param (x1_tlOtherMastersNodeIn_5_a_bits_param), .auto_tl_out_6_a_bits_size (x1_tlOtherMastersNodeIn_5_a_bits_size), .auto_tl_out_6_a_bits_source (x1_tlOtherMastersNodeIn_5_a_bits_source), .auto_tl_out_6_a_bits_address (x1_tlOtherMastersNodeIn_5_a_bits_address), .auto_tl_out_6_a_bits_mask (x1_tlOtherMastersNodeIn_5_a_bits_mask), .auto_tl_out_6_a_bits_data (x1_tlOtherMastersNodeIn_5_a_bits_data), .auto_tl_out_6_a_bits_corrupt (x1_tlOtherMastersNodeIn_5_a_bits_corrupt), .auto_tl_out_6_d_ready (x1_tlOtherMastersNodeIn_5_d_ready), .auto_tl_out_6_d_valid (x1_tlOtherMastersNodeIn_5_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_opcode (x1_tlOtherMastersNodeIn_5_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_param (x1_tlOtherMastersNodeIn_5_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_size (x1_tlOtherMastersNodeIn_5_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_source (x1_tlOtherMastersNodeIn_5_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_sink (x1_tlOtherMastersNodeIn_5_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_denied (x1_tlOtherMastersNodeIn_5_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_data (x1_tlOtherMastersNodeIn_5_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_corrupt (x1_tlOtherMastersNodeIn_5_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_5_a_ready (x1_tlOtherMastersNodeIn_4_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_5_a_valid (x1_tlOtherMastersNodeIn_4_a_valid), .auto_tl_out_5_a_bits_opcode (x1_tlOtherMastersNodeIn_4_a_bits_opcode), .auto_tl_out_5_a_bits_param (x1_tlOtherMastersNodeIn_4_a_bits_param), .auto_tl_out_5_a_bits_size (x1_tlOtherMastersNodeIn_4_a_bits_size), .auto_tl_out_5_a_bits_source (x1_tlOtherMastersNodeIn_4_a_bits_source), .auto_tl_out_5_a_bits_address (x1_tlOtherMastersNodeIn_4_a_bits_address), .auto_tl_out_5_a_bits_mask (x1_tlOtherMastersNodeIn_4_a_bits_mask), .auto_tl_out_5_a_bits_data (x1_tlOtherMastersNodeIn_4_a_bits_data), .auto_tl_out_5_a_bits_corrupt (x1_tlOtherMastersNodeIn_4_a_bits_corrupt), .auto_tl_out_5_d_ready (x1_tlOtherMastersNodeIn_4_d_ready), .auto_tl_out_5_d_valid (x1_tlOtherMastersNodeIn_4_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_opcode (x1_tlOtherMastersNodeIn_4_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_param (x1_tlOtherMastersNodeIn_4_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_size (x1_tlOtherMastersNodeIn_4_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_source (x1_tlOtherMastersNodeIn_4_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_sink (x1_tlOtherMastersNodeIn_4_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_denied (x1_tlOtherMastersNodeIn_4_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_data (x1_tlOtherMastersNodeIn_4_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_corrupt (x1_tlOtherMastersNodeIn_4_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_4_a_ready (x1_tlOtherMastersNodeIn_3_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_4_a_valid (x1_tlOtherMastersNodeIn_3_a_valid), .auto_tl_out_4_a_bits_opcode (x1_tlOtherMastersNodeIn_3_a_bits_opcode), .auto_tl_out_4_a_bits_param (x1_tlOtherMastersNodeIn_3_a_bits_param), .auto_tl_out_4_a_bits_size (x1_tlOtherMastersNodeIn_3_a_bits_size), .auto_tl_out_4_a_bits_source (x1_tlOtherMastersNodeIn_3_a_bits_source), .auto_tl_out_4_a_bits_address (x1_tlOtherMastersNodeIn_3_a_bits_address), .auto_tl_out_4_a_bits_mask (x1_tlOtherMastersNodeIn_3_a_bits_mask), .auto_tl_out_4_a_bits_data (x1_tlOtherMastersNodeIn_3_a_bits_data), .auto_tl_out_4_a_bits_corrupt (x1_tlOtherMastersNodeIn_3_a_bits_corrupt), .auto_tl_out_4_d_ready (x1_tlOtherMastersNodeIn_3_d_ready), .auto_tl_out_4_d_valid (x1_tlOtherMastersNodeIn_3_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_opcode (x1_tlOtherMastersNodeIn_3_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_param (x1_tlOtherMastersNodeIn_3_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_size (x1_tlOtherMastersNodeIn_3_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_source (x1_tlOtherMastersNodeIn_3_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_sink (x1_tlOtherMastersNodeIn_3_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_denied (x1_tlOtherMastersNodeIn_3_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_data (x1_tlOtherMastersNodeIn_3_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_corrupt (x1_tlOtherMastersNodeIn_3_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_3_a_ready (x1_tlOtherMastersNodeIn_2_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_3_a_valid (x1_tlOtherMastersNodeIn_2_a_valid), .auto_tl_out_3_a_bits_opcode (x1_tlOtherMastersNodeIn_2_a_bits_opcode), .auto_tl_out_3_a_bits_param (x1_tlOtherMastersNodeIn_2_a_bits_param), .auto_tl_out_3_a_bits_size (x1_tlOtherMastersNodeIn_2_a_bits_size), .auto_tl_out_3_a_bits_source (x1_tlOtherMastersNodeIn_2_a_bits_source), .auto_tl_out_3_a_bits_address (x1_tlOtherMastersNodeIn_2_a_bits_address), .auto_tl_out_3_a_bits_mask (x1_tlOtherMastersNodeIn_2_a_bits_mask), .auto_tl_out_3_a_bits_data (x1_tlOtherMastersNodeIn_2_a_bits_data), .auto_tl_out_3_a_bits_corrupt (x1_tlOtherMastersNodeIn_2_a_bits_corrupt), .auto_tl_out_3_d_ready (x1_tlOtherMastersNodeIn_2_d_ready), .auto_tl_out_3_d_valid (x1_tlOtherMastersNodeIn_2_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_opcode (x1_tlOtherMastersNodeIn_2_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_param (x1_tlOtherMastersNodeIn_2_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_size (x1_tlOtherMastersNodeIn_2_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_source (x1_tlOtherMastersNodeIn_2_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_sink (x1_tlOtherMastersNodeIn_2_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_denied (x1_tlOtherMastersNodeIn_2_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_data (x1_tlOtherMastersNodeIn_2_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_corrupt (x1_tlOtherMastersNodeIn_2_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_2_a_ready (x1_tlOtherMastersNodeIn_1_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_2_a_valid (x1_tlOtherMastersNodeIn_1_a_valid), .auto_tl_out_2_a_bits_opcode (x1_tlOtherMastersNodeIn_1_a_bits_opcode), .auto_tl_out_2_a_bits_param (x1_tlOtherMastersNodeIn_1_a_bits_param), .auto_tl_out_2_a_bits_size (x1_tlOtherMastersNodeIn_1_a_bits_size), .auto_tl_out_2_a_bits_source (x1_tlOtherMastersNodeIn_1_a_bits_source), .auto_tl_out_2_a_bits_address (x1_tlOtherMastersNodeIn_1_a_bits_address), .auto_tl_out_2_a_bits_mask (x1_tlOtherMastersNodeIn_1_a_bits_mask), .auto_tl_out_2_a_bits_data (x1_tlOtherMastersNodeIn_1_a_bits_data), .auto_tl_out_2_a_bits_corrupt (x1_tlOtherMastersNodeIn_1_a_bits_corrupt), .auto_tl_out_2_d_ready (x1_tlOtherMastersNodeIn_1_d_ready), .auto_tl_out_2_d_valid (x1_tlOtherMastersNodeIn_1_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_opcode (x1_tlOtherMastersNodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_param (x1_tlOtherMastersNodeIn_1_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_size (x1_tlOtherMastersNodeIn_1_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_source (x1_tlOtherMastersNodeIn_1_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_sink (x1_tlOtherMastersNodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_denied (x1_tlOtherMastersNodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_data (x1_tlOtherMastersNodeIn_1_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_corrupt (x1_tlOtherMastersNodeIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_1_a_ready (x1_tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_1_a_valid (x1_tlOtherMastersNodeIn_a_valid), .auto_tl_out_1_a_bits_opcode (x1_tlOtherMastersNodeIn_a_bits_opcode), .auto_tl_out_1_a_bits_param (x1_tlOtherMastersNodeIn_a_bits_param), .auto_tl_out_1_a_bits_size (x1_tlOtherMastersNodeIn_a_bits_size), .auto_tl_out_1_a_bits_source (x1_tlOtherMastersNodeIn_a_bits_source), .auto_tl_out_1_a_bits_address (x1_tlOtherMastersNodeIn_a_bits_address), .auto_tl_out_1_a_bits_mask (x1_tlOtherMastersNodeIn_a_bits_mask), .auto_tl_out_1_a_bits_data (x1_tlOtherMastersNodeIn_a_bits_data), .auto_tl_out_1_a_bits_corrupt (x1_tlOtherMastersNodeIn_a_bits_corrupt), .auto_tl_out_1_d_ready (x1_tlOtherMastersNodeIn_d_ready), .auto_tl_out_1_d_valid (x1_tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_opcode (x1_tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_param (x1_tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_size (x1_tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_source (x1_tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_sink (x1_tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_denied (x1_tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_data (x1_tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_corrupt (x1_tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_0_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_0_a_valid (tlOtherMastersNodeIn_a_valid), .auto_tl_out_0_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_tl_out_0_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_tl_out_0_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_tl_out_0_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_tl_out_0_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_tl_out_0_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_tl_out_0_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_tl_out_0_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt), .auto_tl_out_0_d_ready (tlOtherMastersNodeIn_d_ready), .auto_tl_out_0_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_cmd_ready (_zstd_compressor_io_cmd_ready), .io_cmd_valid (_cmdRouter_io_out_0_valid), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode), // @[LazyRoCC.scala:102:27] .io_cmd_bits_rs1 (_cmdRouter_io_out_0_bits_rs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_rs2 (_cmdRouter_io_out_0_bits_rs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_v (_cmdRouter_io_out_0_bits_status_v), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie), // @[LazyRoCC.scala:102:27] .io_resp_ready (_respArb_io_in_0_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_resp_valid (_zstd_compressor_io_resp_valid), .io_resp_bits_rd (_zstd_compressor_io_resp_bits_rd), .io_resp_bits_data (_zstd_compressor_io_resp_bits_data), .io_mem_req_ready (_dcIF_io_requestor_req_ready), // @[LazyRoCC.scala:106:24] .io_mem_resp_valid (_dcIF_io_requestor_resp_valid), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_size (_dcIF_io_requestor_resp_bits_size), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data (_dcIF_io_requestor_resp_bits_data), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data), // @[LazyRoCC.scala:106:24] .io_exception (_core_io_rocc_exception), // @[RocketTile.scala:147:20] .io_ptw_0_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_0_req_valid (_zstd_compressor_io_ptw_0_req_valid), .io_ptw_0_req_bits_bits_addr (_zstd_compressor_io_ptw_0_req_bits_bits_addr), .io_ptw_0_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_0_req_bits_bits_need_gpa), .io_ptw_0_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_0_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_0_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_0_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_0_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_0_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_0_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_0_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_0_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_0_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_0_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_0_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_0_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_0_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_0_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_0_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_0_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_0_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_0_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_0_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_0_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_0_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_0_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_0_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_1_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_1_req_valid (_zstd_compressor_io_ptw_1_req_valid), .io_ptw_1_req_bits_bits_addr (_zstd_compressor_io_ptw_1_req_bits_bits_addr), .io_ptw_1_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_1_req_bits_bits_need_gpa), .io_ptw_1_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_1_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_1_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_1_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_1_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_1_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_1_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_1_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_1_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_1_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_1_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_1_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_1_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_1_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_1_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_1_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_1_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_1_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_1_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_1_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_1_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_1_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_1_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_1_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_2_req_ready (_ptw_io_requestor_2_req_ready), // @[PTW.scala:802:19] .io_ptw_2_req_valid (_zstd_compressor_io_ptw_2_req_valid), .io_ptw_2_req_bits_bits_addr (_zstd_compressor_io_ptw_2_req_bits_bits_addr), .io_ptw_2_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_2_req_bits_bits_need_gpa), .io_ptw_2_resp_valid (_ptw_io_requestor_2_resp_valid), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_2_status_debug (_ptw_io_requestor_2_status_debug), // @[PTW.scala:802:19] .io_ptw_2_status_cease (_ptw_io_requestor_2_status_cease), // @[PTW.scala:802:19] .io_ptw_2_status_wfi (_ptw_io_requestor_2_status_wfi), // @[PTW.scala:802:19] .io_ptw_2_status_isa (_ptw_io_requestor_2_status_isa), // @[PTW.scala:802:19] .io_ptw_2_status_dprv (_ptw_io_requestor_2_status_dprv), // @[PTW.scala:802:19] .io_ptw_2_status_dv (_ptw_io_requestor_2_status_dv), // @[PTW.scala:802:19] .io_ptw_2_status_prv (_ptw_io_requestor_2_status_prv), // @[PTW.scala:802:19] .io_ptw_2_status_v (_ptw_io_requestor_2_status_v), // @[PTW.scala:802:19] .io_ptw_2_status_mpv (_ptw_io_requestor_2_status_mpv), // @[PTW.scala:802:19] .io_ptw_2_status_gva (_ptw_io_requestor_2_status_gva), // @[PTW.scala:802:19] .io_ptw_2_status_tsr (_ptw_io_requestor_2_status_tsr), // @[PTW.scala:802:19] .io_ptw_2_status_tw (_ptw_io_requestor_2_status_tw), // @[PTW.scala:802:19] .io_ptw_2_status_tvm (_ptw_io_requestor_2_status_tvm), // @[PTW.scala:802:19] .io_ptw_2_status_mxr (_ptw_io_requestor_2_status_mxr), // @[PTW.scala:802:19] .io_ptw_2_status_sum (_ptw_io_requestor_2_status_sum), // @[PTW.scala:802:19] .io_ptw_2_status_mprv (_ptw_io_requestor_2_status_mprv), // @[PTW.scala:802:19] .io_ptw_2_status_fs (_ptw_io_requestor_2_status_fs), // @[PTW.scala:802:19] .io_ptw_2_status_mpp (_ptw_io_requestor_2_status_mpp), // @[PTW.scala:802:19] .io_ptw_2_status_spp (_ptw_io_requestor_2_status_spp), // @[PTW.scala:802:19] .io_ptw_2_status_mpie (_ptw_io_requestor_2_status_mpie), // @[PTW.scala:802:19] .io_ptw_2_status_spie (_ptw_io_requestor_2_status_spie), // @[PTW.scala:802:19] .io_ptw_2_status_mie (_ptw_io_requestor_2_status_mie), // @[PTW.scala:802:19] .io_ptw_2_status_sie (_ptw_io_requestor_2_status_sie), // @[PTW.scala:802:19] .io_ptw_2_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_2_hstatus_spv (_ptw_io_requestor_2_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_2_hstatus_gva (_ptw_io_requestor_2_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_2_gstatus_debug (_ptw_io_requestor_2_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_2_gstatus_cease (_ptw_io_requestor_2_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_2_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_2_gstatus_isa (_ptw_io_requestor_2_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_2_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_dv (_ptw_io_requestor_2_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_prv (_ptw_io_requestor_2_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_v (_ptw_io_requestor_2_gstatus_v), // @[PTW.scala:802:19] .io_ptw_2_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_gva (_ptw_io_requestor_2_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_2_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tw (_ptw_io_requestor_2_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sum (_ptw_io_requestor_2_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_fs (_ptw_io_requestor_2_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_2_gstatus_vs (_ptw_io_requestor_2_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_2_gstatus_spp (_ptw_io_requestor_2_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_ube (_ptw_io_requestor_2_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_2_gstatus_spie (_ptw_io_requestor_2_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_upie (_ptw_io_requestor_2_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mie (_ptw_io_requestor_2_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_hie (_ptw_io_requestor_2_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sie (_ptw_io_requestor_2_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_uie (_ptw_io_requestor_2_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_3_req_ready (_ptw_io_requestor_3_req_ready), // @[PTW.scala:802:19] .io_ptw_3_req_valid (_zstd_compressor_io_ptw_3_req_valid), .io_ptw_3_req_bits_bits_addr (_zstd_compressor_io_ptw_3_req_bits_bits_addr), .io_ptw_3_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_3_req_bits_bits_need_gpa), .io_ptw_3_resp_valid (_ptw_io_requestor_3_resp_valid), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_ae_ptw (_ptw_io_requestor_3_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_ae_final (_ptw_io_requestor_3_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pf (_ptw_io_requestor_3_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gf (_ptw_io_requestor_3_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hr (_ptw_io_requestor_3_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hw (_ptw_io_requestor_3_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hx (_ptw_io_requestor_3_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_reserved_for_future (_ptw_io_requestor_3_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_ppn (_ptw_io_requestor_3_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_reserved_for_software (_ptw_io_requestor_3_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_d (_ptw_io_requestor_3_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_a (_ptw_io_requestor_3_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_g (_ptw_io_requestor_3_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_u (_ptw_io_requestor_3_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_x (_ptw_io_requestor_3_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_w (_ptw_io_requestor_3_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_r (_ptw_io_requestor_3_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_v (_ptw_io_requestor_3_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_level (_ptw_io_requestor_3_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_homogeneous (_ptw_io_requestor_3_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_valid (_ptw_io_requestor_3_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_bits (_ptw_io_requestor_3_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_is_pte (_ptw_io_requestor_3_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_3_ptbr_mode (_ptw_io_requestor_3_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_3_ptbr_ppn (_ptw_io_requestor_3_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_3_status_debug (_ptw_io_requestor_3_status_debug), // @[PTW.scala:802:19] .io_ptw_3_status_cease (_ptw_io_requestor_3_status_cease), // @[PTW.scala:802:19] .io_ptw_3_status_wfi (_ptw_io_requestor_3_status_wfi), // @[PTW.scala:802:19] .io_ptw_3_status_isa (_ptw_io_requestor_3_status_isa), // @[PTW.scala:802:19] .io_ptw_3_status_dprv (_ptw_io_requestor_3_status_dprv), // @[PTW.scala:802:19] .io_ptw_3_status_dv (_ptw_io_requestor_3_status_dv), // @[PTW.scala:802:19] .io_ptw_3_status_prv (_ptw_io_requestor_3_status_prv), // @[PTW.scala:802:19] .io_ptw_3_status_v (_ptw_io_requestor_3_status_v), // @[PTW.scala:802:19] .io_ptw_3_status_mpv (_ptw_io_requestor_3_status_mpv), // @[PTW.scala:802:19] .io_ptw_3_status_gva (_ptw_io_requestor_3_status_gva), // @[PTW.scala:802:19] .io_ptw_3_status_tsr (_ptw_io_requestor_3_status_tsr), // @[PTW.scala:802:19] .io_ptw_3_status_tw (_ptw_io_requestor_3_status_tw), // @[PTW.scala:802:19] .io_ptw_3_status_tvm (_ptw_io_requestor_3_status_tvm), // @[PTW.scala:802:19] .io_ptw_3_status_mxr (_ptw_io_requestor_3_status_mxr), // @[PTW.scala:802:19] .io_ptw_3_status_sum (_ptw_io_requestor_3_status_sum), // @[PTW.scala:802:19] .io_ptw_3_status_mprv (_ptw_io_requestor_3_status_mprv), // @[PTW.scala:802:19] .io_ptw_3_status_fs (_ptw_io_requestor_3_status_fs), // @[PTW.scala:802:19] .io_ptw_3_status_mpp (_ptw_io_requestor_3_status_mpp), // @[PTW.scala:802:19] .io_ptw_3_status_spp (_ptw_io_requestor_3_status_spp), // @[PTW.scala:802:19] .io_ptw_3_status_mpie (_ptw_io_requestor_3_status_mpie), // @[PTW.scala:802:19] .io_ptw_3_status_spie (_ptw_io_requestor_3_status_spie), // @[PTW.scala:802:19] .io_ptw_3_status_mie (_ptw_io_requestor_3_status_mie), // @[PTW.scala:802:19] .io_ptw_3_status_sie (_ptw_io_requestor_3_status_sie), // @[PTW.scala:802:19] .io_ptw_3_hstatus_spvp (_ptw_io_requestor_3_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_3_hstatus_spv (_ptw_io_requestor_3_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_3_hstatus_gva (_ptw_io_requestor_3_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_3_gstatus_debug (_ptw_io_requestor_3_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_3_gstatus_cease (_ptw_io_requestor_3_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_3_gstatus_wfi (_ptw_io_requestor_3_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_3_gstatus_isa (_ptw_io_requestor_3_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_3_gstatus_dprv (_ptw_io_requestor_3_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_dv (_ptw_io_requestor_3_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_prv (_ptw_io_requestor_3_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_v (_ptw_io_requestor_3_gstatus_v), // @[PTW.scala:802:19] .io_ptw_3_gstatus_zero2 (_ptw_io_requestor_3_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpv (_ptw_io_requestor_3_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_gva (_ptw_io_requestor_3_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mbe (_ptw_io_requestor_3_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sbe (_ptw_io_requestor_3_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sxl (_ptw_io_requestor_3_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_3_gstatus_zero1 (_ptw_io_requestor_3_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tsr (_ptw_io_requestor_3_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tw (_ptw_io_requestor_3_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tvm (_ptw_io_requestor_3_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mxr (_ptw_io_requestor_3_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sum (_ptw_io_requestor_3_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mprv (_ptw_io_requestor_3_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_fs (_ptw_io_requestor_3_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpp (_ptw_io_requestor_3_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_3_gstatus_vs (_ptw_io_requestor_3_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_3_gstatus_spp (_ptw_io_requestor_3_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpie (_ptw_io_requestor_3_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_ube (_ptw_io_requestor_3_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_3_gstatus_spie (_ptw_io_requestor_3_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_upie (_ptw_io_requestor_3_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mie (_ptw_io_requestor_3_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_hie (_ptw_io_requestor_3_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sie (_ptw_io_requestor_3_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_uie (_ptw_io_requestor_3_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_l (_ptw_io_requestor_3_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_a (_ptw_io_requestor_3_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_x (_ptw_io_requestor_3_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_w (_ptw_io_requestor_3_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_r (_ptw_io_requestor_3_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_addr (_ptw_io_requestor_3_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_mask (_ptw_io_requestor_3_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_l (_ptw_io_requestor_3_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_a (_ptw_io_requestor_3_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_x (_ptw_io_requestor_3_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_w (_ptw_io_requestor_3_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_r (_ptw_io_requestor_3_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_addr (_ptw_io_requestor_3_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_mask (_ptw_io_requestor_3_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_l (_ptw_io_requestor_3_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_a (_ptw_io_requestor_3_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_x (_ptw_io_requestor_3_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_w (_ptw_io_requestor_3_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_r (_ptw_io_requestor_3_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_addr (_ptw_io_requestor_3_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_mask (_ptw_io_requestor_3_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_l (_ptw_io_requestor_3_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_a (_ptw_io_requestor_3_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_x (_ptw_io_requestor_3_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_w (_ptw_io_requestor_3_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_r (_ptw_io_requestor_3_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_addr (_ptw_io_requestor_3_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_mask (_ptw_io_requestor_3_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_l (_ptw_io_requestor_3_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_a (_ptw_io_requestor_3_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_x (_ptw_io_requestor_3_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_w (_ptw_io_requestor_3_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_r (_ptw_io_requestor_3_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_addr (_ptw_io_requestor_3_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_mask (_ptw_io_requestor_3_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_l (_ptw_io_requestor_3_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_a (_ptw_io_requestor_3_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_x (_ptw_io_requestor_3_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_w (_ptw_io_requestor_3_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_r (_ptw_io_requestor_3_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_addr (_ptw_io_requestor_3_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_mask (_ptw_io_requestor_3_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_l (_ptw_io_requestor_3_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_a (_ptw_io_requestor_3_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_x (_ptw_io_requestor_3_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_w (_ptw_io_requestor_3_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_r (_ptw_io_requestor_3_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_addr (_ptw_io_requestor_3_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_mask (_ptw_io_requestor_3_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_l (_ptw_io_requestor_3_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_a (_ptw_io_requestor_3_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_x (_ptw_io_requestor_3_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_w (_ptw_io_requestor_3_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_r (_ptw_io_requestor_3_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_addr (_ptw_io_requestor_3_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_mask (_ptw_io_requestor_3_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_ren (_ptw_io_requestor_3_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_wen (_ptw_io_requestor_3_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_wdata (_ptw_io_requestor_3_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_value (_ptw_io_requestor_3_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_ren (_ptw_io_requestor_3_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_wen (_ptw_io_requestor_3_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_wdata (_ptw_io_requestor_3_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_value (_ptw_io_requestor_3_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_ren (_ptw_io_requestor_3_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_wen (_ptw_io_requestor_3_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_wdata (_ptw_io_requestor_3_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_value (_ptw_io_requestor_3_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_ren (_ptw_io_requestor_3_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_wen (_ptw_io_requestor_3_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_wdata (_ptw_io_requestor_3_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_value (_ptw_io_requestor_3_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_4_req_ready (_ptw_io_requestor_4_req_ready), // @[PTW.scala:802:19] .io_ptw_4_req_valid (_zstd_compressor_io_ptw_4_req_valid), .io_ptw_4_req_bits_bits_addr (_zstd_compressor_io_ptw_4_req_bits_bits_addr), .io_ptw_4_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_4_req_bits_bits_need_gpa), .io_ptw_4_resp_valid (_ptw_io_requestor_4_resp_valid), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_ae_ptw (_ptw_io_requestor_4_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_ae_final (_ptw_io_requestor_4_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pf (_ptw_io_requestor_4_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gf (_ptw_io_requestor_4_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hr (_ptw_io_requestor_4_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hw (_ptw_io_requestor_4_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hx (_ptw_io_requestor_4_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_reserved_for_future (_ptw_io_requestor_4_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_ppn (_ptw_io_requestor_4_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_reserved_for_software (_ptw_io_requestor_4_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_d (_ptw_io_requestor_4_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_a (_ptw_io_requestor_4_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_g (_ptw_io_requestor_4_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_u (_ptw_io_requestor_4_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_x (_ptw_io_requestor_4_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_w (_ptw_io_requestor_4_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_r (_ptw_io_requestor_4_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_v (_ptw_io_requestor_4_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_level (_ptw_io_requestor_4_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_homogeneous (_ptw_io_requestor_4_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_valid (_ptw_io_requestor_4_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_bits (_ptw_io_requestor_4_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_is_pte (_ptw_io_requestor_4_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_4_ptbr_mode (_ptw_io_requestor_4_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_4_ptbr_ppn (_ptw_io_requestor_4_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_4_status_debug (_ptw_io_requestor_4_status_debug), // @[PTW.scala:802:19] .io_ptw_4_status_cease (_ptw_io_requestor_4_status_cease), // @[PTW.scala:802:19] .io_ptw_4_status_wfi (_ptw_io_requestor_4_status_wfi), // @[PTW.scala:802:19] .io_ptw_4_status_isa (_ptw_io_requestor_4_status_isa), // @[PTW.scala:802:19] .io_ptw_4_status_dprv (_ptw_io_requestor_4_status_dprv), // @[PTW.scala:802:19] .io_ptw_4_status_dv (_ptw_io_requestor_4_status_dv), // @[PTW.scala:802:19] .io_ptw_4_status_prv (_ptw_io_requestor_4_status_prv), // @[PTW.scala:802:19] .io_ptw_4_status_v (_ptw_io_requestor_4_status_v), // @[PTW.scala:802:19] .io_ptw_4_status_mpv (_ptw_io_requestor_4_status_mpv), // @[PTW.scala:802:19] .io_ptw_4_status_gva (_ptw_io_requestor_4_status_gva), // @[PTW.scala:802:19] .io_ptw_4_status_tsr (_ptw_io_requestor_4_status_tsr), // @[PTW.scala:802:19] .io_ptw_4_status_tw (_ptw_io_requestor_4_status_tw), // @[PTW.scala:802:19] .io_ptw_4_status_tvm (_ptw_io_requestor_4_status_tvm), // @[PTW.scala:802:19] .io_ptw_4_status_mxr (_ptw_io_requestor_4_status_mxr), // @[PTW.scala:802:19] .io_ptw_4_status_sum (_ptw_io_requestor_4_status_sum), // @[PTW.scala:802:19] .io_ptw_4_status_mprv (_ptw_io_requestor_4_status_mprv), // @[PTW.scala:802:19] .io_ptw_4_status_fs (_ptw_io_requestor_4_status_fs), // @[PTW.scala:802:19] .io_ptw_4_status_mpp (_ptw_io_requestor_4_status_mpp), // @[PTW.scala:802:19] .io_ptw_4_status_spp (_ptw_io_requestor_4_status_spp), // @[PTW.scala:802:19] .io_ptw_4_status_mpie (_ptw_io_requestor_4_status_mpie), // @[PTW.scala:802:19] .io_ptw_4_status_spie (_ptw_io_requestor_4_status_spie), // @[PTW.scala:802:19] .io_ptw_4_status_mie (_ptw_io_requestor_4_status_mie), // @[PTW.scala:802:19] .io_ptw_4_status_sie (_ptw_io_requestor_4_status_sie), // @[PTW.scala:802:19] .io_ptw_4_hstatus_spvp (_ptw_io_requestor_4_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_4_hstatus_spv (_ptw_io_requestor_4_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_4_hstatus_gva (_ptw_io_requestor_4_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_4_gstatus_debug (_ptw_io_requestor_4_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_4_gstatus_cease (_ptw_io_requestor_4_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_4_gstatus_wfi (_ptw_io_requestor_4_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_4_gstatus_isa (_ptw_io_requestor_4_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_4_gstatus_dprv (_ptw_io_requestor_4_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_dv (_ptw_io_requestor_4_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_prv (_ptw_io_requestor_4_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_v (_ptw_io_requestor_4_gstatus_v), // @[PTW.scala:802:19] .io_ptw_4_gstatus_zero2 (_ptw_io_requestor_4_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpv (_ptw_io_requestor_4_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_gva (_ptw_io_requestor_4_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mbe (_ptw_io_requestor_4_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sbe (_ptw_io_requestor_4_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sxl (_ptw_io_requestor_4_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_4_gstatus_zero1 (_ptw_io_requestor_4_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tsr (_ptw_io_requestor_4_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tw (_ptw_io_requestor_4_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tvm (_ptw_io_requestor_4_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mxr (_ptw_io_requestor_4_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sum (_ptw_io_requestor_4_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mprv (_ptw_io_requestor_4_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_fs (_ptw_io_requestor_4_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpp (_ptw_io_requestor_4_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_4_gstatus_vs (_ptw_io_requestor_4_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_4_gstatus_spp (_ptw_io_requestor_4_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpie (_ptw_io_requestor_4_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_ube (_ptw_io_requestor_4_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_4_gstatus_spie (_ptw_io_requestor_4_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_upie (_ptw_io_requestor_4_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mie (_ptw_io_requestor_4_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_hie (_ptw_io_requestor_4_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sie (_ptw_io_requestor_4_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_uie (_ptw_io_requestor_4_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_l (_ptw_io_requestor_4_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_a (_ptw_io_requestor_4_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_x (_ptw_io_requestor_4_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_w (_ptw_io_requestor_4_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_r (_ptw_io_requestor_4_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_addr (_ptw_io_requestor_4_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_mask (_ptw_io_requestor_4_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_l (_ptw_io_requestor_4_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_a (_ptw_io_requestor_4_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_x (_ptw_io_requestor_4_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_w (_ptw_io_requestor_4_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_r (_ptw_io_requestor_4_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_addr (_ptw_io_requestor_4_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_mask (_ptw_io_requestor_4_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_l (_ptw_io_requestor_4_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_a (_ptw_io_requestor_4_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_x (_ptw_io_requestor_4_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_w (_ptw_io_requestor_4_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_r (_ptw_io_requestor_4_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_addr (_ptw_io_requestor_4_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_mask (_ptw_io_requestor_4_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_l (_ptw_io_requestor_4_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_a (_ptw_io_requestor_4_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_x (_ptw_io_requestor_4_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_w (_ptw_io_requestor_4_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_r (_ptw_io_requestor_4_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_addr (_ptw_io_requestor_4_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_mask (_ptw_io_requestor_4_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_l (_ptw_io_requestor_4_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_a (_ptw_io_requestor_4_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_x (_ptw_io_requestor_4_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_w (_ptw_io_requestor_4_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_r (_ptw_io_requestor_4_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_addr (_ptw_io_requestor_4_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_mask (_ptw_io_requestor_4_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_l (_ptw_io_requestor_4_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_a (_ptw_io_requestor_4_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_x (_ptw_io_requestor_4_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_w (_ptw_io_requestor_4_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_r (_ptw_io_requestor_4_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_addr (_ptw_io_requestor_4_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_mask (_ptw_io_requestor_4_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_l (_ptw_io_requestor_4_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_a (_ptw_io_requestor_4_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_x (_ptw_io_requestor_4_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_w (_ptw_io_requestor_4_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_r (_ptw_io_requestor_4_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_addr (_ptw_io_requestor_4_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_mask (_ptw_io_requestor_4_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_l (_ptw_io_requestor_4_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_a (_ptw_io_requestor_4_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_x (_ptw_io_requestor_4_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_w (_ptw_io_requestor_4_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_r (_ptw_io_requestor_4_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_addr (_ptw_io_requestor_4_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_mask (_ptw_io_requestor_4_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_ren (_ptw_io_requestor_4_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_wen (_ptw_io_requestor_4_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_wdata (_ptw_io_requestor_4_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_value (_ptw_io_requestor_4_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_ren (_ptw_io_requestor_4_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_wen (_ptw_io_requestor_4_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_wdata (_ptw_io_requestor_4_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_value (_ptw_io_requestor_4_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_ren (_ptw_io_requestor_4_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_wen (_ptw_io_requestor_4_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_wdata (_ptw_io_requestor_4_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_value (_ptw_io_requestor_4_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_ren (_ptw_io_requestor_4_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_wen (_ptw_io_requestor_4_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_wdata (_ptw_io_requestor_4_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_value (_ptw_io_requestor_4_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_5_req_ready (_ptw_io_requestor_5_req_ready), // @[PTW.scala:802:19] .io_ptw_5_req_valid (_zstd_compressor_io_ptw_5_req_valid), .io_ptw_5_req_bits_bits_addr (_zstd_compressor_io_ptw_5_req_bits_bits_addr), .io_ptw_5_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_5_req_bits_bits_need_gpa), .io_ptw_5_resp_valid (_ptw_io_requestor_5_resp_valid), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_ae_ptw (_ptw_io_requestor_5_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_ae_final (_ptw_io_requestor_5_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pf (_ptw_io_requestor_5_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gf (_ptw_io_requestor_5_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hr (_ptw_io_requestor_5_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hw (_ptw_io_requestor_5_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hx (_ptw_io_requestor_5_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_reserved_for_future (_ptw_io_requestor_5_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_ppn (_ptw_io_requestor_5_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_reserved_for_software (_ptw_io_requestor_5_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_d (_ptw_io_requestor_5_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_a (_ptw_io_requestor_5_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_g (_ptw_io_requestor_5_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_u (_ptw_io_requestor_5_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_x (_ptw_io_requestor_5_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_w (_ptw_io_requestor_5_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_r (_ptw_io_requestor_5_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_v (_ptw_io_requestor_5_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_level (_ptw_io_requestor_5_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_homogeneous (_ptw_io_requestor_5_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_valid (_ptw_io_requestor_5_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_bits (_ptw_io_requestor_5_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_is_pte (_ptw_io_requestor_5_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_5_ptbr_mode (_ptw_io_requestor_5_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_5_ptbr_ppn (_ptw_io_requestor_5_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_5_status_debug (_ptw_io_requestor_5_status_debug), // @[PTW.scala:802:19] .io_ptw_5_status_cease (_ptw_io_requestor_5_status_cease), // @[PTW.scala:802:19] .io_ptw_5_status_wfi (_ptw_io_requestor_5_status_wfi), // @[PTW.scala:802:19] .io_ptw_5_status_isa (_ptw_io_requestor_5_status_isa), // @[PTW.scala:802:19] .io_ptw_5_status_dprv (_ptw_io_requestor_5_status_dprv), // @[PTW.scala:802:19] .io_ptw_5_status_dv (_ptw_io_requestor_5_status_dv), // @[PTW.scala:802:19] .io_ptw_5_status_prv (_ptw_io_requestor_5_status_prv), // @[PTW.scala:802:19] .io_ptw_5_status_v (_ptw_io_requestor_5_status_v), // @[PTW.scala:802:19] .io_ptw_5_status_mpv (_ptw_io_requestor_5_status_mpv), // @[PTW.scala:802:19] .io_ptw_5_status_gva (_ptw_io_requestor_5_status_gva), // @[PTW.scala:802:19] .io_ptw_5_status_tsr (_ptw_io_requestor_5_status_tsr), // @[PTW.scala:802:19] .io_ptw_5_status_tw (_ptw_io_requestor_5_status_tw), // @[PTW.scala:802:19] .io_ptw_5_status_tvm (_ptw_io_requestor_5_status_tvm), // @[PTW.scala:802:19] .io_ptw_5_status_mxr (_ptw_io_requestor_5_status_mxr), // @[PTW.scala:802:19] .io_ptw_5_status_sum (_ptw_io_requestor_5_status_sum), // @[PTW.scala:802:19] .io_ptw_5_status_mprv (_ptw_io_requestor_5_status_mprv), // @[PTW.scala:802:19] .io_ptw_5_status_fs (_ptw_io_requestor_5_status_fs), // @[PTW.scala:802:19] .io_ptw_5_status_mpp (_ptw_io_requestor_5_status_mpp), // @[PTW.scala:802:19] .io_ptw_5_status_spp (_ptw_io_requestor_5_status_spp), // @[PTW.scala:802:19] .io_ptw_5_status_mpie (_ptw_io_requestor_5_status_mpie), // @[PTW.scala:802:19] .io_ptw_5_status_spie (_ptw_io_requestor_5_status_spie), // @[PTW.scala:802:19] .io_ptw_5_status_mie (_ptw_io_requestor_5_status_mie), // @[PTW.scala:802:19] .io_ptw_5_status_sie (_ptw_io_requestor_5_status_sie), // @[PTW.scala:802:19] .io_ptw_5_hstatus_spvp (_ptw_io_requestor_5_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_5_hstatus_spv (_ptw_io_requestor_5_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_5_hstatus_gva (_ptw_io_requestor_5_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_5_gstatus_debug (_ptw_io_requestor_5_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_5_gstatus_cease (_ptw_io_requestor_5_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_5_gstatus_wfi (_ptw_io_requestor_5_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_5_gstatus_isa (_ptw_io_requestor_5_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_5_gstatus_dprv (_ptw_io_requestor_5_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_dv (_ptw_io_requestor_5_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_prv (_ptw_io_requestor_5_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_v (_ptw_io_requestor_5_gstatus_v), // @[PTW.scala:802:19] .io_ptw_5_gstatus_zero2 (_ptw_io_requestor_5_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpv (_ptw_io_requestor_5_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_gva (_ptw_io_requestor_5_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mbe (_ptw_io_requestor_5_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sbe (_ptw_io_requestor_5_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sxl (_ptw_io_requestor_5_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_5_gstatus_zero1 (_ptw_io_requestor_5_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tsr (_ptw_io_requestor_5_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tw (_ptw_io_requestor_5_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tvm (_ptw_io_requestor_5_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mxr (_ptw_io_requestor_5_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sum (_ptw_io_requestor_5_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mprv (_ptw_io_requestor_5_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_fs (_ptw_io_requestor_5_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpp (_ptw_io_requestor_5_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_5_gstatus_vs (_ptw_io_requestor_5_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_5_gstatus_spp (_ptw_io_requestor_5_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpie (_ptw_io_requestor_5_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_ube (_ptw_io_requestor_5_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_5_gstatus_spie (_ptw_io_requestor_5_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_upie (_ptw_io_requestor_5_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mie (_ptw_io_requestor_5_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_hie (_ptw_io_requestor_5_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sie (_ptw_io_requestor_5_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_uie (_ptw_io_requestor_5_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_l (_ptw_io_requestor_5_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_a (_ptw_io_requestor_5_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_x (_ptw_io_requestor_5_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_w (_ptw_io_requestor_5_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_r (_ptw_io_requestor_5_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_addr (_ptw_io_requestor_5_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_mask (_ptw_io_requestor_5_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_l (_ptw_io_requestor_5_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_a (_ptw_io_requestor_5_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_x (_ptw_io_requestor_5_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_w (_ptw_io_requestor_5_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_r (_ptw_io_requestor_5_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_addr (_ptw_io_requestor_5_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_mask (_ptw_io_requestor_5_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_l (_ptw_io_requestor_5_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_a (_ptw_io_requestor_5_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_x (_ptw_io_requestor_5_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_w (_ptw_io_requestor_5_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_r (_ptw_io_requestor_5_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_addr (_ptw_io_requestor_5_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_mask (_ptw_io_requestor_5_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_l (_ptw_io_requestor_5_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_a (_ptw_io_requestor_5_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_x (_ptw_io_requestor_5_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_w (_ptw_io_requestor_5_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_r (_ptw_io_requestor_5_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_addr (_ptw_io_requestor_5_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_mask (_ptw_io_requestor_5_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_l (_ptw_io_requestor_5_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_a (_ptw_io_requestor_5_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_x (_ptw_io_requestor_5_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_w (_ptw_io_requestor_5_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_r (_ptw_io_requestor_5_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_addr (_ptw_io_requestor_5_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_mask (_ptw_io_requestor_5_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_l (_ptw_io_requestor_5_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_a (_ptw_io_requestor_5_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_x (_ptw_io_requestor_5_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_w (_ptw_io_requestor_5_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_r (_ptw_io_requestor_5_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_addr (_ptw_io_requestor_5_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_mask (_ptw_io_requestor_5_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_l (_ptw_io_requestor_5_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_a (_ptw_io_requestor_5_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_x (_ptw_io_requestor_5_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_w (_ptw_io_requestor_5_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_r (_ptw_io_requestor_5_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_addr (_ptw_io_requestor_5_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_mask (_ptw_io_requestor_5_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_l (_ptw_io_requestor_5_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_a (_ptw_io_requestor_5_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_x (_ptw_io_requestor_5_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_w (_ptw_io_requestor_5_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_r (_ptw_io_requestor_5_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_addr (_ptw_io_requestor_5_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_mask (_ptw_io_requestor_5_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_ren (_ptw_io_requestor_5_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_wen (_ptw_io_requestor_5_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_wdata (_ptw_io_requestor_5_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_value (_ptw_io_requestor_5_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_ren (_ptw_io_requestor_5_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_wen (_ptw_io_requestor_5_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_wdata (_ptw_io_requestor_5_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_value (_ptw_io_requestor_5_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_ren (_ptw_io_requestor_5_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_wen (_ptw_io_requestor_5_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_wdata (_ptw_io_requestor_5_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_value (_ptw_io_requestor_5_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_ren (_ptw_io_requestor_5_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_wen (_ptw_io_requestor_5_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_wdata (_ptw_io_requestor_5_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_value (_ptw_io_requestor_5_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_6_req_ready (_ptw_io_requestor_6_req_ready), // @[PTW.scala:802:19] .io_ptw_6_req_valid (_zstd_compressor_io_ptw_6_req_valid), .io_ptw_6_req_bits_bits_addr (_zstd_compressor_io_ptw_6_req_bits_bits_addr), .io_ptw_6_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_6_req_bits_bits_need_gpa), .io_ptw_6_resp_valid (_ptw_io_requestor_6_resp_valid), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_ae_ptw (_ptw_io_requestor_6_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_ae_final (_ptw_io_requestor_6_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pf (_ptw_io_requestor_6_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gf (_ptw_io_requestor_6_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hr (_ptw_io_requestor_6_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hw (_ptw_io_requestor_6_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hx (_ptw_io_requestor_6_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_reserved_for_future (_ptw_io_requestor_6_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_ppn (_ptw_io_requestor_6_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_reserved_for_software (_ptw_io_requestor_6_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_d (_ptw_io_requestor_6_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_a (_ptw_io_requestor_6_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_g (_ptw_io_requestor_6_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_u (_ptw_io_requestor_6_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_x (_ptw_io_requestor_6_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_w (_ptw_io_requestor_6_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_r (_ptw_io_requestor_6_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_v (_ptw_io_requestor_6_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_level (_ptw_io_requestor_6_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_homogeneous (_ptw_io_requestor_6_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_valid (_ptw_io_requestor_6_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_bits (_ptw_io_requestor_6_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_is_pte (_ptw_io_requestor_6_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_6_ptbr_mode (_ptw_io_requestor_6_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_6_ptbr_ppn (_ptw_io_requestor_6_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_6_status_debug (_ptw_io_requestor_6_status_debug), // @[PTW.scala:802:19] .io_ptw_6_status_cease (_ptw_io_requestor_6_status_cease), // @[PTW.scala:802:19] .io_ptw_6_status_wfi (_ptw_io_requestor_6_status_wfi), // @[PTW.scala:802:19] .io_ptw_6_status_isa (_ptw_io_requestor_6_status_isa), // @[PTW.scala:802:19] .io_ptw_6_status_dprv (_ptw_io_requestor_6_status_dprv), // @[PTW.scala:802:19] .io_ptw_6_status_dv (_ptw_io_requestor_6_status_dv), // @[PTW.scala:802:19] .io_ptw_6_status_prv (_ptw_io_requestor_6_status_prv), // @[PTW.scala:802:19] .io_ptw_6_status_v (_ptw_io_requestor_6_status_v), // @[PTW.scala:802:19] .io_ptw_6_status_mpv (_ptw_io_requestor_6_status_mpv), // @[PTW.scala:802:19] .io_ptw_6_status_gva (_ptw_io_requestor_6_status_gva), // @[PTW.scala:802:19] .io_ptw_6_status_tsr (_ptw_io_requestor_6_status_tsr), // @[PTW.scala:802:19] .io_ptw_6_status_tw (_ptw_io_requestor_6_status_tw), // @[PTW.scala:802:19] .io_ptw_6_status_tvm (_ptw_io_requestor_6_status_tvm), // @[PTW.scala:802:19] .io_ptw_6_status_mxr (_ptw_io_requestor_6_status_mxr), // @[PTW.scala:802:19] .io_ptw_6_status_sum (_ptw_io_requestor_6_status_sum), // @[PTW.scala:802:19] .io_ptw_6_status_mprv (_ptw_io_requestor_6_status_mprv), // @[PTW.scala:802:19] .io_ptw_6_status_fs (_ptw_io_requestor_6_status_fs), // @[PTW.scala:802:19] .io_ptw_6_status_mpp (_ptw_io_requestor_6_status_mpp), // @[PTW.scala:802:19] .io_ptw_6_status_spp (_ptw_io_requestor_6_status_spp), // @[PTW.scala:802:19] .io_ptw_6_status_mpie (_ptw_io_requestor_6_status_mpie), // @[PTW.scala:802:19] .io_ptw_6_status_spie (_ptw_io_requestor_6_status_spie), // @[PTW.scala:802:19] .io_ptw_6_status_mie (_ptw_io_requestor_6_status_mie), // @[PTW.scala:802:19] .io_ptw_6_status_sie (_ptw_io_requestor_6_status_sie), // @[PTW.scala:802:19] .io_ptw_6_hstatus_spvp (_ptw_io_requestor_6_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_6_hstatus_spv (_ptw_io_requestor_6_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_6_hstatus_gva (_ptw_io_requestor_6_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_6_gstatus_debug (_ptw_io_requestor_6_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_6_gstatus_cease (_ptw_io_requestor_6_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_6_gstatus_wfi (_ptw_io_requestor_6_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_6_gstatus_isa (_ptw_io_requestor_6_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_6_gstatus_dprv (_ptw_io_requestor_6_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_dv (_ptw_io_requestor_6_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_prv (_ptw_io_requestor_6_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_v (_ptw_io_requestor_6_gstatus_v), // @[PTW.scala:802:19] .io_ptw_6_gstatus_zero2 (_ptw_io_requestor_6_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpv (_ptw_io_requestor_6_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_gva (_ptw_io_requestor_6_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mbe (_ptw_io_requestor_6_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sbe (_ptw_io_requestor_6_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sxl (_ptw_io_requestor_6_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_6_gstatus_zero1 (_ptw_io_requestor_6_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tsr (_ptw_io_requestor_6_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tw (_ptw_io_requestor_6_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tvm (_ptw_io_requestor_6_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mxr (_ptw_io_requestor_6_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sum (_ptw_io_requestor_6_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mprv (_ptw_io_requestor_6_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_fs (_ptw_io_requestor_6_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpp (_ptw_io_requestor_6_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_6_gstatus_vs (_ptw_io_requestor_6_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_6_gstatus_spp (_ptw_io_requestor_6_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpie (_ptw_io_requestor_6_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_ube (_ptw_io_requestor_6_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_6_gstatus_spie (_ptw_io_requestor_6_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_upie (_ptw_io_requestor_6_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mie (_ptw_io_requestor_6_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_hie (_ptw_io_requestor_6_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sie (_ptw_io_requestor_6_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_uie (_ptw_io_requestor_6_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_l (_ptw_io_requestor_6_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_a (_ptw_io_requestor_6_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_x (_ptw_io_requestor_6_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_w (_ptw_io_requestor_6_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_r (_ptw_io_requestor_6_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_addr (_ptw_io_requestor_6_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_mask (_ptw_io_requestor_6_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_l (_ptw_io_requestor_6_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_a (_ptw_io_requestor_6_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_x (_ptw_io_requestor_6_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_w (_ptw_io_requestor_6_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_r (_ptw_io_requestor_6_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_addr (_ptw_io_requestor_6_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_mask (_ptw_io_requestor_6_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_l (_ptw_io_requestor_6_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_a (_ptw_io_requestor_6_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_x (_ptw_io_requestor_6_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_w (_ptw_io_requestor_6_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_r (_ptw_io_requestor_6_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_addr (_ptw_io_requestor_6_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_mask (_ptw_io_requestor_6_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_l (_ptw_io_requestor_6_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_a (_ptw_io_requestor_6_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_x (_ptw_io_requestor_6_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_w (_ptw_io_requestor_6_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_r (_ptw_io_requestor_6_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_addr (_ptw_io_requestor_6_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_mask (_ptw_io_requestor_6_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_l (_ptw_io_requestor_6_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_a (_ptw_io_requestor_6_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_x (_ptw_io_requestor_6_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_w (_ptw_io_requestor_6_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_r (_ptw_io_requestor_6_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_addr (_ptw_io_requestor_6_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_mask (_ptw_io_requestor_6_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_l (_ptw_io_requestor_6_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_a (_ptw_io_requestor_6_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_x (_ptw_io_requestor_6_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_w (_ptw_io_requestor_6_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_r (_ptw_io_requestor_6_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_addr (_ptw_io_requestor_6_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_mask (_ptw_io_requestor_6_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_l (_ptw_io_requestor_6_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_a (_ptw_io_requestor_6_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_x (_ptw_io_requestor_6_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_w (_ptw_io_requestor_6_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_r (_ptw_io_requestor_6_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_addr (_ptw_io_requestor_6_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_mask (_ptw_io_requestor_6_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_l (_ptw_io_requestor_6_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_a (_ptw_io_requestor_6_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_x (_ptw_io_requestor_6_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_w (_ptw_io_requestor_6_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_r (_ptw_io_requestor_6_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_addr (_ptw_io_requestor_6_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_mask (_ptw_io_requestor_6_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_ren (_ptw_io_requestor_6_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_wen (_ptw_io_requestor_6_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_wdata (_ptw_io_requestor_6_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_value (_ptw_io_requestor_6_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_ren (_ptw_io_requestor_6_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_wen (_ptw_io_requestor_6_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_wdata (_ptw_io_requestor_6_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_value (_ptw_io_requestor_6_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_ren (_ptw_io_requestor_6_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_wen (_ptw_io_requestor_6_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_wdata (_ptw_io_requestor_6_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_value (_ptw_io_requestor_6_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_ren (_ptw_io_requestor_6_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_wen (_ptw_io_requestor_6_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_wdata (_ptw_io_requestor_6_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_value (_ptw_io_requestor_6_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_7_req_ready (_ptw_io_requestor_7_req_ready), // @[PTW.scala:802:19] .io_ptw_7_req_valid (_zstd_compressor_io_ptw_7_req_valid), .io_ptw_7_req_bits_bits_addr (_zstd_compressor_io_ptw_7_req_bits_bits_addr), .io_ptw_7_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_7_req_bits_bits_need_gpa), .io_ptw_7_resp_valid (_ptw_io_requestor_7_resp_valid), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_ae_ptw (_ptw_io_requestor_7_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_ae_final (_ptw_io_requestor_7_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pf (_ptw_io_requestor_7_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gf (_ptw_io_requestor_7_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hr (_ptw_io_requestor_7_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hw (_ptw_io_requestor_7_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hx (_ptw_io_requestor_7_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_reserved_for_future (_ptw_io_requestor_7_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_ppn (_ptw_io_requestor_7_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_reserved_for_software (_ptw_io_requestor_7_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_d (_ptw_io_requestor_7_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_a (_ptw_io_requestor_7_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_g (_ptw_io_requestor_7_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_u (_ptw_io_requestor_7_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_x (_ptw_io_requestor_7_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_w (_ptw_io_requestor_7_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_r (_ptw_io_requestor_7_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_v (_ptw_io_requestor_7_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_level (_ptw_io_requestor_7_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_homogeneous (_ptw_io_requestor_7_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_valid (_ptw_io_requestor_7_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_bits (_ptw_io_requestor_7_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_is_pte (_ptw_io_requestor_7_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_7_ptbr_mode (_ptw_io_requestor_7_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_7_ptbr_ppn (_ptw_io_requestor_7_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_7_status_debug (_ptw_io_requestor_7_status_debug), // @[PTW.scala:802:19] .io_ptw_7_status_cease (_ptw_io_requestor_7_status_cease), // @[PTW.scala:802:19] .io_ptw_7_status_wfi (_ptw_io_requestor_7_status_wfi), // @[PTW.scala:802:19] .io_ptw_7_status_isa (_ptw_io_requestor_7_status_isa), // @[PTW.scala:802:19] .io_ptw_7_status_dprv (_ptw_io_requestor_7_status_dprv), // @[PTW.scala:802:19] .io_ptw_7_status_dv (_ptw_io_requestor_7_status_dv), // @[PTW.scala:802:19] .io_ptw_7_status_prv (_ptw_io_requestor_7_status_prv), // @[PTW.scala:802:19] .io_ptw_7_status_v (_ptw_io_requestor_7_status_v), // @[PTW.scala:802:19] .io_ptw_7_status_mpv (_ptw_io_requestor_7_status_mpv), // @[PTW.scala:802:19] .io_ptw_7_status_gva (_ptw_io_requestor_7_status_gva), // @[PTW.scala:802:19] .io_ptw_7_status_tsr (_ptw_io_requestor_7_status_tsr), // @[PTW.scala:802:19] .io_ptw_7_status_tw (_ptw_io_requestor_7_status_tw), // @[PTW.scala:802:19] .io_ptw_7_status_tvm (_ptw_io_requestor_7_status_tvm), // @[PTW.scala:802:19] .io_ptw_7_status_mxr (_ptw_io_requestor_7_status_mxr), // @[PTW.scala:802:19] .io_ptw_7_status_sum (_ptw_io_requestor_7_status_sum), // @[PTW.scala:802:19] .io_ptw_7_status_mprv (_ptw_io_requestor_7_status_mprv), // @[PTW.scala:802:19] .io_ptw_7_status_fs (_ptw_io_requestor_7_status_fs), // @[PTW.scala:802:19] .io_ptw_7_status_mpp (_ptw_io_requestor_7_status_mpp), // @[PTW.scala:802:19] .io_ptw_7_status_spp (_ptw_io_requestor_7_status_spp), // @[PTW.scala:802:19] .io_ptw_7_status_mpie (_ptw_io_requestor_7_status_mpie), // @[PTW.scala:802:19] .io_ptw_7_status_spie (_ptw_io_requestor_7_status_spie), // @[PTW.scala:802:19] .io_ptw_7_status_mie (_ptw_io_requestor_7_status_mie), // @[PTW.scala:802:19] .io_ptw_7_status_sie (_ptw_io_requestor_7_status_sie), // @[PTW.scala:802:19] .io_ptw_7_hstatus_spvp (_ptw_io_requestor_7_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_7_hstatus_spv (_ptw_io_requestor_7_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_7_hstatus_gva (_ptw_io_requestor_7_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_7_gstatus_debug (_ptw_io_requestor_7_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_7_gstatus_cease (_ptw_io_requestor_7_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_7_gstatus_wfi (_ptw_io_requestor_7_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_7_gstatus_isa (_ptw_io_requestor_7_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_7_gstatus_dprv (_ptw_io_requestor_7_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_dv (_ptw_io_requestor_7_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_prv (_ptw_io_requestor_7_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_v (_ptw_io_requestor_7_gstatus_v), // @[PTW.scala:802:19] .io_ptw_7_gstatus_zero2 (_ptw_io_requestor_7_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpv (_ptw_io_requestor_7_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_gva (_ptw_io_requestor_7_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mbe (_ptw_io_requestor_7_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sbe (_ptw_io_requestor_7_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sxl (_ptw_io_requestor_7_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_7_gstatus_zero1 (_ptw_io_requestor_7_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tsr (_ptw_io_requestor_7_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tw (_ptw_io_requestor_7_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tvm (_ptw_io_requestor_7_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mxr (_ptw_io_requestor_7_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sum (_ptw_io_requestor_7_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mprv (_ptw_io_requestor_7_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_fs (_ptw_io_requestor_7_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpp (_ptw_io_requestor_7_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_7_gstatus_vs (_ptw_io_requestor_7_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_7_gstatus_spp (_ptw_io_requestor_7_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpie (_ptw_io_requestor_7_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_ube (_ptw_io_requestor_7_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_7_gstatus_spie (_ptw_io_requestor_7_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_upie (_ptw_io_requestor_7_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mie (_ptw_io_requestor_7_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_hie (_ptw_io_requestor_7_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sie (_ptw_io_requestor_7_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_uie (_ptw_io_requestor_7_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_l (_ptw_io_requestor_7_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_a (_ptw_io_requestor_7_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_x (_ptw_io_requestor_7_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_w (_ptw_io_requestor_7_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_r (_ptw_io_requestor_7_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_addr (_ptw_io_requestor_7_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_mask (_ptw_io_requestor_7_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_l (_ptw_io_requestor_7_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_a (_ptw_io_requestor_7_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_x (_ptw_io_requestor_7_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_w (_ptw_io_requestor_7_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_r (_ptw_io_requestor_7_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_addr (_ptw_io_requestor_7_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_mask (_ptw_io_requestor_7_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_l (_ptw_io_requestor_7_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_a (_ptw_io_requestor_7_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_x (_ptw_io_requestor_7_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_w (_ptw_io_requestor_7_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_r (_ptw_io_requestor_7_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_addr (_ptw_io_requestor_7_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_mask (_ptw_io_requestor_7_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_l (_ptw_io_requestor_7_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_a (_ptw_io_requestor_7_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_x (_ptw_io_requestor_7_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_w (_ptw_io_requestor_7_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_r (_ptw_io_requestor_7_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_addr (_ptw_io_requestor_7_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_mask (_ptw_io_requestor_7_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_l (_ptw_io_requestor_7_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_a (_ptw_io_requestor_7_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_x (_ptw_io_requestor_7_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_w (_ptw_io_requestor_7_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_r (_ptw_io_requestor_7_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_addr (_ptw_io_requestor_7_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_mask (_ptw_io_requestor_7_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_l (_ptw_io_requestor_7_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_a (_ptw_io_requestor_7_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_x (_ptw_io_requestor_7_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_w (_ptw_io_requestor_7_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_r (_ptw_io_requestor_7_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_addr (_ptw_io_requestor_7_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_mask (_ptw_io_requestor_7_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_l (_ptw_io_requestor_7_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_a (_ptw_io_requestor_7_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_x (_ptw_io_requestor_7_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_w (_ptw_io_requestor_7_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_r (_ptw_io_requestor_7_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_addr (_ptw_io_requestor_7_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_mask (_ptw_io_requestor_7_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_l (_ptw_io_requestor_7_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_a (_ptw_io_requestor_7_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_x (_ptw_io_requestor_7_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_w (_ptw_io_requestor_7_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_r (_ptw_io_requestor_7_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_addr (_ptw_io_requestor_7_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_mask (_ptw_io_requestor_7_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_ren (_ptw_io_requestor_7_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_wen (_ptw_io_requestor_7_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_wdata (_ptw_io_requestor_7_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_value (_ptw_io_requestor_7_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_ren (_ptw_io_requestor_7_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_wen (_ptw_io_requestor_7_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_wdata (_ptw_io_requestor_7_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_value (_ptw_io_requestor_7_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_ren (_ptw_io_requestor_7_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_wen (_ptw_io_requestor_7_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_wdata (_ptw_io_requestor_7_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_value (_ptw_io_requestor_7_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_ren (_ptw_io_requestor_7_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_wen (_ptw_io_requestor_7_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_wdata (_ptw_io_requestor_7_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_value (_ptw_io_requestor_7_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_8_req_ready (_ptw_io_requestor_8_req_ready), // @[PTW.scala:802:19] .io_ptw_8_req_valid (_zstd_compressor_io_ptw_8_req_valid), .io_ptw_8_req_bits_bits_addr (_zstd_compressor_io_ptw_8_req_bits_bits_addr), .io_ptw_8_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_8_req_bits_bits_need_gpa), .io_ptw_8_resp_valid (_ptw_io_requestor_8_resp_valid), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_ae_ptw (_ptw_io_requestor_8_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_ae_final (_ptw_io_requestor_8_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pf (_ptw_io_requestor_8_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gf (_ptw_io_requestor_8_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hr (_ptw_io_requestor_8_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hw (_ptw_io_requestor_8_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hx (_ptw_io_requestor_8_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_reserved_for_future (_ptw_io_requestor_8_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_ppn (_ptw_io_requestor_8_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_reserved_for_software (_ptw_io_requestor_8_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_d (_ptw_io_requestor_8_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_a (_ptw_io_requestor_8_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_g (_ptw_io_requestor_8_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_u (_ptw_io_requestor_8_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_x (_ptw_io_requestor_8_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_w (_ptw_io_requestor_8_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_r (_ptw_io_requestor_8_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_v (_ptw_io_requestor_8_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_level (_ptw_io_requestor_8_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_homogeneous (_ptw_io_requestor_8_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_valid (_ptw_io_requestor_8_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_bits (_ptw_io_requestor_8_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_is_pte (_ptw_io_requestor_8_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_8_ptbr_mode (_ptw_io_requestor_8_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_8_ptbr_ppn (_ptw_io_requestor_8_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_8_status_debug (_ptw_io_requestor_8_status_debug), // @[PTW.scala:802:19] .io_ptw_8_status_cease (_ptw_io_requestor_8_status_cease), // @[PTW.scala:802:19] .io_ptw_8_status_wfi (_ptw_io_requestor_8_status_wfi), // @[PTW.scala:802:19] .io_ptw_8_status_isa (_ptw_io_requestor_8_status_isa), // @[PTW.scala:802:19] .io_ptw_8_status_dprv (_ptw_io_requestor_8_status_dprv), // @[PTW.scala:802:19] .io_ptw_8_status_dv (_ptw_io_requestor_8_status_dv), // @[PTW.scala:802:19] .io_ptw_8_status_prv (_ptw_io_requestor_8_status_prv), // @[PTW.scala:802:19] .io_ptw_8_status_v (_ptw_io_requestor_8_status_v), // @[PTW.scala:802:19] .io_ptw_8_status_mpv (_ptw_io_requestor_8_status_mpv), // @[PTW.scala:802:19] .io_ptw_8_status_gva (_ptw_io_requestor_8_status_gva), // @[PTW.scala:802:19] .io_ptw_8_status_tsr (_ptw_io_requestor_8_status_tsr), // @[PTW.scala:802:19] .io_ptw_8_status_tw (_ptw_io_requestor_8_status_tw), // @[PTW.scala:802:19] .io_ptw_8_status_tvm (_ptw_io_requestor_8_status_tvm), // @[PTW.scala:802:19] .io_ptw_8_status_mxr (_ptw_io_requestor_8_status_mxr), // @[PTW.scala:802:19] .io_ptw_8_status_sum (_ptw_io_requestor_8_status_sum), // @[PTW.scala:802:19] .io_ptw_8_status_mprv (_ptw_io_requestor_8_status_mprv), // @[PTW.scala:802:19] .io_ptw_8_status_fs (_ptw_io_requestor_8_status_fs), // @[PTW.scala:802:19] .io_ptw_8_status_mpp (_ptw_io_requestor_8_status_mpp), // @[PTW.scala:802:19] .io_ptw_8_status_spp (_ptw_io_requestor_8_status_spp), // @[PTW.scala:802:19] .io_ptw_8_status_mpie (_ptw_io_requestor_8_status_mpie), // @[PTW.scala:802:19] .io_ptw_8_status_spie (_ptw_io_requestor_8_status_spie), // @[PTW.scala:802:19] .io_ptw_8_status_mie (_ptw_io_requestor_8_status_mie), // @[PTW.scala:802:19] .io_ptw_8_status_sie (_ptw_io_requestor_8_status_sie), // @[PTW.scala:802:19] .io_ptw_8_hstatus_spvp (_ptw_io_requestor_8_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_8_hstatus_spv (_ptw_io_requestor_8_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_8_hstatus_gva (_ptw_io_requestor_8_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_8_gstatus_debug (_ptw_io_requestor_8_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_8_gstatus_cease (_ptw_io_requestor_8_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_8_gstatus_wfi (_ptw_io_requestor_8_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_8_gstatus_isa (_ptw_io_requestor_8_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_8_gstatus_dprv (_ptw_io_requestor_8_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_dv (_ptw_io_requestor_8_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_prv (_ptw_io_requestor_8_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_v (_ptw_io_requestor_8_gstatus_v), // @[PTW.scala:802:19] .io_ptw_8_gstatus_zero2 (_ptw_io_requestor_8_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpv (_ptw_io_requestor_8_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_gva (_ptw_io_requestor_8_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mbe (_ptw_io_requestor_8_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sbe (_ptw_io_requestor_8_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sxl (_ptw_io_requestor_8_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_8_gstatus_zero1 (_ptw_io_requestor_8_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tsr (_ptw_io_requestor_8_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tw (_ptw_io_requestor_8_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tvm (_ptw_io_requestor_8_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mxr (_ptw_io_requestor_8_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sum (_ptw_io_requestor_8_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mprv (_ptw_io_requestor_8_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_fs (_ptw_io_requestor_8_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpp (_ptw_io_requestor_8_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_8_gstatus_vs (_ptw_io_requestor_8_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_8_gstatus_spp (_ptw_io_requestor_8_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpie (_ptw_io_requestor_8_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_ube (_ptw_io_requestor_8_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_8_gstatus_spie (_ptw_io_requestor_8_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_upie (_ptw_io_requestor_8_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mie (_ptw_io_requestor_8_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_hie (_ptw_io_requestor_8_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sie (_ptw_io_requestor_8_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_uie (_ptw_io_requestor_8_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_l (_ptw_io_requestor_8_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_a (_ptw_io_requestor_8_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_x (_ptw_io_requestor_8_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_w (_ptw_io_requestor_8_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_r (_ptw_io_requestor_8_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_addr (_ptw_io_requestor_8_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_mask (_ptw_io_requestor_8_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_l (_ptw_io_requestor_8_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_a (_ptw_io_requestor_8_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_x (_ptw_io_requestor_8_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_w (_ptw_io_requestor_8_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_r (_ptw_io_requestor_8_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_addr (_ptw_io_requestor_8_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_mask (_ptw_io_requestor_8_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_l (_ptw_io_requestor_8_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_a (_ptw_io_requestor_8_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_x (_ptw_io_requestor_8_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_w (_ptw_io_requestor_8_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_r (_ptw_io_requestor_8_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_addr (_ptw_io_requestor_8_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_mask (_ptw_io_requestor_8_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_l (_ptw_io_requestor_8_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_a (_ptw_io_requestor_8_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_x (_ptw_io_requestor_8_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_w (_ptw_io_requestor_8_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_r (_ptw_io_requestor_8_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_addr (_ptw_io_requestor_8_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_mask (_ptw_io_requestor_8_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_l (_ptw_io_requestor_8_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_a (_ptw_io_requestor_8_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_x (_ptw_io_requestor_8_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_w (_ptw_io_requestor_8_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_r (_ptw_io_requestor_8_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_addr (_ptw_io_requestor_8_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_mask (_ptw_io_requestor_8_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_l (_ptw_io_requestor_8_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_a (_ptw_io_requestor_8_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_x (_ptw_io_requestor_8_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_w (_ptw_io_requestor_8_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_r (_ptw_io_requestor_8_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_addr (_ptw_io_requestor_8_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_mask (_ptw_io_requestor_8_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_l (_ptw_io_requestor_8_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_a (_ptw_io_requestor_8_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_x (_ptw_io_requestor_8_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_w (_ptw_io_requestor_8_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_r (_ptw_io_requestor_8_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_addr (_ptw_io_requestor_8_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_mask (_ptw_io_requestor_8_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_l (_ptw_io_requestor_8_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_a (_ptw_io_requestor_8_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_x (_ptw_io_requestor_8_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_w (_ptw_io_requestor_8_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_r (_ptw_io_requestor_8_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_addr (_ptw_io_requestor_8_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_mask (_ptw_io_requestor_8_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_ren (_ptw_io_requestor_8_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_wen (_ptw_io_requestor_8_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_wdata (_ptw_io_requestor_8_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_value (_ptw_io_requestor_8_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_ren (_ptw_io_requestor_8_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_wen (_ptw_io_requestor_8_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_wdata (_ptw_io_requestor_8_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_value (_ptw_io_requestor_8_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_ren (_ptw_io_requestor_8_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_wen (_ptw_io_requestor_8_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_wdata (_ptw_io_requestor_8_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_value (_ptw_io_requestor_8_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_ren (_ptw_io_requestor_8_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_wen (_ptw_io_requestor_8_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_wdata (_ptw_io_requestor_8_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_value (_ptw_io_requestor_8_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_9_req_ready (_ptw_io_requestor_9_req_ready), // @[PTW.scala:802:19] .io_ptw_9_req_valid (_zstd_compressor_io_ptw_9_req_valid), .io_ptw_9_req_bits_bits_addr (_zstd_compressor_io_ptw_9_req_bits_bits_addr), .io_ptw_9_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_9_req_bits_bits_need_gpa), .io_ptw_9_resp_valid (_ptw_io_requestor_9_resp_valid), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_ae_ptw (_ptw_io_requestor_9_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_ae_final (_ptw_io_requestor_9_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pf (_ptw_io_requestor_9_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gf (_ptw_io_requestor_9_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hr (_ptw_io_requestor_9_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hw (_ptw_io_requestor_9_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hx (_ptw_io_requestor_9_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_reserved_for_future (_ptw_io_requestor_9_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_ppn (_ptw_io_requestor_9_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_reserved_for_software (_ptw_io_requestor_9_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_d (_ptw_io_requestor_9_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_a (_ptw_io_requestor_9_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_g (_ptw_io_requestor_9_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_u (_ptw_io_requestor_9_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_x (_ptw_io_requestor_9_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_w (_ptw_io_requestor_9_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_r (_ptw_io_requestor_9_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_v (_ptw_io_requestor_9_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_level (_ptw_io_requestor_9_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_homogeneous (_ptw_io_requestor_9_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_valid (_ptw_io_requestor_9_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_bits (_ptw_io_requestor_9_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_is_pte (_ptw_io_requestor_9_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_9_ptbr_mode (_ptw_io_requestor_9_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_9_ptbr_ppn (_ptw_io_requestor_9_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_9_status_debug (_ptw_io_requestor_9_status_debug), // @[PTW.scala:802:19] .io_ptw_9_status_cease (_ptw_io_requestor_9_status_cease), // @[PTW.scala:802:19] .io_ptw_9_status_wfi (_ptw_io_requestor_9_status_wfi), // @[PTW.scala:802:19] .io_ptw_9_status_isa (_ptw_io_requestor_9_status_isa), // @[PTW.scala:802:19] .io_ptw_9_status_dprv (_ptw_io_requestor_9_status_dprv), // @[PTW.scala:802:19] .io_ptw_9_status_dv (_ptw_io_requestor_9_status_dv), // @[PTW.scala:802:19] .io_ptw_9_status_prv (_ptw_io_requestor_9_status_prv), // @[PTW.scala:802:19] .io_ptw_9_status_v (_ptw_io_requestor_9_status_v), // @[PTW.scala:802:19] .io_ptw_9_status_mpv (_ptw_io_requestor_9_status_mpv), // @[PTW.scala:802:19] .io_ptw_9_status_gva (_ptw_io_requestor_9_status_gva), // @[PTW.scala:802:19] .io_ptw_9_status_tsr (_ptw_io_requestor_9_status_tsr), // @[PTW.scala:802:19] .io_ptw_9_status_tw (_ptw_io_requestor_9_status_tw), // @[PTW.scala:802:19] .io_ptw_9_status_tvm (_ptw_io_requestor_9_status_tvm), // @[PTW.scala:802:19] .io_ptw_9_status_mxr (_ptw_io_requestor_9_status_mxr), // @[PTW.scala:802:19] .io_ptw_9_status_sum (_ptw_io_requestor_9_status_sum), // @[PTW.scala:802:19] .io_ptw_9_status_mprv (_ptw_io_requestor_9_status_mprv), // @[PTW.scala:802:19] .io_ptw_9_status_fs (_ptw_io_requestor_9_status_fs), // @[PTW.scala:802:19] .io_ptw_9_status_mpp (_ptw_io_requestor_9_status_mpp), // @[PTW.scala:802:19] .io_ptw_9_status_spp (_ptw_io_requestor_9_status_spp), // @[PTW.scala:802:19] .io_ptw_9_status_mpie (_ptw_io_requestor_9_status_mpie), // @[PTW.scala:802:19] .io_ptw_9_status_spie (_ptw_io_requestor_9_status_spie), // @[PTW.scala:802:19] .io_ptw_9_status_mie (_ptw_io_requestor_9_status_mie), // @[PTW.scala:802:19] .io_ptw_9_status_sie (_ptw_io_requestor_9_status_sie), // @[PTW.scala:802:19] .io_ptw_9_hstatus_spvp (_ptw_io_requestor_9_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_9_hstatus_spv (_ptw_io_requestor_9_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_9_hstatus_gva (_ptw_io_requestor_9_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_9_gstatus_debug (_ptw_io_requestor_9_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_9_gstatus_cease (_ptw_io_requestor_9_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_9_gstatus_wfi (_ptw_io_requestor_9_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_9_gstatus_isa (_ptw_io_requestor_9_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_9_gstatus_dprv (_ptw_io_requestor_9_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_dv (_ptw_io_requestor_9_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_prv (_ptw_io_requestor_9_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_v (_ptw_io_requestor_9_gstatus_v), // @[PTW.scala:802:19] .io_ptw_9_gstatus_zero2 (_ptw_io_requestor_9_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpv (_ptw_io_requestor_9_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_gva (_ptw_io_requestor_9_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mbe (_ptw_io_requestor_9_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sbe (_ptw_io_requestor_9_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sxl (_ptw_io_requestor_9_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_9_gstatus_zero1 (_ptw_io_requestor_9_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tsr (_ptw_io_requestor_9_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tw (_ptw_io_requestor_9_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tvm (_ptw_io_requestor_9_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mxr (_ptw_io_requestor_9_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sum (_ptw_io_requestor_9_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mprv (_ptw_io_requestor_9_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_fs (_ptw_io_requestor_9_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpp (_ptw_io_requestor_9_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_9_gstatus_vs (_ptw_io_requestor_9_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_9_gstatus_spp (_ptw_io_requestor_9_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpie (_ptw_io_requestor_9_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_ube (_ptw_io_requestor_9_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_9_gstatus_spie (_ptw_io_requestor_9_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_upie (_ptw_io_requestor_9_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mie (_ptw_io_requestor_9_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_hie (_ptw_io_requestor_9_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sie (_ptw_io_requestor_9_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_uie (_ptw_io_requestor_9_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_l (_ptw_io_requestor_9_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_a (_ptw_io_requestor_9_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_x (_ptw_io_requestor_9_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_w (_ptw_io_requestor_9_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_r (_ptw_io_requestor_9_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_addr (_ptw_io_requestor_9_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_mask (_ptw_io_requestor_9_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_l (_ptw_io_requestor_9_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_a (_ptw_io_requestor_9_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_x (_ptw_io_requestor_9_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_w (_ptw_io_requestor_9_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_r (_ptw_io_requestor_9_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_addr (_ptw_io_requestor_9_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_mask (_ptw_io_requestor_9_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_l (_ptw_io_requestor_9_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_a (_ptw_io_requestor_9_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_x (_ptw_io_requestor_9_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_w (_ptw_io_requestor_9_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_r (_ptw_io_requestor_9_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_addr (_ptw_io_requestor_9_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_mask (_ptw_io_requestor_9_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_l (_ptw_io_requestor_9_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_a (_ptw_io_requestor_9_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_x (_ptw_io_requestor_9_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_w (_ptw_io_requestor_9_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_r (_ptw_io_requestor_9_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_addr (_ptw_io_requestor_9_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_mask (_ptw_io_requestor_9_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_l (_ptw_io_requestor_9_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_a (_ptw_io_requestor_9_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_x (_ptw_io_requestor_9_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_w (_ptw_io_requestor_9_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_r (_ptw_io_requestor_9_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_addr (_ptw_io_requestor_9_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_mask (_ptw_io_requestor_9_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_l (_ptw_io_requestor_9_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_a (_ptw_io_requestor_9_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_x (_ptw_io_requestor_9_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_w (_ptw_io_requestor_9_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_r (_ptw_io_requestor_9_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_addr (_ptw_io_requestor_9_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_mask (_ptw_io_requestor_9_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_l (_ptw_io_requestor_9_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_a (_ptw_io_requestor_9_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_x (_ptw_io_requestor_9_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_w (_ptw_io_requestor_9_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_r (_ptw_io_requestor_9_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_addr (_ptw_io_requestor_9_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_mask (_ptw_io_requestor_9_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_l (_ptw_io_requestor_9_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_a (_ptw_io_requestor_9_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_x (_ptw_io_requestor_9_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_w (_ptw_io_requestor_9_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_r (_ptw_io_requestor_9_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_addr (_ptw_io_requestor_9_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_mask (_ptw_io_requestor_9_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_ren (_ptw_io_requestor_9_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_wen (_ptw_io_requestor_9_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_wdata (_ptw_io_requestor_9_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_value (_ptw_io_requestor_9_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_ren (_ptw_io_requestor_9_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_wen (_ptw_io_requestor_9_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_wdata (_ptw_io_requestor_9_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_value (_ptw_io_requestor_9_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_ren (_ptw_io_requestor_9_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_wen (_ptw_io_requestor_9_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_wdata (_ptw_io_requestor_9_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_value (_ptw_io_requestor_9_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_ren (_ptw_io_requestor_9_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_wen (_ptw_io_requestor_9_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_wdata (_ptw_io_requestor_9_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_value (_ptw_io_requestor_9_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_10_req_ready (_ptw_io_requestor_10_req_ready), // @[PTW.scala:802:19] .io_ptw_10_req_valid (_zstd_compressor_io_ptw_10_req_valid), .io_ptw_10_req_bits_bits_addr (_zstd_compressor_io_ptw_10_req_bits_bits_addr), .io_ptw_10_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_10_req_bits_bits_need_gpa), .io_ptw_10_resp_valid (_ptw_io_requestor_10_resp_valid), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_ae_ptw (_ptw_io_requestor_10_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_ae_final (_ptw_io_requestor_10_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pf (_ptw_io_requestor_10_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gf (_ptw_io_requestor_10_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hr (_ptw_io_requestor_10_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hw (_ptw_io_requestor_10_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hx (_ptw_io_requestor_10_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_reserved_for_future (_ptw_io_requestor_10_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_ppn (_ptw_io_requestor_10_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_reserved_for_software (_ptw_io_requestor_10_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_d (_ptw_io_requestor_10_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_a (_ptw_io_requestor_10_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_g (_ptw_io_requestor_10_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_u (_ptw_io_requestor_10_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_x (_ptw_io_requestor_10_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_w (_ptw_io_requestor_10_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_r (_ptw_io_requestor_10_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_v (_ptw_io_requestor_10_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_level (_ptw_io_requestor_10_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_homogeneous (_ptw_io_requestor_10_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_valid (_ptw_io_requestor_10_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_bits (_ptw_io_requestor_10_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_is_pte (_ptw_io_requestor_10_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_10_ptbr_mode (_ptw_io_requestor_10_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_10_ptbr_ppn (_ptw_io_requestor_10_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_10_status_debug (_ptw_io_requestor_10_status_debug), // @[PTW.scala:802:19] .io_ptw_10_status_cease (_ptw_io_requestor_10_status_cease), // @[PTW.scala:802:19] .io_ptw_10_status_wfi (_ptw_io_requestor_10_status_wfi), // @[PTW.scala:802:19] .io_ptw_10_status_isa (_ptw_io_requestor_10_status_isa), // @[PTW.scala:802:19] .io_ptw_10_status_dprv (_ptw_io_requestor_10_status_dprv), // @[PTW.scala:802:19] .io_ptw_10_status_dv (_ptw_io_requestor_10_status_dv), // @[PTW.scala:802:19] .io_ptw_10_status_prv (_ptw_io_requestor_10_status_prv), // @[PTW.scala:802:19] .io_ptw_10_status_v (_ptw_io_requestor_10_status_v), // @[PTW.scala:802:19] .io_ptw_10_status_mpv (_ptw_io_requestor_10_status_mpv), // @[PTW.scala:802:19] .io_ptw_10_status_gva (_ptw_io_requestor_10_status_gva), // @[PTW.scala:802:19] .io_ptw_10_status_tsr (_ptw_io_requestor_10_status_tsr), // @[PTW.scala:802:19] .io_ptw_10_status_tw (_ptw_io_requestor_10_status_tw), // @[PTW.scala:802:19] .io_ptw_10_status_tvm (_ptw_io_requestor_10_status_tvm), // @[PTW.scala:802:19] .io_ptw_10_status_mxr (_ptw_io_requestor_10_status_mxr), // @[PTW.scala:802:19] .io_ptw_10_status_sum (_ptw_io_requestor_10_status_sum), // @[PTW.scala:802:19] .io_ptw_10_status_mprv (_ptw_io_requestor_10_status_mprv), // @[PTW.scala:802:19] .io_ptw_10_status_fs (_ptw_io_requestor_10_status_fs), // @[PTW.scala:802:19] .io_ptw_10_status_mpp (_ptw_io_requestor_10_status_mpp), // @[PTW.scala:802:19] .io_ptw_10_status_spp (_ptw_io_requestor_10_status_spp), // @[PTW.scala:802:19] .io_ptw_10_status_mpie (_ptw_io_requestor_10_status_mpie), // @[PTW.scala:802:19] .io_ptw_10_status_spie (_ptw_io_requestor_10_status_spie), // @[PTW.scala:802:19] .io_ptw_10_status_mie (_ptw_io_requestor_10_status_mie), // @[PTW.scala:802:19] .io_ptw_10_status_sie (_ptw_io_requestor_10_status_sie), // @[PTW.scala:802:19] .io_ptw_10_hstatus_spvp (_ptw_io_requestor_10_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_10_hstatus_spv (_ptw_io_requestor_10_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_10_hstatus_gva (_ptw_io_requestor_10_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_10_gstatus_debug (_ptw_io_requestor_10_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_10_gstatus_cease (_ptw_io_requestor_10_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_10_gstatus_wfi (_ptw_io_requestor_10_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_10_gstatus_isa (_ptw_io_requestor_10_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_10_gstatus_dprv (_ptw_io_requestor_10_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_dv (_ptw_io_requestor_10_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_prv (_ptw_io_requestor_10_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_v (_ptw_io_requestor_10_gstatus_v), // @[PTW.scala:802:19] .io_ptw_10_gstatus_zero2 (_ptw_io_requestor_10_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpv (_ptw_io_requestor_10_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_gva (_ptw_io_requestor_10_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mbe (_ptw_io_requestor_10_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sbe (_ptw_io_requestor_10_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sxl (_ptw_io_requestor_10_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_10_gstatus_zero1 (_ptw_io_requestor_10_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tsr (_ptw_io_requestor_10_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tw (_ptw_io_requestor_10_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tvm (_ptw_io_requestor_10_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mxr (_ptw_io_requestor_10_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sum (_ptw_io_requestor_10_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mprv (_ptw_io_requestor_10_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_fs (_ptw_io_requestor_10_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpp (_ptw_io_requestor_10_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_10_gstatus_vs (_ptw_io_requestor_10_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_10_gstatus_spp (_ptw_io_requestor_10_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpie (_ptw_io_requestor_10_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_ube (_ptw_io_requestor_10_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_10_gstatus_spie (_ptw_io_requestor_10_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_upie (_ptw_io_requestor_10_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mie (_ptw_io_requestor_10_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_hie (_ptw_io_requestor_10_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sie (_ptw_io_requestor_10_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_uie (_ptw_io_requestor_10_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_l (_ptw_io_requestor_10_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_a (_ptw_io_requestor_10_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_x (_ptw_io_requestor_10_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_w (_ptw_io_requestor_10_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_r (_ptw_io_requestor_10_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_addr (_ptw_io_requestor_10_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_mask (_ptw_io_requestor_10_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_l (_ptw_io_requestor_10_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_a (_ptw_io_requestor_10_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_x (_ptw_io_requestor_10_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_w (_ptw_io_requestor_10_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_r (_ptw_io_requestor_10_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_addr (_ptw_io_requestor_10_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_mask (_ptw_io_requestor_10_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_l (_ptw_io_requestor_10_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_a (_ptw_io_requestor_10_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_x (_ptw_io_requestor_10_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_w (_ptw_io_requestor_10_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_r (_ptw_io_requestor_10_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_addr (_ptw_io_requestor_10_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_mask (_ptw_io_requestor_10_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_l (_ptw_io_requestor_10_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_a (_ptw_io_requestor_10_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_x (_ptw_io_requestor_10_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_w (_ptw_io_requestor_10_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_r (_ptw_io_requestor_10_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_addr (_ptw_io_requestor_10_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_mask (_ptw_io_requestor_10_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_l (_ptw_io_requestor_10_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_a (_ptw_io_requestor_10_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_x (_ptw_io_requestor_10_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_w (_ptw_io_requestor_10_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_r (_ptw_io_requestor_10_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_addr (_ptw_io_requestor_10_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_mask (_ptw_io_requestor_10_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_l (_ptw_io_requestor_10_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_a (_ptw_io_requestor_10_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_x (_ptw_io_requestor_10_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_w (_ptw_io_requestor_10_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_r (_ptw_io_requestor_10_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_addr (_ptw_io_requestor_10_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_mask (_ptw_io_requestor_10_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_l (_ptw_io_requestor_10_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_a (_ptw_io_requestor_10_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_x (_ptw_io_requestor_10_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_w (_ptw_io_requestor_10_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_r (_ptw_io_requestor_10_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_addr (_ptw_io_requestor_10_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_mask (_ptw_io_requestor_10_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_l (_ptw_io_requestor_10_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_a (_ptw_io_requestor_10_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_x (_ptw_io_requestor_10_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_w (_ptw_io_requestor_10_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_r (_ptw_io_requestor_10_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_addr (_ptw_io_requestor_10_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_mask (_ptw_io_requestor_10_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_ren (_ptw_io_requestor_10_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_wen (_ptw_io_requestor_10_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_wdata (_ptw_io_requestor_10_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_value (_ptw_io_requestor_10_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_ren (_ptw_io_requestor_10_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_wen (_ptw_io_requestor_10_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_wdata (_ptw_io_requestor_10_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_value (_ptw_io_requestor_10_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_ren (_ptw_io_requestor_10_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_wen (_ptw_io_requestor_10_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_wdata (_ptw_io_requestor_10_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_value (_ptw_io_requestor_10_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_ren (_ptw_io_requestor_10_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_wen (_ptw_io_requestor_10_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_wdata (_ptw_io_requestor_10_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_value (_ptw_io_requestor_10_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_11_req_ready (_ptw_io_requestor_11_req_ready), // @[PTW.scala:802:19] .io_ptw_11_req_valid (_zstd_compressor_io_ptw_11_req_valid), .io_ptw_11_req_bits_bits_addr (_zstd_compressor_io_ptw_11_req_bits_bits_addr), .io_ptw_11_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_11_req_bits_bits_need_gpa), .io_ptw_11_resp_valid (_ptw_io_requestor_11_resp_valid), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_ae_ptw (_ptw_io_requestor_11_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_ae_final (_ptw_io_requestor_11_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pf (_ptw_io_requestor_11_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gf (_ptw_io_requestor_11_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hr (_ptw_io_requestor_11_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hw (_ptw_io_requestor_11_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hx (_ptw_io_requestor_11_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_reserved_for_future (_ptw_io_requestor_11_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_ppn (_ptw_io_requestor_11_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_reserved_for_software (_ptw_io_requestor_11_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_d (_ptw_io_requestor_11_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_a (_ptw_io_requestor_11_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_g (_ptw_io_requestor_11_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_u (_ptw_io_requestor_11_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_x (_ptw_io_requestor_11_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_w (_ptw_io_requestor_11_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_r (_ptw_io_requestor_11_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_v (_ptw_io_requestor_11_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_level (_ptw_io_requestor_11_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_homogeneous (_ptw_io_requestor_11_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_valid (_ptw_io_requestor_11_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_bits (_ptw_io_requestor_11_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_is_pte (_ptw_io_requestor_11_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_11_ptbr_mode (_ptw_io_requestor_11_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_11_ptbr_ppn (_ptw_io_requestor_11_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_11_status_debug (_ptw_io_requestor_11_status_debug), // @[PTW.scala:802:19] .io_ptw_11_status_cease (_ptw_io_requestor_11_status_cease), // @[PTW.scala:802:19] .io_ptw_11_status_wfi (_ptw_io_requestor_11_status_wfi), // @[PTW.scala:802:19] .io_ptw_11_status_isa (_ptw_io_requestor_11_status_isa), // @[PTW.scala:802:19] .io_ptw_11_status_dprv (_ptw_io_requestor_11_status_dprv), // @[PTW.scala:802:19] .io_ptw_11_status_dv (_ptw_io_requestor_11_status_dv), // @[PTW.scala:802:19] .io_ptw_11_status_prv (_ptw_io_requestor_11_status_prv), // @[PTW.scala:802:19] .io_ptw_11_status_v (_ptw_io_requestor_11_status_v), // @[PTW.scala:802:19] .io_ptw_11_status_mpv (_ptw_io_requestor_11_status_mpv), // @[PTW.scala:802:19] .io_ptw_11_status_gva (_ptw_io_requestor_11_status_gva), // @[PTW.scala:802:19] .io_ptw_11_status_tsr (_ptw_io_requestor_11_status_tsr), // @[PTW.scala:802:19] .io_ptw_11_status_tw (_ptw_io_requestor_11_status_tw), // @[PTW.scala:802:19] .io_ptw_11_status_tvm (_ptw_io_requestor_11_status_tvm), // @[PTW.scala:802:19] .io_ptw_11_status_mxr (_ptw_io_requestor_11_status_mxr), // @[PTW.scala:802:19] .io_ptw_11_status_sum (_ptw_io_requestor_11_status_sum), // @[PTW.scala:802:19] .io_ptw_11_status_mprv (_ptw_io_requestor_11_status_mprv), // @[PTW.scala:802:19] .io_ptw_11_status_fs (_ptw_io_requestor_11_status_fs), // @[PTW.scala:802:19] .io_ptw_11_status_mpp (_ptw_io_requestor_11_status_mpp), // @[PTW.scala:802:19] .io_ptw_11_status_spp (_ptw_io_requestor_11_status_spp), // @[PTW.scala:802:19] .io_ptw_11_status_mpie (_ptw_io_requestor_11_status_mpie), // @[PTW.scala:802:19] .io_ptw_11_status_spie (_ptw_io_requestor_11_status_spie), // @[PTW.scala:802:19] .io_ptw_11_status_mie (_ptw_io_requestor_11_status_mie), // @[PTW.scala:802:19] .io_ptw_11_status_sie (_ptw_io_requestor_11_status_sie), // @[PTW.scala:802:19] .io_ptw_11_hstatus_spvp (_ptw_io_requestor_11_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_11_hstatus_spv (_ptw_io_requestor_11_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_11_hstatus_gva (_ptw_io_requestor_11_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_11_gstatus_debug (_ptw_io_requestor_11_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_11_gstatus_cease (_ptw_io_requestor_11_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_11_gstatus_wfi (_ptw_io_requestor_11_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_11_gstatus_isa (_ptw_io_requestor_11_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_11_gstatus_dprv (_ptw_io_requestor_11_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_dv (_ptw_io_requestor_11_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_prv (_ptw_io_requestor_11_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_v (_ptw_io_requestor_11_gstatus_v), // @[PTW.scala:802:19] .io_ptw_11_gstatus_zero2 (_ptw_io_requestor_11_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpv (_ptw_io_requestor_11_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_gva (_ptw_io_requestor_11_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mbe (_ptw_io_requestor_11_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sbe (_ptw_io_requestor_11_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sxl (_ptw_io_requestor_11_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_11_gstatus_zero1 (_ptw_io_requestor_11_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tsr (_ptw_io_requestor_11_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tw (_ptw_io_requestor_11_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tvm (_ptw_io_requestor_11_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mxr (_ptw_io_requestor_11_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sum (_ptw_io_requestor_11_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mprv (_ptw_io_requestor_11_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_fs (_ptw_io_requestor_11_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpp (_ptw_io_requestor_11_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_11_gstatus_vs (_ptw_io_requestor_11_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_11_gstatus_spp (_ptw_io_requestor_11_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpie (_ptw_io_requestor_11_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_ube (_ptw_io_requestor_11_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_11_gstatus_spie (_ptw_io_requestor_11_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_upie (_ptw_io_requestor_11_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mie (_ptw_io_requestor_11_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_hie (_ptw_io_requestor_11_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sie (_ptw_io_requestor_11_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_uie (_ptw_io_requestor_11_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_l (_ptw_io_requestor_11_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_a (_ptw_io_requestor_11_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_x (_ptw_io_requestor_11_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_w (_ptw_io_requestor_11_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_r (_ptw_io_requestor_11_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_addr (_ptw_io_requestor_11_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_mask (_ptw_io_requestor_11_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_l (_ptw_io_requestor_11_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_a (_ptw_io_requestor_11_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_x (_ptw_io_requestor_11_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_w (_ptw_io_requestor_11_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_r (_ptw_io_requestor_11_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_addr (_ptw_io_requestor_11_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_mask (_ptw_io_requestor_11_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_l (_ptw_io_requestor_11_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_a (_ptw_io_requestor_11_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_x (_ptw_io_requestor_11_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_w (_ptw_io_requestor_11_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_r (_ptw_io_requestor_11_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_addr (_ptw_io_requestor_11_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_mask (_ptw_io_requestor_11_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_l (_ptw_io_requestor_11_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_a (_ptw_io_requestor_11_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_x (_ptw_io_requestor_11_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_w (_ptw_io_requestor_11_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_r (_ptw_io_requestor_11_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_addr (_ptw_io_requestor_11_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_mask (_ptw_io_requestor_11_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_l (_ptw_io_requestor_11_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_a (_ptw_io_requestor_11_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_x (_ptw_io_requestor_11_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_w (_ptw_io_requestor_11_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_r (_ptw_io_requestor_11_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_addr (_ptw_io_requestor_11_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_mask (_ptw_io_requestor_11_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_l (_ptw_io_requestor_11_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_a (_ptw_io_requestor_11_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_x (_ptw_io_requestor_11_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_w (_ptw_io_requestor_11_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_r (_ptw_io_requestor_11_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_addr (_ptw_io_requestor_11_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_mask (_ptw_io_requestor_11_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_l (_ptw_io_requestor_11_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_a (_ptw_io_requestor_11_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_x (_ptw_io_requestor_11_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_w (_ptw_io_requestor_11_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_r (_ptw_io_requestor_11_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_addr (_ptw_io_requestor_11_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_mask (_ptw_io_requestor_11_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_l (_ptw_io_requestor_11_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_a (_ptw_io_requestor_11_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_x (_ptw_io_requestor_11_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_w (_ptw_io_requestor_11_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_r (_ptw_io_requestor_11_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_addr (_ptw_io_requestor_11_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_mask (_ptw_io_requestor_11_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_ren (_ptw_io_requestor_11_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_wen (_ptw_io_requestor_11_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_wdata (_ptw_io_requestor_11_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_value (_ptw_io_requestor_11_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_ren (_ptw_io_requestor_11_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_wen (_ptw_io_requestor_11_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_wdata (_ptw_io_requestor_11_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_value (_ptw_io_requestor_11_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_ren (_ptw_io_requestor_11_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_wen (_ptw_io_requestor_11_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_wdata (_ptw_io_requestor_11_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_value (_ptw_io_requestor_11_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_ren (_ptw_io_requestor_11_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_wen (_ptw_io_requestor_11_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_wdata (_ptw_io_requestor_11_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_value (_ptw_io_requestor_11_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_12_req_ready (_ptw_io_requestor_12_req_ready), // @[PTW.scala:802:19] .io_ptw_12_req_valid (_zstd_compressor_io_ptw_12_req_valid), .io_ptw_12_req_bits_bits_addr (_zstd_compressor_io_ptw_12_req_bits_bits_addr), .io_ptw_12_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_12_req_bits_bits_need_gpa), .io_ptw_12_resp_valid (_ptw_io_requestor_12_resp_valid), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_ae_ptw (_ptw_io_requestor_12_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_ae_final (_ptw_io_requestor_12_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pf (_ptw_io_requestor_12_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gf (_ptw_io_requestor_12_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hr (_ptw_io_requestor_12_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hw (_ptw_io_requestor_12_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hx (_ptw_io_requestor_12_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_reserved_for_future (_ptw_io_requestor_12_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_ppn (_ptw_io_requestor_12_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_reserved_for_software (_ptw_io_requestor_12_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_d (_ptw_io_requestor_12_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_a (_ptw_io_requestor_12_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_g (_ptw_io_requestor_12_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_u (_ptw_io_requestor_12_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_x (_ptw_io_requestor_12_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_w (_ptw_io_requestor_12_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_r (_ptw_io_requestor_12_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_v (_ptw_io_requestor_12_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_level (_ptw_io_requestor_12_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_homogeneous (_ptw_io_requestor_12_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_valid (_ptw_io_requestor_12_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_bits (_ptw_io_requestor_12_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_is_pte (_ptw_io_requestor_12_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_12_ptbr_mode (_ptw_io_requestor_12_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_12_ptbr_ppn (_ptw_io_requestor_12_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_12_status_debug (_ptw_io_requestor_12_status_debug), // @[PTW.scala:802:19] .io_ptw_12_status_cease (_ptw_io_requestor_12_status_cease), // @[PTW.scala:802:19] .io_ptw_12_status_wfi (_ptw_io_requestor_12_status_wfi), // @[PTW.scala:802:19] .io_ptw_12_status_isa (_ptw_io_requestor_12_status_isa), // @[PTW.scala:802:19] .io_ptw_12_status_dprv (_ptw_io_requestor_12_status_dprv), // @[PTW.scala:802:19] .io_ptw_12_status_dv (_ptw_io_requestor_12_status_dv), // @[PTW.scala:802:19] .io_ptw_12_status_prv (_ptw_io_requestor_12_status_prv), // @[PTW.scala:802:19] .io_ptw_12_status_v (_ptw_io_requestor_12_status_v), // @[PTW.scala:802:19] .io_ptw_12_status_mpv (_ptw_io_requestor_12_status_mpv), // @[PTW.scala:802:19] .io_ptw_12_status_gva (_ptw_io_requestor_12_status_gva), // @[PTW.scala:802:19] .io_ptw_12_status_tsr (_ptw_io_requestor_12_status_tsr), // @[PTW.scala:802:19] .io_ptw_12_status_tw (_ptw_io_requestor_12_status_tw), // @[PTW.scala:802:19] .io_ptw_12_status_tvm (_ptw_io_requestor_12_status_tvm), // @[PTW.scala:802:19] .io_ptw_12_status_mxr (_ptw_io_requestor_12_status_mxr), // @[PTW.scala:802:19] .io_ptw_12_status_sum (_ptw_io_requestor_12_status_sum), // @[PTW.scala:802:19] .io_ptw_12_status_mprv (_ptw_io_requestor_12_status_mprv), // @[PTW.scala:802:19] .io_ptw_12_status_fs (_ptw_io_requestor_12_status_fs), // @[PTW.scala:802:19] .io_ptw_12_status_mpp (_ptw_io_requestor_12_status_mpp), // @[PTW.scala:802:19] .io_ptw_12_status_spp (_ptw_io_requestor_12_status_spp), // @[PTW.scala:802:19] .io_ptw_12_status_mpie (_ptw_io_requestor_12_status_mpie), // @[PTW.scala:802:19] .io_ptw_12_status_spie (_ptw_io_requestor_12_status_spie), // @[PTW.scala:802:19] .io_ptw_12_status_mie (_ptw_io_requestor_12_status_mie), // @[PTW.scala:802:19] .io_ptw_12_status_sie (_ptw_io_requestor_12_status_sie), // @[PTW.scala:802:19] .io_ptw_12_hstatus_spvp (_ptw_io_requestor_12_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_12_hstatus_spv (_ptw_io_requestor_12_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_12_hstatus_gva (_ptw_io_requestor_12_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_12_gstatus_debug (_ptw_io_requestor_12_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_12_gstatus_cease (_ptw_io_requestor_12_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_12_gstatus_wfi (_ptw_io_requestor_12_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_12_gstatus_isa (_ptw_io_requestor_12_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_12_gstatus_dprv (_ptw_io_requestor_12_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_dv (_ptw_io_requestor_12_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_prv (_ptw_io_requestor_12_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_v (_ptw_io_requestor_12_gstatus_v), // @[PTW.scala:802:19] .io_ptw_12_gstatus_zero2 (_ptw_io_requestor_12_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpv (_ptw_io_requestor_12_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_gva (_ptw_io_requestor_12_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mbe (_ptw_io_requestor_12_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sbe (_ptw_io_requestor_12_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sxl (_ptw_io_requestor_12_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_12_gstatus_zero1 (_ptw_io_requestor_12_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tsr (_ptw_io_requestor_12_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tw (_ptw_io_requestor_12_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tvm (_ptw_io_requestor_12_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mxr (_ptw_io_requestor_12_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sum (_ptw_io_requestor_12_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mprv (_ptw_io_requestor_12_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_fs (_ptw_io_requestor_12_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpp (_ptw_io_requestor_12_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_12_gstatus_vs (_ptw_io_requestor_12_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_12_gstatus_spp (_ptw_io_requestor_12_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpie (_ptw_io_requestor_12_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_ube (_ptw_io_requestor_12_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_12_gstatus_spie (_ptw_io_requestor_12_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_upie (_ptw_io_requestor_12_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mie (_ptw_io_requestor_12_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_hie (_ptw_io_requestor_12_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sie (_ptw_io_requestor_12_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_uie (_ptw_io_requestor_12_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_l (_ptw_io_requestor_12_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_a (_ptw_io_requestor_12_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_x (_ptw_io_requestor_12_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_w (_ptw_io_requestor_12_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_r (_ptw_io_requestor_12_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_addr (_ptw_io_requestor_12_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_mask (_ptw_io_requestor_12_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_l (_ptw_io_requestor_12_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_a (_ptw_io_requestor_12_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_x (_ptw_io_requestor_12_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_w (_ptw_io_requestor_12_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_r (_ptw_io_requestor_12_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_addr (_ptw_io_requestor_12_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_mask (_ptw_io_requestor_12_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_l (_ptw_io_requestor_12_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_a (_ptw_io_requestor_12_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_x (_ptw_io_requestor_12_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_w (_ptw_io_requestor_12_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_r (_ptw_io_requestor_12_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_addr (_ptw_io_requestor_12_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_mask (_ptw_io_requestor_12_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_l (_ptw_io_requestor_12_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_a (_ptw_io_requestor_12_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_x (_ptw_io_requestor_12_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_w (_ptw_io_requestor_12_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_r (_ptw_io_requestor_12_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_addr (_ptw_io_requestor_12_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_mask (_ptw_io_requestor_12_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_l (_ptw_io_requestor_12_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_a (_ptw_io_requestor_12_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_x (_ptw_io_requestor_12_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_w (_ptw_io_requestor_12_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_r (_ptw_io_requestor_12_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_addr (_ptw_io_requestor_12_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_mask (_ptw_io_requestor_12_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_l (_ptw_io_requestor_12_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_a (_ptw_io_requestor_12_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_x (_ptw_io_requestor_12_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_w (_ptw_io_requestor_12_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_r (_ptw_io_requestor_12_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_addr (_ptw_io_requestor_12_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_mask (_ptw_io_requestor_12_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_l (_ptw_io_requestor_12_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_a (_ptw_io_requestor_12_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_x (_ptw_io_requestor_12_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_w (_ptw_io_requestor_12_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_r (_ptw_io_requestor_12_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_addr (_ptw_io_requestor_12_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_mask (_ptw_io_requestor_12_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_l (_ptw_io_requestor_12_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_a (_ptw_io_requestor_12_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_x (_ptw_io_requestor_12_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_w (_ptw_io_requestor_12_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_r (_ptw_io_requestor_12_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_addr (_ptw_io_requestor_12_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_mask (_ptw_io_requestor_12_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_ren (_ptw_io_requestor_12_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_wen (_ptw_io_requestor_12_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_wdata (_ptw_io_requestor_12_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_value (_ptw_io_requestor_12_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_ren (_ptw_io_requestor_12_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_wen (_ptw_io_requestor_12_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_wdata (_ptw_io_requestor_12_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_value (_ptw_io_requestor_12_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_ren (_ptw_io_requestor_12_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_wen (_ptw_io_requestor_12_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_wdata (_ptw_io_requestor_12_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_value (_ptw_io_requestor_12_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_ren (_ptw_io_requestor_12_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_wen (_ptw_io_requestor_12_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_wdata (_ptw_io_requestor_12_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_value (_ptw_io_requestor_12_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_13_req_ready (_ptw_io_requestor_13_req_ready), // @[PTW.scala:802:19] .io_ptw_13_req_valid (_zstd_compressor_io_ptw_13_req_valid), .io_ptw_13_req_bits_bits_addr (_zstd_compressor_io_ptw_13_req_bits_bits_addr), .io_ptw_13_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_13_req_bits_bits_need_gpa), .io_ptw_13_resp_valid (_ptw_io_requestor_13_resp_valid), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_ae_ptw (_ptw_io_requestor_13_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_ae_final (_ptw_io_requestor_13_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pf (_ptw_io_requestor_13_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gf (_ptw_io_requestor_13_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hr (_ptw_io_requestor_13_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hw (_ptw_io_requestor_13_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hx (_ptw_io_requestor_13_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_reserved_for_future (_ptw_io_requestor_13_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_ppn (_ptw_io_requestor_13_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_reserved_for_software (_ptw_io_requestor_13_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_d (_ptw_io_requestor_13_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_a (_ptw_io_requestor_13_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_g (_ptw_io_requestor_13_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_u (_ptw_io_requestor_13_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_x (_ptw_io_requestor_13_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_w (_ptw_io_requestor_13_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_r (_ptw_io_requestor_13_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_v (_ptw_io_requestor_13_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_level (_ptw_io_requestor_13_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_homogeneous (_ptw_io_requestor_13_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_valid (_ptw_io_requestor_13_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_bits (_ptw_io_requestor_13_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_is_pte (_ptw_io_requestor_13_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_13_ptbr_mode (_ptw_io_requestor_13_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_13_ptbr_ppn (_ptw_io_requestor_13_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_13_status_debug (_ptw_io_requestor_13_status_debug), // @[PTW.scala:802:19] .io_ptw_13_status_cease (_ptw_io_requestor_13_status_cease), // @[PTW.scala:802:19] .io_ptw_13_status_wfi (_ptw_io_requestor_13_status_wfi), // @[PTW.scala:802:19] .io_ptw_13_status_isa (_ptw_io_requestor_13_status_isa), // @[PTW.scala:802:19] .io_ptw_13_status_dprv (_ptw_io_requestor_13_status_dprv), // @[PTW.scala:802:19] .io_ptw_13_status_dv (_ptw_io_requestor_13_status_dv), // @[PTW.scala:802:19] .io_ptw_13_status_prv (_ptw_io_requestor_13_status_prv), // @[PTW.scala:802:19] .io_ptw_13_status_v (_ptw_io_requestor_13_status_v), // @[PTW.scala:802:19] .io_ptw_13_status_mpv (_ptw_io_requestor_13_status_mpv), // @[PTW.scala:802:19] .io_ptw_13_status_gva (_ptw_io_requestor_13_status_gva), // @[PTW.scala:802:19] .io_ptw_13_status_tsr (_ptw_io_requestor_13_status_tsr), // @[PTW.scala:802:19] .io_ptw_13_status_tw (_ptw_io_requestor_13_status_tw), // @[PTW.scala:802:19] .io_ptw_13_status_tvm (_ptw_io_requestor_13_status_tvm), // @[PTW.scala:802:19] .io_ptw_13_status_mxr (_ptw_io_requestor_13_status_mxr), // @[PTW.scala:802:19] .io_ptw_13_status_sum (_ptw_io_requestor_13_status_sum), // @[PTW.scala:802:19] .io_ptw_13_status_mprv (_ptw_io_requestor_13_status_mprv), // @[PTW.scala:802:19] .io_ptw_13_status_fs (_ptw_io_requestor_13_status_fs), // @[PTW.scala:802:19] .io_ptw_13_status_mpp (_ptw_io_requestor_13_status_mpp), // @[PTW.scala:802:19] .io_ptw_13_status_spp (_ptw_io_requestor_13_status_spp), // @[PTW.scala:802:19] .io_ptw_13_status_mpie (_ptw_io_requestor_13_status_mpie), // @[PTW.scala:802:19] .io_ptw_13_status_spie (_ptw_io_requestor_13_status_spie), // @[PTW.scala:802:19] .io_ptw_13_status_mie (_ptw_io_requestor_13_status_mie), // @[PTW.scala:802:19] .io_ptw_13_status_sie (_ptw_io_requestor_13_status_sie), // @[PTW.scala:802:19] .io_ptw_13_hstatus_spvp (_ptw_io_requestor_13_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_13_hstatus_spv (_ptw_io_requestor_13_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_13_hstatus_gva (_ptw_io_requestor_13_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_13_gstatus_debug (_ptw_io_requestor_13_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_13_gstatus_cease (_ptw_io_requestor_13_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_13_gstatus_wfi (_ptw_io_requestor_13_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_13_gstatus_isa (_ptw_io_requestor_13_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_13_gstatus_dprv (_ptw_io_requestor_13_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_dv (_ptw_io_requestor_13_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_prv (_ptw_io_requestor_13_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_v (_ptw_io_requestor_13_gstatus_v), // @[PTW.scala:802:19] .io_ptw_13_gstatus_zero2 (_ptw_io_requestor_13_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpv (_ptw_io_requestor_13_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_gva (_ptw_io_requestor_13_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mbe (_ptw_io_requestor_13_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sbe (_ptw_io_requestor_13_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sxl (_ptw_io_requestor_13_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_13_gstatus_zero1 (_ptw_io_requestor_13_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tsr (_ptw_io_requestor_13_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tw (_ptw_io_requestor_13_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tvm (_ptw_io_requestor_13_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mxr (_ptw_io_requestor_13_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sum (_ptw_io_requestor_13_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mprv (_ptw_io_requestor_13_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_fs (_ptw_io_requestor_13_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpp (_ptw_io_requestor_13_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_13_gstatus_vs (_ptw_io_requestor_13_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_13_gstatus_spp (_ptw_io_requestor_13_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpie (_ptw_io_requestor_13_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_ube (_ptw_io_requestor_13_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_13_gstatus_spie (_ptw_io_requestor_13_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_upie (_ptw_io_requestor_13_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mie (_ptw_io_requestor_13_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_hie (_ptw_io_requestor_13_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sie (_ptw_io_requestor_13_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_uie (_ptw_io_requestor_13_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_l (_ptw_io_requestor_13_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_a (_ptw_io_requestor_13_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_x (_ptw_io_requestor_13_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_w (_ptw_io_requestor_13_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_r (_ptw_io_requestor_13_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_addr (_ptw_io_requestor_13_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_mask (_ptw_io_requestor_13_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_l (_ptw_io_requestor_13_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_a (_ptw_io_requestor_13_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_x (_ptw_io_requestor_13_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_w (_ptw_io_requestor_13_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_r (_ptw_io_requestor_13_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_addr (_ptw_io_requestor_13_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_mask (_ptw_io_requestor_13_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_l (_ptw_io_requestor_13_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_a (_ptw_io_requestor_13_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_x (_ptw_io_requestor_13_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_w (_ptw_io_requestor_13_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_r (_ptw_io_requestor_13_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_addr (_ptw_io_requestor_13_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_mask (_ptw_io_requestor_13_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_l (_ptw_io_requestor_13_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_a (_ptw_io_requestor_13_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_x (_ptw_io_requestor_13_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_w (_ptw_io_requestor_13_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_r (_ptw_io_requestor_13_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_addr (_ptw_io_requestor_13_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_mask (_ptw_io_requestor_13_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_l (_ptw_io_requestor_13_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_a (_ptw_io_requestor_13_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_x (_ptw_io_requestor_13_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_w (_ptw_io_requestor_13_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_r (_ptw_io_requestor_13_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_addr (_ptw_io_requestor_13_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_mask (_ptw_io_requestor_13_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_l (_ptw_io_requestor_13_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_a (_ptw_io_requestor_13_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_x (_ptw_io_requestor_13_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_w (_ptw_io_requestor_13_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_r (_ptw_io_requestor_13_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_addr (_ptw_io_requestor_13_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_mask (_ptw_io_requestor_13_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_l (_ptw_io_requestor_13_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_a (_ptw_io_requestor_13_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_x (_ptw_io_requestor_13_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_w (_ptw_io_requestor_13_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_r (_ptw_io_requestor_13_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_addr (_ptw_io_requestor_13_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_mask (_ptw_io_requestor_13_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_l (_ptw_io_requestor_13_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_a (_ptw_io_requestor_13_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_x (_ptw_io_requestor_13_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_w (_ptw_io_requestor_13_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_r (_ptw_io_requestor_13_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_addr (_ptw_io_requestor_13_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_mask (_ptw_io_requestor_13_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_ren (_ptw_io_requestor_13_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_wen (_ptw_io_requestor_13_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_wdata (_ptw_io_requestor_13_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_value (_ptw_io_requestor_13_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_ren (_ptw_io_requestor_13_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_wen (_ptw_io_requestor_13_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_wdata (_ptw_io_requestor_13_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_value (_ptw_io_requestor_13_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_ren (_ptw_io_requestor_13_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_wen (_ptw_io_requestor_13_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_wdata (_ptw_io_requestor_13_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_value (_ptw_io_requestor_13_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_ren (_ptw_io_requestor_13_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_wen (_ptw_io_requestor_13_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_wdata (_ptw_io_requestor_13_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_value (_ptw_io_requestor_13_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_14_req_ready (_ptw_io_requestor_14_req_ready), // @[PTW.scala:802:19] .io_ptw_14_req_valid (_zstd_compressor_io_ptw_14_req_valid), .io_ptw_14_req_bits_bits_addr (_zstd_compressor_io_ptw_14_req_bits_bits_addr), .io_ptw_14_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_14_req_bits_bits_need_gpa), .io_ptw_14_resp_valid (_ptw_io_requestor_14_resp_valid), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_ae_ptw (_ptw_io_requestor_14_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_ae_final (_ptw_io_requestor_14_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pf (_ptw_io_requestor_14_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gf (_ptw_io_requestor_14_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hr (_ptw_io_requestor_14_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hw (_ptw_io_requestor_14_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hx (_ptw_io_requestor_14_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_reserved_for_future (_ptw_io_requestor_14_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_ppn (_ptw_io_requestor_14_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_reserved_for_software (_ptw_io_requestor_14_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_d (_ptw_io_requestor_14_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_a (_ptw_io_requestor_14_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_g (_ptw_io_requestor_14_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_u (_ptw_io_requestor_14_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_x (_ptw_io_requestor_14_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_w (_ptw_io_requestor_14_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_r (_ptw_io_requestor_14_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_v (_ptw_io_requestor_14_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_level (_ptw_io_requestor_14_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_homogeneous (_ptw_io_requestor_14_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_valid (_ptw_io_requestor_14_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_bits (_ptw_io_requestor_14_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_is_pte (_ptw_io_requestor_14_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_14_ptbr_mode (_ptw_io_requestor_14_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_14_ptbr_ppn (_ptw_io_requestor_14_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_14_status_debug (_ptw_io_requestor_14_status_debug), // @[PTW.scala:802:19] .io_ptw_14_status_cease (_ptw_io_requestor_14_status_cease), // @[PTW.scala:802:19] .io_ptw_14_status_wfi (_ptw_io_requestor_14_status_wfi), // @[PTW.scala:802:19] .io_ptw_14_status_isa (_ptw_io_requestor_14_status_isa), // @[PTW.scala:802:19] .io_ptw_14_status_dprv (_ptw_io_requestor_14_status_dprv), // @[PTW.scala:802:19] .io_ptw_14_status_dv (_ptw_io_requestor_14_status_dv), // @[PTW.scala:802:19] .io_ptw_14_status_prv (_ptw_io_requestor_14_status_prv), // @[PTW.scala:802:19] .io_ptw_14_status_v (_ptw_io_requestor_14_status_v), // @[PTW.scala:802:19] .io_ptw_14_status_mpv (_ptw_io_requestor_14_status_mpv), // @[PTW.scala:802:19] .io_ptw_14_status_gva (_ptw_io_requestor_14_status_gva), // @[PTW.scala:802:19] .io_ptw_14_status_tsr (_ptw_io_requestor_14_status_tsr), // @[PTW.scala:802:19] .io_ptw_14_status_tw (_ptw_io_requestor_14_status_tw), // @[PTW.scala:802:19] .io_ptw_14_status_tvm (_ptw_io_requestor_14_status_tvm), // @[PTW.scala:802:19] .io_ptw_14_status_mxr (_ptw_io_requestor_14_status_mxr), // @[PTW.scala:802:19] .io_ptw_14_status_sum (_ptw_io_requestor_14_status_sum), // @[PTW.scala:802:19] .io_ptw_14_status_mprv (_ptw_io_requestor_14_status_mprv), // @[PTW.scala:802:19] .io_ptw_14_status_fs (_ptw_io_requestor_14_status_fs), // @[PTW.scala:802:19] .io_ptw_14_status_mpp (_ptw_io_requestor_14_status_mpp), // @[PTW.scala:802:19] .io_ptw_14_status_spp (_ptw_io_requestor_14_status_spp), // @[PTW.scala:802:19] .io_ptw_14_status_mpie (_ptw_io_requestor_14_status_mpie), // @[PTW.scala:802:19] .io_ptw_14_status_spie (_ptw_io_requestor_14_status_spie), // @[PTW.scala:802:19] .io_ptw_14_status_mie (_ptw_io_requestor_14_status_mie), // @[PTW.scala:802:19] .io_ptw_14_status_sie (_ptw_io_requestor_14_status_sie), // @[PTW.scala:802:19] .io_ptw_14_hstatus_spvp (_ptw_io_requestor_14_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_14_hstatus_spv (_ptw_io_requestor_14_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_14_hstatus_gva (_ptw_io_requestor_14_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_14_gstatus_debug (_ptw_io_requestor_14_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_14_gstatus_cease (_ptw_io_requestor_14_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_14_gstatus_wfi (_ptw_io_requestor_14_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_14_gstatus_isa (_ptw_io_requestor_14_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_14_gstatus_dprv (_ptw_io_requestor_14_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_dv (_ptw_io_requestor_14_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_prv (_ptw_io_requestor_14_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_v (_ptw_io_requestor_14_gstatus_v), // @[PTW.scala:802:19] .io_ptw_14_gstatus_zero2 (_ptw_io_requestor_14_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpv (_ptw_io_requestor_14_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_gva (_ptw_io_requestor_14_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mbe (_ptw_io_requestor_14_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sbe (_ptw_io_requestor_14_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sxl (_ptw_io_requestor_14_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_14_gstatus_zero1 (_ptw_io_requestor_14_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tsr (_ptw_io_requestor_14_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tw (_ptw_io_requestor_14_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tvm (_ptw_io_requestor_14_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mxr (_ptw_io_requestor_14_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sum (_ptw_io_requestor_14_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mprv (_ptw_io_requestor_14_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_fs (_ptw_io_requestor_14_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpp (_ptw_io_requestor_14_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_14_gstatus_vs (_ptw_io_requestor_14_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_14_gstatus_spp (_ptw_io_requestor_14_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpie (_ptw_io_requestor_14_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_ube (_ptw_io_requestor_14_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_14_gstatus_spie (_ptw_io_requestor_14_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_upie (_ptw_io_requestor_14_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mie (_ptw_io_requestor_14_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_hie (_ptw_io_requestor_14_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sie (_ptw_io_requestor_14_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_uie (_ptw_io_requestor_14_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_l (_ptw_io_requestor_14_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_a (_ptw_io_requestor_14_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_x (_ptw_io_requestor_14_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_w (_ptw_io_requestor_14_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_r (_ptw_io_requestor_14_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_addr (_ptw_io_requestor_14_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_mask (_ptw_io_requestor_14_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_l (_ptw_io_requestor_14_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_a (_ptw_io_requestor_14_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_x (_ptw_io_requestor_14_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_w (_ptw_io_requestor_14_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_r (_ptw_io_requestor_14_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_addr (_ptw_io_requestor_14_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_mask (_ptw_io_requestor_14_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_l (_ptw_io_requestor_14_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_a (_ptw_io_requestor_14_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_x (_ptw_io_requestor_14_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_w (_ptw_io_requestor_14_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_r (_ptw_io_requestor_14_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_addr (_ptw_io_requestor_14_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_mask (_ptw_io_requestor_14_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_l (_ptw_io_requestor_14_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_a (_ptw_io_requestor_14_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_x (_ptw_io_requestor_14_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_w (_ptw_io_requestor_14_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_r (_ptw_io_requestor_14_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_addr (_ptw_io_requestor_14_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_mask (_ptw_io_requestor_14_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_l (_ptw_io_requestor_14_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_a (_ptw_io_requestor_14_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_x (_ptw_io_requestor_14_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_w (_ptw_io_requestor_14_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_r (_ptw_io_requestor_14_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_addr (_ptw_io_requestor_14_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_mask (_ptw_io_requestor_14_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_l (_ptw_io_requestor_14_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_a (_ptw_io_requestor_14_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_x (_ptw_io_requestor_14_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_w (_ptw_io_requestor_14_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_r (_ptw_io_requestor_14_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_addr (_ptw_io_requestor_14_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_mask (_ptw_io_requestor_14_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_l (_ptw_io_requestor_14_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_a (_ptw_io_requestor_14_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_x (_ptw_io_requestor_14_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_w (_ptw_io_requestor_14_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_r (_ptw_io_requestor_14_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_addr (_ptw_io_requestor_14_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_mask (_ptw_io_requestor_14_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_l (_ptw_io_requestor_14_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_a (_ptw_io_requestor_14_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_x (_ptw_io_requestor_14_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_w (_ptw_io_requestor_14_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_r (_ptw_io_requestor_14_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_addr (_ptw_io_requestor_14_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_mask (_ptw_io_requestor_14_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_ren (_ptw_io_requestor_14_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_wen (_ptw_io_requestor_14_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_wdata (_ptw_io_requestor_14_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_value (_ptw_io_requestor_14_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_ren (_ptw_io_requestor_14_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_wen (_ptw_io_requestor_14_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_wdata (_ptw_io_requestor_14_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_value (_ptw_io_requestor_14_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_ren (_ptw_io_requestor_14_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_wen (_ptw_io_requestor_14_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_wdata (_ptw_io_requestor_14_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_value (_ptw_io_requestor_14_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_ren (_ptw_io_requestor_14_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_wen (_ptw_io_requestor_14_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_wdata (_ptw_io_requestor_14_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_value (_ptw_io_requestor_14_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_15_req_ready (_ptw_io_requestor_15_req_ready), // @[PTW.scala:802:19] .io_ptw_15_req_valid (_zstd_compressor_io_ptw_15_req_valid), .io_ptw_15_req_bits_bits_addr (_zstd_compressor_io_ptw_15_req_bits_bits_addr), .io_ptw_15_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_15_req_bits_bits_need_gpa), .io_ptw_15_resp_valid (_ptw_io_requestor_15_resp_valid), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_ae_ptw (_ptw_io_requestor_15_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_ae_final (_ptw_io_requestor_15_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pf (_ptw_io_requestor_15_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gf (_ptw_io_requestor_15_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hr (_ptw_io_requestor_15_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hw (_ptw_io_requestor_15_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hx (_ptw_io_requestor_15_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_reserved_for_future (_ptw_io_requestor_15_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_ppn (_ptw_io_requestor_15_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_reserved_for_software (_ptw_io_requestor_15_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_d (_ptw_io_requestor_15_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_a (_ptw_io_requestor_15_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_g (_ptw_io_requestor_15_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_u (_ptw_io_requestor_15_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_x (_ptw_io_requestor_15_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_w (_ptw_io_requestor_15_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_r (_ptw_io_requestor_15_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_v (_ptw_io_requestor_15_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_level (_ptw_io_requestor_15_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_homogeneous (_ptw_io_requestor_15_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_valid (_ptw_io_requestor_15_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_bits (_ptw_io_requestor_15_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_is_pte (_ptw_io_requestor_15_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_15_ptbr_mode (_ptw_io_requestor_15_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_15_ptbr_ppn (_ptw_io_requestor_15_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_15_status_debug (_ptw_io_requestor_15_status_debug), // @[PTW.scala:802:19] .io_ptw_15_status_cease (_ptw_io_requestor_15_status_cease), // @[PTW.scala:802:19] .io_ptw_15_status_wfi (_ptw_io_requestor_15_status_wfi), // @[PTW.scala:802:19] .io_ptw_15_status_isa (_ptw_io_requestor_15_status_isa), // @[PTW.scala:802:19] .io_ptw_15_status_dprv (_ptw_io_requestor_15_status_dprv), // @[PTW.scala:802:19] .io_ptw_15_status_dv (_ptw_io_requestor_15_status_dv), // @[PTW.scala:802:19] .io_ptw_15_status_prv (_ptw_io_requestor_15_status_prv), // @[PTW.scala:802:19] .io_ptw_15_status_v (_ptw_io_requestor_15_status_v), // @[PTW.scala:802:19] .io_ptw_15_status_mpv (_ptw_io_requestor_15_status_mpv), // @[PTW.scala:802:19] .io_ptw_15_status_gva (_ptw_io_requestor_15_status_gva), // @[PTW.scala:802:19] .io_ptw_15_status_tsr (_ptw_io_requestor_15_status_tsr), // @[PTW.scala:802:19] .io_ptw_15_status_tw (_ptw_io_requestor_15_status_tw), // @[PTW.scala:802:19] .io_ptw_15_status_tvm (_ptw_io_requestor_15_status_tvm), // @[PTW.scala:802:19] .io_ptw_15_status_mxr (_ptw_io_requestor_15_status_mxr), // @[PTW.scala:802:19] .io_ptw_15_status_sum (_ptw_io_requestor_15_status_sum), // @[PTW.scala:802:19] .io_ptw_15_status_mprv (_ptw_io_requestor_15_status_mprv), // @[PTW.scala:802:19] .io_ptw_15_status_fs (_ptw_io_requestor_15_status_fs), // @[PTW.scala:802:19] .io_ptw_15_status_mpp (_ptw_io_requestor_15_status_mpp), // @[PTW.scala:802:19] .io_ptw_15_status_spp (_ptw_io_requestor_15_status_spp), // @[PTW.scala:802:19] .io_ptw_15_status_mpie (_ptw_io_requestor_15_status_mpie), // @[PTW.scala:802:19] .io_ptw_15_status_spie (_ptw_io_requestor_15_status_spie), // @[PTW.scala:802:19] .io_ptw_15_status_mie (_ptw_io_requestor_15_status_mie), // @[PTW.scala:802:19] .io_ptw_15_status_sie (_ptw_io_requestor_15_status_sie), // @[PTW.scala:802:19] .io_ptw_15_hstatus_spvp (_ptw_io_requestor_15_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_15_hstatus_spv (_ptw_io_requestor_15_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_15_hstatus_gva (_ptw_io_requestor_15_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_15_gstatus_debug (_ptw_io_requestor_15_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_15_gstatus_cease (_ptw_io_requestor_15_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_15_gstatus_wfi (_ptw_io_requestor_15_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_15_gstatus_isa (_ptw_io_requestor_15_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_15_gstatus_dprv (_ptw_io_requestor_15_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_dv (_ptw_io_requestor_15_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_prv (_ptw_io_requestor_15_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_v (_ptw_io_requestor_15_gstatus_v), // @[PTW.scala:802:19] .io_ptw_15_gstatus_zero2 (_ptw_io_requestor_15_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpv (_ptw_io_requestor_15_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_gva (_ptw_io_requestor_15_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mbe (_ptw_io_requestor_15_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sbe (_ptw_io_requestor_15_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sxl (_ptw_io_requestor_15_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_15_gstatus_zero1 (_ptw_io_requestor_15_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tsr (_ptw_io_requestor_15_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tw (_ptw_io_requestor_15_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tvm (_ptw_io_requestor_15_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mxr (_ptw_io_requestor_15_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sum (_ptw_io_requestor_15_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mprv (_ptw_io_requestor_15_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_fs (_ptw_io_requestor_15_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpp (_ptw_io_requestor_15_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_15_gstatus_vs (_ptw_io_requestor_15_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_15_gstatus_spp (_ptw_io_requestor_15_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpie (_ptw_io_requestor_15_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_ube (_ptw_io_requestor_15_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_15_gstatus_spie (_ptw_io_requestor_15_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_upie (_ptw_io_requestor_15_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mie (_ptw_io_requestor_15_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_hie (_ptw_io_requestor_15_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sie (_ptw_io_requestor_15_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_uie (_ptw_io_requestor_15_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_l (_ptw_io_requestor_15_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_a (_ptw_io_requestor_15_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_x (_ptw_io_requestor_15_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_w (_ptw_io_requestor_15_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_r (_ptw_io_requestor_15_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_addr (_ptw_io_requestor_15_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_mask (_ptw_io_requestor_15_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_l (_ptw_io_requestor_15_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_a (_ptw_io_requestor_15_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_x (_ptw_io_requestor_15_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_w (_ptw_io_requestor_15_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_r (_ptw_io_requestor_15_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_addr (_ptw_io_requestor_15_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_mask (_ptw_io_requestor_15_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_l (_ptw_io_requestor_15_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_a (_ptw_io_requestor_15_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_x (_ptw_io_requestor_15_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_w (_ptw_io_requestor_15_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_r (_ptw_io_requestor_15_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_addr (_ptw_io_requestor_15_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_mask (_ptw_io_requestor_15_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_l (_ptw_io_requestor_15_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_a (_ptw_io_requestor_15_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_x (_ptw_io_requestor_15_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_w (_ptw_io_requestor_15_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_r (_ptw_io_requestor_15_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_addr (_ptw_io_requestor_15_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_mask (_ptw_io_requestor_15_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_l (_ptw_io_requestor_15_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_a (_ptw_io_requestor_15_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_x (_ptw_io_requestor_15_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_w (_ptw_io_requestor_15_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_r (_ptw_io_requestor_15_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_addr (_ptw_io_requestor_15_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_mask (_ptw_io_requestor_15_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_l (_ptw_io_requestor_15_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_a (_ptw_io_requestor_15_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_x (_ptw_io_requestor_15_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_w (_ptw_io_requestor_15_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_r (_ptw_io_requestor_15_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_addr (_ptw_io_requestor_15_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_mask (_ptw_io_requestor_15_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_l (_ptw_io_requestor_15_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_a (_ptw_io_requestor_15_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_x (_ptw_io_requestor_15_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_w (_ptw_io_requestor_15_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_r (_ptw_io_requestor_15_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_addr (_ptw_io_requestor_15_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_mask (_ptw_io_requestor_15_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_l (_ptw_io_requestor_15_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_a (_ptw_io_requestor_15_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_x (_ptw_io_requestor_15_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_w (_ptw_io_requestor_15_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_r (_ptw_io_requestor_15_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_addr (_ptw_io_requestor_15_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_mask (_ptw_io_requestor_15_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_ren (_ptw_io_requestor_15_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_wen (_ptw_io_requestor_15_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_wdata (_ptw_io_requestor_15_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_value (_ptw_io_requestor_15_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_ren (_ptw_io_requestor_15_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_wen (_ptw_io_requestor_15_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_wdata (_ptw_io_requestor_15_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_value (_ptw_io_requestor_15_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_ren (_ptw_io_requestor_15_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_wen (_ptw_io_requestor_15_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_wdata (_ptw_io_requestor_15_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_value (_ptw_io_requestor_15_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_ren (_ptw_io_requestor_15_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_wen (_ptw_io_requestor_15_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_wdata (_ptw_io_requestor_15_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_value (_ptw_io_requestor_15_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_16_req_ready (_ptw_io_requestor_16_req_ready), // @[PTW.scala:802:19] .io_ptw_16_req_valid (_zstd_compressor_io_ptw_16_req_valid), .io_ptw_16_req_bits_bits_addr (_zstd_compressor_io_ptw_16_req_bits_bits_addr), .io_ptw_16_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_16_req_bits_bits_need_gpa), .io_ptw_16_resp_valid (_ptw_io_requestor_16_resp_valid), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_ae_ptw (_ptw_io_requestor_16_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_ae_final (_ptw_io_requestor_16_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pf (_ptw_io_requestor_16_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gf (_ptw_io_requestor_16_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hr (_ptw_io_requestor_16_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hw (_ptw_io_requestor_16_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hx (_ptw_io_requestor_16_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_reserved_for_future (_ptw_io_requestor_16_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_ppn (_ptw_io_requestor_16_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_reserved_for_software (_ptw_io_requestor_16_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_d (_ptw_io_requestor_16_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_a (_ptw_io_requestor_16_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_g (_ptw_io_requestor_16_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_u (_ptw_io_requestor_16_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_x (_ptw_io_requestor_16_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_w (_ptw_io_requestor_16_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_r (_ptw_io_requestor_16_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_v (_ptw_io_requestor_16_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_level (_ptw_io_requestor_16_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_homogeneous (_ptw_io_requestor_16_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_valid (_ptw_io_requestor_16_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_bits (_ptw_io_requestor_16_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_is_pte (_ptw_io_requestor_16_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_16_ptbr_mode (_ptw_io_requestor_16_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_16_ptbr_ppn (_ptw_io_requestor_16_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_16_status_debug (_ptw_io_requestor_16_status_debug), // @[PTW.scala:802:19] .io_ptw_16_status_cease (_ptw_io_requestor_16_status_cease), // @[PTW.scala:802:19] .io_ptw_16_status_wfi (_ptw_io_requestor_16_status_wfi), // @[PTW.scala:802:19] .io_ptw_16_status_isa (_ptw_io_requestor_16_status_isa), // @[PTW.scala:802:19] .io_ptw_16_status_dprv (_ptw_io_requestor_16_status_dprv), // @[PTW.scala:802:19] .io_ptw_16_status_dv (_ptw_io_requestor_16_status_dv), // @[PTW.scala:802:19] .io_ptw_16_status_prv (_ptw_io_requestor_16_status_prv), // @[PTW.scala:802:19] .io_ptw_16_status_v (_ptw_io_requestor_16_status_v), // @[PTW.scala:802:19] .io_ptw_16_status_mpv (_ptw_io_requestor_16_status_mpv), // @[PTW.scala:802:19] .io_ptw_16_status_gva (_ptw_io_requestor_16_status_gva), // @[PTW.scala:802:19] .io_ptw_16_status_tsr (_ptw_io_requestor_16_status_tsr), // @[PTW.scala:802:19] .io_ptw_16_status_tw (_ptw_io_requestor_16_status_tw), // @[PTW.scala:802:19] .io_ptw_16_status_tvm (_ptw_io_requestor_16_status_tvm), // @[PTW.scala:802:19] .io_ptw_16_status_mxr (_ptw_io_requestor_16_status_mxr), // @[PTW.scala:802:19] .io_ptw_16_status_sum (_ptw_io_requestor_16_status_sum), // @[PTW.scala:802:19] .io_ptw_16_status_mprv (_ptw_io_requestor_16_status_mprv), // @[PTW.scala:802:19] .io_ptw_16_status_fs (_ptw_io_requestor_16_status_fs), // @[PTW.scala:802:19] .io_ptw_16_status_mpp (_ptw_io_requestor_16_status_mpp), // @[PTW.scala:802:19] .io_ptw_16_status_spp (_ptw_io_requestor_16_status_spp), // @[PTW.scala:802:19] .io_ptw_16_status_mpie (_ptw_io_requestor_16_status_mpie), // @[PTW.scala:802:19] .io_ptw_16_status_spie (_ptw_io_requestor_16_status_spie), // @[PTW.scala:802:19] .io_ptw_16_status_mie (_ptw_io_requestor_16_status_mie), // @[PTW.scala:802:19] .io_ptw_16_status_sie (_ptw_io_requestor_16_status_sie), // @[PTW.scala:802:19] .io_ptw_16_hstatus_spvp (_ptw_io_requestor_16_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_16_hstatus_spv (_ptw_io_requestor_16_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_16_hstatus_gva (_ptw_io_requestor_16_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_16_gstatus_debug (_ptw_io_requestor_16_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_16_gstatus_cease (_ptw_io_requestor_16_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_16_gstatus_wfi (_ptw_io_requestor_16_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_16_gstatus_isa (_ptw_io_requestor_16_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_16_gstatus_dprv (_ptw_io_requestor_16_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_dv (_ptw_io_requestor_16_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_prv (_ptw_io_requestor_16_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_v (_ptw_io_requestor_16_gstatus_v), // @[PTW.scala:802:19] .io_ptw_16_gstatus_zero2 (_ptw_io_requestor_16_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpv (_ptw_io_requestor_16_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_gva (_ptw_io_requestor_16_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mbe (_ptw_io_requestor_16_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sbe (_ptw_io_requestor_16_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sxl (_ptw_io_requestor_16_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_16_gstatus_zero1 (_ptw_io_requestor_16_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tsr (_ptw_io_requestor_16_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tw (_ptw_io_requestor_16_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tvm (_ptw_io_requestor_16_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mxr (_ptw_io_requestor_16_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sum (_ptw_io_requestor_16_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mprv (_ptw_io_requestor_16_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_fs (_ptw_io_requestor_16_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpp (_ptw_io_requestor_16_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_16_gstatus_vs (_ptw_io_requestor_16_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_16_gstatus_spp (_ptw_io_requestor_16_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpie (_ptw_io_requestor_16_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_ube (_ptw_io_requestor_16_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_16_gstatus_spie (_ptw_io_requestor_16_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_upie (_ptw_io_requestor_16_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mie (_ptw_io_requestor_16_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_hie (_ptw_io_requestor_16_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sie (_ptw_io_requestor_16_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_uie (_ptw_io_requestor_16_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_l (_ptw_io_requestor_16_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_a (_ptw_io_requestor_16_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_x (_ptw_io_requestor_16_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_w (_ptw_io_requestor_16_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_r (_ptw_io_requestor_16_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_addr (_ptw_io_requestor_16_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_mask (_ptw_io_requestor_16_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_l (_ptw_io_requestor_16_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_a (_ptw_io_requestor_16_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_x (_ptw_io_requestor_16_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_w (_ptw_io_requestor_16_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_r (_ptw_io_requestor_16_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_addr (_ptw_io_requestor_16_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_mask (_ptw_io_requestor_16_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_l (_ptw_io_requestor_16_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_a (_ptw_io_requestor_16_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_x (_ptw_io_requestor_16_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_w (_ptw_io_requestor_16_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_r (_ptw_io_requestor_16_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_addr (_ptw_io_requestor_16_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_mask (_ptw_io_requestor_16_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_l (_ptw_io_requestor_16_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_a (_ptw_io_requestor_16_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_x (_ptw_io_requestor_16_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_w (_ptw_io_requestor_16_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_r (_ptw_io_requestor_16_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_addr (_ptw_io_requestor_16_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_mask (_ptw_io_requestor_16_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_l (_ptw_io_requestor_16_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_a (_ptw_io_requestor_16_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_x (_ptw_io_requestor_16_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_w (_ptw_io_requestor_16_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_r (_ptw_io_requestor_16_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_addr (_ptw_io_requestor_16_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_mask (_ptw_io_requestor_16_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_l (_ptw_io_requestor_16_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_a (_ptw_io_requestor_16_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_x (_ptw_io_requestor_16_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_w (_ptw_io_requestor_16_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_r (_ptw_io_requestor_16_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_addr (_ptw_io_requestor_16_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_mask (_ptw_io_requestor_16_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_l (_ptw_io_requestor_16_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_a (_ptw_io_requestor_16_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_x (_ptw_io_requestor_16_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_w (_ptw_io_requestor_16_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_r (_ptw_io_requestor_16_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_addr (_ptw_io_requestor_16_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_mask (_ptw_io_requestor_16_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_l (_ptw_io_requestor_16_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_a (_ptw_io_requestor_16_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_x (_ptw_io_requestor_16_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_w (_ptw_io_requestor_16_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_r (_ptw_io_requestor_16_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_addr (_ptw_io_requestor_16_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_mask (_ptw_io_requestor_16_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_ren (_ptw_io_requestor_16_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_wen (_ptw_io_requestor_16_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_wdata (_ptw_io_requestor_16_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_value (_ptw_io_requestor_16_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_ren (_ptw_io_requestor_16_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_wen (_ptw_io_requestor_16_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_wdata (_ptw_io_requestor_16_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_value (_ptw_io_requestor_16_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_ren (_ptw_io_requestor_16_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_wen (_ptw_io_requestor_16_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_wdata (_ptw_io_requestor_16_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_value (_ptw_io_requestor_16_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_ren (_ptw_io_requestor_16_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_wen (_ptw_io_requestor_16_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_wdata (_ptw_io_requestor_16_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_value (_ptw_io_requestor_16_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_17_req_ready (_ptw_io_requestor_17_req_ready), // @[PTW.scala:802:19] .io_ptw_17_req_valid (_zstd_compressor_io_ptw_17_req_valid), .io_ptw_17_req_bits_bits_addr (_zstd_compressor_io_ptw_17_req_bits_bits_addr), .io_ptw_17_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_17_req_bits_bits_need_gpa), .io_ptw_17_resp_valid (_ptw_io_requestor_17_resp_valid), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_ae_ptw (_ptw_io_requestor_17_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_ae_final (_ptw_io_requestor_17_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pf (_ptw_io_requestor_17_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gf (_ptw_io_requestor_17_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hr (_ptw_io_requestor_17_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hw (_ptw_io_requestor_17_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hx (_ptw_io_requestor_17_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_reserved_for_future (_ptw_io_requestor_17_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_ppn (_ptw_io_requestor_17_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_reserved_for_software (_ptw_io_requestor_17_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_d (_ptw_io_requestor_17_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_a (_ptw_io_requestor_17_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_g (_ptw_io_requestor_17_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_u (_ptw_io_requestor_17_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_x (_ptw_io_requestor_17_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_w (_ptw_io_requestor_17_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_r (_ptw_io_requestor_17_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_v (_ptw_io_requestor_17_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_level (_ptw_io_requestor_17_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_homogeneous (_ptw_io_requestor_17_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_valid (_ptw_io_requestor_17_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_bits (_ptw_io_requestor_17_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_is_pte (_ptw_io_requestor_17_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_17_ptbr_mode (_ptw_io_requestor_17_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_17_ptbr_ppn (_ptw_io_requestor_17_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_17_status_debug (_ptw_io_requestor_17_status_debug), // @[PTW.scala:802:19] .io_ptw_17_status_cease (_ptw_io_requestor_17_status_cease), // @[PTW.scala:802:19] .io_ptw_17_status_wfi (_ptw_io_requestor_17_status_wfi), // @[PTW.scala:802:19] .io_ptw_17_status_isa (_ptw_io_requestor_17_status_isa), // @[PTW.scala:802:19] .io_ptw_17_status_dprv (_ptw_io_requestor_17_status_dprv), // @[PTW.scala:802:19] .io_ptw_17_status_dv (_ptw_io_requestor_17_status_dv), // @[PTW.scala:802:19] .io_ptw_17_status_prv (_ptw_io_requestor_17_status_prv), // @[PTW.scala:802:19] .io_ptw_17_status_v (_ptw_io_requestor_17_status_v), // @[PTW.scala:802:19] .io_ptw_17_status_mpv (_ptw_io_requestor_17_status_mpv), // @[PTW.scala:802:19] .io_ptw_17_status_gva (_ptw_io_requestor_17_status_gva), // @[PTW.scala:802:19] .io_ptw_17_status_tsr (_ptw_io_requestor_17_status_tsr), // @[PTW.scala:802:19] .io_ptw_17_status_tw (_ptw_io_requestor_17_status_tw), // @[PTW.scala:802:19] .io_ptw_17_status_tvm (_ptw_io_requestor_17_status_tvm), // @[PTW.scala:802:19] .io_ptw_17_status_mxr (_ptw_io_requestor_17_status_mxr), // @[PTW.scala:802:19] .io_ptw_17_status_sum (_ptw_io_requestor_17_status_sum), // @[PTW.scala:802:19] .io_ptw_17_status_mprv (_ptw_io_requestor_17_status_mprv), // @[PTW.scala:802:19] .io_ptw_17_status_fs (_ptw_io_requestor_17_status_fs), // @[PTW.scala:802:19] .io_ptw_17_status_mpp (_ptw_io_requestor_17_status_mpp), // @[PTW.scala:802:19] .io_ptw_17_status_spp (_ptw_io_requestor_17_status_spp), // @[PTW.scala:802:19] .io_ptw_17_status_mpie (_ptw_io_requestor_17_status_mpie), // @[PTW.scala:802:19] .io_ptw_17_status_spie (_ptw_io_requestor_17_status_spie), // @[PTW.scala:802:19] .io_ptw_17_status_mie (_ptw_io_requestor_17_status_mie), // @[PTW.scala:802:19] .io_ptw_17_status_sie (_ptw_io_requestor_17_status_sie), // @[PTW.scala:802:19] .io_ptw_17_hstatus_spvp (_ptw_io_requestor_17_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_17_hstatus_spv (_ptw_io_requestor_17_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_17_hstatus_gva (_ptw_io_requestor_17_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_17_gstatus_debug (_ptw_io_requestor_17_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_17_gstatus_cease (_ptw_io_requestor_17_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_17_gstatus_wfi (_ptw_io_requestor_17_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_17_gstatus_isa (_ptw_io_requestor_17_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_17_gstatus_dprv (_ptw_io_requestor_17_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_dv (_ptw_io_requestor_17_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_prv (_ptw_io_requestor_17_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_v (_ptw_io_requestor_17_gstatus_v), // @[PTW.scala:802:19] .io_ptw_17_gstatus_zero2 (_ptw_io_requestor_17_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpv (_ptw_io_requestor_17_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_gva (_ptw_io_requestor_17_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mbe (_ptw_io_requestor_17_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sbe (_ptw_io_requestor_17_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sxl (_ptw_io_requestor_17_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_17_gstatus_zero1 (_ptw_io_requestor_17_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tsr (_ptw_io_requestor_17_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tw (_ptw_io_requestor_17_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tvm (_ptw_io_requestor_17_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mxr (_ptw_io_requestor_17_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sum (_ptw_io_requestor_17_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mprv (_ptw_io_requestor_17_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_fs (_ptw_io_requestor_17_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpp (_ptw_io_requestor_17_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_17_gstatus_vs (_ptw_io_requestor_17_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_17_gstatus_spp (_ptw_io_requestor_17_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpie (_ptw_io_requestor_17_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_ube (_ptw_io_requestor_17_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_17_gstatus_spie (_ptw_io_requestor_17_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_upie (_ptw_io_requestor_17_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mie (_ptw_io_requestor_17_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_hie (_ptw_io_requestor_17_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sie (_ptw_io_requestor_17_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_uie (_ptw_io_requestor_17_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_l (_ptw_io_requestor_17_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_a (_ptw_io_requestor_17_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_x (_ptw_io_requestor_17_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_w (_ptw_io_requestor_17_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_r (_ptw_io_requestor_17_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_addr (_ptw_io_requestor_17_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_mask (_ptw_io_requestor_17_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_l (_ptw_io_requestor_17_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_a (_ptw_io_requestor_17_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_x (_ptw_io_requestor_17_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_w (_ptw_io_requestor_17_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_r (_ptw_io_requestor_17_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_addr (_ptw_io_requestor_17_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_mask (_ptw_io_requestor_17_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_l (_ptw_io_requestor_17_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_a (_ptw_io_requestor_17_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_x (_ptw_io_requestor_17_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_w (_ptw_io_requestor_17_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_r (_ptw_io_requestor_17_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_addr (_ptw_io_requestor_17_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_mask (_ptw_io_requestor_17_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_l (_ptw_io_requestor_17_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_a (_ptw_io_requestor_17_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_x (_ptw_io_requestor_17_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_w (_ptw_io_requestor_17_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_r (_ptw_io_requestor_17_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_addr (_ptw_io_requestor_17_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_mask (_ptw_io_requestor_17_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_l (_ptw_io_requestor_17_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_a (_ptw_io_requestor_17_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_x (_ptw_io_requestor_17_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_w (_ptw_io_requestor_17_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_r (_ptw_io_requestor_17_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_addr (_ptw_io_requestor_17_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_mask (_ptw_io_requestor_17_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_l (_ptw_io_requestor_17_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_a (_ptw_io_requestor_17_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_x (_ptw_io_requestor_17_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_w (_ptw_io_requestor_17_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_r (_ptw_io_requestor_17_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_addr (_ptw_io_requestor_17_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_mask (_ptw_io_requestor_17_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_l (_ptw_io_requestor_17_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_a (_ptw_io_requestor_17_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_x (_ptw_io_requestor_17_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_w (_ptw_io_requestor_17_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_r (_ptw_io_requestor_17_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_addr (_ptw_io_requestor_17_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_mask (_ptw_io_requestor_17_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_l (_ptw_io_requestor_17_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_a (_ptw_io_requestor_17_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_x (_ptw_io_requestor_17_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_w (_ptw_io_requestor_17_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_r (_ptw_io_requestor_17_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_addr (_ptw_io_requestor_17_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_mask (_ptw_io_requestor_17_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_ren (_ptw_io_requestor_17_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_wen (_ptw_io_requestor_17_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_wdata (_ptw_io_requestor_17_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_value (_ptw_io_requestor_17_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_ren (_ptw_io_requestor_17_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_wen (_ptw_io_requestor_17_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_wdata (_ptw_io_requestor_17_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_value (_ptw_io_requestor_17_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_ren (_ptw_io_requestor_17_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_wen (_ptw_io_requestor_17_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_wdata (_ptw_io_requestor_17_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_value (_ptw_io_requestor_17_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_ren (_ptw_io_requestor_17_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_wen (_ptw_io_requestor_17_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_wdata (_ptw_io_requestor_17_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_value (_ptw_io_requestor_17_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Configs.scala:62:39] Frontend frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_19_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_19_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_19_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_19_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_19_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_19_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_19_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_19_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_19_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_19_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_19_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_19_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_19_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_19_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_19_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_19_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_19_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_19_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_19_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_19_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_19_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_19_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_19_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_19_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_19_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_19_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_19_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_19_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_19_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_19_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_19_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_19_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_19_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_19_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_19_status_v), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_19_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_19_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_19_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_19_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_19_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_19_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_19_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_19_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_19_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_19_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_19_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_19_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_19_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_19_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_19_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_19_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_19_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_19_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_19_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_19_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_19_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_19_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_19_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_19_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_19_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_19_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_19_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_19_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_19_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_19_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_19_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_19_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_19_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_19_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_19_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_19_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_19_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_19_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_19_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_19_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_19_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_19_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_19_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_19_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_19_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_19_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_19_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_19_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_19_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_19_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_19_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_19_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_19_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_19_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_19_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_19_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_19_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_19_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_19_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_19_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_19_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_19_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_19_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_19_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_19_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_19_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_19_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_19_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_19_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_19_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_19_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_19_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_19_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_19_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_19_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_19_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_19_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_19_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_19_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_19_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_19_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_19_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_19_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_19_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_19_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_19_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_19_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_19_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_19_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_19_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_19_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_19_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_19_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_19_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_19_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_19_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_19_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_19_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_19_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_19_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_19_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_19_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_19_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_19_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_19_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_19_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_19_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_19_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_19_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_19_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_19_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_19_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_19_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_19_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_19_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_19_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_19_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_19_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_19_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_19_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_19_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_19_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_19_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[LazyRoCC.scala:106:24] .io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[LazyRoCC.scala:106:24] .io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[LazyRoCC.scala:106:24] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_2_req_ready (_dcacheArb_io_requestor_2_req_ready), .io_requestor_2_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_2_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_2_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_2_s2_nack (_dcacheArb_io_requestor_2_s2_nack), .io_requestor_2_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw), .io_requestor_2_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached), .io_requestor_2_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr), .io_requestor_2_resp_valid (_dcacheArb_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr), .io_requestor_2_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag), .io_requestor_2_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd), .io_requestor_2_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size), .io_requestor_2_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed), .io_requestor_2_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv), .io_requestor_2_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv), .io_requestor_2_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data), .io_requestor_2_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask), .io_requestor_2_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay), .io_requestor_2_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data), .io_requestor_2_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass), .io_requestor_2_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw), .io_requestor_2_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data), .io_requestor_2_replay_next (_dcacheArb_io_requestor_2_replay_next), .io_requestor_2_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld), .io_requestor_2_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st), .io_requestor_2_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld), .io_requestor_2_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st), .io_requestor_2_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld), .io_requestor_2_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st), .io_requestor_2_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa), .io_requestor_2_ordered (_dcacheArb_io_requestor_2_ordered), .io_requestor_2_store_pending (_dcacheArb_io_requestor_2_store_pending), .io_requestor_2_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire), .io_requestor_2_perf_release (_dcacheArb_io_requestor_2_perf_release), .io_requestor_2_perf_grant (_dcacheArb_io_requestor_2_perf_grant), .io_requestor_2_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss), .io_requestor_2_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked), .io_requestor_2_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad), .io_requestor_2_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW), .io_requestor_2_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad), .io_requestor_2_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad), .io_requestor_2_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore), .io_requestor_2_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_zstd_compressor_io_ptw_0_req_valid), // @[Configs.scala:62:39] .io_requestor_0_req_bits_bits_addr (_zstd_compressor_io_ptw_0_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_0_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_0_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_zstd_compressor_io_ptw_1_req_valid), // @[Configs.scala:62:39] .io_requestor_1_req_bits_bits_addr (_zstd_compressor_io_ptw_1_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_1_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_1_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready), .io_requestor_2_req_valid (_zstd_compressor_io_ptw_2_req_valid), // @[Configs.scala:62:39] .io_requestor_2_req_bits_bits_addr (_zstd_compressor_io_ptw_2_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_2_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_2_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), .io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), .io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), .io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), .io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), .io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), .io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), .io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), .io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), .io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), .io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), .io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), .io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), .io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), .io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), .io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), .io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), .io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), .io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), .io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), .io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), .io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), .io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), .io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), .io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), .io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug), .io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease), .io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi), .io_requestor_2_status_isa (_ptw_io_requestor_2_status_isa), .io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv), .io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv), .io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv), .io_requestor_2_status_v (_ptw_io_requestor_2_status_v), .io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv), .io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva), .io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr), .io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw), .io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm), .io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr), .io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum), .io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv), .io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs), .io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp), .io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp), .io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie), .io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie), .io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie), .io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie), .io_requestor_2_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp), .io_requestor_2_hstatus_spv (_ptw_io_requestor_2_hstatus_spv), .io_requestor_2_hstatus_gva (_ptw_io_requestor_2_hstatus_gva), .io_requestor_2_gstatus_debug (_ptw_io_requestor_2_gstatus_debug), .io_requestor_2_gstatus_cease (_ptw_io_requestor_2_gstatus_cease), .io_requestor_2_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi), .io_requestor_2_gstatus_isa (_ptw_io_requestor_2_gstatus_isa), .io_requestor_2_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv), .io_requestor_2_gstatus_dv (_ptw_io_requestor_2_gstatus_dv), .io_requestor_2_gstatus_prv (_ptw_io_requestor_2_gstatus_prv), .io_requestor_2_gstatus_v (_ptw_io_requestor_2_gstatus_v), .io_requestor_2_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2), .io_requestor_2_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv), .io_requestor_2_gstatus_gva (_ptw_io_requestor_2_gstatus_gva), .io_requestor_2_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe), .io_requestor_2_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe), .io_requestor_2_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl), .io_requestor_2_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1), .io_requestor_2_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr), .io_requestor_2_gstatus_tw (_ptw_io_requestor_2_gstatus_tw), .io_requestor_2_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm), .io_requestor_2_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr), .io_requestor_2_gstatus_sum (_ptw_io_requestor_2_gstatus_sum), .io_requestor_2_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv), .io_requestor_2_gstatus_fs (_ptw_io_requestor_2_gstatus_fs), .io_requestor_2_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp), .io_requestor_2_gstatus_vs (_ptw_io_requestor_2_gstatus_vs), .io_requestor_2_gstatus_spp (_ptw_io_requestor_2_gstatus_spp), .io_requestor_2_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie), .io_requestor_2_gstatus_ube (_ptw_io_requestor_2_gstatus_ube), .io_requestor_2_gstatus_spie (_ptw_io_requestor_2_gstatus_spie), .io_requestor_2_gstatus_upie (_ptw_io_requestor_2_gstatus_upie), .io_requestor_2_gstatus_mie (_ptw_io_requestor_2_gstatus_mie), .io_requestor_2_gstatus_hie (_ptw_io_requestor_2_gstatus_hie), .io_requestor_2_gstatus_sie (_ptw_io_requestor_2_gstatus_sie), .io_requestor_2_gstatus_uie (_ptw_io_requestor_2_gstatus_uie), .io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), .io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), .io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), .io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), .io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), .io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), .io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), .io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), .io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), .io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), .io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), .io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), .io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), .io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), .io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), .io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), .io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), .io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), .io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), .io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), .io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), .io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), .io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), .io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), .io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), .io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), .io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), .io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), .io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), .io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), .io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), .io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), .io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), .io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), .io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), .io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), .io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), .io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), .io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), .io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), .io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), .io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), .io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), .io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), .io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), .io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), .io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), .io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), .io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), .io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), .io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), .io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), .io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), .io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), .io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), .io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), .io_requestor_2_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren), .io_requestor_2_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen), .io_requestor_2_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata), .io_requestor_2_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value), .io_requestor_2_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren), .io_requestor_2_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen), .io_requestor_2_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata), .io_requestor_2_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value), .io_requestor_2_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren), .io_requestor_2_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen), .io_requestor_2_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata), .io_requestor_2_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value), .io_requestor_2_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren), .io_requestor_2_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen), .io_requestor_2_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata), .io_requestor_2_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value), .io_requestor_3_req_ready (_ptw_io_requestor_3_req_ready), .io_requestor_3_req_valid (_zstd_compressor_io_ptw_3_req_valid), // @[Configs.scala:62:39] .io_requestor_3_req_bits_bits_addr (_zstd_compressor_io_ptw_3_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_3_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_3_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_3_resp_valid (_ptw_io_requestor_3_resp_valid), .io_requestor_3_resp_bits_ae_ptw (_ptw_io_requestor_3_resp_bits_ae_ptw), .io_requestor_3_resp_bits_ae_final (_ptw_io_requestor_3_resp_bits_ae_final), .io_requestor_3_resp_bits_pf (_ptw_io_requestor_3_resp_bits_pf), .io_requestor_3_resp_bits_gf (_ptw_io_requestor_3_resp_bits_gf), .io_requestor_3_resp_bits_hr (_ptw_io_requestor_3_resp_bits_hr), .io_requestor_3_resp_bits_hw (_ptw_io_requestor_3_resp_bits_hw), .io_requestor_3_resp_bits_hx (_ptw_io_requestor_3_resp_bits_hx), .io_requestor_3_resp_bits_pte_reserved_for_future (_ptw_io_requestor_3_resp_bits_pte_reserved_for_future), .io_requestor_3_resp_bits_pte_ppn (_ptw_io_requestor_3_resp_bits_pte_ppn), .io_requestor_3_resp_bits_pte_reserved_for_software (_ptw_io_requestor_3_resp_bits_pte_reserved_for_software), .io_requestor_3_resp_bits_pte_d (_ptw_io_requestor_3_resp_bits_pte_d), .io_requestor_3_resp_bits_pte_a (_ptw_io_requestor_3_resp_bits_pte_a), .io_requestor_3_resp_bits_pte_g (_ptw_io_requestor_3_resp_bits_pte_g), .io_requestor_3_resp_bits_pte_u (_ptw_io_requestor_3_resp_bits_pte_u), .io_requestor_3_resp_bits_pte_x (_ptw_io_requestor_3_resp_bits_pte_x), .io_requestor_3_resp_bits_pte_w (_ptw_io_requestor_3_resp_bits_pte_w), .io_requestor_3_resp_bits_pte_r (_ptw_io_requestor_3_resp_bits_pte_r), .io_requestor_3_resp_bits_pte_v (_ptw_io_requestor_3_resp_bits_pte_v), .io_requestor_3_resp_bits_level (_ptw_io_requestor_3_resp_bits_level), .io_requestor_3_resp_bits_homogeneous (_ptw_io_requestor_3_resp_bits_homogeneous), .io_requestor_3_resp_bits_gpa_valid (_ptw_io_requestor_3_resp_bits_gpa_valid), .io_requestor_3_resp_bits_gpa_bits (_ptw_io_requestor_3_resp_bits_gpa_bits), .io_requestor_3_resp_bits_gpa_is_pte (_ptw_io_requestor_3_resp_bits_gpa_is_pte), .io_requestor_3_ptbr_mode (_ptw_io_requestor_3_ptbr_mode), .io_requestor_3_ptbr_ppn (_ptw_io_requestor_3_ptbr_ppn), .io_requestor_3_status_debug (_ptw_io_requestor_3_status_debug), .io_requestor_3_status_cease (_ptw_io_requestor_3_status_cease), .io_requestor_3_status_wfi (_ptw_io_requestor_3_status_wfi), .io_requestor_3_status_isa (_ptw_io_requestor_3_status_isa), .io_requestor_3_status_dprv (_ptw_io_requestor_3_status_dprv), .io_requestor_3_status_dv (_ptw_io_requestor_3_status_dv), .io_requestor_3_status_prv (_ptw_io_requestor_3_status_prv), .io_requestor_3_status_v (_ptw_io_requestor_3_status_v), .io_requestor_3_status_mpv (_ptw_io_requestor_3_status_mpv), .io_requestor_3_status_gva (_ptw_io_requestor_3_status_gva), .io_requestor_3_status_tsr (_ptw_io_requestor_3_status_tsr), .io_requestor_3_status_tw (_ptw_io_requestor_3_status_tw), .io_requestor_3_status_tvm (_ptw_io_requestor_3_status_tvm), .io_requestor_3_status_mxr (_ptw_io_requestor_3_status_mxr), .io_requestor_3_status_sum (_ptw_io_requestor_3_status_sum), .io_requestor_3_status_mprv (_ptw_io_requestor_3_status_mprv), .io_requestor_3_status_fs (_ptw_io_requestor_3_status_fs), .io_requestor_3_status_mpp (_ptw_io_requestor_3_status_mpp), .io_requestor_3_status_spp (_ptw_io_requestor_3_status_spp), .io_requestor_3_status_mpie (_ptw_io_requestor_3_status_mpie), .io_requestor_3_status_spie (_ptw_io_requestor_3_status_spie), .io_requestor_3_status_mie (_ptw_io_requestor_3_status_mie), .io_requestor_3_status_sie (_ptw_io_requestor_3_status_sie), .io_requestor_3_hstatus_spvp (_ptw_io_requestor_3_hstatus_spvp), .io_requestor_3_hstatus_spv (_ptw_io_requestor_3_hstatus_spv), .io_requestor_3_hstatus_gva (_ptw_io_requestor_3_hstatus_gva), .io_requestor_3_gstatus_debug (_ptw_io_requestor_3_gstatus_debug), .io_requestor_3_gstatus_cease (_ptw_io_requestor_3_gstatus_cease), .io_requestor_3_gstatus_wfi (_ptw_io_requestor_3_gstatus_wfi), .io_requestor_3_gstatus_isa (_ptw_io_requestor_3_gstatus_isa), .io_requestor_3_gstatus_dprv (_ptw_io_requestor_3_gstatus_dprv), .io_requestor_3_gstatus_dv (_ptw_io_requestor_3_gstatus_dv), .io_requestor_3_gstatus_prv (_ptw_io_requestor_3_gstatus_prv), .io_requestor_3_gstatus_v (_ptw_io_requestor_3_gstatus_v), .io_requestor_3_gstatus_zero2 (_ptw_io_requestor_3_gstatus_zero2), .io_requestor_3_gstatus_mpv (_ptw_io_requestor_3_gstatus_mpv), .io_requestor_3_gstatus_gva (_ptw_io_requestor_3_gstatus_gva), .io_requestor_3_gstatus_mbe (_ptw_io_requestor_3_gstatus_mbe), .io_requestor_3_gstatus_sbe (_ptw_io_requestor_3_gstatus_sbe), .io_requestor_3_gstatus_sxl (_ptw_io_requestor_3_gstatus_sxl), .io_requestor_3_gstatus_zero1 (_ptw_io_requestor_3_gstatus_zero1), .io_requestor_3_gstatus_tsr (_ptw_io_requestor_3_gstatus_tsr), .io_requestor_3_gstatus_tw (_ptw_io_requestor_3_gstatus_tw), .io_requestor_3_gstatus_tvm (_ptw_io_requestor_3_gstatus_tvm), .io_requestor_3_gstatus_mxr (_ptw_io_requestor_3_gstatus_mxr), .io_requestor_3_gstatus_sum (_ptw_io_requestor_3_gstatus_sum), .io_requestor_3_gstatus_mprv (_ptw_io_requestor_3_gstatus_mprv), .io_requestor_3_gstatus_fs (_ptw_io_requestor_3_gstatus_fs), .io_requestor_3_gstatus_mpp (_ptw_io_requestor_3_gstatus_mpp), .io_requestor_3_gstatus_vs (_ptw_io_requestor_3_gstatus_vs), .io_requestor_3_gstatus_spp (_ptw_io_requestor_3_gstatus_spp), .io_requestor_3_gstatus_mpie (_ptw_io_requestor_3_gstatus_mpie), .io_requestor_3_gstatus_ube (_ptw_io_requestor_3_gstatus_ube), .io_requestor_3_gstatus_spie (_ptw_io_requestor_3_gstatus_spie), .io_requestor_3_gstatus_upie (_ptw_io_requestor_3_gstatus_upie), .io_requestor_3_gstatus_mie (_ptw_io_requestor_3_gstatus_mie), .io_requestor_3_gstatus_hie (_ptw_io_requestor_3_gstatus_hie), .io_requestor_3_gstatus_sie (_ptw_io_requestor_3_gstatus_sie), .io_requestor_3_gstatus_uie (_ptw_io_requestor_3_gstatus_uie), .io_requestor_3_pmp_0_cfg_l (_ptw_io_requestor_3_pmp_0_cfg_l), .io_requestor_3_pmp_0_cfg_a (_ptw_io_requestor_3_pmp_0_cfg_a), .io_requestor_3_pmp_0_cfg_x (_ptw_io_requestor_3_pmp_0_cfg_x), .io_requestor_3_pmp_0_cfg_w (_ptw_io_requestor_3_pmp_0_cfg_w), .io_requestor_3_pmp_0_cfg_r (_ptw_io_requestor_3_pmp_0_cfg_r), .io_requestor_3_pmp_0_addr (_ptw_io_requestor_3_pmp_0_addr), .io_requestor_3_pmp_0_mask (_ptw_io_requestor_3_pmp_0_mask), .io_requestor_3_pmp_1_cfg_l (_ptw_io_requestor_3_pmp_1_cfg_l), .io_requestor_3_pmp_1_cfg_a (_ptw_io_requestor_3_pmp_1_cfg_a), .io_requestor_3_pmp_1_cfg_x (_ptw_io_requestor_3_pmp_1_cfg_x), .io_requestor_3_pmp_1_cfg_w (_ptw_io_requestor_3_pmp_1_cfg_w), .io_requestor_3_pmp_1_cfg_r (_ptw_io_requestor_3_pmp_1_cfg_r), .io_requestor_3_pmp_1_addr (_ptw_io_requestor_3_pmp_1_addr), .io_requestor_3_pmp_1_mask (_ptw_io_requestor_3_pmp_1_mask), .io_requestor_3_pmp_2_cfg_l (_ptw_io_requestor_3_pmp_2_cfg_l), .io_requestor_3_pmp_2_cfg_a (_ptw_io_requestor_3_pmp_2_cfg_a), .io_requestor_3_pmp_2_cfg_x (_ptw_io_requestor_3_pmp_2_cfg_x), .io_requestor_3_pmp_2_cfg_w (_ptw_io_requestor_3_pmp_2_cfg_w), .io_requestor_3_pmp_2_cfg_r (_ptw_io_requestor_3_pmp_2_cfg_r), .io_requestor_3_pmp_2_addr (_ptw_io_requestor_3_pmp_2_addr), .io_requestor_3_pmp_2_mask (_ptw_io_requestor_3_pmp_2_mask), .io_requestor_3_pmp_3_cfg_l (_ptw_io_requestor_3_pmp_3_cfg_l), .io_requestor_3_pmp_3_cfg_a (_ptw_io_requestor_3_pmp_3_cfg_a), .io_requestor_3_pmp_3_cfg_x (_ptw_io_requestor_3_pmp_3_cfg_x), .io_requestor_3_pmp_3_cfg_w (_ptw_io_requestor_3_pmp_3_cfg_w), .io_requestor_3_pmp_3_cfg_r (_ptw_io_requestor_3_pmp_3_cfg_r), .io_requestor_3_pmp_3_addr (_ptw_io_requestor_3_pmp_3_addr), .io_requestor_3_pmp_3_mask (_ptw_io_requestor_3_pmp_3_mask), .io_requestor_3_pmp_4_cfg_l (_ptw_io_requestor_3_pmp_4_cfg_l), .io_requestor_3_pmp_4_cfg_a (_ptw_io_requestor_3_pmp_4_cfg_a), .io_requestor_3_pmp_4_cfg_x (_ptw_io_requestor_3_pmp_4_cfg_x), .io_requestor_3_pmp_4_cfg_w (_ptw_io_requestor_3_pmp_4_cfg_w), .io_requestor_3_pmp_4_cfg_r (_ptw_io_requestor_3_pmp_4_cfg_r), .io_requestor_3_pmp_4_addr (_ptw_io_requestor_3_pmp_4_addr), .io_requestor_3_pmp_4_mask (_ptw_io_requestor_3_pmp_4_mask), .io_requestor_3_pmp_5_cfg_l (_ptw_io_requestor_3_pmp_5_cfg_l), .io_requestor_3_pmp_5_cfg_a (_ptw_io_requestor_3_pmp_5_cfg_a), .io_requestor_3_pmp_5_cfg_x (_ptw_io_requestor_3_pmp_5_cfg_x), .io_requestor_3_pmp_5_cfg_w (_ptw_io_requestor_3_pmp_5_cfg_w), .io_requestor_3_pmp_5_cfg_r (_ptw_io_requestor_3_pmp_5_cfg_r), .io_requestor_3_pmp_5_addr (_ptw_io_requestor_3_pmp_5_addr), .io_requestor_3_pmp_5_mask (_ptw_io_requestor_3_pmp_5_mask), .io_requestor_3_pmp_6_cfg_l (_ptw_io_requestor_3_pmp_6_cfg_l), .io_requestor_3_pmp_6_cfg_a (_ptw_io_requestor_3_pmp_6_cfg_a), .io_requestor_3_pmp_6_cfg_x (_ptw_io_requestor_3_pmp_6_cfg_x), .io_requestor_3_pmp_6_cfg_w (_ptw_io_requestor_3_pmp_6_cfg_w), .io_requestor_3_pmp_6_cfg_r (_ptw_io_requestor_3_pmp_6_cfg_r), .io_requestor_3_pmp_6_addr (_ptw_io_requestor_3_pmp_6_addr), .io_requestor_3_pmp_6_mask (_ptw_io_requestor_3_pmp_6_mask), .io_requestor_3_pmp_7_cfg_l (_ptw_io_requestor_3_pmp_7_cfg_l), .io_requestor_3_pmp_7_cfg_a (_ptw_io_requestor_3_pmp_7_cfg_a), .io_requestor_3_pmp_7_cfg_x (_ptw_io_requestor_3_pmp_7_cfg_x), .io_requestor_3_pmp_7_cfg_w (_ptw_io_requestor_3_pmp_7_cfg_w), .io_requestor_3_pmp_7_cfg_r (_ptw_io_requestor_3_pmp_7_cfg_r), .io_requestor_3_pmp_7_addr (_ptw_io_requestor_3_pmp_7_addr), .io_requestor_3_pmp_7_mask (_ptw_io_requestor_3_pmp_7_mask), .io_requestor_3_customCSRs_csrs_0_ren (_ptw_io_requestor_3_customCSRs_csrs_0_ren), .io_requestor_3_customCSRs_csrs_0_wen (_ptw_io_requestor_3_customCSRs_csrs_0_wen), .io_requestor_3_customCSRs_csrs_0_wdata (_ptw_io_requestor_3_customCSRs_csrs_0_wdata), .io_requestor_3_customCSRs_csrs_0_value (_ptw_io_requestor_3_customCSRs_csrs_0_value), .io_requestor_3_customCSRs_csrs_1_ren (_ptw_io_requestor_3_customCSRs_csrs_1_ren), .io_requestor_3_customCSRs_csrs_1_wen (_ptw_io_requestor_3_customCSRs_csrs_1_wen), .io_requestor_3_customCSRs_csrs_1_wdata (_ptw_io_requestor_3_customCSRs_csrs_1_wdata), .io_requestor_3_customCSRs_csrs_1_value (_ptw_io_requestor_3_customCSRs_csrs_1_value), .io_requestor_3_customCSRs_csrs_2_ren (_ptw_io_requestor_3_customCSRs_csrs_2_ren), .io_requestor_3_customCSRs_csrs_2_wen (_ptw_io_requestor_3_customCSRs_csrs_2_wen), .io_requestor_3_customCSRs_csrs_2_wdata (_ptw_io_requestor_3_customCSRs_csrs_2_wdata), .io_requestor_3_customCSRs_csrs_2_value (_ptw_io_requestor_3_customCSRs_csrs_2_value), .io_requestor_3_customCSRs_csrs_3_ren (_ptw_io_requestor_3_customCSRs_csrs_3_ren), .io_requestor_3_customCSRs_csrs_3_wen (_ptw_io_requestor_3_customCSRs_csrs_3_wen), .io_requestor_3_customCSRs_csrs_3_wdata (_ptw_io_requestor_3_customCSRs_csrs_3_wdata), .io_requestor_3_customCSRs_csrs_3_value (_ptw_io_requestor_3_customCSRs_csrs_3_value), .io_requestor_4_req_ready (_ptw_io_requestor_4_req_ready), .io_requestor_4_req_valid (_zstd_compressor_io_ptw_4_req_valid), // @[Configs.scala:62:39] .io_requestor_4_req_bits_bits_addr (_zstd_compressor_io_ptw_4_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_4_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_4_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_4_resp_valid (_ptw_io_requestor_4_resp_valid), .io_requestor_4_resp_bits_ae_ptw (_ptw_io_requestor_4_resp_bits_ae_ptw), .io_requestor_4_resp_bits_ae_final (_ptw_io_requestor_4_resp_bits_ae_final), .io_requestor_4_resp_bits_pf (_ptw_io_requestor_4_resp_bits_pf), .io_requestor_4_resp_bits_gf (_ptw_io_requestor_4_resp_bits_gf), .io_requestor_4_resp_bits_hr (_ptw_io_requestor_4_resp_bits_hr), .io_requestor_4_resp_bits_hw (_ptw_io_requestor_4_resp_bits_hw), .io_requestor_4_resp_bits_hx (_ptw_io_requestor_4_resp_bits_hx), .io_requestor_4_resp_bits_pte_reserved_for_future (_ptw_io_requestor_4_resp_bits_pte_reserved_for_future), .io_requestor_4_resp_bits_pte_ppn (_ptw_io_requestor_4_resp_bits_pte_ppn), .io_requestor_4_resp_bits_pte_reserved_for_software (_ptw_io_requestor_4_resp_bits_pte_reserved_for_software), .io_requestor_4_resp_bits_pte_d (_ptw_io_requestor_4_resp_bits_pte_d), .io_requestor_4_resp_bits_pte_a (_ptw_io_requestor_4_resp_bits_pte_a), .io_requestor_4_resp_bits_pte_g (_ptw_io_requestor_4_resp_bits_pte_g), .io_requestor_4_resp_bits_pte_u (_ptw_io_requestor_4_resp_bits_pte_u), .io_requestor_4_resp_bits_pte_x (_ptw_io_requestor_4_resp_bits_pte_x), .io_requestor_4_resp_bits_pte_w (_ptw_io_requestor_4_resp_bits_pte_w), .io_requestor_4_resp_bits_pte_r (_ptw_io_requestor_4_resp_bits_pte_r), .io_requestor_4_resp_bits_pte_v (_ptw_io_requestor_4_resp_bits_pte_v), .io_requestor_4_resp_bits_level (_ptw_io_requestor_4_resp_bits_level), .io_requestor_4_resp_bits_homogeneous (_ptw_io_requestor_4_resp_bits_homogeneous), .io_requestor_4_resp_bits_gpa_valid (_ptw_io_requestor_4_resp_bits_gpa_valid), .io_requestor_4_resp_bits_gpa_bits (_ptw_io_requestor_4_resp_bits_gpa_bits), .io_requestor_4_resp_bits_gpa_is_pte (_ptw_io_requestor_4_resp_bits_gpa_is_pte), .io_requestor_4_ptbr_mode (_ptw_io_requestor_4_ptbr_mode), .io_requestor_4_ptbr_ppn (_ptw_io_requestor_4_ptbr_ppn), .io_requestor_4_status_debug (_ptw_io_requestor_4_status_debug), .io_requestor_4_status_cease (_ptw_io_requestor_4_status_cease), .io_requestor_4_status_wfi (_ptw_io_requestor_4_status_wfi), .io_requestor_4_status_isa (_ptw_io_requestor_4_status_isa), .io_requestor_4_status_dprv (_ptw_io_requestor_4_status_dprv), .io_requestor_4_status_dv (_ptw_io_requestor_4_status_dv), .io_requestor_4_status_prv (_ptw_io_requestor_4_status_prv), .io_requestor_4_status_v (_ptw_io_requestor_4_status_v), .io_requestor_4_status_mpv (_ptw_io_requestor_4_status_mpv), .io_requestor_4_status_gva (_ptw_io_requestor_4_status_gva), .io_requestor_4_status_tsr (_ptw_io_requestor_4_status_tsr), .io_requestor_4_status_tw (_ptw_io_requestor_4_status_tw), .io_requestor_4_status_tvm (_ptw_io_requestor_4_status_tvm), .io_requestor_4_status_mxr (_ptw_io_requestor_4_status_mxr), .io_requestor_4_status_sum (_ptw_io_requestor_4_status_sum), .io_requestor_4_status_mprv (_ptw_io_requestor_4_status_mprv), .io_requestor_4_status_fs (_ptw_io_requestor_4_status_fs), .io_requestor_4_status_mpp (_ptw_io_requestor_4_status_mpp), .io_requestor_4_status_spp (_ptw_io_requestor_4_status_spp), .io_requestor_4_status_mpie (_ptw_io_requestor_4_status_mpie), .io_requestor_4_status_spie (_ptw_io_requestor_4_status_spie), .io_requestor_4_status_mie (_ptw_io_requestor_4_status_mie), .io_requestor_4_status_sie (_ptw_io_requestor_4_status_sie), .io_requestor_4_hstatus_spvp (_ptw_io_requestor_4_hstatus_spvp), .io_requestor_4_hstatus_spv (_ptw_io_requestor_4_hstatus_spv), .io_requestor_4_hstatus_gva (_ptw_io_requestor_4_hstatus_gva), .io_requestor_4_gstatus_debug (_ptw_io_requestor_4_gstatus_debug), .io_requestor_4_gstatus_cease (_ptw_io_requestor_4_gstatus_cease), .io_requestor_4_gstatus_wfi (_ptw_io_requestor_4_gstatus_wfi), .io_requestor_4_gstatus_isa (_ptw_io_requestor_4_gstatus_isa), .io_requestor_4_gstatus_dprv (_ptw_io_requestor_4_gstatus_dprv), .io_requestor_4_gstatus_dv (_ptw_io_requestor_4_gstatus_dv), .io_requestor_4_gstatus_prv (_ptw_io_requestor_4_gstatus_prv), .io_requestor_4_gstatus_v (_ptw_io_requestor_4_gstatus_v), .io_requestor_4_gstatus_zero2 (_ptw_io_requestor_4_gstatus_zero2), .io_requestor_4_gstatus_mpv (_ptw_io_requestor_4_gstatus_mpv), .io_requestor_4_gstatus_gva (_ptw_io_requestor_4_gstatus_gva), .io_requestor_4_gstatus_mbe (_ptw_io_requestor_4_gstatus_mbe), .io_requestor_4_gstatus_sbe (_ptw_io_requestor_4_gstatus_sbe), .io_requestor_4_gstatus_sxl (_ptw_io_requestor_4_gstatus_sxl), .io_requestor_4_gstatus_zero1 (_ptw_io_requestor_4_gstatus_zero1), .io_requestor_4_gstatus_tsr (_ptw_io_requestor_4_gstatus_tsr), .io_requestor_4_gstatus_tw (_ptw_io_requestor_4_gstatus_tw), .io_requestor_4_gstatus_tvm (_ptw_io_requestor_4_gstatus_tvm), .io_requestor_4_gstatus_mxr (_ptw_io_requestor_4_gstatus_mxr), .io_requestor_4_gstatus_sum (_ptw_io_requestor_4_gstatus_sum), .io_requestor_4_gstatus_mprv (_ptw_io_requestor_4_gstatus_mprv), .io_requestor_4_gstatus_fs (_ptw_io_requestor_4_gstatus_fs), .io_requestor_4_gstatus_mpp (_ptw_io_requestor_4_gstatus_mpp), .io_requestor_4_gstatus_vs (_ptw_io_requestor_4_gstatus_vs), .io_requestor_4_gstatus_spp (_ptw_io_requestor_4_gstatus_spp), .io_requestor_4_gstatus_mpie (_ptw_io_requestor_4_gstatus_mpie), .io_requestor_4_gstatus_ube (_ptw_io_requestor_4_gstatus_ube), .io_requestor_4_gstatus_spie (_ptw_io_requestor_4_gstatus_spie), .io_requestor_4_gstatus_upie (_ptw_io_requestor_4_gstatus_upie), .io_requestor_4_gstatus_mie (_ptw_io_requestor_4_gstatus_mie), .io_requestor_4_gstatus_hie (_ptw_io_requestor_4_gstatus_hie), .io_requestor_4_gstatus_sie (_ptw_io_requestor_4_gstatus_sie), .io_requestor_4_gstatus_uie (_ptw_io_requestor_4_gstatus_uie), .io_requestor_4_pmp_0_cfg_l (_ptw_io_requestor_4_pmp_0_cfg_l), .io_requestor_4_pmp_0_cfg_a (_ptw_io_requestor_4_pmp_0_cfg_a), .io_requestor_4_pmp_0_cfg_x (_ptw_io_requestor_4_pmp_0_cfg_x), .io_requestor_4_pmp_0_cfg_w (_ptw_io_requestor_4_pmp_0_cfg_w), .io_requestor_4_pmp_0_cfg_r (_ptw_io_requestor_4_pmp_0_cfg_r), .io_requestor_4_pmp_0_addr (_ptw_io_requestor_4_pmp_0_addr), .io_requestor_4_pmp_0_mask (_ptw_io_requestor_4_pmp_0_mask), .io_requestor_4_pmp_1_cfg_l (_ptw_io_requestor_4_pmp_1_cfg_l), .io_requestor_4_pmp_1_cfg_a (_ptw_io_requestor_4_pmp_1_cfg_a), .io_requestor_4_pmp_1_cfg_x (_ptw_io_requestor_4_pmp_1_cfg_x), .io_requestor_4_pmp_1_cfg_w (_ptw_io_requestor_4_pmp_1_cfg_w), .io_requestor_4_pmp_1_cfg_r (_ptw_io_requestor_4_pmp_1_cfg_r), .io_requestor_4_pmp_1_addr (_ptw_io_requestor_4_pmp_1_addr), .io_requestor_4_pmp_1_mask (_ptw_io_requestor_4_pmp_1_mask), .io_requestor_4_pmp_2_cfg_l (_ptw_io_requestor_4_pmp_2_cfg_l), .io_requestor_4_pmp_2_cfg_a (_ptw_io_requestor_4_pmp_2_cfg_a), .io_requestor_4_pmp_2_cfg_x (_ptw_io_requestor_4_pmp_2_cfg_x), .io_requestor_4_pmp_2_cfg_w (_ptw_io_requestor_4_pmp_2_cfg_w), .io_requestor_4_pmp_2_cfg_r (_ptw_io_requestor_4_pmp_2_cfg_r), .io_requestor_4_pmp_2_addr (_ptw_io_requestor_4_pmp_2_addr), .io_requestor_4_pmp_2_mask (_ptw_io_requestor_4_pmp_2_mask), .io_requestor_4_pmp_3_cfg_l (_ptw_io_requestor_4_pmp_3_cfg_l), .io_requestor_4_pmp_3_cfg_a (_ptw_io_requestor_4_pmp_3_cfg_a), .io_requestor_4_pmp_3_cfg_x (_ptw_io_requestor_4_pmp_3_cfg_x), .io_requestor_4_pmp_3_cfg_w (_ptw_io_requestor_4_pmp_3_cfg_w), .io_requestor_4_pmp_3_cfg_r (_ptw_io_requestor_4_pmp_3_cfg_r), .io_requestor_4_pmp_3_addr (_ptw_io_requestor_4_pmp_3_addr), .io_requestor_4_pmp_3_mask (_ptw_io_requestor_4_pmp_3_mask), .io_requestor_4_pmp_4_cfg_l (_ptw_io_requestor_4_pmp_4_cfg_l), .io_requestor_4_pmp_4_cfg_a (_ptw_io_requestor_4_pmp_4_cfg_a), .io_requestor_4_pmp_4_cfg_x (_ptw_io_requestor_4_pmp_4_cfg_x), .io_requestor_4_pmp_4_cfg_w (_ptw_io_requestor_4_pmp_4_cfg_w), .io_requestor_4_pmp_4_cfg_r (_ptw_io_requestor_4_pmp_4_cfg_r), .io_requestor_4_pmp_4_addr (_ptw_io_requestor_4_pmp_4_addr), .io_requestor_4_pmp_4_mask (_ptw_io_requestor_4_pmp_4_mask), .io_requestor_4_pmp_5_cfg_l (_ptw_io_requestor_4_pmp_5_cfg_l), .io_requestor_4_pmp_5_cfg_a (_ptw_io_requestor_4_pmp_5_cfg_a), .io_requestor_4_pmp_5_cfg_x (_ptw_io_requestor_4_pmp_5_cfg_x), .io_requestor_4_pmp_5_cfg_w (_ptw_io_requestor_4_pmp_5_cfg_w), .io_requestor_4_pmp_5_cfg_r (_ptw_io_requestor_4_pmp_5_cfg_r), .io_requestor_4_pmp_5_addr (_ptw_io_requestor_4_pmp_5_addr), .io_requestor_4_pmp_5_mask (_ptw_io_requestor_4_pmp_5_mask), .io_requestor_4_pmp_6_cfg_l (_ptw_io_requestor_4_pmp_6_cfg_l), .io_requestor_4_pmp_6_cfg_a (_ptw_io_requestor_4_pmp_6_cfg_a), .io_requestor_4_pmp_6_cfg_x (_ptw_io_requestor_4_pmp_6_cfg_x), .io_requestor_4_pmp_6_cfg_w (_ptw_io_requestor_4_pmp_6_cfg_w), .io_requestor_4_pmp_6_cfg_r (_ptw_io_requestor_4_pmp_6_cfg_r), .io_requestor_4_pmp_6_addr (_ptw_io_requestor_4_pmp_6_addr), .io_requestor_4_pmp_6_mask (_ptw_io_requestor_4_pmp_6_mask), .io_requestor_4_pmp_7_cfg_l (_ptw_io_requestor_4_pmp_7_cfg_l), .io_requestor_4_pmp_7_cfg_a (_ptw_io_requestor_4_pmp_7_cfg_a), .io_requestor_4_pmp_7_cfg_x (_ptw_io_requestor_4_pmp_7_cfg_x), .io_requestor_4_pmp_7_cfg_w (_ptw_io_requestor_4_pmp_7_cfg_w), .io_requestor_4_pmp_7_cfg_r (_ptw_io_requestor_4_pmp_7_cfg_r), .io_requestor_4_pmp_7_addr (_ptw_io_requestor_4_pmp_7_addr), .io_requestor_4_pmp_7_mask (_ptw_io_requestor_4_pmp_7_mask), .io_requestor_4_customCSRs_csrs_0_ren (_ptw_io_requestor_4_customCSRs_csrs_0_ren), .io_requestor_4_customCSRs_csrs_0_wen (_ptw_io_requestor_4_customCSRs_csrs_0_wen), .io_requestor_4_customCSRs_csrs_0_wdata (_ptw_io_requestor_4_customCSRs_csrs_0_wdata), .io_requestor_4_customCSRs_csrs_0_value (_ptw_io_requestor_4_customCSRs_csrs_0_value), .io_requestor_4_customCSRs_csrs_1_ren (_ptw_io_requestor_4_customCSRs_csrs_1_ren), .io_requestor_4_customCSRs_csrs_1_wen (_ptw_io_requestor_4_customCSRs_csrs_1_wen), .io_requestor_4_customCSRs_csrs_1_wdata (_ptw_io_requestor_4_customCSRs_csrs_1_wdata), .io_requestor_4_customCSRs_csrs_1_value (_ptw_io_requestor_4_customCSRs_csrs_1_value), .io_requestor_4_customCSRs_csrs_2_ren (_ptw_io_requestor_4_customCSRs_csrs_2_ren), .io_requestor_4_customCSRs_csrs_2_wen (_ptw_io_requestor_4_customCSRs_csrs_2_wen), .io_requestor_4_customCSRs_csrs_2_wdata (_ptw_io_requestor_4_customCSRs_csrs_2_wdata), .io_requestor_4_customCSRs_csrs_2_value (_ptw_io_requestor_4_customCSRs_csrs_2_value), .io_requestor_4_customCSRs_csrs_3_ren (_ptw_io_requestor_4_customCSRs_csrs_3_ren), .io_requestor_4_customCSRs_csrs_3_wen (_ptw_io_requestor_4_customCSRs_csrs_3_wen), .io_requestor_4_customCSRs_csrs_3_wdata (_ptw_io_requestor_4_customCSRs_csrs_3_wdata), .io_requestor_4_customCSRs_csrs_3_value (_ptw_io_requestor_4_customCSRs_csrs_3_value), .io_requestor_5_req_ready (_ptw_io_requestor_5_req_ready), .io_requestor_5_req_valid (_zstd_compressor_io_ptw_5_req_valid), // @[Configs.scala:62:39] .io_requestor_5_req_bits_bits_addr (_zstd_compressor_io_ptw_5_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_5_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_5_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_5_resp_valid (_ptw_io_requestor_5_resp_valid), .io_requestor_5_resp_bits_ae_ptw (_ptw_io_requestor_5_resp_bits_ae_ptw), .io_requestor_5_resp_bits_ae_final (_ptw_io_requestor_5_resp_bits_ae_final), .io_requestor_5_resp_bits_pf (_ptw_io_requestor_5_resp_bits_pf), .io_requestor_5_resp_bits_gf (_ptw_io_requestor_5_resp_bits_gf), .io_requestor_5_resp_bits_hr (_ptw_io_requestor_5_resp_bits_hr), .io_requestor_5_resp_bits_hw (_ptw_io_requestor_5_resp_bits_hw), .io_requestor_5_resp_bits_hx (_ptw_io_requestor_5_resp_bits_hx), .io_requestor_5_resp_bits_pte_reserved_for_future (_ptw_io_requestor_5_resp_bits_pte_reserved_for_future), .io_requestor_5_resp_bits_pte_ppn (_ptw_io_requestor_5_resp_bits_pte_ppn), .io_requestor_5_resp_bits_pte_reserved_for_software (_ptw_io_requestor_5_resp_bits_pte_reserved_for_software), .io_requestor_5_resp_bits_pte_d (_ptw_io_requestor_5_resp_bits_pte_d), .io_requestor_5_resp_bits_pte_a (_ptw_io_requestor_5_resp_bits_pte_a), .io_requestor_5_resp_bits_pte_g (_ptw_io_requestor_5_resp_bits_pte_g), .io_requestor_5_resp_bits_pte_u (_ptw_io_requestor_5_resp_bits_pte_u), .io_requestor_5_resp_bits_pte_x (_ptw_io_requestor_5_resp_bits_pte_x), .io_requestor_5_resp_bits_pte_w (_ptw_io_requestor_5_resp_bits_pte_w), .io_requestor_5_resp_bits_pte_r (_ptw_io_requestor_5_resp_bits_pte_r), .io_requestor_5_resp_bits_pte_v (_ptw_io_requestor_5_resp_bits_pte_v), .io_requestor_5_resp_bits_level (_ptw_io_requestor_5_resp_bits_level), .io_requestor_5_resp_bits_homogeneous (_ptw_io_requestor_5_resp_bits_homogeneous), .io_requestor_5_resp_bits_gpa_valid (_ptw_io_requestor_5_resp_bits_gpa_valid), .io_requestor_5_resp_bits_gpa_bits (_ptw_io_requestor_5_resp_bits_gpa_bits), .io_requestor_5_resp_bits_gpa_is_pte (_ptw_io_requestor_5_resp_bits_gpa_is_pte), .io_requestor_5_ptbr_mode (_ptw_io_requestor_5_ptbr_mode), .io_requestor_5_ptbr_ppn (_ptw_io_requestor_5_ptbr_ppn), .io_requestor_5_status_debug (_ptw_io_requestor_5_status_debug), .io_requestor_5_status_cease (_ptw_io_requestor_5_status_cease), .io_requestor_5_status_wfi (_ptw_io_requestor_5_status_wfi), .io_requestor_5_status_isa (_ptw_io_requestor_5_status_isa), .io_requestor_5_status_dprv (_ptw_io_requestor_5_status_dprv), .io_requestor_5_status_dv (_ptw_io_requestor_5_status_dv), .io_requestor_5_status_prv (_ptw_io_requestor_5_status_prv), .io_requestor_5_status_v (_ptw_io_requestor_5_status_v), .io_requestor_5_status_mpv (_ptw_io_requestor_5_status_mpv), .io_requestor_5_status_gva (_ptw_io_requestor_5_status_gva), .io_requestor_5_status_tsr (_ptw_io_requestor_5_status_tsr), .io_requestor_5_status_tw (_ptw_io_requestor_5_status_tw), .io_requestor_5_status_tvm (_ptw_io_requestor_5_status_tvm), .io_requestor_5_status_mxr (_ptw_io_requestor_5_status_mxr), .io_requestor_5_status_sum (_ptw_io_requestor_5_status_sum), .io_requestor_5_status_mprv (_ptw_io_requestor_5_status_mprv), .io_requestor_5_status_fs (_ptw_io_requestor_5_status_fs), .io_requestor_5_status_mpp (_ptw_io_requestor_5_status_mpp), .io_requestor_5_status_spp (_ptw_io_requestor_5_status_spp), .io_requestor_5_status_mpie (_ptw_io_requestor_5_status_mpie), .io_requestor_5_status_spie (_ptw_io_requestor_5_status_spie), .io_requestor_5_status_mie (_ptw_io_requestor_5_status_mie), .io_requestor_5_status_sie (_ptw_io_requestor_5_status_sie), .io_requestor_5_hstatus_spvp (_ptw_io_requestor_5_hstatus_spvp), .io_requestor_5_hstatus_spv (_ptw_io_requestor_5_hstatus_spv), .io_requestor_5_hstatus_gva (_ptw_io_requestor_5_hstatus_gva), .io_requestor_5_gstatus_debug (_ptw_io_requestor_5_gstatus_debug), .io_requestor_5_gstatus_cease (_ptw_io_requestor_5_gstatus_cease), .io_requestor_5_gstatus_wfi (_ptw_io_requestor_5_gstatus_wfi), .io_requestor_5_gstatus_isa (_ptw_io_requestor_5_gstatus_isa), .io_requestor_5_gstatus_dprv (_ptw_io_requestor_5_gstatus_dprv), .io_requestor_5_gstatus_dv (_ptw_io_requestor_5_gstatus_dv), .io_requestor_5_gstatus_prv (_ptw_io_requestor_5_gstatus_prv), .io_requestor_5_gstatus_v (_ptw_io_requestor_5_gstatus_v), .io_requestor_5_gstatus_zero2 (_ptw_io_requestor_5_gstatus_zero2), .io_requestor_5_gstatus_mpv (_ptw_io_requestor_5_gstatus_mpv), .io_requestor_5_gstatus_gva (_ptw_io_requestor_5_gstatus_gva), .io_requestor_5_gstatus_mbe (_ptw_io_requestor_5_gstatus_mbe), .io_requestor_5_gstatus_sbe (_ptw_io_requestor_5_gstatus_sbe), .io_requestor_5_gstatus_sxl (_ptw_io_requestor_5_gstatus_sxl), .io_requestor_5_gstatus_zero1 (_ptw_io_requestor_5_gstatus_zero1), .io_requestor_5_gstatus_tsr (_ptw_io_requestor_5_gstatus_tsr), .io_requestor_5_gstatus_tw (_ptw_io_requestor_5_gstatus_tw), .io_requestor_5_gstatus_tvm (_ptw_io_requestor_5_gstatus_tvm), .io_requestor_5_gstatus_mxr (_ptw_io_requestor_5_gstatus_mxr), .io_requestor_5_gstatus_sum (_ptw_io_requestor_5_gstatus_sum), .io_requestor_5_gstatus_mprv (_ptw_io_requestor_5_gstatus_mprv), .io_requestor_5_gstatus_fs (_ptw_io_requestor_5_gstatus_fs), .io_requestor_5_gstatus_mpp (_ptw_io_requestor_5_gstatus_mpp), .io_requestor_5_gstatus_vs (_ptw_io_requestor_5_gstatus_vs), .io_requestor_5_gstatus_spp (_ptw_io_requestor_5_gstatus_spp), .io_requestor_5_gstatus_mpie (_ptw_io_requestor_5_gstatus_mpie), .io_requestor_5_gstatus_ube (_ptw_io_requestor_5_gstatus_ube), .io_requestor_5_gstatus_spie (_ptw_io_requestor_5_gstatus_spie), .io_requestor_5_gstatus_upie (_ptw_io_requestor_5_gstatus_upie), .io_requestor_5_gstatus_mie (_ptw_io_requestor_5_gstatus_mie), .io_requestor_5_gstatus_hie (_ptw_io_requestor_5_gstatus_hie), .io_requestor_5_gstatus_sie (_ptw_io_requestor_5_gstatus_sie), .io_requestor_5_gstatus_uie (_ptw_io_requestor_5_gstatus_uie), .io_requestor_5_pmp_0_cfg_l (_ptw_io_requestor_5_pmp_0_cfg_l), .io_requestor_5_pmp_0_cfg_a (_ptw_io_requestor_5_pmp_0_cfg_a), .io_requestor_5_pmp_0_cfg_x (_ptw_io_requestor_5_pmp_0_cfg_x), .io_requestor_5_pmp_0_cfg_w (_ptw_io_requestor_5_pmp_0_cfg_w), .io_requestor_5_pmp_0_cfg_r (_ptw_io_requestor_5_pmp_0_cfg_r), .io_requestor_5_pmp_0_addr (_ptw_io_requestor_5_pmp_0_addr), .io_requestor_5_pmp_0_mask (_ptw_io_requestor_5_pmp_0_mask), .io_requestor_5_pmp_1_cfg_l (_ptw_io_requestor_5_pmp_1_cfg_l), .io_requestor_5_pmp_1_cfg_a (_ptw_io_requestor_5_pmp_1_cfg_a), .io_requestor_5_pmp_1_cfg_x (_ptw_io_requestor_5_pmp_1_cfg_x), .io_requestor_5_pmp_1_cfg_w (_ptw_io_requestor_5_pmp_1_cfg_w), .io_requestor_5_pmp_1_cfg_r (_ptw_io_requestor_5_pmp_1_cfg_r), .io_requestor_5_pmp_1_addr (_ptw_io_requestor_5_pmp_1_addr), .io_requestor_5_pmp_1_mask (_ptw_io_requestor_5_pmp_1_mask), .io_requestor_5_pmp_2_cfg_l (_ptw_io_requestor_5_pmp_2_cfg_l), .io_requestor_5_pmp_2_cfg_a (_ptw_io_requestor_5_pmp_2_cfg_a), .io_requestor_5_pmp_2_cfg_x (_ptw_io_requestor_5_pmp_2_cfg_x), .io_requestor_5_pmp_2_cfg_w (_ptw_io_requestor_5_pmp_2_cfg_w), .io_requestor_5_pmp_2_cfg_r (_ptw_io_requestor_5_pmp_2_cfg_r), .io_requestor_5_pmp_2_addr (_ptw_io_requestor_5_pmp_2_addr), .io_requestor_5_pmp_2_mask (_ptw_io_requestor_5_pmp_2_mask), .io_requestor_5_pmp_3_cfg_l (_ptw_io_requestor_5_pmp_3_cfg_l), .io_requestor_5_pmp_3_cfg_a (_ptw_io_requestor_5_pmp_3_cfg_a), .io_requestor_5_pmp_3_cfg_x (_ptw_io_requestor_5_pmp_3_cfg_x), .io_requestor_5_pmp_3_cfg_w (_ptw_io_requestor_5_pmp_3_cfg_w), .io_requestor_5_pmp_3_cfg_r (_ptw_io_requestor_5_pmp_3_cfg_r), .io_requestor_5_pmp_3_addr (_ptw_io_requestor_5_pmp_3_addr), .io_requestor_5_pmp_3_mask (_ptw_io_requestor_5_pmp_3_mask), .io_requestor_5_pmp_4_cfg_l (_ptw_io_requestor_5_pmp_4_cfg_l), .io_requestor_5_pmp_4_cfg_a (_ptw_io_requestor_5_pmp_4_cfg_a), .io_requestor_5_pmp_4_cfg_x (_ptw_io_requestor_5_pmp_4_cfg_x), .io_requestor_5_pmp_4_cfg_w (_ptw_io_requestor_5_pmp_4_cfg_w), .io_requestor_5_pmp_4_cfg_r (_ptw_io_requestor_5_pmp_4_cfg_r), .io_requestor_5_pmp_4_addr (_ptw_io_requestor_5_pmp_4_addr), .io_requestor_5_pmp_4_mask (_ptw_io_requestor_5_pmp_4_mask), .io_requestor_5_pmp_5_cfg_l (_ptw_io_requestor_5_pmp_5_cfg_l), .io_requestor_5_pmp_5_cfg_a (_ptw_io_requestor_5_pmp_5_cfg_a), .io_requestor_5_pmp_5_cfg_x (_ptw_io_requestor_5_pmp_5_cfg_x), .io_requestor_5_pmp_5_cfg_w (_ptw_io_requestor_5_pmp_5_cfg_w), .io_requestor_5_pmp_5_cfg_r (_ptw_io_requestor_5_pmp_5_cfg_r), .io_requestor_5_pmp_5_addr (_ptw_io_requestor_5_pmp_5_addr), .io_requestor_5_pmp_5_mask (_ptw_io_requestor_5_pmp_5_mask), .io_requestor_5_pmp_6_cfg_l (_ptw_io_requestor_5_pmp_6_cfg_l), .io_requestor_5_pmp_6_cfg_a (_ptw_io_requestor_5_pmp_6_cfg_a), .io_requestor_5_pmp_6_cfg_x (_ptw_io_requestor_5_pmp_6_cfg_x), .io_requestor_5_pmp_6_cfg_w (_ptw_io_requestor_5_pmp_6_cfg_w), .io_requestor_5_pmp_6_cfg_r (_ptw_io_requestor_5_pmp_6_cfg_r), .io_requestor_5_pmp_6_addr (_ptw_io_requestor_5_pmp_6_addr), .io_requestor_5_pmp_6_mask (_ptw_io_requestor_5_pmp_6_mask), .io_requestor_5_pmp_7_cfg_l (_ptw_io_requestor_5_pmp_7_cfg_l), .io_requestor_5_pmp_7_cfg_a (_ptw_io_requestor_5_pmp_7_cfg_a), .io_requestor_5_pmp_7_cfg_x (_ptw_io_requestor_5_pmp_7_cfg_x), .io_requestor_5_pmp_7_cfg_w (_ptw_io_requestor_5_pmp_7_cfg_w), .io_requestor_5_pmp_7_cfg_r (_ptw_io_requestor_5_pmp_7_cfg_r), .io_requestor_5_pmp_7_addr (_ptw_io_requestor_5_pmp_7_addr), .io_requestor_5_pmp_7_mask (_ptw_io_requestor_5_pmp_7_mask), .io_requestor_5_customCSRs_csrs_0_ren (_ptw_io_requestor_5_customCSRs_csrs_0_ren), .io_requestor_5_customCSRs_csrs_0_wen (_ptw_io_requestor_5_customCSRs_csrs_0_wen), .io_requestor_5_customCSRs_csrs_0_wdata (_ptw_io_requestor_5_customCSRs_csrs_0_wdata), .io_requestor_5_customCSRs_csrs_0_value (_ptw_io_requestor_5_customCSRs_csrs_0_value), .io_requestor_5_customCSRs_csrs_1_ren (_ptw_io_requestor_5_customCSRs_csrs_1_ren), .io_requestor_5_customCSRs_csrs_1_wen (_ptw_io_requestor_5_customCSRs_csrs_1_wen), .io_requestor_5_customCSRs_csrs_1_wdata (_ptw_io_requestor_5_customCSRs_csrs_1_wdata), .io_requestor_5_customCSRs_csrs_1_value (_ptw_io_requestor_5_customCSRs_csrs_1_value), .io_requestor_5_customCSRs_csrs_2_ren (_ptw_io_requestor_5_customCSRs_csrs_2_ren), .io_requestor_5_customCSRs_csrs_2_wen (_ptw_io_requestor_5_customCSRs_csrs_2_wen), .io_requestor_5_customCSRs_csrs_2_wdata (_ptw_io_requestor_5_customCSRs_csrs_2_wdata), .io_requestor_5_customCSRs_csrs_2_value (_ptw_io_requestor_5_customCSRs_csrs_2_value), .io_requestor_5_customCSRs_csrs_3_ren (_ptw_io_requestor_5_customCSRs_csrs_3_ren), .io_requestor_5_customCSRs_csrs_3_wen (_ptw_io_requestor_5_customCSRs_csrs_3_wen), .io_requestor_5_customCSRs_csrs_3_wdata (_ptw_io_requestor_5_customCSRs_csrs_3_wdata), .io_requestor_5_customCSRs_csrs_3_value (_ptw_io_requestor_5_customCSRs_csrs_3_value), .io_requestor_6_req_ready (_ptw_io_requestor_6_req_ready), .io_requestor_6_req_valid (_zstd_compressor_io_ptw_6_req_valid), // @[Configs.scala:62:39] .io_requestor_6_req_bits_bits_addr (_zstd_compressor_io_ptw_6_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_6_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_6_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_6_resp_valid (_ptw_io_requestor_6_resp_valid), .io_requestor_6_resp_bits_ae_ptw (_ptw_io_requestor_6_resp_bits_ae_ptw), .io_requestor_6_resp_bits_ae_final (_ptw_io_requestor_6_resp_bits_ae_final), .io_requestor_6_resp_bits_pf (_ptw_io_requestor_6_resp_bits_pf), .io_requestor_6_resp_bits_gf (_ptw_io_requestor_6_resp_bits_gf), .io_requestor_6_resp_bits_hr (_ptw_io_requestor_6_resp_bits_hr), .io_requestor_6_resp_bits_hw (_ptw_io_requestor_6_resp_bits_hw), .io_requestor_6_resp_bits_hx (_ptw_io_requestor_6_resp_bits_hx), .io_requestor_6_resp_bits_pte_reserved_for_future (_ptw_io_requestor_6_resp_bits_pte_reserved_for_future), .io_requestor_6_resp_bits_pte_ppn (_ptw_io_requestor_6_resp_bits_pte_ppn), .io_requestor_6_resp_bits_pte_reserved_for_software (_ptw_io_requestor_6_resp_bits_pte_reserved_for_software), .io_requestor_6_resp_bits_pte_d (_ptw_io_requestor_6_resp_bits_pte_d), .io_requestor_6_resp_bits_pte_a (_ptw_io_requestor_6_resp_bits_pte_a), .io_requestor_6_resp_bits_pte_g (_ptw_io_requestor_6_resp_bits_pte_g), .io_requestor_6_resp_bits_pte_u (_ptw_io_requestor_6_resp_bits_pte_u), .io_requestor_6_resp_bits_pte_x (_ptw_io_requestor_6_resp_bits_pte_x), .io_requestor_6_resp_bits_pte_w (_ptw_io_requestor_6_resp_bits_pte_w), .io_requestor_6_resp_bits_pte_r (_ptw_io_requestor_6_resp_bits_pte_r), .io_requestor_6_resp_bits_pte_v (_ptw_io_requestor_6_resp_bits_pte_v), .io_requestor_6_resp_bits_level (_ptw_io_requestor_6_resp_bits_level), .io_requestor_6_resp_bits_homogeneous (_ptw_io_requestor_6_resp_bits_homogeneous), .io_requestor_6_resp_bits_gpa_valid (_ptw_io_requestor_6_resp_bits_gpa_valid), .io_requestor_6_resp_bits_gpa_bits (_ptw_io_requestor_6_resp_bits_gpa_bits), .io_requestor_6_resp_bits_gpa_is_pte (_ptw_io_requestor_6_resp_bits_gpa_is_pte), .io_requestor_6_ptbr_mode (_ptw_io_requestor_6_ptbr_mode), .io_requestor_6_ptbr_ppn (_ptw_io_requestor_6_ptbr_ppn), .io_requestor_6_status_debug (_ptw_io_requestor_6_status_debug), .io_requestor_6_status_cease (_ptw_io_requestor_6_status_cease), .io_requestor_6_status_wfi (_ptw_io_requestor_6_status_wfi), .io_requestor_6_status_isa (_ptw_io_requestor_6_status_isa), .io_requestor_6_status_dprv (_ptw_io_requestor_6_status_dprv), .io_requestor_6_status_dv (_ptw_io_requestor_6_status_dv), .io_requestor_6_status_prv (_ptw_io_requestor_6_status_prv), .io_requestor_6_status_v (_ptw_io_requestor_6_status_v), .io_requestor_6_status_mpv (_ptw_io_requestor_6_status_mpv), .io_requestor_6_status_gva (_ptw_io_requestor_6_status_gva), .io_requestor_6_status_tsr (_ptw_io_requestor_6_status_tsr), .io_requestor_6_status_tw (_ptw_io_requestor_6_status_tw), .io_requestor_6_status_tvm (_ptw_io_requestor_6_status_tvm), .io_requestor_6_status_mxr (_ptw_io_requestor_6_status_mxr), .io_requestor_6_status_sum (_ptw_io_requestor_6_status_sum), .io_requestor_6_status_mprv (_ptw_io_requestor_6_status_mprv), .io_requestor_6_status_fs (_ptw_io_requestor_6_status_fs), .io_requestor_6_status_mpp (_ptw_io_requestor_6_status_mpp), .io_requestor_6_status_spp (_ptw_io_requestor_6_status_spp), .io_requestor_6_status_mpie (_ptw_io_requestor_6_status_mpie), .io_requestor_6_status_spie (_ptw_io_requestor_6_status_spie), .io_requestor_6_status_mie (_ptw_io_requestor_6_status_mie), .io_requestor_6_status_sie (_ptw_io_requestor_6_status_sie), .io_requestor_6_hstatus_spvp (_ptw_io_requestor_6_hstatus_spvp), .io_requestor_6_hstatus_spv (_ptw_io_requestor_6_hstatus_spv), .io_requestor_6_hstatus_gva (_ptw_io_requestor_6_hstatus_gva), .io_requestor_6_gstatus_debug (_ptw_io_requestor_6_gstatus_debug), .io_requestor_6_gstatus_cease (_ptw_io_requestor_6_gstatus_cease), .io_requestor_6_gstatus_wfi (_ptw_io_requestor_6_gstatus_wfi), .io_requestor_6_gstatus_isa (_ptw_io_requestor_6_gstatus_isa), .io_requestor_6_gstatus_dprv (_ptw_io_requestor_6_gstatus_dprv), .io_requestor_6_gstatus_dv (_ptw_io_requestor_6_gstatus_dv), .io_requestor_6_gstatus_prv (_ptw_io_requestor_6_gstatus_prv), .io_requestor_6_gstatus_v (_ptw_io_requestor_6_gstatus_v), .io_requestor_6_gstatus_zero2 (_ptw_io_requestor_6_gstatus_zero2), .io_requestor_6_gstatus_mpv (_ptw_io_requestor_6_gstatus_mpv), .io_requestor_6_gstatus_gva (_ptw_io_requestor_6_gstatus_gva), .io_requestor_6_gstatus_mbe (_ptw_io_requestor_6_gstatus_mbe), .io_requestor_6_gstatus_sbe (_ptw_io_requestor_6_gstatus_sbe), .io_requestor_6_gstatus_sxl (_ptw_io_requestor_6_gstatus_sxl), .io_requestor_6_gstatus_zero1 (_ptw_io_requestor_6_gstatus_zero1), .io_requestor_6_gstatus_tsr (_ptw_io_requestor_6_gstatus_tsr), .io_requestor_6_gstatus_tw (_ptw_io_requestor_6_gstatus_tw), .io_requestor_6_gstatus_tvm (_ptw_io_requestor_6_gstatus_tvm), .io_requestor_6_gstatus_mxr (_ptw_io_requestor_6_gstatus_mxr), .io_requestor_6_gstatus_sum (_ptw_io_requestor_6_gstatus_sum), .io_requestor_6_gstatus_mprv (_ptw_io_requestor_6_gstatus_mprv), .io_requestor_6_gstatus_fs (_ptw_io_requestor_6_gstatus_fs), .io_requestor_6_gstatus_mpp (_ptw_io_requestor_6_gstatus_mpp), .io_requestor_6_gstatus_vs (_ptw_io_requestor_6_gstatus_vs), .io_requestor_6_gstatus_spp (_ptw_io_requestor_6_gstatus_spp), .io_requestor_6_gstatus_mpie (_ptw_io_requestor_6_gstatus_mpie), .io_requestor_6_gstatus_ube (_ptw_io_requestor_6_gstatus_ube), .io_requestor_6_gstatus_spie (_ptw_io_requestor_6_gstatus_spie), .io_requestor_6_gstatus_upie (_ptw_io_requestor_6_gstatus_upie), .io_requestor_6_gstatus_mie (_ptw_io_requestor_6_gstatus_mie), .io_requestor_6_gstatus_hie (_ptw_io_requestor_6_gstatus_hie), .io_requestor_6_gstatus_sie (_ptw_io_requestor_6_gstatus_sie), .io_requestor_6_gstatus_uie (_ptw_io_requestor_6_gstatus_uie), .io_requestor_6_pmp_0_cfg_l (_ptw_io_requestor_6_pmp_0_cfg_l), .io_requestor_6_pmp_0_cfg_a (_ptw_io_requestor_6_pmp_0_cfg_a), .io_requestor_6_pmp_0_cfg_x (_ptw_io_requestor_6_pmp_0_cfg_x), .io_requestor_6_pmp_0_cfg_w (_ptw_io_requestor_6_pmp_0_cfg_w), .io_requestor_6_pmp_0_cfg_r (_ptw_io_requestor_6_pmp_0_cfg_r), .io_requestor_6_pmp_0_addr (_ptw_io_requestor_6_pmp_0_addr), .io_requestor_6_pmp_0_mask (_ptw_io_requestor_6_pmp_0_mask), .io_requestor_6_pmp_1_cfg_l (_ptw_io_requestor_6_pmp_1_cfg_l), .io_requestor_6_pmp_1_cfg_a (_ptw_io_requestor_6_pmp_1_cfg_a), .io_requestor_6_pmp_1_cfg_x (_ptw_io_requestor_6_pmp_1_cfg_x), .io_requestor_6_pmp_1_cfg_w (_ptw_io_requestor_6_pmp_1_cfg_w), .io_requestor_6_pmp_1_cfg_r (_ptw_io_requestor_6_pmp_1_cfg_r), .io_requestor_6_pmp_1_addr (_ptw_io_requestor_6_pmp_1_addr), .io_requestor_6_pmp_1_mask (_ptw_io_requestor_6_pmp_1_mask), .io_requestor_6_pmp_2_cfg_l (_ptw_io_requestor_6_pmp_2_cfg_l), .io_requestor_6_pmp_2_cfg_a (_ptw_io_requestor_6_pmp_2_cfg_a), .io_requestor_6_pmp_2_cfg_x (_ptw_io_requestor_6_pmp_2_cfg_x), .io_requestor_6_pmp_2_cfg_w (_ptw_io_requestor_6_pmp_2_cfg_w), .io_requestor_6_pmp_2_cfg_r (_ptw_io_requestor_6_pmp_2_cfg_r), .io_requestor_6_pmp_2_addr (_ptw_io_requestor_6_pmp_2_addr), .io_requestor_6_pmp_2_mask (_ptw_io_requestor_6_pmp_2_mask), .io_requestor_6_pmp_3_cfg_l (_ptw_io_requestor_6_pmp_3_cfg_l), .io_requestor_6_pmp_3_cfg_a (_ptw_io_requestor_6_pmp_3_cfg_a), .io_requestor_6_pmp_3_cfg_x (_ptw_io_requestor_6_pmp_3_cfg_x), .io_requestor_6_pmp_3_cfg_w (_ptw_io_requestor_6_pmp_3_cfg_w), .io_requestor_6_pmp_3_cfg_r (_ptw_io_requestor_6_pmp_3_cfg_r), .io_requestor_6_pmp_3_addr (_ptw_io_requestor_6_pmp_3_addr), .io_requestor_6_pmp_3_mask (_ptw_io_requestor_6_pmp_3_mask), .io_requestor_6_pmp_4_cfg_l (_ptw_io_requestor_6_pmp_4_cfg_l), .io_requestor_6_pmp_4_cfg_a (_ptw_io_requestor_6_pmp_4_cfg_a), .io_requestor_6_pmp_4_cfg_x (_ptw_io_requestor_6_pmp_4_cfg_x), .io_requestor_6_pmp_4_cfg_w (_ptw_io_requestor_6_pmp_4_cfg_w), .io_requestor_6_pmp_4_cfg_r (_ptw_io_requestor_6_pmp_4_cfg_r), .io_requestor_6_pmp_4_addr (_ptw_io_requestor_6_pmp_4_addr), .io_requestor_6_pmp_4_mask (_ptw_io_requestor_6_pmp_4_mask), .io_requestor_6_pmp_5_cfg_l (_ptw_io_requestor_6_pmp_5_cfg_l), .io_requestor_6_pmp_5_cfg_a (_ptw_io_requestor_6_pmp_5_cfg_a), .io_requestor_6_pmp_5_cfg_x (_ptw_io_requestor_6_pmp_5_cfg_x), .io_requestor_6_pmp_5_cfg_w (_ptw_io_requestor_6_pmp_5_cfg_w), .io_requestor_6_pmp_5_cfg_r (_ptw_io_requestor_6_pmp_5_cfg_r), .io_requestor_6_pmp_5_addr (_ptw_io_requestor_6_pmp_5_addr), .io_requestor_6_pmp_5_mask (_ptw_io_requestor_6_pmp_5_mask), .io_requestor_6_pmp_6_cfg_l (_ptw_io_requestor_6_pmp_6_cfg_l), .io_requestor_6_pmp_6_cfg_a (_ptw_io_requestor_6_pmp_6_cfg_a), .io_requestor_6_pmp_6_cfg_x (_ptw_io_requestor_6_pmp_6_cfg_x), .io_requestor_6_pmp_6_cfg_w (_ptw_io_requestor_6_pmp_6_cfg_w), .io_requestor_6_pmp_6_cfg_r (_ptw_io_requestor_6_pmp_6_cfg_r), .io_requestor_6_pmp_6_addr (_ptw_io_requestor_6_pmp_6_addr), .io_requestor_6_pmp_6_mask (_ptw_io_requestor_6_pmp_6_mask), .io_requestor_6_pmp_7_cfg_l (_ptw_io_requestor_6_pmp_7_cfg_l), .io_requestor_6_pmp_7_cfg_a (_ptw_io_requestor_6_pmp_7_cfg_a), .io_requestor_6_pmp_7_cfg_x (_ptw_io_requestor_6_pmp_7_cfg_x), .io_requestor_6_pmp_7_cfg_w (_ptw_io_requestor_6_pmp_7_cfg_w), .io_requestor_6_pmp_7_cfg_r (_ptw_io_requestor_6_pmp_7_cfg_r), .io_requestor_6_pmp_7_addr (_ptw_io_requestor_6_pmp_7_addr), .io_requestor_6_pmp_7_mask (_ptw_io_requestor_6_pmp_7_mask), .io_requestor_6_customCSRs_csrs_0_ren (_ptw_io_requestor_6_customCSRs_csrs_0_ren), .io_requestor_6_customCSRs_csrs_0_wen (_ptw_io_requestor_6_customCSRs_csrs_0_wen), .io_requestor_6_customCSRs_csrs_0_wdata (_ptw_io_requestor_6_customCSRs_csrs_0_wdata), .io_requestor_6_customCSRs_csrs_0_value (_ptw_io_requestor_6_customCSRs_csrs_0_value), .io_requestor_6_customCSRs_csrs_1_ren (_ptw_io_requestor_6_customCSRs_csrs_1_ren), .io_requestor_6_customCSRs_csrs_1_wen (_ptw_io_requestor_6_customCSRs_csrs_1_wen), .io_requestor_6_customCSRs_csrs_1_wdata (_ptw_io_requestor_6_customCSRs_csrs_1_wdata), .io_requestor_6_customCSRs_csrs_1_value (_ptw_io_requestor_6_customCSRs_csrs_1_value), .io_requestor_6_customCSRs_csrs_2_ren (_ptw_io_requestor_6_customCSRs_csrs_2_ren), .io_requestor_6_customCSRs_csrs_2_wen (_ptw_io_requestor_6_customCSRs_csrs_2_wen), .io_requestor_6_customCSRs_csrs_2_wdata (_ptw_io_requestor_6_customCSRs_csrs_2_wdata), .io_requestor_6_customCSRs_csrs_2_value (_ptw_io_requestor_6_customCSRs_csrs_2_value), .io_requestor_6_customCSRs_csrs_3_ren (_ptw_io_requestor_6_customCSRs_csrs_3_ren), .io_requestor_6_customCSRs_csrs_3_wen (_ptw_io_requestor_6_customCSRs_csrs_3_wen), .io_requestor_6_customCSRs_csrs_3_wdata (_ptw_io_requestor_6_customCSRs_csrs_3_wdata), .io_requestor_6_customCSRs_csrs_3_value (_ptw_io_requestor_6_customCSRs_csrs_3_value), .io_requestor_7_req_ready (_ptw_io_requestor_7_req_ready), .io_requestor_7_req_valid (_zstd_compressor_io_ptw_7_req_valid), // @[Configs.scala:62:39] .io_requestor_7_req_bits_bits_addr (_zstd_compressor_io_ptw_7_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_7_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_7_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_7_resp_valid (_ptw_io_requestor_7_resp_valid), .io_requestor_7_resp_bits_ae_ptw (_ptw_io_requestor_7_resp_bits_ae_ptw), .io_requestor_7_resp_bits_ae_final (_ptw_io_requestor_7_resp_bits_ae_final), .io_requestor_7_resp_bits_pf (_ptw_io_requestor_7_resp_bits_pf), .io_requestor_7_resp_bits_gf (_ptw_io_requestor_7_resp_bits_gf), .io_requestor_7_resp_bits_hr (_ptw_io_requestor_7_resp_bits_hr), .io_requestor_7_resp_bits_hw (_ptw_io_requestor_7_resp_bits_hw), .io_requestor_7_resp_bits_hx (_ptw_io_requestor_7_resp_bits_hx), .io_requestor_7_resp_bits_pte_reserved_for_future (_ptw_io_requestor_7_resp_bits_pte_reserved_for_future), .io_requestor_7_resp_bits_pte_ppn (_ptw_io_requestor_7_resp_bits_pte_ppn), .io_requestor_7_resp_bits_pte_reserved_for_software (_ptw_io_requestor_7_resp_bits_pte_reserved_for_software), .io_requestor_7_resp_bits_pte_d (_ptw_io_requestor_7_resp_bits_pte_d), .io_requestor_7_resp_bits_pte_a (_ptw_io_requestor_7_resp_bits_pte_a), .io_requestor_7_resp_bits_pte_g (_ptw_io_requestor_7_resp_bits_pte_g), .io_requestor_7_resp_bits_pte_u (_ptw_io_requestor_7_resp_bits_pte_u), .io_requestor_7_resp_bits_pte_x (_ptw_io_requestor_7_resp_bits_pte_x), .io_requestor_7_resp_bits_pte_w (_ptw_io_requestor_7_resp_bits_pte_w), .io_requestor_7_resp_bits_pte_r (_ptw_io_requestor_7_resp_bits_pte_r), .io_requestor_7_resp_bits_pte_v (_ptw_io_requestor_7_resp_bits_pte_v), .io_requestor_7_resp_bits_level (_ptw_io_requestor_7_resp_bits_level), .io_requestor_7_resp_bits_homogeneous (_ptw_io_requestor_7_resp_bits_homogeneous), .io_requestor_7_resp_bits_gpa_valid (_ptw_io_requestor_7_resp_bits_gpa_valid), .io_requestor_7_resp_bits_gpa_bits (_ptw_io_requestor_7_resp_bits_gpa_bits), .io_requestor_7_resp_bits_gpa_is_pte (_ptw_io_requestor_7_resp_bits_gpa_is_pte), .io_requestor_7_ptbr_mode (_ptw_io_requestor_7_ptbr_mode), .io_requestor_7_ptbr_ppn (_ptw_io_requestor_7_ptbr_ppn), .io_requestor_7_status_debug (_ptw_io_requestor_7_status_debug), .io_requestor_7_status_cease (_ptw_io_requestor_7_status_cease), .io_requestor_7_status_wfi (_ptw_io_requestor_7_status_wfi), .io_requestor_7_status_isa (_ptw_io_requestor_7_status_isa), .io_requestor_7_status_dprv (_ptw_io_requestor_7_status_dprv), .io_requestor_7_status_dv (_ptw_io_requestor_7_status_dv), .io_requestor_7_status_prv (_ptw_io_requestor_7_status_prv), .io_requestor_7_status_v (_ptw_io_requestor_7_status_v), .io_requestor_7_status_mpv (_ptw_io_requestor_7_status_mpv), .io_requestor_7_status_gva (_ptw_io_requestor_7_status_gva), .io_requestor_7_status_tsr (_ptw_io_requestor_7_status_tsr), .io_requestor_7_status_tw (_ptw_io_requestor_7_status_tw), .io_requestor_7_status_tvm (_ptw_io_requestor_7_status_tvm), .io_requestor_7_status_mxr (_ptw_io_requestor_7_status_mxr), .io_requestor_7_status_sum (_ptw_io_requestor_7_status_sum), .io_requestor_7_status_mprv (_ptw_io_requestor_7_status_mprv), .io_requestor_7_status_fs (_ptw_io_requestor_7_status_fs), .io_requestor_7_status_mpp (_ptw_io_requestor_7_status_mpp), .io_requestor_7_status_spp (_ptw_io_requestor_7_status_spp), .io_requestor_7_status_mpie (_ptw_io_requestor_7_status_mpie), .io_requestor_7_status_spie (_ptw_io_requestor_7_status_spie), .io_requestor_7_status_mie (_ptw_io_requestor_7_status_mie), .io_requestor_7_status_sie (_ptw_io_requestor_7_status_sie), .io_requestor_7_hstatus_spvp (_ptw_io_requestor_7_hstatus_spvp), .io_requestor_7_hstatus_spv (_ptw_io_requestor_7_hstatus_spv), .io_requestor_7_hstatus_gva (_ptw_io_requestor_7_hstatus_gva), .io_requestor_7_gstatus_debug (_ptw_io_requestor_7_gstatus_debug), .io_requestor_7_gstatus_cease (_ptw_io_requestor_7_gstatus_cease), .io_requestor_7_gstatus_wfi (_ptw_io_requestor_7_gstatus_wfi), .io_requestor_7_gstatus_isa (_ptw_io_requestor_7_gstatus_isa), .io_requestor_7_gstatus_dprv (_ptw_io_requestor_7_gstatus_dprv), .io_requestor_7_gstatus_dv (_ptw_io_requestor_7_gstatus_dv), .io_requestor_7_gstatus_prv (_ptw_io_requestor_7_gstatus_prv), .io_requestor_7_gstatus_v (_ptw_io_requestor_7_gstatus_v), .io_requestor_7_gstatus_zero2 (_ptw_io_requestor_7_gstatus_zero2), .io_requestor_7_gstatus_mpv (_ptw_io_requestor_7_gstatus_mpv), .io_requestor_7_gstatus_gva (_ptw_io_requestor_7_gstatus_gva), .io_requestor_7_gstatus_mbe (_ptw_io_requestor_7_gstatus_mbe), .io_requestor_7_gstatus_sbe (_ptw_io_requestor_7_gstatus_sbe), .io_requestor_7_gstatus_sxl (_ptw_io_requestor_7_gstatus_sxl), .io_requestor_7_gstatus_zero1 (_ptw_io_requestor_7_gstatus_zero1), .io_requestor_7_gstatus_tsr (_ptw_io_requestor_7_gstatus_tsr), .io_requestor_7_gstatus_tw (_ptw_io_requestor_7_gstatus_tw), .io_requestor_7_gstatus_tvm (_ptw_io_requestor_7_gstatus_tvm), .io_requestor_7_gstatus_mxr (_ptw_io_requestor_7_gstatus_mxr), .io_requestor_7_gstatus_sum (_ptw_io_requestor_7_gstatus_sum), .io_requestor_7_gstatus_mprv (_ptw_io_requestor_7_gstatus_mprv), .io_requestor_7_gstatus_fs (_ptw_io_requestor_7_gstatus_fs), .io_requestor_7_gstatus_mpp (_ptw_io_requestor_7_gstatus_mpp), .io_requestor_7_gstatus_vs (_ptw_io_requestor_7_gstatus_vs), .io_requestor_7_gstatus_spp (_ptw_io_requestor_7_gstatus_spp), .io_requestor_7_gstatus_mpie (_ptw_io_requestor_7_gstatus_mpie), .io_requestor_7_gstatus_ube (_ptw_io_requestor_7_gstatus_ube), .io_requestor_7_gstatus_spie (_ptw_io_requestor_7_gstatus_spie), .io_requestor_7_gstatus_upie (_ptw_io_requestor_7_gstatus_upie), .io_requestor_7_gstatus_mie (_ptw_io_requestor_7_gstatus_mie), .io_requestor_7_gstatus_hie (_ptw_io_requestor_7_gstatus_hie), .io_requestor_7_gstatus_sie (_ptw_io_requestor_7_gstatus_sie), .io_requestor_7_gstatus_uie (_ptw_io_requestor_7_gstatus_uie), .io_requestor_7_pmp_0_cfg_l (_ptw_io_requestor_7_pmp_0_cfg_l), .io_requestor_7_pmp_0_cfg_a (_ptw_io_requestor_7_pmp_0_cfg_a), .io_requestor_7_pmp_0_cfg_x (_ptw_io_requestor_7_pmp_0_cfg_x), .io_requestor_7_pmp_0_cfg_w (_ptw_io_requestor_7_pmp_0_cfg_w), .io_requestor_7_pmp_0_cfg_r (_ptw_io_requestor_7_pmp_0_cfg_r), .io_requestor_7_pmp_0_addr (_ptw_io_requestor_7_pmp_0_addr), .io_requestor_7_pmp_0_mask (_ptw_io_requestor_7_pmp_0_mask), .io_requestor_7_pmp_1_cfg_l (_ptw_io_requestor_7_pmp_1_cfg_l), .io_requestor_7_pmp_1_cfg_a (_ptw_io_requestor_7_pmp_1_cfg_a), .io_requestor_7_pmp_1_cfg_x (_ptw_io_requestor_7_pmp_1_cfg_x), .io_requestor_7_pmp_1_cfg_w (_ptw_io_requestor_7_pmp_1_cfg_w), .io_requestor_7_pmp_1_cfg_r (_ptw_io_requestor_7_pmp_1_cfg_r), .io_requestor_7_pmp_1_addr (_ptw_io_requestor_7_pmp_1_addr), .io_requestor_7_pmp_1_mask (_ptw_io_requestor_7_pmp_1_mask), .io_requestor_7_pmp_2_cfg_l (_ptw_io_requestor_7_pmp_2_cfg_l), .io_requestor_7_pmp_2_cfg_a (_ptw_io_requestor_7_pmp_2_cfg_a), .io_requestor_7_pmp_2_cfg_x (_ptw_io_requestor_7_pmp_2_cfg_x), .io_requestor_7_pmp_2_cfg_w (_ptw_io_requestor_7_pmp_2_cfg_w), .io_requestor_7_pmp_2_cfg_r (_ptw_io_requestor_7_pmp_2_cfg_r), .io_requestor_7_pmp_2_addr (_ptw_io_requestor_7_pmp_2_addr), .io_requestor_7_pmp_2_mask (_ptw_io_requestor_7_pmp_2_mask), .io_requestor_7_pmp_3_cfg_l (_ptw_io_requestor_7_pmp_3_cfg_l), .io_requestor_7_pmp_3_cfg_a (_ptw_io_requestor_7_pmp_3_cfg_a), .io_requestor_7_pmp_3_cfg_x (_ptw_io_requestor_7_pmp_3_cfg_x), .io_requestor_7_pmp_3_cfg_w (_ptw_io_requestor_7_pmp_3_cfg_w), .io_requestor_7_pmp_3_cfg_r (_ptw_io_requestor_7_pmp_3_cfg_r), .io_requestor_7_pmp_3_addr (_ptw_io_requestor_7_pmp_3_addr), .io_requestor_7_pmp_3_mask (_ptw_io_requestor_7_pmp_3_mask), .io_requestor_7_pmp_4_cfg_l (_ptw_io_requestor_7_pmp_4_cfg_l), .io_requestor_7_pmp_4_cfg_a (_ptw_io_requestor_7_pmp_4_cfg_a), .io_requestor_7_pmp_4_cfg_x (_ptw_io_requestor_7_pmp_4_cfg_x), .io_requestor_7_pmp_4_cfg_w (_ptw_io_requestor_7_pmp_4_cfg_w), .io_requestor_7_pmp_4_cfg_r (_ptw_io_requestor_7_pmp_4_cfg_r), .io_requestor_7_pmp_4_addr (_ptw_io_requestor_7_pmp_4_addr), .io_requestor_7_pmp_4_mask (_ptw_io_requestor_7_pmp_4_mask), .io_requestor_7_pmp_5_cfg_l (_ptw_io_requestor_7_pmp_5_cfg_l), .io_requestor_7_pmp_5_cfg_a (_ptw_io_requestor_7_pmp_5_cfg_a), .io_requestor_7_pmp_5_cfg_x (_ptw_io_requestor_7_pmp_5_cfg_x), .io_requestor_7_pmp_5_cfg_w (_ptw_io_requestor_7_pmp_5_cfg_w), .io_requestor_7_pmp_5_cfg_r (_ptw_io_requestor_7_pmp_5_cfg_r), .io_requestor_7_pmp_5_addr (_ptw_io_requestor_7_pmp_5_addr), .io_requestor_7_pmp_5_mask (_ptw_io_requestor_7_pmp_5_mask), .io_requestor_7_pmp_6_cfg_l (_ptw_io_requestor_7_pmp_6_cfg_l), .io_requestor_7_pmp_6_cfg_a (_ptw_io_requestor_7_pmp_6_cfg_a), .io_requestor_7_pmp_6_cfg_x (_ptw_io_requestor_7_pmp_6_cfg_x), .io_requestor_7_pmp_6_cfg_w (_ptw_io_requestor_7_pmp_6_cfg_w), .io_requestor_7_pmp_6_cfg_r (_ptw_io_requestor_7_pmp_6_cfg_r), .io_requestor_7_pmp_6_addr (_ptw_io_requestor_7_pmp_6_addr), .io_requestor_7_pmp_6_mask (_ptw_io_requestor_7_pmp_6_mask), .io_requestor_7_pmp_7_cfg_l (_ptw_io_requestor_7_pmp_7_cfg_l), .io_requestor_7_pmp_7_cfg_a (_ptw_io_requestor_7_pmp_7_cfg_a), .io_requestor_7_pmp_7_cfg_x (_ptw_io_requestor_7_pmp_7_cfg_x), .io_requestor_7_pmp_7_cfg_w (_ptw_io_requestor_7_pmp_7_cfg_w), .io_requestor_7_pmp_7_cfg_r (_ptw_io_requestor_7_pmp_7_cfg_r), .io_requestor_7_pmp_7_addr (_ptw_io_requestor_7_pmp_7_addr), .io_requestor_7_pmp_7_mask (_ptw_io_requestor_7_pmp_7_mask), .io_requestor_7_customCSRs_csrs_0_ren (_ptw_io_requestor_7_customCSRs_csrs_0_ren), .io_requestor_7_customCSRs_csrs_0_wen (_ptw_io_requestor_7_customCSRs_csrs_0_wen), .io_requestor_7_customCSRs_csrs_0_wdata (_ptw_io_requestor_7_customCSRs_csrs_0_wdata), .io_requestor_7_customCSRs_csrs_0_value (_ptw_io_requestor_7_customCSRs_csrs_0_value), .io_requestor_7_customCSRs_csrs_1_ren (_ptw_io_requestor_7_customCSRs_csrs_1_ren), .io_requestor_7_customCSRs_csrs_1_wen (_ptw_io_requestor_7_customCSRs_csrs_1_wen), .io_requestor_7_customCSRs_csrs_1_wdata (_ptw_io_requestor_7_customCSRs_csrs_1_wdata), .io_requestor_7_customCSRs_csrs_1_value (_ptw_io_requestor_7_customCSRs_csrs_1_value), .io_requestor_7_customCSRs_csrs_2_ren (_ptw_io_requestor_7_customCSRs_csrs_2_ren), .io_requestor_7_customCSRs_csrs_2_wen (_ptw_io_requestor_7_customCSRs_csrs_2_wen), .io_requestor_7_customCSRs_csrs_2_wdata (_ptw_io_requestor_7_customCSRs_csrs_2_wdata), .io_requestor_7_customCSRs_csrs_2_value (_ptw_io_requestor_7_customCSRs_csrs_2_value), .io_requestor_7_customCSRs_csrs_3_ren (_ptw_io_requestor_7_customCSRs_csrs_3_ren), .io_requestor_7_customCSRs_csrs_3_wen (_ptw_io_requestor_7_customCSRs_csrs_3_wen), .io_requestor_7_customCSRs_csrs_3_wdata (_ptw_io_requestor_7_customCSRs_csrs_3_wdata), .io_requestor_7_customCSRs_csrs_3_value (_ptw_io_requestor_7_customCSRs_csrs_3_value), .io_requestor_8_req_ready (_ptw_io_requestor_8_req_ready), .io_requestor_8_req_valid (_zstd_compressor_io_ptw_8_req_valid), // @[Configs.scala:62:39] .io_requestor_8_req_bits_bits_addr (_zstd_compressor_io_ptw_8_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_8_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_8_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_8_resp_valid (_ptw_io_requestor_8_resp_valid), .io_requestor_8_resp_bits_ae_ptw (_ptw_io_requestor_8_resp_bits_ae_ptw), .io_requestor_8_resp_bits_ae_final (_ptw_io_requestor_8_resp_bits_ae_final), .io_requestor_8_resp_bits_pf (_ptw_io_requestor_8_resp_bits_pf), .io_requestor_8_resp_bits_gf (_ptw_io_requestor_8_resp_bits_gf), .io_requestor_8_resp_bits_hr (_ptw_io_requestor_8_resp_bits_hr), .io_requestor_8_resp_bits_hw (_ptw_io_requestor_8_resp_bits_hw), .io_requestor_8_resp_bits_hx (_ptw_io_requestor_8_resp_bits_hx), .io_requestor_8_resp_bits_pte_reserved_for_future (_ptw_io_requestor_8_resp_bits_pte_reserved_for_future), .io_requestor_8_resp_bits_pte_ppn (_ptw_io_requestor_8_resp_bits_pte_ppn), .io_requestor_8_resp_bits_pte_reserved_for_software (_ptw_io_requestor_8_resp_bits_pte_reserved_for_software), .io_requestor_8_resp_bits_pte_d (_ptw_io_requestor_8_resp_bits_pte_d), .io_requestor_8_resp_bits_pte_a (_ptw_io_requestor_8_resp_bits_pte_a), .io_requestor_8_resp_bits_pte_g (_ptw_io_requestor_8_resp_bits_pte_g), .io_requestor_8_resp_bits_pte_u (_ptw_io_requestor_8_resp_bits_pte_u), .io_requestor_8_resp_bits_pte_x (_ptw_io_requestor_8_resp_bits_pte_x), .io_requestor_8_resp_bits_pte_w (_ptw_io_requestor_8_resp_bits_pte_w), .io_requestor_8_resp_bits_pte_r (_ptw_io_requestor_8_resp_bits_pte_r), .io_requestor_8_resp_bits_pte_v (_ptw_io_requestor_8_resp_bits_pte_v), .io_requestor_8_resp_bits_level (_ptw_io_requestor_8_resp_bits_level), .io_requestor_8_resp_bits_homogeneous (_ptw_io_requestor_8_resp_bits_homogeneous), .io_requestor_8_resp_bits_gpa_valid (_ptw_io_requestor_8_resp_bits_gpa_valid), .io_requestor_8_resp_bits_gpa_bits (_ptw_io_requestor_8_resp_bits_gpa_bits), .io_requestor_8_resp_bits_gpa_is_pte (_ptw_io_requestor_8_resp_bits_gpa_is_pte), .io_requestor_8_ptbr_mode (_ptw_io_requestor_8_ptbr_mode), .io_requestor_8_ptbr_ppn (_ptw_io_requestor_8_ptbr_ppn), .io_requestor_8_status_debug (_ptw_io_requestor_8_status_debug), .io_requestor_8_status_cease (_ptw_io_requestor_8_status_cease), .io_requestor_8_status_wfi (_ptw_io_requestor_8_status_wfi), .io_requestor_8_status_isa (_ptw_io_requestor_8_status_isa), .io_requestor_8_status_dprv (_ptw_io_requestor_8_status_dprv), .io_requestor_8_status_dv (_ptw_io_requestor_8_status_dv), .io_requestor_8_status_prv (_ptw_io_requestor_8_status_prv), .io_requestor_8_status_v (_ptw_io_requestor_8_status_v), .io_requestor_8_status_mpv (_ptw_io_requestor_8_status_mpv), .io_requestor_8_status_gva (_ptw_io_requestor_8_status_gva), .io_requestor_8_status_tsr (_ptw_io_requestor_8_status_tsr), .io_requestor_8_status_tw (_ptw_io_requestor_8_status_tw), .io_requestor_8_status_tvm (_ptw_io_requestor_8_status_tvm), .io_requestor_8_status_mxr (_ptw_io_requestor_8_status_mxr), .io_requestor_8_status_sum (_ptw_io_requestor_8_status_sum), .io_requestor_8_status_mprv (_ptw_io_requestor_8_status_mprv), .io_requestor_8_status_fs (_ptw_io_requestor_8_status_fs), .io_requestor_8_status_mpp (_ptw_io_requestor_8_status_mpp), .io_requestor_8_status_spp (_ptw_io_requestor_8_status_spp), .io_requestor_8_status_mpie (_ptw_io_requestor_8_status_mpie), .io_requestor_8_status_spie (_ptw_io_requestor_8_status_spie), .io_requestor_8_status_mie (_ptw_io_requestor_8_status_mie), .io_requestor_8_status_sie (_ptw_io_requestor_8_status_sie), .io_requestor_8_hstatus_spvp (_ptw_io_requestor_8_hstatus_spvp), .io_requestor_8_hstatus_spv (_ptw_io_requestor_8_hstatus_spv), .io_requestor_8_hstatus_gva (_ptw_io_requestor_8_hstatus_gva), .io_requestor_8_gstatus_debug (_ptw_io_requestor_8_gstatus_debug), .io_requestor_8_gstatus_cease (_ptw_io_requestor_8_gstatus_cease), .io_requestor_8_gstatus_wfi (_ptw_io_requestor_8_gstatus_wfi), .io_requestor_8_gstatus_isa (_ptw_io_requestor_8_gstatus_isa), .io_requestor_8_gstatus_dprv (_ptw_io_requestor_8_gstatus_dprv), .io_requestor_8_gstatus_dv (_ptw_io_requestor_8_gstatus_dv), .io_requestor_8_gstatus_prv (_ptw_io_requestor_8_gstatus_prv), .io_requestor_8_gstatus_v (_ptw_io_requestor_8_gstatus_v), .io_requestor_8_gstatus_zero2 (_ptw_io_requestor_8_gstatus_zero2), .io_requestor_8_gstatus_mpv (_ptw_io_requestor_8_gstatus_mpv), .io_requestor_8_gstatus_gva (_ptw_io_requestor_8_gstatus_gva), .io_requestor_8_gstatus_mbe (_ptw_io_requestor_8_gstatus_mbe), .io_requestor_8_gstatus_sbe (_ptw_io_requestor_8_gstatus_sbe), .io_requestor_8_gstatus_sxl (_ptw_io_requestor_8_gstatus_sxl), .io_requestor_8_gstatus_zero1 (_ptw_io_requestor_8_gstatus_zero1), .io_requestor_8_gstatus_tsr (_ptw_io_requestor_8_gstatus_tsr), .io_requestor_8_gstatus_tw (_ptw_io_requestor_8_gstatus_tw), .io_requestor_8_gstatus_tvm (_ptw_io_requestor_8_gstatus_tvm), .io_requestor_8_gstatus_mxr (_ptw_io_requestor_8_gstatus_mxr), .io_requestor_8_gstatus_sum (_ptw_io_requestor_8_gstatus_sum), .io_requestor_8_gstatus_mprv (_ptw_io_requestor_8_gstatus_mprv), .io_requestor_8_gstatus_fs (_ptw_io_requestor_8_gstatus_fs), .io_requestor_8_gstatus_mpp (_ptw_io_requestor_8_gstatus_mpp), .io_requestor_8_gstatus_vs (_ptw_io_requestor_8_gstatus_vs), .io_requestor_8_gstatus_spp (_ptw_io_requestor_8_gstatus_spp), .io_requestor_8_gstatus_mpie (_ptw_io_requestor_8_gstatus_mpie), .io_requestor_8_gstatus_ube (_ptw_io_requestor_8_gstatus_ube), .io_requestor_8_gstatus_spie (_ptw_io_requestor_8_gstatus_spie), .io_requestor_8_gstatus_upie (_ptw_io_requestor_8_gstatus_upie), .io_requestor_8_gstatus_mie (_ptw_io_requestor_8_gstatus_mie), .io_requestor_8_gstatus_hie (_ptw_io_requestor_8_gstatus_hie), .io_requestor_8_gstatus_sie (_ptw_io_requestor_8_gstatus_sie), .io_requestor_8_gstatus_uie (_ptw_io_requestor_8_gstatus_uie), .io_requestor_8_pmp_0_cfg_l (_ptw_io_requestor_8_pmp_0_cfg_l), .io_requestor_8_pmp_0_cfg_a (_ptw_io_requestor_8_pmp_0_cfg_a), .io_requestor_8_pmp_0_cfg_x (_ptw_io_requestor_8_pmp_0_cfg_x), .io_requestor_8_pmp_0_cfg_w (_ptw_io_requestor_8_pmp_0_cfg_w), .io_requestor_8_pmp_0_cfg_r (_ptw_io_requestor_8_pmp_0_cfg_r), .io_requestor_8_pmp_0_addr (_ptw_io_requestor_8_pmp_0_addr), .io_requestor_8_pmp_0_mask (_ptw_io_requestor_8_pmp_0_mask), .io_requestor_8_pmp_1_cfg_l (_ptw_io_requestor_8_pmp_1_cfg_l), .io_requestor_8_pmp_1_cfg_a (_ptw_io_requestor_8_pmp_1_cfg_a), .io_requestor_8_pmp_1_cfg_x (_ptw_io_requestor_8_pmp_1_cfg_x), .io_requestor_8_pmp_1_cfg_w (_ptw_io_requestor_8_pmp_1_cfg_w), .io_requestor_8_pmp_1_cfg_r (_ptw_io_requestor_8_pmp_1_cfg_r), .io_requestor_8_pmp_1_addr (_ptw_io_requestor_8_pmp_1_addr), .io_requestor_8_pmp_1_mask (_ptw_io_requestor_8_pmp_1_mask), .io_requestor_8_pmp_2_cfg_l (_ptw_io_requestor_8_pmp_2_cfg_l), .io_requestor_8_pmp_2_cfg_a (_ptw_io_requestor_8_pmp_2_cfg_a), .io_requestor_8_pmp_2_cfg_x (_ptw_io_requestor_8_pmp_2_cfg_x), .io_requestor_8_pmp_2_cfg_w (_ptw_io_requestor_8_pmp_2_cfg_w), .io_requestor_8_pmp_2_cfg_r (_ptw_io_requestor_8_pmp_2_cfg_r), .io_requestor_8_pmp_2_addr (_ptw_io_requestor_8_pmp_2_addr), .io_requestor_8_pmp_2_mask (_ptw_io_requestor_8_pmp_2_mask), .io_requestor_8_pmp_3_cfg_l (_ptw_io_requestor_8_pmp_3_cfg_l), .io_requestor_8_pmp_3_cfg_a (_ptw_io_requestor_8_pmp_3_cfg_a), .io_requestor_8_pmp_3_cfg_x (_ptw_io_requestor_8_pmp_3_cfg_x), .io_requestor_8_pmp_3_cfg_w (_ptw_io_requestor_8_pmp_3_cfg_w), .io_requestor_8_pmp_3_cfg_r (_ptw_io_requestor_8_pmp_3_cfg_r), .io_requestor_8_pmp_3_addr (_ptw_io_requestor_8_pmp_3_addr), .io_requestor_8_pmp_3_mask (_ptw_io_requestor_8_pmp_3_mask), .io_requestor_8_pmp_4_cfg_l (_ptw_io_requestor_8_pmp_4_cfg_l), .io_requestor_8_pmp_4_cfg_a (_ptw_io_requestor_8_pmp_4_cfg_a), .io_requestor_8_pmp_4_cfg_x (_ptw_io_requestor_8_pmp_4_cfg_x), .io_requestor_8_pmp_4_cfg_w (_ptw_io_requestor_8_pmp_4_cfg_w), .io_requestor_8_pmp_4_cfg_r (_ptw_io_requestor_8_pmp_4_cfg_r), .io_requestor_8_pmp_4_addr (_ptw_io_requestor_8_pmp_4_addr), .io_requestor_8_pmp_4_mask (_ptw_io_requestor_8_pmp_4_mask), .io_requestor_8_pmp_5_cfg_l (_ptw_io_requestor_8_pmp_5_cfg_l), .io_requestor_8_pmp_5_cfg_a (_ptw_io_requestor_8_pmp_5_cfg_a), .io_requestor_8_pmp_5_cfg_x (_ptw_io_requestor_8_pmp_5_cfg_x), .io_requestor_8_pmp_5_cfg_w (_ptw_io_requestor_8_pmp_5_cfg_w), .io_requestor_8_pmp_5_cfg_r (_ptw_io_requestor_8_pmp_5_cfg_r), .io_requestor_8_pmp_5_addr (_ptw_io_requestor_8_pmp_5_addr), .io_requestor_8_pmp_5_mask (_ptw_io_requestor_8_pmp_5_mask), .io_requestor_8_pmp_6_cfg_l (_ptw_io_requestor_8_pmp_6_cfg_l), .io_requestor_8_pmp_6_cfg_a (_ptw_io_requestor_8_pmp_6_cfg_a), .io_requestor_8_pmp_6_cfg_x (_ptw_io_requestor_8_pmp_6_cfg_x), .io_requestor_8_pmp_6_cfg_w (_ptw_io_requestor_8_pmp_6_cfg_w), .io_requestor_8_pmp_6_cfg_r (_ptw_io_requestor_8_pmp_6_cfg_r), .io_requestor_8_pmp_6_addr (_ptw_io_requestor_8_pmp_6_addr), .io_requestor_8_pmp_6_mask (_ptw_io_requestor_8_pmp_6_mask), .io_requestor_8_pmp_7_cfg_l (_ptw_io_requestor_8_pmp_7_cfg_l), .io_requestor_8_pmp_7_cfg_a (_ptw_io_requestor_8_pmp_7_cfg_a), .io_requestor_8_pmp_7_cfg_x (_ptw_io_requestor_8_pmp_7_cfg_x), .io_requestor_8_pmp_7_cfg_w (_ptw_io_requestor_8_pmp_7_cfg_w), .io_requestor_8_pmp_7_cfg_r (_ptw_io_requestor_8_pmp_7_cfg_r), .io_requestor_8_pmp_7_addr (_ptw_io_requestor_8_pmp_7_addr), .io_requestor_8_pmp_7_mask (_ptw_io_requestor_8_pmp_7_mask), .io_requestor_8_customCSRs_csrs_0_ren (_ptw_io_requestor_8_customCSRs_csrs_0_ren), .io_requestor_8_customCSRs_csrs_0_wen (_ptw_io_requestor_8_customCSRs_csrs_0_wen), .io_requestor_8_customCSRs_csrs_0_wdata (_ptw_io_requestor_8_customCSRs_csrs_0_wdata), .io_requestor_8_customCSRs_csrs_0_value (_ptw_io_requestor_8_customCSRs_csrs_0_value), .io_requestor_8_customCSRs_csrs_1_ren (_ptw_io_requestor_8_customCSRs_csrs_1_ren), .io_requestor_8_customCSRs_csrs_1_wen (_ptw_io_requestor_8_customCSRs_csrs_1_wen), .io_requestor_8_customCSRs_csrs_1_wdata (_ptw_io_requestor_8_customCSRs_csrs_1_wdata), .io_requestor_8_customCSRs_csrs_1_value (_ptw_io_requestor_8_customCSRs_csrs_1_value), .io_requestor_8_customCSRs_csrs_2_ren (_ptw_io_requestor_8_customCSRs_csrs_2_ren), .io_requestor_8_customCSRs_csrs_2_wen (_ptw_io_requestor_8_customCSRs_csrs_2_wen), .io_requestor_8_customCSRs_csrs_2_wdata (_ptw_io_requestor_8_customCSRs_csrs_2_wdata), .io_requestor_8_customCSRs_csrs_2_value (_ptw_io_requestor_8_customCSRs_csrs_2_value), .io_requestor_8_customCSRs_csrs_3_ren (_ptw_io_requestor_8_customCSRs_csrs_3_ren), .io_requestor_8_customCSRs_csrs_3_wen (_ptw_io_requestor_8_customCSRs_csrs_3_wen), .io_requestor_8_customCSRs_csrs_3_wdata (_ptw_io_requestor_8_customCSRs_csrs_3_wdata), .io_requestor_8_customCSRs_csrs_3_value (_ptw_io_requestor_8_customCSRs_csrs_3_value), .io_requestor_9_req_ready (_ptw_io_requestor_9_req_ready), .io_requestor_9_req_valid (_zstd_compressor_io_ptw_9_req_valid), // @[Configs.scala:62:39] .io_requestor_9_req_bits_bits_addr (_zstd_compressor_io_ptw_9_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_9_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_9_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_9_resp_valid (_ptw_io_requestor_9_resp_valid), .io_requestor_9_resp_bits_ae_ptw (_ptw_io_requestor_9_resp_bits_ae_ptw), .io_requestor_9_resp_bits_ae_final (_ptw_io_requestor_9_resp_bits_ae_final), .io_requestor_9_resp_bits_pf (_ptw_io_requestor_9_resp_bits_pf), .io_requestor_9_resp_bits_gf (_ptw_io_requestor_9_resp_bits_gf), .io_requestor_9_resp_bits_hr (_ptw_io_requestor_9_resp_bits_hr), .io_requestor_9_resp_bits_hw (_ptw_io_requestor_9_resp_bits_hw), .io_requestor_9_resp_bits_hx (_ptw_io_requestor_9_resp_bits_hx), .io_requestor_9_resp_bits_pte_reserved_for_future (_ptw_io_requestor_9_resp_bits_pte_reserved_for_future), .io_requestor_9_resp_bits_pte_ppn (_ptw_io_requestor_9_resp_bits_pte_ppn), .io_requestor_9_resp_bits_pte_reserved_for_software (_ptw_io_requestor_9_resp_bits_pte_reserved_for_software), .io_requestor_9_resp_bits_pte_d (_ptw_io_requestor_9_resp_bits_pte_d), .io_requestor_9_resp_bits_pte_a (_ptw_io_requestor_9_resp_bits_pte_a), .io_requestor_9_resp_bits_pte_g (_ptw_io_requestor_9_resp_bits_pte_g), .io_requestor_9_resp_bits_pte_u (_ptw_io_requestor_9_resp_bits_pte_u), .io_requestor_9_resp_bits_pte_x (_ptw_io_requestor_9_resp_bits_pte_x), .io_requestor_9_resp_bits_pte_w (_ptw_io_requestor_9_resp_bits_pte_w), .io_requestor_9_resp_bits_pte_r (_ptw_io_requestor_9_resp_bits_pte_r), .io_requestor_9_resp_bits_pte_v (_ptw_io_requestor_9_resp_bits_pte_v), .io_requestor_9_resp_bits_level (_ptw_io_requestor_9_resp_bits_level), .io_requestor_9_resp_bits_homogeneous (_ptw_io_requestor_9_resp_bits_homogeneous), .io_requestor_9_resp_bits_gpa_valid (_ptw_io_requestor_9_resp_bits_gpa_valid), .io_requestor_9_resp_bits_gpa_bits (_ptw_io_requestor_9_resp_bits_gpa_bits), .io_requestor_9_resp_bits_gpa_is_pte (_ptw_io_requestor_9_resp_bits_gpa_is_pte), .io_requestor_9_ptbr_mode (_ptw_io_requestor_9_ptbr_mode), .io_requestor_9_ptbr_ppn (_ptw_io_requestor_9_ptbr_ppn), .io_requestor_9_status_debug (_ptw_io_requestor_9_status_debug), .io_requestor_9_status_cease (_ptw_io_requestor_9_status_cease), .io_requestor_9_status_wfi (_ptw_io_requestor_9_status_wfi), .io_requestor_9_status_isa (_ptw_io_requestor_9_status_isa), .io_requestor_9_status_dprv (_ptw_io_requestor_9_status_dprv), .io_requestor_9_status_dv (_ptw_io_requestor_9_status_dv), .io_requestor_9_status_prv (_ptw_io_requestor_9_status_prv), .io_requestor_9_status_v (_ptw_io_requestor_9_status_v), .io_requestor_9_status_mpv (_ptw_io_requestor_9_status_mpv), .io_requestor_9_status_gva (_ptw_io_requestor_9_status_gva), .io_requestor_9_status_tsr (_ptw_io_requestor_9_status_tsr), .io_requestor_9_status_tw (_ptw_io_requestor_9_status_tw), .io_requestor_9_status_tvm (_ptw_io_requestor_9_status_tvm), .io_requestor_9_status_mxr (_ptw_io_requestor_9_status_mxr), .io_requestor_9_status_sum (_ptw_io_requestor_9_status_sum), .io_requestor_9_status_mprv (_ptw_io_requestor_9_status_mprv), .io_requestor_9_status_fs (_ptw_io_requestor_9_status_fs), .io_requestor_9_status_mpp (_ptw_io_requestor_9_status_mpp), .io_requestor_9_status_spp (_ptw_io_requestor_9_status_spp), .io_requestor_9_status_mpie (_ptw_io_requestor_9_status_mpie), .io_requestor_9_status_spie (_ptw_io_requestor_9_status_spie), .io_requestor_9_status_mie (_ptw_io_requestor_9_status_mie), .io_requestor_9_status_sie (_ptw_io_requestor_9_status_sie), .io_requestor_9_hstatus_spvp (_ptw_io_requestor_9_hstatus_spvp), .io_requestor_9_hstatus_spv (_ptw_io_requestor_9_hstatus_spv), .io_requestor_9_hstatus_gva (_ptw_io_requestor_9_hstatus_gva), .io_requestor_9_gstatus_debug (_ptw_io_requestor_9_gstatus_debug), .io_requestor_9_gstatus_cease (_ptw_io_requestor_9_gstatus_cease), .io_requestor_9_gstatus_wfi (_ptw_io_requestor_9_gstatus_wfi), .io_requestor_9_gstatus_isa (_ptw_io_requestor_9_gstatus_isa), .io_requestor_9_gstatus_dprv (_ptw_io_requestor_9_gstatus_dprv), .io_requestor_9_gstatus_dv (_ptw_io_requestor_9_gstatus_dv), .io_requestor_9_gstatus_prv (_ptw_io_requestor_9_gstatus_prv), .io_requestor_9_gstatus_v (_ptw_io_requestor_9_gstatus_v), .io_requestor_9_gstatus_zero2 (_ptw_io_requestor_9_gstatus_zero2), .io_requestor_9_gstatus_mpv (_ptw_io_requestor_9_gstatus_mpv), .io_requestor_9_gstatus_gva (_ptw_io_requestor_9_gstatus_gva), .io_requestor_9_gstatus_mbe (_ptw_io_requestor_9_gstatus_mbe), .io_requestor_9_gstatus_sbe (_ptw_io_requestor_9_gstatus_sbe), .io_requestor_9_gstatus_sxl (_ptw_io_requestor_9_gstatus_sxl), .io_requestor_9_gstatus_zero1 (_ptw_io_requestor_9_gstatus_zero1), .io_requestor_9_gstatus_tsr (_ptw_io_requestor_9_gstatus_tsr), .io_requestor_9_gstatus_tw (_ptw_io_requestor_9_gstatus_tw), .io_requestor_9_gstatus_tvm (_ptw_io_requestor_9_gstatus_tvm), .io_requestor_9_gstatus_mxr (_ptw_io_requestor_9_gstatus_mxr), .io_requestor_9_gstatus_sum (_ptw_io_requestor_9_gstatus_sum), .io_requestor_9_gstatus_mprv (_ptw_io_requestor_9_gstatus_mprv), .io_requestor_9_gstatus_fs (_ptw_io_requestor_9_gstatus_fs), .io_requestor_9_gstatus_mpp (_ptw_io_requestor_9_gstatus_mpp), .io_requestor_9_gstatus_vs (_ptw_io_requestor_9_gstatus_vs), .io_requestor_9_gstatus_spp (_ptw_io_requestor_9_gstatus_spp), .io_requestor_9_gstatus_mpie (_ptw_io_requestor_9_gstatus_mpie), .io_requestor_9_gstatus_ube (_ptw_io_requestor_9_gstatus_ube), .io_requestor_9_gstatus_spie (_ptw_io_requestor_9_gstatus_spie), .io_requestor_9_gstatus_upie (_ptw_io_requestor_9_gstatus_upie), .io_requestor_9_gstatus_mie (_ptw_io_requestor_9_gstatus_mie), .io_requestor_9_gstatus_hie (_ptw_io_requestor_9_gstatus_hie), .io_requestor_9_gstatus_sie (_ptw_io_requestor_9_gstatus_sie), .io_requestor_9_gstatus_uie (_ptw_io_requestor_9_gstatus_uie), .io_requestor_9_pmp_0_cfg_l (_ptw_io_requestor_9_pmp_0_cfg_l), .io_requestor_9_pmp_0_cfg_a (_ptw_io_requestor_9_pmp_0_cfg_a), .io_requestor_9_pmp_0_cfg_x (_ptw_io_requestor_9_pmp_0_cfg_x), .io_requestor_9_pmp_0_cfg_w (_ptw_io_requestor_9_pmp_0_cfg_w), .io_requestor_9_pmp_0_cfg_r (_ptw_io_requestor_9_pmp_0_cfg_r), .io_requestor_9_pmp_0_addr (_ptw_io_requestor_9_pmp_0_addr), .io_requestor_9_pmp_0_mask (_ptw_io_requestor_9_pmp_0_mask), .io_requestor_9_pmp_1_cfg_l (_ptw_io_requestor_9_pmp_1_cfg_l), .io_requestor_9_pmp_1_cfg_a (_ptw_io_requestor_9_pmp_1_cfg_a), .io_requestor_9_pmp_1_cfg_x (_ptw_io_requestor_9_pmp_1_cfg_x), .io_requestor_9_pmp_1_cfg_w (_ptw_io_requestor_9_pmp_1_cfg_w), .io_requestor_9_pmp_1_cfg_r (_ptw_io_requestor_9_pmp_1_cfg_r), .io_requestor_9_pmp_1_addr (_ptw_io_requestor_9_pmp_1_addr), .io_requestor_9_pmp_1_mask (_ptw_io_requestor_9_pmp_1_mask), .io_requestor_9_pmp_2_cfg_l (_ptw_io_requestor_9_pmp_2_cfg_l), .io_requestor_9_pmp_2_cfg_a (_ptw_io_requestor_9_pmp_2_cfg_a), .io_requestor_9_pmp_2_cfg_x (_ptw_io_requestor_9_pmp_2_cfg_x), .io_requestor_9_pmp_2_cfg_w (_ptw_io_requestor_9_pmp_2_cfg_w), .io_requestor_9_pmp_2_cfg_r (_ptw_io_requestor_9_pmp_2_cfg_r), .io_requestor_9_pmp_2_addr (_ptw_io_requestor_9_pmp_2_addr), .io_requestor_9_pmp_2_mask (_ptw_io_requestor_9_pmp_2_mask), .io_requestor_9_pmp_3_cfg_l (_ptw_io_requestor_9_pmp_3_cfg_l), .io_requestor_9_pmp_3_cfg_a (_ptw_io_requestor_9_pmp_3_cfg_a), .io_requestor_9_pmp_3_cfg_x (_ptw_io_requestor_9_pmp_3_cfg_x), .io_requestor_9_pmp_3_cfg_w (_ptw_io_requestor_9_pmp_3_cfg_w), .io_requestor_9_pmp_3_cfg_r (_ptw_io_requestor_9_pmp_3_cfg_r), .io_requestor_9_pmp_3_addr (_ptw_io_requestor_9_pmp_3_addr), .io_requestor_9_pmp_3_mask (_ptw_io_requestor_9_pmp_3_mask), .io_requestor_9_pmp_4_cfg_l (_ptw_io_requestor_9_pmp_4_cfg_l), .io_requestor_9_pmp_4_cfg_a (_ptw_io_requestor_9_pmp_4_cfg_a), .io_requestor_9_pmp_4_cfg_x (_ptw_io_requestor_9_pmp_4_cfg_x), .io_requestor_9_pmp_4_cfg_w (_ptw_io_requestor_9_pmp_4_cfg_w), .io_requestor_9_pmp_4_cfg_r (_ptw_io_requestor_9_pmp_4_cfg_r), .io_requestor_9_pmp_4_addr (_ptw_io_requestor_9_pmp_4_addr), .io_requestor_9_pmp_4_mask (_ptw_io_requestor_9_pmp_4_mask), .io_requestor_9_pmp_5_cfg_l (_ptw_io_requestor_9_pmp_5_cfg_l), .io_requestor_9_pmp_5_cfg_a (_ptw_io_requestor_9_pmp_5_cfg_a), .io_requestor_9_pmp_5_cfg_x (_ptw_io_requestor_9_pmp_5_cfg_x), .io_requestor_9_pmp_5_cfg_w (_ptw_io_requestor_9_pmp_5_cfg_w), .io_requestor_9_pmp_5_cfg_r (_ptw_io_requestor_9_pmp_5_cfg_r), .io_requestor_9_pmp_5_addr (_ptw_io_requestor_9_pmp_5_addr), .io_requestor_9_pmp_5_mask (_ptw_io_requestor_9_pmp_5_mask), .io_requestor_9_pmp_6_cfg_l (_ptw_io_requestor_9_pmp_6_cfg_l), .io_requestor_9_pmp_6_cfg_a (_ptw_io_requestor_9_pmp_6_cfg_a), .io_requestor_9_pmp_6_cfg_x (_ptw_io_requestor_9_pmp_6_cfg_x), .io_requestor_9_pmp_6_cfg_w (_ptw_io_requestor_9_pmp_6_cfg_w), .io_requestor_9_pmp_6_cfg_r (_ptw_io_requestor_9_pmp_6_cfg_r), .io_requestor_9_pmp_6_addr (_ptw_io_requestor_9_pmp_6_addr), .io_requestor_9_pmp_6_mask (_ptw_io_requestor_9_pmp_6_mask), .io_requestor_9_pmp_7_cfg_l (_ptw_io_requestor_9_pmp_7_cfg_l), .io_requestor_9_pmp_7_cfg_a (_ptw_io_requestor_9_pmp_7_cfg_a), .io_requestor_9_pmp_7_cfg_x (_ptw_io_requestor_9_pmp_7_cfg_x), .io_requestor_9_pmp_7_cfg_w (_ptw_io_requestor_9_pmp_7_cfg_w), .io_requestor_9_pmp_7_cfg_r (_ptw_io_requestor_9_pmp_7_cfg_r), .io_requestor_9_pmp_7_addr (_ptw_io_requestor_9_pmp_7_addr), .io_requestor_9_pmp_7_mask (_ptw_io_requestor_9_pmp_7_mask), .io_requestor_9_customCSRs_csrs_0_ren (_ptw_io_requestor_9_customCSRs_csrs_0_ren), .io_requestor_9_customCSRs_csrs_0_wen (_ptw_io_requestor_9_customCSRs_csrs_0_wen), .io_requestor_9_customCSRs_csrs_0_wdata (_ptw_io_requestor_9_customCSRs_csrs_0_wdata), .io_requestor_9_customCSRs_csrs_0_value (_ptw_io_requestor_9_customCSRs_csrs_0_value), .io_requestor_9_customCSRs_csrs_1_ren (_ptw_io_requestor_9_customCSRs_csrs_1_ren), .io_requestor_9_customCSRs_csrs_1_wen (_ptw_io_requestor_9_customCSRs_csrs_1_wen), .io_requestor_9_customCSRs_csrs_1_wdata (_ptw_io_requestor_9_customCSRs_csrs_1_wdata), .io_requestor_9_customCSRs_csrs_1_value (_ptw_io_requestor_9_customCSRs_csrs_1_value), .io_requestor_9_customCSRs_csrs_2_ren (_ptw_io_requestor_9_customCSRs_csrs_2_ren), .io_requestor_9_customCSRs_csrs_2_wen (_ptw_io_requestor_9_customCSRs_csrs_2_wen), .io_requestor_9_customCSRs_csrs_2_wdata (_ptw_io_requestor_9_customCSRs_csrs_2_wdata), .io_requestor_9_customCSRs_csrs_2_value (_ptw_io_requestor_9_customCSRs_csrs_2_value), .io_requestor_9_customCSRs_csrs_3_ren (_ptw_io_requestor_9_customCSRs_csrs_3_ren), .io_requestor_9_customCSRs_csrs_3_wen (_ptw_io_requestor_9_customCSRs_csrs_3_wen), .io_requestor_9_customCSRs_csrs_3_wdata (_ptw_io_requestor_9_customCSRs_csrs_3_wdata), .io_requestor_9_customCSRs_csrs_3_value (_ptw_io_requestor_9_customCSRs_csrs_3_value), .io_requestor_10_req_ready (_ptw_io_requestor_10_req_ready), .io_requestor_10_req_valid (_zstd_compressor_io_ptw_10_req_valid), // @[Configs.scala:62:39] .io_requestor_10_req_bits_bits_addr (_zstd_compressor_io_ptw_10_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_10_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_10_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_10_resp_valid (_ptw_io_requestor_10_resp_valid), .io_requestor_10_resp_bits_ae_ptw (_ptw_io_requestor_10_resp_bits_ae_ptw), .io_requestor_10_resp_bits_ae_final (_ptw_io_requestor_10_resp_bits_ae_final), .io_requestor_10_resp_bits_pf (_ptw_io_requestor_10_resp_bits_pf), .io_requestor_10_resp_bits_gf (_ptw_io_requestor_10_resp_bits_gf), .io_requestor_10_resp_bits_hr (_ptw_io_requestor_10_resp_bits_hr), .io_requestor_10_resp_bits_hw (_ptw_io_requestor_10_resp_bits_hw), .io_requestor_10_resp_bits_hx (_ptw_io_requestor_10_resp_bits_hx), .io_requestor_10_resp_bits_pte_reserved_for_future (_ptw_io_requestor_10_resp_bits_pte_reserved_for_future), .io_requestor_10_resp_bits_pte_ppn (_ptw_io_requestor_10_resp_bits_pte_ppn), .io_requestor_10_resp_bits_pte_reserved_for_software (_ptw_io_requestor_10_resp_bits_pte_reserved_for_software), .io_requestor_10_resp_bits_pte_d (_ptw_io_requestor_10_resp_bits_pte_d), .io_requestor_10_resp_bits_pte_a (_ptw_io_requestor_10_resp_bits_pte_a), .io_requestor_10_resp_bits_pte_g (_ptw_io_requestor_10_resp_bits_pte_g), .io_requestor_10_resp_bits_pte_u (_ptw_io_requestor_10_resp_bits_pte_u), .io_requestor_10_resp_bits_pte_x (_ptw_io_requestor_10_resp_bits_pte_x), .io_requestor_10_resp_bits_pte_w (_ptw_io_requestor_10_resp_bits_pte_w), .io_requestor_10_resp_bits_pte_r (_ptw_io_requestor_10_resp_bits_pte_r), .io_requestor_10_resp_bits_pte_v (_ptw_io_requestor_10_resp_bits_pte_v), .io_requestor_10_resp_bits_level (_ptw_io_requestor_10_resp_bits_level), .io_requestor_10_resp_bits_homogeneous (_ptw_io_requestor_10_resp_bits_homogeneous), .io_requestor_10_resp_bits_gpa_valid (_ptw_io_requestor_10_resp_bits_gpa_valid), .io_requestor_10_resp_bits_gpa_bits (_ptw_io_requestor_10_resp_bits_gpa_bits), .io_requestor_10_resp_bits_gpa_is_pte (_ptw_io_requestor_10_resp_bits_gpa_is_pte), .io_requestor_10_ptbr_mode (_ptw_io_requestor_10_ptbr_mode), .io_requestor_10_ptbr_ppn (_ptw_io_requestor_10_ptbr_ppn), .io_requestor_10_status_debug (_ptw_io_requestor_10_status_debug), .io_requestor_10_status_cease (_ptw_io_requestor_10_status_cease), .io_requestor_10_status_wfi (_ptw_io_requestor_10_status_wfi), .io_requestor_10_status_isa (_ptw_io_requestor_10_status_isa), .io_requestor_10_status_dprv (_ptw_io_requestor_10_status_dprv), .io_requestor_10_status_dv (_ptw_io_requestor_10_status_dv), .io_requestor_10_status_prv (_ptw_io_requestor_10_status_prv), .io_requestor_10_status_v (_ptw_io_requestor_10_status_v), .io_requestor_10_status_mpv (_ptw_io_requestor_10_status_mpv), .io_requestor_10_status_gva (_ptw_io_requestor_10_status_gva), .io_requestor_10_status_tsr (_ptw_io_requestor_10_status_tsr), .io_requestor_10_status_tw (_ptw_io_requestor_10_status_tw), .io_requestor_10_status_tvm (_ptw_io_requestor_10_status_tvm), .io_requestor_10_status_mxr (_ptw_io_requestor_10_status_mxr), .io_requestor_10_status_sum (_ptw_io_requestor_10_status_sum), .io_requestor_10_status_mprv (_ptw_io_requestor_10_status_mprv), .io_requestor_10_status_fs (_ptw_io_requestor_10_status_fs), .io_requestor_10_status_mpp (_ptw_io_requestor_10_status_mpp), .io_requestor_10_status_spp (_ptw_io_requestor_10_status_spp), .io_requestor_10_status_mpie (_ptw_io_requestor_10_status_mpie), .io_requestor_10_status_spie (_ptw_io_requestor_10_status_spie), .io_requestor_10_status_mie (_ptw_io_requestor_10_status_mie), .io_requestor_10_status_sie (_ptw_io_requestor_10_status_sie), .io_requestor_10_hstatus_spvp (_ptw_io_requestor_10_hstatus_spvp), .io_requestor_10_hstatus_spv (_ptw_io_requestor_10_hstatus_spv), .io_requestor_10_hstatus_gva (_ptw_io_requestor_10_hstatus_gva), .io_requestor_10_gstatus_debug (_ptw_io_requestor_10_gstatus_debug), .io_requestor_10_gstatus_cease (_ptw_io_requestor_10_gstatus_cease), .io_requestor_10_gstatus_wfi (_ptw_io_requestor_10_gstatus_wfi), .io_requestor_10_gstatus_isa (_ptw_io_requestor_10_gstatus_isa), .io_requestor_10_gstatus_dprv (_ptw_io_requestor_10_gstatus_dprv), .io_requestor_10_gstatus_dv (_ptw_io_requestor_10_gstatus_dv), .io_requestor_10_gstatus_prv (_ptw_io_requestor_10_gstatus_prv), .io_requestor_10_gstatus_v (_ptw_io_requestor_10_gstatus_v), .io_requestor_10_gstatus_zero2 (_ptw_io_requestor_10_gstatus_zero2), .io_requestor_10_gstatus_mpv (_ptw_io_requestor_10_gstatus_mpv), .io_requestor_10_gstatus_gva (_ptw_io_requestor_10_gstatus_gva), .io_requestor_10_gstatus_mbe (_ptw_io_requestor_10_gstatus_mbe), .io_requestor_10_gstatus_sbe (_ptw_io_requestor_10_gstatus_sbe), .io_requestor_10_gstatus_sxl (_ptw_io_requestor_10_gstatus_sxl), .io_requestor_10_gstatus_zero1 (_ptw_io_requestor_10_gstatus_zero1), .io_requestor_10_gstatus_tsr (_ptw_io_requestor_10_gstatus_tsr), .io_requestor_10_gstatus_tw (_ptw_io_requestor_10_gstatus_tw), .io_requestor_10_gstatus_tvm (_ptw_io_requestor_10_gstatus_tvm), .io_requestor_10_gstatus_mxr (_ptw_io_requestor_10_gstatus_mxr), .io_requestor_10_gstatus_sum (_ptw_io_requestor_10_gstatus_sum), .io_requestor_10_gstatus_mprv (_ptw_io_requestor_10_gstatus_mprv), .io_requestor_10_gstatus_fs (_ptw_io_requestor_10_gstatus_fs), .io_requestor_10_gstatus_mpp (_ptw_io_requestor_10_gstatus_mpp), .io_requestor_10_gstatus_vs (_ptw_io_requestor_10_gstatus_vs), .io_requestor_10_gstatus_spp (_ptw_io_requestor_10_gstatus_spp), .io_requestor_10_gstatus_mpie (_ptw_io_requestor_10_gstatus_mpie), .io_requestor_10_gstatus_ube (_ptw_io_requestor_10_gstatus_ube), .io_requestor_10_gstatus_spie (_ptw_io_requestor_10_gstatus_spie), .io_requestor_10_gstatus_upie (_ptw_io_requestor_10_gstatus_upie), .io_requestor_10_gstatus_mie (_ptw_io_requestor_10_gstatus_mie), .io_requestor_10_gstatus_hie (_ptw_io_requestor_10_gstatus_hie), .io_requestor_10_gstatus_sie (_ptw_io_requestor_10_gstatus_sie), .io_requestor_10_gstatus_uie (_ptw_io_requestor_10_gstatus_uie), .io_requestor_10_pmp_0_cfg_l (_ptw_io_requestor_10_pmp_0_cfg_l), .io_requestor_10_pmp_0_cfg_a (_ptw_io_requestor_10_pmp_0_cfg_a), .io_requestor_10_pmp_0_cfg_x (_ptw_io_requestor_10_pmp_0_cfg_x), .io_requestor_10_pmp_0_cfg_w (_ptw_io_requestor_10_pmp_0_cfg_w), .io_requestor_10_pmp_0_cfg_r (_ptw_io_requestor_10_pmp_0_cfg_r), .io_requestor_10_pmp_0_addr (_ptw_io_requestor_10_pmp_0_addr), .io_requestor_10_pmp_0_mask (_ptw_io_requestor_10_pmp_0_mask), .io_requestor_10_pmp_1_cfg_l (_ptw_io_requestor_10_pmp_1_cfg_l), .io_requestor_10_pmp_1_cfg_a (_ptw_io_requestor_10_pmp_1_cfg_a), .io_requestor_10_pmp_1_cfg_x (_ptw_io_requestor_10_pmp_1_cfg_x), .io_requestor_10_pmp_1_cfg_w (_ptw_io_requestor_10_pmp_1_cfg_w), .io_requestor_10_pmp_1_cfg_r (_ptw_io_requestor_10_pmp_1_cfg_r), .io_requestor_10_pmp_1_addr (_ptw_io_requestor_10_pmp_1_addr), .io_requestor_10_pmp_1_mask (_ptw_io_requestor_10_pmp_1_mask), .io_requestor_10_pmp_2_cfg_l (_ptw_io_requestor_10_pmp_2_cfg_l), .io_requestor_10_pmp_2_cfg_a (_ptw_io_requestor_10_pmp_2_cfg_a), .io_requestor_10_pmp_2_cfg_x (_ptw_io_requestor_10_pmp_2_cfg_x), .io_requestor_10_pmp_2_cfg_w (_ptw_io_requestor_10_pmp_2_cfg_w), .io_requestor_10_pmp_2_cfg_r (_ptw_io_requestor_10_pmp_2_cfg_r), .io_requestor_10_pmp_2_addr (_ptw_io_requestor_10_pmp_2_addr), .io_requestor_10_pmp_2_mask (_ptw_io_requestor_10_pmp_2_mask), .io_requestor_10_pmp_3_cfg_l (_ptw_io_requestor_10_pmp_3_cfg_l), .io_requestor_10_pmp_3_cfg_a (_ptw_io_requestor_10_pmp_3_cfg_a), .io_requestor_10_pmp_3_cfg_x (_ptw_io_requestor_10_pmp_3_cfg_x), .io_requestor_10_pmp_3_cfg_w (_ptw_io_requestor_10_pmp_3_cfg_w), .io_requestor_10_pmp_3_cfg_r (_ptw_io_requestor_10_pmp_3_cfg_r), .io_requestor_10_pmp_3_addr (_ptw_io_requestor_10_pmp_3_addr), .io_requestor_10_pmp_3_mask (_ptw_io_requestor_10_pmp_3_mask), .io_requestor_10_pmp_4_cfg_l (_ptw_io_requestor_10_pmp_4_cfg_l), .io_requestor_10_pmp_4_cfg_a (_ptw_io_requestor_10_pmp_4_cfg_a), .io_requestor_10_pmp_4_cfg_x (_ptw_io_requestor_10_pmp_4_cfg_x), .io_requestor_10_pmp_4_cfg_w (_ptw_io_requestor_10_pmp_4_cfg_w), .io_requestor_10_pmp_4_cfg_r (_ptw_io_requestor_10_pmp_4_cfg_r), .io_requestor_10_pmp_4_addr (_ptw_io_requestor_10_pmp_4_addr), .io_requestor_10_pmp_4_mask (_ptw_io_requestor_10_pmp_4_mask), .io_requestor_10_pmp_5_cfg_l (_ptw_io_requestor_10_pmp_5_cfg_l), .io_requestor_10_pmp_5_cfg_a (_ptw_io_requestor_10_pmp_5_cfg_a), .io_requestor_10_pmp_5_cfg_x (_ptw_io_requestor_10_pmp_5_cfg_x), .io_requestor_10_pmp_5_cfg_w (_ptw_io_requestor_10_pmp_5_cfg_w), .io_requestor_10_pmp_5_cfg_r (_ptw_io_requestor_10_pmp_5_cfg_r), .io_requestor_10_pmp_5_addr (_ptw_io_requestor_10_pmp_5_addr), .io_requestor_10_pmp_5_mask (_ptw_io_requestor_10_pmp_5_mask), .io_requestor_10_pmp_6_cfg_l (_ptw_io_requestor_10_pmp_6_cfg_l), .io_requestor_10_pmp_6_cfg_a (_ptw_io_requestor_10_pmp_6_cfg_a), .io_requestor_10_pmp_6_cfg_x (_ptw_io_requestor_10_pmp_6_cfg_x), .io_requestor_10_pmp_6_cfg_w (_ptw_io_requestor_10_pmp_6_cfg_w), .io_requestor_10_pmp_6_cfg_r (_ptw_io_requestor_10_pmp_6_cfg_r), .io_requestor_10_pmp_6_addr (_ptw_io_requestor_10_pmp_6_addr), .io_requestor_10_pmp_6_mask (_ptw_io_requestor_10_pmp_6_mask), .io_requestor_10_pmp_7_cfg_l (_ptw_io_requestor_10_pmp_7_cfg_l), .io_requestor_10_pmp_7_cfg_a (_ptw_io_requestor_10_pmp_7_cfg_a), .io_requestor_10_pmp_7_cfg_x (_ptw_io_requestor_10_pmp_7_cfg_x), .io_requestor_10_pmp_7_cfg_w (_ptw_io_requestor_10_pmp_7_cfg_w), .io_requestor_10_pmp_7_cfg_r (_ptw_io_requestor_10_pmp_7_cfg_r), .io_requestor_10_pmp_7_addr (_ptw_io_requestor_10_pmp_7_addr), .io_requestor_10_pmp_7_mask (_ptw_io_requestor_10_pmp_7_mask), .io_requestor_10_customCSRs_csrs_0_ren (_ptw_io_requestor_10_customCSRs_csrs_0_ren), .io_requestor_10_customCSRs_csrs_0_wen (_ptw_io_requestor_10_customCSRs_csrs_0_wen), .io_requestor_10_customCSRs_csrs_0_wdata (_ptw_io_requestor_10_customCSRs_csrs_0_wdata), .io_requestor_10_customCSRs_csrs_0_value (_ptw_io_requestor_10_customCSRs_csrs_0_value), .io_requestor_10_customCSRs_csrs_1_ren (_ptw_io_requestor_10_customCSRs_csrs_1_ren), .io_requestor_10_customCSRs_csrs_1_wen (_ptw_io_requestor_10_customCSRs_csrs_1_wen), .io_requestor_10_customCSRs_csrs_1_wdata (_ptw_io_requestor_10_customCSRs_csrs_1_wdata), .io_requestor_10_customCSRs_csrs_1_value (_ptw_io_requestor_10_customCSRs_csrs_1_value), .io_requestor_10_customCSRs_csrs_2_ren (_ptw_io_requestor_10_customCSRs_csrs_2_ren), .io_requestor_10_customCSRs_csrs_2_wen (_ptw_io_requestor_10_customCSRs_csrs_2_wen), .io_requestor_10_customCSRs_csrs_2_wdata (_ptw_io_requestor_10_customCSRs_csrs_2_wdata), .io_requestor_10_customCSRs_csrs_2_value (_ptw_io_requestor_10_customCSRs_csrs_2_value), .io_requestor_10_customCSRs_csrs_3_ren (_ptw_io_requestor_10_customCSRs_csrs_3_ren), .io_requestor_10_customCSRs_csrs_3_wen (_ptw_io_requestor_10_customCSRs_csrs_3_wen), .io_requestor_10_customCSRs_csrs_3_wdata (_ptw_io_requestor_10_customCSRs_csrs_3_wdata), .io_requestor_10_customCSRs_csrs_3_value (_ptw_io_requestor_10_customCSRs_csrs_3_value), .io_requestor_11_req_ready (_ptw_io_requestor_11_req_ready), .io_requestor_11_req_valid (_zstd_compressor_io_ptw_11_req_valid), // @[Configs.scala:62:39] .io_requestor_11_req_bits_bits_addr (_zstd_compressor_io_ptw_11_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_11_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_11_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_11_resp_valid (_ptw_io_requestor_11_resp_valid), .io_requestor_11_resp_bits_ae_ptw (_ptw_io_requestor_11_resp_bits_ae_ptw), .io_requestor_11_resp_bits_ae_final (_ptw_io_requestor_11_resp_bits_ae_final), .io_requestor_11_resp_bits_pf (_ptw_io_requestor_11_resp_bits_pf), .io_requestor_11_resp_bits_gf (_ptw_io_requestor_11_resp_bits_gf), .io_requestor_11_resp_bits_hr (_ptw_io_requestor_11_resp_bits_hr), .io_requestor_11_resp_bits_hw (_ptw_io_requestor_11_resp_bits_hw), .io_requestor_11_resp_bits_hx (_ptw_io_requestor_11_resp_bits_hx), .io_requestor_11_resp_bits_pte_reserved_for_future (_ptw_io_requestor_11_resp_bits_pte_reserved_for_future), .io_requestor_11_resp_bits_pte_ppn (_ptw_io_requestor_11_resp_bits_pte_ppn), .io_requestor_11_resp_bits_pte_reserved_for_software (_ptw_io_requestor_11_resp_bits_pte_reserved_for_software), .io_requestor_11_resp_bits_pte_d (_ptw_io_requestor_11_resp_bits_pte_d), .io_requestor_11_resp_bits_pte_a (_ptw_io_requestor_11_resp_bits_pte_a), .io_requestor_11_resp_bits_pte_g (_ptw_io_requestor_11_resp_bits_pte_g), .io_requestor_11_resp_bits_pte_u (_ptw_io_requestor_11_resp_bits_pte_u), .io_requestor_11_resp_bits_pte_x (_ptw_io_requestor_11_resp_bits_pte_x), .io_requestor_11_resp_bits_pte_w (_ptw_io_requestor_11_resp_bits_pte_w), .io_requestor_11_resp_bits_pte_r (_ptw_io_requestor_11_resp_bits_pte_r), .io_requestor_11_resp_bits_pte_v (_ptw_io_requestor_11_resp_bits_pte_v), .io_requestor_11_resp_bits_level (_ptw_io_requestor_11_resp_bits_level), .io_requestor_11_resp_bits_homogeneous (_ptw_io_requestor_11_resp_bits_homogeneous), .io_requestor_11_resp_bits_gpa_valid (_ptw_io_requestor_11_resp_bits_gpa_valid), .io_requestor_11_resp_bits_gpa_bits (_ptw_io_requestor_11_resp_bits_gpa_bits), .io_requestor_11_resp_bits_gpa_is_pte (_ptw_io_requestor_11_resp_bits_gpa_is_pte), .io_requestor_11_ptbr_mode (_ptw_io_requestor_11_ptbr_mode), .io_requestor_11_ptbr_ppn (_ptw_io_requestor_11_ptbr_ppn), .io_requestor_11_status_debug (_ptw_io_requestor_11_status_debug), .io_requestor_11_status_cease (_ptw_io_requestor_11_status_cease), .io_requestor_11_status_wfi (_ptw_io_requestor_11_status_wfi), .io_requestor_11_status_isa (_ptw_io_requestor_11_status_isa), .io_requestor_11_status_dprv (_ptw_io_requestor_11_status_dprv), .io_requestor_11_status_dv (_ptw_io_requestor_11_status_dv), .io_requestor_11_status_prv (_ptw_io_requestor_11_status_prv), .io_requestor_11_status_v (_ptw_io_requestor_11_status_v), .io_requestor_11_status_mpv (_ptw_io_requestor_11_status_mpv), .io_requestor_11_status_gva (_ptw_io_requestor_11_status_gva), .io_requestor_11_status_tsr (_ptw_io_requestor_11_status_tsr), .io_requestor_11_status_tw (_ptw_io_requestor_11_status_tw), .io_requestor_11_status_tvm (_ptw_io_requestor_11_status_tvm), .io_requestor_11_status_mxr (_ptw_io_requestor_11_status_mxr), .io_requestor_11_status_sum (_ptw_io_requestor_11_status_sum), .io_requestor_11_status_mprv (_ptw_io_requestor_11_status_mprv), .io_requestor_11_status_fs (_ptw_io_requestor_11_status_fs), .io_requestor_11_status_mpp (_ptw_io_requestor_11_status_mpp), .io_requestor_11_status_spp (_ptw_io_requestor_11_status_spp), .io_requestor_11_status_mpie (_ptw_io_requestor_11_status_mpie), .io_requestor_11_status_spie (_ptw_io_requestor_11_status_spie), .io_requestor_11_status_mie (_ptw_io_requestor_11_status_mie), .io_requestor_11_status_sie (_ptw_io_requestor_11_status_sie), .io_requestor_11_hstatus_spvp (_ptw_io_requestor_11_hstatus_spvp), .io_requestor_11_hstatus_spv (_ptw_io_requestor_11_hstatus_spv), .io_requestor_11_hstatus_gva (_ptw_io_requestor_11_hstatus_gva), .io_requestor_11_gstatus_debug (_ptw_io_requestor_11_gstatus_debug), .io_requestor_11_gstatus_cease (_ptw_io_requestor_11_gstatus_cease), .io_requestor_11_gstatus_wfi (_ptw_io_requestor_11_gstatus_wfi), .io_requestor_11_gstatus_isa (_ptw_io_requestor_11_gstatus_isa), .io_requestor_11_gstatus_dprv (_ptw_io_requestor_11_gstatus_dprv), .io_requestor_11_gstatus_dv (_ptw_io_requestor_11_gstatus_dv), .io_requestor_11_gstatus_prv (_ptw_io_requestor_11_gstatus_prv), .io_requestor_11_gstatus_v (_ptw_io_requestor_11_gstatus_v), .io_requestor_11_gstatus_zero2 (_ptw_io_requestor_11_gstatus_zero2), .io_requestor_11_gstatus_mpv (_ptw_io_requestor_11_gstatus_mpv), .io_requestor_11_gstatus_gva (_ptw_io_requestor_11_gstatus_gva), .io_requestor_11_gstatus_mbe (_ptw_io_requestor_11_gstatus_mbe), .io_requestor_11_gstatus_sbe (_ptw_io_requestor_11_gstatus_sbe), .io_requestor_11_gstatus_sxl (_ptw_io_requestor_11_gstatus_sxl), .io_requestor_11_gstatus_zero1 (_ptw_io_requestor_11_gstatus_zero1), .io_requestor_11_gstatus_tsr (_ptw_io_requestor_11_gstatus_tsr), .io_requestor_11_gstatus_tw (_ptw_io_requestor_11_gstatus_tw), .io_requestor_11_gstatus_tvm (_ptw_io_requestor_11_gstatus_tvm), .io_requestor_11_gstatus_mxr (_ptw_io_requestor_11_gstatus_mxr), .io_requestor_11_gstatus_sum (_ptw_io_requestor_11_gstatus_sum), .io_requestor_11_gstatus_mprv (_ptw_io_requestor_11_gstatus_mprv), .io_requestor_11_gstatus_fs (_ptw_io_requestor_11_gstatus_fs), .io_requestor_11_gstatus_mpp (_ptw_io_requestor_11_gstatus_mpp), .io_requestor_11_gstatus_vs (_ptw_io_requestor_11_gstatus_vs), .io_requestor_11_gstatus_spp (_ptw_io_requestor_11_gstatus_spp), .io_requestor_11_gstatus_mpie (_ptw_io_requestor_11_gstatus_mpie), .io_requestor_11_gstatus_ube (_ptw_io_requestor_11_gstatus_ube), .io_requestor_11_gstatus_spie (_ptw_io_requestor_11_gstatus_spie), .io_requestor_11_gstatus_upie (_ptw_io_requestor_11_gstatus_upie), .io_requestor_11_gstatus_mie (_ptw_io_requestor_11_gstatus_mie), .io_requestor_11_gstatus_hie (_ptw_io_requestor_11_gstatus_hie), .io_requestor_11_gstatus_sie (_ptw_io_requestor_11_gstatus_sie), .io_requestor_11_gstatus_uie (_ptw_io_requestor_11_gstatus_uie), .io_requestor_11_pmp_0_cfg_l (_ptw_io_requestor_11_pmp_0_cfg_l), .io_requestor_11_pmp_0_cfg_a (_ptw_io_requestor_11_pmp_0_cfg_a), .io_requestor_11_pmp_0_cfg_x (_ptw_io_requestor_11_pmp_0_cfg_x), .io_requestor_11_pmp_0_cfg_w (_ptw_io_requestor_11_pmp_0_cfg_w), .io_requestor_11_pmp_0_cfg_r (_ptw_io_requestor_11_pmp_0_cfg_r), .io_requestor_11_pmp_0_addr (_ptw_io_requestor_11_pmp_0_addr), .io_requestor_11_pmp_0_mask (_ptw_io_requestor_11_pmp_0_mask), .io_requestor_11_pmp_1_cfg_l (_ptw_io_requestor_11_pmp_1_cfg_l), .io_requestor_11_pmp_1_cfg_a (_ptw_io_requestor_11_pmp_1_cfg_a), .io_requestor_11_pmp_1_cfg_x (_ptw_io_requestor_11_pmp_1_cfg_x), .io_requestor_11_pmp_1_cfg_w (_ptw_io_requestor_11_pmp_1_cfg_w), .io_requestor_11_pmp_1_cfg_r (_ptw_io_requestor_11_pmp_1_cfg_r), .io_requestor_11_pmp_1_addr (_ptw_io_requestor_11_pmp_1_addr), .io_requestor_11_pmp_1_mask (_ptw_io_requestor_11_pmp_1_mask), .io_requestor_11_pmp_2_cfg_l (_ptw_io_requestor_11_pmp_2_cfg_l), .io_requestor_11_pmp_2_cfg_a (_ptw_io_requestor_11_pmp_2_cfg_a), .io_requestor_11_pmp_2_cfg_x (_ptw_io_requestor_11_pmp_2_cfg_x), .io_requestor_11_pmp_2_cfg_w (_ptw_io_requestor_11_pmp_2_cfg_w), .io_requestor_11_pmp_2_cfg_r (_ptw_io_requestor_11_pmp_2_cfg_r), .io_requestor_11_pmp_2_addr (_ptw_io_requestor_11_pmp_2_addr), .io_requestor_11_pmp_2_mask (_ptw_io_requestor_11_pmp_2_mask), .io_requestor_11_pmp_3_cfg_l (_ptw_io_requestor_11_pmp_3_cfg_l), .io_requestor_11_pmp_3_cfg_a (_ptw_io_requestor_11_pmp_3_cfg_a), .io_requestor_11_pmp_3_cfg_x (_ptw_io_requestor_11_pmp_3_cfg_x), .io_requestor_11_pmp_3_cfg_w (_ptw_io_requestor_11_pmp_3_cfg_w), .io_requestor_11_pmp_3_cfg_r (_ptw_io_requestor_11_pmp_3_cfg_r), .io_requestor_11_pmp_3_addr (_ptw_io_requestor_11_pmp_3_addr), .io_requestor_11_pmp_3_mask (_ptw_io_requestor_11_pmp_3_mask), .io_requestor_11_pmp_4_cfg_l (_ptw_io_requestor_11_pmp_4_cfg_l), .io_requestor_11_pmp_4_cfg_a (_ptw_io_requestor_11_pmp_4_cfg_a), .io_requestor_11_pmp_4_cfg_x (_ptw_io_requestor_11_pmp_4_cfg_x), .io_requestor_11_pmp_4_cfg_w (_ptw_io_requestor_11_pmp_4_cfg_w), .io_requestor_11_pmp_4_cfg_r (_ptw_io_requestor_11_pmp_4_cfg_r), .io_requestor_11_pmp_4_addr (_ptw_io_requestor_11_pmp_4_addr), .io_requestor_11_pmp_4_mask (_ptw_io_requestor_11_pmp_4_mask), .io_requestor_11_pmp_5_cfg_l (_ptw_io_requestor_11_pmp_5_cfg_l), .io_requestor_11_pmp_5_cfg_a (_ptw_io_requestor_11_pmp_5_cfg_a), .io_requestor_11_pmp_5_cfg_x (_ptw_io_requestor_11_pmp_5_cfg_x), .io_requestor_11_pmp_5_cfg_w (_ptw_io_requestor_11_pmp_5_cfg_w), .io_requestor_11_pmp_5_cfg_r (_ptw_io_requestor_11_pmp_5_cfg_r), .io_requestor_11_pmp_5_addr (_ptw_io_requestor_11_pmp_5_addr), .io_requestor_11_pmp_5_mask (_ptw_io_requestor_11_pmp_5_mask), .io_requestor_11_pmp_6_cfg_l (_ptw_io_requestor_11_pmp_6_cfg_l), .io_requestor_11_pmp_6_cfg_a (_ptw_io_requestor_11_pmp_6_cfg_a), .io_requestor_11_pmp_6_cfg_x (_ptw_io_requestor_11_pmp_6_cfg_x), .io_requestor_11_pmp_6_cfg_w (_ptw_io_requestor_11_pmp_6_cfg_w), .io_requestor_11_pmp_6_cfg_r (_ptw_io_requestor_11_pmp_6_cfg_r), .io_requestor_11_pmp_6_addr (_ptw_io_requestor_11_pmp_6_addr), .io_requestor_11_pmp_6_mask (_ptw_io_requestor_11_pmp_6_mask), .io_requestor_11_pmp_7_cfg_l (_ptw_io_requestor_11_pmp_7_cfg_l), .io_requestor_11_pmp_7_cfg_a (_ptw_io_requestor_11_pmp_7_cfg_a), .io_requestor_11_pmp_7_cfg_x (_ptw_io_requestor_11_pmp_7_cfg_x), .io_requestor_11_pmp_7_cfg_w (_ptw_io_requestor_11_pmp_7_cfg_w), .io_requestor_11_pmp_7_cfg_r (_ptw_io_requestor_11_pmp_7_cfg_r), .io_requestor_11_pmp_7_addr (_ptw_io_requestor_11_pmp_7_addr), .io_requestor_11_pmp_7_mask (_ptw_io_requestor_11_pmp_7_mask), .io_requestor_11_customCSRs_csrs_0_ren (_ptw_io_requestor_11_customCSRs_csrs_0_ren), .io_requestor_11_customCSRs_csrs_0_wen (_ptw_io_requestor_11_customCSRs_csrs_0_wen), .io_requestor_11_customCSRs_csrs_0_wdata (_ptw_io_requestor_11_customCSRs_csrs_0_wdata), .io_requestor_11_customCSRs_csrs_0_value (_ptw_io_requestor_11_customCSRs_csrs_0_value), .io_requestor_11_customCSRs_csrs_1_ren (_ptw_io_requestor_11_customCSRs_csrs_1_ren), .io_requestor_11_customCSRs_csrs_1_wen (_ptw_io_requestor_11_customCSRs_csrs_1_wen), .io_requestor_11_customCSRs_csrs_1_wdata (_ptw_io_requestor_11_customCSRs_csrs_1_wdata), .io_requestor_11_customCSRs_csrs_1_value (_ptw_io_requestor_11_customCSRs_csrs_1_value), .io_requestor_11_customCSRs_csrs_2_ren (_ptw_io_requestor_11_customCSRs_csrs_2_ren), .io_requestor_11_customCSRs_csrs_2_wen (_ptw_io_requestor_11_customCSRs_csrs_2_wen), .io_requestor_11_customCSRs_csrs_2_wdata (_ptw_io_requestor_11_customCSRs_csrs_2_wdata), .io_requestor_11_customCSRs_csrs_2_value (_ptw_io_requestor_11_customCSRs_csrs_2_value), .io_requestor_11_customCSRs_csrs_3_ren (_ptw_io_requestor_11_customCSRs_csrs_3_ren), .io_requestor_11_customCSRs_csrs_3_wen (_ptw_io_requestor_11_customCSRs_csrs_3_wen), .io_requestor_11_customCSRs_csrs_3_wdata (_ptw_io_requestor_11_customCSRs_csrs_3_wdata), .io_requestor_11_customCSRs_csrs_3_value (_ptw_io_requestor_11_customCSRs_csrs_3_value), .io_requestor_12_req_ready (_ptw_io_requestor_12_req_ready), .io_requestor_12_req_valid (_zstd_compressor_io_ptw_12_req_valid), // @[Configs.scala:62:39] .io_requestor_12_req_bits_bits_addr (_zstd_compressor_io_ptw_12_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_12_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_12_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_12_resp_valid (_ptw_io_requestor_12_resp_valid), .io_requestor_12_resp_bits_ae_ptw (_ptw_io_requestor_12_resp_bits_ae_ptw), .io_requestor_12_resp_bits_ae_final (_ptw_io_requestor_12_resp_bits_ae_final), .io_requestor_12_resp_bits_pf (_ptw_io_requestor_12_resp_bits_pf), .io_requestor_12_resp_bits_gf (_ptw_io_requestor_12_resp_bits_gf), .io_requestor_12_resp_bits_hr (_ptw_io_requestor_12_resp_bits_hr), .io_requestor_12_resp_bits_hw (_ptw_io_requestor_12_resp_bits_hw), .io_requestor_12_resp_bits_hx (_ptw_io_requestor_12_resp_bits_hx), .io_requestor_12_resp_bits_pte_reserved_for_future (_ptw_io_requestor_12_resp_bits_pte_reserved_for_future), .io_requestor_12_resp_bits_pte_ppn (_ptw_io_requestor_12_resp_bits_pte_ppn), .io_requestor_12_resp_bits_pte_reserved_for_software (_ptw_io_requestor_12_resp_bits_pte_reserved_for_software), .io_requestor_12_resp_bits_pte_d (_ptw_io_requestor_12_resp_bits_pte_d), .io_requestor_12_resp_bits_pte_a (_ptw_io_requestor_12_resp_bits_pte_a), .io_requestor_12_resp_bits_pte_g (_ptw_io_requestor_12_resp_bits_pte_g), .io_requestor_12_resp_bits_pte_u (_ptw_io_requestor_12_resp_bits_pte_u), .io_requestor_12_resp_bits_pte_x (_ptw_io_requestor_12_resp_bits_pte_x), .io_requestor_12_resp_bits_pte_w (_ptw_io_requestor_12_resp_bits_pte_w), .io_requestor_12_resp_bits_pte_r (_ptw_io_requestor_12_resp_bits_pte_r), .io_requestor_12_resp_bits_pte_v (_ptw_io_requestor_12_resp_bits_pte_v), .io_requestor_12_resp_bits_level (_ptw_io_requestor_12_resp_bits_level), .io_requestor_12_resp_bits_homogeneous (_ptw_io_requestor_12_resp_bits_homogeneous), .io_requestor_12_resp_bits_gpa_valid (_ptw_io_requestor_12_resp_bits_gpa_valid), .io_requestor_12_resp_bits_gpa_bits (_ptw_io_requestor_12_resp_bits_gpa_bits), .io_requestor_12_resp_bits_gpa_is_pte (_ptw_io_requestor_12_resp_bits_gpa_is_pte), .io_requestor_12_ptbr_mode (_ptw_io_requestor_12_ptbr_mode), .io_requestor_12_ptbr_ppn (_ptw_io_requestor_12_ptbr_ppn), .io_requestor_12_status_debug (_ptw_io_requestor_12_status_debug), .io_requestor_12_status_cease (_ptw_io_requestor_12_status_cease), .io_requestor_12_status_wfi (_ptw_io_requestor_12_status_wfi), .io_requestor_12_status_isa (_ptw_io_requestor_12_status_isa), .io_requestor_12_status_dprv (_ptw_io_requestor_12_status_dprv), .io_requestor_12_status_dv (_ptw_io_requestor_12_status_dv), .io_requestor_12_status_prv (_ptw_io_requestor_12_status_prv), .io_requestor_12_status_v (_ptw_io_requestor_12_status_v), .io_requestor_12_status_mpv (_ptw_io_requestor_12_status_mpv), .io_requestor_12_status_gva (_ptw_io_requestor_12_status_gva), .io_requestor_12_status_tsr (_ptw_io_requestor_12_status_tsr), .io_requestor_12_status_tw (_ptw_io_requestor_12_status_tw), .io_requestor_12_status_tvm (_ptw_io_requestor_12_status_tvm), .io_requestor_12_status_mxr (_ptw_io_requestor_12_status_mxr), .io_requestor_12_status_sum (_ptw_io_requestor_12_status_sum), .io_requestor_12_status_mprv (_ptw_io_requestor_12_status_mprv), .io_requestor_12_status_fs (_ptw_io_requestor_12_status_fs), .io_requestor_12_status_mpp (_ptw_io_requestor_12_status_mpp), .io_requestor_12_status_spp (_ptw_io_requestor_12_status_spp), .io_requestor_12_status_mpie (_ptw_io_requestor_12_status_mpie), .io_requestor_12_status_spie (_ptw_io_requestor_12_status_spie), .io_requestor_12_status_mie (_ptw_io_requestor_12_status_mie), .io_requestor_12_status_sie (_ptw_io_requestor_12_status_sie), .io_requestor_12_hstatus_spvp (_ptw_io_requestor_12_hstatus_spvp), .io_requestor_12_hstatus_spv (_ptw_io_requestor_12_hstatus_spv), .io_requestor_12_hstatus_gva (_ptw_io_requestor_12_hstatus_gva), .io_requestor_12_gstatus_debug (_ptw_io_requestor_12_gstatus_debug), .io_requestor_12_gstatus_cease (_ptw_io_requestor_12_gstatus_cease), .io_requestor_12_gstatus_wfi (_ptw_io_requestor_12_gstatus_wfi), .io_requestor_12_gstatus_isa (_ptw_io_requestor_12_gstatus_isa), .io_requestor_12_gstatus_dprv (_ptw_io_requestor_12_gstatus_dprv), .io_requestor_12_gstatus_dv (_ptw_io_requestor_12_gstatus_dv), .io_requestor_12_gstatus_prv (_ptw_io_requestor_12_gstatus_prv), .io_requestor_12_gstatus_v (_ptw_io_requestor_12_gstatus_v), .io_requestor_12_gstatus_zero2 (_ptw_io_requestor_12_gstatus_zero2), .io_requestor_12_gstatus_mpv (_ptw_io_requestor_12_gstatus_mpv), .io_requestor_12_gstatus_gva (_ptw_io_requestor_12_gstatus_gva), .io_requestor_12_gstatus_mbe (_ptw_io_requestor_12_gstatus_mbe), .io_requestor_12_gstatus_sbe (_ptw_io_requestor_12_gstatus_sbe), .io_requestor_12_gstatus_sxl (_ptw_io_requestor_12_gstatus_sxl), .io_requestor_12_gstatus_zero1 (_ptw_io_requestor_12_gstatus_zero1), .io_requestor_12_gstatus_tsr (_ptw_io_requestor_12_gstatus_tsr), .io_requestor_12_gstatus_tw (_ptw_io_requestor_12_gstatus_tw), .io_requestor_12_gstatus_tvm (_ptw_io_requestor_12_gstatus_tvm), .io_requestor_12_gstatus_mxr (_ptw_io_requestor_12_gstatus_mxr), .io_requestor_12_gstatus_sum (_ptw_io_requestor_12_gstatus_sum), .io_requestor_12_gstatus_mprv (_ptw_io_requestor_12_gstatus_mprv), .io_requestor_12_gstatus_fs (_ptw_io_requestor_12_gstatus_fs), .io_requestor_12_gstatus_mpp (_ptw_io_requestor_12_gstatus_mpp), .io_requestor_12_gstatus_vs (_ptw_io_requestor_12_gstatus_vs), .io_requestor_12_gstatus_spp (_ptw_io_requestor_12_gstatus_spp), .io_requestor_12_gstatus_mpie (_ptw_io_requestor_12_gstatus_mpie), .io_requestor_12_gstatus_ube (_ptw_io_requestor_12_gstatus_ube), .io_requestor_12_gstatus_spie (_ptw_io_requestor_12_gstatus_spie), .io_requestor_12_gstatus_upie (_ptw_io_requestor_12_gstatus_upie), .io_requestor_12_gstatus_mie (_ptw_io_requestor_12_gstatus_mie), .io_requestor_12_gstatus_hie (_ptw_io_requestor_12_gstatus_hie), .io_requestor_12_gstatus_sie (_ptw_io_requestor_12_gstatus_sie), .io_requestor_12_gstatus_uie (_ptw_io_requestor_12_gstatus_uie), .io_requestor_12_pmp_0_cfg_l (_ptw_io_requestor_12_pmp_0_cfg_l), .io_requestor_12_pmp_0_cfg_a (_ptw_io_requestor_12_pmp_0_cfg_a), .io_requestor_12_pmp_0_cfg_x (_ptw_io_requestor_12_pmp_0_cfg_x), .io_requestor_12_pmp_0_cfg_w (_ptw_io_requestor_12_pmp_0_cfg_w), .io_requestor_12_pmp_0_cfg_r (_ptw_io_requestor_12_pmp_0_cfg_r), .io_requestor_12_pmp_0_addr (_ptw_io_requestor_12_pmp_0_addr), .io_requestor_12_pmp_0_mask (_ptw_io_requestor_12_pmp_0_mask), .io_requestor_12_pmp_1_cfg_l (_ptw_io_requestor_12_pmp_1_cfg_l), .io_requestor_12_pmp_1_cfg_a (_ptw_io_requestor_12_pmp_1_cfg_a), .io_requestor_12_pmp_1_cfg_x (_ptw_io_requestor_12_pmp_1_cfg_x), .io_requestor_12_pmp_1_cfg_w (_ptw_io_requestor_12_pmp_1_cfg_w), .io_requestor_12_pmp_1_cfg_r (_ptw_io_requestor_12_pmp_1_cfg_r), .io_requestor_12_pmp_1_addr (_ptw_io_requestor_12_pmp_1_addr), .io_requestor_12_pmp_1_mask (_ptw_io_requestor_12_pmp_1_mask), .io_requestor_12_pmp_2_cfg_l (_ptw_io_requestor_12_pmp_2_cfg_l), .io_requestor_12_pmp_2_cfg_a (_ptw_io_requestor_12_pmp_2_cfg_a), .io_requestor_12_pmp_2_cfg_x (_ptw_io_requestor_12_pmp_2_cfg_x), .io_requestor_12_pmp_2_cfg_w (_ptw_io_requestor_12_pmp_2_cfg_w), .io_requestor_12_pmp_2_cfg_r (_ptw_io_requestor_12_pmp_2_cfg_r), .io_requestor_12_pmp_2_addr (_ptw_io_requestor_12_pmp_2_addr), .io_requestor_12_pmp_2_mask (_ptw_io_requestor_12_pmp_2_mask), .io_requestor_12_pmp_3_cfg_l (_ptw_io_requestor_12_pmp_3_cfg_l), .io_requestor_12_pmp_3_cfg_a (_ptw_io_requestor_12_pmp_3_cfg_a), .io_requestor_12_pmp_3_cfg_x (_ptw_io_requestor_12_pmp_3_cfg_x), .io_requestor_12_pmp_3_cfg_w (_ptw_io_requestor_12_pmp_3_cfg_w), .io_requestor_12_pmp_3_cfg_r (_ptw_io_requestor_12_pmp_3_cfg_r), .io_requestor_12_pmp_3_addr (_ptw_io_requestor_12_pmp_3_addr), .io_requestor_12_pmp_3_mask (_ptw_io_requestor_12_pmp_3_mask), .io_requestor_12_pmp_4_cfg_l (_ptw_io_requestor_12_pmp_4_cfg_l), .io_requestor_12_pmp_4_cfg_a (_ptw_io_requestor_12_pmp_4_cfg_a), .io_requestor_12_pmp_4_cfg_x (_ptw_io_requestor_12_pmp_4_cfg_x), .io_requestor_12_pmp_4_cfg_w (_ptw_io_requestor_12_pmp_4_cfg_w), .io_requestor_12_pmp_4_cfg_r (_ptw_io_requestor_12_pmp_4_cfg_r), .io_requestor_12_pmp_4_addr (_ptw_io_requestor_12_pmp_4_addr), .io_requestor_12_pmp_4_mask (_ptw_io_requestor_12_pmp_4_mask), .io_requestor_12_pmp_5_cfg_l (_ptw_io_requestor_12_pmp_5_cfg_l), .io_requestor_12_pmp_5_cfg_a (_ptw_io_requestor_12_pmp_5_cfg_a), .io_requestor_12_pmp_5_cfg_x (_ptw_io_requestor_12_pmp_5_cfg_x), .io_requestor_12_pmp_5_cfg_w (_ptw_io_requestor_12_pmp_5_cfg_w), .io_requestor_12_pmp_5_cfg_r (_ptw_io_requestor_12_pmp_5_cfg_r), .io_requestor_12_pmp_5_addr (_ptw_io_requestor_12_pmp_5_addr), .io_requestor_12_pmp_5_mask (_ptw_io_requestor_12_pmp_5_mask), .io_requestor_12_pmp_6_cfg_l (_ptw_io_requestor_12_pmp_6_cfg_l), .io_requestor_12_pmp_6_cfg_a (_ptw_io_requestor_12_pmp_6_cfg_a), .io_requestor_12_pmp_6_cfg_x (_ptw_io_requestor_12_pmp_6_cfg_x), .io_requestor_12_pmp_6_cfg_w (_ptw_io_requestor_12_pmp_6_cfg_w), .io_requestor_12_pmp_6_cfg_r (_ptw_io_requestor_12_pmp_6_cfg_r), .io_requestor_12_pmp_6_addr (_ptw_io_requestor_12_pmp_6_addr), .io_requestor_12_pmp_6_mask (_ptw_io_requestor_12_pmp_6_mask), .io_requestor_12_pmp_7_cfg_l (_ptw_io_requestor_12_pmp_7_cfg_l), .io_requestor_12_pmp_7_cfg_a (_ptw_io_requestor_12_pmp_7_cfg_a), .io_requestor_12_pmp_7_cfg_x (_ptw_io_requestor_12_pmp_7_cfg_x), .io_requestor_12_pmp_7_cfg_w (_ptw_io_requestor_12_pmp_7_cfg_w), .io_requestor_12_pmp_7_cfg_r (_ptw_io_requestor_12_pmp_7_cfg_r), .io_requestor_12_pmp_7_addr (_ptw_io_requestor_12_pmp_7_addr), .io_requestor_12_pmp_7_mask (_ptw_io_requestor_12_pmp_7_mask), .io_requestor_12_customCSRs_csrs_0_ren (_ptw_io_requestor_12_customCSRs_csrs_0_ren), .io_requestor_12_customCSRs_csrs_0_wen (_ptw_io_requestor_12_customCSRs_csrs_0_wen), .io_requestor_12_customCSRs_csrs_0_wdata (_ptw_io_requestor_12_customCSRs_csrs_0_wdata), .io_requestor_12_customCSRs_csrs_0_value (_ptw_io_requestor_12_customCSRs_csrs_0_value), .io_requestor_12_customCSRs_csrs_1_ren (_ptw_io_requestor_12_customCSRs_csrs_1_ren), .io_requestor_12_customCSRs_csrs_1_wen (_ptw_io_requestor_12_customCSRs_csrs_1_wen), .io_requestor_12_customCSRs_csrs_1_wdata (_ptw_io_requestor_12_customCSRs_csrs_1_wdata), .io_requestor_12_customCSRs_csrs_1_value (_ptw_io_requestor_12_customCSRs_csrs_1_value), .io_requestor_12_customCSRs_csrs_2_ren (_ptw_io_requestor_12_customCSRs_csrs_2_ren), .io_requestor_12_customCSRs_csrs_2_wen (_ptw_io_requestor_12_customCSRs_csrs_2_wen), .io_requestor_12_customCSRs_csrs_2_wdata (_ptw_io_requestor_12_customCSRs_csrs_2_wdata), .io_requestor_12_customCSRs_csrs_2_value (_ptw_io_requestor_12_customCSRs_csrs_2_value), .io_requestor_12_customCSRs_csrs_3_ren (_ptw_io_requestor_12_customCSRs_csrs_3_ren), .io_requestor_12_customCSRs_csrs_3_wen (_ptw_io_requestor_12_customCSRs_csrs_3_wen), .io_requestor_12_customCSRs_csrs_3_wdata (_ptw_io_requestor_12_customCSRs_csrs_3_wdata), .io_requestor_12_customCSRs_csrs_3_value (_ptw_io_requestor_12_customCSRs_csrs_3_value), .io_requestor_13_req_ready (_ptw_io_requestor_13_req_ready), .io_requestor_13_req_valid (_zstd_compressor_io_ptw_13_req_valid), // @[Configs.scala:62:39] .io_requestor_13_req_bits_bits_addr (_zstd_compressor_io_ptw_13_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_13_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_13_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_13_resp_valid (_ptw_io_requestor_13_resp_valid), .io_requestor_13_resp_bits_ae_ptw (_ptw_io_requestor_13_resp_bits_ae_ptw), .io_requestor_13_resp_bits_ae_final (_ptw_io_requestor_13_resp_bits_ae_final), .io_requestor_13_resp_bits_pf (_ptw_io_requestor_13_resp_bits_pf), .io_requestor_13_resp_bits_gf (_ptw_io_requestor_13_resp_bits_gf), .io_requestor_13_resp_bits_hr (_ptw_io_requestor_13_resp_bits_hr), .io_requestor_13_resp_bits_hw (_ptw_io_requestor_13_resp_bits_hw), .io_requestor_13_resp_bits_hx (_ptw_io_requestor_13_resp_bits_hx), .io_requestor_13_resp_bits_pte_reserved_for_future (_ptw_io_requestor_13_resp_bits_pte_reserved_for_future), .io_requestor_13_resp_bits_pte_ppn (_ptw_io_requestor_13_resp_bits_pte_ppn), .io_requestor_13_resp_bits_pte_reserved_for_software (_ptw_io_requestor_13_resp_bits_pte_reserved_for_software), .io_requestor_13_resp_bits_pte_d (_ptw_io_requestor_13_resp_bits_pte_d), .io_requestor_13_resp_bits_pte_a (_ptw_io_requestor_13_resp_bits_pte_a), .io_requestor_13_resp_bits_pte_g (_ptw_io_requestor_13_resp_bits_pte_g), .io_requestor_13_resp_bits_pte_u (_ptw_io_requestor_13_resp_bits_pte_u), .io_requestor_13_resp_bits_pte_x (_ptw_io_requestor_13_resp_bits_pte_x), .io_requestor_13_resp_bits_pte_w (_ptw_io_requestor_13_resp_bits_pte_w), .io_requestor_13_resp_bits_pte_r (_ptw_io_requestor_13_resp_bits_pte_r), .io_requestor_13_resp_bits_pte_v (_ptw_io_requestor_13_resp_bits_pte_v), .io_requestor_13_resp_bits_level (_ptw_io_requestor_13_resp_bits_level), .io_requestor_13_resp_bits_homogeneous (_ptw_io_requestor_13_resp_bits_homogeneous), .io_requestor_13_resp_bits_gpa_valid (_ptw_io_requestor_13_resp_bits_gpa_valid), .io_requestor_13_resp_bits_gpa_bits (_ptw_io_requestor_13_resp_bits_gpa_bits), .io_requestor_13_resp_bits_gpa_is_pte (_ptw_io_requestor_13_resp_bits_gpa_is_pte), .io_requestor_13_ptbr_mode (_ptw_io_requestor_13_ptbr_mode), .io_requestor_13_ptbr_ppn (_ptw_io_requestor_13_ptbr_ppn), .io_requestor_13_status_debug (_ptw_io_requestor_13_status_debug), .io_requestor_13_status_cease (_ptw_io_requestor_13_status_cease), .io_requestor_13_status_wfi (_ptw_io_requestor_13_status_wfi), .io_requestor_13_status_isa (_ptw_io_requestor_13_status_isa), .io_requestor_13_status_dprv (_ptw_io_requestor_13_status_dprv), .io_requestor_13_status_dv (_ptw_io_requestor_13_status_dv), .io_requestor_13_status_prv (_ptw_io_requestor_13_status_prv), .io_requestor_13_status_v (_ptw_io_requestor_13_status_v), .io_requestor_13_status_mpv (_ptw_io_requestor_13_status_mpv), .io_requestor_13_status_gva (_ptw_io_requestor_13_status_gva), .io_requestor_13_status_tsr (_ptw_io_requestor_13_status_tsr), .io_requestor_13_status_tw (_ptw_io_requestor_13_status_tw), .io_requestor_13_status_tvm (_ptw_io_requestor_13_status_tvm), .io_requestor_13_status_mxr (_ptw_io_requestor_13_status_mxr), .io_requestor_13_status_sum (_ptw_io_requestor_13_status_sum), .io_requestor_13_status_mprv (_ptw_io_requestor_13_status_mprv), .io_requestor_13_status_fs (_ptw_io_requestor_13_status_fs), .io_requestor_13_status_mpp (_ptw_io_requestor_13_status_mpp), .io_requestor_13_status_spp (_ptw_io_requestor_13_status_spp), .io_requestor_13_status_mpie (_ptw_io_requestor_13_status_mpie), .io_requestor_13_status_spie (_ptw_io_requestor_13_status_spie), .io_requestor_13_status_mie (_ptw_io_requestor_13_status_mie), .io_requestor_13_status_sie (_ptw_io_requestor_13_status_sie), .io_requestor_13_hstatus_spvp (_ptw_io_requestor_13_hstatus_spvp), .io_requestor_13_hstatus_spv (_ptw_io_requestor_13_hstatus_spv), .io_requestor_13_hstatus_gva (_ptw_io_requestor_13_hstatus_gva), .io_requestor_13_gstatus_debug (_ptw_io_requestor_13_gstatus_debug), .io_requestor_13_gstatus_cease (_ptw_io_requestor_13_gstatus_cease), .io_requestor_13_gstatus_wfi (_ptw_io_requestor_13_gstatus_wfi), .io_requestor_13_gstatus_isa (_ptw_io_requestor_13_gstatus_isa), .io_requestor_13_gstatus_dprv (_ptw_io_requestor_13_gstatus_dprv), .io_requestor_13_gstatus_dv (_ptw_io_requestor_13_gstatus_dv), .io_requestor_13_gstatus_prv (_ptw_io_requestor_13_gstatus_prv), .io_requestor_13_gstatus_v (_ptw_io_requestor_13_gstatus_v), .io_requestor_13_gstatus_zero2 (_ptw_io_requestor_13_gstatus_zero2), .io_requestor_13_gstatus_mpv (_ptw_io_requestor_13_gstatus_mpv), .io_requestor_13_gstatus_gva (_ptw_io_requestor_13_gstatus_gva), .io_requestor_13_gstatus_mbe (_ptw_io_requestor_13_gstatus_mbe), .io_requestor_13_gstatus_sbe (_ptw_io_requestor_13_gstatus_sbe), .io_requestor_13_gstatus_sxl (_ptw_io_requestor_13_gstatus_sxl), .io_requestor_13_gstatus_zero1 (_ptw_io_requestor_13_gstatus_zero1), .io_requestor_13_gstatus_tsr (_ptw_io_requestor_13_gstatus_tsr), .io_requestor_13_gstatus_tw (_ptw_io_requestor_13_gstatus_tw), .io_requestor_13_gstatus_tvm (_ptw_io_requestor_13_gstatus_tvm), .io_requestor_13_gstatus_mxr (_ptw_io_requestor_13_gstatus_mxr), .io_requestor_13_gstatus_sum (_ptw_io_requestor_13_gstatus_sum), .io_requestor_13_gstatus_mprv (_ptw_io_requestor_13_gstatus_mprv), .io_requestor_13_gstatus_fs (_ptw_io_requestor_13_gstatus_fs), .io_requestor_13_gstatus_mpp (_ptw_io_requestor_13_gstatus_mpp), .io_requestor_13_gstatus_vs (_ptw_io_requestor_13_gstatus_vs), .io_requestor_13_gstatus_spp (_ptw_io_requestor_13_gstatus_spp), .io_requestor_13_gstatus_mpie (_ptw_io_requestor_13_gstatus_mpie), .io_requestor_13_gstatus_ube (_ptw_io_requestor_13_gstatus_ube), .io_requestor_13_gstatus_spie (_ptw_io_requestor_13_gstatus_spie), .io_requestor_13_gstatus_upie (_ptw_io_requestor_13_gstatus_upie), .io_requestor_13_gstatus_mie (_ptw_io_requestor_13_gstatus_mie), .io_requestor_13_gstatus_hie (_ptw_io_requestor_13_gstatus_hie), .io_requestor_13_gstatus_sie (_ptw_io_requestor_13_gstatus_sie), .io_requestor_13_gstatus_uie (_ptw_io_requestor_13_gstatus_uie), .io_requestor_13_pmp_0_cfg_l (_ptw_io_requestor_13_pmp_0_cfg_l), .io_requestor_13_pmp_0_cfg_a (_ptw_io_requestor_13_pmp_0_cfg_a), .io_requestor_13_pmp_0_cfg_x (_ptw_io_requestor_13_pmp_0_cfg_x), .io_requestor_13_pmp_0_cfg_w (_ptw_io_requestor_13_pmp_0_cfg_w), .io_requestor_13_pmp_0_cfg_r (_ptw_io_requestor_13_pmp_0_cfg_r), .io_requestor_13_pmp_0_addr (_ptw_io_requestor_13_pmp_0_addr), .io_requestor_13_pmp_0_mask (_ptw_io_requestor_13_pmp_0_mask), .io_requestor_13_pmp_1_cfg_l (_ptw_io_requestor_13_pmp_1_cfg_l), .io_requestor_13_pmp_1_cfg_a (_ptw_io_requestor_13_pmp_1_cfg_a), .io_requestor_13_pmp_1_cfg_x (_ptw_io_requestor_13_pmp_1_cfg_x), .io_requestor_13_pmp_1_cfg_w (_ptw_io_requestor_13_pmp_1_cfg_w), .io_requestor_13_pmp_1_cfg_r (_ptw_io_requestor_13_pmp_1_cfg_r), .io_requestor_13_pmp_1_addr (_ptw_io_requestor_13_pmp_1_addr), .io_requestor_13_pmp_1_mask (_ptw_io_requestor_13_pmp_1_mask), .io_requestor_13_pmp_2_cfg_l (_ptw_io_requestor_13_pmp_2_cfg_l), .io_requestor_13_pmp_2_cfg_a (_ptw_io_requestor_13_pmp_2_cfg_a), .io_requestor_13_pmp_2_cfg_x (_ptw_io_requestor_13_pmp_2_cfg_x), .io_requestor_13_pmp_2_cfg_w (_ptw_io_requestor_13_pmp_2_cfg_w), .io_requestor_13_pmp_2_cfg_r (_ptw_io_requestor_13_pmp_2_cfg_r), .io_requestor_13_pmp_2_addr (_ptw_io_requestor_13_pmp_2_addr), .io_requestor_13_pmp_2_mask (_ptw_io_requestor_13_pmp_2_mask), .io_requestor_13_pmp_3_cfg_l (_ptw_io_requestor_13_pmp_3_cfg_l), .io_requestor_13_pmp_3_cfg_a (_ptw_io_requestor_13_pmp_3_cfg_a), .io_requestor_13_pmp_3_cfg_x (_ptw_io_requestor_13_pmp_3_cfg_x), .io_requestor_13_pmp_3_cfg_w (_ptw_io_requestor_13_pmp_3_cfg_w), .io_requestor_13_pmp_3_cfg_r (_ptw_io_requestor_13_pmp_3_cfg_r), .io_requestor_13_pmp_3_addr (_ptw_io_requestor_13_pmp_3_addr), .io_requestor_13_pmp_3_mask (_ptw_io_requestor_13_pmp_3_mask), .io_requestor_13_pmp_4_cfg_l (_ptw_io_requestor_13_pmp_4_cfg_l), .io_requestor_13_pmp_4_cfg_a (_ptw_io_requestor_13_pmp_4_cfg_a), .io_requestor_13_pmp_4_cfg_x (_ptw_io_requestor_13_pmp_4_cfg_x), .io_requestor_13_pmp_4_cfg_w (_ptw_io_requestor_13_pmp_4_cfg_w), .io_requestor_13_pmp_4_cfg_r (_ptw_io_requestor_13_pmp_4_cfg_r), .io_requestor_13_pmp_4_addr (_ptw_io_requestor_13_pmp_4_addr), .io_requestor_13_pmp_4_mask (_ptw_io_requestor_13_pmp_4_mask), .io_requestor_13_pmp_5_cfg_l (_ptw_io_requestor_13_pmp_5_cfg_l), .io_requestor_13_pmp_5_cfg_a (_ptw_io_requestor_13_pmp_5_cfg_a), .io_requestor_13_pmp_5_cfg_x (_ptw_io_requestor_13_pmp_5_cfg_x), .io_requestor_13_pmp_5_cfg_w (_ptw_io_requestor_13_pmp_5_cfg_w), .io_requestor_13_pmp_5_cfg_r (_ptw_io_requestor_13_pmp_5_cfg_r), .io_requestor_13_pmp_5_addr (_ptw_io_requestor_13_pmp_5_addr), .io_requestor_13_pmp_5_mask (_ptw_io_requestor_13_pmp_5_mask), .io_requestor_13_pmp_6_cfg_l (_ptw_io_requestor_13_pmp_6_cfg_l), .io_requestor_13_pmp_6_cfg_a (_ptw_io_requestor_13_pmp_6_cfg_a), .io_requestor_13_pmp_6_cfg_x (_ptw_io_requestor_13_pmp_6_cfg_x), .io_requestor_13_pmp_6_cfg_w (_ptw_io_requestor_13_pmp_6_cfg_w), .io_requestor_13_pmp_6_cfg_r (_ptw_io_requestor_13_pmp_6_cfg_r), .io_requestor_13_pmp_6_addr (_ptw_io_requestor_13_pmp_6_addr), .io_requestor_13_pmp_6_mask (_ptw_io_requestor_13_pmp_6_mask), .io_requestor_13_pmp_7_cfg_l (_ptw_io_requestor_13_pmp_7_cfg_l), .io_requestor_13_pmp_7_cfg_a (_ptw_io_requestor_13_pmp_7_cfg_a), .io_requestor_13_pmp_7_cfg_x (_ptw_io_requestor_13_pmp_7_cfg_x), .io_requestor_13_pmp_7_cfg_w (_ptw_io_requestor_13_pmp_7_cfg_w), .io_requestor_13_pmp_7_cfg_r (_ptw_io_requestor_13_pmp_7_cfg_r), .io_requestor_13_pmp_7_addr (_ptw_io_requestor_13_pmp_7_addr), .io_requestor_13_pmp_7_mask (_ptw_io_requestor_13_pmp_7_mask), .io_requestor_13_customCSRs_csrs_0_ren (_ptw_io_requestor_13_customCSRs_csrs_0_ren), .io_requestor_13_customCSRs_csrs_0_wen (_ptw_io_requestor_13_customCSRs_csrs_0_wen), .io_requestor_13_customCSRs_csrs_0_wdata (_ptw_io_requestor_13_customCSRs_csrs_0_wdata), .io_requestor_13_customCSRs_csrs_0_value (_ptw_io_requestor_13_customCSRs_csrs_0_value), .io_requestor_13_customCSRs_csrs_1_ren (_ptw_io_requestor_13_customCSRs_csrs_1_ren), .io_requestor_13_customCSRs_csrs_1_wen (_ptw_io_requestor_13_customCSRs_csrs_1_wen), .io_requestor_13_customCSRs_csrs_1_wdata (_ptw_io_requestor_13_customCSRs_csrs_1_wdata), .io_requestor_13_customCSRs_csrs_1_value (_ptw_io_requestor_13_customCSRs_csrs_1_value), .io_requestor_13_customCSRs_csrs_2_ren (_ptw_io_requestor_13_customCSRs_csrs_2_ren), .io_requestor_13_customCSRs_csrs_2_wen (_ptw_io_requestor_13_customCSRs_csrs_2_wen), .io_requestor_13_customCSRs_csrs_2_wdata (_ptw_io_requestor_13_customCSRs_csrs_2_wdata), .io_requestor_13_customCSRs_csrs_2_value (_ptw_io_requestor_13_customCSRs_csrs_2_value), .io_requestor_13_customCSRs_csrs_3_ren (_ptw_io_requestor_13_customCSRs_csrs_3_ren), .io_requestor_13_customCSRs_csrs_3_wen (_ptw_io_requestor_13_customCSRs_csrs_3_wen), .io_requestor_13_customCSRs_csrs_3_wdata (_ptw_io_requestor_13_customCSRs_csrs_3_wdata), .io_requestor_13_customCSRs_csrs_3_value (_ptw_io_requestor_13_customCSRs_csrs_3_value), .io_requestor_14_req_ready (_ptw_io_requestor_14_req_ready), .io_requestor_14_req_valid (_zstd_compressor_io_ptw_14_req_valid), // @[Configs.scala:62:39] .io_requestor_14_req_bits_bits_addr (_zstd_compressor_io_ptw_14_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_14_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_14_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_14_resp_valid (_ptw_io_requestor_14_resp_valid), .io_requestor_14_resp_bits_ae_ptw (_ptw_io_requestor_14_resp_bits_ae_ptw), .io_requestor_14_resp_bits_ae_final (_ptw_io_requestor_14_resp_bits_ae_final), .io_requestor_14_resp_bits_pf (_ptw_io_requestor_14_resp_bits_pf), .io_requestor_14_resp_bits_gf (_ptw_io_requestor_14_resp_bits_gf), .io_requestor_14_resp_bits_hr (_ptw_io_requestor_14_resp_bits_hr), .io_requestor_14_resp_bits_hw (_ptw_io_requestor_14_resp_bits_hw), .io_requestor_14_resp_bits_hx (_ptw_io_requestor_14_resp_bits_hx), .io_requestor_14_resp_bits_pte_reserved_for_future (_ptw_io_requestor_14_resp_bits_pte_reserved_for_future), .io_requestor_14_resp_bits_pte_ppn (_ptw_io_requestor_14_resp_bits_pte_ppn), .io_requestor_14_resp_bits_pte_reserved_for_software (_ptw_io_requestor_14_resp_bits_pte_reserved_for_software), .io_requestor_14_resp_bits_pte_d (_ptw_io_requestor_14_resp_bits_pte_d), .io_requestor_14_resp_bits_pte_a (_ptw_io_requestor_14_resp_bits_pte_a), .io_requestor_14_resp_bits_pte_g (_ptw_io_requestor_14_resp_bits_pte_g), .io_requestor_14_resp_bits_pte_u (_ptw_io_requestor_14_resp_bits_pte_u), .io_requestor_14_resp_bits_pte_x (_ptw_io_requestor_14_resp_bits_pte_x), .io_requestor_14_resp_bits_pte_w (_ptw_io_requestor_14_resp_bits_pte_w), .io_requestor_14_resp_bits_pte_r (_ptw_io_requestor_14_resp_bits_pte_r), .io_requestor_14_resp_bits_pte_v (_ptw_io_requestor_14_resp_bits_pte_v), .io_requestor_14_resp_bits_level (_ptw_io_requestor_14_resp_bits_level), .io_requestor_14_resp_bits_homogeneous (_ptw_io_requestor_14_resp_bits_homogeneous), .io_requestor_14_resp_bits_gpa_valid (_ptw_io_requestor_14_resp_bits_gpa_valid), .io_requestor_14_resp_bits_gpa_bits (_ptw_io_requestor_14_resp_bits_gpa_bits), .io_requestor_14_resp_bits_gpa_is_pte (_ptw_io_requestor_14_resp_bits_gpa_is_pte), .io_requestor_14_ptbr_mode (_ptw_io_requestor_14_ptbr_mode), .io_requestor_14_ptbr_ppn (_ptw_io_requestor_14_ptbr_ppn), .io_requestor_14_status_debug (_ptw_io_requestor_14_status_debug), .io_requestor_14_status_cease (_ptw_io_requestor_14_status_cease), .io_requestor_14_status_wfi (_ptw_io_requestor_14_status_wfi), .io_requestor_14_status_isa (_ptw_io_requestor_14_status_isa), .io_requestor_14_status_dprv (_ptw_io_requestor_14_status_dprv), .io_requestor_14_status_dv (_ptw_io_requestor_14_status_dv), .io_requestor_14_status_prv (_ptw_io_requestor_14_status_prv), .io_requestor_14_status_v (_ptw_io_requestor_14_status_v), .io_requestor_14_status_mpv (_ptw_io_requestor_14_status_mpv), .io_requestor_14_status_gva (_ptw_io_requestor_14_status_gva), .io_requestor_14_status_tsr (_ptw_io_requestor_14_status_tsr), .io_requestor_14_status_tw (_ptw_io_requestor_14_status_tw), .io_requestor_14_status_tvm (_ptw_io_requestor_14_status_tvm), .io_requestor_14_status_mxr (_ptw_io_requestor_14_status_mxr), .io_requestor_14_status_sum (_ptw_io_requestor_14_status_sum), .io_requestor_14_status_mprv (_ptw_io_requestor_14_status_mprv), .io_requestor_14_status_fs (_ptw_io_requestor_14_status_fs), .io_requestor_14_status_mpp (_ptw_io_requestor_14_status_mpp), .io_requestor_14_status_spp (_ptw_io_requestor_14_status_spp), .io_requestor_14_status_mpie (_ptw_io_requestor_14_status_mpie), .io_requestor_14_status_spie (_ptw_io_requestor_14_status_spie), .io_requestor_14_status_mie (_ptw_io_requestor_14_status_mie), .io_requestor_14_status_sie (_ptw_io_requestor_14_status_sie), .io_requestor_14_hstatus_spvp (_ptw_io_requestor_14_hstatus_spvp), .io_requestor_14_hstatus_spv (_ptw_io_requestor_14_hstatus_spv), .io_requestor_14_hstatus_gva (_ptw_io_requestor_14_hstatus_gva), .io_requestor_14_gstatus_debug (_ptw_io_requestor_14_gstatus_debug), .io_requestor_14_gstatus_cease (_ptw_io_requestor_14_gstatus_cease), .io_requestor_14_gstatus_wfi (_ptw_io_requestor_14_gstatus_wfi), .io_requestor_14_gstatus_isa (_ptw_io_requestor_14_gstatus_isa), .io_requestor_14_gstatus_dprv (_ptw_io_requestor_14_gstatus_dprv), .io_requestor_14_gstatus_dv (_ptw_io_requestor_14_gstatus_dv), .io_requestor_14_gstatus_prv (_ptw_io_requestor_14_gstatus_prv), .io_requestor_14_gstatus_v (_ptw_io_requestor_14_gstatus_v), .io_requestor_14_gstatus_zero2 (_ptw_io_requestor_14_gstatus_zero2), .io_requestor_14_gstatus_mpv (_ptw_io_requestor_14_gstatus_mpv), .io_requestor_14_gstatus_gva (_ptw_io_requestor_14_gstatus_gva), .io_requestor_14_gstatus_mbe (_ptw_io_requestor_14_gstatus_mbe), .io_requestor_14_gstatus_sbe (_ptw_io_requestor_14_gstatus_sbe), .io_requestor_14_gstatus_sxl (_ptw_io_requestor_14_gstatus_sxl), .io_requestor_14_gstatus_zero1 (_ptw_io_requestor_14_gstatus_zero1), .io_requestor_14_gstatus_tsr (_ptw_io_requestor_14_gstatus_tsr), .io_requestor_14_gstatus_tw (_ptw_io_requestor_14_gstatus_tw), .io_requestor_14_gstatus_tvm (_ptw_io_requestor_14_gstatus_tvm), .io_requestor_14_gstatus_mxr (_ptw_io_requestor_14_gstatus_mxr), .io_requestor_14_gstatus_sum (_ptw_io_requestor_14_gstatus_sum), .io_requestor_14_gstatus_mprv (_ptw_io_requestor_14_gstatus_mprv), .io_requestor_14_gstatus_fs (_ptw_io_requestor_14_gstatus_fs), .io_requestor_14_gstatus_mpp (_ptw_io_requestor_14_gstatus_mpp), .io_requestor_14_gstatus_vs (_ptw_io_requestor_14_gstatus_vs), .io_requestor_14_gstatus_spp (_ptw_io_requestor_14_gstatus_spp), .io_requestor_14_gstatus_mpie (_ptw_io_requestor_14_gstatus_mpie), .io_requestor_14_gstatus_ube (_ptw_io_requestor_14_gstatus_ube), .io_requestor_14_gstatus_spie (_ptw_io_requestor_14_gstatus_spie), .io_requestor_14_gstatus_upie (_ptw_io_requestor_14_gstatus_upie), .io_requestor_14_gstatus_mie (_ptw_io_requestor_14_gstatus_mie), .io_requestor_14_gstatus_hie (_ptw_io_requestor_14_gstatus_hie), .io_requestor_14_gstatus_sie (_ptw_io_requestor_14_gstatus_sie), .io_requestor_14_gstatus_uie (_ptw_io_requestor_14_gstatus_uie), .io_requestor_14_pmp_0_cfg_l (_ptw_io_requestor_14_pmp_0_cfg_l), .io_requestor_14_pmp_0_cfg_a (_ptw_io_requestor_14_pmp_0_cfg_a), .io_requestor_14_pmp_0_cfg_x (_ptw_io_requestor_14_pmp_0_cfg_x), .io_requestor_14_pmp_0_cfg_w (_ptw_io_requestor_14_pmp_0_cfg_w), .io_requestor_14_pmp_0_cfg_r (_ptw_io_requestor_14_pmp_0_cfg_r), .io_requestor_14_pmp_0_addr (_ptw_io_requestor_14_pmp_0_addr), .io_requestor_14_pmp_0_mask (_ptw_io_requestor_14_pmp_0_mask), .io_requestor_14_pmp_1_cfg_l (_ptw_io_requestor_14_pmp_1_cfg_l), .io_requestor_14_pmp_1_cfg_a (_ptw_io_requestor_14_pmp_1_cfg_a), .io_requestor_14_pmp_1_cfg_x (_ptw_io_requestor_14_pmp_1_cfg_x), .io_requestor_14_pmp_1_cfg_w (_ptw_io_requestor_14_pmp_1_cfg_w), .io_requestor_14_pmp_1_cfg_r (_ptw_io_requestor_14_pmp_1_cfg_r), .io_requestor_14_pmp_1_addr (_ptw_io_requestor_14_pmp_1_addr), .io_requestor_14_pmp_1_mask (_ptw_io_requestor_14_pmp_1_mask), .io_requestor_14_pmp_2_cfg_l (_ptw_io_requestor_14_pmp_2_cfg_l), .io_requestor_14_pmp_2_cfg_a (_ptw_io_requestor_14_pmp_2_cfg_a), .io_requestor_14_pmp_2_cfg_x (_ptw_io_requestor_14_pmp_2_cfg_x), .io_requestor_14_pmp_2_cfg_w (_ptw_io_requestor_14_pmp_2_cfg_w), .io_requestor_14_pmp_2_cfg_r (_ptw_io_requestor_14_pmp_2_cfg_r), .io_requestor_14_pmp_2_addr (_ptw_io_requestor_14_pmp_2_addr), .io_requestor_14_pmp_2_mask (_ptw_io_requestor_14_pmp_2_mask), .io_requestor_14_pmp_3_cfg_l (_ptw_io_requestor_14_pmp_3_cfg_l), .io_requestor_14_pmp_3_cfg_a (_ptw_io_requestor_14_pmp_3_cfg_a), .io_requestor_14_pmp_3_cfg_x (_ptw_io_requestor_14_pmp_3_cfg_x), .io_requestor_14_pmp_3_cfg_w (_ptw_io_requestor_14_pmp_3_cfg_w), .io_requestor_14_pmp_3_cfg_r (_ptw_io_requestor_14_pmp_3_cfg_r), .io_requestor_14_pmp_3_addr (_ptw_io_requestor_14_pmp_3_addr), .io_requestor_14_pmp_3_mask (_ptw_io_requestor_14_pmp_3_mask), .io_requestor_14_pmp_4_cfg_l (_ptw_io_requestor_14_pmp_4_cfg_l), .io_requestor_14_pmp_4_cfg_a (_ptw_io_requestor_14_pmp_4_cfg_a), .io_requestor_14_pmp_4_cfg_x (_ptw_io_requestor_14_pmp_4_cfg_x), .io_requestor_14_pmp_4_cfg_w (_ptw_io_requestor_14_pmp_4_cfg_w), .io_requestor_14_pmp_4_cfg_r (_ptw_io_requestor_14_pmp_4_cfg_r), .io_requestor_14_pmp_4_addr (_ptw_io_requestor_14_pmp_4_addr), .io_requestor_14_pmp_4_mask (_ptw_io_requestor_14_pmp_4_mask), .io_requestor_14_pmp_5_cfg_l (_ptw_io_requestor_14_pmp_5_cfg_l), .io_requestor_14_pmp_5_cfg_a (_ptw_io_requestor_14_pmp_5_cfg_a), .io_requestor_14_pmp_5_cfg_x (_ptw_io_requestor_14_pmp_5_cfg_x), .io_requestor_14_pmp_5_cfg_w (_ptw_io_requestor_14_pmp_5_cfg_w), .io_requestor_14_pmp_5_cfg_r (_ptw_io_requestor_14_pmp_5_cfg_r), .io_requestor_14_pmp_5_addr (_ptw_io_requestor_14_pmp_5_addr), .io_requestor_14_pmp_5_mask (_ptw_io_requestor_14_pmp_5_mask), .io_requestor_14_pmp_6_cfg_l (_ptw_io_requestor_14_pmp_6_cfg_l), .io_requestor_14_pmp_6_cfg_a (_ptw_io_requestor_14_pmp_6_cfg_a), .io_requestor_14_pmp_6_cfg_x (_ptw_io_requestor_14_pmp_6_cfg_x), .io_requestor_14_pmp_6_cfg_w (_ptw_io_requestor_14_pmp_6_cfg_w), .io_requestor_14_pmp_6_cfg_r (_ptw_io_requestor_14_pmp_6_cfg_r), .io_requestor_14_pmp_6_addr (_ptw_io_requestor_14_pmp_6_addr), .io_requestor_14_pmp_6_mask (_ptw_io_requestor_14_pmp_6_mask), .io_requestor_14_pmp_7_cfg_l (_ptw_io_requestor_14_pmp_7_cfg_l), .io_requestor_14_pmp_7_cfg_a (_ptw_io_requestor_14_pmp_7_cfg_a), .io_requestor_14_pmp_7_cfg_x (_ptw_io_requestor_14_pmp_7_cfg_x), .io_requestor_14_pmp_7_cfg_w (_ptw_io_requestor_14_pmp_7_cfg_w), .io_requestor_14_pmp_7_cfg_r (_ptw_io_requestor_14_pmp_7_cfg_r), .io_requestor_14_pmp_7_addr (_ptw_io_requestor_14_pmp_7_addr), .io_requestor_14_pmp_7_mask (_ptw_io_requestor_14_pmp_7_mask), .io_requestor_14_customCSRs_csrs_0_ren (_ptw_io_requestor_14_customCSRs_csrs_0_ren), .io_requestor_14_customCSRs_csrs_0_wen (_ptw_io_requestor_14_customCSRs_csrs_0_wen), .io_requestor_14_customCSRs_csrs_0_wdata (_ptw_io_requestor_14_customCSRs_csrs_0_wdata), .io_requestor_14_customCSRs_csrs_0_value (_ptw_io_requestor_14_customCSRs_csrs_0_value), .io_requestor_14_customCSRs_csrs_1_ren (_ptw_io_requestor_14_customCSRs_csrs_1_ren), .io_requestor_14_customCSRs_csrs_1_wen (_ptw_io_requestor_14_customCSRs_csrs_1_wen), .io_requestor_14_customCSRs_csrs_1_wdata (_ptw_io_requestor_14_customCSRs_csrs_1_wdata), .io_requestor_14_customCSRs_csrs_1_value (_ptw_io_requestor_14_customCSRs_csrs_1_value), .io_requestor_14_customCSRs_csrs_2_ren (_ptw_io_requestor_14_customCSRs_csrs_2_ren), .io_requestor_14_customCSRs_csrs_2_wen (_ptw_io_requestor_14_customCSRs_csrs_2_wen), .io_requestor_14_customCSRs_csrs_2_wdata (_ptw_io_requestor_14_customCSRs_csrs_2_wdata), .io_requestor_14_customCSRs_csrs_2_value (_ptw_io_requestor_14_customCSRs_csrs_2_value), .io_requestor_14_customCSRs_csrs_3_ren (_ptw_io_requestor_14_customCSRs_csrs_3_ren), .io_requestor_14_customCSRs_csrs_3_wen (_ptw_io_requestor_14_customCSRs_csrs_3_wen), .io_requestor_14_customCSRs_csrs_3_wdata (_ptw_io_requestor_14_customCSRs_csrs_3_wdata), .io_requestor_14_customCSRs_csrs_3_value (_ptw_io_requestor_14_customCSRs_csrs_3_value), .io_requestor_15_req_ready (_ptw_io_requestor_15_req_ready), .io_requestor_15_req_valid (_zstd_compressor_io_ptw_15_req_valid), // @[Configs.scala:62:39] .io_requestor_15_req_bits_bits_addr (_zstd_compressor_io_ptw_15_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_15_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_15_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_15_resp_valid (_ptw_io_requestor_15_resp_valid), .io_requestor_15_resp_bits_ae_ptw (_ptw_io_requestor_15_resp_bits_ae_ptw), .io_requestor_15_resp_bits_ae_final (_ptw_io_requestor_15_resp_bits_ae_final), .io_requestor_15_resp_bits_pf (_ptw_io_requestor_15_resp_bits_pf), .io_requestor_15_resp_bits_gf (_ptw_io_requestor_15_resp_bits_gf), .io_requestor_15_resp_bits_hr (_ptw_io_requestor_15_resp_bits_hr), .io_requestor_15_resp_bits_hw (_ptw_io_requestor_15_resp_bits_hw), .io_requestor_15_resp_bits_hx (_ptw_io_requestor_15_resp_bits_hx), .io_requestor_15_resp_bits_pte_reserved_for_future (_ptw_io_requestor_15_resp_bits_pte_reserved_for_future), .io_requestor_15_resp_bits_pte_ppn (_ptw_io_requestor_15_resp_bits_pte_ppn), .io_requestor_15_resp_bits_pte_reserved_for_software (_ptw_io_requestor_15_resp_bits_pte_reserved_for_software), .io_requestor_15_resp_bits_pte_d (_ptw_io_requestor_15_resp_bits_pte_d), .io_requestor_15_resp_bits_pte_a (_ptw_io_requestor_15_resp_bits_pte_a), .io_requestor_15_resp_bits_pte_g (_ptw_io_requestor_15_resp_bits_pte_g), .io_requestor_15_resp_bits_pte_u (_ptw_io_requestor_15_resp_bits_pte_u), .io_requestor_15_resp_bits_pte_x (_ptw_io_requestor_15_resp_bits_pte_x), .io_requestor_15_resp_bits_pte_w (_ptw_io_requestor_15_resp_bits_pte_w), .io_requestor_15_resp_bits_pte_r (_ptw_io_requestor_15_resp_bits_pte_r), .io_requestor_15_resp_bits_pte_v (_ptw_io_requestor_15_resp_bits_pte_v), .io_requestor_15_resp_bits_level (_ptw_io_requestor_15_resp_bits_level), .io_requestor_15_resp_bits_homogeneous (_ptw_io_requestor_15_resp_bits_homogeneous), .io_requestor_15_resp_bits_gpa_valid (_ptw_io_requestor_15_resp_bits_gpa_valid), .io_requestor_15_resp_bits_gpa_bits (_ptw_io_requestor_15_resp_bits_gpa_bits), .io_requestor_15_resp_bits_gpa_is_pte (_ptw_io_requestor_15_resp_bits_gpa_is_pte), .io_requestor_15_ptbr_mode (_ptw_io_requestor_15_ptbr_mode), .io_requestor_15_ptbr_ppn (_ptw_io_requestor_15_ptbr_ppn), .io_requestor_15_status_debug (_ptw_io_requestor_15_status_debug), .io_requestor_15_status_cease (_ptw_io_requestor_15_status_cease), .io_requestor_15_status_wfi (_ptw_io_requestor_15_status_wfi), .io_requestor_15_status_isa (_ptw_io_requestor_15_status_isa), .io_requestor_15_status_dprv (_ptw_io_requestor_15_status_dprv), .io_requestor_15_status_dv (_ptw_io_requestor_15_status_dv), .io_requestor_15_status_prv (_ptw_io_requestor_15_status_prv), .io_requestor_15_status_v (_ptw_io_requestor_15_status_v), .io_requestor_15_status_mpv (_ptw_io_requestor_15_status_mpv), .io_requestor_15_status_gva (_ptw_io_requestor_15_status_gva), .io_requestor_15_status_tsr (_ptw_io_requestor_15_status_tsr), .io_requestor_15_status_tw (_ptw_io_requestor_15_status_tw), .io_requestor_15_status_tvm (_ptw_io_requestor_15_status_tvm), .io_requestor_15_status_mxr (_ptw_io_requestor_15_status_mxr), .io_requestor_15_status_sum (_ptw_io_requestor_15_status_sum), .io_requestor_15_status_mprv (_ptw_io_requestor_15_status_mprv), .io_requestor_15_status_fs (_ptw_io_requestor_15_status_fs), .io_requestor_15_status_mpp (_ptw_io_requestor_15_status_mpp), .io_requestor_15_status_spp (_ptw_io_requestor_15_status_spp), .io_requestor_15_status_mpie (_ptw_io_requestor_15_status_mpie), .io_requestor_15_status_spie (_ptw_io_requestor_15_status_spie), .io_requestor_15_status_mie (_ptw_io_requestor_15_status_mie), .io_requestor_15_status_sie (_ptw_io_requestor_15_status_sie), .io_requestor_15_hstatus_spvp (_ptw_io_requestor_15_hstatus_spvp), .io_requestor_15_hstatus_spv (_ptw_io_requestor_15_hstatus_spv), .io_requestor_15_hstatus_gva (_ptw_io_requestor_15_hstatus_gva), .io_requestor_15_gstatus_debug (_ptw_io_requestor_15_gstatus_debug), .io_requestor_15_gstatus_cease (_ptw_io_requestor_15_gstatus_cease), .io_requestor_15_gstatus_wfi (_ptw_io_requestor_15_gstatus_wfi), .io_requestor_15_gstatus_isa (_ptw_io_requestor_15_gstatus_isa), .io_requestor_15_gstatus_dprv (_ptw_io_requestor_15_gstatus_dprv), .io_requestor_15_gstatus_dv (_ptw_io_requestor_15_gstatus_dv), .io_requestor_15_gstatus_prv (_ptw_io_requestor_15_gstatus_prv), .io_requestor_15_gstatus_v (_ptw_io_requestor_15_gstatus_v), .io_requestor_15_gstatus_zero2 (_ptw_io_requestor_15_gstatus_zero2), .io_requestor_15_gstatus_mpv (_ptw_io_requestor_15_gstatus_mpv), .io_requestor_15_gstatus_gva (_ptw_io_requestor_15_gstatus_gva), .io_requestor_15_gstatus_mbe (_ptw_io_requestor_15_gstatus_mbe), .io_requestor_15_gstatus_sbe (_ptw_io_requestor_15_gstatus_sbe), .io_requestor_15_gstatus_sxl (_ptw_io_requestor_15_gstatus_sxl), .io_requestor_15_gstatus_zero1 (_ptw_io_requestor_15_gstatus_zero1), .io_requestor_15_gstatus_tsr (_ptw_io_requestor_15_gstatus_tsr), .io_requestor_15_gstatus_tw (_ptw_io_requestor_15_gstatus_tw), .io_requestor_15_gstatus_tvm (_ptw_io_requestor_15_gstatus_tvm), .io_requestor_15_gstatus_mxr (_ptw_io_requestor_15_gstatus_mxr), .io_requestor_15_gstatus_sum (_ptw_io_requestor_15_gstatus_sum), .io_requestor_15_gstatus_mprv (_ptw_io_requestor_15_gstatus_mprv), .io_requestor_15_gstatus_fs (_ptw_io_requestor_15_gstatus_fs), .io_requestor_15_gstatus_mpp (_ptw_io_requestor_15_gstatus_mpp), .io_requestor_15_gstatus_vs (_ptw_io_requestor_15_gstatus_vs), .io_requestor_15_gstatus_spp (_ptw_io_requestor_15_gstatus_spp), .io_requestor_15_gstatus_mpie (_ptw_io_requestor_15_gstatus_mpie), .io_requestor_15_gstatus_ube (_ptw_io_requestor_15_gstatus_ube), .io_requestor_15_gstatus_spie (_ptw_io_requestor_15_gstatus_spie), .io_requestor_15_gstatus_upie (_ptw_io_requestor_15_gstatus_upie), .io_requestor_15_gstatus_mie (_ptw_io_requestor_15_gstatus_mie), .io_requestor_15_gstatus_hie (_ptw_io_requestor_15_gstatus_hie), .io_requestor_15_gstatus_sie (_ptw_io_requestor_15_gstatus_sie), .io_requestor_15_gstatus_uie (_ptw_io_requestor_15_gstatus_uie), .io_requestor_15_pmp_0_cfg_l (_ptw_io_requestor_15_pmp_0_cfg_l), .io_requestor_15_pmp_0_cfg_a (_ptw_io_requestor_15_pmp_0_cfg_a), .io_requestor_15_pmp_0_cfg_x (_ptw_io_requestor_15_pmp_0_cfg_x), .io_requestor_15_pmp_0_cfg_w (_ptw_io_requestor_15_pmp_0_cfg_w), .io_requestor_15_pmp_0_cfg_r (_ptw_io_requestor_15_pmp_0_cfg_r), .io_requestor_15_pmp_0_addr (_ptw_io_requestor_15_pmp_0_addr), .io_requestor_15_pmp_0_mask (_ptw_io_requestor_15_pmp_0_mask), .io_requestor_15_pmp_1_cfg_l (_ptw_io_requestor_15_pmp_1_cfg_l), .io_requestor_15_pmp_1_cfg_a (_ptw_io_requestor_15_pmp_1_cfg_a), .io_requestor_15_pmp_1_cfg_x (_ptw_io_requestor_15_pmp_1_cfg_x), .io_requestor_15_pmp_1_cfg_w (_ptw_io_requestor_15_pmp_1_cfg_w), .io_requestor_15_pmp_1_cfg_r (_ptw_io_requestor_15_pmp_1_cfg_r), .io_requestor_15_pmp_1_addr (_ptw_io_requestor_15_pmp_1_addr), .io_requestor_15_pmp_1_mask (_ptw_io_requestor_15_pmp_1_mask), .io_requestor_15_pmp_2_cfg_l (_ptw_io_requestor_15_pmp_2_cfg_l), .io_requestor_15_pmp_2_cfg_a (_ptw_io_requestor_15_pmp_2_cfg_a), .io_requestor_15_pmp_2_cfg_x (_ptw_io_requestor_15_pmp_2_cfg_x), .io_requestor_15_pmp_2_cfg_w (_ptw_io_requestor_15_pmp_2_cfg_w), .io_requestor_15_pmp_2_cfg_r (_ptw_io_requestor_15_pmp_2_cfg_r), .io_requestor_15_pmp_2_addr (_ptw_io_requestor_15_pmp_2_addr), .io_requestor_15_pmp_2_mask (_ptw_io_requestor_15_pmp_2_mask), .io_requestor_15_pmp_3_cfg_l (_ptw_io_requestor_15_pmp_3_cfg_l), .io_requestor_15_pmp_3_cfg_a (_ptw_io_requestor_15_pmp_3_cfg_a), .io_requestor_15_pmp_3_cfg_x (_ptw_io_requestor_15_pmp_3_cfg_x), .io_requestor_15_pmp_3_cfg_w (_ptw_io_requestor_15_pmp_3_cfg_w), .io_requestor_15_pmp_3_cfg_r (_ptw_io_requestor_15_pmp_3_cfg_r), .io_requestor_15_pmp_3_addr (_ptw_io_requestor_15_pmp_3_addr), .io_requestor_15_pmp_3_mask (_ptw_io_requestor_15_pmp_3_mask), .io_requestor_15_pmp_4_cfg_l (_ptw_io_requestor_15_pmp_4_cfg_l), .io_requestor_15_pmp_4_cfg_a (_ptw_io_requestor_15_pmp_4_cfg_a), .io_requestor_15_pmp_4_cfg_x (_ptw_io_requestor_15_pmp_4_cfg_x), .io_requestor_15_pmp_4_cfg_w (_ptw_io_requestor_15_pmp_4_cfg_w), .io_requestor_15_pmp_4_cfg_r (_ptw_io_requestor_15_pmp_4_cfg_r), .io_requestor_15_pmp_4_addr (_ptw_io_requestor_15_pmp_4_addr), .io_requestor_15_pmp_4_mask (_ptw_io_requestor_15_pmp_4_mask), .io_requestor_15_pmp_5_cfg_l (_ptw_io_requestor_15_pmp_5_cfg_l), .io_requestor_15_pmp_5_cfg_a (_ptw_io_requestor_15_pmp_5_cfg_a), .io_requestor_15_pmp_5_cfg_x (_ptw_io_requestor_15_pmp_5_cfg_x), .io_requestor_15_pmp_5_cfg_w (_ptw_io_requestor_15_pmp_5_cfg_w), .io_requestor_15_pmp_5_cfg_r (_ptw_io_requestor_15_pmp_5_cfg_r), .io_requestor_15_pmp_5_addr (_ptw_io_requestor_15_pmp_5_addr), .io_requestor_15_pmp_5_mask (_ptw_io_requestor_15_pmp_5_mask), .io_requestor_15_pmp_6_cfg_l (_ptw_io_requestor_15_pmp_6_cfg_l), .io_requestor_15_pmp_6_cfg_a (_ptw_io_requestor_15_pmp_6_cfg_a), .io_requestor_15_pmp_6_cfg_x (_ptw_io_requestor_15_pmp_6_cfg_x), .io_requestor_15_pmp_6_cfg_w (_ptw_io_requestor_15_pmp_6_cfg_w), .io_requestor_15_pmp_6_cfg_r (_ptw_io_requestor_15_pmp_6_cfg_r), .io_requestor_15_pmp_6_addr (_ptw_io_requestor_15_pmp_6_addr), .io_requestor_15_pmp_6_mask (_ptw_io_requestor_15_pmp_6_mask), .io_requestor_15_pmp_7_cfg_l (_ptw_io_requestor_15_pmp_7_cfg_l), .io_requestor_15_pmp_7_cfg_a (_ptw_io_requestor_15_pmp_7_cfg_a), .io_requestor_15_pmp_7_cfg_x (_ptw_io_requestor_15_pmp_7_cfg_x), .io_requestor_15_pmp_7_cfg_w (_ptw_io_requestor_15_pmp_7_cfg_w), .io_requestor_15_pmp_7_cfg_r (_ptw_io_requestor_15_pmp_7_cfg_r), .io_requestor_15_pmp_7_addr (_ptw_io_requestor_15_pmp_7_addr), .io_requestor_15_pmp_7_mask (_ptw_io_requestor_15_pmp_7_mask), .io_requestor_15_customCSRs_csrs_0_ren (_ptw_io_requestor_15_customCSRs_csrs_0_ren), .io_requestor_15_customCSRs_csrs_0_wen (_ptw_io_requestor_15_customCSRs_csrs_0_wen), .io_requestor_15_customCSRs_csrs_0_wdata (_ptw_io_requestor_15_customCSRs_csrs_0_wdata), .io_requestor_15_customCSRs_csrs_0_value (_ptw_io_requestor_15_customCSRs_csrs_0_value), .io_requestor_15_customCSRs_csrs_1_ren (_ptw_io_requestor_15_customCSRs_csrs_1_ren), .io_requestor_15_customCSRs_csrs_1_wen (_ptw_io_requestor_15_customCSRs_csrs_1_wen), .io_requestor_15_customCSRs_csrs_1_wdata (_ptw_io_requestor_15_customCSRs_csrs_1_wdata), .io_requestor_15_customCSRs_csrs_1_value (_ptw_io_requestor_15_customCSRs_csrs_1_value), .io_requestor_15_customCSRs_csrs_2_ren (_ptw_io_requestor_15_customCSRs_csrs_2_ren), .io_requestor_15_customCSRs_csrs_2_wen (_ptw_io_requestor_15_customCSRs_csrs_2_wen), .io_requestor_15_customCSRs_csrs_2_wdata (_ptw_io_requestor_15_customCSRs_csrs_2_wdata), .io_requestor_15_customCSRs_csrs_2_value (_ptw_io_requestor_15_customCSRs_csrs_2_value), .io_requestor_15_customCSRs_csrs_3_ren (_ptw_io_requestor_15_customCSRs_csrs_3_ren), .io_requestor_15_customCSRs_csrs_3_wen (_ptw_io_requestor_15_customCSRs_csrs_3_wen), .io_requestor_15_customCSRs_csrs_3_wdata (_ptw_io_requestor_15_customCSRs_csrs_3_wdata), .io_requestor_15_customCSRs_csrs_3_value (_ptw_io_requestor_15_customCSRs_csrs_3_value), .io_requestor_16_req_ready (_ptw_io_requestor_16_req_ready), .io_requestor_16_req_valid (_zstd_compressor_io_ptw_16_req_valid), // @[Configs.scala:62:39] .io_requestor_16_req_bits_bits_addr (_zstd_compressor_io_ptw_16_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_16_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_16_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_16_resp_valid (_ptw_io_requestor_16_resp_valid), .io_requestor_16_resp_bits_ae_ptw (_ptw_io_requestor_16_resp_bits_ae_ptw), .io_requestor_16_resp_bits_ae_final (_ptw_io_requestor_16_resp_bits_ae_final), .io_requestor_16_resp_bits_pf (_ptw_io_requestor_16_resp_bits_pf), .io_requestor_16_resp_bits_gf (_ptw_io_requestor_16_resp_bits_gf), .io_requestor_16_resp_bits_hr (_ptw_io_requestor_16_resp_bits_hr), .io_requestor_16_resp_bits_hw (_ptw_io_requestor_16_resp_bits_hw), .io_requestor_16_resp_bits_hx (_ptw_io_requestor_16_resp_bits_hx), .io_requestor_16_resp_bits_pte_reserved_for_future (_ptw_io_requestor_16_resp_bits_pte_reserved_for_future), .io_requestor_16_resp_bits_pte_ppn (_ptw_io_requestor_16_resp_bits_pte_ppn), .io_requestor_16_resp_bits_pte_reserved_for_software (_ptw_io_requestor_16_resp_bits_pte_reserved_for_software), .io_requestor_16_resp_bits_pte_d (_ptw_io_requestor_16_resp_bits_pte_d), .io_requestor_16_resp_bits_pte_a (_ptw_io_requestor_16_resp_bits_pte_a), .io_requestor_16_resp_bits_pte_g (_ptw_io_requestor_16_resp_bits_pte_g), .io_requestor_16_resp_bits_pte_u (_ptw_io_requestor_16_resp_bits_pte_u), .io_requestor_16_resp_bits_pte_x (_ptw_io_requestor_16_resp_bits_pte_x), .io_requestor_16_resp_bits_pte_w (_ptw_io_requestor_16_resp_bits_pte_w), .io_requestor_16_resp_bits_pte_r (_ptw_io_requestor_16_resp_bits_pte_r), .io_requestor_16_resp_bits_pte_v (_ptw_io_requestor_16_resp_bits_pte_v), .io_requestor_16_resp_bits_level (_ptw_io_requestor_16_resp_bits_level), .io_requestor_16_resp_bits_homogeneous (_ptw_io_requestor_16_resp_bits_homogeneous), .io_requestor_16_resp_bits_gpa_valid (_ptw_io_requestor_16_resp_bits_gpa_valid), .io_requestor_16_resp_bits_gpa_bits (_ptw_io_requestor_16_resp_bits_gpa_bits), .io_requestor_16_resp_bits_gpa_is_pte (_ptw_io_requestor_16_resp_bits_gpa_is_pte), .io_requestor_16_ptbr_mode (_ptw_io_requestor_16_ptbr_mode), .io_requestor_16_ptbr_ppn (_ptw_io_requestor_16_ptbr_ppn), .io_requestor_16_status_debug (_ptw_io_requestor_16_status_debug), .io_requestor_16_status_cease (_ptw_io_requestor_16_status_cease), .io_requestor_16_status_wfi (_ptw_io_requestor_16_status_wfi), .io_requestor_16_status_isa (_ptw_io_requestor_16_status_isa), .io_requestor_16_status_dprv (_ptw_io_requestor_16_status_dprv), .io_requestor_16_status_dv (_ptw_io_requestor_16_status_dv), .io_requestor_16_status_prv (_ptw_io_requestor_16_status_prv), .io_requestor_16_status_v (_ptw_io_requestor_16_status_v), .io_requestor_16_status_mpv (_ptw_io_requestor_16_status_mpv), .io_requestor_16_status_gva (_ptw_io_requestor_16_status_gva), .io_requestor_16_status_tsr (_ptw_io_requestor_16_status_tsr), .io_requestor_16_status_tw (_ptw_io_requestor_16_status_tw), .io_requestor_16_status_tvm (_ptw_io_requestor_16_status_tvm), .io_requestor_16_status_mxr (_ptw_io_requestor_16_status_mxr), .io_requestor_16_status_sum (_ptw_io_requestor_16_status_sum), .io_requestor_16_status_mprv (_ptw_io_requestor_16_status_mprv), .io_requestor_16_status_fs (_ptw_io_requestor_16_status_fs), .io_requestor_16_status_mpp (_ptw_io_requestor_16_status_mpp), .io_requestor_16_status_spp (_ptw_io_requestor_16_status_spp), .io_requestor_16_status_mpie (_ptw_io_requestor_16_status_mpie), .io_requestor_16_status_spie (_ptw_io_requestor_16_status_spie), .io_requestor_16_status_mie (_ptw_io_requestor_16_status_mie), .io_requestor_16_status_sie (_ptw_io_requestor_16_status_sie), .io_requestor_16_hstatus_spvp (_ptw_io_requestor_16_hstatus_spvp), .io_requestor_16_hstatus_spv (_ptw_io_requestor_16_hstatus_spv), .io_requestor_16_hstatus_gva (_ptw_io_requestor_16_hstatus_gva), .io_requestor_16_gstatus_debug (_ptw_io_requestor_16_gstatus_debug), .io_requestor_16_gstatus_cease (_ptw_io_requestor_16_gstatus_cease), .io_requestor_16_gstatus_wfi (_ptw_io_requestor_16_gstatus_wfi), .io_requestor_16_gstatus_isa (_ptw_io_requestor_16_gstatus_isa), .io_requestor_16_gstatus_dprv (_ptw_io_requestor_16_gstatus_dprv), .io_requestor_16_gstatus_dv (_ptw_io_requestor_16_gstatus_dv), .io_requestor_16_gstatus_prv (_ptw_io_requestor_16_gstatus_prv), .io_requestor_16_gstatus_v (_ptw_io_requestor_16_gstatus_v), .io_requestor_16_gstatus_zero2 (_ptw_io_requestor_16_gstatus_zero2), .io_requestor_16_gstatus_mpv (_ptw_io_requestor_16_gstatus_mpv), .io_requestor_16_gstatus_gva (_ptw_io_requestor_16_gstatus_gva), .io_requestor_16_gstatus_mbe (_ptw_io_requestor_16_gstatus_mbe), .io_requestor_16_gstatus_sbe (_ptw_io_requestor_16_gstatus_sbe), .io_requestor_16_gstatus_sxl (_ptw_io_requestor_16_gstatus_sxl), .io_requestor_16_gstatus_zero1 (_ptw_io_requestor_16_gstatus_zero1), .io_requestor_16_gstatus_tsr (_ptw_io_requestor_16_gstatus_tsr), .io_requestor_16_gstatus_tw (_ptw_io_requestor_16_gstatus_tw), .io_requestor_16_gstatus_tvm (_ptw_io_requestor_16_gstatus_tvm), .io_requestor_16_gstatus_mxr (_ptw_io_requestor_16_gstatus_mxr), .io_requestor_16_gstatus_sum (_ptw_io_requestor_16_gstatus_sum), .io_requestor_16_gstatus_mprv (_ptw_io_requestor_16_gstatus_mprv), .io_requestor_16_gstatus_fs (_ptw_io_requestor_16_gstatus_fs), .io_requestor_16_gstatus_mpp (_ptw_io_requestor_16_gstatus_mpp), .io_requestor_16_gstatus_vs (_ptw_io_requestor_16_gstatus_vs), .io_requestor_16_gstatus_spp (_ptw_io_requestor_16_gstatus_spp), .io_requestor_16_gstatus_mpie (_ptw_io_requestor_16_gstatus_mpie), .io_requestor_16_gstatus_ube (_ptw_io_requestor_16_gstatus_ube), .io_requestor_16_gstatus_spie (_ptw_io_requestor_16_gstatus_spie), .io_requestor_16_gstatus_upie (_ptw_io_requestor_16_gstatus_upie), .io_requestor_16_gstatus_mie (_ptw_io_requestor_16_gstatus_mie), .io_requestor_16_gstatus_hie (_ptw_io_requestor_16_gstatus_hie), .io_requestor_16_gstatus_sie (_ptw_io_requestor_16_gstatus_sie), .io_requestor_16_gstatus_uie (_ptw_io_requestor_16_gstatus_uie), .io_requestor_16_pmp_0_cfg_l (_ptw_io_requestor_16_pmp_0_cfg_l), .io_requestor_16_pmp_0_cfg_a (_ptw_io_requestor_16_pmp_0_cfg_a), .io_requestor_16_pmp_0_cfg_x (_ptw_io_requestor_16_pmp_0_cfg_x), .io_requestor_16_pmp_0_cfg_w (_ptw_io_requestor_16_pmp_0_cfg_w), .io_requestor_16_pmp_0_cfg_r (_ptw_io_requestor_16_pmp_0_cfg_r), .io_requestor_16_pmp_0_addr (_ptw_io_requestor_16_pmp_0_addr), .io_requestor_16_pmp_0_mask (_ptw_io_requestor_16_pmp_0_mask), .io_requestor_16_pmp_1_cfg_l (_ptw_io_requestor_16_pmp_1_cfg_l), .io_requestor_16_pmp_1_cfg_a (_ptw_io_requestor_16_pmp_1_cfg_a), .io_requestor_16_pmp_1_cfg_x (_ptw_io_requestor_16_pmp_1_cfg_x), .io_requestor_16_pmp_1_cfg_w (_ptw_io_requestor_16_pmp_1_cfg_w), .io_requestor_16_pmp_1_cfg_r (_ptw_io_requestor_16_pmp_1_cfg_r), .io_requestor_16_pmp_1_addr (_ptw_io_requestor_16_pmp_1_addr), .io_requestor_16_pmp_1_mask (_ptw_io_requestor_16_pmp_1_mask), .io_requestor_16_pmp_2_cfg_l (_ptw_io_requestor_16_pmp_2_cfg_l), .io_requestor_16_pmp_2_cfg_a (_ptw_io_requestor_16_pmp_2_cfg_a), .io_requestor_16_pmp_2_cfg_x (_ptw_io_requestor_16_pmp_2_cfg_x), .io_requestor_16_pmp_2_cfg_w (_ptw_io_requestor_16_pmp_2_cfg_w), .io_requestor_16_pmp_2_cfg_r (_ptw_io_requestor_16_pmp_2_cfg_r), .io_requestor_16_pmp_2_addr (_ptw_io_requestor_16_pmp_2_addr), .io_requestor_16_pmp_2_mask (_ptw_io_requestor_16_pmp_2_mask), .io_requestor_16_pmp_3_cfg_l (_ptw_io_requestor_16_pmp_3_cfg_l), .io_requestor_16_pmp_3_cfg_a (_ptw_io_requestor_16_pmp_3_cfg_a), .io_requestor_16_pmp_3_cfg_x (_ptw_io_requestor_16_pmp_3_cfg_x), .io_requestor_16_pmp_3_cfg_w (_ptw_io_requestor_16_pmp_3_cfg_w), .io_requestor_16_pmp_3_cfg_r (_ptw_io_requestor_16_pmp_3_cfg_r), .io_requestor_16_pmp_3_addr (_ptw_io_requestor_16_pmp_3_addr), .io_requestor_16_pmp_3_mask (_ptw_io_requestor_16_pmp_3_mask), .io_requestor_16_pmp_4_cfg_l (_ptw_io_requestor_16_pmp_4_cfg_l), .io_requestor_16_pmp_4_cfg_a (_ptw_io_requestor_16_pmp_4_cfg_a), .io_requestor_16_pmp_4_cfg_x (_ptw_io_requestor_16_pmp_4_cfg_x), .io_requestor_16_pmp_4_cfg_w (_ptw_io_requestor_16_pmp_4_cfg_w), .io_requestor_16_pmp_4_cfg_r (_ptw_io_requestor_16_pmp_4_cfg_r), .io_requestor_16_pmp_4_addr (_ptw_io_requestor_16_pmp_4_addr), .io_requestor_16_pmp_4_mask (_ptw_io_requestor_16_pmp_4_mask), .io_requestor_16_pmp_5_cfg_l (_ptw_io_requestor_16_pmp_5_cfg_l), .io_requestor_16_pmp_5_cfg_a (_ptw_io_requestor_16_pmp_5_cfg_a), .io_requestor_16_pmp_5_cfg_x (_ptw_io_requestor_16_pmp_5_cfg_x), .io_requestor_16_pmp_5_cfg_w (_ptw_io_requestor_16_pmp_5_cfg_w), .io_requestor_16_pmp_5_cfg_r (_ptw_io_requestor_16_pmp_5_cfg_r), .io_requestor_16_pmp_5_addr (_ptw_io_requestor_16_pmp_5_addr), .io_requestor_16_pmp_5_mask (_ptw_io_requestor_16_pmp_5_mask), .io_requestor_16_pmp_6_cfg_l (_ptw_io_requestor_16_pmp_6_cfg_l), .io_requestor_16_pmp_6_cfg_a (_ptw_io_requestor_16_pmp_6_cfg_a), .io_requestor_16_pmp_6_cfg_x (_ptw_io_requestor_16_pmp_6_cfg_x), .io_requestor_16_pmp_6_cfg_w (_ptw_io_requestor_16_pmp_6_cfg_w), .io_requestor_16_pmp_6_cfg_r (_ptw_io_requestor_16_pmp_6_cfg_r), .io_requestor_16_pmp_6_addr (_ptw_io_requestor_16_pmp_6_addr), .io_requestor_16_pmp_6_mask (_ptw_io_requestor_16_pmp_6_mask), .io_requestor_16_pmp_7_cfg_l (_ptw_io_requestor_16_pmp_7_cfg_l), .io_requestor_16_pmp_7_cfg_a (_ptw_io_requestor_16_pmp_7_cfg_a), .io_requestor_16_pmp_7_cfg_x (_ptw_io_requestor_16_pmp_7_cfg_x), .io_requestor_16_pmp_7_cfg_w (_ptw_io_requestor_16_pmp_7_cfg_w), .io_requestor_16_pmp_7_cfg_r (_ptw_io_requestor_16_pmp_7_cfg_r), .io_requestor_16_pmp_7_addr (_ptw_io_requestor_16_pmp_7_addr), .io_requestor_16_pmp_7_mask (_ptw_io_requestor_16_pmp_7_mask), .io_requestor_16_customCSRs_csrs_0_ren (_ptw_io_requestor_16_customCSRs_csrs_0_ren), .io_requestor_16_customCSRs_csrs_0_wen (_ptw_io_requestor_16_customCSRs_csrs_0_wen), .io_requestor_16_customCSRs_csrs_0_wdata (_ptw_io_requestor_16_customCSRs_csrs_0_wdata), .io_requestor_16_customCSRs_csrs_0_value (_ptw_io_requestor_16_customCSRs_csrs_0_value), .io_requestor_16_customCSRs_csrs_1_ren (_ptw_io_requestor_16_customCSRs_csrs_1_ren), .io_requestor_16_customCSRs_csrs_1_wen (_ptw_io_requestor_16_customCSRs_csrs_1_wen), .io_requestor_16_customCSRs_csrs_1_wdata (_ptw_io_requestor_16_customCSRs_csrs_1_wdata), .io_requestor_16_customCSRs_csrs_1_value (_ptw_io_requestor_16_customCSRs_csrs_1_value), .io_requestor_16_customCSRs_csrs_2_ren (_ptw_io_requestor_16_customCSRs_csrs_2_ren), .io_requestor_16_customCSRs_csrs_2_wen (_ptw_io_requestor_16_customCSRs_csrs_2_wen), .io_requestor_16_customCSRs_csrs_2_wdata (_ptw_io_requestor_16_customCSRs_csrs_2_wdata), .io_requestor_16_customCSRs_csrs_2_value (_ptw_io_requestor_16_customCSRs_csrs_2_value), .io_requestor_16_customCSRs_csrs_3_ren (_ptw_io_requestor_16_customCSRs_csrs_3_ren), .io_requestor_16_customCSRs_csrs_3_wen (_ptw_io_requestor_16_customCSRs_csrs_3_wen), .io_requestor_16_customCSRs_csrs_3_wdata (_ptw_io_requestor_16_customCSRs_csrs_3_wdata), .io_requestor_16_customCSRs_csrs_3_value (_ptw_io_requestor_16_customCSRs_csrs_3_value), .io_requestor_17_req_ready (_ptw_io_requestor_17_req_ready), .io_requestor_17_req_valid (_zstd_compressor_io_ptw_17_req_valid), // @[Configs.scala:62:39] .io_requestor_17_req_bits_bits_addr (_zstd_compressor_io_ptw_17_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_17_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_17_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_17_resp_valid (_ptw_io_requestor_17_resp_valid), .io_requestor_17_resp_bits_ae_ptw (_ptw_io_requestor_17_resp_bits_ae_ptw), .io_requestor_17_resp_bits_ae_final (_ptw_io_requestor_17_resp_bits_ae_final), .io_requestor_17_resp_bits_pf (_ptw_io_requestor_17_resp_bits_pf), .io_requestor_17_resp_bits_gf (_ptw_io_requestor_17_resp_bits_gf), .io_requestor_17_resp_bits_hr (_ptw_io_requestor_17_resp_bits_hr), .io_requestor_17_resp_bits_hw (_ptw_io_requestor_17_resp_bits_hw), .io_requestor_17_resp_bits_hx (_ptw_io_requestor_17_resp_bits_hx), .io_requestor_17_resp_bits_pte_reserved_for_future (_ptw_io_requestor_17_resp_bits_pte_reserved_for_future), .io_requestor_17_resp_bits_pte_ppn (_ptw_io_requestor_17_resp_bits_pte_ppn), .io_requestor_17_resp_bits_pte_reserved_for_software (_ptw_io_requestor_17_resp_bits_pte_reserved_for_software), .io_requestor_17_resp_bits_pte_d (_ptw_io_requestor_17_resp_bits_pte_d), .io_requestor_17_resp_bits_pte_a (_ptw_io_requestor_17_resp_bits_pte_a), .io_requestor_17_resp_bits_pte_g (_ptw_io_requestor_17_resp_bits_pte_g), .io_requestor_17_resp_bits_pte_u (_ptw_io_requestor_17_resp_bits_pte_u), .io_requestor_17_resp_bits_pte_x (_ptw_io_requestor_17_resp_bits_pte_x), .io_requestor_17_resp_bits_pte_w (_ptw_io_requestor_17_resp_bits_pte_w), .io_requestor_17_resp_bits_pte_r (_ptw_io_requestor_17_resp_bits_pte_r), .io_requestor_17_resp_bits_pte_v (_ptw_io_requestor_17_resp_bits_pte_v), .io_requestor_17_resp_bits_level (_ptw_io_requestor_17_resp_bits_level), .io_requestor_17_resp_bits_homogeneous (_ptw_io_requestor_17_resp_bits_homogeneous), .io_requestor_17_resp_bits_gpa_valid (_ptw_io_requestor_17_resp_bits_gpa_valid), .io_requestor_17_resp_bits_gpa_bits (_ptw_io_requestor_17_resp_bits_gpa_bits), .io_requestor_17_resp_bits_gpa_is_pte (_ptw_io_requestor_17_resp_bits_gpa_is_pte), .io_requestor_17_ptbr_mode (_ptw_io_requestor_17_ptbr_mode), .io_requestor_17_ptbr_ppn (_ptw_io_requestor_17_ptbr_ppn), .io_requestor_17_status_debug (_ptw_io_requestor_17_status_debug), .io_requestor_17_status_cease (_ptw_io_requestor_17_status_cease), .io_requestor_17_status_wfi (_ptw_io_requestor_17_status_wfi), .io_requestor_17_status_isa (_ptw_io_requestor_17_status_isa), .io_requestor_17_status_dprv (_ptw_io_requestor_17_status_dprv), .io_requestor_17_status_dv (_ptw_io_requestor_17_status_dv), .io_requestor_17_status_prv (_ptw_io_requestor_17_status_prv), .io_requestor_17_status_v (_ptw_io_requestor_17_status_v), .io_requestor_17_status_mpv (_ptw_io_requestor_17_status_mpv), .io_requestor_17_status_gva (_ptw_io_requestor_17_status_gva), .io_requestor_17_status_tsr (_ptw_io_requestor_17_status_tsr), .io_requestor_17_status_tw (_ptw_io_requestor_17_status_tw), .io_requestor_17_status_tvm (_ptw_io_requestor_17_status_tvm), .io_requestor_17_status_mxr (_ptw_io_requestor_17_status_mxr), .io_requestor_17_status_sum (_ptw_io_requestor_17_status_sum), .io_requestor_17_status_mprv (_ptw_io_requestor_17_status_mprv), .io_requestor_17_status_fs (_ptw_io_requestor_17_status_fs), .io_requestor_17_status_mpp (_ptw_io_requestor_17_status_mpp), .io_requestor_17_status_spp (_ptw_io_requestor_17_status_spp), .io_requestor_17_status_mpie (_ptw_io_requestor_17_status_mpie), .io_requestor_17_status_spie (_ptw_io_requestor_17_status_spie), .io_requestor_17_status_mie (_ptw_io_requestor_17_status_mie), .io_requestor_17_status_sie (_ptw_io_requestor_17_status_sie), .io_requestor_17_hstatus_spvp (_ptw_io_requestor_17_hstatus_spvp), .io_requestor_17_hstatus_spv (_ptw_io_requestor_17_hstatus_spv), .io_requestor_17_hstatus_gva (_ptw_io_requestor_17_hstatus_gva), .io_requestor_17_gstatus_debug (_ptw_io_requestor_17_gstatus_debug), .io_requestor_17_gstatus_cease (_ptw_io_requestor_17_gstatus_cease), .io_requestor_17_gstatus_wfi (_ptw_io_requestor_17_gstatus_wfi), .io_requestor_17_gstatus_isa (_ptw_io_requestor_17_gstatus_isa), .io_requestor_17_gstatus_dprv (_ptw_io_requestor_17_gstatus_dprv), .io_requestor_17_gstatus_dv (_ptw_io_requestor_17_gstatus_dv), .io_requestor_17_gstatus_prv (_ptw_io_requestor_17_gstatus_prv), .io_requestor_17_gstatus_v (_ptw_io_requestor_17_gstatus_v), .io_requestor_17_gstatus_zero2 (_ptw_io_requestor_17_gstatus_zero2), .io_requestor_17_gstatus_mpv (_ptw_io_requestor_17_gstatus_mpv), .io_requestor_17_gstatus_gva (_ptw_io_requestor_17_gstatus_gva), .io_requestor_17_gstatus_mbe (_ptw_io_requestor_17_gstatus_mbe), .io_requestor_17_gstatus_sbe (_ptw_io_requestor_17_gstatus_sbe), .io_requestor_17_gstatus_sxl (_ptw_io_requestor_17_gstatus_sxl), .io_requestor_17_gstatus_zero1 (_ptw_io_requestor_17_gstatus_zero1), .io_requestor_17_gstatus_tsr (_ptw_io_requestor_17_gstatus_tsr), .io_requestor_17_gstatus_tw (_ptw_io_requestor_17_gstatus_tw), .io_requestor_17_gstatus_tvm (_ptw_io_requestor_17_gstatus_tvm), .io_requestor_17_gstatus_mxr (_ptw_io_requestor_17_gstatus_mxr), .io_requestor_17_gstatus_sum (_ptw_io_requestor_17_gstatus_sum), .io_requestor_17_gstatus_mprv (_ptw_io_requestor_17_gstatus_mprv), .io_requestor_17_gstatus_fs (_ptw_io_requestor_17_gstatus_fs), .io_requestor_17_gstatus_mpp (_ptw_io_requestor_17_gstatus_mpp), .io_requestor_17_gstatus_vs (_ptw_io_requestor_17_gstatus_vs), .io_requestor_17_gstatus_spp (_ptw_io_requestor_17_gstatus_spp), .io_requestor_17_gstatus_mpie (_ptw_io_requestor_17_gstatus_mpie), .io_requestor_17_gstatus_ube (_ptw_io_requestor_17_gstatus_ube), .io_requestor_17_gstatus_spie (_ptw_io_requestor_17_gstatus_spie), .io_requestor_17_gstatus_upie (_ptw_io_requestor_17_gstatus_upie), .io_requestor_17_gstatus_mie (_ptw_io_requestor_17_gstatus_mie), .io_requestor_17_gstatus_hie (_ptw_io_requestor_17_gstatus_hie), .io_requestor_17_gstatus_sie (_ptw_io_requestor_17_gstatus_sie), .io_requestor_17_gstatus_uie (_ptw_io_requestor_17_gstatus_uie), .io_requestor_17_pmp_0_cfg_l (_ptw_io_requestor_17_pmp_0_cfg_l), .io_requestor_17_pmp_0_cfg_a (_ptw_io_requestor_17_pmp_0_cfg_a), .io_requestor_17_pmp_0_cfg_x (_ptw_io_requestor_17_pmp_0_cfg_x), .io_requestor_17_pmp_0_cfg_w (_ptw_io_requestor_17_pmp_0_cfg_w), .io_requestor_17_pmp_0_cfg_r (_ptw_io_requestor_17_pmp_0_cfg_r), .io_requestor_17_pmp_0_addr (_ptw_io_requestor_17_pmp_0_addr), .io_requestor_17_pmp_0_mask (_ptw_io_requestor_17_pmp_0_mask), .io_requestor_17_pmp_1_cfg_l (_ptw_io_requestor_17_pmp_1_cfg_l), .io_requestor_17_pmp_1_cfg_a (_ptw_io_requestor_17_pmp_1_cfg_a), .io_requestor_17_pmp_1_cfg_x (_ptw_io_requestor_17_pmp_1_cfg_x), .io_requestor_17_pmp_1_cfg_w (_ptw_io_requestor_17_pmp_1_cfg_w), .io_requestor_17_pmp_1_cfg_r (_ptw_io_requestor_17_pmp_1_cfg_r), .io_requestor_17_pmp_1_addr (_ptw_io_requestor_17_pmp_1_addr), .io_requestor_17_pmp_1_mask (_ptw_io_requestor_17_pmp_1_mask), .io_requestor_17_pmp_2_cfg_l (_ptw_io_requestor_17_pmp_2_cfg_l), .io_requestor_17_pmp_2_cfg_a (_ptw_io_requestor_17_pmp_2_cfg_a), .io_requestor_17_pmp_2_cfg_x (_ptw_io_requestor_17_pmp_2_cfg_x), .io_requestor_17_pmp_2_cfg_w (_ptw_io_requestor_17_pmp_2_cfg_w), .io_requestor_17_pmp_2_cfg_r (_ptw_io_requestor_17_pmp_2_cfg_r), .io_requestor_17_pmp_2_addr (_ptw_io_requestor_17_pmp_2_addr), .io_requestor_17_pmp_2_mask (_ptw_io_requestor_17_pmp_2_mask), .io_requestor_17_pmp_3_cfg_l (_ptw_io_requestor_17_pmp_3_cfg_l), .io_requestor_17_pmp_3_cfg_a (_ptw_io_requestor_17_pmp_3_cfg_a), .io_requestor_17_pmp_3_cfg_x (_ptw_io_requestor_17_pmp_3_cfg_x), .io_requestor_17_pmp_3_cfg_w (_ptw_io_requestor_17_pmp_3_cfg_w), .io_requestor_17_pmp_3_cfg_r (_ptw_io_requestor_17_pmp_3_cfg_r), .io_requestor_17_pmp_3_addr (_ptw_io_requestor_17_pmp_3_addr), .io_requestor_17_pmp_3_mask (_ptw_io_requestor_17_pmp_3_mask), .io_requestor_17_pmp_4_cfg_l (_ptw_io_requestor_17_pmp_4_cfg_l), .io_requestor_17_pmp_4_cfg_a (_ptw_io_requestor_17_pmp_4_cfg_a), .io_requestor_17_pmp_4_cfg_x (_ptw_io_requestor_17_pmp_4_cfg_x), .io_requestor_17_pmp_4_cfg_w (_ptw_io_requestor_17_pmp_4_cfg_w), .io_requestor_17_pmp_4_cfg_r (_ptw_io_requestor_17_pmp_4_cfg_r), .io_requestor_17_pmp_4_addr (_ptw_io_requestor_17_pmp_4_addr), .io_requestor_17_pmp_4_mask (_ptw_io_requestor_17_pmp_4_mask), .io_requestor_17_pmp_5_cfg_l (_ptw_io_requestor_17_pmp_5_cfg_l), .io_requestor_17_pmp_5_cfg_a (_ptw_io_requestor_17_pmp_5_cfg_a), .io_requestor_17_pmp_5_cfg_x (_ptw_io_requestor_17_pmp_5_cfg_x), .io_requestor_17_pmp_5_cfg_w (_ptw_io_requestor_17_pmp_5_cfg_w), .io_requestor_17_pmp_5_cfg_r (_ptw_io_requestor_17_pmp_5_cfg_r), .io_requestor_17_pmp_5_addr (_ptw_io_requestor_17_pmp_5_addr), .io_requestor_17_pmp_5_mask (_ptw_io_requestor_17_pmp_5_mask), .io_requestor_17_pmp_6_cfg_l (_ptw_io_requestor_17_pmp_6_cfg_l), .io_requestor_17_pmp_6_cfg_a (_ptw_io_requestor_17_pmp_6_cfg_a), .io_requestor_17_pmp_6_cfg_x (_ptw_io_requestor_17_pmp_6_cfg_x), .io_requestor_17_pmp_6_cfg_w (_ptw_io_requestor_17_pmp_6_cfg_w), .io_requestor_17_pmp_6_cfg_r (_ptw_io_requestor_17_pmp_6_cfg_r), .io_requestor_17_pmp_6_addr (_ptw_io_requestor_17_pmp_6_addr), .io_requestor_17_pmp_6_mask (_ptw_io_requestor_17_pmp_6_mask), .io_requestor_17_pmp_7_cfg_l (_ptw_io_requestor_17_pmp_7_cfg_l), .io_requestor_17_pmp_7_cfg_a (_ptw_io_requestor_17_pmp_7_cfg_a), .io_requestor_17_pmp_7_cfg_x (_ptw_io_requestor_17_pmp_7_cfg_x), .io_requestor_17_pmp_7_cfg_w (_ptw_io_requestor_17_pmp_7_cfg_w), .io_requestor_17_pmp_7_cfg_r (_ptw_io_requestor_17_pmp_7_cfg_r), .io_requestor_17_pmp_7_addr (_ptw_io_requestor_17_pmp_7_addr), .io_requestor_17_pmp_7_mask (_ptw_io_requestor_17_pmp_7_mask), .io_requestor_17_customCSRs_csrs_0_ren (_ptw_io_requestor_17_customCSRs_csrs_0_ren), .io_requestor_17_customCSRs_csrs_0_wen (_ptw_io_requestor_17_customCSRs_csrs_0_wen), .io_requestor_17_customCSRs_csrs_0_wdata (_ptw_io_requestor_17_customCSRs_csrs_0_wdata), .io_requestor_17_customCSRs_csrs_0_value (_ptw_io_requestor_17_customCSRs_csrs_0_value), .io_requestor_17_customCSRs_csrs_1_ren (_ptw_io_requestor_17_customCSRs_csrs_1_ren), .io_requestor_17_customCSRs_csrs_1_wen (_ptw_io_requestor_17_customCSRs_csrs_1_wen), .io_requestor_17_customCSRs_csrs_1_wdata (_ptw_io_requestor_17_customCSRs_csrs_1_wdata), .io_requestor_17_customCSRs_csrs_1_value (_ptw_io_requestor_17_customCSRs_csrs_1_value), .io_requestor_17_customCSRs_csrs_2_ren (_ptw_io_requestor_17_customCSRs_csrs_2_ren), .io_requestor_17_customCSRs_csrs_2_wen (_ptw_io_requestor_17_customCSRs_csrs_2_wen), .io_requestor_17_customCSRs_csrs_2_wdata (_ptw_io_requestor_17_customCSRs_csrs_2_wdata), .io_requestor_17_customCSRs_csrs_2_value (_ptw_io_requestor_17_customCSRs_csrs_2_value), .io_requestor_17_customCSRs_csrs_3_ren (_ptw_io_requestor_17_customCSRs_csrs_3_ren), .io_requestor_17_customCSRs_csrs_3_wen (_ptw_io_requestor_17_customCSRs_csrs_3_wen), .io_requestor_17_customCSRs_csrs_3_wdata (_ptw_io_requestor_17_customCSRs_csrs_3_wdata), .io_requestor_17_customCSRs_csrs_3_value (_ptw_io_requestor_17_customCSRs_csrs_3_value), .io_requestor_18_req_ready (_ptw_io_requestor_18_req_ready), .io_requestor_18_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_18_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_18_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_18_resp_valid (_ptw_io_requestor_18_resp_valid), .io_requestor_18_resp_bits_ae_ptw (_ptw_io_requestor_18_resp_bits_ae_ptw), .io_requestor_18_resp_bits_ae_final (_ptw_io_requestor_18_resp_bits_ae_final), .io_requestor_18_resp_bits_pf (_ptw_io_requestor_18_resp_bits_pf), .io_requestor_18_resp_bits_gf (_ptw_io_requestor_18_resp_bits_gf), .io_requestor_18_resp_bits_hr (_ptw_io_requestor_18_resp_bits_hr), .io_requestor_18_resp_bits_hw (_ptw_io_requestor_18_resp_bits_hw), .io_requestor_18_resp_bits_hx (_ptw_io_requestor_18_resp_bits_hx), .io_requestor_18_resp_bits_pte_reserved_for_future (_ptw_io_requestor_18_resp_bits_pte_reserved_for_future), .io_requestor_18_resp_bits_pte_ppn (_ptw_io_requestor_18_resp_bits_pte_ppn), .io_requestor_18_resp_bits_pte_reserved_for_software (_ptw_io_requestor_18_resp_bits_pte_reserved_for_software), .io_requestor_18_resp_bits_pte_d (_ptw_io_requestor_18_resp_bits_pte_d), .io_requestor_18_resp_bits_pte_a (_ptw_io_requestor_18_resp_bits_pte_a), .io_requestor_18_resp_bits_pte_g (_ptw_io_requestor_18_resp_bits_pte_g), .io_requestor_18_resp_bits_pte_u (_ptw_io_requestor_18_resp_bits_pte_u), .io_requestor_18_resp_bits_pte_x (_ptw_io_requestor_18_resp_bits_pte_x), .io_requestor_18_resp_bits_pte_w (_ptw_io_requestor_18_resp_bits_pte_w), .io_requestor_18_resp_bits_pte_r (_ptw_io_requestor_18_resp_bits_pte_r), .io_requestor_18_resp_bits_pte_v (_ptw_io_requestor_18_resp_bits_pte_v), .io_requestor_18_resp_bits_level (_ptw_io_requestor_18_resp_bits_level), .io_requestor_18_resp_bits_homogeneous (_ptw_io_requestor_18_resp_bits_homogeneous), .io_requestor_18_resp_bits_gpa_valid (_ptw_io_requestor_18_resp_bits_gpa_valid), .io_requestor_18_resp_bits_gpa_bits (_ptw_io_requestor_18_resp_bits_gpa_bits), .io_requestor_18_resp_bits_gpa_is_pte (_ptw_io_requestor_18_resp_bits_gpa_is_pte), .io_requestor_18_ptbr_mode (_ptw_io_requestor_18_ptbr_mode), .io_requestor_18_ptbr_ppn (_ptw_io_requestor_18_ptbr_ppn), .io_requestor_18_status_debug (_ptw_io_requestor_18_status_debug), .io_requestor_18_status_cease (_ptw_io_requestor_18_status_cease), .io_requestor_18_status_wfi (_ptw_io_requestor_18_status_wfi), .io_requestor_18_status_isa (_ptw_io_requestor_18_status_isa), .io_requestor_18_status_dprv (_ptw_io_requestor_18_status_dprv), .io_requestor_18_status_dv (_ptw_io_requestor_18_status_dv), .io_requestor_18_status_prv (_ptw_io_requestor_18_status_prv), .io_requestor_18_status_v (_ptw_io_requestor_18_status_v), .io_requestor_18_status_mpv (_ptw_io_requestor_18_status_mpv), .io_requestor_18_status_gva (_ptw_io_requestor_18_status_gva), .io_requestor_18_status_tsr (_ptw_io_requestor_18_status_tsr), .io_requestor_18_status_tw (_ptw_io_requestor_18_status_tw), .io_requestor_18_status_tvm (_ptw_io_requestor_18_status_tvm), .io_requestor_18_status_mxr (_ptw_io_requestor_18_status_mxr), .io_requestor_18_status_sum (_ptw_io_requestor_18_status_sum), .io_requestor_18_status_mprv (_ptw_io_requestor_18_status_mprv), .io_requestor_18_status_fs (_ptw_io_requestor_18_status_fs), .io_requestor_18_status_mpp (_ptw_io_requestor_18_status_mpp), .io_requestor_18_status_spp (_ptw_io_requestor_18_status_spp), .io_requestor_18_status_mpie (_ptw_io_requestor_18_status_mpie), .io_requestor_18_status_spie (_ptw_io_requestor_18_status_spie), .io_requestor_18_status_mie (_ptw_io_requestor_18_status_mie), .io_requestor_18_status_sie (_ptw_io_requestor_18_status_sie), .io_requestor_18_hstatus_spvp (_ptw_io_requestor_18_hstatus_spvp), .io_requestor_18_hstatus_spv (_ptw_io_requestor_18_hstatus_spv), .io_requestor_18_hstatus_gva (_ptw_io_requestor_18_hstatus_gva), .io_requestor_18_gstatus_debug (_ptw_io_requestor_18_gstatus_debug), .io_requestor_18_gstatus_cease (_ptw_io_requestor_18_gstatus_cease), .io_requestor_18_gstatus_wfi (_ptw_io_requestor_18_gstatus_wfi), .io_requestor_18_gstatus_isa (_ptw_io_requestor_18_gstatus_isa), .io_requestor_18_gstatus_dprv (_ptw_io_requestor_18_gstatus_dprv), .io_requestor_18_gstatus_dv (_ptw_io_requestor_18_gstatus_dv), .io_requestor_18_gstatus_prv (_ptw_io_requestor_18_gstatus_prv), .io_requestor_18_gstatus_v (_ptw_io_requestor_18_gstatus_v), .io_requestor_18_gstatus_zero2 (_ptw_io_requestor_18_gstatus_zero2), .io_requestor_18_gstatus_mpv (_ptw_io_requestor_18_gstatus_mpv), .io_requestor_18_gstatus_gva (_ptw_io_requestor_18_gstatus_gva), .io_requestor_18_gstatus_mbe (_ptw_io_requestor_18_gstatus_mbe), .io_requestor_18_gstatus_sbe (_ptw_io_requestor_18_gstatus_sbe), .io_requestor_18_gstatus_sxl (_ptw_io_requestor_18_gstatus_sxl), .io_requestor_18_gstatus_zero1 (_ptw_io_requestor_18_gstatus_zero1), .io_requestor_18_gstatus_tsr (_ptw_io_requestor_18_gstatus_tsr), .io_requestor_18_gstatus_tw (_ptw_io_requestor_18_gstatus_tw), .io_requestor_18_gstatus_tvm (_ptw_io_requestor_18_gstatus_tvm), .io_requestor_18_gstatus_mxr (_ptw_io_requestor_18_gstatus_mxr), .io_requestor_18_gstatus_sum (_ptw_io_requestor_18_gstatus_sum), .io_requestor_18_gstatus_mprv (_ptw_io_requestor_18_gstatus_mprv), .io_requestor_18_gstatus_fs (_ptw_io_requestor_18_gstatus_fs), .io_requestor_18_gstatus_mpp (_ptw_io_requestor_18_gstatus_mpp), .io_requestor_18_gstatus_vs (_ptw_io_requestor_18_gstatus_vs), .io_requestor_18_gstatus_spp (_ptw_io_requestor_18_gstatus_spp), .io_requestor_18_gstatus_mpie (_ptw_io_requestor_18_gstatus_mpie), .io_requestor_18_gstatus_ube (_ptw_io_requestor_18_gstatus_ube), .io_requestor_18_gstatus_spie (_ptw_io_requestor_18_gstatus_spie), .io_requestor_18_gstatus_upie (_ptw_io_requestor_18_gstatus_upie), .io_requestor_18_gstatus_mie (_ptw_io_requestor_18_gstatus_mie), .io_requestor_18_gstatus_hie (_ptw_io_requestor_18_gstatus_hie), .io_requestor_18_gstatus_sie (_ptw_io_requestor_18_gstatus_sie), .io_requestor_18_gstatus_uie (_ptw_io_requestor_18_gstatus_uie), .io_requestor_18_pmp_0_cfg_l (_ptw_io_requestor_18_pmp_0_cfg_l), .io_requestor_18_pmp_0_cfg_a (_ptw_io_requestor_18_pmp_0_cfg_a), .io_requestor_18_pmp_0_cfg_x (_ptw_io_requestor_18_pmp_0_cfg_x), .io_requestor_18_pmp_0_cfg_w (_ptw_io_requestor_18_pmp_0_cfg_w), .io_requestor_18_pmp_0_cfg_r (_ptw_io_requestor_18_pmp_0_cfg_r), .io_requestor_18_pmp_0_addr (_ptw_io_requestor_18_pmp_0_addr), .io_requestor_18_pmp_0_mask (_ptw_io_requestor_18_pmp_0_mask), .io_requestor_18_pmp_1_cfg_l (_ptw_io_requestor_18_pmp_1_cfg_l), .io_requestor_18_pmp_1_cfg_a (_ptw_io_requestor_18_pmp_1_cfg_a), .io_requestor_18_pmp_1_cfg_x (_ptw_io_requestor_18_pmp_1_cfg_x), .io_requestor_18_pmp_1_cfg_w (_ptw_io_requestor_18_pmp_1_cfg_w), .io_requestor_18_pmp_1_cfg_r (_ptw_io_requestor_18_pmp_1_cfg_r), .io_requestor_18_pmp_1_addr (_ptw_io_requestor_18_pmp_1_addr), .io_requestor_18_pmp_1_mask (_ptw_io_requestor_18_pmp_1_mask), .io_requestor_18_pmp_2_cfg_l (_ptw_io_requestor_18_pmp_2_cfg_l), .io_requestor_18_pmp_2_cfg_a (_ptw_io_requestor_18_pmp_2_cfg_a), .io_requestor_18_pmp_2_cfg_x (_ptw_io_requestor_18_pmp_2_cfg_x), .io_requestor_18_pmp_2_cfg_w (_ptw_io_requestor_18_pmp_2_cfg_w), .io_requestor_18_pmp_2_cfg_r (_ptw_io_requestor_18_pmp_2_cfg_r), .io_requestor_18_pmp_2_addr (_ptw_io_requestor_18_pmp_2_addr), .io_requestor_18_pmp_2_mask (_ptw_io_requestor_18_pmp_2_mask), .io_requestor_18_pmp_3_cfg_l (_ptw_io_requestor_18_pmp_3_cfg_l), .io_requestor_18_pmp_3_cfg_a (_ptw_io_requestor_18_pmp_3_cfg_a), .io_requestor_18_pmp_3_cfg_x (_ptw_io_requestor_18_pmp_3_cfg_x), .io_requestor_18_pmp_3_cfg_w (_ptw_io_requestor_18_pmp_3_cfg_w), .io_requestor_18_pmp_3_cfg_r (_ptw_io_requestor_18_pmp_3_cfg_r), .io_requestor_18_pmp_3_addr (_ptw_io_requestor_18_pmp_3_addr), .io_requestor_18_pmp_3_mask (_ptw_io_requestor_18_pmp_3_mask), .io_requestor_18_pmp_4_cfg_l (_ptw_io_requestor_18_pmp_4_cfg_l), .io_requestor_18_pmp_4_cfg_a (_ptw_io_requestor_18_pmp_4_cfg_a), .io_requestor_18_pmp_4_cfg_x (_ptw_io_requestor_18_pmp_4_cfg_x), .io_requestor_18_pmp_4_cfg_w (_ptw_io_requestor_18_pmp_4_cfg_w), .io_requestor_18_pmp_4_cfg_r (_ptw_io_requestor_18_pmp_4_cfg_r), .io_requestor_18_pmp_4_addr (_ptw_io_requestor_18_pmp_4_addr), .io_requestor_18_pmp_4_mask (_ptw_io_requestor_18_pmp_4_mask), .io_requestor_18_pmp_5_cfg_l (_ptw_io_requestor_18_pmp_5_cfg_l), .io_requestor_18_pmp_5_cfg_a (_ptw_io_requestor_18_pmp_5_cfg_a), .io_requestor_18_pmp_5_cfg_x (_ptw_io_requestor_18_pmp_5_cfg_x), .io_requestor_18_pmp_5_cfg_w (_ptw_io_requestor_18_pmp_5_cfg_w), .io_requestor_18_pmp_5_cfg_r (_ptw_io_requestor_18_pmp_5_cfg_r), .io_requestor_18_pmp_5_addr (_ptw_io_requestor_18_pmp_5_addr), .io_requestor_18_pmp_5_mask (_ptw_io_requestor_18_pmp_5_mask), .io_requestor_18_pmp_6_cfg_l (_ptw_io_requestor_18_pmp_6_cfg_l), .io_requestor_18_pmp_6_cfg_a (_ptw_io_requestor_18_pmp_6_cfg_a), .io_requestor_18_pmp_6_cfg_x (_ptw_io_requestor_18_pmp_6_cfg_x), .io_requestor_18_pmp_6_cfg_w (_ptw_io_requestor_18_pmp_6_cfg_w), .io_requestor_18_pmp_6_cfg_r (_ptw_io_requestor_18_pmp_6_cfg_r), .io_requestor_18_pmp_6_addr (_ptw_io_requestor_18_pmp_6_addr), .io_requestor_18_pmp_6_mask (_ptw_io_requestor_18_pmp_6_mask), .io_requestor_18_pmp_7_cfg_l (_ptw_io_requestor_18_pmp_7_cfg_l), .io_requestor_18_pmp_7_cfg_a (_ptw_io_requestor_18_pmp_7_cfg_a), .io_requestor_18_pmp_7_cfg_x (_ptw_io_requestor_18_pmp_7_cfg_x), .io_requestor_18_pmp_7_cfg_w (_ptw_io_requestor_18_pmp_7_cfg_w), .io_requestor_18_pmp_7_cfg_r (_ptw_io_requestor_18_pmp_7_cfg_r), .io_requestor_18_pmp_7_addr (_ptw_io_requestor_18_pmp_7_addr), .io_requestor_18_pmp_7_mask (_ptw_io_requestor_18_pmp_7_mask), .io_requestor_18_customCSRs_csrs_0_ren (_ptw_io_requestor_18_customCSRs_csrs_0_ren), .io_requestor_18_customCSRs_csrs_0_wen (_ptw_io_requestor_18_customCSRs_csrs_0_wen), .io_requestor_18_customCSRs_csrs_0_wdata (_ptw_io_requestor_18_customCSRs_csrs_0_wdata), .io_requestor_18_customCSRs_csrs_0_value (_ptw_io_requestor_18_customCSRs_csrs_0_value), .io_requestor_18_customCSRs_csrs_1_ren (_ptw_io_requestor_18_customCSRs_csrs_1_ren), .io_requestor_18_customCSRs_csrs_1_wen (_ptw_io_requestor_18_customCSRs_csrs_1_wen), .io_requestor_18_customCSRs_csrs_1_wdata (_ptw_io_requestor_18_customCSRs_csrs_1_wdata), .io_requestor_18_customCSRs_csrs_1_value (_ptw_io_requestor_18_customCSRs_csrs_1_value), .io_requestor_18_customCSRs_csrs_2_ren (_ptw_io_requestor_18_customCSRs_csrs_2_ren), .io_requestor_18_customCSRs_csrs_2_wen (_ptw_io_requestor_18_customCSRs_csrs_2_wen), .io_requestor_18_customCSRs_csrs_2_wdata (_ptw_io_requestor_18_customCSRs_csrs_2_wdata), .io_requestor_18_customCSRs_csrs_2_value (_ptw_io_requestor_18_customCSRs_csrs_2_value), .io_requestor_18_customCSRs_csrs_3_ren (_ptw_io_requestor_18_customCSRs_csrs_3_ren), .io_requestor_18_customCSRs_csrs_3_wen (_ptw_io_requestor_18_customCSRs_csrs_3_wen), .io_requestor_18_customCSRs_csrs_3_wdata (_ptw_io_requestor_18_customCSRs_csrs_3_wdata), .io_requestor_18_customCSRs_csrs_3_value (_ptw_io_requestor_18_customCSRs_csrs_3_value), .io_requestor_19_req_ready (_ptw_io_requestor_19_req_ready), .io_requestor_19_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_19_resp_valid (_ptw_io_requestor_19_resp_valid), .io_requestor_19_resp_bits_ae_ptw (_ptw_io_requestor_19_resp_bits_ae_ptw), .io_requestor_19_resp_bits_ae_final (_ptw_io_requestor_19_resp_bits_ae_final), .io_requestor_19_resp_bits_pf (_ptw_io_requestor_19_resp_bits_pf), .io_requestor_19_resp_bits_gf (_ptw_io_requestor_19_resp_bits_gf), .io_requestor_19_resp_bits_hr (_ptw_io_requestor_19_resp_bits_hr), .io_requestor_19_resp_bits_hw (_ptw_io_requestor_19_resp_bits_hw), .io_requestor_19_resp_bits_hx (_ptw_io_requestor_19_resp_bits_hx), .io_requestor_19_resp_bits_pte_reserved_for_future (_ptw_io_requestor_19_resp_bits_pte_reserved_for_future), .io_requestor_19_resp_bits_pte_ppn (_ptw_io_requestor_19_resp_bits_pte_ppn), .io_requestor_19_resp_bits_pte_reserved_for_software (_ptw_io_requestor_19_resp_bits_pte_reserved_for_software), .io_requestor_19_resp_bits_pte_d (_ptw_io_requestor_19_resp_bits_pte_d), .io_requestor_19_resp_bits_pte_a (_ptw_io_requestor_19_resp_bits_pte_a), .io_requestor_19_resp_bits_pte_g (_ptw_io_requestor_19_resp_bits_pte_g), .io_requestor_19_resp_bits_pte_u (_ptw_io_requestor_19_resp_bits_pte_u), .io_requestor_19_resp_bits_pte_x (_ptw_io_requestor_19_resp_bits_pte_x), .io_requestor_19_resp_bits_pte_w (_ptw_io_requestor_19_resp_bits_pte_w), .io_requestor_19_resp_bits_pte_r (_ptw_io_requestor_19_resp_bits_pte_r), .io_requestor_19_resp_bits_pte_v (_ptw_io_requestor_19_resp_bits_pte_v), .io_requestor_19_resp_bits_level (_ptw_io_requestor_19_resp_bits_level), .io_requestor_19_resp_bits_homogeneous (_ptw_io_requestor_19_resp_bits_homogeneous), .io_requestor_19_resp_bits_gpa_valid (_ptw_io_requestor_19_resp_bits_gpa_valid), .io_requestor_19_resp_bits_gpa_bits (_ptw_io_requestor_19_resp_bits_gpa_bits), .io_requestor_19_resp_bits_gpa_is_pte (_ptw_io_requestor_19_resp_bits_gpa_is_pte), .io_requestor_19_ptbr_mode (_ptw_io_requestor_19_ptbr_mode), .io_requestor_19_ptbr_ppn (_ptw_io_requestor_19_ptbr_ppn), .io_requestor_19_status_debug (_ptw_io_requestor_19_status_debug), .io_requestor_19_status_cease (_ptw_io_requestor_19_status_cease), .io_requestor_19_status_wfi (_ptw_io_requestor_19_status_wfi), .io_requestor_19_status_isa (_ptw_io_requestor_19_status_isa), .io_requestor_19_status_dprv (_ptw_io_requestor_19_status_dprv), .io_requestor_19_status_dv (_ptw_io_requestor_19_status_dv), .io_requestor_19_status_prv (_ptw_io_requestor_19_status_prv), .io_requestor_19_status_v (_ptw_io_requestor_19_status_v), .io_requestor_19_status_mpv (_ptw_io_requestor_19_status_mpv), .io_requestor_19_status_gva (_ptw_io_requestor_19_status_gva), .io_requestor_19_status_tsr (_ptw_io_requestor_19_status_tsr), .io_requestor_19_status_tw (_ptw_io_requestor_19_status_tw), .io_requestor_19_status_tvm (_ptw_io_requestor_19_status_tvm), .io_requestor_19_status_mxr (_ptw_io_requestor_19_status_mxr), .io_requestor_19_status_sum (_ptw_io_requestor_19_status_sum), .io_requestor_19_status_mprv (_ptw_io_requestor_19_status_mprv), .io_requestor_19_status_fs (_ptw_io_requestor_19_status_fs), .io_requestor_19_status_mpp (_ptw_io_requestor_19_status_mpp), .io_requestor_19_status_spp (_ptw_io_requestor_19_status_spp), .io_requestor_19_status_mpie (_ptw_io_requestor_19_status_mpie), .io_requestor_19_status_spie (_ptw_io_requestor_19_status_spie), .io_requestor_19_status_mie (_ptw_io_requestor_19_status_mie), .io_requestor_19_status_sie (_ptw_io_requestor_19_status_sie), .io_requestor_19_hstatus_spvp (_ptw_io_requestor_19_hstatus_spvp), .io_requestor_19_hstatus_spv (_ptw_io_requestor_19_hstatus_spv), .io_requestor_19_hstatus_gva (_ptw_io_requestor_19_hstatus_gva), .io_requestor_19_gstatus_debug (_ptw_io_requestor_19_gstatus_debug), .io_requestor_19_gstatus_cease (_ptw_io_requestor_19_gstatus_cease), .io_requestor_19_gstatus_wfi (_ptw_io_requestor_19_gstatus_wfi), .io_requestor_19_gstatus_isa (_ptw_io_requestor_19_gstatus_isa), .io_requestor_19_gstatus_dprv (_ptw_io_requestor_19_gstatus_dprv), .io_requestor_19_gstatus_dv (_ptw_io_requestor_19_gstatus_dv), .io_requestor_19_gstatus_prv (_ptw_io_requestor_19_gstatus_prv), .io_requestor_19_gstatus_v (_ptw_io_requestor_19_gstatus_v), .io_requestor_19_gstatus_zero2 (_ptw_io_requestor_19_gstatus_zero2), .io_requestor_19_gstatus_mpv (_ptw_io_requestor_19_gstatus_mpv), .io_requestor_19_gstatus_gva (_ptw_io_requestor_19_gstatus_gva), .io_requestor_19_gstatus_mbe (_ptw_io_requestor_19_gstatus_mbe), .io_requestor_19_gstatus_sbe (_ptw_io_requestor_19_gstatus_sbe), .io_requestor_19_gstatus_sxl (_ptw_io_requestor_19_gstatus_sxl), .io_requestor_19_gstatus_zero1 (_ptw_io_requestor_19_gstatus_zero1), .io_requestor_19_gstatus_tsr (_ptw_io_requestor_19_gstatus_tsr), .io_requestor_19_gstatus_tw (_ptw_io_requestor_19_gstatus_tw), .io_requestor_19_gstatus_tvm (_ptw_io_requestor_19_gstatus_tvm), .io_requestor_19_gstatus_mxr (_ptw_io_requestor_19_gstatus_mxr), .io_requestor_19_gstatus_sum (_ptw_io_requestor_19_gstatus_sum), .io_requestor_19_gstatus_mprv (_ptw_io_requestor_19_gstatus_mprv), .io_requestor_19_gstatus_fs (_ptw_io_requestor_19_gstatus_fs), .io_requestor_19_gstatus_mpp (_ptw_io_requestor_19_gstatus_mpp), .io_requestor_19_gstatus_vs (_ptw_io_requestor_19_gstatus_vs), .io_requestor_19_gstatus_spp (_ptw_io_requestor_19_gstatus_spp), .io_requestor_19_gstatus_mpie (_ptw_io_requestor_19_gstatus_mpie), .io_requestor_19_gstatus_ube (_ptw_io_requestor_19_gstatus_ube), .io_requestor_19_gstatus_spie (_ptw_io_requestor_19_gstatus_spie), .io_requestor_19_gstatus_upie (_ptw_io_requestor_19_gstatus_upie), .io_requestor_19_gstatus_mie (_ptw_io_requestor_19_gstatus_mie), .io_requestor_19_gstatus_hie (_ptw_io_requestor_19_gstatus_hie), .io_requestor_19_gstatus_sie (_ptw_io_requestor_19_gstatus_sie), .io_requestor_19_gstatus_uie (_ptw_io_requestor_19_gstatus_uie), .io_requestor_19_pmp_0_cfg_l (_ptw_io_requestor_19_pmp_0_cfg_l), .io_requestor_19_pmp_0_cfg_a (_ptw_io_requestor_19_pmp_0_cfg_a), .io_requestor_19_pmp_0_cfg_x (_ptw_io_requestor_19_pmp_0_cfg_x), .io_requestor_19_pmp_0_cfg_w (_ptw_io_requestor_19_pmp_0_cfg_w), .io_requestor_19_pmp_0_cfg_r (_ptw_io_requestor_19_pmp_0_cfg_r), .io_requestor_19_pmp_0_addr (_ptw_io_requestor_19_pmp_0_addr), .io_requestor_19_pmp_0_mask (_ptw_io_requestor_19_pmp_0_mask), .io_requestor_19_pmp_1_cfg_l (_ptw_io_requestor_19_pmp_1_cfg_l), .io_requestor_19_pmp_1_cfg_a (_ptw_io_requestor_19_pmp_1_cfg_a), .io_requestor_19_pmp_1_cfg_x (_ptw_io_requestor_19_pmp_1_cfg_x), .io_requestor_19_pmp_1_cfg_w (_ptw_io_requestor_19_pmp_1_cfg_w), .io_requestor_19_pmp_1_cfg_r (_ptw_io_requestor_19_pmp_1_cfg_r), .io_requestor_19_pmp_1_addr (_ptw_io_requestor_19_pmp_1_addr), .io_requestor_19_pmp_1_mask (_ptw_io_requestor_19_pmp_1_mask), .io_requestor_19_pmp_2_cfg_l (_ptw_io_requestor_19_pmp_2_cfg_l), .io_requestor_19_pmp_2_cfg_a (_ptw_io_requestor_19_pmp_2_cfg_a), .io_requestor_19_pmp_2_cfg_x (_ptw_io_requestor_19_pmp_2_cfg_x), .io_requestor_19_pmp_2_cfg_w (_ptw_io_requestor_19_pmp_2_cfg_w), .io_requestor_19_pmp_2_cfg_r (_ptw_io_requestor_19_pmp_2_cfg_r), .io_requestor_19_pmp_2_addr (_ptw_io_requestor_19_pmp_2_addr), .io_requestor_19_pmp_2_mask (_ptw_io_requestor_19_pmp_2_mask), .io_requestor_19_pmp_3_cfg_l (_ptw_io_requestor_19_pmp_3_cfg_l), .io_requestor_19_pmp_3_cfg_a (_ptw_io_requestor_19_pmp_3_cfg_a), .io_requestor_19_pmp_3_cfg_x (_ptw_io_requestor_19_pmp_3_cfg_x), .io_requestor_19_pmp_3_cfg_w (_ptw_io_requestor_19_pmp_3_cfg_w), .io_requestor_19_pmp_3_cfg_r (_ptw_io_requestor_19_pmp_3_cfg_r), .io_requestor_19_pmp_3_addr (_ptw_io_requestor_19_pmp_3_addr), .io_requestor_19_pmp_3_mask (_ptw_io_requestor_19_pmp_3_mask), .io_requestor_19_pmp_4_cfg_l (_ptw_io_requestor_19_pmp_4_cfg_l), .io_requestor_19_pmp_4_cfg_a (_ptw_io_requestor_19_pmp_4_cfg_a), .io_requestor_19_pmp_4_cfg_x (_ptw_io_requestor_19_pmp_4_cfg_x), .io_requestor_19_pmp_4_cfg_w (_ptw_io_requestor_19_pmp_4_cfg_w), .io_requestor_19_pmp_4_cfg_r (_ptw_io_requestor_19_pmp_4_cfg_r), .io_requestor_19_pmp_4_addr (_ptw_io_requestor_19_pmp_4_addr), .io_requestor_19_pmp_4_mask (_ptw_io_requestor_19_pmp_4_mask), .io_requestor_19_pmp_5_cfg_l (_ptw_io_requestor_19_pmp_5_cfg_l), .io_requestor_19_pmp_5_cfg_a (_ptw_io_requestor_19_pmp_5_cfg_a), .io_requestor_19_pmp_5_cfg_x (_ptw_io_requestor_19_pmp_5_cfg_x), .io_requestor_19_pmp_5_cfg_w (_ptw_io_requestor_19_pmp_5_cfg_w), .io_requestor_19_pmp_5_cfg_r (_ptw_io_requestor_19_pmp_5_cfg_r), .io_requestor_19_pmp_5_addr (_ptw_io_requestor_19_pmp_5_addr), .io_requestor_19_pmp_5_mask (_ptw_io_requestor_19_pmp_5_mask), .io_requestor_19_pmp_6_cfg_l (_ptw_io_requestor_19_pmp_6_cfg_l), .io_requestor_19_pmp_6_cfg_a (_ptw_io_requestor_19_pmp_6_cfg_a), .io_requestor_19_pmp_6_cfg_x (_ptw_io_requestor_19_pmp_6_cfg_x), .io_requestor_19_pmp_6_cfg_w (_ptw_io_requestor_19_pmp_6_cfg_w), .io_requestor_19_pmp_6_cfg_r (_ptw_io_requestor_19_pmp_6_cfg_r), .io_requestor_19_pmp_6_addr (_ptw_io_requestor_19_pmp_6_addr), .io_requestor_19_pmp_6_mask (_ptw_io_requestor_19_pmp_6_mask), .io_requestor_19_pmp_7_cfg_l (_ptw_io_requestor_19_pmp_7_cfg_l), .io_requestor_19_pmp_7_cfg_a (_ptw_io_requestor_19_pmp_7_cfg_a), .io_requestor_19_pmp_7_cfg_x (_ptw_io_requestor_19_pmp_7_cfg_x), .io_requestor_19_pmp_7_cfg_w (_ptw_io_requestor_19_pmp_7_cfg_w), .io_requestor_19_pmp_7_cfg_r (_ptw_io_requestor_19_pmp_7_cfg_r), .io_requestor_19_pmp_7_addr (_ptw_io_requestor_19_pmp_7_addr), .io_requestor_19_pmp_7_mask (_ptw_io_requestor_19_pmp_7_mask), .io_requestor_19_customCSRs_csrs_0_ren (_ptw_io_requestor_19_customCSRs_csrs_0_ren), .io_requestor_19_customCSRs_csrs_0_wen (_ptw_io_requestor_19_customCSRs_csrs_0_wen), .io_requestor_19_customCSRs_csrs_0_wdata (_ptw_io_requestor_19_customCSRs_csrs_0_wdata), .io_requestor_19_customCSRs_csrs_0_value (_ptw_io_requestor_19_customCSRs_csrs_0_value), .io_requestor_19_customCSRs_csrs_1_ren (_ptw_io_requestor_19_customCSRs_csrs_1_ren), .io_requestor_19_customCSRs_csrs_1_wen (_ptw_io_requestor_19_customCSRs_csrs_1_wen), .io_requestor_19_customCSRs_csrs_1_wdata (_ptw_io_requestor_19_customCSRs_csrs_1_wdata), .io_requestor_19_customCSRs_csrs_1_value (_ptw_io_requestor_19_customCSRs_csrs_1_value), .io_requestor_19_customCSRs_csrs_2_ren (_ptw_io_requestor_19_customCSRs_csrs_2_ren), .io_requestor_19_customCSRs_csrs_2_wen (_ptw_io_requestor_19_customCSRs_csrs_2_wen), .io_requestor_19_customCSRs_csrs_2_wdata (_ptw_io_requestor_19_customCSRs_csrs_2_wdata), .io_requestor_19_customCSRs_csrs_2_value (_ptw_io_requestor_19_customCSRs_csrs_2_value), .io_requestor_19_customCSRs_csrs_3_ren (_ptw_io_requestor_19_customCSRs_csrs_3_ren), .io_requestor_19_customCSRs_csrs_3_wen (_ptw_io_requestor_19_customCSRs_csrs_3_wen), .io_requestor_19_customCSRs_csrs_3_wdata (_ptw_io_requestor_19_customCSRs_csrs_3_wdata), .io_requestor_19_customCSRs_csrs_3_value (_ptw_io_requestor_19_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] RRArbiter respArb ( // @[LazyRoCC.scala:101:25] .clock (clock), .reset (reset), .io_in_0_ready (_respArb_io_in_0_ready), .io_in_0_valid (_respArb_io_in_0_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_0_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd), // @[Decoupled.scala:362:21] .io_in_0_bits_data (_respArb_io_in_0_q_io_deq_bits_data), // @[Decoupled.scala:362:21] .io_out_ready (_core_io_rocc_resp_ready), // @[RocketTile.scala:147:20] .io_out_valid (_respArb_io_out_valid), .io_out_bits_rd (_respArb_io_out_bits_rd), .io_out_bits_data (_respArb_io_out_bits_data) ); // @[LazyRoCC.scala:101:25] RoccCommandRouter cmdRouter ( // @[LazyRoCC.scala:102:27] .clock (clock), .reset (reset), .io_in_ready (_cmdRouter_io_in_ready), .io_in_valid (_core_io_rocc_cmd_valid), // @[RocketTile.scala:147:20] .io_in_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct), // @[RocketTile.scala:147:20] .io_in_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2), // @[RocketTile.scala:147:20] .io_in_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1), // @[RocketTile.scala:147:20] .io_in_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd), // @[RocketTile.scala:147:20] .io_in_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1), // @[RocketTile.scala:147:20] .io_in_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2), // @[RocketTile.scala:147:20] .io_in_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd), // @[RocketTile.scala:147:20] .io_in_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode), // @[RocketTile.scala:147:20] .io_in_bits_rs1 (_core_io_rocc_cmd_bits_rs1), // @[RocketTile.scala:147:20] .io_in_bits_rs2 (_core_io_rocc_cmd_bits_rs2), // @[RocketTile.scala:147:20] .io_in_bits_status_debug (_core_io_rocc_cmd_bits_status_debug), // @[RocketTile.scala:147:20] .io_in_bits_status_cease (_core_io_rocc_cmd_bits_status_cease), // @[RocketTile.scala:147:20] .io_in_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi), // @[RocketTile.scala:147:20] .io_in_bits_status_isa (_core_io_rocc_cmd_bits_status_isa), // @[RocketTile.scala:147:20] .io_in_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv), // @[RocketTile.scala:147:20] .io_in_bits_status_dv (_core_io_rocc_cmd_bits_status_dv), // @[RocketTile.scala:147:20] .io_in_bits_status_prv (_core_io_rocc_cmd_bits_status_prv), // @[RocketTile.scala:147:20] .io_in_bits_status_v (_core_io_rocc_cmd_bits_status_v), // @[RocketTile.scala:147:20] .io_in_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv), // @[RocketTile.scala:147:20] .io_in_bits_status_gva (_core_io_rocc_cmd_bits_status_gva), // @[RocketTile.scala:147:20] .io_in_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr), // @[RocketTile.scala:147:20] .io_in_bits_status_tw (_core_io_rocc_cmd_bits_status_tw), // @[RocketTile.scala:147:20] .io_in_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm), // @[RocketTile.scala:147:20] .io_in_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr), // @[RocketTile.scala:147:20] .io_in_bits_status_sum (_core_io_rocc_cmd_bits_status_sum), // @[RocketTile.scala:147:20] .io_in_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv), // @[RocketTile.scala:147:20] .io_in_bits_status_fs (_core_io_rocc_cmd_bits_status_fs), // @[RocketTile.scala:147:20] .io_in_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp), // @[RocketTile.scala:147:20] .io_in_bits_status_spp (_core_io_rocc_cmd_bits_status_spp), // @[RocketTile.scala:147:20] .io_in_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie), // @[RocketTile.scala:147:20] .io_in_bits_status_spie (_core_io_rocc_cmd_bits_status_spie), // @[RocketTile.scala:147:20] .io_in_bits_status_mie (_core_io_rocc_cmd_bits_status_mie), // @[RocketTile.scala:147:20] .io_in_bits_status_sie (_core_io_rocc_cmd_bits_status_sie), // @[RocketTile.scala:147:20] .io_out_0_ready (_zstd_compressor_io_cmd_ready), // @[Configs.scala:62:39] .io_out_0_valid (_cmdRouter_io_out_0_valid), .io_out_0_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct), .io_out_0_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2), .io_out_0_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1), .io_out_0_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd), .io_out_0_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1), .io_out_0_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2), .io_out_0_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd), .io_out_0_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode), .io_out_0_bits_rs1 (_cmdRouter_io_out_0_bits_rs1), .io_out_0_bits_rs2 (_cmdRouter_io_out_0_bits_rs2), .io_out_0_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug), .io_out_0_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease), .io_out_0_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi), .io_out_0_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa), .io_out_0_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv), .io_out_0_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv), .io_out_0_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv), .io_out_0_bits_status_v (_cmdRouter_io_out_0_bits_status_v), .io_out_0_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd), .io_out_0_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2), .io_out_0_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv), .io_out_0_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva), .io_out_0_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe), .io_out_0_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe), .io_out_0_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl), .io_out_0_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl), .io_out_0_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32), .io_out_0_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1), .io_out_0_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr), .io_out_0_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw), .io_out_0_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm), .io_out_0_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr), .io_out_0_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum), .io_out_0_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv), .io_out_0_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs), .io_out_0_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs), .io_out_0_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp), .io_out_0_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs), .io_out_0_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp), .io_out_0_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie), .io_out_0_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube), .io_out_0_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie), .io_out_0_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie), .io_out_0_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie), .io_out_0_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie), .io_out_0_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie), .io_out_0_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie), .io_busy (_core_io_rocc_busy_T) ); // @[LazyRoCC.scala:102:27] SimpleHellaCacheIF dcIF ( // @[LazyRoCC.scala:106:24] .clock (clock), .reset (reset), .io_requestor_req_ready (_dcIF_io_requestor_req_ready), .io_requestor_resp_valid (_dcIF_io_requestor_resp_valid), .io_requestor_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr), .io_requestor_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag), .io_requestor_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd), .io_requestor_resp_bits_size (_dcIF_io_requestor_resp_bits_size), .io_requestor_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed), .io_requestor_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv), .io_requestor_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv), .io_requestor_resp_bits_data (_dcIF_io_requestor_resp_bits_data), .io_requestor_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask), .io_requestor_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay), .io_requestor_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data), .io_requestor_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass), .io_requestor_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw), .io_requestor_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data), .io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_cache_req_valid (_dcIF_io_cache_req_valid), .io_cache_s1_data_data (_dcIF_io_cache_s1_data_data), .io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask), .io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[HellaCache.scala:292:25] ); // @[LazyRoCC.scala:106:24] Queue2_RoCCResponse respArb_io_in_0_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_respArb_io_in_0_q_io_enq_ready), .io_enq_valid (_zstd_compressor_io_resp_valid), // @[Configs.scala:62:39] .io_enq_bits_rd (_zstd_compressor_io_resp_bits_rd), // @[Configs.scala:62:39] .io_enq_bits_data (_zstd_compressor_io_resp_bits_data), // @[Configs.scala:62:39] .io_deq_ready (_respArb_io_in_0_ready), // @[LazyRoCC.scala:101:25] .io_deq_valid (_respArb_io_in_0_q_io_deq_valid), .io_deq_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd), .io_deq_bits_data (_respArb_io_in_0_q_io_deq_bits_data) ); // @[Decoupled.scala:362:21] Rocket core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_2_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_2_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_2_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_2_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_2_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_2_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_2_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_2_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_rocc_cmd_ready (_cmdRouter_io_in_ready), // @[LazyRoCC.scala:102:27] .io_rocc_cmd_valid (_core_io_rocc_cmd_valid), .io_rocc_cmd_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct), .io_rocc_cmd_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2), .io_rocc_cmd_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1), .io_rocc_cmd_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd), .io_rocc_cmd_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1), .io_rocc_cmd_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2), .io_rocc_cmd_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd), .io_rocc_cmd_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode), .io_rocc_cmd_bits_rs1 (_core_io_rocc_cmd_bits_rs1), .io_rocc_cmd_bits_rs2 (_core_io_rocc_cmd_bits_rs2), .io_rocc_cmd_bits_status_debug (_core_io_rocc_cmd_bits_status_debug), .io_rocc_cmd_bits_status_cease (_core_io_rocc_cmd_bits_status_cease), .io_rocc_cmd_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi), .io_rocc_cmd_bits_status_isa (_core_io_rocc_cmd_bits_status_isa), .io_rocc_cmd_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv), .io_rocc_cmd_bits_status_dv (_core_io_rocc_cmd_bits_status_dv), .io_rocc_cmd_bits_status_prv (_core_io_rocc_cmd_bits_status_prv), .io_rocc_cmd_bits_status_v (_core_io_rocc_cmd_bits_status_v), .io_rocc_cmd_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv), .io_rocc_cmd_bits_status_gva (_core_io_rocc_cmd_bits_status_gva), .io_rocc_cmd_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr), .io_rocc_cmd_bits_status_tw (_core_io_rocc_cmd_bits_status_tw), .io_rocc_cmd_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm), .io_rocc_cmd_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr), .io_rocc_cmd_bits_status_sum (_core_io_rocc_cmd_bits_status_sum), .io_rocc_cmd_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv), .io_rocc_cmd_bits_status_fs (_core_io_rocc_cmd_bits_status_fs), .io_rocc_cmd_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp), .io_rocc_cmd_bits_status_spp (_core_io_rocc_cmd_bits_status_spp), .io_rocc_cmd_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie), .io_rocc_cmd_bits_status_spie (_core_io_rocc_cmd_bits_status_spie), .io_rocc_cmd_bits_status_mie (_core_io_rocc_cmd_bits_status_mie), .io_rocc_cmd_bits_status_sie (_core_io_rocc_cmd_bits_status_sie), .io_rocc_resp_ready (_core_io_rocc_resp_ready), .io_rocc_resp_valid (_respArb_io_out_valid), // @[LazyRoCC.scala:101:25] .io_rocc_resp_bits_rd (_respArb_io_out_bits_rd), // @[LazyRoCC.scala:101:25] .io_rocc_resp_bits_data (_respArb_io_out_bits_data), // @[LazyRoCC.scala:101:25] .io_rocc_busy (_core_io_rocc_busy_T), // @[RocketTile.scala:213:49] .io_rocc_exception (_core_io_rocc_exception), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_18_a_valid = auto_buffer_out_18_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_opcode = auto_buffer_out_18_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_param = auto_buffer_out_18_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_size = auto_buffer_out_18_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_source = auto_buffer_out_18_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_address = auto_buffer_out_18_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_mask = auto_buffer_out_18_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_data = auto_buffer_out_18_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_b_ready = auto_buffer_out_18_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_valid = auto_buffer_out_18_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_opcode = auto_buffer_out_18_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_param = auto_buffer_out_18_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_size = auto_buffer_out_18_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_source = auto_buffer_out_18_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_address = auto_buffer_out_18_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_data = auto_buffer_out_18_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_d_ready = auto_buffer_out_18_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_e_valid = auto_buffer_out_18_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_e_bits_sink = auto_buffer_out_18_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_valid = auto_buffer_out_17_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_opcode = auto_buffer_out_17_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_param = auto_buffer_out_17_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_size = auto_buffer_out_17_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_source = auto_buffer_out_17_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_address = auto_buffer_out_17_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_mask = auto_buffer_out_17_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_data = auto_buffer_out_17_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_corrupt = auto_buffer_out_17_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_d_ready = auto_buffer_out_17_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_valid = auto_buffer_out_16_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_opcode = auto_buffer_out_16_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_param = auto_buffer_out_16_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_size = auto_buffer_out_16_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_source = auto_buffer_out_16_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_address = auto_buffer_out_16_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_mask = auto_buffer_out_16_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_data = auto_buffer_out_16_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_corrupt = auto_buffer_out_16_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_d_ready = auto_buffer_out_16_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_valid = auto_buffer_out_15_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_opcode = auto_buffer_out_15_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_param = auto_buffer_out_15_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_size = auto_buffer_out_15_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_source = auto_buffer_out_15_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_address = auto_buffer_out_15_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_mask = auto_buffer_out_15_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_data = auto_buffer_out_15_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_corrupt = auto_buffer_out_15_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_d_ready = auto_buffer_out_15_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_valid = auto_buffer_out_14_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_opcode = auto_buffer_out_14_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_param = auto_buffer_out_14_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_size = auto_buffer_out_14_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_source = auto_buffer_out_14_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_address = auto_buffer_out_14_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_mask = auto_buffer_out_14_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_data = auto_buffer_out_14_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_corrupt = auto_buffer_out_14_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_d_ready = auto_buffer_out_14_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_valid = auto_buffer_out_13_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_opcode = auto_buffer_out_13_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_param = auto_buffer_out_13_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_size = auto_buffer_out_13_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_source = auto_buffer_out_13_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_address = auto_buffer_out_13_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_mask = auto_buffer_out_13_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_data = auto_buffer_out_13_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_corrupt = auto_buffer_out_13_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_d_ready = auto_buffer_out_13_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_valid = auto_buffer_out_12_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_opcode = auto_buffer_out_12_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_param = auto_buffer_out_12_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_size = auto_buffer_out_12_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_source = auto_buffer_out_12_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_address = auto_buffer_out_12_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_mask = auto_buffer_out_12_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_data = auto_buffer_out_12_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_corrupt = auto_buffer_out_12_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_d_ready = auto_buffer_out_12_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_valid = auto_buffer_out_11_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_opcode = auto_buffer_out_11_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_param = auto_buffer_out_11_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_size = auto_buffer_out_11_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_source = auto_buffer_out_11_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_address = auto_buffer_out_11_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_mask = auto_buffer_out_11_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_data = auto_buffer_out_11_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_corrupt = auto_buffer_out_11_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_d_ready = auto_buffer_out_11_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_valid = auto_buffer_out_10_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_opcode = auto_buffer_out_10_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_param = auto_buffer_out_10_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_size = auto_buffer_out_10_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_source = auto_buffer_out_10_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_address = auto_buffer_out_10_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_mask = auto_buffer_out_10_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_data = auto_buffer_out_10_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_corrupt = auto_buffer_out_10_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_d_ready = auto_buffer_out_10_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_valid = auto_buffer_out_9_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_opcode = auto_buffer_out_9_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_param = auto_buffer_out_9_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_size = auto_buffer_out_9_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_source = auto_buffer_out_9_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_address = auto_buffer_out_9_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_mask = auto_buffer_out_9_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_data = auto_buffer_out_9_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_corrupt = auto_buffer_out_9_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_d_ready = auto_buffer_out_9_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_valid = auto_buffer_out_8_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_opcode = auto_buffer_out_8_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_param = auto_buffer_out_8_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_size = auto_buffer_out_8_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_source = auto_buffer_out_8_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_address = auto_buffer_out_8_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_mask = auto_buffer_out_8_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_data = auto_buffer_out_8_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_corrupt = auto_buffer_out_8_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_d_ready = auto_buffer_out_8_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_valid = auto_buffer_out_7_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_opcode = auto_buffer_out_7_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_param = auto_buffer_out_7_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_size = auto_buffer_out_7_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_source = auto_buffer_out_7_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_address = auto_buffer_out_7_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_mask = auto_buffer_out_7_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_data = auto_buffer_out_7_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_corrupt = auto_buffer_out_7_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_d_ready = auto_buffer_out_7_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_valid = auto_buffer_out_6_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_opcode = auto_buffer_out_6_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_param = auto_buffer_out_6_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_size = auto_buffer_out_6_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_source = auto_buffer_out_6_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_address = auto_buffer_out_6_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_mask = auto_buffer_out_6_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_data = auto_buffer_out_6_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_corrupt = auto_buffer_out_6_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_d_ready = auto_buffer_out_6_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_valid = auto_buffer_out_5_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_opcode = auto_buffer_out_5_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_param = auto_buffer_out_5_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_size = auto_buffer_out_5_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_source = auto_buffer_out_5_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_address = auto_buffer_out_5_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_mask = auto_buffer_out_5_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_data = auto_buffer_out_5_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_corrupt = auto_buffer_out_5_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_d_ready = auto_buffer_out_5_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_valid = auto_buffer_out_4_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_opcode = auto_buffer_out_4_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_param = auto_buffer_out_4_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_size = auto_buffer_out_4_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_source = auto_buffer_out_4_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_address = auto_buffer_out_4_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_mask = auto_buffer_out_4_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_data = auto_buffer_out_4_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_corrupt = auto_buffer_out_4_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_d_ready = auto_buffer_out_4_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_valid = auto_buffer_out_3_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_opcode = auto_buffer_out_3_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_param = auto_buffer_out_3_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_size = auto_buffer_out_3_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_source = auto_buffer_out_3_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_address = auto_buffer_out_3_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_mask = auto_buffer_out_3_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_data = auto_buffer_out_3_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_corrupt = auto_buffer_out_3_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_d_ready = auto_buffer_out_3_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_valid = auto_buffer_out_2_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_opcode = auto_buffer_out_2_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_param = auto_buffer_out_2_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_size = auto_buffer_out_2_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_source = auto_buffer_out_2_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_address = auto_buffer_out_2_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_mask = auto_buffer_out_2_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_data = auto_buffer_out_2_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_corrupt = auto_buffer_out_2_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_d_ready = auto_buffer_out_2_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_valid = auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_opcode = auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_param = auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_size = auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_source = auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_address = auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_mask = auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_data = auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_corrupt = auto_buffer_out_1_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_d_ready = auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_valid = auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_opcode = auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_param = auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_size = auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_source = auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_address = auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_mask = auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_data = auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_corrupt = auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_d_ready = auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BankedStore : input clock : Clock input reset : Reset output io : { flip sinkC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, flip sinkC_dat : { data : UInt<128>}, flip sinkD_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkD_dat : { data : UInt<64>}, flip sourceC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceC_dat : { data : UInt<64>}, flip sourceD_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, sourceD_rdat : { data : UInt<128>}, flip sourceD_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, flip sourceD_wdat : { data : UInt<128>}} smem cc_banks_0 : UInt<64> [8192] smem cc_banks_1 : UInt<64> [8192] smem cc_banks_2 : UInt<64> [8192] smem cc_banks_3 : UInt<64> [8192] smem cc_banks_4 : UInt<64> [8192] smem cc_banks_5 : UInt<64> [8192] smem cc_banks_6 : UInt<64> [8192] smem cc_banks_7 : UInt<64> [8192] node sinkC_req_words_0 = bits(io.sinkC_dat.data, 63, 0) node sinkC_req_words_1 = bits(io.sinkC_dat.data, 127, 64) node sinkC_req_a_hi = cat(io.sinkC_adr.bits.way, io.sinkC_adr.bits.set) node sinkC_req_a = cat(sinkC_req_a_hi, io.sinkC_adr.bits.beat) wire sinkC_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkC_req_select_T = bits(sinkC_req_a, 1, 0) node sinkC_req_select_shiftAmount = bits(_sinkC_req_select_T, 1, 0) node _sinkC_req_select_T_1 = dshl(UInt<1>(0h1), sinkC_req_select_shiftAmount) node sinkC_req_select = bits(_sinkC_req_select_T_1, 3, 0) node _sinkC_req_ready_T = bits(sinkC_req.bankSum, 1, 0) node _sinkC_req_ready_T_1 = and(_sinkC_req_ready_T, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_2 = orr(_sinkC_req_ready_T_1) node _sinkC_req_ready_T_3 = eq(_sinkC_req_ready_T_2, UInt<1>(0h0)) node _sinkC_req_ready_T_4 = bits(sinkC_req.bankSum, 3, 2) node _sinkC_req_ready_T_5 = and(_sinkC_req_ready_T_4, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_6 = orr(_sinkC_req_ready_T_5) node _sinkC_req_ready_T_7 = eq(_sinkC_req_ready_T_6, UInt<1>(0h0)) node _sinkC_req_ready_T_8 = bits(sinkC_req.bankSum, 5, 4) node _sinkC_req_ready_T_9 = and(_sinkC_req_ready_T_8, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_10 = orr(_sinkC_req_ready_T_9) node _sinkC_req_ready_T_11 = eq(_sinkC_req_ready_T_10, UInt<1>(0h0)) node _sinkC_req_ready_T_12 = bits(sinkC_req.bankSum, 7, 6) node _sinkC_req_ready_T_13 = and(_sinkC_req_ready_T_12, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_14 = orr(_sinkC_req_ready_T_13) node _sinkC_req_ready_T_15 = eq(_sinkC_req_ready_T_14, UInt<1>(0h0)) node sinkC_req_ready_lo = cat(_sinkC_req_ready_T_7, _sinkC_req_ready_T_3) node sinkC_req_ready_hi = cat(_sinkC_req_ready_T_15, _sinkC_req_ready_T_11) node sinkC_req_ready = cat(sinkC_req_ready_hi, sinkC_req_ready_lo) node _sinkC_req_io_sinkC_adr_ready_T = bits(sinkC_req_a, 1, 0) node _sinkC_req_io_sinkC_adr_ready_T_1 = dshr(sinkC_req_ready, _sinkC_req_io_sinkC_adr_ready_T) node _sinkC_req_io_sinkC_adr_ready_T_2 = bits(_sinkC_req_io_sinkC_adr_ready_T_1, 0, 0) connect io.sinkC_adr.ready, _sinkC_req_io_sinkC_adr_ready_T_2 connect sinkC_req.wen, UInt<1>(0h1) node _sinkC_req_out_index_T = shr(sinkC_req_a, 2) connect sinkC_req.index, _sinkC_req_out_index_T node _sinkC_req_out_bankSel_T = bits(sinkC_req_select, 0, 0) node _sinkC_req_out_bankSel_T_1 = bits(sinkC_req_select, 1, 1) node _sinkC_req_out_bankSel_T_2 = bits(sinkC_req_select, 2, 2) node _sinkC_req_out_bankSel_T_3 = bits(sinkC_req_select, 3, 3) node _sinkC_req_out_bankSel_T_4 = mux(_sinkC_req_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_5 = mux(_sinkC_req_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_6 = mux(_sinkC_req_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_7 = mux(_sinkC_req_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankSel_lo = cat(_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4) node sinkC_req_out_bankSel_hi = cat(_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6) node _sinkC_req_out_bankSel_T_8 = cat(sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo) node _sinkC_req_out_bankSel_T_9 = cat(io.sinkC_adr.bits.mask, io.sinkC_adr.bits.mask) node _sinkC_req_out_bankSel_T_10 = cat(_sinkC_req_out_bankSel_T_9, _sinkC_req_out_bankSel_T_9) node _sinkC_req_out_bankSel_T_11 = and(_sinkC_req_out_bankSel_T_8, _sinkC_req_out_bankSel_T_10) node _sinkC_req_out_bankSel_T_12 = mux(io.sinkC_adr.valid, _sinkC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkC_req.bankSel, _sinkC_req_out_bankSel_T_12 node _sinkC_req_out_bankEn_T = bits(sinkC_req_ready, 0, 0) node _sinkC_req_out_bankEn_T_1 = bits(sinkC_req_ready, 1, 1) node _sinkC_req_out_bankEn_T_2 = bits(sinkC_req_ready, 2, 2) node _sinkC_req_out_bankEn_T_3 = bits(sinkC_req_ready, 3, 3) node _sinkC_req_out_bankEn_T_4 = mux(_sinkC_req_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_5 = mux(_sinkC_req_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_6 = mux(_sinkC_req_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_7 = mux(_sinkC_req_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankEn_lo = cat(_sinkC_req_out_bankEn_T_5, _sinkC_req_out_bankEn_T_4) node sinkC_req_out_bankEn_hi = cat(_sinkC_req_out_bankEn_T_7, _sinkC_req_out_bankEn_T_6) node _sinkC_req_out_bankEn_T_8 = cat(sinkC_req_out_bankEn_hi, sinkC_req_out_bankEn_lo) node _sinkC_req_out_bankEn_T_9 = and(sinkC_req.bankSel, _sinkC_req_out_bankEn_T_8) node _sinkC_req_out_bankEn_T_10 = mux(io.sinkC_adr.bits.noop, UInt<1>(0h0), _sinkC_req_out_bankEn_T_9) connect sinkC_req.bankEn, _sinkC_req_out_bankEn_T_10 connect sinkC_req.data[0], sinkC_req_words_0 connect sinkC_req.data[1], sinkC_req_words_1 connect sinkC_req.data[2], sinkC_req_words_0 connect sinkC_req.data[3], sinkC_req_words_1 connect sinkC_req.data[4], sinkC_req_words_0 connect sinkC_req.data[5], sinkC_req_words_1 connect sinkC_req.data[6], sinkC_req_words_0 connect sinkC_req.data[7], sinkC_req_words_1 node sinkD_req_words_0 = bits(io.sinkD_dat.data, 63, 0) node sinkD_req_a_hi = cat(io.sinkD_adr.bits.way, io.sinkD_adr.bits.set) node sinkD_req_a = cat(sinkD_req_a_hi, io.sinkD_adr.bits.beat) wire sinkD_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkD_req_select_T = bits(sinkD_req_a, 2, 0) node sinkD_req_select_shiftAmount = bits(_sinkD_req_select_T, 2, 0) node _sinkD_req_select_T_1 = dshl(UInt<1>(0h1), sinkD_req_select_shiftAmount) node sinkD_req_select = bits(_sinkD_req_select_T_1, 7, 0) node _sinkD_req_ready_T = bits(sinkD_req.bankSum, 0, 0) node _sinkD_req_ready_T_1 = and(_sinkD_req_ready_T, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_2 = orr(_sinkD_req_ready_T_1) node _sinkD_req_ready_T_3 = eq(_sinkD_req_ready_T_2, UInt<1>(0h0)) node _sinkD_req_ready_T_4 = bits(sinkD_req.bankSum, 1, 1) node _sinkD_req_ready_T_5 = and(_sinkD_req_ready_T_4, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_6 = orr(_sinkD_req_ready_T_5) node _sinkD_req_ready_T_7 = eq(_sinkD_req_ready_T_6, UInt<1>(0h0)) node _sinkD_req_ready_T_8 = bits(sinkD_req.bankSum, 2, 2) node _sinkD_req_ready_T_9 = and(_sinkD_req_ready_T_8, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_10 = orr(_sinkD_req_ready_T_9) node _sinkD_req_ready_T_11 = eq(_sinkD_req_ready_T_10, UInt<1>(0h0)) node _sinkD_req_ready_T_12 = bits(sinkD_req.bankSum, 3, 3) node _sinkD_req_ready_T_13 = and(_sinkD_req_ready_T_12, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_14 = orr(_sinkD_req_ready_T_13) node _sinkD_req_ready_T_15 = eq(_sinkD_req_ready_T_14, UInt<1>(0h0)) node _sinkD_req_ready_T_16 = bits(sinkD_req.bankSum, 4, 4) node _sinkD_req_ready_T_17 = and(_sinkD_req_ready_T_16, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_18 = orr(_sinkD_req_ready_T_17) node _sinkD_req_ready_T_19 = eq(_sinkD_req_ready_T_18, UInt<1>(0h0)) node _sinkD_req_ready_T_20 = bits(sinkD_req.bankSum, 5, 5) node _sinkD_req_ready_T_21 = and(_sinkD_req_ready_T_20, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_22 = orr(_sinkD_req_ready_T_21) node _sinkD_req_ready_T_23 = eq(_sinkD_req_ready_T_22, UInt<1>(0h0)) node _sinkD_req_ready_T_24 = bits(sinkD_req.bankSum, 6, 6) node _sinkD_req_ready_T_25 = and(_sinkD_req_ready_T_24, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_26 = orr(_sinkD_req_ready_T_25) node _sinkD_req_ready_T_27 = eq(_sinkD_req_ready_T_26, UInt<1>(0h0)) node _sinkD_req_ready_T_28 = bits(sinkD_req.bankSum, 7, 7) node _sinkD_req_ready_T_29 = and(_sinkD_req_ready_T_28, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_30 = orr(_sinkD_req_ready_T_29) node _sinkD_req_ready_T_31 = eq(_sinkD_req_ready_T_30, UInt<1>(0h0)) node sinkD_req_ready_lo_lo = cat(_sinkD_req_ready_T_7, _sinkD_req_ready_T_3) node sinkD_req_ready_lo_hi = cat(_sinkD_req_ready_T_15, _sinkD_req_ready_T_11) node sinkD_req_ready_lo = cat(sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo) node sinkD_req_ready_hi_lo = cat(_sinkD_req_ready_T_23, _sinkD_req_ready_T_19) node sinkD_req_ready_hi_hi = cat(_sinkD_req_ready_T_31, _sinkD_req_ready_T_27) node sinkD_req_ready_hi = cat(sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo) node sinkD_req_ready = cat(sinkD_req_ready_hi, sinkD_req_ready_lo) node _sinkD_req_io_sinkD_adr_ready_T = bits(sinkD_req_a, 2, 0) node _sinkD_req_io_sinkD_adr_ready_T_1 = dshr(sinkD_req_ready, _sinkD_req_io_sinkD_adr_ready_T) node _sinkD_req_io_sinkD_adr_ready_T_2 = bits(_sinkD_req_io_sinkD_adr_ready_T_1, 0, 0) connect io.sinkD_adr.ready, _sinkD_req_io_sinkD_adr_ready_T_2 connect sinkD_req.wen, UInt<1>(0h1) node _sinkD_req_out_index_T = shr(sinkD_req_a, 3) connect sinkD_req.index, _sinkD_req_out_index_T node _sinkD_req_out_bankSel_T = bits(sinkD_req_select, 0, 0) node _sinkD_req_out_bankSel_T_1 = bits(sinkD_req_select, 1, 1) node _sinkD_req_out_bankSel_T_2 = bits(sinkD_req_select, 2, 2) node _sinkD_req_out_bankSel_T_3 = bits(sinkD_req_select, 3, 3) node _sinkD_req_out_bankSel_T_4 = bits(sinkD_req_select, 4, 4) node _sinkD_req_out_bankSel_T_5 = bits(sinkD_req_select, 5, 5) node _sinkD_req_out_bankSel_T_6 = bits(sinkD_req_select, 6, 6) node _sinkD_req_out_bankSel_T_7 = bits(sinkD_req_select, 7, 7) node sinkD_req_out_bankSel_lo_lo = cat(_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T) node sinkD_req_out_bankSel_lo_hi = cat(_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2) node sinkD_req_out_bankSel_lo = cat(sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo) node sinkD_req_out_bankSel_hi_lo = cat(_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4) node sinkD_req_out_bankSel_hi_hi = cat(_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6) node sinkD_req_out_bankSel_hi = cat(sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo) node _sinkD_req_out_bankSel_T_8 = cat(sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo) node _sinkD_req_out_bankSel_T_9 = bits(io.sinkD_adr.bits.mask, 0, 0) node _sinkD_req_out_bankSel_T_10 = mux(_sinkD_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sinkD_req_out_bankSel_T_11 = and(_sinkD_req_out_bankSel_T_8, _sinkD_req_out_bankSel_T_10) node _sinkD_req_out_bankSel_T_12 = mux(io.sinkD_adr.valid, _sinkD_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkD_req.bankSel, _sinkD_req_out_bankSel_T_12 node _sinkD_req_out_bankEn_T = bits(sinkD_req_ready, 0, 0) node _sinkD_req_out_bankEn_T_1 = bits(sinkD_req_ready, 1, 1) node _sinkD_req_out_bankEn_T_2 = bits(sinkD_req_ready, 2, 2) node _sinkD_req_out_bankEn_T_3 = bits(sinkD_req_ready, 3, 3) node _sinkD_req_out_bankEn_T_4 = bits(sinkD_req_ready, 4, 4) node _sinkD_req_out_bankEn_T_5 = bits(sinkD_req_ready, 5, 5) node _sinkD_req_out_bankEn_T_6 = bits(sinkD_req_ready, 6, 6) node _sinkD_req_out_bankEn_T_7 = bits(sinkD_req_ready, 7, 7) node sinkD_req_out_bankEn_lo_lo = cat(_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T) node sinkD_req_out_bankEn_lo_hi = cat(_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2) node sinkD_req_out_bankEn_lo = cat(sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo) node sinkD_req_out_bankEn_hi_lo = cat(_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4) node sinkD_req_out_bankEn_hi_hi = cat(_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6) node sinkD_req_out_bankEn_hi = cat(sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo) node _sinkD_req_out_bankEn_T_8 = cat(sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo) node _sinkD_req_out_bankEn_T_9 = and(sinkD_req.bankSel, _sinkD_req_out_bankEn_T_8) node _sinkD_req_out_bankEn_T_10 = mux(io.sinkD_adr.bits.noop, UInt<1>(0h0), _sinkD_req_out_bankEn_T_9) connect sinkD_req.bankEn, _sinkD_req_out_bankEn_T_10 connect sinkD_req.data[0], sinkD_req_words_0 connect sinkD_req.data[1], sinkD_req_words_0 connect sinkD_req.data[2], sinkD_req_words_0 connect sinkD_req.data[3], sinkD_req_words_0 connect sinkD_req.data[4], sinkD_req_words_0 connect sinkD_req.data[5], sinkD_req_words_0 connect sinkD_req.data[6], sinkD_req_words_0 connect sinkD_req.data[7], sinkD_req_words_0 node sourceC_req_a_hi = cat(io.sourceC_adr.bits.way, io.sourceC_adr.bits.set) node sourceC_req_a = cat(sourceC_req_a_hi, io.sourceC_adr.bits.beat) wire sourceC_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceC_req_select_T = bits(sourceC_req_a, 2, 0) node sourceC_req_select_shiftAmount = bits(_sourceC_req_select_T, 2, 0) node _sourceC_req_select_T_1 = dshl(UInt<1>(0h1), sourceC_req_select_shiftAmount) node sourceC_req_select = bits(_sourceC_req_select_T_1, 7, 0) node _sourceC_req_ready_T = bits(sourceC_req.bankSum, 0, 0) node _sourceC_req_ready_T_1 = and(_sourceC_req_ready_T, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_2 = orr(_sourceC_req_ready_T_1) node _sourceC_req_ready_T_3 = eq(_sourceC_req_ready_T_2, UInt<1>(0h0)) node _sourceC_req_ready_T_4 = bits(sourceC_req.bankSum, 1, 1) node _sourceC_req_ready_T_5 = and(_sourceC_req_ready_T_4, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_6 = orr(_sourceC_req_ready_T_5) node _sourceC_req_ready_T_7 = eq(_sourceC_req_ready_T_6, UInt<1>(0h0)) node _sourceC_req_ready_T_8 = bits(sourceC_req.bankSum, 2, 2) node _sourceC_req_ready_T_9 = and(_sourceC_req_ready_T_8, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_10 = orr(_sourceC_req_ready_T_9) node _sourceC_req_ready_T_11 = eq(_sourceC_req_ready_T_10, UInt<1>(0h0)) node _sourceC_req_ready_T_12 = bits(sourceC_req.bankSum, 3, 3) node _sourceC_req_ready_T_13 = and(_sourceC_req_ready_T_12, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_14 = orr(_sourceC_req_ready_T_13) node _sourceC_req_ready_T_15 = eq(_sourceC_req_ready_T_14, UInt<1>(0h0)) node _sourceC_req_ready_T_16 = bits(sourceC_req.bankSum, 4, 4) node _sourceC_req_ready_T_17 = and(_sourceC_req_ready_T_16, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_18 = orr(_sourceC_req_ready_T_17) node _sourceC_req_ready_T_19 = eq(_sourceC_req_ready_T_18, UInt<1>(0h0)) node _sourceC_req_ready_T_20 = bits(sourceC_req.bankSum, 5, 5) node _sourceC_req_ready_T_21 = and(_sourceC_req_ready_T_20, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_22 = orr(_sourceC_req_ready_T_21) node _sourceC_req_ready_T_23 = eq(_sourceC_req_ready_T_22, UInt<1>(0h0)) node _sourceC_req_ready_T_24 = bits(sourceC_req.bankSum, 6, 6) node _sourceC_req_ready_T_25 = and(_sourceC_req_ready_T_24, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_26 = orr(_sourceC_req_ready_T_25) node _sourceC_req_ready_T_27 = eq(_sourceC_req_ready_T_26, UInt<1>(0h0)) node _sourceC_req_ready_T_28 = bits(sourceC_req.bankSum, 7, 7) node _sourceC_req_ready_T_29 = and(_sourceC_req_ready_T_28, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_30 = orr(_sourceC_req_ready_T_29) node _sourceC_req_ready_T_31 = eq(_sourceC_req_ready_T_30, UInt<1>(0h0)) node sourceC_req_ready_lo_lo = cat(_sourceC_req_ready_T_7, _sourceC_req_ready_T_3) node sourceC_req_ready_lo_hi = cat(_sourceC_req_ready_T_15, _sourceC_req_ready_T_11) node sourceC_req_ready_lo = cat(sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo) node sourceC_req_ready_hi_lo = cat(_sourceC_req_ready_T_23, _sourceC_req_ready_T_19) node sourceC_req_ready_hi_hi = cat(_sourceC_req_ready_T_31, _sourceC_req_ready_T_27) node sourceC_req_ready_hi = cat(sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo) node sourceC_req_ready = cat(sourceC_req_ready_hi, sourceC_req_ready_lo) node _sourceC_req_io_sourceC_adr_ready_T = bits(sourceC_req_a, 2, 0) node _sourceC_req_io_sourceC_adr_ready_T_1 = dshr(sourceC_req_ready, _sourceC_req_io_sourceC_adr_ready_T) node _sourceC_req_io_sourceC_adr_ready_T_2 = bits(_sourceC_req_io_sourceC_adr_ready_T_1, 0, 0) connect io.sourceC_adr.ready, _sourceC_req_io_sourceC_adr_ready_T_2 connect sourceC_req.wen, UInt<1>(0h0) node _sourceC_req_out_index_T = shr(sourceC_req_a, 3) connect sourceC_req.index, _sourceC_req_out_index_T node _sourceC_req_out_bankSel_T = bits(sourceC_req_select, 0, 0) node _sourceC_req_out_bankSel_T_1 = bits(sourceC_req_select, 1, 1) node _sourceC_req_out_bankSel_T_2 = bits(sourceC_req_select, 2, 2) node _sourceC_req_out_bankSel_T_3 = bits(sourceC_req_select, 3, 3) node _sourceC_req_out_bankSel_T_4 = bits(sourceC_req_select, 4, 4) node _sourceC_req_out_bankSel_T_5 = bits(sourceC_req_select, 5, 5) node _sourceC_req_out_bankSel_T_6 = bits(sourceC_req_select, 6, 6) node _sourceC_req_out_bankSel_T_7 = bits(sourceC_req_select, 7, 7) node sourceC_req_out_bankSel_lo_lo = cat(_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T) node sourceC_req_out_bankSel_lo_hi = cat(_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2) node sourceC_req_out_bankSel_lo = cat(sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo) node sourceC_req_out_bankSel_hi_lo = cat(_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4) node sourceC_req_out_bankSel_hi_hi = cat(_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6) node sourceC_req_out_bankSel_hi = cat(sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo) node _sourceC_req_out_bankSel_T_8 = cat(sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo) node _sourceC_req_out_bankSel_T_9 = bits(io.sourceC_adr.bits.mask, 0, 0) node _sourceC_req_out_bankSel_T_10 = mux(_sourceC_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sourceC_req_out_bankSel_T_11 = and(_sourceC_req_out_bankSel_T_8, _sourceC_req_out_bankSel_T_10) node _sourceC_req_out_bankSel_T_12 = mux(io.sourceC_adr.valid, _sourceC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sourceC_req.bankSel, _sourceC_req_out_bankSel_T_12 node _sourceC_req_out_bankEn_T = bits(sourceC_req_ready, 0, 0) node _sourceC_req_out_bankEn_T_1 = bits(sourceC_req_ready, 1, 1) node _sourceC_req_out_bankEn_T_2 = bits(sourceC_req_ready, 2, 2) node _sourceC_req_out_bankEn_T_3 = bits(sourceC_req_ready, 3, 3) node _sourceC_req_out_bankEn_T_4 = bits(sourceC_req_ready, 4, 4) node _sourceC_req_out_bankEn_T_5 = bits(sourceC_req_ready, 5, 5) node _sourceC_req_out_bankEn_T_6 = bits(sourceC_req_ready, 6, 6) node _sourceC_req_out_bankEn_T_7 = bits(sourceC_req_ready, 7, 7) node sourceC_req_out_bankEn_lo_lo = cat(_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T) node sourceC_req_out_bankEn_lo_hi = cat(_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2) node sourceC_req_out_bankEn_lo = cat(sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo) node sourceC_req_out_bankEn_hi_lo = cat(_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4) node sourceC_req_out_bankEn_hi_hi = cat(_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6) node sourceC_req_out_bankEn_hi = cat(sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo) node _sourceC_req_out_bankEn_T_8 = cat(sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo) node _sourceC_req_out_bankEn_T_9 = and(sourceC_req.bankSel, _sourceC_req_out_bankEn_T_8) node _sourceC_req_out_bankEn_T_10 = mux(io.sourceC_adr.bits.noop, UInt<1>(0h0), _sourceC_req_out_bankEn_T_9) connect sourceC_req.bankEn, _sourceC_req_out_bankEn_T_10 connect sourceC_req.data[0], UInt<64>(0h0) connect sourceC_req.data[1], UInt<64>(0h0) connect sourceC_req.data[2], UInt<64>(0h0) connect sourceC_req.data[3], UInt<64>(0h0) connect sourceC_req.data[4], UInt<64>(0h0) connect sourceC_req.data[5], UInt<64>(0h0) connect sourceC_req.data[6], UInt<64>(0h0) connect sourceC_req.data[7], UInt<64>(0h0) node sourceD_rreq_a_hi = cat(io.sourceD_radr.bits.way, io.sourceD_radr.bits.set) node sourceD_rreq_a = cat(sourceD_rreq_a_hi, io.sourceD_radr.bits.beat) wire sourceD_rreq : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_rreq_select_T = bits(sourceD_rreq_a, 1, 0) node sourceD_rreq_select_shiftAmount = bits(_sourceD_rreq_select_T, 1, 0) node _sourceD_rreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_rreq_select_shiftAmount) node sourceD_rreq_select = bits(_sourceD_rreq_select_T_1, 3, 0) node _sourceD_rreq_ready_T = bits(sourceD_rreq.bankSum, 1, 0) node _sourceD_rreq_ready_T_1 = and(_sourceD_rreq_ready_T, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_2 = orr(_sourceD_rreq_ready_T_1) node _sourceD_rreq_ready_T_3 = eq(_sourceD_rreq_ready_T_2, UInt<1>(0h0)) node _sourceD_rreq_ready_T_4 = bits(sourceD_rreq.bankSum, 3, 2) node _sourceD_rreq_ready_T_5 = and(_sourceD_rreq_ready_T_4, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_6 = orr(_sourceD_rreq_ready_T_5) node _sourceD_rreq_ready_T_7 = eq(_sourceD_rreq_ready_T_6, UInt<1>(0h0)) node _sourceD_rreq_ready_T_8 = bits(sourceD_rreq.bankSum, 5, 4) node _sourceD_rreq_ready_T_9 = and(_sourceD_rreq_ready_T_8, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_10 = orr(_sourceD_rreq_ready_T_9) node _sourceD_rreq_ready_T_11 = eq(_sourceD_rreq_ready_T_10, UInt<1>(0h0)) node _sourceD_rreq_ready_T_12 = bits(sourceD_rreq.bankSum, 7, 6) node _sourceD_rreq_ready_T_13 = and(_sourceD_rreq_ready_T_12, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_14 = orr(_sourceD_rreq_ready_T_13) node _sourceD_rreq_ready_T_15 = eq(_sourceD_rreq_ready_T_14, UInt<1>(0h0)) node sourceD_rreq_ready_lo = cat(_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3) node sourceD_rreq_ready_hi = cat(_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11) node sourceD_rreq_ready = cat(sourceD_rreq_ready_hi, sourceD_rreq_ready_lo) node _sourceD_rreq_io_sourceD_radr_ready_T = bits(sourceD_rreq_a, 1, 0) node _sourceD_rreq_io_sourceD_radr_ready_T_1 = dshr(sourceD_rreq_ready, _sourceD_rreq_io_sourceD_radr_ready_T) node _sourceD_rreq_io_sourceD_radr_ready_T_2 = bits(_sourceD_rreq_io_sourceD_radr_ready_T_1, 0, 0) connect io.sourceD_radr.ready, _sourceD_rreq_io_sourceD_radr_ready_T_2 connect sourceD_rreq.wen, UInt<1>(0h0) node _sourceD_rreq_out_index_T = shr(sourceD_rreq_a, 2) connect sourceD_rreq.index, _sourceD_rreq_out_index_T node _sourceD_rreq_out_bankSel_T = bits(sourceD_rreq_select, 0, 0) node _sourceD_rreq_out_bankSel_T_1 = bits(sourceD_rreq_select, 1, 1) node _sourceD_rreq_out_bankSel_T_2 = bits(sourceD_rreq_select, 2, 2) node _sourceD_rreq_out_bankSel_T_3 = bits(sourceD_rreq_select, 3, 3) node _sourceD_rreq_out_bankSel_T_4 = mux(_sourceD_rreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_5 = mux(_sourceD_rreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_6 = mux(_sourceD_rreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_7 = mux(_sourceD_rreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankSel_lo = cat(_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4) node sourceD_rreq_out_bankSel_hi = cat(_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6) node _sourceD_rreq_out_bankSel_T_8 = cat(sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo) node _sourceD_rreq_out_bankSel_T_9 = cat(io.sourceD_radr.bits.mask, io.sourceD_radr.bits.mask) node _sourceD_rreq_out_bankSel_T_10 = cat(_sourceD_rreq_out_bankSel_T_9, _sourceD_rreq_out_bankSel_T_9) node _sourceD_rreq_out_bankSel_T_11 = and(_sourceD_rreq_out_bankSel_T_8, _sourceD_rreq_out_bankSel_T_10) node _sourceD_rreq_out_bankSel_T_12 = mux(io.sourceD_radr.valid, _sourceD_rreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_rreq.bankSel, _sourceD_rreq_out_bankSel_T_12 node _sourceD_rreq_out_bankEn_T = bits(sourceD_rreq_ready, 0, 0) node _sourceD_rreq_out_bankEn_T_1 = bits(sourceD_rreq_ready, 1, 1) node _sourceD_rreq_out_bankEn_T_2 = bits(sourceD_rreq_ready, 2, 2) node _sourceD_rreq_out_bankEn_T_3 = bits(sourceD_rreq_ready, 3, 3) node _sourceD_rreq_out_bankEn_T_4 = mux(_sourceD_rreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_5 = mux(_sourceD_rreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_6 = mux(_sourceD_rreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_7 = mux(_sourceD_rreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankEn_lo = cat(_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4) node sourceD_rreq_out_bankEn_hi = cat(_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6) node _sourceD_rreq_out_bankEn_T_8 = cat(sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo) node _sourceD_rreq_out_bankEn_T_9 = and(sourceD_rreq.bankSel, _sourceD_rreq_out_bankEn_T_8) node _sourceD_rreq_out_bankEn_T_10 = mux(io.sourceD_radr.bits.noop, UInt<1>(0h0), _sourceD_rreq_out_bankEn_T_9) connect sourceD_rreq.bankEn, _sourceD_rreq_out_bankEn_T_10 connect sourceD_rreq.data[0], UInt<64>(0h0) connect sourceD_rreq.data[1], UInt<64>(0h0) connect sourceD_rreq.data[2], UInt<64>(0h0) connect sourceD_rreq.data[3], UInt<64>(0h0) connect sourceD_rreq.data[4], UInt<64>(0h0) connect sourceD_rreq.data[5], UInt<64>(0h0) connect sourceD_rreq.data[6], UInt<64>(0h0) connect sourceD_rreq.data[7], UInt<64>(0h0) node sourceD_wreq_words_0 = bits(io.sourceD_wdat.data, 63, 0) node sourceD_wreq_words_1 = bits(io.sourceD_wdat.data, 127, 64) node sourceD_wreq_a_hi = cat(io.sourceD_wadr.bits.way, io.sourceD_wadr.bits.set) node sourceD_wreq_a = cat(sourceD_wreq_a_hi, io.sourceD_wadr.bits.beat) wire sourceD_wreq : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_wreq_select_T = bits(sourceD_wreq_a, 1, 0) node sourceD_wreq_select_shiftAmount = bits(_sourceD_wreq_select_T, 1, 0) node _sourceD_wreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_wreq_select_shiftAmount) node sourceD_wreq_select = bits(_sourceD_wreq_select_T_1, 3, 0) node _sourceD_wreq_ready_T = bits(sourceD_wreq.bankSum, 1, 0) node _sourceD_wreq_ready_T_1 = and(_sourceD_wreq_ready_T, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_2 = orr(_sourceD_wreq_ready_T_1) node _sourceD_wreq_ready_T_3 = eq(_sourceD_wreq_ready_T_2, UInt<1>(0h0)) node _sourceD_wreq_ready_T_4 = bits(sourceD_wreq.bankSum, 3, 2) node _sourceD_wreq_ready_T_5 = and(_sourceD_wreq_ready_T_4, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_6 = orr(_sourceD_wreq_ready_T_5) node _sourceD_wreq_ready_T_7 = eq(_sourceD_wreq_ready_T_6, UInt<1>(0h0)) node _sourceD_wreq_ready_T_8 = bits(sourceD_wreq.bankSum, 5, 4) node _sourceD_wreq_ready_T_9 = and(_sourceD_wreq_ready_T_8, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_10 = orr(_sourceD_wreq_ready_T_9) node _sourceD_wreq_ready_T_11 = eq(_sourceD_wreq_ready_T_10, UInt<1>(0h0)) node _sourceD_wreq_ready_T_12 = bits(sourceD_wreq.bankSum, 7, 6) node _sourceD_wreq_ready_T_13 = and(_sourceD_wreq_ready_T_12, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_14 = orr(_sourceD_wreq_ready_T_13) node _sourceD_wreq_ready_T_15 = eq(_sourceD_wreq_ready_T_14, UInt<1>(0h0)) node sourceD_wreq_ready_lo = cat(_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3) node sourceD_wreq_ready_hi = cat(_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11) node sourceD_wreq_ready = cat(sourceD_wreq_ready_hi, sourceD_wreq_ready_lo) node _sourceD_wreq_io_sourceD_wadr_ready_T = bits(sourceD_wreq_a, 1, 0) node _sourceD_wreq_io_sourceD_wadr_ready_T_1 = dshr(sourceD_wreq_ready, _sourceD_wreq_io_sourceD_wadr_ready_T) node _sourceD_wreq_io_sourceD_wadr_ready_T_2 = bits(_sourceD_wreq_io_sourceD_wadr_ready_T_1, 0, 0) connect io.sourceD_wadr.ready, _sourceD_wreq_io_sourceD_wadr_ready_T_2 connect sourceD_wreq.wen, UInt<1>(0h1) node _sourceD_wreq_out_index_T = shr(sourceD_wreq_a, 2) connect sourceD_wreq.index, _sourceD_wreq_out_index_T node _sourceD_wreq_out_bankSel_T = bits(sourceD_wreq_select, 0, 0) node _sourceD_wreq_out_bankSel_T_1 = bits(sourceD_wreq_select, 1, 1) node _sourceD_wreq_out_bankSel_T_2 = bits(sourceD_wreq_select, 2, 2) node _sourceD_wreq_out_bankSel_T_3 = bits(sourceD_wreq_select, 3, 3) node _sourceD_wreq_out_bankSel_T_4 = mux(_sourceD_wreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_5 = mux(_sourceD_wreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_6 = mux(_sourceD_wreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_7 = mux(_sourceD_wreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankSel_lo = cat(_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4) node sourceD_wreq_out_bankSel_hi = cat(_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6) node _sourceD_wreq_out_bankSel_T_8 = cat(sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo) node _sourceD_wreq_out_bankSel_T_9 = cat(io.sourceD_wadr.bits.mask, io.sourceD_wadr.bits.mask) node _sourceD_wreq_out_bankSel_T_10 = cat(_sourceD_wreq_out_bankSel_T_9, _sourceD_wreq_out_bankSel_T_9) node _sourceD_wreq_out_bankSel_T_11 = and(_sourceD_wreq_out_bankSel_T_8, _sourceD_wreq_out_bankSel_T_10) node _sourceD_wreq_out_bankSel_T_12 = mux(io.sourceD_wadr.valid, _sourceD_wreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_wreq.bankSel, _sourceD_wreq_out_bankSel_T_12 node _sourceD_wreq_out_bankEn_T = bits(sourceD_wreq_ready, 0, 0) node _sourceD_wreq_out_bankEn_T_1 = bits(sourceD_wreq_ready, 1, 1) node _sourceD_wreq_out_bankEn_T_2 = bits(sourceD_wreq_ready, 2, 2) node _sourceD_wreq_out_bankEn_T_3 = bits(sourceD_wreq_ready, 3, 3) node _sourceD_wreq_out_bankEn_T_4 = mux(_sourceD_wreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_5 = mux(_sourceD_wreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_6 = mux(_sourceD_wreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_7 = mux(_sourceD_wreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankEn_lo = cat(_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4) node sourceD_wreq_out_bankEn_hi = cat(_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6) node _sourceD_wreq_out_bankEn_T_8 = cat(sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo) node _sourceD_wreq_out_bankEn_T_9 = and(sourceD_wreq.bankSel, _sourceD_wreq_out_bankEn_T_8) node _sourceD_wreq_out_bankEn_T_10 = mux(io.sourceD_wadr.bits.noop, UInt<1>(0h0), _sourceD_wreq_out_bankEn_T_9) connect sourceD_wreq.bankEn, _sourceD_wreq_out_bankEn_T_10 connect sourceD_wreq.data[0], sourceD_wreq_words_0 connect sourceD_wreq.data[1], sourceD_wreq_words_1 connect sourceD_wreq.data[2], sourceD_wreq_words_0 connect sourceD_wreq.data[3], sourceD_wreq_words_1 connect sourceD_wreq.data[4], sourceD_wreq_words_0 connect sourceD_wreq.data[5], sourceD_wreq_words_1 connect sourceD_wreq.data[6], sourceD_wreq_words_0 connect sourceD_wreq.data[7], sourceD_wreq_words_1 connect sinkC_req.bankSum, UInt<1>(0h0) node _T = or(sinkC_req.bankSel, UInt<1>(0h0)) connect sourceC_req.bankSum, _T node _T_1 = or(sourceC_req.bankSel, _T) connect sinkD_req.bankSum, _T_1 node _T_2 = or(sinkD_req.bankSel, _T_1) connect sourceD_wreq.bankSum, _T_2 node _T_3 = or(sourceD_wreq.bankSel, _T_2) connect sourceD_rreq.bankSum, _T_3 node _T_4 = or(sourceD_rreq.bankSel, _T_3) node _regout_en_T = bits(sinkC_req.bankEn, 0, 0) node _regout_en_T_1 = bits(sourceC_req.bankEn, 0, 0) node _regout_en_T_2 = bits(sinkD_req.bankEn, 0, 0) node _regout_en_T_3 = bits(sourceD_wreq.bankEn, 0, 0) node _regout_en_T_4 = bits(sourceD_rreq.bankEn, 0, 0) node _regout_en_T_5 = or(_regout_en_T, _regout_en_T_1) node _regout_en_T_6 = or(_regout_en_T_5, _regout_en_T_2) node _regout_en_T_7 = or(_regout_en_T_6, _regout_en_T_3) node regout_en = or(_regout_en_T_7, _regout_en_T_4) node regout_sel_0 = bits(sinkC_req.bankSel, 0, 0) node regout_sel_1 = bits(sourceC_req.bankSel, 0, 0) node regout_sel_2 = bits(sinkD_req.bankSel, 0, 0) node regout_sel_3 = bits(sourceD_wreq.bankSel, 0, 0) node regout_sel_4 = bits(sourceD_rreq.bankSel, 0, 0) node _regout_wen_T = mux(regout_sel_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_1 = mux(regout_sel_2, sinkD_req.wen, _regout_wen_T) node _regout_wen_T_2 = mux(regout_sel_1, sourceC_req.wen, _regout_wen_T_1) node regout_wen = mux(regout_sel_0, sinkC_req.wen, _regout_wen_T_2) node _regout_idx_T = mux(regout_sel_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_1 = mux(regout_sel_2, sinkD_req.index, _regout_idx_T) node _regout_idx_T_2 = mux(regout_sel_1, sourceC_req.index, _regout_idx_T_1) node regout_idx = mux(regout_sel_0, sinkC_req.index, _regout_idx_T_2) node _regout_data_T = mux(regout_sel_3, sourceD_wreq.data[0], sourceD_rreq.data[0]) node _regout_data_T_1 = mux(regout_sel_2, sinkD_req.data[0], _regout_data_T) node _regout_data_T_2 = mux(regout_sel_1, sourceC_req.data[0], _regout_data_T_1) node regout_data = mux(regout_sel_0, sinkC_req.data[0], _regout_data_T_2) node _regout_T = and(regout_wen, regout_en) when _regout_T : write mport regout_MPORT = cc_banks_0[regout_idx], clock connect regout_MPORT, regout_data node _regout_T_1 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_2 = and(_regout_T_1, regout_en) wire _regout_WIRE : UInt<13> invalidate _regout_WIRE when _regout_T_2 : connect _regout_WIRE, regout_idx read mport regout_MPORT_1 = cc_banks_0[_regout_WIRE], clock node _regout_T_3 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_4 = and(_regout_T_3, regout_en) reg regout_REG : UInt<1>, clock connect regout_REG, _regout_T_4 reg regout_r : UInt<64>, clock when regout_REG : connect regout_r, regout_MPORT_1 node _regout_en_T_8 = bits(sinkC_req.bankEn, 1, 1) node _regout_en_T_9 = bits(sourceC_req.bankEn, 1, 1) node _regout_en_T_10 = bits(sinkD_req.bankEn, 1, 1) node _regout_en_T_11 = bits(sourceD_wreq.bankEn, 1, 1) node _regout_en_T_12 = bits(sourceD_rreq.bankEn, 1, 1) node _regout_en_T_13 = or(_regout_en_T_8, _regout_en_T_9) node _regout_en_T_14 = or(_regout_en_T_13, _regout_en_T_10) node _regout_en_T_15 = or(_regout_en_T_14, _regout_en_T_11) node regout_en_1 = or(_regout_en_T_15, _regout_en_T_12) node regout_sel_0_1 = bits(sinkC_req.bankSel, 1, 1) node regout_sel_1_1 = bits(sourceC_req.bankSel, 1, 1) node regout_sel_2_1 = bits(sinkD_req.bankSel, 1, 1) node regout_sel_3_1 = bits(sourceD_wreq.bankSel, 1, 1) node regout_sel_4_1 = bits(sourceD_rreq.bankSel, 1, 1) node _regout_wen_T_3 = mux(regout_sel_3_1, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_4 = mux(regout_sel_2_1, sinkD_req.wen, _regout_wen_T_3) node _regout_wen_T_5 = mux(regout_sel_1_1, sourceC_req.wen, _regout_wen_T_4) node regout_wen_1 = mux(regout_sel_0_1, sinkC_req.wen, _regout_wen_T_5) node _regout_idx_T_3 = mux(regout_sel_3_1, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_4 = mux(regout_sel_2_1, sinkD_req.index, _regout_idx_T_3) node _regout_idx_T_5 = mux(regout_sel_1_1, sourceC_req.index, _regout_idx_T_4) node regout_idx_1 = mux(regout_sel_0_1, sinkC_req.index, _regout_idx_T_5) node _regout_data_T_3 = mux(regout_sel_3_1, sourceD_wreq.data[1], sourceD_rreq.data[1]) node _regout_data_T_4 = mux(regout_sel_2_1, sinkD_req.data[1], _regout_data_T_3) node _regout_data_T_5 = mux(regout_sel_1_1, sourceC_req.data[1], _regout_data_T_4) node regout_data_1 = mux(regout_sel_0_1, sinkC_req.data[1], _regout_data_T_5) node _regout_T_5 = and(regout_wen_1, regout_en_1) when _regout_T_5 : write mport regout_MPORT_2 = cc_banks_1[regout_idx_1], clock connect regout_MPORT_2, regout_data_1 node _regout_T_6 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_7 = and(_regout_T_6, regout_en_1) wire _regout_WIRE_1 : UInt<13> invalidate _regout_WIRE_1 when _regout_T_7 : connect _regout_WIRE_1, regout_idx_1 read mport regout_MPORT_3 = cc_banks_1[_regout_WIRE_1], clock node _regout_T_8 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_9 = and(_regout_T_8, regout_en_1) reg regout_REG_1 : UInt<1>, clock connect regout_REG_1, _regout_T_9 reg regout_r_1 : UInt<64>, clock when regout_REG_1 : connect regout_r_1, regout_MPORT_3 node _regout_en_T_16 = bits(sinkC_req.bankEn, 2, 2) node _regout_en_T_17 = bits(sourceC_req.bankEn, 2, 2) node _regout_en_T_18 = bits(sinkD_req.bankEn, 2, 2) node _regout_en_T_19 = bits(sourceD_wreq.bankEn, 2, 2) node _regout_en_T_20 = bits(sourceD_rreq.bankEn, 2, 2) node _regout_en_T_21 = or(_regout_en_T_16, _regout_en_T_17) node _regout_en_T_22 = or(_regout_en_T_21, _regout_en_T_18) node _regout_en_T_23 = or(_regout_en_T_22, _regout_en_T_19) node regout_en_2 = or(_regout_en_T_23, _regout_en_T_20) node regout_sel_0_2 = bits(sinkC_req.bankSel, 2, 2) node regout_sel_1_2 = bits(sourceC_req.bankSel, 2, 2) node regout_sel_2_2 = bits(sinkD_req.bankSel, 2, 2) node regout_sel_3_2 = bits(sourceD_wreq.bankSel, 2, 2) node regout_sel_4_2 = bits(sourceD_rreq.bankSel, 2, 2) node _regout_wen_T_6 = mux(regout_sel_3_2, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_7 = mux(regout_sel_2_2, sinkD_req.wen, _regout_wen_T_6) node _regout_wen_T_8 = mux(regout_sel_1_2, sourceC_req.wen, _regout_wen_T_7) node regout_wen_2 = mux(regout_sel_0_2, sinkC_req.wen, _regout_wen_T_8) node _regout_idx_T_6 = mux(regout_sel_3_2, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_7 = mux(regout_sel_2_2, sinkD_req.index, _regout_idx_T_6) node _regout_idx_T_8 = mux(regout_sel_1_2, sourceC_req.index, _regout_idx_T_7) node regout_idx_2 = mux(regout_sel_0_2, sinkC_req.index, _regout_idx_T_8) node _regout_data_T_6 = mux(regout_sel_3_2, sourceD_wreq.data[2], sourceD_rreq.data[2]) node _regout_data_T_7 = mux(regout_sel_2_2, sinkD_req.data[2], _regout_data_T_6) node _regout_data_T_8 = mux(regout_sel_1_2, sourceC_req.data[2], _regout_data_T_7) node regout_data_2 = mux(regout_sel_0_2, sinkC_req.data[2], _regout_data_T_8) node _regout_T_10 = and(regout_wen_2, regout_en_2) when _regout_T_10 : write mport regout_MPORT_4 = cc_banks_2[regout_idx_2], clock connect regout_MPORT_4, regout_data_2 node _regout_T_11 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_12 = and(_regout_T_11, regout_en_2) wire _regout_WIRE_2 : UInt<13> invalidate _regout_WIRE_2 when _regout_T_12 : connect _regout_WIRE_2, regout_idx_2 read mport regout_MPORT_5 = cc_banks_2[_regout_WIRE_2], clock node _regout_T_13 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_14 = and(_regout_T_13, regout_en_2) reg regout_REG_2 : UInt<1>, clock connect regout_REG_2, _regout_T_14 reg regout_r_2 : UInt<64>, clock when regout_REG_2 : connect regout_r_2, regout_MPORT_5 node _regout_en_T_24 = bits(sinkC_req.bankEn, 3, 3) node _regout_en_T_25 = bits(sourceC_req.bankEn, 3, 3) node _regout_en_T_26 = bits(sinkD_req.bankEn, 3, 3) node _regout_en_T_27 = bits(sourceD_wreq.bankEn, 3, 3) node _regout_en_T_28 = bits(sourceD_rreq.bankEn, 3, 3) node _regout_en_T_29 = or(_regout_en_T_24, _regout_en_T_25) node _regout_en_T_30 = or(_regout_en_T_29, _regout_en_T_26) node _regout_en_T_31 = or(_regout_en_T_30, _regout_en_T_27) node regout_en_3 = or(_regout_en_T_31, _regout_en_T_28) node regout_sel_0_3 = bits(sinkC_req.bankSel, 3, 3) node regout_sel_1_3 = bits(sourceC_req.bankSel, 3, 3) node regout_sel_2_3 = bits(sinkD_req.bankSel, 3, 3) node regout_sel_3_3 = bits(sourceD_wreq.bankSel, 3, 3) node regout_sel_4_3 = bits(sourceD_rreq.bankSel, 3, 3) node _regout_wen_T_9 = mux(regout_sel_3_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_10 = mux(regout_sel_2_3, sinkD_req.wen, _regout_wen_T_9) node _regout_wen_T_11 = mux(regout_sel_1_3, sourceC_req.wen, _regout_wen_T_10) node regout_wen_3 = mux(regout_sel_0_3, sinkC_req.wen, _regout_wen_T_11) node _regout_idx_T_9 = mux(regout_sel_3_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_10 = mux(regout_sel_2_3, sinkD_req.index, _regout_idx_T_9) node _regout_idx_T_11 = mux(regout_sel_1_3, sourceC_req.index, _regout_idx_T_10) node regout_idx_3 = mux(regout_sel_0_3, sinkC_req.index, _regout_idx_T_11) node _regout_data_T_9 = mux(regout_sel_3_3, sourceD_wreq.data[3], sourceD_rreq.data[3]) node _regout_data_T_10 = mux(regout_sel_2_3, sinkD_req.data[3], _regout_data_T_9) node _regout_data_T_11 = mux(regout_sel_1_3, sourceC_req.data[3], _regout_data_T_10) node regout_data_3 = mux(regout_sel_0_3, sinkC_req.data[3], _regout_data_T_11) node _regout_T_15 = and(regout_wen_3, regout_en_3) when _regout_T_15 : write mport regout_MPORT_6 = cc_banks_3[regout_idx_3], clock connect regout_MPORT_6, regout_data_3 node _regout_T_16 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_17 = and(_regout_T_16, regout_en_3) wire _regout_WIRE_3 : UInt<13> invalidate _regout_WIRE_3 when _regout_T_17 : connect _regout_WIRE_3, regout_idx_3 read mport regout_MPORT_7 = cc_banks_3[_regout_WIRE_3], clock node _regout_T_18 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_19 = and(_regout_T_18, regout_en_3) reg regout_REG_3 : UInt<1>, clock connect regout_REG_3, _regout_T_19 reg regout_r_3 : UInt<64>, clock when regout_REG_3 : connect regout_r_3, regout_MPORT_7 node _regout_en_T_32 = bits(sinkC_req.bankEn, 4, 4) node _regout_en_T_33 = bits(sourceC_req.bankEn, 4, 4) node _regout_en_T_34 = bits(sinkD_req.bankEn, 4, 4) node _regout_en_T_35 = bits(sourceD_wreq.bankEn, 4, 4) node _regout_en_T_36 = bits(sourceD_rreq.bankEn, 4, 4) node _regout_en_T_37 = or(_regout_en_T_32, _regout_en_T_33) node _regout_en_T_38 = or(_regout_en_T_37, _regout_en_T_34) node _regout_en_T_39 = or(_regout_en_T_38, _regout_en_T_35) node regout_en_4 = or(_regout_en_T_39, _regout_en_T_36) node regout_sel_0_4 = bits(sinkC_req.bankSel, 4, 4) node regout_sel_1_4 = bits(sourceC_req.bankSel, 4, 4) node regout_sel_2_4 = bits(sinkD_req.bankSel, 4, 4) node regout_sel_3_4 = bits(sourceD_wreq.bankSel, 4, 4) node regout_sel_4_4 = bits(sourceD_rreq.bankSel, 4, 4) node _regout_wen_T_12 = mux(regout_sel_3_4, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_13 = mux(regout_sel_2_4, sinkD_req.wen, _regout_wen_T_12) node _regout_wen_T_14 = mux(regout_sel_1_4, sourceC_req.wen, _regout_wen_T_13) node regout_wen_4 = mux(regout_sel_0_4, sinkC_req.wen, _regout_wen_T_14) node _regout_idx_T_12 = mux(regout_sel_3_4, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_13 = mux(regout_sel_2_4, sinkD_req.index, _regout_idx_T_12) node _regout_idx_T_14 = mux(regout_sel_1_4, sourceC_req.index, _regout_idx_T_13) node regout_idx_4 = mux(regout_sel_0_4, sinkC_req.index, _regout_idx_T_14) node _regout_data_T_12 = mux(regout_sel_3_4, sourceD_wreq.data[4], sourceD_rreq.data[4]) node _regout_data_T_13 = mux(regout_sel_2_4, sinkD_req.data[4], _regout_data_T_12) node _regout_data_T_14 = mux(regout_sel_1_4, sourceC_req.data[4], _regout_data_T_13) node regout_data_4 = mux(regout_sel_0_4, sinkC_req.data[4], _regout_data_T_14) node _regout_T_20 = and(regout_wen_4, regout_en_4) when _regout_T_20 : write mport regout_MPORT_8 = cc_banks_4[regout_idx_4], clock connect regout_MPORT_8, regout_data_4 node _regout_T_21 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_22 = and(_regout_T_21, regout_en_4) wire _regout_WIRE_4 : UInt<13> invalidate _regout_WIRE_4 when _regout_T_22 : connect _regout_WIRE_4, regout_idx_4 read mport regout_MPORT_9 = cc_banks_4[_regout_WIRE_4], clock node _regout_T_23 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_24 = and(_regout_T_23, regout_en_4) reg regout_REG_4 : UInt<1>, clock connect regout_REG_4, _regout_T_24 reg regout_r_4 : UInt<64>, clock when regout_REG_4 : connect regout_r_4, regout_MPORT_9 node _regout_en_T_40 = bits(sinkC_req.bankEn, 5, 5) node _regout_en_T_41 = bits(sourceC_req.bankEn, 5, 5) node _regout_en_T_42 = bits(sinkD_req.bankEn, 5, 5) node _regout_en_T_43 = bits(sourceD_wreq.bankEn, 5, 5) node _regout_en_T_44 = bits(sourceD_rreq.bankEn, 5, 5) node _regout_en_T_45 = or(_regout_en_T_40, _regout_en_T_41) node _regout_en_T_46 = or(_regout_en_T_45, _regout_en_T_42) node _regout_en_T_47 = or(_regout_en_T_46, _regout_en_T_43) node regout_en_5 = or(_regout_en_T_47, _regout_en_T_44) node regout_sel_0_5 = bits(sinkC_req.bankSel, 5, 5) node regout_sel_1_5 = bits(sourceC_req.bankSel, 5, 5) node regout_sel_2_5 = bits(sinkD_req.bankSel, 5, 5) node regout_sel_3_5 = bits(sourceD_wreq.bankSel, 5, 5) node regout_sel_4_5 = bits(sourceD_rreq.bankSel, 5, 5) node _regout_wen_T_15 = mux(regout_sel_3_5, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_16 = mux(regout_sel_2_5, sinkD_req.wen, _regout_wen_T_15) node _regout_wen_T_17 = mux(regout_sel_1_5, sourceC_req.wen, _regout_wen_T_16) node regout_wen_5 = mux(regout_sel_0_5, sinkC_req.wen, _regout_wen_T_17) node _regout_idx_T_15 = mux(regout_sel_3_5, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_16 = mux(regout_sel_2_5, sinkD_req.index, _regout_idx_T_15) node _regout_idx_T_17 = mux(regout_sel_1_5, sourceC_req.index, _regout_idx_T_16) node regout_idx_5 = mux(regout_sel_0_5, sinkC_req.index, _regout_idx_T_17) node _regout_data_T_15 = mux(regout_sel_3_5, sourceD_wreq.data[5], sourceD_rreq.data[5]) node _regout_data_T_16 = mux(regout_sel_2_5, sinkD_req.data[5], _regout_data_T_15) node _regout_data_T_17 = mux(regout_sel_1_5, sourceC_req.data[5], _regout_data_T_16) node regout_data_5 = mux(regout_sel_0_5, sinkC_req.data[5], _regout_data_T_17) node _regout_T_25 = and(regout_wen_5, regout_en_5) when _regout_T_25 : write mport regout_MPORT_10 = cc_banks_5[regout_idx_5], clock connect regout_MPORT_10, regout_data_5 node _regout_T_26 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_27 = and(_regout_T_26, regout_en_5) wire _regout_WIRE_5 : UInt<13> invalidate _regout_WIRE_5 when _regout_T_27 : connect _regout_WIRE_5, regout_idx_5 read mport regout_MPORT_11 = cc_banks_5[_regout_WIRE_5], clock node _regout_T_28 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_29 = and(_regout_T_28, regout_en_5) reg regout_REG_5 : UInt<1>, clock connect regout_REG_5, _regout_T_29 reg regout_r_5 : UInt<64>, clock when regout_REG_5 : connect regout_r_5, regout_MPORT_11 node _regout_en_T_48 = bits(sinkC_req.bankEn, 6, 6) node _regout_en_T_49 = bits(sourceC_req.bankEn, 6, 6) node _regout_en_T_50 = bits(sinkD_req.bankEn, 6, 6) node _regout_en_T_51 = bits(sourceD_wreq.bankEn, 6, 6) node _regout_en_T_52 = bits(sourceD_rreq.bankEn, 6, 6) node _regout_en_T_53 = or(_regout_en_T_48, _regout_en_T_49) node _regout_en_T_54 = or(_regout_en_T_53, _regout_en_T_50) node _regout_en_T_55 = or(_regout_en_T_54, _regout_en_T_51) node regout_en_6 = or(_regout_en_T_55, _regout_en_T_52) node regout_sel_0_6 = bits(sinkC_req.bankSel, 6, 6) node regout_sel_1_6 = bits(sourceC_req.bankSel, 6, 6) node regout_sel_2_6 = bits(sinkD_req.bankSel, 6, 6) node regout_sel_3_6 = bits(sourceD_wreq.bankSel, 6, 6) node regout_sel_4_6 = bits(sourceD_rreq.bankSel, 6, 6) node _regout_wen_T_18 = mux(regout_sel_3_6, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_19 = mux(regout_sel_2_6, sinkD_req.wen, _regout_wen_T_18) node _regout_wen_T_20 = mux(regout_sel_1_6, sourceC_req.wen, _regout_wen_T_19) node regout_wen_6 = mux(regout_sel_0_6, sinkC_req.wen, _regout_wen_T_20) node _regout_idx_T_18 = mux(regout_sel_3_6, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_19 = mux(regout_sel_2_6, sinkD_req.index, _regout_idx_T_18) node _regout_idx_T_20 = mux(regout_sel_1_6, sourceC_req.index, _regout_idx_T_19) node regout_idx_6 = mux(regout_sel_0_6, sinkC_req.index, _regout_idx_T_20) node _regout_data_T_18 = mux(regout_sel_3_6, sourceD_wreq.data[6], sourceD_rreq.data[6]) node _regout_data_T_19 = mux(regout_sel_2_6, sinkD_req.data[6], _regout_data_T_18) node _regout_data_T_20 = mux(regout_sel_1_6, sourceC_req.data[6], _regout_data_T_19) node regout_data_6 = mux(regout_sel_0_6, sinkC_req.data[6], _regout_data_T_20) node _regout_T_30 = and(regout_wen_6, regout_en_6) when _regout_T_30 : write mport regout_MPORT_12 = cc_banks_6[regout_idx_6], clock connect regout_MPORT_12, regout_data_6 node _regout_T_31 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_32 = and(_regout_T_31, regout_en_6) wire _regout_WIRE_6 : UInt<13> invalidate _regout_WIRE_6 when _regout_T_32 : connect _regout_WIRE_6, regout_idx_6 read mport regout_MPORT_13 = cc_banks_6[_regout_WIRE_6], clock node _regout_T_33 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_34 = and(_regout_T_33, regout_en_6) reg regout_REG_6 : UInt<1>, clock connect regout_REG_6, _regout_T_34 reg regout_r_6 : UInt<64>, clock when regout_REG_6 : connect regout_r_6, regout_MPORT_13 node _regout_en_T_56 = bits(sinkC_req.bankEn, 7, 7) node _regout_en_T_57 = bits(sourceC_req.bankEn, 7, 7) node _regout_en_T_58 = bits(sinkD_req.bankEn, 7, 7) node _regout_en_T_59 = bits(sourceD_wreq.bankEn, 7, 7) node _regout_en_T_60 = bits(sourceD_rreq.bankEn, 7, 7) node _regout_en_T_61 = or(_regout_en_T_56, _regout_en_T_57) node _regout_en_T_62 = or(_regout_en_T_61, _regout_en_T_58) node _regout_en_T_63 = or(_regout_en_T_62, _regout_en_T_59) node regout_en_7 = or(_regout_en_T_63, _regout_en_T_60) node regout_sel_0_7 = bits(sinkC_req.bankSel, 7, 7) node regout_sel_1_7 = bits(sourceC_req.bankSel, 7, 7) node regout_sel_2_7 = bits(sinkD_req.bankSel, 7, 7) node regout_sel_3_7 = bits(sourceD_wreq.bankSel, 7, 7) node regout_sel_4_7 = bits(sourceD_rreq.bankSel, 7, 7) node _regout_wen_T_21 = mux(regout_sel_3_7, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_22 = mux(regout_sel_2_7, sinkD_req.wen, _regout_wen_T_21) node _regout_wen_T_23 = mux(regout_sel_1_7, sourceC_req.wen, _regout_wen_T_22) node regout_wen_7 = mux(regout_sel_0_7, sinkC_req.wen, _regout_wen_T_23) node _regout_idx_T_21 = mux(regout_sel_3_7, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_22 = mux(regout_sel_2_7, sinkD_req.index, _regout_idx_T_21) node _regout_idx_T_23 = mux(regout_sel_1_7, sourceC_req.index, _regout_idx_T_22) node regout_idx_7 = mux(regout_sel_0_7, sinkC_req.index, _regout_idx_T_23) node _regout_data_T_21 = mux(regout_sel_3_7, sourceD_wreq.data[7], sourceD_rreq.data[7]) node _regout_data_T_22 = mux(regout_sel_2_7, sinkD_req.data[7], _regout_data_T_21) node _regout_data_T_23 = mux(regout_sel_1_7, sourceC_req.data[7], _regout_data_T_22) node regout_data_7 = mux(regout_sel_0_7, sinkC_req.data[7], _regout_data_T_23) node _regout_T_35 = and(regout_wen_7, regout_en_7) when _regout_T_35 : write mport regout_MPORT_14 = cc_banks_7[regout_idx_7], clock connect regout_MPORT_14, regout_data_7 node _regout_T_36 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_37 = and(_regout_T_36, regout_en_7) wire _regout_WIRE_7 : UInt<13> invalidate _regout_WIRE_7 when _regout_T_37 : connect _regout_WIRE_7, regout_idx_7 read mport regout_MPORT_15 = cc_banks_7[_regout_WIRE_7], clock node _regout_T_38 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_39 = and(_regout_T_38, regout_en_7) reg regout_REG_7 : UInt<1>, clock connect regout_REG_7, _regout_T_39 reg regout_r_7 : UInt<64>, clock when regout_REG_7 : connect regout_r_7, regout_MPORT_15 wire regout : UInt<64>[8] connect regout[0], regout_r connect regout[1], regout_r_1 connect regout[2], regout_r_2 connect regout[3], regout_r_3 connect regout[4], regout_r_4 connect regout[5], regout_r_5 connect regout[6], regout_r_6 connect regout[7], regout_r_7 reg regsel_sourceC_REG : UInt, clock connect regsel_sourceC_REG, sourceC_req.bankEn reg regsel_sourceC : UInt, clock connect regsel_sourceC, regsel_sourceC_REG reg regsel_sourceD_REG : UInt, clock connect regsel_sourceD_REG, sourceD_rreq.bankEn reg regsel_sourceD : UInt, clock connect regsel_sourceD, regsel_sourceD_REG node _decodeC_T = bits(regsel_sourceC, 0, 0) node _decodeC_T_1 = mux(_decodeC_T, regout[0], UInt<1>(0h0)) node _decodeC_T_2 = bits(regsel_sourceC, 1, 1) node _decodeC_T_3 = mux(_decodeC_T_2, regout[1], UInt<1>(0h0)) node _decodeC_T_4 = bits(regsel_sourceC, 2, 2) node _decodeC_T_5 = mux(_decodeC_T_4, regout[2], UInt<1>(0h0)) node _decodeC_T_6 = bits(regsel_sourceC, 3, 3) node _decodeC_T_7 = mux(_decodeC_T_6, regout[3], UInt<1>(0h0)) node _decodeC_T_8 = bits(regsel_sourceC, 4, 4) node _decodeC_T_9 = mux(_decodeC_T_8, regout[4], UInt<1>(0h0)) node _decodeC_T_10 = bits(regsel_sourceC, 5, 5) node _decodeC_T_11 = mux(_decodeC_T_10, regout[5], UInt<1>(0h0)) node _decodeC_T_12 = bits(regsel_sourceC, 6, 6) node _decodeC_T_13 = mux(_decodeC_T_12, regout[6], UInt<1>(0h0)) node _decodeC_T_14 = bits(regsel_sourceC, 7, 7) node _decodeC_T_15 = mux(_decodeC_T_14, regout[7], UInt<1>(0h0)) node _decodeC_T_16 = or(_decodeC_T_1, _decodeC_T_3) node _decodeC_T_17 = or(_decodeC_T_16, _decodeC_T_5) node _decodeC_T_18 = or(_decodeC_T_17, _decodeC_T_7) node _decodeC_T_19 = or(_decodeC_T_18, _decodeC_T_9) node _decodeC_T_20 = or(_decodeC_T_19, _decodeC_T_11) node _decodeC_T_21 = or(_decodeC_T_20, _decodeC_T_13) node decodeC_0 = or(_decodeC_T_21, _decodeC_T_15) connect io.sourceC_dat.data, decodeC_0 node _decodeD_T = bits(regsel_sourceD, 0, 0) node _decodeD_T_1 = mux(_decodeD_T, regout[0], UInt<1>(0h0)) node _decodeD_T_2 = bits(regsel_sourceD, 1, 1) node _decodeD_T_3 = mux(_decodeD_T_2, regout[1], UInt<1>(0h0)) node _decodeD_T_4 = bits(regsel_sourceD, 2, 2) node _decodeD_T_5 = mux(_decodeD_T_4, regout[2], UInt<1>(0h0)) node _decodeD_T_6 = bits(regsel_sourceD, 3, 3) node _decodeD_T_7 = mux(_decodeD_T_6, regout[3], UInt<1>(0h0)) node _decodeD_T_8 = bits(regsel_sourceD, 4, 4) node _decodeD_T_9 = mux(_decodeD_T_8, regout[4], UInt<1>(0h0)) node _decodeD_T_10 = bits(regsel_sourceD, 5, 5) node _decodeD_T_11 = mux(_decodeD_T_10, regout[5], UInt<1>(0h0)) node _decodeD_T_12 = bits(regsel_sourceD, 6, 6) node _decodeD_T_13 = mux(_decodeD_T_12, regout[6], UInt<1>(0h0)) node _decodeD_T_14 = bits(regsel_sourceD, 7, 7) node _decodeD_T_15 = mux(_decodeD_T_14, regout[7], UInt<1>(0h0)) node _decodeD_T_16 = or(_decodeD_T_1, _decodeD_T_5) node _decodeD_T_17 = or(_decodeD_T_16, _decodeD_T_9) node decodeD_0 = or(_decodeD_T_17, _decodeD_T_13) node _decodeD_T_18 = or(_decodeD_T_3, _decodeD_T_7) node _decodeD_T_19 = or(_decodeD_T_18, _decodeD_T_11) node decodeD_1 = or(_decodeD_T_19, _decodeD_T_15) node _io_sourceD_rdat_data_T = cat(decodeD_1, decodeD_0) connect io.sourceD_rdat.data, _io_sourceD_rdat_data_T	module BankedStore( // @[BankedStore.scala:59:7] input clock, // @[BankedStore.scala:59:7] input reset, // @[BankedStore.scala:59:7] output io_sinkC_adr_ready, // @[BankedStore.scala:61:14] input io_sinkC_adr_valid, // @[BankedStore.scala:61:14] input io_sinkC_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkC_adr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sinkC_dat_data, // @[BankedStore.scala:61:14] output io_sinkD_adr_ready, // @[BankedStore.scala:61:14] input io_sinkD_adr_valid, // @[BankedStore.scala:61:14] input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14] input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14] output io_sourceC_adr_ready, // @[BankedStore.scala:61:14] input io_sourceC_adr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14] output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14] output io_sourceD_radr_ready, // @[BankedStore.scala:61:14] input io_sourceD_radr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14] output [127:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14] output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14] input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14] ); wire [7:0] sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [63:0] _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_sinkC_adr_valid_0 = io_sinkC_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkC_adr_bits_noop_0 = io_sinkC_adr_bits_noop; // @[BankedStore.scala:59:7] wire [2:0] io_sinkC_adr_bits_way_0 = io_sinkC_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sinkC_adr_bits_set_0 = io_sinkC_adr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_beat_0 = io_sinkC_adr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_mask_0 = io_sinkC_adr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sinkC_dat_data_0 = io_sinkC_dat_data; // @[BankedStore.scala:59:7] wire io_sinkD_adr_valid_0 = io_sinkD_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkD_adr_bits_noop_0 = io_sinkD_adr_bits_noop; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_way_0 = io_sinkD_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sinkD_adr_bits_set_0 = io_sinkD_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_beat_0 = io_sinkD_adr_bits_beat; // @[BankedStore.scala:59:7] wire [63:0] io_sinkD_dat_data_0 = io_sinkD_dat_data; // @[BankedStore.scala:59:7] wire io_sourceC_adr_valid_0 = io_sourceC_adr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_way_0 = io_sourceC_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceC_adr_bits_set_0 = io_sourceC_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_beat_0 = io_sourceC_adr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_radr_valid_0 = io_sourceD_radr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_radr_bits_way_0 = io_sourceD_radr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_radr_bits_set_0 = io_sourceD_radr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_beat_0 = io_sourceD_radr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_mask_0 = io_sourceD_radr_bits_mask; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_valid_0 = io_sourceD_wadr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_wadr_bits_way_0 = io_sourceD_wadr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_wadr_bits_set_0 = io_sourceD_wadr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_beat_0 = io_sourceD_wadr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_mask_0 = io_sourceD_wadr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_wdat_data_0 = io_sourceD_wdat_data; // @[BankedStore.scala:59:7] wire [7:0] sinkC_req_bankSum = 8'h0; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_ready_T = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_1 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_4 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_5 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_8 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_9 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_12 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_13 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] sinkC_req_ready_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] _sinkC_req_out_bankEn_T_4 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_5 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_6 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_7 = 2'h3; // @[BankedStore.scala:137:72] wire [3:0] sinkC_req_ready = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_lo = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_hi = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [7:0] _sinkC_req_out_bankEn_T_8 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sinkD_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sourceC_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [63:0] sourceC_req_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire io_sourceC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire _sinkC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101] wire sourceC_req_wen = 1'h0; // @[BankedStore.scala:128:19] wire sourceD_rreq_wen = 1'h0; // @[BankedStore.scala:128:19] wire io_sinkD_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire io_sourceC_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire sinkC_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire _sinkC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72] wire sinkD_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire _sourceC_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire sourceD_wreq_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] sinkD_req_words_0 = io_sinkD_dat_data_0; // @[BankedStore.scala:59:7, :123:19] wire _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] decodeC_0; // @[BankedStore.scala:180:85] wire _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:132:21] wire [127:0] _io_sourceD_rdat_data_T; // @[BankedStore.scala:189:30] wire _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:132:21] wire io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] wire [63:0] io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] wire [12:0] regout_idx; // @[Mux.scala:50:70] wire _regout_T; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE; // @[BankedStore.scala:172:21] wire _regout_T_2; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_1; // @[Mux.scala:50:70] wire _regout_T_5; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_1; // @[BankedStore.scala:172:21] wire _regout_T_7; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_2; // @[Mux.scala:50:70] wire _regout_T_10; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_2; // @[BankedStore.scala:172:21] wire _regout_T_12; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_3; // @[Mux.scala:50:70] wire _regout_T_15; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_3; // @[BankedStore.scala:172:21] wire _regout_T_17; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_4; // @[Mux.scala:50:70] wire _regout_T_20; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_4; // @[BankedStore.scala:172:21] wire _regout_T_22; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_5; // @[Mux.scala:50:70] wire _regout_T_25; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_5; // @[BankedStore.scala:172:21] wire _regout_T_27; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_6; // @[Mux.scala:50:70] wire _regout_T_30; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_6; // @[BankedStore.scala:172:21] wire _regout_T_32; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_7; // @[Mux.scala:50:70] wire _regout_T_35; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_7; // @[BankedStore.scala:172:21] wire _regout_T_37; // @[BankedStore.scala:172:32] wire [63:0] sinkC_req_words_0 = io_sinkC_dat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_0 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_2 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_4 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_6 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_words_1 = io_sinkC_dat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_1 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_3 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_5 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_7 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sinkC_req_a_hi = {io_sinkC_adr_bits_way_0, io_sinkC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sinkC_req_a = {sinkC_req_a_hi, io_sinkC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sinkC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkC_req_out_bankEn_T_9 = sinkC_req_bankSel; // @[BankedStore.scala:128:19, :137:55] wire [7:0] sourceC_req_bankSum = sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sinkC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkC_req_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_select_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sinkC_req_io_sinkC_adr_ready_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sinkC_req_select_shiftAmount = _sinkC_req_select_T; // @[OneHot.scala:64:49] wire [3:0] _sinkC_req_select_T_1 = 4'h1 << sinkC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sinkC_req_select = _sinkC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hF >> _sinkC_req_io_sinkC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}, :137:72] assign _sinkC_req_io_sinkC_adr_ready_T_2 = _sinkC_req_io_sinkC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkC_adr_ready_0 = _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkC_req_out_index_T = sinkC_req_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sinkC_req_index = _sinkC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkC_req_out_bankSel_T = sinkC_req_select[0]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_1 = sinkC_req_select[1]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_2 = sinkC_req_select[2]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_3 = sinkC_req_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sinkC_req_out_bankSel_T_4 = {2{_sinkC_req_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_5 = {2{_sinkC_req_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_6 = {2{_sinkC_req_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_7 = {2{_sinkC_req_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_lo = {_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_hi = {_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sinkC_req_out_bankSel_T_8 = {sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sinkC_req_out_bankSel_T_9 = {2{io_sinkC_adr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sinkC_req_out_bankSel_T_10 = {2{_sinkC_req_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sinkC_req_out_bankSel_T_11 = _sinkC_req_out_bankSel_T_8 & _sinkC_req_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sinkC_req_out_bankSel_T_12 = io_sinkC_adr_valid_0 ? _sinkC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkC_req_bankSel = _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] assign _sinkC_req_out_bankEn_T_10 = io_sinkC_adr_bits_noop_0 ? 8'h0 : _sinkC_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkC_req_bankEn = _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sinkD_req_data_0 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_1 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_2 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_3 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_4 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_5 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_6 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_7 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sinkD_req_a_hi = {io_sinkD_adr_bits_way_0, io_sinkD_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sinkD_req_a = {sinkD_req_a_hi, io_sinkD_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sinkD_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sinkD_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sinkD_req_select_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sinkD_req_io_sinkD_adr_ready_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sinkD_req_select_shiftAmount = _sinkD_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sinkD_req_select_T_1 = 8'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sinkD_req_select = _sinkD_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sinkD_req_ready_T = sinkD_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_1 = _sinkD_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_2 = _sinkD_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_3 = ~_sinkD_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_4 = sinkD_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_5 = _sinkD_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_6 = _sinkD_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_7 = ~_sinkD_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_8 = sinkD_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_9 = _sinkD_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_10 = _sinkD_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_11 = ~_sinkD_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_12 = sinkD_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_13 = _sinkD_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_14 = _sinkD_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_15 = ~_sinkD_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_16 = sinkD_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_17 = _sinkD_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_18 = _sinkD_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_19 = ~_sinkD_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_20 = sinkD_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_21 = _sinkD_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_22 = _sinkD_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_23 = ~_sinkD_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_24 = sinkD_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_25 = _sinkD_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_26 = _sinkD_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_27 = ~_sinkD_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_28 = sinkD_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_29 = _sinkD_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_30 = _sinkD_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_31 = ~_sinkD_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sinkD_req_ready_lo_lo = {_sinkD_req_ready_T_7, _sinkD_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_lo_hi = {_sinkD_req_ready_T_15, _sinkD_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_lo = {sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sinkD_req_ready_hi_lo = {_sinkD_req_ready_T_23, _sinkD_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_hi_hi = {_sinkD_req_ready_T_31, _sinkD_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_hi = {sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sinkD_req_ready = {sinkD_req_ready_hi, sinkD_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _sinkD_req_io_sinkD_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sinkD_req_io_sinkD_adr_ready_T_2 = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkD_adr_ready_0 = _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkD_req_out_index_T = sinkD_req_a[15:3]; // @[BankedStore.scala:126:91, :135:23] assign sinkD_req_index = _sinkD_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkD_req_out_bankSel_T = sinkD_req_select[0]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_1 = sinkD_req_select[1]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_2 = sinkD_req_select[2]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_3 = sinkD_req_select[3]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_4 = sinkD_req_select[4]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_5 = sinkD_req_select[5]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_6 = sinkD_req_select[6]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_7 = sinkD_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sinkD_req_out_bankSel_lo_lo = {_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_lo_hi = {_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_lo = {sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_lo = {_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_hi = {_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_hi = {sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_8 = {sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_11 = _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sinkD_req_out_bankSel_T_12 = io_sinkD_adr_valid_0 ? _sinkD_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkD_req_bankSel = _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sinkD_req_out_bankEn_T = sinkD_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_1 = sinkD_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_2 = sinkD_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_3 = sinkD_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_4 = sinkD_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_5 = sinkD_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_6 = sinkD_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_7 = sinkD_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sinkD_req_out_bankEn_lo_lo = {_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_lo_hi = {_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_lo = {sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_lo = {_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_hi = {_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_hi = {sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_8 = {sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_9 = sinkD_req_bankSel & _sinkD_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sinkD_req_out_bankEn_T_10 = io_sinkD_adr_bits_noop_0 ? 8'h0 : _sinkD_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkD_req_bankEn = _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceC_req_a_hi = {io_sourceC_adr_bits_way_0, io_sourceC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sourceC_req_a = {sourceC_req_a_hi, io_sourceC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sourceC_req_select_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sourceC_req_io_sourceC_adr_ready_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sourceC_req_select_shiftAmount = _sourceC_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sourceC_req_select_T_1 = 8'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sourceC_req_select = _sourceC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sourceC_req_ready_T = sourceC_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_1 = _sourceC_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_2 = _sourceC_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_3 = ~_sourceC_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_4 = sourceC_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_5 = _sourceC_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_6 = _sourceC_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_7 = ~_sourceC_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_8 = sourceC_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_9 = _sourceC_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_10 = _sourceC_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_11 = ~_sourceC_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_12 = sourceC_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_13 = _sourceC_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_14 = _sourceC_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_15 = ~_sourceC_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_16 = sourceC_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_17 = _sourceC_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_18 = _sourceC_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_19 = ~_sourceC_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_20 = sourceC_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_21 = _sourceC_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_22 = _sourceC_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_23 = ~_sourceC_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_24 = sourceC_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_25 = _sourceC_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_26 = _sourceC_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_27 = ~_sourceC_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_28 = sourceC_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_29 = _sourceC_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_30 = _sourceC_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_31 = ~_sourceC_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceC_req_ready_lo_lo = {_sourceC_req_ready_T_7, _sourceC_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_lo_hi = {_sourceC_req_ready_T_15, _sourceC_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_lo = {sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sourceC_req_ready_hi_lo = {_sourceC_req_ready_T_23, _sourceC_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_hi_hi = {_sourceC_req_ready_T_31, _sourceC_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_hi = {sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sourceC_req_ready = {sourceC_req_ready_hi, sourceC_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> _sourceC_req_io_sourceC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceC_req_io_sourceC_adr_ready_T_2 = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceC_adr_ready_0 = _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceC_req_out_index_T = sourceC_req_a[15:3]; // @[BankedStore.scala:126:91, :135:23] assign sourceC_req_index = _sourceC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceC_req_out_bankSel_T = sourceC_req_select[0]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_1 = sourceC_req_select[1]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_2 = sourceC_req_select[2]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_3 = sourceC_req_select[3]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_4 = sourceC_req_select[4]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_5 = sourceC_req_select[5]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_6 = sourceC_req_select[6]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_7 = sourceC_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sourceC_req_out_bankSel_lo_lo = {_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_lo_hi = {_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_lo = {sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_lo = {_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_hi = {_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_hi = {sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_8 = {sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_11 = _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sourceC_req_out_bankSel_T_12 = io_sourceC_adr_valid_0 ? _sourceC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceC_req_bankSel = _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceC_req_out_bankEn_T = sourceC_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_1 = sourceC_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_2 = sourceC_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_3 = sourceC_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_4 = sourceC_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_5 = sourceC_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_6 = sourceC_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_7 = sourceC_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sourceC_req_out_bankEn_lo_lo = {_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_lo_hi = {_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_lo = {sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_lo = {_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_hi = {_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_hi = {sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_8 = {sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_9 = sourceC_req_bankSel & _sourceC_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceC_req_out_bankEn_T_10 = _sourceC_req_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceC_req_bankEn = _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceD_rreq_a_hi = {io_sourceD_radr_bits_way_0, io_sourceD_radr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sourceD_rreq_a = {sourceD_rreq_a_hi, io_sourceD_radr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceD_rreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceD_rreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_rreq_select_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_rreq_io_sourceD_radr_ready_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_rreq_select_shiftAmount = _sourceD_rreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_rreq_select_T_1 = 4'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_rreq_select = _sourceD_rreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_rreq_ready_T = sourceD_rreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_1 = _sourceD_rreq_ready_T & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_2 = \|_sourceD_rreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_3 = ~_sourceD_rreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_4 = sourceD_rreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_5 = _sourceD_rreq_ready_T_4 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_6 = \|_sourceD_rreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_7 = ~_sourceD_rreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_8 = sourceD_rreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_9 = _sourceD_rreq_ready_T_8 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_10 = \|_sourceD_rreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_11 = ~_sourceD_rreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_12 = sourceD_rreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_13 = _sourceD_rreq_ready_T_12 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_14 = \|_sourceD_rreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_15 = ~_sourceD_rreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_rreq_ready_lo = {_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_rreq_ready_hi = {_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_rreq_ready = {sourceD_rreq_ready_hi, sourceD_rreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _sourceD_rreq_io_sourceD_radr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_rreq_io_sourceD_radr_ready_T_2 = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_radr_ready_0 = _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_rreq_out_index_T = sourceD_rreq_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_rreq_index = _sourceD_rreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_rreq_out_bankSel_T = sourceD_rreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_1 = sourceD_rreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_2 = sourceD_rreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_3 = sourceD_rreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_rreq_out_bankSel_T_4 = {2{_sourceD_rreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_5 = {2{_sourceD_rreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_6 = {2{_sourceD_rreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_7 = {2{_sourceD_rreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_lo = {_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_hi = {_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_rreq_out_bankSel_T_8 = {sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_rreq_out_bankSel_T_9 = {2{io_sourceD_radr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_10 = {2{_sourceD_rreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_11 = _sourceD_rreq_out_bankSel_T_8 & _sourceD_rreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_rreq_out_bankSel_T_12 = io_sourceD_radr_valid_0 ? _sourceD_rreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_rreq_bankSel = _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_rreq_out_bankEn_T = sourceD_rreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_1 = sourceD_rreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_2 = sourceD_rreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_3 = sourceD_rreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_4 = {2{_sourceD_rreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_5 = {2{_sourceD_rreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_6 = {2{_sourceD_rreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_7 = {2{_sourceD_rreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_lo = {_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_hi = {_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_8 = {sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_9 = sourceD_rreq_bankSel & _sourceD_rreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_rreq_out_bankEn_T_10 = _sourceD_rreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_rreq_bankEn = _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sourceD_wreq_words_0 = io_sourceD_wdat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_0 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_2 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_4 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_6 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_words_1 = io_sourceD_wdat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_1 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_3 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_5 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_7 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sourceD_wreq_a_hi = {io_sourceD_wadr_bits_way_0, io_sourceD_wadr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sourceD_wreq_a = {sourceD_wreq_a_hi, io_sourceD_wadr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceD_wreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceD_wreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_wreq_select_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_wreq_io_sourceD_wadr_ready_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_wreq_select_shiftAmount = _sourceD_wreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_wreq_select_T_1 = 4'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_wreq_select = _sourceD_wreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_wreq_ready_T = sourceD_wreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_1 = _sourceD_wreq_ready_T & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_2 = \|_sourceD_wreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_3 = ~_sourceD_wreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_4 = sourceD_wreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_5 = _sourceD_wreq_ready_T_4 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_6 = \|_sourceD_wreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_7 = ~_sourceD_wreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_8 = sourceD_wreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_9 = _sourceD_wreq_ready_T_8 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_10 = \|_sourceD_wreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_11 = ~_sourceD_wreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_12 = sourceD_wreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_13 = _sourceD_wreq_ready_T_12 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_14 = \|_sourceD_wreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_15 = ~_sourceD_wreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_wreq_ready_lo = {_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_wreq_ready_hi = {_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_wreq_ready = {sourceD_wreq_ready_hi, sourceD_wreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _sourceD_wreq_io_sourceD_wadr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_wreq_io_sourceD_wadr_ready_T_2 = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_wadr_ready_0 = _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_wreq_out_index_T = sourceD_wreq_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_wreq_index = _sourceD_wreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_wreq_out_bankSel_T = sourceD_wreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_1 = sourceD_wreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_2 = sourceD_wreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_3 = sourceD_wreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_wreq_out_bankSel_T_4 = {2{_sourceD_wreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_5 = {2{_sourceD_wreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_6 = {2{_sourceD_wreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_7 = {2{_sourceD_wreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_lo = {_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_hi = {_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_wreq_out_bankSel_T_8 = {sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_wreq_out_bankSel_T_9 = {2{io_sourceD_wadr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_10 = {2{_sourceD_wreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_11 = _sourceD_wreq_out_bankSel_T_8 & _sourceD_wreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_wreq_out_bankSel_T_12 = io_sourceD_wadr_valid_0 ? _sourceD_wreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_wreq_bankSel = _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_wreq_out_bankEn_T = sourceD_wreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_1 = sourceD_wreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_2 = sourceD_wreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_3 = sourceD_wreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_4 = {2{_sourceD_wreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_5 = {2{_sourceD_wreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_6 = {2{_sourceD_wreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_7 = {2{_sourceD_wreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_lo = {_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_hi = {_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_8 = {sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_9 = sourceD_wreq_bankSel & _sourceD_wreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_wreq_out_bankEn_T_10 = _sourceD_wreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_wreq_bankEn = _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] assign sinkD_req_bankSum = sourceC_req_bankSel \| sinkC_req_bankSel; // @[BankedStore.scala:128:19, :161:17] assign sourceD_wreq_bankSum = sinkD_req_bankSel \| sinkD_req_bankSum; // @[BankedStore.scala:128:19, :161:17] assign sourceD_rreq_bankSum = sourceD_wreq_bankSel \| sourceD_wreq_bankSum; // @[BankedStore.scala:128:19, :161:17] wire _regout_en_T = sinkC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_1 = sourceC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_2 = sinkD_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_3 = sourceD_wreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_4 = sourceD_rreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_5 = _regout_en_T \| _regout_en_T_1; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_6 = _regout_en_T_5 \| _regout_en_T_2; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_7 = _regout_en_T_6 \| _regout_en_T_3; // @[BankedStore.scala:165:{32,45}] wire regout_en = _regout_en_T_7 \| _regout_en_T_4; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0 = sinkC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1 = sourceC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2 = sinkD_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3 = sourceD_wreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T = regout_sel_3; // @[Mux.scala:50:70] wire regout_sel_4 = sourceD_rreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_1 = regout_sel_2 \| _regout_wen_T; // @[Mux.scala:50:70] wire _regout_wen_T_2 = ~regout_sel_1 & _regout_wen_T_1; // @[Mux.scala:50:70] wire regout_wen = regout_sel_0 \| _regout_wen_T_2; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T = regout_sel_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_1 = regout_sel_2 ? sinkD_req_index : _regout_idx_T; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_2 = regout_sel_1 ? sourceC_req_index : _regout_idx_T_1; // @[Mux.scala:50:70] assign regout_idx = regout_sel_0 ? sinkC_req_index : _regout_idx_T_2; // @[Mux.scala:50:70] assign _regout_WIRE = regout_idx; // @[Mux.scala:50:70] wire [63:0] _regout_data_T = regout_sel_3 ? sourceD_wreq_data_0 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_1 = regout_sel_2 ? sinkD_req_data_0 : _regout_data_T; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_2 = regout_sel_1 ? 64'h0 : _regout_data_T_1; // @[Mux.scala:50:70] wire [63:0] regout_data = regout_sel_0 ? sinkC_req_data_0 : _regout_data_T_2; // @[Mux.scala:50:70] assign _regout_T = regout_wen & regout_en; // @[Mux.scala:50:70] wire _regout_T_1 = ~regout_wen; // @[Mux.scala:50:70] assign _regout_T_2 = _regout_T_1 & regout_en; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_3 = ~regout_wen; // @[Mux.scala:50:70] wire _regout_T_4 = _regout_T_3 & regout_en; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG; // @[BankedStore.scala:172:47] reg [63:0] regout_r; // @[BankedStore.scala:172:14] wire [63:0] regout_0 = regout_r; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_8 = sinkC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_9 = sourceC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_10 = sinkD_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_11 = sourceD_wreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_12 = sourceD_rreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_13 = _regout_en_T_8 \| _regout_en_T_9; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_14 = _regout_en_T_13 \| _regout_en_T_10; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_15 = _regout_en_T_14 \| _regout_en_T_11; // @[BankedStore.scala:165:{32,45}] wire regout_en_1 = _regout_en_T_15 \| _regout_en_T_12; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_1 = sinkC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_1 = sourceC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_1 = sinkD_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_1 = sourceD_wreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_3 = regout_sel_3_1; // @[Mux.scala:50:70] wire regout_sel_4_1 = sourceD_rreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_4 = regout_sel_2_1 \| _regout_wen_T_3; // @[Mux.scala:50:70] wire _regout_wen_T_5 = ~regout_sel_1_1 & _regout_wen_T_4; // @[Mux.scala:50:70] wire regout_wen_1 = regout_sel_0_1 \| _regout_wen_T_5; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_3 = regout_sel_3_1 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_4 = regout_sel_2_1 ? sinkD_req_index : _regout_idx_T_3; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_5 = regout_sel_1_1 ? sourceC_req_index : _regout_idx_T_4; // @[Mux.scala:50:70] assign regout_idx_1 = regout_sel_0_1 ? sinkC_req_index : _regout_idx_T_5; // @[Mux.scala:50:70] assign _regout_WIRE_1 = regout_idx_1; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_3 = regout_sel_3_1 ? sourceD_wreq_data_1 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_4 = regout_sel_2_1 ? sinkD_req_data_1 : _regout_data_T_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_5 = regout_sel_1_1 ? 64'h0 : _regout_data_T_4; // @[Mux.scala:50:70] wire [63:0] regout_data_1 = regout_sel_0_1 ? sinkC_req_data_1 : _regout_data_T_5; // @[Mux.scala:50:70] assign _regout_T_5 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] wire _regout_T_6 = ~regout_wen_1; // @[Mux.scala:50:70] assign _regout_T_7 = _regout_T_6 & regout_en_1; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_8 = ~regout_wen_1; // @[Mux.scala:50:70] wire _regout_T_9 = _regout_T_8 & regout_en_1; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_1; // @[BankedStore.scala:172:47] reg [63:0] regout_r_1; // @[BankedStore.scala:172:14] wire [63:0] regout_1 = regout_r_1; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_16 = sinkC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_17 = sourceC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_18 = sinkD_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_19 = sourceD_wreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_20 = sourceD_rreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_21 = _regout_en_T_16 \| _regout_en_T_17; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_22 = _regout_en_T_21 \| _regout_en_T_18; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_23 = _regout_en_T_22 \| _regout_en_T_19; // @[BankedStore.scala:165:{32,45}] wire regout_en_2 = _regout_en_T_23 \| _regout_en_T_20; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_2 = sinkC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_2 = sourceC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_2 = sinkD_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_2 = sourceD_wreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_6 = regout_sel_3_2; // @[Mux.scala:50:70] wire regout_sel_4_2 = sourceD_rreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_7 = regout_sel_2_2 \| _regout_wen_T_6; // @[Mux.scala:50:70] wire _regout_wen_T_8 = ~regout_sel_1_2 & _regout_wen_T_7; // @[Mux.scala:50:70] wire regout_wen_2 = regout_sel_0_2 \| _regout_wen_T_8; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_6 = regout_sel_3_2 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_7 = regout_sel_2_2 ? sinkD_req_index : _regout_idx_T_6; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_8 = regout_sel_1_2 ? sourceC_req_index : _regout_idx_T_7; // @[Mux.scala:50:70] assign regout_idx_2 = regout_sel_0_2 ? sinkC_req_index : _regout_idx_T_8; // @[Mux.scala:50:70] assign _regout_WIRE_2 = regout_idx_2; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_6 = regout_sel_3_2 ? sourceD_wreq_data_2 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_7 = regout_sel_2_2 ? sinkD_req_data_2 : _regout_data_T_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_8 = regout_sel_1_2 ? 64'h0 : _regout_data_T_7; // @[Mux.scala:50:70] wire [63:0] regout_data_2 = regout_sel_0_2 ? sinkC_req_data_2 : _regout_data_T_8; // @[Mux.scala:50:70] assign _regout_T_10 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] wire _regout_T_11 = ~regout_wen_2; // @[Mux.scala:50:70] assign _regout_T_12 = _regout_T_11 & regout_en_2; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_13 = ~regout_wen_2; // @[Mux.scala:50:70] wire _regout_T_14 = _regout_T_13 & regout_en_2; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_2; // @[BankedStore.scala:172:47] reg [63:0] regout_r_2; // @[BankedStore.scala:172:14] wire [63:0] regout_2 = regout_r_2; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_24 = sinkC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_25 = sourceC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_26 = sinkD_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_27 = sourceD_wreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_28 = sourceD_rreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_29 = _regout_en_T_24 \| _regout_en_T_25; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_30 = _regout_en_T_29 \| _regout_en_T_26; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_31 = _regout_en_T_30 \| _regout_en_T_27; // @[BankedStore.scala:165:{32,45}] wire regout_en_3 = _regout_en_T_31 \| _regout_en_T_28; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_3 = sinkC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_3 = sourceC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_3 = sinkD_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_3 = sourceD_wreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_9 = regout_sel_3_3; // @[Mux.scala:50:70] wire regout_sel_4_3 = sourceD_rreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_10 = regout_sel_2_3 \| _regout_wen_T_9; // @[Mux.scala:50:70] wire _regout_wen_T_11 = ~regout_sel_1_3 & _regout_wen_T_10; // @[Mux.scala:50:70] wire regout_wen_3 = regout_sel_0_3 \| _regout_wen_T_11; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_9 = regout_sel_3_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_10 = regout_sel_2_3 ? sinkD_req_index : _regout_idx_T_9; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_11 = regout_sel_1_3 ? sourceC_req_index : _regout_idx_T_10; // @[Mux.scala:50:70] assign regout_idx_3 = regout_sel_0_3 ? sinkC_req_index : _regout_idx_T_11; // @[Mux.scala:50:70] assign _regout_WIRE_3 = regout_idx_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_9 = regout_sel_3_3 ? sourceD_wreq_data_3 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_10 = regout_sel_2_3 ? sinkD_req_data_3 : _regout_data_T_9; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_11 = regout_sel_1_3 ? 64'h0 : _regout_data_T_10; // @[Mux.scala:50:70] wire [63:0] regout_data_3 = regout_sel_0_3 ? sinkC_req_data_3 : _regout_data_T_11; // @[Mux.scala:50:70] assign _regout_T_15 = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] wire _regout_T_16 = ~regout_wen_3; // @[Mux.scala:50:70] assign _regout_T_17 = _regout_T_16 & regout_en_3; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_18 = ~regout_wen_3; // @[Mux.scala:50:70] wire _regout_T_19 = _regout_T_18 & regout_en_3; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_3; // @[BankedStore.scala:172:47] reg [63:0] regout_r_3; // @[BankedStore.scala:172:14] wire [63:0] regout_3 = regout_r_3; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_32 = sinkC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_33 = sourceC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_34 = sinkD_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_35 = sourceD_wreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_36 = sourceD_rreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_37 = _regout_en_T_32 \| _regout_en_T_33; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_38 = _regout_en_T_37 \| _regout_en_T_34; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_39 = _regout_en_T_38 \| _regout_en_T_35; // @[BankedStore.scala:165:{32,45}] wire regout_en_4 = _regout_en_T_39 \| _regout_en_T_36; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_4 = sinkC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_4 = sourceC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_4 = sinkD_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_4 = sourceD_wreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_12 = regout_sel_3_4; // @[Mux.scala:50:70] wire regout_sel_4_4 = sourceD_rreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_13 = regout_sel_2_4 \| _regout_wen_T_12; // @[Mux.scala:50:70] wire _regout_wen_T_14 = ~regout_sel_1_4 & _regout_wen_T_13; // @[Mux.scala:50:70] wire regout_wen_4 = regout_sel_0_4 \| _regout_wen_T_14; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_12 = regout_sel_3_4 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_13 = regout_sel_2_4 ? sinkD_req_index : _regout_idx_T_12; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_14 = regout_sel_1_4 ? sourceC_req_index : _regout_idx_T_13; // @[Mux.scala:50:70] assign regout_idx_4 = regout_sel_0_4 ? sinkC_req_index : _regout_idx_T_14; // @[Mux.scala:50:70] assign _regout_WIRE_4 = regout_idx_4; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_12 = regout_sel_3_4 ? sourceD_wreq_data_4 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_13 = regout_sel_2_4 ? sinkD_req_data_4 : _regout_data_T_12; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_14 = regout_sel_1_4 ? 64'h0 : _regout_data_T_13; // @[Mux.scala:50:70] wire [63:0] regout_data_4 = regout_sel_0_4 ? sinkC_req_data_4 : _regout_data_T_14; // @[Mux.scala:50:70] assign _regout_T_20 = regout_wen_4 & regout_en_4; // @[Mux.scala:50:70] wire _regout_T_21 = ~regout_wen_4; // @[Mux.scala:50:70] assign _regout_T_22 = _regout_T_21 & regout_en_4; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_23 = ~regout_wen_4; // @[Mux.scala:50:70] wire _regout_T_24 = _regout_T_23 & regout_en_4; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_4; // @[BankedStore.scala:172:47] reg [63:0] regout_r_4; // @[BankedStore.scala:172:14] wire [63:0] regout_4 = regout_r_4; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_40 = sinkC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_41 = sourceC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_42 = sinkD_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_43 = sourceD_wreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_44 = sourceD_rreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_45 = _regout_en_T_40 \| _regout_en_T_41; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_46 = _regout_en_T_45 \| _regout_en_T_42; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_47 = _regout_en_T_46 \| _regout_en_T_43; // @[BankedStore.scala:165:{32,45}] wire regout_en_5 = _regout_en_T_47 \| _regout_en_T_44; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_5 = sinkC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_5 = sourceC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_5 = sinkD_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_5 = sourceD_wreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_15 = regout_sel_3_5; // @[Mux.scala:50:70] wire regout_sel_4_5 = sourceD_rreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_16 = regout_sel_2_5 \| _regout_wen_T_15; // @[Mux.scala:50:70] wire _regout_wen_T_17 = ~regout_sel_1_5 & _regout_wen_T_16; // @[Mux.scala:50:70] wire regout_wen_5 = regout_sel_0_5 \| _regout_wen_T_17; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_15 = regout_sel_3_5 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_16 = regout_sel_2_5 ? sinkD_req_index : _regout_idx_T_15; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_17 = regout_sel_1_5 ? sourceC_req_index : _regout_idx_T_16; // @[Mux.scala:50:70] assign regout_idx_5 = regout_sel_0_5 ? sinkC_req_index : _regout_idx_T_17; // @[Mux.scala:50:70] assign _regout_WIRE_5 = regout_idx_5; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_15 = regout_sel_3_5 ? sourceD_wreq_data_5 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_16 = regout_sel_2_5 ? sinkD_req_data_5 : _regout_data_T_15; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_17 = regout_sel_1_5 ? 64'h0 : _regout_data_T_16; // @[Mux.scala:50:70] wire [63:0] regout_data_5 = regout_sel_0_5 ? sinkC_req_data_5 : _regout_data_T_17; // @[Mux.scala:50:70] assign _regout_T_25 = regout_wen_5 & regout_en_5; // @[Mux.scala:50:70] wire _regout_T_26 = ~regout_wen_5; // @[Mux.scala:50:70] assign _regout_T_27 = _regout_T_26 & regout_en_5; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_28 = ~regout_wen_5; // @[Mux.scala:50:70] wire _regout_T_29 = _regout_T_28 & regout_en_5; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_5; // @[BankedStore.scala:172:47] reg [63:0] regout_r_5; // @[BankedStore.scala:172:14] wire [63:0] regout_5 = regout_r_5; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_48 = sinkC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_49 = sourceC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_50 = sinkD_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_51 = sourceD_wreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_52 = sourceD_rreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_53 = _regout_en_T_48 \| _regout_en_T_49; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_54 = _regout_en_T_53 \| _regout_en_T_50; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_55 = _regout_en_T_54 \| _regout_en_T_51; // @[BankedStore.scala:165:{32,45}] wire regout_en_6 = _regout_en_T_55 \| _regout_en_T_52; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_6 = sinkC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_6 = sourceC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_6 = sinkD_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_6 = sourceD_wreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_18 = regout_sel_3_6; // @[Mux.scala:50:70] wire regout_sel_4_6 = sourceD_rreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_19 = regout_sel_2_6 \| _regout_wen_T_18; // @[Mux.scala:50:70] wire _regout_wen_T_20 = ~regout_sel_1_6 & _regout_wen_T_19; // @[Mux.scala:50:70] wire regout_wen_6 = regout_sel_0_6 \| _regout_wen_T_20; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_18 = regout_sel_3_6 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_19 = regout_sel_2_6 ? sinkD_req_index : _regout_idx_T_18; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_20 = regout_sel_1_6 ? sourceC_req_index : _regout_idx_T_19; // @[Mux.scala:50:70] assign regout_idx_6 = regout_sel_0_6 ? sinkC_req_index : _regout_idx_T_20; // @[Mux.scala:50:70] assign _regout_WIRE_6 = regout_idx_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_18 = regout_sel_3_6 ? sourceD_wreq_data_6 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_19 = regout_sel_2_6 ? sinkD_req_data_6 : _regout_data_T_18; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_20 = regout_sel_1_6 ? 64'h0 : _regout_data_T_19; // @[Mux.scala:50:70] wire [63:0] regout_data_6 = regout_sel_0_6 ? sinkC_req_data_6 : _regout_data_T_20; // @[Mux.scala:50:70] assign _regout_T_30 = regout_wen_6 & regout_en_6; // @[Mux.scala:50:70] wire _regout_T_31 = ~regout_wen_6; // @[Mux.scala:50:70] assign _regout_T_32 = _regout_T_31 & regout_en_6; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_33 = ~regout_wen_6; // @[Mux.scala:50:70] wire _regout_T_34 = _regout_T_33 & regout_en_6; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_6; // @[BankedStore.scala:172:47] reg [63:0] regout_r_6; // @[BankedStore.scala:172:14] wire [63:0] regout_6 = regout_r_6; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_56 = sinkC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_57 = sourceC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_58 = sinkD_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_59 = sourceD_wreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_60 = sourceD_rreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_61 = _regout_en_T_56 \| _regout_en_T_57; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_62 = _regout_en_T_61 \| _regout_en_T_58; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_63 = _regout_en_T_62 \| _regout_en_T_59; // @[BankedStore.scala:165:{32,45}] wire regout_en_7 = _regout_en_T_63 \| _regout_en_T_60; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_7 = sinkC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_7 = sourceC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_7 = sinkD_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_7 = sourceD_wreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_21 = regout_sel_3_7; // @[Mux.scala:50:70] wire regout_sel_4_7 = sourceD_rreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_22 = regout_sel_2_7 \| _regout_wen_T_21; // @[Mux.scala:50:70] wire _regout_wen_T_23 = ~regout_sel_1_7 & _regout_wen_T_22; // @[Mux.scala:50:70] wire regout_wen_7 = regout_sel_0_7 \| _regout_wen_T_23; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_21 = regout_sel_3_7 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_22 = regout_sel_2_7 ? sinkD_req_index : _regout_idx_T_21; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_23 = regout_sel_1_7 ? sourceC_req_index : _regout_idx_T_22; // @[Mux.scala:50:70] assign regout_idx_7 = regout_sel_0_7 ? sinkC_req_index : _regout_idx_T_23; // @[Mux.scala:50:70] assign _regout_WIRE_7 = regout_idx_7; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_21 = regout_sel_3_7 ? sourceD_wreq_data_7 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_22 = regout_sel_2_7 ? sinkD_req_data_7 : _regout_data_T_21; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_23 = regout_sel_1_7 ? 64'h0 : _regout_data_T_22; // @[Mux.scala:50:70] wire [63:0] regout_data_7 = regout_sel_0_7 ? sinkC_req_data_7 : _regout_data_T_23; // @[Mux.scala:50:70] assign _regout_T_35 = regout_wen_7 & regout_en_7; // @[Mux.scala:50:70] wire _regout_T_36 = ~regout_wen_7; // @[Mux.scala:50:70] assign _regout_T_37 = _regout_T_36 & regout_en_7; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_38 = ~regout_wen_7; // @[Mux.scala:50:70] wire _regout_T_39 = _regout_T_38 & regout_en_7; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_7; // @[BankedStore.scala:172:47] reg [63:0] regout_r_7; // @[BankedStore.scala:172:14] wire [63:0] regout_7 = regout_r_7; // @[BankedStore.scala:164:23, :172:14] reg [7:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39] reg [7:0] regsel_sourceC; // @[BankedStore.scala:175:31] reg [7:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39] reg [7:0] regsel_sourceD; // @[BankedStore.scala:176:31] wire _decodeC_T = regsel_sourceC[0]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_1 = _decodeC_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_2 = regsel_sourceC[1]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_3 = _decodeC_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_4 = regsel_sourceC[2]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_5 = _decodeC_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_6 = regsel_sourceC[3]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_7 = _decodeC_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_8 = regsel_sourceC[4]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_9 = _decodeC_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_10 = regsel_sourceC[5]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_11 = _decodeC_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_12 = regsel_sourceC[6]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_13 = _decodeC_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_14 = regsel_sourceC[7]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_15 = _decodeC_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire [63:0] _decodeC_T_16 = _decodeC_T_1 \| _decodeC_T_3; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_17 = _decodeC_T_16 \| _decodeC_T_5; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_18 = _decodeC_T_17 \| _decodeC_T_7; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_19 = _decodeC_T_18 \| _decodeC_T_9; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_20 = _decodeC_T_19 \| _decodeC_T_11; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_21 = _decodeC_T_20 \| _decodeC_T_13; // @[BankedStore.scala:179:23, :180:85] assign decodeC_0 = _decodeC_T_21 \| _decodeC_T_15; // @[BankedStore.scala:179:23, :180:85] assign io_sourceC_dat_data_0 = decodeC_0; // @[BankedStore.scala:59:7, :180:85] wire _decodeD_T = regsel_sourceD[0]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_1 = _decodeD_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_2 = regsel_sourceD[1]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_3 = _decodeD_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_4 = regsel_sourceD[2]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_5 = _decodeD_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_6 = regsel_sourceD[3]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_7 = _decodeD_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_8 = regsel_sourceD[4]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_9 = _decodeD_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_10 = regsel_sourceD[5]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_11 = _decodeD_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_12 = regsel_sourceD[6]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_13 = _decodeD_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_14 = regsel_sourceD[7]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_15 = _decodeD_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire [63:0] _decodeD_T_16 = _decodeD_T_1 \| _decodeD_T_5; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_17 = _decodeD_T_16 \| _decodeD_T_9; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_0 = _decodeD_T_17 \| _decodeD_T_13; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_18 = _decodeD_T_3 \| _decodeD_T_7; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_19 = _decodeD_T_18 \| _decodeD_T_11; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_1 = _decodeD_T_19 \| _decodeD_T_15; // @[BankedStore.scala:186:23, :187:85] assign _io_sourceD_rdat_data_T = {decodeD_1, decodeD_0}; // @[BankedStore.scala:187:85, :189:30] assign io_sourceD_rdat_data_0 = _io_sourceD_rdat_data_T; // @[BankedStore.scala:59:7, :189:30] always @(posedge clock) begin // @[BankedStore.scala:59:7] regout_REG <= _regout_T_4; // @[BankedStore.scala:172:{47,53}] if (regout_REG) // @[BankedStore.scala:172:47] regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_1 <= _regout_T_9; // @[BankedStore.scala:172:{47,53}] if (regout_REG_1) // @[BankedStore.scala:172:47] regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_2 <= _regout_T_14; // @[BankedStore.scala:172:{47,53}] if (regout_REG_2) // @[BankedStore.scala:172:47] regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_3 <= _regout_T_19; // @[BankedStore.scala:172:{47,53}] if (regout_REG_3) // @[BankedStore.scala:172:47] regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_4 <= _regout_T_24; // @[BankedStore.scala:172:{47,53}] if (regout_REG_4) // @[BankedStore.scala:172:47] regout_r_4 <= _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_5 <= _regout_T_29; // @[BankedStore.scala:172:{47,53}] if (regout_REG_5) // @[BankedStore.scala:172:47] regout_r_5 <= _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_6 <= _regout_T_34; // @[BankedStore.scala:172:{47,53}] if (regout_REG_6) // @[BankedStore.scala:172:47] regout_r_6 <= _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_7 <= _regout_T_39; // @[BankedStore.scala:172:{47,53}] if (regout_REG_7) // @[BankedStore.scala:172:47] regout_r_7 <= _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:128:19, :175:39] regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}] regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:128:19, :176:39] regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}] always @(posedge) cc_banks_0 cc_banks_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T ? regout_idx : _regout_WIRE), // @[Mux.scala:50:70] .RW0_en (_regout_T_2 \| _regout_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen), // @[Mux.scala:50:70] .RW0_wdata (regout_data), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_1 cc_banks_1 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_5 ? regout_idx_1 : _regout_WIRE_1), // @[Mux.scala:50:70] .RW0_en (_regout_T_7 \| _regout_T_5), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_1), // @[Mux.scala:50:70] .RW0_wdata (regout_data_1), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_1_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_2 cc_banks_2 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_10 ? regout_idx_2 : _regout_WIRE_2), // @[Mux.scala:50:70] .RW0_en (_regout_T_12 \| _regout_T_10), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_2), // @[Mux.scala:50:70] .RW0_wdata (regout_data_2), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_2_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_3 cc_banks_3 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_15 ? regout_idx_3 : _regout_WIRE_3), // @[Mux.scala:50:70] .RW0_en (_regout_T_17 \| _regout_T_15), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_3), // @[Mux.scala:50:70] .RW0_wdata (regout_data_3), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_3_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_4 cc_banks_4 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_20 ? regout_idx_4 : _regout_WIRE_4), // @[Mux.scala:50:70] .RW0_en (_regout_T_22 \| _regout_T_20), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_4), // @[Mux.scala:50:70] .RW0_wdata (regout_data_4), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_4_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_5 cc_banks_5 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_25 ? regout_idx_5 : _regout_WIRE_5), // @[Mux.scala:50:70] .RW0_en (_regout_T_27 \| _regout_T_25), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_5), // @[Mux.scala:50:70] .RW0_wdata (regout_data_5), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_5_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_6 cc_banks_6 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_30 ? regout_idx_6 : _regout_WIRE_6), // @[Mux.scala:50:70] .RW0_en (_regout_T_32 \| _regout_T_30), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_6), // @[Mux.scala:50:70] .RW0_wdata (regout_data_6), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_6_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_7 cc_banks_7 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_35 ? regout_idx_7 : _regout_WIRE_7), // @[Mux.scala:50:70] .RW0_en (_regout_T_37 \| _regout_T_35), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_7), // @[Mux.scala:50:70] .RW0_wdata (regout_data_7), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_7_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] assign io_sinkC_adr_ready = io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sinkD_adr_ready = io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_adr_ready = io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_dat_data = io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_radr_ready = io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceD_rdat_data = io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_wadr_ready = io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_247 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_247( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_17 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_17(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_6 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a32d256s5k3z4u_6( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget16 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_2 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a29d128s6k1z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 3, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonOut_a_bits_data_mux : UInt<64>[2] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[2] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<4>(0hf), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[1], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T \| _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel \| repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T \| _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready \| _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 \| _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 \| _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_2 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d128s6k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_3 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_3( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_387 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_387( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<13>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_70 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_71 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<13>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_86 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[20] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18]) node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = and(_T_11, _T_24) node _T_185 = and(_T_184, _T_37) node _T_186 = and(_T_185, _T_50) node _T_187 = and(_T_186, _T_63) node _T_188 = and(_T_187, _T_71) node _T_189 = and(_T_188, _T_79) node _T_190 = and(_T_189, _T_87) node _T_191 = and(_T_190, _T_95) node _T_192 = and(_T_191, _T_103) node _T_193 = and(_T_192, _T_111) node _T_194 = and(_T_193, _T_119) node _T_195 = and(_T_194, _T_127) node _T_196 = and(_T_195, _T_135) node _T_197 = and(_T_196, _T_143) node _T_198 = and(_T_197, _T_151) node _T_199 = and(_T_198, _T_159) node _T_200 = and(_T_199, _T_167) node _T_201 = and(_T_200, _T_175) node _T_202 = and(_T_201, _T_183) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_202, UInt<1>(0h1), "") : assert_1 node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_206 : node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_4) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<1>(0h1)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_5) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h2)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_6) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_229 = shr(io.in.a.bits.source, 2) node _T_230 = eq(_T_229, UInt<2>(0h3)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_7) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_250 = or(_T_210, _T_216) node _T_251 = or(_T_250, _T_222) node _T_252 = or(_T_251, _T_228) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_235) node _T_255 = or(_T_254, _T_236) node _T_256 = or(_T_255, _T_237) node _T_257 = or(_T_256, _T_238) node _T_258 = or(_T_257, _T_239) node _T_259 = or(_T_258, _T_240) node _T_260 = or(_T_259, _T_241) node _T_261 = or(_T_260, _T_242) node _T_262 = or(_T_261, _T_243) node _T_263 = or(_T_262, _T_244) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_246) node _T_266 = or(_T_265, _T_247) node _T_267 = or(_T_266, _T_248) node _T_268 = or(_T_267, _T_249) node _T_269 = and(_T_209, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<13>(0h1000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = and(_T_270, _T_278) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_279, UInt<1>(0h1), "") : assert_2 node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_8) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<1>(0h1)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_9) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h2)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_10) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<2>(0h3)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_11) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_317 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[20] connect _WIRE[0], _T_283 connect _WIRE[1], _T_289 connect _WIRE[2], _T_295 connect _WIRE[3], _T_301 connect _WIRE[4], _T_307 connect _WIRE[5], _T_308 connect _WIRE[6], _T_309 connect _WIRE[7], _T_310 connect _WIRE[8], _T_311 connect _WIRE[9], _T_312 connect _WIRE[10], _T_313 connect _WIRE[11], _T_314 connect _WIRE[12], _T_315 connect _WIRE[13], _T_316 connect _WIRE[14], _T_317 connect _WIRE[15], _T_318 connect _WIRE[16], _T_319 connect _WIRE[17], _T_320 connect _WIRE[18], _T_321 connect _WIRE[19], _T_322 node _T_323 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_324 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_325 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_326 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_327 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_328 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_329 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_331 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_332 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE[5], _T_323, UInt<1>(0h0)) node _T_335 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE[8], _T_324, UInt<1>(0h0)) node _T_338 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE[10], _T_325, UInt<1>(0h0)) node _T_340 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = mux(_WIRE[12], _T_326, UInt<1>(0h0)) node _T_342 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE[14], _T_327, UInt<1>(0h0)) node _T_344 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_345 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_346 = mux(_WIRE[17], _T_328, UInt<1>(0h0)) node _T_347 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_348 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_349 = or(_T_329, _T_330) node _T_350 = or(_T_349, _T_331) node _T_351 = or(_T_350, _T_332) node _T_352 = or(_T_351, _T_333) node _T_353 = or(_T_352, _T_334) node _T_354 = or(_T_353, _T_335) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_338) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_340) node _T_360 = or(_T_359, _T_341) node _T_361 = or(_T_360, _T_342) node _T_362 = or(_T_361, _T_343) node _T_363 = or(_T_362, _T_344) node _T_364 = or(_T_363, _T_345) node _T_365 = or(_T_364, _T_346) node _T_366 = or(_T_365, _T_347) node _T_367 = or(_T_366, _T_348) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_1, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_379, UInt<1>(0h1), "") : assert_3 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_386, UInt<1>(0h1), "") : assert_5 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_393, UInt<1>(0h1), "") : assert_7 node _T_397 = not(io.in.a.bits.mask) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_398, UInt<1>(0h1), "") : assert_8 node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_402, UInt<1>(0h1), "") : assert_9 node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_406 : node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<1>(0h0)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_12) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_417 = shr(io.in.a.bits.source, 2) node _T_418 = eq(_T_417, UInt<1>(0h1)) node _T_419 = leq(UInt<1>(0h0), uncommonBits_13) node _T_420 = and(_T_418, _T_419) node _T_421 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_422 = and(_T_420, _T_421) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_423 = shr(io.in.a.bits.source, 2) node _T_424 = eq(_T_423, UInt<2>(0h2)) node _T_425 = leq(UInt<1>(0h0), uncommonBits_14) node _T_426 = and(_T_424, _T_425) node _T_427 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_428 = and(_T_426, _T_427) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<2>(0h3)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_15) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_450 = or(_T_410, _T_416) node _T_451 = or(_T_450, _T_422) node _T_452 = or(_T_451, _T_428) node _T_453 = or(_T_452, _T_434) node _T_454 = or(_T_453, _T_435) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_437) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_439) node _T_459 = or(_T_458, _T_440) node _T_460 = or(_T_459, _T_441) node _T_461 = or(_T_460, _T_442) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_444) node _T_464 = or(_T_463, _T_445) node _T_465 = or(_T_464, _T_446) node _T_466 = or(_T_465, _T_447) node _T_467 = or(_T_466, _T_448) node _T_468 = or(_T_467, _T_449) node _T_469 = and(_T_409, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = and(_T_471, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_479, UInt<1>(0h1), "") : assert_10 node _T_483 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<1>(0h0)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_16) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<1>(0h1)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_17) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<2>(0h2)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_18) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<2>(0h3)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_19) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_510 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[20] connect _WIRE_2[0], _T_483 connect _WIRE_2[1], _T_489 connect _WIRE_2[2], _T_495 connect _WIRE_2[3], _T_501 connect _WIRE_2[4], _T_507 connect _WIRE_2[5], _T_508 connect _WIRE_2[6], _T_509 connect _WIRE_2[7], _T_510 connect _WIRE_2[8], _T_511 connect _WIRE_2[9], _T_512 connect _WIRE_2[10], _T_513 connect _WIRE_2[11], _T_514 connect _WIRE_2[12], _T_515 connect _WIRE_2[13], _T_516 connect _WIRE_2[14], _T_517 connect _WIRE_2[15], _T_518 connect _WIRE_2[16], _T_519 connect _WIRE_2[17], _T_520 connect _WIRE_2[18], _T_521 connect _WIRE_2[19], _T_522 node _T_523 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_526 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_527 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_528 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_529 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[5], _T_523, UInt<1>(0h0)) node _T_535 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_536 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_537 = mux(_WIRE_2[8], _T_524, UInt<1>(0h0)) node _T_538 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_539 = mux(_WIRE_2[10], _T_525, UInt<1>(0h0)) node _T_540 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_541 = mux(_WIRE_2[12], _T_526, UInt<1>(0h0)) node _T_542 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[14], _T_527, UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[17], _T_528, UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = or(_T_529, _T_530) node _T_550 = or(_T_549, _T_531) node _T_551 = or(_T_550, _T_532) node _T_552 = or(_T_551, _T_533) node _T_553 = or(_T_552, _T_534) node _T_554 = or(_T_553, _T_535) node _T_555 = or(_T_554, _T_536) node _T_556 = or(_T_555, _T_537) node _T_557 = or(_T_556, _T_538) node _T_558 = or(_T_557, _T_539) node _T_559 = or(_T_558, _T_540) node _T_560 = or(_T_559, _T_541) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_543) node _T_563 = or(_T_562, _T_544) node _T_564 = or(_T_563, _T_545) node _T_565 = or(_T_564, _T_546) node _T_566 = or(_T_565, _T_547) node _T_567 = or(_T_566, _T_548) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_567 node _T_568 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_569 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_570 = and(_T_568, _T_569) node _T_571 = or(UInt<1>(0h0), _T_570) node _T_572 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = and(_T_571, _T_576) node _T_578 = or(UInt<1>(0h0), _T_577) node _T_579 = and(_WIRE_3, _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_579, UInt<1>(0h1), "") : assert_11 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_586 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_586, UInt<1>(0h1), "") : assert_13 node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(is_aligned, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_593 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_593, UInt<1>(0h1), "") : assert_15 node _T_597 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_597, UInt<1>(0h1), "") : assert_16 node _T_601 = not(io.in.a.bits.mask) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_602, UInt<1>(0h1), "") : assert_17 node _T_606 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_607 = asUInt(reset) node _T_608 = eq(_T_607, UInt<1>(0h0)) when _T_608 : node _T_609 = eq(_T_606, UInt<1>(0h0)) when _T_609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_606, UInt<1>(0h1), "") : assert_18 node _T_610 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_610 : node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_615 = shr(io.in.a.bits.source, 2) node _T_616 = eq(_T_615, UInt<1>(0h0)) node _T_617 = leq(UInt<1>(0h0), uncommonBits_20) node _T_618 = and(_T_616, _T_617) node _T_619 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h1)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_21) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_626 = and(_T_624, _T_625) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_627 = shr(io.in.a.bits.source, 2) node _T_628 = eq(_T_627, UInt<2>(0h2)) node _T_629 = leq(UInt<1>(0h0), uncommonBits_22) node _T_630 = and(_T_628, _T_629) node _T_631 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_632 = and(_T_630, _T_631) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<2>(0h3)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_23) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_654 = or(_T_614, _T_620) node _T_655 = or(_T_654, _T_626) node _T_656 = or(_T_655, _T_632) node _T_657 = or(_T_656, _T_638) node _T_658 = or(_T_657, _T_639) node _T_659 = or(_T_658, _T_640) node _T_660 = or(_T_659, _T_641) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_643) node _T_663 = or(_T_662, _T_644) node _T_664 = or(_T_663, _T_645) node _T_665 = or(_T_664, _T_646) node _T_666 = or(_T_665, _T_647) node _T_667 = or(_T_666, _T_648) node _T_668 = or(_T_667, _T_649) node _T_669 = or(_T_668, _T_650) node _T_670 = or(_T_669, _T_651) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_653) node _T_673 = and(_T_613, _T_672) node _T_674 = or(UInt<1>(0h0), _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_674, UInt<1>(0h1), "") : assert_19 node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_680 = and(_T_678, _T_679) node _T_681 = or(UInt<1>(0h0), _T_680) node _T_682 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = and(_T_681, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_688, UInt<1>(0h1), "") : assert_20 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_698, UInt<1>(0h1), "") : assert_23 node _T_702 = eq(io.in.a.bits.mask, mask) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_702, UInt<1>(0h1), "") : assert_24 node _T_706 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_706, UInt<1>(0h1), "") : assert_25 node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_710 : node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_24) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_721 = shr(io.in.a.bits.source, 2) node _T_722 = eq(_T_721, UInt<1>(0h1)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_25) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_26) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_733 = shr(io.in.a.bits.source, 2) node _T_734 = eq(_T_733, UInt<2>(0h3)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_27) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_740 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_747 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_748 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_752 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_754 = or(_T_714, _T_720) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_732) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_739) node _T_759 = or(_T_758, _T_740) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_743) node _T_763 = or(_T_762, _T_744) node _T_764 = or(_T_763, _T_745) node _T_765 = or(_T_764, _T_746) node _T_766 = or(_T_765, _T_747) node _T_767 = or(_T_766, _T_748) node _T_768 = or(_T_767, _T_749) node _T_769 = or(_T_768, _T_750) node _T_770 = or(_T_769, _T_751) node _T_771 = or(_T_770, _T_752) node _T_772 = or(_T_771, _T_753) node _T_773 = and(_T_713, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_776 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = and(_T_778, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = and(_T_774, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_786, UInt<1>(0h1), "") : assert_26 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_796 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_796, UInt<1>(0h1), "") : assert_29 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_800, UInt<1>(0h1), "") : assert_30 node _T_804 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_28) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_29) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_30) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_31) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_847 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_848 = or(_T_808, _T_814) node _T_849 = or(_T_848, _T_820) node _T_850 = or(_T_849, _T_826) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_833) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_835) node _T_855 = or(_T_854, _T_836) node _T_856 = or(_T_855, _T_837) node _T_857 = or(_T_856, _T_838) node _T_858 = or(_T_857, _T_839) node _T_859 = or(_T_858, _T_840) node _T_860 = or(_T_859, _T_841) node _T_861 = or(_T_860, _T_842) node _T_862 = or(_T_861, _T_843) node _T_863 = or(_T_862, _T_844) node _T_864 = or(_T_863, _T_845) node _T_865 = or(_T_864, _T_846) node _T_866 = or(_T_865, _T_847) node _T_867 = and(_T_807, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_870 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _T_872 = or(UInt<1>(0h0), _T_871) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_880, UInt<1>(0h1), "") : assert_31 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_890, UInt<1>(0h1), "") : assert_34 node _T_894 = not(mask) node _T_895 = and(io.in.a.bits.mask, _T_894) node _T_896 = eq(_T_895, UInt<1>(0h0)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_896, UInt<1>(0h1), "") : assert_35 node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_32) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_33) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_34) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_35) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_933 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_936 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_939 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_942 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_943 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_944 = or(_T_904, _T_910) node _T_945 = or(_T_944, _T_916) node _T_946 = or(_T_945, _T_922) node _T_947 = or(_T_946, _T_928) node _T_948 = or(_T_947, _T_929) node _T_949 = or(_T_948, _T_930) node _T_950 = or(_T_949, _T_931) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_933) node _T_953 = or(_T_952, _T_934) node _T_954 = or(_T_953, _T_935) node _T_955 = or(_T_954, _T_936) node _T_956 = or(_T_955, _T_937) node _T_957 = or(_T_956, _T_938) node _T_958 = or(_T_957, _T_939) node _T_959 = or(_T_958, _T_940) node _T_960 = or(_T_959, _T_941) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_943) node _T_963 = and(_T_903, _T_962) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_966 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = and(_T_965, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = and(_T_964, _T_972) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_973, UInt<1>(0h1), "") : assert_36 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(source_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(is_aligned, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_983 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_983, UInt<1>(0h1), "") : assert_39 node _T_987 = eq(io.in.a.bits.mask, mask) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_987, UInt<1>(0h1), "") : assert_40 node _T_991 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_991 : node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_994 = and(_T_992, _T_993) node _T_995 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<1>(0h0)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_36) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1002 = shr(io.in.a.bits.source, 2) node _T_1003 = eq(_T_1002, UInt<1>(0h1)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1007 = and(_T_1005, _T_1006) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1008 = shr(io.in.a.bits.source, 2) node _T_1009 = eq(_T_1008, UInt<2>(0h2)) node _T_1010 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1013 = and(_T_1011, _T_1012) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1014 = shr(io.in.a.bits.source, 2) node _T_1015 = eq(_T_1014, UInt<2>(0h3)) node _T_1016 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1034 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1035 = or(_T_995, _T_1001) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1013) node _T_1038 = or(_T_1037, _T_1019) node _T_1039 = or(_T_1038, _T_1020) node _T_1040 = or(_T_1039, _T_1021) node _T_1041 = or(_T_1040, _T_1022) node _T_1042 = or(_T_1041, _T_1023) node _T_1043 = or(_T_1042, _T_1024) node _T_1044 = or(_T_1043, _T_1025) node _T_1045 = or(_T_1044, _T_1026) node _T_1046 = or(_T_1045, _T_1027) node _T_1047 = or(_T_1046, _T_1028) node _T_1048 = or(_T_1047, _T_1029) node _T_1049 = or(_T_1048, _T_1030) node _T_1050 = or(_T_1049, _T_1031) node _T_1051 = or(_T_1050, _T_1032) node _T_1052 = or(_T_1051, _T_1033) node _T_1053 = or(_T_1052, _T_1034) node _T_1054 = and(_T_994, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1057 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1058 = cvt(_T_1057) node _T_1059 = and(_T_1058, asSInt(UInt<13>(0h1000))) node _T_1060 = asSInt(_T_1059) node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0))) node _T_1062 = and(_T_1056, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1055, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_41 node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(is_aligned, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1074 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_44 node _T_1078 = eq(io.in.a.bits.mask, mask) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_45 node _T_1082 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1082 : node _T_1083 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1084 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h1)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<2>(0h2)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1125 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1126 = or(_T_1086, _T_1092) node _T_1127 = or(_T_1126, _T_1098) node _T_1128 = or(_T_1127, _T_1104) node _T_1129 = or(_T_1128, _T_1110) node _T_1130 = or(_T_1129, _T_1111) node _T_1131 = or(_T_1130, _T_1112) node _T_1132 = or(_T_1131, _T_1113) node _T_1133 = or(_T_1132, _T_1114) node _T_1134 = or(_T_1133, _T_1115) node _T_1135 = or(_T_1134, _T_1116) node _T_1136 = or(_T_1135, _T_1117) node _T_1137 = or(_T_1136, _T_1118) node _T_1138 = or(_T_1137, _T_1119) node _T_1139 = or(_T_1138, _T_1120) node _T_1140 = or(_T_1139, _T_1121) node _T_1141 = or(_T_1140, _T_1122) node _T_1142 = or(_T_1141, _T_1123) node _T_1143 = or(_T_1142, _T_1124) node _T_1144 = or(_T_1143, _T_1125) node _T_1145 = and(_T_1085, _T_1144) node _T_1146 = or(UInt<1>(0h0), _T_1145) node _T_1147 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = and(_T_1147, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = and(_T_1146, _T_1154) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46 node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(is_aligned, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49 node _T_1169 = eq(io.in.a.bits.mask, mask) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50 node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52 node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_59 = shr(io.in.d.bits.source, 2) node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0)) node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[20] connect _source_ok_WIRE_1[0], _source_ok_T_58 connect _source_ok_WIRE_1[1], _source_ok_T_64 connect _source_ok_WIRE_1[2], _source_ok_T_70 connect _source_ok_WIRE_1[3], _source_ok_T_76 connect _source_ok_WIRE_1[4], _source_ok_T_82 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 connect _source_ok_WIRE_1[10], _source_ok_T_88 connect _source_ok_WIRE_1[11], _source_ok_T_89 connect _source_ok_WIRE_1[12], _source_ok_T_90 connect _source_ok_WIRE_1[13], _source_ok_T_91 connect _source_ok_WIRE_1[14], _source_ok_T_92 connect _source_ok_WIRE_1[15], _source_ok_T_93 connect _source_ok_WIRE_1[16], _source_ok_T_94 connect _source_ok_WIRE_1[17], _source_ok_T_95 connect _source_ok_WIRE_1[18], _source_ok_T_96 connect _source_ok_WIRE_1[19], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18]) node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1181 : node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(source_ok_1, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54 node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55 node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56 node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57 node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1201 : node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(source_ok_1, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(sink_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60 node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61 node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62 node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63 node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1225 = or(UInt<1>(0h0), _T_1224) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64 node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1229 : node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(source_ok_1, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(sink_ok, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67 node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68 node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69 node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1249 = or(_T_1248, io.in.d.bits.corrupt) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70 node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1254 = or(UInt<1>(0h0), _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71 node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1258 : node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(source_ok_1, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73 node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74 node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1271 = or(UInt<1>(0h0), _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75 node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1275 : node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(source_ok_1, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77 node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1284 = or(_T_1283, io.in.d.bits.corrupt) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78 node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1289 = or(UInt<1>(0h0), _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79 node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1293 : node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(source_ok_1, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81 node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82 node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1306 = or(UInt<1>(0h0), _T_1305) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1322 = eq(a_first, UInt<1>(0h0)) node _T_1323 = and(io.in.a.valid, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.a.bits.opcode, opcode) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87 node _T_1328 = eq(io.in.a.bits.param, param) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88 node _T_1332 = eq(io.in.a.bits.size, size) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89 node _T_1336 = eq(io.in.a.bits.source, source) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90 node _T_1340 = eq(io.in.a.bits.address, address) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91 node _T_1344 = and(io.in.a.ready, io.in.a.valid) node _T_1345 = and(_T_1344, a_first) when _T_1345 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1346 = eq(d_first, UInt<1>(0h0)) node _T_1347 = and(io.in.d.valid, _T_1346) when _T_1347 : node _T_1348 = eq(io.in.d.bits.opcode, opcode_1) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92 node _T_1352 = eq(io.in.d.bits.param, param_1) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93 node _T_1356 = eq(io.in.d.bits.size, size_1) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94 node _T_1360 = eq(io.in.d.bits.source, source_1) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95 node _T_1364 = eq(io.in.d.bits.sink, sink) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96 node _T_1368 = eq(io.in.d.bits.denied, denied) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97 node _T_1372 = and(io.in.d.ready, io.in.d.valid) node _T_1373 = and(_T_1372, d_first) when _T_1373 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1374 = and(io.in.a.valid, a_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) when _T_1375 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1376 = and(io.in.a.ready, io.in.a.valid) node _T_1377 = and(_T_1376, a_first_1) node _T_1378 = and(_T_1377, UInt<1>(0h1)) when _T_1378 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1379 = dshr(inflight, io.in.a.bits.source) node _T_1380 = bits(_T_1379, 0, 0) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1385 = and(io.in.d.valid, d_first_1) node _T_1386 = and(_T_1385, UInt<1>(0h1)) node _T_1387 = eq(d_release_ack, UInt<1>(0h0)) node _T_1388 = and(_T_1386, _T_1387) when _T_1388 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1389 = and(io.in.d.ready, io.in.d.valid) node _T_1390 = and(_T_1389, d_first_1) node _T_1391 = and(_T_1390, UInt<1>(0h1)) node _T_1392 = eq(d_release_ack, UInt<1>(0h0)) node _T_1393 = and(_T_1391, _T_1392) when _T_1393 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1394 = and(io.in.d.valid, d_first_1) node _T_1395 = and(_T_1394, UInt<1>(0h1)) node _T_1396 = eq(d_release_ack, UInt<1>(0h0)) node _T_1397 = and(_T_1395, _T_1396) when _T_1397 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1398 = dshr(inflight, io.in.d.bits.source) node _T_1399 = bits(_T_1398, 0, 0) node _T_1400 = or(_T_1399, same_cycle_resp) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100 node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101 else : node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1416 = or(_T_1414, _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102 node _T_1420 = eq(io.in.d.bits.size, a_size_lookup) node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(_T_1420, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103 node _T_1424 = and(io.in.d.valid, d_first_1) node _T_1425 = and(_T_1424, a_first_1) node _T_1426 = and(_T_1425, io.in.a.valid) node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1428 = and(_T_1426, _T_1427) node _T_1429 = eq(d_release_ack, UInt<1>(0h0)) node _T_1430 = and(_T_1428, _T_1429) when _T_1430 : node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1432 = or(_T_1431, io.in.a.ready) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104 node _T_1436 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1437 = orr(a_set_wo_ready) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) node _T_1439 = or(_T_1436, _T_1438) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_175 node _T_1443 = orr(inflight) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) node _T_1445 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1446 = or(_T_1444, _T_1445) node _T_1447 = lt(watchdog, plusarg_reader.out) node _T_1448 = or(_T_1446, _T_1447) node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(_T_1448, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1448, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1452 = and(io.in.a.ready, io.in.a.valid) node _T_1453 = and(io.in.d.ready, io.in.d.valid) node _T_1454 = or(_T_1452, _T_1453) when _T_1454 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1455 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1456 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1457 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1458 = and(_T_1456, _T_1457) node _T_1459 = and(_T_1455, _T_1458) when _T_1459 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1460 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1461 = and(_T_1460, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1462 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1463 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = and(_T_1461, _T_1464) when _T_1465 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1466 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1467 = bits(_T_1466, 0, 0) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1472 = and(io.in.d.valid, d_first_2) node _T_1473 = and(_T_1472, UInt<1>(0h1)) node _T_1474 = and(_T_1473, d_release_ack_1) when _T_1474 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1475 = and(io.in.d.ready, io.in.d.valid) node _T_1476 = and(_T_1475, d_first_2) node _T_1477 = and(_T_1476, UInt<1>(0h1)) node _T_1478 = and(_T_1477, d_release_ack_1) when _T_1478 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1479 = and(io.in.d.valid, d_first_2) node _T_1480 = and(_T_1479, UInt<1>(0h1)) node _T_1481 = and(_T_1480, d_release_ack_1) when _T_1481 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1482 = dshr(inflight_1, io.in.d.bits.source) node _T_1483 = bits(_T_1482, 0, 0) node _T_1484 = or(_T_1483, same_cycle_resp_1) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1488 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_109 else : node _T_1492 = eq(io.in.d.bits.size, c_size_lookup) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_110 node _T_1496 = and(io.in.d.valid, d_first_2) node _T_1497 = and(_T_1496, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1498 = and(_T_1497, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1499 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = and(_T_1500, d_release_ack_1) node _T_1502 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1503 = and(_T_1501, _T_1502) when _T_1503 : node _T_1504 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1505 = or(_T_1504, _WIRE_27.ready) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_111 node _T_1509 = orr(c_set_wo_ready) when _T_1509 : node _T_1510 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_176 node _T_1514 = orr(inflight_1) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) node _T_1516 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1517 = or(_T_1515, _T_1516) node _T_1518 = lt(watchdog_1, plusarg_reader_1.out) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1523 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1524 = and(io.in.d.ready, io.in.d.valid) node _T_1525 = or(_T_1523, _T_1524) when _T_1525 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_86( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_57 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_110 = _source_ok_T_109 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_111 = _source_ok_T_110 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_115 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _T_1452 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1452; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1452; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1525; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1378 = _T_1452 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1496 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1496 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1478 = _T_1525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1478 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1478 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1478 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_54 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)	module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_54 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NullLocalBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, f1_lhist : UInt<1>, f3_lhist : UInt<1>, flip f3_taken_br : UInt<1>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, mispredict : UInt<1>, repair : UInt<1>, pc : UInt<40>, lhist : UInt<1>}} connect io.f1_lhist, UInt<1>(0h0) connect io.f3_lhist, UInt<1>(0h0)	module NullLocalBranchPredictorBank_1( // @[local.scala:38:7] input clock, // @[local.scala:38:7] input reset, // @[local.scala:38:7] input io_f0_valid, // @[local.scala:17:14] input [39:0] io_f0_pc, // @[local.scala:17:14] input io_f3_taken_br, // @[local.scala:17:14] input io_f3_fire, // @[local.scala:17:14] input io_update_valid, // @[local.scala:17:14] input io_update_mispredict, // @[local.scala:17:14] input io_update_repair, // @[local.scala:17:14] input [39:0] io_update_pc, // @[local.scala:17:14] input io_update_lhist // @[local.scala:17:14] ); wire io_f0_valid_0 = io_f0_valid; // @[local.scala:38:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[local.scala:38:7] wire io_f3_taken_br_0 = io_f3_taken_br; // @[local.scala:38:7] wire io_f3_fire_0 = io_f3_fire; // @[local.scala:38:7] wire io_update_valid_0 = io_update_valid; // @[local.scala:38:7] wire io_update_mispredict_0 = io_update_mispredict; // @[local.scala:38:7] wire io_update_repair_0 = io_update_repair; // @[local.scala:38:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[local.scala:38:7] wire io_update_lhist_0 = io_update_lhist; // @[local.scala:38:7] wire io_f1_lhist = 1'h0; // @[local.scala:38:7] wire io_f3_lhist = 1'h0; // @[local.scala:38:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_185 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_185( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_16 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_16( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_84 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_84( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_15 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 9, 6) node req_tag = shr(req.addr, 10) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_16 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock reg refill_ctr : UInt<3>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5) node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7) node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9) node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<3>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 3) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<1>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<3>(0h7)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1	module BoomMSHR_15( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h7; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h7; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h7; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h7; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h7; // @[mshrs.scala:36:7] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h7; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata \| io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_fbus_i2_o1_a32d64s5k6z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_22 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_23 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<5>(0h10)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready connect anonIn.d.bits.source, UInt<1>(0h0) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_16.bits.sink, UInt<6>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_18.bits.sink, UInt<6>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_20.bits.sink, UInt<6>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_22.bits.sink, UInt<6>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<4>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<4>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<5>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<4>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<5>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<4>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T = bits(in[1].d.bits.source, 3, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_40.bits.sink, UInt<6>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_42.bits.sink, UInt<6>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_44.bits.sink, UInt<6>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_46.bits.sink, UInt<6>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<5>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<32>(0h0) connect _WIRE_50.bits.source, UInt<5>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<5>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<32>(0h0) connect _WIRE_54.bits.source, UInt<5>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<5>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<32>(0h0) connect _WIRE_58.bits.source, UInt<5>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<5>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<32>(0h0) connect _WIRE_62.bits.source, UInt<5>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_64.bits.sink, UInt<6>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_66.bits.sink, UInt<6>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_68.bits.sink, UInt<6>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_70.bits.sink, UInt<6>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<5>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<5>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<5>(0h10)) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_3.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 3, 0) node _requestBOI_T = shr(_requestBOI_WIRE_3.bits.source, 4) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<4>(0hf)) node requestBOI_0_1 = and(_requestBOI_T_3, _requestBOI_T_4) node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<5>(0h10)) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 3, 0) node _requestDOI_T = shr(out[0].d.bits.source, 4) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<4>(0hf)) node requestDOI_0_1 = and(_requestDOI_T_3, _requestDOI_T_4) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE.bits.sink, UInt<6>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_1.bits.sink, UInt<6>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 5, 0) node _requestEIO_T = shr(_requestEIO_WIRE_1.bits.sink, 6) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<6>(0h3f)) node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_2.bits.sink, UInt<6>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_3.bits.sink, UInt<6>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 5, 0) node _requestEIO_T_5 = shr(_requestEIO_WIRE_3.bits.sink, 6) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<6>(0h3f)) node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE.bits.sink, UInt<6>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_2.bits.sink, UInt<6>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_2.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE.bits.sink, UInt<6>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}[1] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_2.bits.sink, UInt<6>(0h0) connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}[1] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<5> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<5>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_74.bits.sink, UInt<6>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.mask, UInt<8>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<5>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.mask invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode connect in[0].d, portsDIO_filtered[0] connect portsBIO_filtered[0].ready, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<5>(0h0) connect _WIRE_78.bits.size, UInt<4>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.corrupt invalidate _WIRE_79.bits.data invalidate _WIRE_79.bits.mask invalidate _WIRE_79.bits.address invalidate _WIRE_79.bits.source invalidate _WIRE_79.bits.size invalidate _WIRE_79.bits.param invalidate _WIRE_79.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0) extmodule plusarg_reader_80 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_81 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLXbar_fbus_i2_o1_a32d64s5k6z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire requestDOI_0_0 = auto_anon_out_d_bits_source == 5'h10; // @[Parameters.scala:46:9] wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & requestDOI_0_0; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[4]); // @[Xbar.scala:355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] \| readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_in_1_a_valid} \| _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _out_0_a_valid_T = auto_anon_in_0_a_valid \| auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<4>, vc_free : UInt<4>}} wire _in_flight_WIRE : UInt<1>[4] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) regreset in_flight : UInt<1>[4], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = or(_T_12, _T_19) node _T_63 = or(_T_62, _T_26) node _T_64 = or(_T_63, _T_33) node _T_65 = or(_T_64, _T_40) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_54) node _T_68 = or(_T_67, _T_61) node _T_69 = or(_T_5, _T_68) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_69, UInt<1>(0h1), "") : assert_1 node _T_73 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = or(_T_80, _T_87) node _T_159 = or(_T_158, _T_94) node _T_160 = or(_T_159, _T_101) node _T_161 = or(_T_160, _T_108) node _T_162 = or(_T_161, _T_115) node _T_163 = or(_T_162, _T_122) node _T_164 = or(_T_163, _T_129) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_143) node _T_167 = or(_T_166, _T_150) node _T_168 = or(_T_167, _T_157) node _T_169 = or(_T_73, _T_168) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_169, UInt<1>(0h1), "") : assert_2 node _T_173 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_201 = and(_T_199, _T_200) node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_206 = and(_T_204, _T_205) node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_217 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_224 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_245 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_278 = and(_T_276, _T_277) node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_285 = and(_T_283, _T_284) node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_309 = and(_T_307, _T_308) node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(_T_180, _T_187) node _T_315 = or(_T_314, _T_194) node _T_316 = or(_T_315, _T_201) node _T_317 = or(_T_316, _T_208) node _T_318 = or(_T_317, _T_215) node _T_319 = or(_T_318, _T_222) node _T_320 = or(_T_319, _T_229) node _T_321 = or(_T_320, _T_236) node _T_322 = or(_T_321, _T_243) node _T_323 = or(_T_322, _T_250) node _T_324 = or(_T_323, _T_257) node _T_325 = or(_T_324, _T_264) node _T_326 = or(_T_325, _T_271) node _T_327 = or(_T_326, _T_278) node _T_328 = or(_T_327, _T_285) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_299) node _T_331 = or(_T_330, _T_306) node _T_332 = or(_T_331, _T_313) node _T_333 = or(_T_173, _T_332) node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : node _T_336 = eq(_T_333, UInt<1>(0h0)) when _T_336 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_333, UInt<1>(0h1), "") : assert_3 node _T_337 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_339 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_346 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_353 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_360 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_367 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_372 = and(_T_370, _T_371) node _T_373 = or(_T_344, _T_351) node _T_374 = or(_T_373, _T_358) node _T_375 = or(_T_374, _T_365) node _T_376 = or(_T_375, _T_372) node _T_377 = or(_T_337, _T_376) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_377, UInt<1>(0h1), "") : assert_4	module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h70)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h71)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h72)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h73)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<7>(0h7c)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 2) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<7>(0h7b)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 5) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0hd)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_43 = shr(io.in.a.bits.source, 5) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<4>(0hc)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_49 = shr(io.in.a.bits.source, 5) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<4>(0hb)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_55 = shr(io.in.a.bits.source, 5) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<4>(0ha)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_61 = shr(io.in.a.bits.source, 5) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<4>(0h9)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_67 = shr(io.in.a.bits.source, 5) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_73 = shr(io.in.a.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<7>(0h7a)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_79 = shr(io.in.a.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<7>(0h79)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_85 = shr(io.in.a.bits.source, 5) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<3>(0h7)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_91 = shr(io.in.a.bits.source, 5) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<3>(0h6)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_97 = shr(io.in.a.bits.source, 5) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<3>(0h5)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_103 = shr(io.in.a.bits.source, 5) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_109 = shr(io.in.a.bits.source, 5) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<2>(0h3)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_115 = shr(io.in.a.bits.source, 5) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_121 = shr(io.in.a.bits.source, 5) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h1)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_127 = shr(io.in.a.bits.source, 5) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h0)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_T_133 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _source_ok_T_134 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE : UInt<1>[25] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_48 connect _source_ok_WIRE[9], _source_ok_T_54 connect _source_ok_WIRE[10], _source_ok_T_60 connect _source_ok_WIRE[11], _source_ok_T_66 connect _source_ok_WIRE[12], _source_ok_T_72 connect _source_ok_WIRE[13], _source_ok_T_78 connect _source_ok_WIRE[14], _source_ok_T_84 connect _source_ok_WIRE[15], _source_ok_T_90 connect _source_ok_WIRE[16], _source_ok_T_96 connect _source_ok_WIRE[17], _source_ok_T_102 connect _source_ok_WIRE[18], _source_ok_T_108 connect _source_ok_WIRE[19], _source_ok_T_114 connect _source_ok_WIRE[20], _source_ok_T_120 connect _source_ok_WIRE[21], _source_ok_T_126 connect _source_ok_WIRE[22], _source_ok_T_132 connect _source_ok_WIRE[23], _source_ok_T_133 connect _source_ok_WIRE[24], _source_ok_T_134 node _source_ok_T_135 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE[2]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE[3]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE[4]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE[5]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE[6]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE[7]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE[8]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE[9]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE[10]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE[11]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE[12]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE[13]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE[14]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE[15]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE[16]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE[17]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE[18]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE[19]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE[20]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE[21]) node _source_ok_T_156 = or(_source_ok_T_155, _source_ok_WIRE[22]) node _source_ok_T_157 = or(_source_ok_T_156, _source_ok_WIRE[23]) node source_ok = or(_source_ok_T_157, _source_ok_WIRE[24]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h70)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h71)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h72)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h73)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<7>(0h7c)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_77 = shr(io.in.a.bits.source, 2) node _T_78 = eq(_T_77, UInt<7>(0h7b)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_90 = shr(io.in.a.bits.source, 5) node _T_91 = eq(_T_90, UInt<4>(0hd)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_103 = shr(io.in.a.bits.source, 5) node _T_104 = eq(_T_103, UInt<4>(0hc)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_7) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_116 = shr(io.in.a.bits.source, 5) node _T_117 = eq(_T_116, UInt<4>(0hb)) node _T_118 = leq(UInt<1>(0h0), uncommonBits_8) node _T_119 = and(_T_117, _T_118) node _T_120 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_124 = cvt(_T_123) node _T_125 = and(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = asSInt(_T_125) node _T_127 = eq(_T_126, asSInt(UInt<1>(0h0))) node _T_128 = or(_T_122, _T_127) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_129 = shr(io.in.a.bits.source, 5) node _T_130 = eq(_T_129, UInt<4>(0ha)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_9) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_135, _T_140) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_142 = shr(io.in.a.bits.source, 5) node _T_143 = eq(_T_142, UInt<4>(0h9)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_10) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = or(_T_148, _T_153) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_155 = shr(io.in.a.bits.source, 5) node _T_156 = eq(_T_155, UInt<4>(0h8)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_11) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_168 = shr(io.in.a.bits.source, 2) node _T_169 = eq(_T_168, UInt<7>(0h7a)) node _T_170 = leq(UInt<1>(0h0), uncommonBits_12) node _T_171 = and(_T_169, _T_170) node _T_172 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_174, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<7>(0h79)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = or(_T_187, _T_192) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_194 = shr(io.in.a.bits.source, 5) node _T_195 = eq(_T_194, UInt<3>(0h7)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_14) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_207 = shr(io.in.a.bits.source, 5) node _T_208 = eq(_T_207, UInt<3>(0h6)) node _T_209 = leq(UInt<1>(0h0), uncommonBits_15) node _T_210 = and(_T_208, _T_209) node _T_211 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(_T_212, UInt<1>(0h0)) node _T_214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = or(_T_213, _T_218) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_220 = shr(io.in.a.bits.source, 5) node _T_221 = eq(_T_220, UInt<3>(0h5)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_16) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = or(_T_226, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h4)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = or(_T_239, _T_244) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_246 = shr(io.in.a.bits.source, 5) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_18) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_254 = cvt(_T_253) node _T_255 = and(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = asSInt(_T_255) node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0))) node _T_258 = or(_T_252, _T_257) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_259 = shr(io.in.a.bits.source, 5) node _T_260 = eq(_T_259, UInt<2>(0h2)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_19) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_272 = shr(io.in.a.bits.source, 5) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_20) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_278, _T_283) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_285 = shr(io.in.a.bits.source, 5) node _T_286 = eq(_T_285, UInt<1>(0h0)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_21) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(_T_290, UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_291, _T_296) node _T_298 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = or(_T_299, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_307 = eq(_T_306, UInt<1>(0h0)) node _T_308 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = and(_T_11, _T_24) node _T_315 = and(_T_314, _T_37) node _T_316 = and(_T_315, _T_50) node _T_317 = and(_T_316, _T_63) node _T_318 = and(_T_317, _T_76) node _T_319 = and(_T_318, _T_89) node _T_320 = and(_T_319, _T_102) node _T_321 = and(_T_320, _T_115) node _T_322 = and(_T_321, _T_128) node _T_323 = and(_T_322, _T_141) node _T_324 = and(_T_323, _T_154) node _T_325 = and(_T_324, _T_167) node _T_326 = and(_T_325, _T_180) node _T_327 = and(_T_326, _T_193) node _T_328 = and(_T_327, _T_206) node _T_329 = and(_T_328, _T_219) node _T_330 = and(_T_329, _T_232) node _T_331 = and(_T_330, _T_245) node _T_332 = and(_T_331, _T_258) node _T_333 = and(_T_332, _T_271) node _T_334 = and(_T_333, _T_284) node _T_335 = and(_T_334, _T_297) node _T_336 = and(_T_335, _T_305) node _T_337 = and(_T_336, _T_313) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_337, UInt<1>(0h1), "") : assert_1 node _T_341 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_341 : node _T_342 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_343 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_346 = shr(io.in.a.bits.source, 2) node _T_347 = eq(_T_346, UInt<7>(0h70)) node _T_348 = leq(UInt<1>(0h0), uncommonBits_22) node _T_349 = and(_T_347, _T_348) node _T_350 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_351 = and(_T_349, _T_350) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<7>(0h71)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_23) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<7>(0h72)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_24) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<7>(0h73)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_25) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<7>(0h7c)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_26) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_376 = shr(io.in.a.bits.source, 2) node _T_377 = eq(_T_376, UInt<7>(0h7b)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_27) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_382 = shr(io.in.a.bits.source, 5) node _T_383 = eq(_T_382, UInt<4>(0hd)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_28) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_388 = shr(io.in.a.bits.source, 5) node _T_389 = eq(_T_388, UInt<4>(0hc)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_29) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_394 = shr(io.in.a.bits.source, 5) node _T_395 = eq(_T_394, UInt<4>(0hb)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_30) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<4>(0ha)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_31) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<4>(0h9)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_32) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<4>(0h8)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_33) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<7>(0h7a)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_34) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<7>(0h79)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_35) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h7)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_36) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h6)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_37) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h5)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_38) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h4)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_39) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_454 = shr(io.in.a.bits.source, 5) node _T_455 = eq(_T_454, UInt<2>(0h3)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_40) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_459 = and(_T_457, _T_458) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_460 = shr(io.in.a.bits.source, 5) node _T_461 = eq(_T_460, UInt<2>(0h2)) node _T_462 = leq(UInt<1>(0h0), uncommonBits_41) node _T_463 = and(_T_461, _T_462) node _T_464 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_465 = and(_T_463, _T_464) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_466 = shr(io.in.a.bits.source, 5) node _T_467 = eq(_T_466, UInt<1>(0h1)) node _T_468 = leq(UInt<1>(0h0), uncommonBits_42) node _T_469 = and(_T_467, _T_468) node _T_470 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_471 = and(_T_469, _T_470) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_472 = shr(io.in.a.bits.source, 5) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_43) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_479 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_480 = or(_T_345, _T_351) node _T_481 = or(_T_480, _T_357) node _T_482 = or(_T_481, _T_363) node _T_483 = or(_T_482, _T_369) node _T_484 = or(_T_483, _T_375) node _T_485 = or(_T_484, _T_381) node _T_486 = or(_T_485, _T_387) node _T_487 = or(_T_486, _T_393) node _T_488 = or(_T_487, _T_399) node _T_489 = or(_T_488, _T_405) node _T_490 = or(_T_489, _T_411) node _T_491 = or(_T_490, _T_417) node _T_492 = or(_T_491, _T_423) node _T_493 = or(_T_492, _T_429) node _T_494 = or(_T_493, _T_435) node _T_495 = or(_T_494, _T_441) node _T_496 = or(_T_495, _T_447) node _T_497 = or(_T_496, _T_453) node _T_498 = or(_T_497, _T_459) node _T_499 = or(_T_498, _T_465) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_477) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_479) node _T_504 = and(_T_344, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_507 = or(UInt<1>(0h0), _T_506) node _T_508 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<17>(0h10000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<29>(0h10000000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = or(_T_512, _T_517) node _T_519 = and(_T_507, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_505, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<7>(0h70)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_44) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<7>(0h71)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_45) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<7>(0h72)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_46) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<7>(0h73)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_47) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_550 = shr(io.in.a.bits.source, 2) node _T_551 = eq(_T_550, UInt<7>(0h7c)) node _T_552 = leq(UInt<1>(0h0), uncommonBits_48) node _T_553 = and(_T_551, _T_552) node _T_554 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_555 = and(_T_553, _T_554) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_556 = shr(io.in.a.bits.source, 2) node _T_557 = eq(_T_556, UInt<7>(0h7b)) node _T_558 = leq(UInt<1>(0h0), uncommonBits_49) node _T_559 = and(_T_557, _T_558) node _T_560 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_561 = and(_T_559, _T_560) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_562 = shr(io.in.a.bits.source, 5) node _T_563 = eq(_T_562, UInt<4>(0hd)) node _T_564 = leq(UInt<1>(0h0), uncommonBits_50) node _T_565 = and(_T_563, _T_564) node _T_566 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_567 = and(_T_565, _T_566) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_568 = shr(io.in.a.bits.source, 5) node _T_569 = eq(_T_568, UInt<4>(0hc)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_51) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_573 = and(_T_571, _T_572) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_574 = shr(io.in.a.bits.source, 5) node _T_575 = eq(_T_574, UInt<4>(0hb)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_52) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_580 = shr(io.in.a.bits.source, 5) node _T_581 = eq(_T_580, UInt<4>(0ha)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_53) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_586 = shr(io.in.a.bits.source, 5) node _T_587 = eq(_T_586, UInt<4>(0h9)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_54) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_592 = shr(io.in.a.bits.source, 5) node _T_593 = eq(_T_592, UInt<4>(0h8)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_55) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h7a)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_56) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<7>(0h79)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_57) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_610 = shr(io.in.a.bits.source, 5) node _T_611 = eq(_T_610, UInt<3>(0h7)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_58) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_615 = and(_T_613, _T_614) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_616 = shr(io.in.a.bits.source, 5) node _T_617 = eq(_T_616, UInt<3>(0h6)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_59) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_622 = shr(io.in.a.bits.source, 5) node _T_623 = eq(_T_622, UInt<3>(0h5)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_60) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_628 = shr(io.in.a.bits.source, 5) node _T_629 = eq(_T_628, UInt<3>(0h4)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_61) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_633 = and(_T_631, _T_632) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_634 = shr(io.in.a.bits.source, 5) node _T_635 = eq(_T_634, UInt<2>(0h3)) node _T_636 = leq(UInt<1>(0h0), uncommonBits_62) node _T_637 = and(_T_635, _T_636) node _T_638 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_639 = and(_T_637, _T_638) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_640 = shr(io.in.a.bits.source, 5) node _T_641 = eq(_T_640, UInt<2>(0h2)) node _T_642 = leq(UInt<1>(0h0), uncommonBits_63) node _T_643 = and(_T_641, _T_642) node _T_644 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_645 = and(_T_643, _T_644) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_646 = shr(io.in.a.bits.source, 5) node _T_647 = eq(_T_646, UInt<1>(0h1)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_64) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_652 = shr(io.in.a.bits.source, 5) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_65) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_657 = and(_T_655, _T_656) node _T_658 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_659 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _WIRE : UInt<1>[25] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_555 connect _WIRE[6], _T_561 connect _WIRE[7], _T_567 connect _WIRE[8], _T_573 connect _WIRE[9], _T_579 connect _WIRE[10], _T_585 connect _WIRE[11], _T_591 connect _WIRE[12], _T_597 connect _WIRE[13], _T_603 connect _WIRE[14], _T_609 connect _WIRE[15], _T_615 connect _WIRE[16], _T_621 connect _WIRE[17], _T_627 connect _WIRE[18], _T_633 connect _WIRE[19], _T_639 connect _WIRE[20], _T_645 connect _WIRE[21], _T_651 connect _WIRE[22], _T_657 connect _WIRE[23], _T_658 connect _WIRE[24], _T_659 node _T_660 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_661 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_662 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_663 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_664 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_666 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_668 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_673 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_674 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_676 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE[23], _T_660, UInt<1>(0h0)) node _T_685 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = or(_T_661, _T_662) node _T_687 = or(_T_686, _T_663) node _T_688 = or(_T_687, _T_664) node _T_689 = or(_T_688, _T_665) node _T_690 = or(_T_689, _T_666) node _T_691 = or(_T_690, _T_667) node _T_692 = or(_T_691, _T_668) node _T_693 = or(_T_692, _T_669) node _T_694 = or(_T_693, _T_670) node _T_695 = or(_T_694, _T_671) node _T_696 = or(_T_695, _T_672) node _T_697 = or(_T_696, _T_673) node _T_698 = or(_T_697, _T_674) node _T_699 = or(_T_698, _T_675) node _T_700 = or(_T_699, _T_676) node _T_701 = or(_T_700, _T_677) node _T_702 = or(_T_701, _T_678) node _T_703 = or(_T_702, _T_679) node _T_704 = or(_T_703, _T_680) node _T_705 = or(_T_704, _T_681) node _T_706 = or(_T_705, _T_682) node _T_707 = or(_T_706, _T_683) node _T_708 = or(_T_707, _T_684) node _T_709 = or(_T_708, _T_685) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_709 node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_715 = cvt(_T_714) node _T_716 = and(_T_715, asSInt(UInt<17>(0h10000))) node _T_717 = asSInt(_T_716) node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) node _T_719 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<29>(0h10000000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = or(_T_718, _T_723) node _T_725 = and(_T_713, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = and(_WIRE_1, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_727, UInt<1>(0h1), "") : assert_3 node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(source_ok, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_734 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_T_734, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_734, UInt<1>(0h1), "") : assert_5 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_741 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_741, UInt<1>(0h1), "") : assert_7 node _T_745 = not(io.in.a.bits.mask) node _T_746 = eq(_T_745, UInt<1>(0h0)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_746, UInt<1>(0h1), "") : assert_8 node _T_750 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_750, UInt<1>(0h1), "") : assert_9 node _T_754 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_754 : node _T_755 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_756 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_759 = shr(io.in.a.bits.source, 2) node _T_760 = eq(_T_759, UInt<7>(0h70)) node _T_761 = leq(UInt<1>(0h0), uncommonBits_66) node _T_762 = and(_T_760, _T_761) node _T_763 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_764 = and(_T_762, _T_763) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_765 = shr(io.in.a.bits.source, 2) node _T_766 = eq(_T_765, UInt<7>(0h71)) node _T_767 = leq(UInt<1>(0h0), uncommonBits_67) node _T_768 = and(_T_766, _T_767) node _T_769 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_770 = and(_T_768, _T_769) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_771 = shr(io.in.a.bits.source, 2) node _T_772 = eq(_T_771, UInt<7>(0h72)) node _T_773 = leq(UInt<1>(0h0), uncommonBits_68) node _T_774 = and(_T_772, _T_773) node _T_775 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_776 = and(_T_774, _T_775) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_777 = shr(io.in.a.bits.source, 2) node _T_778 = eq(_T_777, UInt<7>(0h73)) node _T_779 = leq(UInt<1>(0h0), uncommonBits_69) node _T_780 = and(_T_778, _T_779) node _T_781 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<7>(0h7c)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_70) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_789 = shr(io.in.a.bits.source, 2) node _T_790 = eq(_T_789, UInt<7>(0h7b)) node _T_791 = leq(UInt<1>(0h0), uncommonBits_71) node _T_792 = and(_T_790, _T_791) node _T_793 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_794 = and(_T_792, _T_793) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 4, 0) node _T_795 = shr(io.in.a.bits.source, 5) node _T_796 = eq(_T_795, UInt<4>(0hd)) node _T_797 = leq(UInt<1>(0h0), uncommonBits_72) node _T_798 = and(_T_796, _T_797) node _T_799 = leq(uncommonBits_72, UInt<5>(0h1f)) node _T_800 = and(_T_798, _T_799) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 4, 0) node _T_801 = shr(io.in.a.bits.source, 5) node _T_802 = eq(_T_801, UInt<4>(0hc)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_73) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_73, UInt<5>(0h1f)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 4, 0) node _T_807 = shr(io.in.a.bits.source, 5) node _T_808 = eq(_T_807, UInt<4>(0hb)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_74) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_74, UInt<5>(0h1f)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 4, 0) node _T_813 = shr(io.in.a.bits.source, 5) node _T_814 = eq(_T_813, UInt<4>(0ha)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_75) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_75, UInt<5>(0h1f)) node _T_818 = and(_T_816, _T_817) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_819 = shr(io.in.a.bits.source, 5) node _T_820 = eq(_T_819, UInt<4>(0h9)) node _T_821 = leq(UInt<1>(0h0), uncommonBits_76) node _T_822 = and(_T_820, _T_821) node _T_823 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_824 = and(_T_822, _T_823) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_825 = shr(io.in.a.bits.source, 5) node _T_826 = eq(_T_825, UInt<4>(0h8)) node _T_827 = leq(UInt<1>(0h0), uncommonBits_77) node _T_828 = and(_T_826, _T_827) node _T_829 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_830 = and(_T_828, _T_829) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_831 = shr(io.in.a.bits.source, 2) node _T_832 = eq(_T_831, UInt<7>(0h7a)) node _T_833 = leq(UInt<1>(0h0), uncommonBits_78) node _T_834 = and(_T_832, _T_833) node _T_835 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_836 = and(_T_834, _T_835) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0) node _T_837 = shr(io.in.a.bits.source, 2) node _T_838 = eq(_T_837, UInt<7>(0h79)) node _T_839 = leq(UInt<1>(0h0), uncommonBits_79) node _T_840 = and(_T_838, _T_839) node _T_841 = leq(uncommonBits_79, UInt<2>(0h3)) node _T_842 = and(_T_840, _T_841) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_843 = shr(io.in.a.bits.source, 5) node _T_844 = eq(_T_843, UInt<3>(0h7)) node _T_845 = leq(UInt<1>(0h0), uncommonBits_80) node _T_846 = and(_T_844, _T_845) node _T_847 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_849 = shr(io.in.a.bits.source, 5) node _T_850 = eq(_T_849, UInt<3>(0h6)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_81) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_855 = shr(io.in.a.bits.source, 5) node _T_856 = eq(_T_855, UInt<3>(0h5)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_82) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_861 = shr(io.in.a.bits.source, 5) node _T_862 = eq(_T_861, UInt<3>(0h4)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_83) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_866 = and(_T_864, _T_865) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 4, 0) node _T_867 = shr(io.in.a.bits.source, 5) node _T_868 = eq(_T_867, UInt<2>(0h3)) node _T_869 = leq(UInt<1>(0h0), uncommonBits_84) node _T_870 = and(_T_868, _T_869) node _T_871 = leq(uncommonBits_84, UInt<5>(0h1f)) node _T_872 = and(_T_870, _T_871) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 4, 0) node _T_873 = shr(io.in.a.bits.source, 5) node _T_874 = eq(_T_873, UInt<2>(0h2)) node _T_875 = leq(UInt<1>(0h0), uncommonBits_85) node _T_876 = and(_T_874, _T_875) node _T_877 = leq(uncommonBits_85, UInt<5>(0h1f)) node _T_878 = and(_T_876, _T_877) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 4, 0) node _T_879 = shr(io.in.a.bits.source, 5) node _T_880 = eq(_T_879, UInt<1>(0h1)) node _T_881 = leq(UInt<1>(0h0), uncommonBits_86) node _T_882 = and(_T_880, _T_881) node _T_883 = leq(uncommonBits_86, UInt<5>(0h1f)) node _T_884 = and(_T_882, _T_883) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 4, 0) node _T_885 = shr(io.in.a.bits.source, 5) node _T_886 = eq(_T_885, UInt<1>(0h0)) node _T_887 = leq(UInt<1>(0h0), uncommonBits_87) node _T_888 = and(_T_886, _T_887) node _T_889 = leq(uncommonBits_87, UInt<5>(0h1f)) node _T_890 = and(_T_888, _T_889) node _T_891 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_892 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_893 = or(_T_758, _T_764) node _T_894 = or(_T_893, _T_770) node _T_895 = or(_T_894, _T_776) node _T_896 = or(_T_895, _T_782) node _T_897 = or(_T_896, _T_788) node _T_898 = or(_T_897, _T_794) node _T_899 = or(_T_898, _T_800) node _T_900 = or(_T_899, _T_806) node _T_901 = or(_T_900, _T_812) node _T_902 = or(_T_901, _T_818) node _T_903 = or(_T_902, _T_824) node _T_904 = or(_T_903, _T_830) node _T_905 = or(_T_904, _T_836) node _T_906 = or(_T_905, _T_842) node _T_907 = or(_T_906, _T_848) node _T_908 = or(_T_907, _T_854) node _T_909 = or(_T_908, _T_860) node _T_910 = or(_T_909, _T_866) node _T_911 = or(_T_910, _T_872) node _T_912 = or(_T_911, _T_878) node _T_913 = or(_T_912, _T_884) node _T_914 = or(_T_913, _T_890) node _T_915 = or(_T_914, _T_891) node _T_916 = or(_T_915, _T_892) node _T_917 = and(_T_757, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<29>(0h10000000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = or(_T_925, _T_930) node _T_932 = and(_T_920, _T_931) node _T_933 = or(UInt<1>(0h0), _T_932) node _T_934 = and(_T_918, _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_934, UInt<1>(0h1), "") : assert_10 node _T_938 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_939 = shr(io.in.a.bits.source, 2) node _T_940 = eq(_T_939, UInt<7>(0h70)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_88) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 1, 0) node _T_945 = shr(io.in.a.bits.source, 2) node _T_946 = eq(_T_945, UInt<7>(0h71)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_89) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_89, UInt<2>(0h3)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<7>(0h72)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_90) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_90, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<7>(0h73)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_91) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_91, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<7>(0h7c)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_92) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_92, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<7>(0h7b)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_93) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_93, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_975 = shr(io.in.a.bits.source, 5) node _T_976 = eq(_T_975, UInt<4>(0hd)) node _T_977 = leq(UInt<1>(0h0), uncommonBits_94) node _T_978 = and(_T_976, _T_977) node _T_979 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_980 = and(_T_978, _T_979) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_981 = shr(io.in.a.bits.source, 5) node _T_982 = eq(_T_981, UInt<4>(0hc)) node _T_983 = leq(UInt<1>(0h0), uncommonBits_95) node _T_984 = and(_T_982, _T_983) node _T_985 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_986 = and(_T_984, _T_985) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 4, 0) node _T_987 = shr(io.in.a.bits.source, 5) node _T_988 = eq(_T_987, UInt<4>(0hb)) node _T_989 = leq(UInt<1>(0h0), uncommonBits_96) node _T_990 = and(_T_988, _T_989) node _T_991 = leq(uncommonBits_96, UInt<5>(0h1f)) node _T_992 = and(_T_990, _T_991) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 4, 0) node _T_993 = shr(io.in.a.bits.source, 5) node _T_994 = eq(_T_993, UInt<4>(0ha)) node _T_995 = leq(UInt<1>(0h0), uncommonBits_97) node _T_996 = and(_T_994, _T_995) node _T_997 = leq(uncommonBits_97, UInt<5>(0h1f)) node _T_998 = and(_T_996, _T_997) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 4, 0) node _T_999 = shr(io.in.a.bits.source, 5) node _T_1000 = eq(_T_999, UInt<4>(0h9)) node _T_1001 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = leq(uncommonBits_98, UInt<5>(0h1f)) node _T_1004 = and(_T_1002, _T_1003) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 4, 0) node _T_1005 = shr(io.in.a.bits.source, 5) node _T_1006 = eq(_T_1005, UInt<4>(0h8)) node _T_1007 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = leq(uncommonBits_99, UInt<5>(0h1f)) node _T_1010 = and(_T_1008, _T_1009) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0) node _T_1011 = shr(io.in.a.bits.source, 2) node _T_1012 = eq(_T_1011, UInt<7>(0h7a)) node _T_1013 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = leq(uncommonBits_100, UInt<2>(0h3)) node _T_1016 = and(_T_1014, _T_1015) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0) node _T_1017 = shr(io.in.a.bits.source, 2) node _T_1018 = eq(_T_1017, UInt<7>(0h79)) node _T_1019 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1020 = and(_T_1018, _T_1019) node _T_1021 = leq(uncommonBits_101, UInt<2>(0h3)) node _T_1022 = and(_T_1020, _T_1021) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1023 = shr(io.in.a.bits.source, 5) node _T_1024 = eq(_T_1023, UInt<3>(0h7)) node _T_1025 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1028 = and(_T_1026, _T_1027) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1029 = shr(io.in.a.bits.source, 5) node _T_1030 = eq(_T_1029, UInt<3>(0h6)) node _T_1031 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1034 = and(_T_1032, _T_1033) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1035 = shr(io.in.a.bits.source, 5) node _T_1036 = eq(_T_1035, UInt<3>(0h5)) node _T_1037 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1040 = and(_T_1038, _T_1039) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1041 = shr(io.in.a.bits.source, 5) node _T_1042 = eq(_T_1041, UInt<3>(0h4)) node _T_1043 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1046 = and(_T_1044, _T_1045) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1047 = shr(io.in.a.bits.source, 5) node _T_1048 = eq(_T_1047, UInt<2>(0h3)) node _T_1049 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1050 = and(_T_1048, _T_1049) node _T_1051 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1052 = and(_T_1050, _T_1051) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1053 = shr(io.in.a.bits.source, 5) node _T_1054 = eq(_T_1053, UInt<2>(0h2)) node _T_1055 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1058 = and(_T_1056, _T_1057) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 4, 0) node _T_1059 = shr(io.in.a.bits.source, 5) node _T_1060 = eq(_T_1059, UInt<1>(0h1)) node _T_1061 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = leq(uncommonBits_108, UInt<5>(0h1f)) node _T_1064 = and(_T_1062, _T_1063) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 4, 0) node _T_1065 = shr(io.in.a.bits.source, 5) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) node _T_1067 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = leq(uncommonBits_109, UInt<5>(0h1f)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1072 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _WIRE_2 : UInt<1>[25] connect _WIRE_2[0], _T_938 connect _WIRE_2[1], _T_944 connect _WIRE_2[2], _T_950 connect _WIRE_2[3], _T_956 connect _WIRE_2[4], _T_962 connect _WIRE_2[5], _T_968 connect _WIRE_2[6], _T_974 connect _WIRE_2[7], _T_980 connect _WIRE_2[8], _T_986 connect _WIRE_2[9], _T_992 connect _WIRE_2[10], _T_998 connect _WIRE_2[11], _T_1004 connect _WIRE_2[12], _T_1010 connect _WIRE_2[13], _T_1016 connect _WIRE_2[14], _T_1022 connect _WIRE_2[15], _T_1028 connect _WIRE_2[16], _T_1034 connect _WIRE_2[17], _T_1040 connect _WIRE_2[18], _T_1046 connect _WIRE_2[19], _T_1052 connect _WIRE_2[20], _T_1058 connect _WIRE_2[21], _T_1064 connect _WIRE_2[22], _T_1070 connect _WIRE_2[23], _T_1071 connect _WIRE_2[24], _T_1072 node _T_1073 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1074 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1075 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1076 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1077 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1078 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1079 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1080 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1081 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1082 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1083 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1084 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1085 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1086 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1087 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1088 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1089 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1090 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1091 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_1092 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1094 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1096 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1097 = mux(_WIRE_2[23], _T_1073, UInt<1>(0h0)) node _T_1098 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1099 = or(_T_1074, _T_1075) node _T_1100 = or(_T_1099, _T_1076) node _T_1101 = or(_T_1100, _T_1077) node _T_1102 = or(_T_1101, _T_1078) node _T_1103 = or(_T_1102, _T_1079) node _T_1104 = or(_T_1103, _T_1080) node _T_1105 = or(_T_1104, _T_1081) node _T_1106 = or(_T_1105, _T_1082) node _T_1107 = or(_T_1106, _T_1083) node _T_1108 = or(_T_1107, _T_1084) node _T_1109 = or(_T_1108, _T_1085) node _T_1110 = or(_T_1109, _T_1086) node _T_1111 = or(_T_1110, _T_1087) node _T_1112 = or(_T_1111, _T_1088) node _T_1113 = or(_T_1112, _T_1089) node _T_1114 = or(_T_1113, _T_1090) node _T_1115 = or(_T_1114, _T_1091) node _T_1116 = or(_T_1115, _T_1092) node _T_1117 = or(_T_1116, _T_1093) node _T_1118 = or(_T_1117, _T_1094) node _T_1119 = or(_T_1118, _T_1095) node _T_1120 = or(_T_1119, _T_1096) node _T_1121 = or(_T_1120, _T_1097) node _T_1122 = or(_T_1121, _T_1098) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1122 node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<17>(0h10000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<29>(0h10000000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = or(_T_1131, _T_1136) node _T_1138 = and(_T_1126, _T_1137) node _T_1139 = or(UInt<1>(0h0), _T_1138) node _T_1140 = and(_WIRE_3, _T_1139) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_11 node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1147 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_13 node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(is_aligned, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1154 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_15 node _T_1158 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_16 node _T_1162 = not(io.in.a.bits.mask) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_17 node _T_1167 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_18 node _T_1171 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1171 : node _T_1172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1173 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1176 = shr(io.in.a.bits.source, 2) node _T_1177 = eq(_T_1176, UInt<7>(0h70)) node _T_1178 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1181 = and(_T_1179, _T_1180) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1182 = shr(io.in.a.bits.source, 2) node _T_1183 = eq(_T_1182, UInt<7>(0h71)) node _T_1184 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1185 = and(_T_1183, _T_1184) node _T_1186 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1187 = and(_T_1185, _T_1186) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<7>(0h72)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_112, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<7>(0h73)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_113, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<7>(0h7c)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_114, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<7>(0h7b)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_115, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1212 = shr(io.in.a.bits.source, 5) node _T_1213 = eq(_T_1212, UInt<4>(0hd)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1217 = and(_T_1215, _T_1216) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1218 = shr(io.in.a.bits.source, 5) node _T_1219 = eq(_T_1218, UInt<4>(0hc)) node _T_1220 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1221 = and(_T_1219, _T_1220) node _T_1222 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1223 = and(_T_1221, _T_1222) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1224 = shr(io.in.a.bits.source, 5) node _T_1225 = eq(_T_1224, UInt<4>(0hb)) node _T_1226 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1229 = and(_T_1227, _T_1228) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1230 = shr(io.in.a.bits.source, 5) node _T_1231 = eq(_T_1230, UInt<4>(0ha)) node _T_1232 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1235 = and(_T_1233, _T_1234) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 4, 0) node _T_1236 = shr(io.in.a.bits.source, 5) node _T_1237 = eq(_T_1236, UInt<4>(0h9)) node _T_1238 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = leq(uncommonBits_120, UInt<5>(0h1f)) node _T_1241 = and(_T_1239, _T_1240) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 4, 0) node _T_1242 = shr(io.in.a.bits.source, 5) node _T_1243 = eq(_T_1242, UInt<4>(0h8)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_121, UInt<5>(0h1f)) node _T_1247 = and(_T_1245, _T_1246) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1248 = shr(io.in.a.bits.source, 2) node _T_1249 = eq(_T_1248, UInt<7>(0h7a)) node _T_1250 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1253 = and(_T_1251, _T_1252) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1254 = shr(io.in.a.bits.source, 2) node _T_1255 = eq(_T_1254, UInt<7>(0h79)) node _T_1256 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1259 = and(_T_1257, _T_1258) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1260 = shr(io.in.a.bits.source, 5) node _T_1261 = eq(_T_1260, UInt<3>(0h7)) node _T_1262 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1265 = and(_T_1263, _T_1264) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1266 = shr(io.in.a.bits.source, 5) node _T_1267 = eq(_T_1266, UInt<3>(0h6)) node _T_1268 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1271 = and(_T_1269, _T_1270) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1272 = shr(io.in.a.bits.source, 5) node _T_1273 = eq(_T_1272, UInt<3>(0h5)) node _T_1274 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1277 = and(_T_1275, _T_1276) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1278 = shr(io.in.a.bits.source, 5) node _T_1279 = eq(_T_1278, UInt<3>(0h4)) node _T_1280 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1281 = and(_T_1279, _T_1280) node _T_1282 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1283 = and(_T_1281, _T_1282) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1284 = shr(io.in.a.bits.source, 5) node _T_1285 = eq(_T_1284, UInt<2>(0h3)) node _T_1286 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1289 = and(_T_1287, _T_1288) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1290 = shr(io.in.a.bits.source, 5) node _T_1291 = eq(_T_1290, UInt<2>(0h2)) node _T_1292 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1293 = and(_T_1291, _T_1292) node _T_1294 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1295 = and(_T_1293, _T_1294) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1296 = shr(io.in.a.bits.source, 5) node _T_1297 = eq(_T_1296, UInt<1>(0h1)) node _T_1298 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1301 = and(_T_1299, _T_1300) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1302 = shr(io.in.a.bits.source, 5) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1310 = or(_T_1175, _T_1181) node _T_1311 = or(_T_1310, _T_1187) node _T_1312 = or(_T_1311, _T_1193) node _T_1313 = or(_T_1312, _T_1199) node _T_1314 = or(_T_1313, _T_1205) node _T_1315 = or(_T_1314, _T_1211) node _T_1316 = or(_T_1315, _T_1217) node _T_1317 = or(_T_1316, _T_1223) node _T_1318 = or(_T_1317, _T_1229) node _T_1319 = or(_T_1318, _T_1235) node _T_1320 = or(_T_1319, _T_1241) node _T_1321 = or(_T_1320, _T_1247) node _T_1322 = or(_T_1321, _T_1253) node _T_1323 = or(_T_1322, _T_1259) node _T_1324 = or(_T_1323, _T_1265) node _T_1325 = or(_T_1324, _T_1271) node _T_1326 = or(_T_1325, _T_1277) node _T_1327 = or(_T_1326, _T_1283) node _T_1328 = or(_T_1327, _T_1289) node _T_1329 = or(_T_1328, _T_1295) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1307) node _T_1332 = or(_T_1331, _T_1308) node _T_1333 = or(_T_1332, _T_1309) node _T_1334 = and(_T_1174, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_19 node _T_1339 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1340 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = or(UInt<1>(0h0), _T_1341) node _T_1343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<17>(0h10000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<29>(0h10000000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = or(_T_1347, _T_1352) node _T_1354 = and(_T_1342, _T_1353) node _T_1355 = or(UInt<1>(0h0), _T_1354) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_20 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(source_ok, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(is_aligned, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1365 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_23 node _T_1369 = eq(io.in.a.bits.mask, mask) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_24 node _T_1373 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_25 node _T_1377 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1377 : node _T_1378 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1379 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1380 = and(_T_1378, _T_1379) node _T_1381 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_132 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_132 = bits(_uncommonBits_T_132, 1, 0) node _T_1382 = shr(io.in.a.bits.source, 2) node _T_1383 = eq(_T_1382, UInt<7>(0h70)) node _T_1384 = leq(UInt<1>(0h0), uncommonBits_132) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = leq(uncommonBits_132, UInt<2>(0h3)) node _T_1387 = and(_T_1385, _T_1386) node _uncommonBits_T_133 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_133 = bits(_uncommonBits_T_133, 1, 0) node _T_1388 = shr(io.in.a.bits.source, 2) node _T_1389 = eq(_T_1388, UInt<7>(0h71)) node _T_1390 = leq(UInt<1>(0h0), uncommonBits_133) node _T_1391 = and(_T_1389, _T_1390) node _T_1392 = leq(uncommonBits_133, UInt<2>(0h3)) node _T_1393 = and(_T_1391, _T_1392) node _uncommonBits_T_134 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_134 = bits(_uncommonBits_T_134, 1, 0) node _T_1394 = shr(io.in.a.bits.source, 2) node _T_1395 = eq(_T_1394, UInt<7>(0h72)) node _T_1396 = leq(UInt<1>(0h0), uncommonBits_134) node _T_1397 = and(_T_1395, _T_1396) node _T_1398 = leq(uncommonBits_134, UInt<2>(0h3)) node _T_1399 = and(_T_1397, _T_1398) node _uncommonBits_T_135 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_135 = bits(_uncommonBits_T_135, 1, 0) node _T_1400 = shr(io.in.a.bits.source, 2) node _T_1401 = eq(_T_1400, UInt<7>(0h73)) node _T_1402 = leq(UInt<1>(0h0), uncommonBits_135) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = leq(uncommonBits_135, UInt<2>(0h3)) node _T_1405 = and(_T_1403, _T_1404) node _uncommonBits_T_136 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_136 = bits(_uncommonBits_T_136, 1, 0) node _T_1406 = shr(io.in.a.bits.source, 2) node _T_1407 = eq(_T_1406, UInt<7>(0h7c)) node _T_1408 = leq(UInt<1>(0h0), uncommonBits_136) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = leq(uncommonBits_136, UInt<2>(0h3)) node _T_1411 = and(_T_1409, _T_1410) node _uncommonBits_T_137 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_137 = bits(_uncommonBits_T_137, 1, 0) node _T_1412 = shr(io.in.a.bits.source, 2) node _T_1413 = eq(_T_1412, UInt<7>(0h7b)) node _T_1414 = leq(UInt<1>(0h0), uncommonBits_137) node _T_1415 = and(_T_1413, _T_1414) node _T_1416 = leq(uncommonBits_137, UInt<2>(0h3)) node _T_1417 = and(_T_1415, _T_1416) node _uncommonBits_T_138 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_138 = bits(_uncommonBits_T_138, 4, 0) node _T_1418 = shr(io.in.a.bits.source, 5) node _T_1419 = eq(_T_1418, UInt<4>(0hd)) node _T_1420 = leq(UInt<1>(0h0), uncommonBits_138) node _T_1421 = and(_T_1419, _T_1420) node _T_1422 = leq(uncommonBits_138, UInt<5>(0h1f)) node _T_1423 = and(_T_1421, _T_1422) node _uncommonBits_T_139 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_139 = bits(_uncommonBits_T_139, 4, 0) node _T_1424 = shr(io.in.a.bits.source, 5) node _T_1425 = eq(_T_1424, UInt<4>(0hc)) node _T_1426 = leq(UInt<1>(0h0), uncommonBits_139) node _T_1427 = and(_T_1425, _T_1426) node _T_1428 = leq(uncommonBits_139, UInt<5>(0h1f)) node _T_1429 = and(_T_1427, _T_1428) node _uncommonBits_T_140 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_140 = bits(_uncommonBits_T_140, 4, 0) node _T_1430 = shr(io.in.a.bits.source, 5) node _T_1431 = eq(_T_1430, UInt<4>(0hb)) node _T_1432 = leq(UInt<1>(0h0), uncommonBits_140) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = leq(uncommonBits_140, UInt<5>(0h1f)) node _T_1435 = and(_T_1433, _T_1434) node _uncommonBits_T_141 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_141 = bits(_uncommonBits_T_141, 4, 0) node _T_1436 = shr(io.in.a.bits.source, 5) node _T_1437 = eq(_T_1436, UInt<4>(0ha)) node _T_1438 = leq(UInt<1>(0h0), uncommonBits_141) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = leq(uncommonBits_141, UInt<5>(0h1f)) node _T_1441 = and(_T_1439, _T_1440) node _uncommonBits_T_142 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_142 = bits(_uncommonBits_T_142, 4, 0) node _T_1442 = shr(io.in.a.bits.source, 5) node _T_1443 = eq(_T_1442, UInt<4>(0h9)) node _T_1444 = leq(UInt<1>(0h0), uncommonBits_142) node _T_1445 = and(_T_1443, _T_1444) node _T_1446 = leq(uncommonBits_142, UInt<5>(0h1f)) node _T_1447 = and(_T_1445, _T_1446) node _uncommonBits_T_143 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_143 = bits(_uncommonBits_T_143, 4, 0) node _T_1448 = shr(io.in.a.bits.source, 5) node _T_1449 = eq(_T_1448, UInt<4>(0h8)) node _T_1450 = leq(UInt<1>(0h0), uncommonBits_143) node _T_1451 = and(_T_1449, _T_1450) node _T_1452 = leq(uncommonBits_143, UInt<5>(0h1f)) node _T_1453 = and(_T_1451, _T_1452) node _uncommonBits_T_144 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_144 = bits(_uncommonBits_T_144, 1, 0) node _T_1454 = shr(io.in.a.bits.source, 2) node _T_1455 = eq(_T_1454, UInt<7>(0h7a)) node _T_1456 = leq(UInt<1>(0h0), uncommonBits_144) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = leq(uncommonBits_144, UInt<2>(0h3)) node _T_1459 = and(_T_1457, _T_1458) node _uncommonBits_T_145 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_145 = bits(_uncommonBits_T_145, 1, 0) node _T_1460 = shr(io.in.a.bits.source, 2) node _T_1461 = eq(_T_1460, UInt<7>(0h79)) node _T_1462 = leq(UInt<1>(0h0), uncommonBits_145) node _T_1463 = and(_T_1461, _T_1462) node _T_1464 = leq(uncommonBits_145, UInt<2>(0h3)) node _T_1465 = and(_T_1463, _T_1464) node _uncommonBits_T_146 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_146 = bits(_uncommonBits_T_146, 4, 0) node _T_1466 = shr(io.in.a.bits.source, 5) node _T_1467 = eq(_T_1466, UInt<3>(0h7)) node _T_1468 = leq(UInt<1>(0h0), uncommonBits_146) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = leq(uncommonBits_146, UInt<5>(0h1f)) node _T_1471 = and(_T_1469, _T_1470) node _uncommonBits_T_147 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_147 = bits(_uncommonBits_T_147, 4, 0) node _T_1472 = shr(io.in.a.bits.source, 5) node _T_1473 = eq(_T_1472, UInt<3>(0h6)) node _T_1474 = leq(UInt<1>(0h0), uncommonBits_147) node _T_1475 = and(_T_1473, _T_1474) node _T_1476 = leq(uncommonBits_147, UInt<5>(0h1f)) node _T_1477 = and(_T_1475, _T_1476) node _uncommonBits_T_148 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_148 = bits(_uncommonBits_T_148, 4, 0) node _T_1478 = shr(io.in.a.bits.source, 5) node _T_1479 = eq(_T_1478, UInt<3>(0h5)) node _T_1480 = leq(UInt<1>(0h0), uncommonBits_148) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = leq(uncommonBits_148, UInt<5>(0h1f)) node _T_1483 = and(_T_1481, _T_1482) node _uncommonBits_T_149 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_149 = bits(_uncommonBits_T_149, 4, 0) node _T_1484 = shr(io.in.a.bits.source, 5) node _T_1485 = eq(_T_1484, UInt<3>(0h4)) node _T_1486 = leq(UInt<1>(0h0), uncommonBits_149) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = leq(uncommonBits_149, UInt<5>(0h1f)) node _T_1489 = and(_T_1487, _T_1488) node _uncommonBits_T_150 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_150 = bits(_uncommonBits_T_150, 4, 0) node _T_1490 = shr(io.in.a.bits.source, 5) node _T_1491 = eq(_T_1490, UInt<2>(0h3)) node _T_1492 = leq(UInt<1>(0h0), uncommonBits_150) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = leq(uncommonBits_150, UInt<5>(0h1f)) node _T_1495 = and(_T_1493, _T_1494) node _uncommonBits_T_151 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_151 = bits(_uncommonBits_T_151, 4, 0) node _T_1496 = shr(io.in.a.bits.source, 5) node _T_1497 = eq(_T_1496, UInt<2>(0h2)) node _T_1498 = leq(UInt<1>(0h0), uncommonBits_151) node _T_1499 = and(_T_1497, _T_1498) node _T_1500 = leq(uncommonBits_151, UInt<5>(0h1f)) node _T_1501 = and(_T_1499, _T_1500) node _uncommonBits_T_152 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_152 = bits(_uncommonBits_T_152, 4, 0) node _T_1502 = shr(io.in.a.bits.source, 5) node _T_1503 = eq(_T_1502, UInt<1>(0h1)) node _T_1504 = leq(UInt<1>(0h0), uncommonBits_152) node _T_1505 = and(_T_1503, _T_1504) node _T_1506 = leq(uncommonBits_152, UInt<5>(0h1f)) node _T_1507 = and(_T_1505, _T_1506) node _uncommonBits_T_153 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_153 = bits(_uncommonBits_T_153, 4, 0) node _T_1508 = shr(io.in.a.bits.source, 5) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) node _T_1510 = leq(UInt<1>(0h0), uncommonBits_153) node _T_1511 = and(_T_1509, _T_1510) node _T_1512 = leq(uncommonBits_153, UInt<5>(0h1f)) node _T_1513 = and(_T_1511, _T_1512) node _T_1514 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1515 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1516 = or(_T_1381, _T_1387) node _T_1517 = or(_T_1516, _T_1393) node _T_1518 = or(_T_1517, _T_1399) node _T_1519 = or(_T_1518, _T_1405) node _T_1520 = or(_T_1519, _T_1411) node _T_1521 = or(_T_1520, _T_1417) node _T_1522 = or(_T_1521, _T_1423) node _T_1523 = or(_T_1522, _T_1429) node _T_1524 = or(_T_1523, _T_1435) node _T_1525 = or(_T_1524, _T_1441) node _T_1526 = or(_T_1525, _T_1447) node _T_1527 = or(_T_1526, _T_1453) node _T_1528 = or(_T_1527, _T_1459) node _T_1529 = or(_T_1528, _T_1465) node _T_1530 = or(_T_1529, _T_1471) node _T_1531 = or(_T_1530, _T_1477) node _T_1532 = or(_T_1531, _T_1483) node _T_1533 = or(_T_1532, _T_1489) node _T_1534 = or(_T_1533, _T_1495) node _T_1535 = or(_T_1534, _T_1501) node _T_1536 = or(_T_1535, _T_1507) node _T_1537 = or(_T_1536, _T_1513) node _T_1538 = or(_T_1537, _T_1514) node _T_1539 = or(_T_1538, _T_1515) node _T_1540 = and(_T_1380, _T_1539) node _T_1541 = or(UInt<1>(0h0), _T_1540) node _T_1542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1543 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1544 = and(_T_1542, _T_1543) node _T_1545 = or(UInt<1>(0h0), _T_1544) node _T_1546 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1547 = cvt(_T_1546) node _T_1548 = and(_T_1547, asSInt(UInt<17>(0h10000))) node _T_1549 = asSInt(_T_1548) node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0))) node _T_1551 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1552 = cvt(_T_1551) node _T_1553 = and(_T_1552, asSInt(UInt<29>(0h10000000))) node _T_1554 = asSInt(_T_1553) node _T_1555 = eq(_T_1554, asSInt(UInt<1>(0h0))) node _T_1556 = or(_T_1550, _T_1555) node _T_1557 = and(_T_1545, _T_1556) node _T_1558 = or(UInt<1>(0h0), _T_1557) node _T_1559 = and(_T_1541, _T_1558) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_26 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(source_ok, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_29 node _T_1573 = eq(io.in.a.bits.mask, mask) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_30 node _T_1577 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_154 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_154 = bits(_uncommonBits_T_154, 1, 0) node _T_1582 = shr(io.in.a.bits.source, 2) node _T_1583 = eq(_T_1582, UInt<7>(0h70)) node _T_1584 = leq(UInt<1>(0h0), uncommonBits_154) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = leq(uncommonBits_154, UInt<2>(0h3)) node _T_1587 = and(_T_1585, _T_1586) node _uncommonBits_T_155 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_155 = bits(_uncommonBits_T_155, 1, 0) node _T_1588 = shr(io.in.a.bits.source, 2) node _T_1589 = eq(_T_1588, UInt<7>(0h71)) node _T_1590 = leq(UInt<1>(0h0), uncommonBits_155) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = leq(uncommonBits_155, UInt<2>(0h3)) node _T_1593 = and(_T_1591, _T_1592) node _uncommonBits_T_156 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_156 = bits(_uncommonBits_T_156, 1, 0) node _T_1594 = shr(io.in.a.bits.source, 2) node _T_1595 = eq(_T_1594, UInt<7>(0h72)) node _T_1596 = leq(UInt<1>(0h0), uncommonBits_156) node _T_1597 = and(_T_1595, _T_1596) node _T_1598 = leq(uncommonBits_156, UInt<2>(0h3)) node _T_1599 = and(_T_1597, _T_1598) node _uncommonBits_T_157 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_157 = bits(_uncommonBits_T_157, 1, 0) node _T_1600 = shr(io.in.a.bits.source, 2) node _T_1601 = eq(_T_1600, UInt<7>(0h73)) node _T_1602 = leq(UInt<1>(0h0), uncommonBits_157) node _T_1603 = and(_T_1601, _T_1602) node _T_1604 = leq(uncommonBits_157, UInt<2>(0h3)) node _T_1605 = and(_T_1603, _T_1604) node _uncommonBits_T_158 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_158 = bits(_uncommonBits_T_158, 1, 0) node _T_1606 = shr(io.in.a.bits.source, 2) node _T_1607 = eq(_T_1606, UInt<7>(0h7c)) node _T_1608 = leq(UInt<1>(0h0), uncommonBits_158) node _T_1609 = and(_T_1607, _T_1608) node _T_1610 = leq(uncommonBits_158, UInt<2>(0h3)) node _T_1611 = and(_T_1609, _T_1610) node _uncommonBits_T_159 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_159 = bits(_uncommonBits_T_159, 1, 0) node _T_1612 = shr(io.in.a.bits.source, 2) node _T_1613 = eq(_T_1612, UInt<7>(0h7b)) node _T_1614 = leq(UInt<1>(0h0), uncommonBits_159) node _T_1615 = and(_T_1613, _T_1614) node _T_1616 = leq(uncommonBits_159, UInt<2>(0h3)) node _T_1617 = and(_T_1615, _T_1616) node _uncommonBits_T_160 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_160 = bits(_uncommonBits_T_160, 4, 0) node _T_1618 = shr(io.in.a.bits.source, 5) node _T_1619 = eq(_T_1618, UInt<4>(0hd)) node _T_1620 = leq(UInt<1>(0h0), uncommonBits_160) node _T_1621 = and(_T_1619, _T_1620) node _T_1622 = leq(uncommonBits_160, UInt<5>(0h1f)) node _T_1623 = and(_T_1621, _T_1622) node _uncommonBits_T_161 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_161 = bits(_uncommonBits_T_161, 4, 0) node _T_1624 = shr(io.in.a.bits.source, 5) node _T_1625 = eq(_T_1624, UInt<4>(0hc)) node _T_1626 = leq(UInt<1>(0h0), uncommonBits_161) node _T_1627 = and(_T_1625, _T_1626) node _T_1628 = leq(uncommonBits_161, UInt<5>(0h1f)) node _T_1629 = and(_T_1627, _T_1628) node _uncommonBits_T_162 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_162 = bits(_uncommonBits_T_162, 4, 0) node _T_1630 = shr(io.in.a.bits.source, 5) node _T_1631 = eq(_T_1630, UInt<4>(0hb)) node _T_1632 = leq(UInt<1>(0h0), uncommonBits_162) node _T_1633 = and(_T_1631, _T_1632) node _T_1634 = leq(uncommonBits_162, UInt<5>(0h1f)) node _T_1635 = and(_T_1633, _T_1634) node _uncommonBits_T_163 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_163 = bits(_uncommonBits_T_163, 4, 0) node _T_1636 = shr(io.in.a.bits.source, 5) node _T_1637 = eq(_T_1636, UInt<4>(0ha)) node _T_1638 = leq(UInt<1>(0h0), uncommonBits_163) node _T_1639 = and(_T_1637, _T_1638) node _T_1640 = leq(uncommonBits_163, UInt<5>(0h1f)) node _T_1641 = and(_T_1639, _T_1640) node _uncommonBits_T_164 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_164 = bits(_uncommonBits_T_164, 4, 0) node _T_1642 = shr(io.in.a.bits.source, 5) node _T_1643 = eq(_T_1642, UInt<4>(0h9)) node _T_1644 = leq(UInt<1>(0h0), uncommonBits_164) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = leq(uncommonBits_164, UInt<5>(0h1f)) node _T_1647 = and(_T_1645, _T_1646) node _uncommonBits_T_165 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_165 = bits(_uncommonBits_T_165, 4, 0) node _T_1648 = shr(io.in.a.bits.source, 5) node _T_1649 = eq(_T_1648, UInt<4>(0h8)) node _T_1650 = leq(UInt<1>(0h0), uncommonBits_165) node _T_1651 = and(_T_1649, _T_1650) node _T_1652 = leq(uncommonBits_165, UInt<5>(0h1f)) node _T_1653 = and(_T_1651, _T_1652) node _uncommonBits_T_166 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_166 = bits(_uncommonBits_T_166, 1, 0) node _T_1654 = shr(io.in.a.bits.source, 2) node _T_1655 = eq(_T_1654, UInt<7>(0h7a)) node _T_1656 = leq(UInt<1>(0h0), uncommonBits_166) node _T_1657 = and(_T_1655, _T_1656) node _T_1658 = leq(uncommonBits_166, UInt<2>(0h3)) node _T_1659 = and(_T_1657, _T_1658) node _uncommonBits_T_167 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_167 = bits(_uncommonBits_T_167, 1, 0) node _T_1660 = shr(io.in.a.bits.source, 2) node _T_1661 = eq(_T_1660, UInt<7>(0h79)) node _T_1662 = leq(UInt<1>(0h0), uncommonBits_167) node _T_1663 = and(_T_1661, _T_1662) node _T_1664 = leq(uncommonBits_167, UInt<2>(0h3)) node _T_1665 = and(_T_1663, _T_1664) node _uncommonBits_T_168 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_168 = bits(_uncommonBits_T_168, 4, 0) node _T_1666 = shr(io.in.a.bits.source, 5) node _T_1667 = eq(_T_1666, UInt<3>(0h7)) node _T_1668 = leq(UInt<1>(0h0), uncommonBits_168) node _T_1669 = and(_T_1667, _T_1668) node _T_1670 = leq(uncommonBits_168, UInt<5>(0h1f)) node _T_1671 = and(_T_1669, _T_1670) node _uncommonBits_T_169 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_169 = bits(_uncommonBits_T_169, 4, 0) node _T_1672 = shr(io.in.a.bits.source, 5) node _T_1673 = eq(_T_1672, UInt<3>(0h6)) node _T_1674 = leq(UInt<1>(0h0), uncommonBits_169) node _T_1675 = and(_T_1673, _T_1674) node _T_1676 = leq(uncommonBits_169, UInt<5>(0h1f)) node _T_1677 = and(_T_1675, _T_1676) node _uncommonBits_T_170 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_170 = bits(_uncommonBits_T_170, 4, 0) node _T_1678 = shr(io.in.a.bits.source, 5) node _T_1679 = eq(_T_1678, UInt<3>(0h5)) node _T_1680 = leq(UInt<1>(0h0), uncommonBits_170) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = leq(uncommonBits_170, UInt<5>(0h1f)) node _T_1683 = and(_T_1681, _T_1682) node _uncommonBits_T_171 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_171 = bits(_uncommonBits_T_171, 4, 0) node _T_1684 = shr(io.in.a.bits.source, 5) node _T_1685 = eq(_T_1684, UInt<3>(0h4)) node _T_1686 = leq(UInt<1>(0h0), uncommonBits_171) node _T_1687 = and(_T_1685, _T_1686) node _T_1688 = leq(uncommonBits_171, UInt<5>(0h1f)) node _T_1689 = and(_T_1687, _T_1688) node _uncommonBits_T_172 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_172 = bits(_uncommonBits_T_172, 4, 0) node _T_1690 = shr(io.in.a.bits.source, 5) node _T_1691 = eq(_T_1690, UInt<2>(0h3)) node _T_1692 = leq(UInt<1>(0h0), uncommonBits_172) node _T_1693 = and(_T_1691, _T_1692) node _T_1694 = leq(uncommonBits_172, UInt<5>(0h1f)) node _T_1695 = and(_T_1693, _T_1694) node _uncommonBits_T_173 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_173 = bits(_uncommonBits_T_173, 4, 0) node _T_1696 = shr(io.in.a.bits.source, 5) node _T_1697 = eq(_T_1696, UInt<2>(0h2)) node _T_1698 = leq(UInt<1>(0h0), uncommonBits_173) node _T_1699 = and(_T_1697, _T_1698) node _T_1700 = leq(uncommonBits_173, UInt<5>(0h1f)) node _T_1701 = and(_T_1699, _T_1700) node _uncommonBits_T_174 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_174 = bits(_uncommonBits_T_174, 4, 0) node _T_1702 = shr(io.in.a.bits.source, 5) node _T_1703 = eq(_T_1702, UInt<1>(0h1)) node _T_1704 = leq(UInt<1>(0h0), uncommonBits_174) node _T_1705 = and(_T_1703, _T_1704) node _T_1706 = leq(uncommonBits_174, UInt<5>(0h1f)) node _T_1707 = and(_T_1705, _T_1706) node _uncommonBits_T_175 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_175 = bits(_uncommonBits_T_175, 4, 0) node _T_1708 = shr(io.in.a.bits.source, 5) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) node _T_1710 = leq(UInt<1>(0h0), uncommonBits_175) node _T_1711 = and(_T_1709, _T_1710) node _T_1712 = leq(uncommonBits_175, UInt<5>(0h1f)) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1715 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1716 = or(_T_1581, _T_1587) node _T_1717 = or(_T_1716, _T_1593) node _T_1718 = or(_T_1717, _T_1599) node _T_1719 = or(_T_1718, _T_1605) node _T_1720 = or(_T_1719, _T_1611) node _T_1721 = or(_T_1720, _T_1617) node _T_1722 = or(_T_1721, _T_1623) node _T_1723 = or(_T_1722, _T_1629) node _T_1724 = or(_T_1723, _T_1635) node _T_1725 = or(_T_1724, _T_1641) node _T_1726 = or(_T_1725, _T_1647) node _T_1727 = or(_T_1726, _T_1653) node _T_1728 = or(_T_1727, _T_1659) node _T_1729 = or(_T_1728, _T_1665) node _T_1730 = or(_T_1729, _T_1671) node _T_1731 = or(_T_1730, _T_1677) node _T_1732 = or(_T_1731, _T_1683) node _T_1733 = or(_T_1732, _T_1689) node _T_1734 = or(_T_1733, _T_1695) node _T_1735 = or(_T_1734, _T_1701) node _T_1736 = or(_T_1735, _T_1707) node _T_1737 = or(_T_1736, _T_1713) node _T_1738 = or(_T_1737, _T_1714) node _T_1739 = or(_T_1738, _T_1715) node _T_1740 = and(_T_1580, _T_1739) node _T_1741 = or(UInt<1>(0h0), _T_1740) node _T_1742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1743 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = or(UInt<1>(0h0), _T_1744) node _T_1746 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<17>(0h10000))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1752 = cvt(_T_1751) node _T_1753 = and(_T_1752, asSInt(UInt<29>(0h10000000))) node _T_1754 = asSInt(_T_1753) node _T_1755 = eq(_T_1754, asSInt(UInt<1>(0h0))) node _T_1756 = or(_T_1750, _T_1755) node _T_1757 = and(_T_1745, _T_1756) node _T_1758 = or(UInt<1>(0h0), _T_1757) node _T_1759 = and(_T_1741, _T_1758) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_31 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(source_ok, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1769 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_34 node _T_1773 = not(mask) node _T_1774 = and(io.in.a.bits.mask, _T_1773) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_35 node _T_1779 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1779 : node _T_1780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1782 = and(_T_1780, _T_1781) node _T_1783 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_176 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_176 = bits(_uncommonBits_T_176, 1, 0) node _T_1784 = shr(io.in.a.bits.source, 2) node _T_1785 = eq(_T_1784, UInt<7>(0h70)) node _T_1786 = leq(UInt<1>(0h0), uncommonBits_176) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = leq(uncommonBits_176, UInt<2>(0h3)) node _T_1789 = and(_T_1787, _T_1788) node _uncommonBits_T_177 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_177 = bits(_uncommonBits_T_177, 1, 0) node _T_1790 = shr(io.in.a.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<7>(0h71)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_177) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_177, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_178 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_178 = bits(_uncommonBits_T_178, 1, 0) node _T_1796 = shr(io.in.a.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<7>(0h72)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_178) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_178, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_179 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_179 = bits(_uncommonBits_T_179, 1, 0) node _T_1802 = shr(io.in.a.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<7>(0h73)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_179) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_179, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_180 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_180 = bits(_uncommonBits_T_180, 1, 0) node _T_1808 = shr(io.in.a.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<7>(0h7c)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_180) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_180, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_181 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_181 = bits(_uncommonBits_T_181, 1, 0) node _T_1814 = shr(io.in.a.bits.source, 2) node _T_1815 = eq(_T_1814, UInt<7>(0h7b)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_181) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_181, UInt<2>(0h3)) node _T_1819 = and(_T_1817, _T_1818) node _uncommonBits_T_182 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_182 = bits(_uncommonBits_T_182, 4, 0) node _T_1820 = shr(io.in.a.bits.source, 5) node _T_1821 = eq(_T_1820, UInt<4>(0hd)) node _T_1822 = leq(UInt<1>(0h0), uncommonBits_182) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = leq(uncommonBits_182, UInt<5>(0h1f)) node _T_1825 = and(_T_1823, _T_1824) node _uncommonBits_T_183 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_183 = bits(_uncommonBits_T_183, 4, 0) node _T_1826 = shr(io.in.a.bits.source, 5) node _T_1827 = eq(_T_1826, UInt<4>(0hc)) node _T_1828 = leq(UInt<1>(0h0), uncommonBits_183) node _T_1829 = and(_T_1827, _T_1828) node _T_1830 = leq(uncommonBits_183, UInt<5>(0h1f)) node _T_1831 = and(_T_1829, _T_1830) node _uncommonBits_T_184 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_184 = bits(_uncommonBits_T_184, 4, 0) node _T_1832 = shr(io.in.a.bits.source, 5) node _T_1833 = eq(_T_1832, UInt<4>(0hb)) node _T_1834 = leq(UInt<1>(0h0), uncommonBits_184) node _T_1835 = and(_T_1833, _T_1834) node _T_1836 = leq(uncommonBits_184, UInt<5>(0h1f)) node _T_1837 = and(_T_1835, _T_1836) node _uncommonBits_T_185 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_185 = bits(_uncommonBits_T_185, 4, 0) node _T_1838 = shr(io.in.a.bits.source, 5) node _T_1839 = eq(_T_1838, UInt<4>(0ha)) node _T_1840 = leq(UInt<1>(0h0), uncommonBits_185) node _T_1841 = and(_T_1839, _T_1840) node _T_1842 = leq(uncommonBits_185, UInt<5>(0h1f)) node _T_1843 = and(_T_1841, _T_1842) node _uncommonBits_T_186 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_186 = bits(_uncommonBits_T_186, 4, 0) node _T_1844 = shr(io.in.a.bits.source, 5) node _T_1845 = eq(_T_1844, UInt<4>(0h9)) node _T_1846 = leq(UInt<1>(0h0), uncommonBits_186) node _T_1847 = and(_T_1845, _T_1846) node _T_1848 = leq(uncommonBits_186, UInt<5>(0h1f)) node _T_1849 = and(_T_1847, _T_1848) node _uncommonBits_T_187 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_187 = bits(_uncommonBits_T_187, 4, 0) node _T_1850 = shr(io.in.a.bits.source, 5) node _T_1851 = eq(_T_1850, UInt<4>(0h8)) node _T_1852 = leq(UInt<1>(0h0), uncommonBits_187) node _T_1853 = and(_T_1851, _T_1852) node _T_1854 = leq(uncommonBits_187, UInt<5>(0h1f)) node _T_1855 = and(_T_1853, _T_1854) node _uncommonBits_T_188 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_188 = bits(_uncommonBits_T_188, 1, 0) node _T_1856 = shr(io.in.a.bits.source, 2) node _T_1857 = eq(_T_1856, UInt<7>(0h7a)) node _T_1858 = leq(UInt<1>(0h0), uncommonBits_188) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = leq(uncommonBits_188, UInt<2>(0h3)) node _T_1861 = and(_T_1859, _T_1860) node _uncommonBits_T_189 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_189 = bits(_uncommonBits_T_189, 1, 0) node _T_1862 = shr(io.in.a.bits.source, 2) node _T_1863 = eq(_T_1862, UInt<7>(0h79)) node _T_1864 = leq(UInt<1>(0h0), uncommonBits_189) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = leq(uncommonBits_189, UInt<2>(0h3)) node _T_1867 = and(_T_1865, _T_1866) node _uncommonBits_T_190 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_190 = bits(_uncommonBits_T_190, 4, 0) node _T_1868 = shr(io.in.a.bits.source, 5) node _T_1869 = eq(_T_1868, UInt<3>(0h7)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_190) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_190, UInt<5>(0h1f)) node _T_1873 = and(_T_1871, _T_1872) node _uncommonBits_T_191 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_191 = bits(_uncommonBits_T_191, 4, 0) node _T_1874 = shr(io.in.a.bits.source, 5) node _T_1875 = eq(_T_1874, UInt<3>(0h6)) node _T_1876 = leq(UInt<1>(0h0), uncommonBits_191) node _T_1877 = and(_T_1875, _T_1876) node _T_1878 = leq(uncommonBits_191, UInt<5>(0h1f)) node _T_1879 = and(_T_1877, _T_1878) node _uncommonBits_T_192 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_192 = bits(_uncommonBits_T_192, 4, 0) node _T_1880 = shr(io.in.a.bits.source, 5) node _T_1881 = eq(_T_1880, UInt<3>(0h5)) node _T_1882 = leq(UInt<1>(0h0), uncommonBits_192) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = leq(uncommonBits_192, UInt<5>(0h1f)) node _T_1885 = and(_T_1883, _T_1884) node _uncommonBits_T_193 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_193 = bits(_uncommonBits_T_193, 4, 0) node _T_1886 = shr(io.in.a.bits.source, 5) node _T_1887 = eq(_T_1886, UInt<3>(0h4)) node _T_1888 = leq(UInt<1>(0h0), uncommonBits_193) node _T_1889 = and(_T_1887, _T_1888) node _T_1890 = leq(uncommonBits_193, UInt<5>(0h1f)) node _T_1891 = and(_T_1889, _T_1890) node _uncommonBits_T_194 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_194 = bits(_uncommonBits_T_194, 4, 0) node _T_1892 = shr(io.in.a.bits.source, 5) node _T_1893 = eq(_T_1892, UInt<2>(0h3)) node _T_1894 = leq(UInt<1>(0h0), uncommonBits_194) node _T_1895 = and(_T_1893, _T_1894) node _T_1896 = leq(uncommonBits_194, UInt<5>(0h1f)) node _T_1897 = and(_T_1895, _T_1896) node _uncommonBits_T_195 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_195 = bits(_uncommonBits_T_195, 4, 0) node _T_1898 = shr(io.in.a.bits.source, 5) node _T_1899 = eq(_T_1898, UInt<2>(0h2)) node _T_1900 = leq(UInt<1>(0h0), uncommonBits_195) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = leq(uncommonBits_195, UInt<5>(0h1f)) node _T_1903 = and(_T_1901, _T_1902) node _uncommonBits_T_196 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_196 = bits(_uncommonBits_T_196, 4, 0) node _T_1904 = shr(io.in.a.bits.source, 5) node _T_1905 = eq(_T_1904, UInt<1>(0h1)) node _T_1906 = leq(UInt<1>(0h0), uncommonBits_196) node _T_1907 = and(_T_1905, _T_1906) node _T_1908 = leq(uncommonBits_196, UInt<5>(0h1f)) node _T_1909 = and(_T_1907, _T_1908) node _uncommonBits_T_197 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_197 = bits(_uncommonBits_T_197, 4, 0) node _T_1910 = shr(io.in.a.bits.source, 5) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) node _T_1912 = leq(UInt<1>(0h0), uncommonBits_197) node _T_1913 = and(_T_1911, _T_1912) node _T_1914 = leq(uncommonBits_197, UInt<5>(0h1f)) node _T_1915 = and(_T_1913, _T_1914) node _T_1916 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1917 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1918 = or(_T_1783, _T_1789) node _T_1919 = or(_T_1918, _T_1795) node _T_1920 = or(_T_1919, _T_1801) node _T_1921 = or(_T_1920, _T_1807) node _T_1922 = or(_T_1921, _T_1813) node _T_1923 = or(_T_1922, _T_1819) node _T_1924 = or(_T_1923, _T_1825) node _T_1925 = or(_T_1924, _T_1831) node _T_1926 = or(_T_1925, _T_1837) node _T_1927 = or(_T_1926, _T_1843) node _T_1928 = or(_T_1927, _T_1849) node _T_1929 = or(_T_1928, _T_1855) node _T_1930 = or(_T_1929, _T_1861) node _T_1931 = or(_T_1930, _T_1867) node _T_1932 = or(_T_1931, _T_1873) node _T_1933 = or(_T_1932, _T_1879) node _T_1934 = or(_T_1933, _T_1885) node _T_1935 = or(_T_1934, _T_1891) node _T_1936 = or(_T_1935, _T_1897) node _T_1937 = or(_T_1936, _T_1903) node _T_1938 = or(_T_1937, _T_1909) node _T_1939 = or(_T_1938, _T_1915) node _T_1940 = or(_T_1939, _T_1916) node _T_1941 = or(_T_1940, _T_1917) node _T_1942 = and(_T_1782, _T_1941) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1945 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1946 = and(_T_1944, _T_1945) node _T_1947 = or(UInt<1>(0h0), _T_1946) node _T_1948 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<17>(0h10000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1952, _T_1957) node _T_1959 = and(_T_1947, _T_1958) node _T_1960 = or(UInt<1>(0h0), _T_1959) node _T_1961 = and(_T_1943, _T_1960) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_36 node _T_1965 = asUInt(reset) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) when _T_1966 : node _T_1967 = eq(source_ok, UInt<1>(0h0)) when _T_1967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(is_aligned, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1971 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_39 node _T_1975 = eq(io.in.a.bits.mask, mask) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_40 node _T_1979 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1979 : node _T_1980 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1981 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1982 = and(_T_1980, _T_1981) node _T_1983 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_198 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_198 = bits(_uncommonBits_T_198, 1, 0) node _T_1984 = shr(io.in.a.bits.source, 2) node _T_1985 = eq(_T_1984, UInt<7>(0h70)) node _T_1986 = leq(UInt<1>(0h0), uncommonBits_198) node _T_1987 = and(_T_1985, _T_1986) node _T_1988 = leq(uncommonBits_198, UInt<2>(0h3)) node _T_1989 = and(_T_1987, _T_1988) node _uncommonBits_T_199 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_199 = bits(_uncommonBits_T_199, 1, 0) node _T_1990 = shr(io.in.a.bits.source, 2) node _T_1991 = eq(_T_1990, UInt<7>(0h71)) node _T_1992 = leq(UInt<1>(0h0), uncommonBits_199) node _T_1993 = and(_T_1991, _T_1992) node _T_1994 = leq(uncommonBits_199, UInt<2>(0h3)) node _T_1995 = and(_T_1993, _T_1994) node _uncommonBits_T_200 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_200 = bits(_uncommonBits_T_200, 1, 0) node _T_1996 = shr(io.in.a.bits.source, 2) node _T_1997 = eq(_T_1996, UInt<7>(0h72)) node _T_1998 = leq(UInt<1>(0h0), uncommonBits_200) node _T_1999 = and(_T_1997, _T_1998) node _T_2000 = leq(uncommonBits_200, UInt<2>(0h3)) node _T_2001 = and(_T_1999, _T_2000) node _uncommonBits_T_201 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_201 = bits(_uncommonBits_T_201, 1, 0) node _T_2002 = shr(io.in.a.bits.source, 2) node _T_2003 = eq(_T_2002, UInt<7>(0h73)) node _T_2004 = leq(UInt<1>(0h0), uncommonBits_201) node _T_2005 = and(_T_2003, _T_2004) node _T_2006 = leq(uncommonBits_201, UInt<2>(0h3)) node _T_2007 = and(_T_2005, _T_2006) node _uncommonBits_T_202 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_202 = bits(_uncommonBits_T_202, 1, 0) node _T_2008 = shr(io.in.a.bits.source, 2) node _T_2009 = eq(_T_2008, UInt<7>(0h7c)) node _T_2010 = leq(UInt<1>(0h0), uncommonBits_202) node _T_2011 = and(_T_2009, _T_2010) node _T_2012 = leq(uncommonBits_202, UInt<2>(0h3)) node _T_2013 = and(_T_2011, _T_2012) node _uncommonBits_T_203 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_203 = bits(_uncommonBits_T_203, 1, 0) node _T_2014 = shr(io.in.a.bits.source, 2) node _T_2015 = eq(_T_2014, UInt<7>(0h7b)) node _T_2016 = leq(UInt<1>(0h0), uncommonBits_203) node _T_2017 = and(_T_2015, _T_2016) node _T_2018 = leq(uncommonBits_203, UInt<2>(0h3)) node _T_2019 = and(_T_2017, _T_2018) node _uncommonBits_T_204 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_204 = bits(_uncommonBits_T_204, 4, 0) node _T_2020 = shr(io.in.a.bits.source, 5) node _T_2021 = eq(_T_2020, UInt<4>(0hd)) node _T_2022 = leq(UInt<1>(0h0), uncommonBits_204) node _T_2023 = and(_T_2021, _T_2022) node _T_2024 = leq(uncommonBits_204, UInt<5>(0h1f)) node _T_2025 = and(_T_2023, _T_2024) node _uncommonBits_T_205 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_205 = bits(_uncommonBits_T_205, 4, 0) node _T_2026 = shr(io.in.a.bits.source, 5) node _T_2027 = eq(_T_2026, UInt<4>(0hc)) node _T_2028 = leq(UInt<1>(0h0), uncommonBits_205) node _T_2029 = and(_T_2027, _T_2028) node _T_2030 = leq(uncommonBits_205, UInt<5>(0h1f)) node _T_2031 = and(_T_2029, _T_2030) node _uncommonBits_T_206 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_206 = bits(_uncommonBits_T_206, 4, 0) node _T_2032 = shr(io.in.a.bits.source, 5) node _T_2033 = eq(_T_2032, UInt<4>(0hb)) node _T_2034 = leq(UInt<1>(0h0), uncommonBits_206) node _T_2035 = and(_T_2033, _T_2034) node _T_2036 = leq(uncommonBits_206, UInt<5>(0h1f)) node _T_2037 = and(_T_2035, _T_2036) node _uncommonBits_T_207 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_207 = bits(_uncommonBits_T_207, 4, 0) node _T_2038 = shr(io.in.a.bits.source, 5) node _T_2039 = eq(_T_2038, UInt<4>(0ha)) node _T_2040 = leq(UInt<1>(0h0), uncommonBits_207) node _T_2041 = and(_T_2039, _T_2040) node _T_2042 = leq(uncommonBits_207, UInt<5>(0h1f)) node _T_2043 = and(_T_2041, _T_2042) node _uncommonBits_T_208 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_208 = bits(_uncommonBits_T_208, 4, 0) node _T_2044 = shr(io.in.a.bits.source, 5) node _T_2045 = eq(_T_2044, UInt<4>(0h9)) node _T_2046 = leq(UInt<1>(0h0), uncommonBits_208) node _T_2047 = and(_T_2045, _T_2046) node _T_2048 = leq(uncommonBits_208, UInt<5>(0h1f)) node _T_2049 = and(_T_2047, _T_2048) node _uncommonBits_T_209 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_209 = bits(_uncommonBits_T_209, 4, 0) node _T_2050 = shr(io.in.a.bits.source, 5) node _T_2051 = eq(_T_2050, UInt<4>(0h8)) node _T_2052 = leq(UInt<1>(0h0), uncommonBits_209) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = leq(uncommonBits_209, UInt<5>(0h1f)) node _T_2055 = and(_T_2053, _T_2054) node _uncommonBits_T_210 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_210 = bits(_uncommonBits_T_210, 1, 0) node _T_2056 = shr(io.in.a.bits.source, 2) node _T_2057 = eq(_T_2056, UInt<7>(0h7a)) node _T_2058 = leq(UInt<1>(0h0), uncommonBits_210) node _T_2059 = and(_T_2057, _T_2058) node _T_2060 = leq(uncommonBits_210, UInt<2>(0h3)) node _T_2061 = and(_T_2059, _T_2060) node _uncommonBits_T_211 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_211 = bits(_uncommonBits_T_211, 1, 0) node _T_2062 = shr(io.in.a.bits.source, 2) node _T_2063 = eq(_T_2062, UInt<7>(0h79)) node _T_2064 = leq(UInt<1>(0h0), uncommonBits_211) node _T_2065 = and(_T_2063, _T_2064) node _T_2066 = leq(uncommonBits_211, UInt<2>(0h3)) node _T_2067 = and(_T_2065, _T_2066) node _uncommonBits_T_212 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_212 = bits(_uncommonBits_T_212, 4, 0) node _T_2068 = shr(io.in.a.bits.source, 5) node _T_2069 = eq(_T_2068, UInt<3>(0h7)) node _T_2070 = leq(UInt<1>(0h0), uncommonBits_212) node _T_2071 = and(_T_2069, _T_2070) node _T_2072 = leq(uncommonBits_212, UInt<5>(0h1f)) node _T_2073 = and(_T_2071, _T_2072) node _uncommonBits_T_213 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_213 = bits(_uncommonBits_T_213, 4, 0) node _T_2074 = shr(io.in.a.bits.source, 5) node _T_2075 = eq(_T_2074, UInt<3>(0h6)) node _T_2076 = leq(UInt<1>(0h0), uncommonBits_213) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = leq(uncommonBits_213, UInt<5>(0h1f)) node _T_2079 = and(_T_2077, _T_2078) node _uncommonBits_T_214 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_214 = bits(_uncommonBits_T_214, 4, 0) node _T_2080 = shr(io.in.a.bits.source, 5) node _T_2081 = eq(_T_2080, UInt<3>(0h5)) node _T_2082 = leq(UInt<1>(0h0), uncommonBits_214) node _T_2083 = and(_T_2081, _T_2082) node _T_2084 = leq(uncommonBits_214, UInt<5>(0h1f)) node _T_2085 = and(_T_2083, _T_2084) node _uncommonBits_T_215 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_215 = bits(_uncommonBits_T_215, 4, 0) node _T_2086 = shr(io.in.a.bits.source, 5) node _T_2087 = eq(_T_2086, UInt<3>(0h4)) node _T_2088 = leq(UInt<1>(0h0), uncommonBits_215) node _T_2089 = and(_T_2087, _T_2088) node _T_2090 = leq(uncommonBits_215, UInt<5>(0h1f)) node _T_2091 = and(_T_2089, _T_2090) node _uncommonBits_T_216 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_216 = bits(_uncommonBits_T_216, 4, 0) node _T_2092 = shr(io.in.a.bits.source, 5) node _T_2093 = eq(_T_2092, UInt<2>(0h3)) node _T_2094 = leq(UInt<1>(0h0), uncommonBits_216) node _T_2095 = and(_T_2093, _T_2094) node _T_2096 = leq(uncommonBits_216, UInt<5>(0h1f)) node _T_2097 = and(_T_2095, _T_2096) node _uncommonBits_T_217 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_217 = bits(_uncommonBits_T_217, 4, 0) node _T_2098 = shr(io.in.a.bits.source, 5) node _T_2099 = eq(_T_2098, UInt<2>(0h2)) node _T_2100 = leq(UInt<1>(0h0), uncommonBits_217) node _T_2101 = and(_T_2099, _T_2100) node _T_2102 = leq(uncommonBits_217, UInt<5>(0h1f)) node _T_2103 = and(_T_2101, _T_2102) node _uncommonBits_T_218 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_218 = bits(_uncommonBits_T_218, 4, 0) node _T_2104 = shr(io.in.a.bits.source, 5) node _T_2105 = eq(_T_2104, UInt<1>(0h1)) node _T_2106 = leq(UInt<1>(0h0), uncommonBits_218) node _T_2107 = and(_T_2105, _T_2106) node _T_2108 = leq(uncommonBits_218, UInt<5>(0h1f)) node _T_2109 = and(_T_2107, _T_2108) node _uncommonBits_T_219 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_219 = bits(_uncommonBits_T_219, 4, 0) node _T_2110 = shr(io.in.a.bits.source, 5) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) node _T_2112 = leq(UInt<1>(0h0), uncommonBits_219) node _T_2113 = and(_T_2111, _T_2112) node _T_2114 = leq(uncommonBits_219, UInt<5>(0h1f)) node _T_2115 = and(_T_2113, _T_2114) node _T_2116 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2117 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2118 = or(_T_1983, _T_1989) node _T_2119 = or(_T_2118, _T_1995) node _T_2120 = or(_T_2119, _T_2001) node _T_2121 = or(_T_2120, _T_2007) node _T_2122 = or(_T_2121, _T_2013) node _T_2123 = or(_T_2122, _T_2019) node _T_2124 = or(_T_2123, _T_2025) node _T_2125 = or(_T_2124, _T_2031) node _T_2126 = or(_T_2125, _T_2037) node _T_2127 = or(_T_2126, _T_2043) node _T_2128 = or(_T_2127, _T_2049) node _T_2129 = or(_T_2128, _T_2055) node _T_2130 = or(_T_2129, _T_2061) node _T_2131 = or(_T_2130, _T_2067) node _T_2132 = or(_T_2131, _T_2073) node _T_2133 = or(_T_2132, _T_2079) node _T_2134 = or(_T_2133, _T_2085) node _T_2135 = or(_T_2134, _T_2091) node _T_2136 = or(_T_2135, _T_2097) node _T_2137 = or(_T_2136, _T_2103) node _T_2138 = or(_T_2137, _T_2109) node _T_2139 = or(_T_2138, _T_2115) node _T_2140 = or(_T_2139, _T_2116) node _T_2141 = or(_T_2140, _T_2117) node _T_2142 = and(_T_1982, _T_2141) node _T_2143 = or(UInt<1>(0h0), _T_2142) node _T_2144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2145 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_2146 = and(_T_2144, _T_2145) node _T_2147 = or(UInt<1>(0h0), _T_2146) node _T_2148 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_2149 = cvt(_T_2148) node _T_2150 = and(_T_2149, asSInt(UInt<17>(0h10000))) node _T_2151 = asSInt(_T_2150) node _T_2152 = eq(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_2154 = cvt(_T_2153) node _T_2155 = and(_T_2154, asSInt(UInt<29>(0h10000000))) node _T_2156 = asSInt(_T_2155) node _T_2157 = eq(_T_2156, asSInt(UInt<1>(0h0))) node _T_2158 = or(_T_2152, _T_2157) node _T_2159 = and(_T_2147, _T_2158) node _T_2160 = or(UInt<1>(0h0), _T_2159) node _T_2161 = and(_T_2143, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_41 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(source_ok, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2168 = asUInt(reset) node _T_2169 = eq(_T_2168, UInt<1>(0h0)) when _T_2169 : node _T_2170 = eq(is_aligned, UInt<1>(0h0)) when _T_2170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2171 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_44 node _T_2175 = eq(io.in.a.bits.mask, mask) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_45 node _T_2179 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2179 : node _T_2180 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2181 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2182 = and(_T_2180, _T_2181) node _T_2183 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_220 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_220 = bits(_uncommonBits_T_220, 1, 0) node _T_2184 = shr(io.in.a.bits.source, 2) node _T_2185 = eq(_T_2184, UInt<7>(0h70)) node _T_2186 = leq(UInt<1>(0h0), uncommonBits_220) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = leq(uncommonBits_220, UInt<2>(0h3)) node _T_2189 = and(_T_2187, _T_2188) node _uncommonBits_T_221 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_221 = bits(_uncommonBits_T_221, 1, 0) node _T_2190 = shr(io.in.a.bits.source, 2) node _T_2191 = eq(_T_2190, UInt<7>(0h71)) node _T_2192 = leq(UInt<1>(0h0), uncommonBits_221) node _T_2193 = and(_T_2191, _T_2192) node _T_2194 = leq(uncommonBits_221, UInt<2>(0h3)) node _T_2195 = and(_T_2193, _T_2194) node _uncommonBits_T_222 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_222 = bits(_uncommonBits_T_222, 1, 0) node _T_2196 = shr(io.in.a.bits.source, 2) node _T_2197 = eq(_T_2196, UInt<7>(0h72)) node _T_2198 = leq(UInt<1>(0h0), uncommonBits_222) node _T_2199 = and(_T_2197, _T_2198) node _T_2200 = leq(uncommonBits_222, UInt<2>(0h3)) node _T_2201 = and(_T_2199, _T_2200) node _uncommonBits_T_223 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_223 = bits(_uncommonBits_T_223, 1, 0) node _T_2202 = shr(io.in.a.bits.source, 2) node _T_2203 = eq(_T_2202, UInt<7>(0h73)) node _T_2204 = leq(UInt<1>(0h0), uncommonBits_223) node _T_2205 = and(_T_2203, _T_2204) node _T_2206 = leq(uncommonBits_223, UInt<2>(0h3)) node _T_2207 = and(_T_2205, _T_2206) node _uncommonBits_T_224 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_224 = bits(_uncommonBits_T_224, 1, 0) node _T_2208 = shr(io.in.a.bits.source, 2) node _T_2209 = eq(_T_2208, UInt<7>(0h7c)) node _T_2210 = leq(UInt<1>(0h0), uncommonBits_224) node _T_2211 = and(_T_2209, _T_2210) node _T_2212 = leq(uncommonBits_224, UInt<2>(0h3)) node _T_2213 = and(_T_2211, _T_2212) node _uncommonBits_T_225 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_225 = bits(_uncommonBits_T_225, 1, 0) node _T_2214 = shr(io.in.a.bits.source, 2) node _T_2215 = eq(_T_2214, UInt<7>(0h7b)) node _T_2216 = leq(UInt<1>(0h0), uncommonBits_225) node _T_2217 = and(_T_2215, _T_2216) node _T_2218 = leq(uncommonBits_225, UInt<2>(0h3)) node _T_2219 = and(_T_2217, _T_2218) node _uncommonBits_T_226 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_226 = bits(_uncommonBits_T_226, 4, 0) node _T_2220 = shr(io.in.a.bits.source, 5) node _T_2221 = eq(_T_2220, UInt<4>(0hd)) node _T_2222 = leq(UInt<1>(0h0), uncommonBits_226) node _T_2223 = and(_T_2221, _T_2222) node _T_2224 = leq(uncommonBits_226, UInt<5>(0h1f)) node _T_2225 = and(_T_2223, _T_2224) node _uncommonBits_T_227 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_227 = bits(_uncommonBits_T_227, 4, 0) node _T_2226 = shr(io.in.a.bits.source, 5) node _T_2227 = eq(_T_2226, UInt<4>(0hc)) node _T_2228 = leq(UInt<1>(0h0), uncommonBits_227) node _T_2229 = and(_T_2227, _T_2228) node _T_2230 = leq(uncommonBits_227, UInt<5>(0h1f)) node _T_2231 = and(_T_2229, _T_2230) node _uncommonBits_T_228 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_228 = bits(_uncommonBits_T_228, 4, 0) node _T_2232 = shr(io.in.a.bits.source, 5) node _T_2233 = eq(_T_2232, UInt<4>(0hb)) node _T_2234 = leq(UInt<1>(0h0), uncommonBits_228) node _T_2235 = and(_T_2233, _T_2234) node _T_2236 = leq(uncommonBits_228, UInt<5>(0h1f)) node _T_2237 = and(_T_2235, _T_2236) node _uncommonBits_T_229 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_229 = bits(_uncommonBits_T_229, 4, 0) node _T_2238 = shr(io.in.a.bits.source, 5) node _T_2239 = eq(_T_2238, UInt<4>(0ha)) node _T_2240 = leq(UInt<1>(0h0), uncommonBits_229) node _T_2241 = and(_T_2239, _T_2240) node _T_2242 = leq(uncommonBits_229, UInt<5>(0h1f)) node _T_2243 = and(_T_2241, _T_2242) node _uncommonBits_T_230 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_230 = bits(_uncommonBits_T_230, 4, 0) node _T_2244 = shr(io.in.a.bits.source, 5) node _T_2245 = eq(_T_2244, UInt<4>(0h9)) node _T_2246 = leq(UInt<1>(0h0), uncommonBits_230) node _T_2247 = and(_T_2245, _T_2246) node _T_2248 = leq(uncommonBits_230, UInt<5>(0h1f)) node _T_2249 = and(_T_2247, _T_2248) node _uncommonBits_T_231 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_231 = bits(_uncommonBits_T_231, 4, 0) node _T_2250 = shr(io.in.a.bits.source, 5) node _T_2251 = eq(_T_2250, UInt<4>(0h8)) node _T_2252 = leq(UInt<1>(0h0), uncommonBits_231) node _T_2253 = and(_T_2251, _T_2252) node _T_2254 = leq(uncommonBits_231, UInt<5>(0h1f)) node _T_2255 = and(_T_2253, _T_2254) node _uncommonBits_T_232 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_232 = bits(_uncommonBits_T_232, 1, 0) node _T_2256 = shr(io.in.a.bits.source, 2) node _T_2257 = eq(_T_2256, UInt<7>(0h7a)) node _T_2258 = leq(UInt<1>(0h0), uncommonBits_232) node _T_2259 = and(_T_2257, _T_2258) node _T_2260 = leq(uncommonBits_232, UInt<2>(0h3)) node _T_2261 = and(_T_2259, _T_2260) node _uncommonBits_T_233 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_233 = bits(_uncommonBits_T_233, 1, 0) node _T_2262 = shr(io.in.a.bits.source, 2) node _T_2263 = eq(_T_2262, UInt<7>(0h79)) node _T_2264 = leq(UInt<1>(0h0), uncommonBits_233) node _T_2265 = and(_T_2263, _T_2264) node _T_2266 = leq(uncommonBits_233, UInt<2>(0h3)) node _T_2267 = and(_T_2265, _T_2266) node _uncommonBits_T_234 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_234 = bits(_uncommonBits_T_234, 4, 0) node _T_2268 = shr(io.in.a.bits.source, 5) node _T_2269 = eq(_T_2268, UInt<3>(0h7)) node _T_2270 = leq(UInt<1>(0h0), uncommonBits_234) node _T_2271 = and(_T_2269, _T_2270) node _T_2272 = leq(uncommonBits_234, UInt<5>(0h1f)) node _T_2273 = and(_T_2271, _T_2272) node _uncommonBits_T_235 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_235 = bits(_uncommonBits_T_235, 4, 0) node _T_2274 = shr(io.in.a.bits.source, 5) node _T_2275 = eq(_T_2274, UInt<3>(0h6)) node _T_2276 = leq(UInt<1>(0h0), uncommonBits_235) node _T_2277 = and(_T_2275, _T_2276) node _T_2278 = leq(uncommonBits_235, UInt<5>(0h1f)) node _T_2279 = and(_T_2277, _T_2278) node _uncommonBits_T_236 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_236 = bits(_uncommonBits_T_236, 4, 0) node _T_2280 = shr(io.in.a.bits.source, 5) node _T_2281 = eq(_T_2280, UInt<3>(0h5)) node _T_2282 = leq(UInt<1>(0h0), uncommonBits_236) node _T_2283 = and(_T_2281, _T_2282) node _T_2284 = leq(uncommonBits_236, UInt<5>(0h1f)) node _T_2285 = and(_T_2283, _T_2284) node _uncommonBits_T_237 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_237 = bits(_uncommonBits_T_237, 4, 0) node _T_2286 = shr(io.in.a.bits.source, 5) node _T_2287 = eq(_T_2286, UInt<3>(0h4)) node _T_2288 = leq(UInt<1>(0h0), uncommonBits_237) node _T_2289 = and(_T_2287, _T_2288) node _T_2290 = leq(uncommonBits_237, UInt<5>(0h1f)) node _T_2291 = and(_T_2289, _T_2290) node _uncommonBits_T_238 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_238 = bits(_uncommonBits_T_238, 4, 0) node _T_2292 = shr(io.in.a.bits.source, 5) node _T_2293 = eq(_T_2292, UInt<2>(0h3)) node _T_2294 = leq(UInt<1>(0h0), uncommonBits_238) node _T_2295 = and(_T_2293, _T_2294) node _T_2296 = leq(uncommonBits_238, UInt<5>(0h1f)) node _T_2297 = and(_T_2295, _T_2296) node _uncommonBits_T_239 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_239 = bits(_uncommonBits_T_239, 4, 0) node _T_2298 = shr(io.in.a.bits.source, 5) node _T_2299 = eq(_T_2298, UInt<2>(0h2)) node _T_2300 = leq(UInt<1>(0h0), uncommonBits_239) node _T_2301 = and(_T_2299, _T_2300) node _T_2302 = leq(uncommonBits_239, UInt<5>(0h1f)) node _T_2303 = and(_T_2301, _T_2302) node _uncommonBits_T_240 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_240 = bits(_uncommonBits_T_240, 4, 0) node _T_2304 = shr(io.in.a.bits.source, 5) node _T_2305 = eq(_T_2304, UInt<1>(0h1)) node _T_2306 = leq(UInt<1>(0h0), uncommonBits_240) node _T_2307 = and(_T_2305, _T_2306) node _T_2308 = leq(uncommonBits_240, UInt<5>(0h1f)) node _T_2309 = and(_T_2307, _T_2308) node _uncommonBits_T_241 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_241 = bits(_uncommonBits_T_241, 4, 0) node _T_2310 = shr(io.in.a.bits.source, 5) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) node _T_2312 = leq(UInt<1>(0h0), uncommonBits_241) node _T_2313 = and(_T_2311, _T_2312) node _T_2314 = leq(uncommonBits_241, UInt<5>(0h1f)) node _T_2315 = and(_T_2313, _T_2314) node _T_2316 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2317 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2318 = or(_T_2183, _T_2189) node _T_2319 = or(_T_2318, _T_2195) node _T_2320 = or(_T_2319, _T_2201) node _T_2321 = or(_T_2320, _T_2207) node _T_2322 = or(_T_2321, _T_2213) node _T_2323 = or(_T_2322, _T_2219) node _T_2324 = or(_T_2323, _T_2225) node _T_2325 = or(_T_2324, _T_2231) node _T_2326 = or(_T_2325, _T_2237) node _T_2327 = or(_T_2326, _T_2243) node _T_2328 = or(_T_2327, _T_2249) node _T_2329 = or(_T_2328, _T_2255) node _T_2330 = or(_T_2329, _T_2261) node _T_2331 = or(_T_2330, _T_2267) node _T_2332 = or(_T_2331, _T_2273) node _T_2333 = or(_T_2332, _T_2279) node _T_2334 = or(_T_2333, _T_2285) node _T_2335 = or(_T_2334, _T_2291) node _T_2336 = or(_T_2335, _T_2297) node _T_2337 = or(_T_2336, _T_2303) node _T_2338 = or(_T_2337, _T_2309) node _T_2339 = or(_T_2338, _T_2315) node _T_2340 = or(_T_2339, _T_2316) node _T_2341 = or(_T_2340, _T_2317) node _T_2342 = and(_T_2182, _T_2341) node _T_2343 = or(UInt<1>(0h0), _T_2342) node _T_2344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2345 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_2346 = and(_T_2344, _T_2345) node _T_2347 = or(UInt<1>(0h0), _T_2346) node _T_2348 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_2349 = cvt(_T_2348) node _T_2350 = and(_T_2349, asSInt(UInt<17>(0h10000))) node _T_2351 = asSInt(_T_2350) node _T_2352 = eq(_T_2351, asSInt(UInt<1>(0h0))) node _T_2353 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_2354 = cvt(_T_2353) node _T_2355 = and(_T_2354, asSInt(UInt<29>(0h10000000))) node _T_2356 = asSInt(_T_2355) node _T_2357 = eq(_T_2356, asSInt(UInt<1>(0h0))) node _T_2358 = or(_T_2352, _T_2357) node _T_2359 = and(_T_2347, _T_2358) node _T_2360 = or(UInt<1>(0h0), _T_2359) node _T_2361 = and(_T_2343, _T_2360) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_46 node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(source_ok, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(is_aligned, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2371 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_49 node _T_2375 = eq(io.in.a.bits.mask, mask) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_50 node _T_2379 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2383 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_52 node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 1, 0) node _source_ok_T_159 = shr(io.in.d.bits.source, 2) node _source_ok_T_160 = eq(_source_ok_T_159, UInt<7>(0h70)) node _source_ok_T_161 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_162 = and(_source_ok_T_160, _source_ok_T_161) node _source_ok_T_163 = leq(source_ok_uncommonBits_22, UInt<2>(0h3)) node _source_ok_T_164 = and(_source_ok_T_162, _source_ok_T_163) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 1, 0) node _source_ok_T_165 = shr(io.in.d.bits.source, 2) node _source_ok_T_166 = eq(_source_ok_T_165, UInt<7>(0h71)) node _source_ok_T_167 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167) node _source_ok_T_169 = leq(source_ok_uncommonBits_23, UInt<2>(0h3)) node _source_ok_T_170 = and(_source_ok_T_168, _source_ok_T_169) node _source_ok_uncommonBits_T_24 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_24 = bits(_source_ok_uncommonBits_T_24, 1, 0) node _source_ok_T_171 = shr(io.in.d.bits.source, 2) node _source_ok_T_172 = eq(_source_ok_T_171, UInt<7>(0h72)) node _source_ok_T_173 = leq(UInt<1>(0h0), source_ok_uncommonBits_24) node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173) node _source_ok_T_175 = leq(source_ok_uncommonBits_24, UInt<2>(0h3)) node _source_ok_T_176 = and(_source_ok_T_174, _source_ok_T_175) node _source_ok_uncommonBits_T_25 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_25 = bits(_source_ok_uncommonBits_T_25, 1, 0) node _source_ok_T_177 = shr(io.in.d.bits.source, 2) node _source_ok_T_178 = eq(_source_ok_T_177, UInt<7>(0h73)) node _source_ok_T_179 = leq(UInt<1>(0h0), source_ok_uncommonBits_25) node _source_ok_T_180 = and(_source_ok_T_178, _source_ok_T_179) node _source_ok_T_181 = leq(source_ok_uncommonBits_25, UInt<2>(0h3)) node _source_ok_T_182 = and(_source_ok_T_180, _source_ok_T_181) node _source_ok_uncommonBits_T_26 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_26 = bits(_source_ok_uncommonBits_T_26, 1, 0) node _source_ok_T_183 = shr(io.in.d.bits.source, 2) node _source_ok_T_184 = eq(_source_ok_T_183, UInt<7>(0h7c)) node _source_ok_T_185 = leq(UInt<1>(0h0), source_ok_uncommonBits_26) node _source_ok_T_186 = and(_source_ok_T_184, _source_ok_T_185) node _source_ok_T_187 = leq(source_ok_uncommonBits_26, UInt<2>(0h3)) node _source_ok_T_188 = and(_source_ok_T_186, _source_ok_T_187) node _source_ok_uncommonBits_T_27 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_27 = bits(_source_ok_uncommonBits_T_27, 1, 0) node _source_ok_T_189 = shr(io.in.d.bits.source, 2) node _source_ok_T_190 = eq(_source_ok_T_189, UInt<7>(0h7b)) node _source_ok_T_191 = leq(UInt<1>(0h0), source_ok_uncommonBits_27) node _source_ok_T_192 = and(_source_ok_T_190, _source_ok_T_191) node _source_ok_T_193 = leq(source_ok_uncommonBits_27, UInt<2>(0h3)) node _source_ok_T_194 = and(_source_ok_T_192, _source_ok_T_193) node _source_ok_uncommonBits_T_28 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_28 = bits(_source_ok_uncommonBits_T_28, 4, 0) node _source_ok_T_195 = shr(io.in.d.bits.source, 5) node _source_ok_T_196 = eq(_source_ok_T_195, UInt<4>(0hd)) node _source_ok_T_197 = leq(UInt<1>(0h0), source_ok_uncommonBits_28) node _source_ok_T_198 = and(_source_ok_T_196, _source_ok_T_197) node _source_ok_T_199 = leq(source_ok_uncommonBits_28, UInt<5>(0h1f)) node _source_ok_T_200 = and(_source_ok_T_198, _source_ok_T_199) node _source_ok_uncommonBits_T_29 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_29 = bits(_source_ok_uncommonBits_T_29, 4, 0) node _source_ok_T_201 = shr(io.in.d.bits.source, 5) node _source_ok_T_202 = eq(_source_ok_T_201, UInt<4>(0hc)) node _source_ok_T_203 = leq(UInt<1>(0h0), source_ok_uncommonBits_29) node _source_ok_T_204 = and(_source_ok_T_202, _source_ok_T_203) node _source_ok_T_205 = leq(source_ok_uncommonBits_29, UInt<5>(0h1f)) node _source_ok_T_206 = and(_source_ok_T_204, _source_ok_T_205) node _source_ok_uncommonBits_T_30 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_30 = bits(_source_ok_uncommonBits_T_30, 4, 0) node _source_ok_T_207 = shr(io.in.d.bits.source, 5) node _source_ok_T_208 = eq(_source_ok_T_207, UInt<4>(0hb)) node _source_ok_T_209 = leq(UInt<1>(0h0), source_ok_uncommonBits_30) node _source_ok_T_210 = and(_source_ok_T_208, _source_ok_T_209) node _source_ok_T_211 = leq(source_ok_uncommonBits_30, UInt<5>(0h1f)) node _source_ok_T_212 = and(_source_ok_T_210, _source_ok_T_211) node _source_ok_uncommonBits_T_31 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_31 = bits(_source_ok_uncommonBits_T_31, 4, 0) node _source_ok_T_213 = shr(io.in.d.bits.source, 5) node _source_ok_T_214 = eq(_source_ok_T_213, UInt<4>(0ha)) node _source_ok_T_215 = leq(UInt<1>(0h0), source_ok_uncommonBits_31) node _source_ok_T_216 = and(_source_ok_T_214, _source_ok_T_215) node _source_ok_T_217 = leq(source_ok_uncommonBits_31, UInt<5>(0h1f)) node _source_ok_T_218 = and(_source_ok_T_216, _source_ok_T_217) node _source_ok_uncommonBits_T_32 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_32 = bits(_source_ok_uncommonBits_T_32, 4, 0) node _source_ok_T_219 = shr(io.in.d.bits.source, 5) node _source_ok_T_220 = eq(_source_ok_T_219, UInt<4>(0h9)) node _source_ok_T_221 = leq(UInt<1>(0h0), source_ok_uncommonBits_32) node _source_ok_T_222 = and(_source_ok_T_220, _source_ok_T_221) node _source_ok_T_223 = leq(source_ok_uncommonBits_32, UInt<5>(0h1f)) node _source_ok_T_224 = and(_source_ok_T_222, _source_ok_T_223) node _source_ok_uncommonBits_T_33 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_33 = bits(_source_ok_uncommonBits_T_33, 4, 0) node _source_ok_T_225 = shr(io.in.d.bits.source, 5) node _source_ok_T_226 = eq(_source_ok_T_225, UInt<4>(0h8)) node _source_ok_T_227 = leq(UInt<1>(0h0), source_ok_uncommonBits_33) node _source_ok_T_228 = and(_source_ok_T_226, _source_ok_T_227) node _source_ok_T_229 = leq(source_ok_uncommonBits_33, UInt<5>(0h1f)) node _source_ok_T_230 = and(_source_ok_T_228, _source_ok_T_229) node _source_ok_uncommonBits_T_34 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_34 = bits(_source_ok_uncommonBits_T_34, 1, 0) node _source_ok_T_231 = shr(io.in.d.bits.source, 2) node _source_ok_T_232 = eq(_source_ok_T_231, UInt<7>(0h7a)) node _source_ok_T_233 = leq(UInt<1>(0h0), source_ok_uncommonBits_34) node _source_ok_T_234 = and(_source_ok_T_232, _source_ok_T_233) node _source_ok_T_235 = leq(source_ok_uncommonBits_34, UInt<2>(0h3)) node _source_ok_T_236 = and(_source_ok_T_234, _source_ok_T_235) node _source_ok_uncommonBits_T_35 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_35 = bits(_source_ok_uncommonBits_T_35, 1, 0) node _source_ok_T_237 = shr(io.in.d.bits.source, 2) node _source_ok_T_238 = eq(_source_ok_T_237, UInt<7>(0h79)) node _source_ok_T_239 = leq(UInt<1>(0h0), source_ok_uncommonBits_35) node _source_ok_T_240 = and(_source_ok_T_238, _source_ok_T_239) node _source_ok_T_241 = leq(source_ok_uncommonBits_35, UInt<2>(0h3)) node _source_ok_T_242 = and(_source_ok_T_240, _source_ok_T_241) node _source_ok_uncommonBits_T_36 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_36 = bits(_source_ok_uncommonBits_T_36, 4, 0) node _source_ok_T_243 = shr(io.in.d.bits.source, 5) node _source_ok_T_244 = eq(_source_ok_T_243, UInt<3>(0h7)) node _source_ok_T_245 = leq(UInt<1>(0h0), source_ok_uncommonBits_36) node _source_ok_T_246 = and(_source_ok_T_244, _source_ok_T_245) node _source_ok_T_247 = leq(source_ok_uncommonBits_36, UInt<5>(0h1f)) node _source_ok_T_248 = and(_source_ok_T_246, _source_ok_T_247) node _source_ok_uncommonBits_T_37 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_37 = bits(_source_ok_uncommonBits_T_37, 4, 0) node _source_ok_T_249 = shr(io.in.d.bits.source, 5) node _source_ok_T_250 = eq(_source_ok_T_249, UInt<3>(0h6)) node _source_ok_T_251 = leq(UInt<1>(0h0), source_ok_uncommonBits_37) node _source_ok_T_252 = and(_source_ok_T_250, _source_ok_T_251) node _source_ok_T_253 = leq(source_ok_uncommonBits_37, UInt<5>(0h1f)) node _source_ok_T_254 = and(_source_ok_T_252, _source_ok_T_253) node _source_ok_uncommonBits_T_38 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_38 = bits(_source_ok_uncommonBits_T_38, 4, 0) node _source_ok_T_255 = shr(io.in.d.bits.source, 5) node _source_ok_T_256 = eq(_source_ok_T_255, UInt<3>(0h5)) node _source_ok_T_257 = leq(UInt<1>(0h0), source_ok_uncommonBits_38) node _source_ok_T_258 = and(_source_ok_T_256, _source_ok_T_257) node _source_ok_T_259 = leq(source_ok_uncommonBits_38, UInt<5>(0h1f)) node _source_ok_T_260 = and(_source_ok_T_258, _source_ok_T_259) node _source_ok_uncommonBits_T_39 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_39 = bits(_source_ok_uncommonBits_T_39, 4, 0) node _source_ok_T_261 = shr(io.in.d.bits.source, 5) node _source_ok_T_262 = eq(_source_ok_T_261, UInt<3>(0h4)) node _source_ok_T_263 = leq(UInt<1>(0h0), source_ok_uncommonBits_39) node _source_ok_T_264 = and(_source_ok_T_262, _source_ok_T_263) node _source_ok_T_265 = leq(source_ok_uncommonBits_39, UInt<5>(0h1f)) node _source_ok_T_266 = and(_source_ok_T_264, _source_ok_T_265) node _source_ok_uncommonBits_T_40 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_40 = bits(_source_ok_uncommonBits_T_40, 4, 0) node _source_ok_T_267 = shr(io.in.d.bits.source, 5) node _source_ok_T_268 = eq(_source_ok_T_267, UInt<2>(0h3)) node _source_ok_T_269 = leq(UInt<1>(0h0), source_ok_uncommonBits_40) node _source_ok_T_270 = and(_source_ok_T_268, _source_ok_T_269) node _source_ok_T_271 = leq(source_ok_uncommonBits_40, UInt<5>(0h1f)) node _source_ok_T_272 = and(_source_ok_T_270, _source_ok_T_271) node _source_ok_uncommonBits_T_41 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_41 = bits(_source_ok_uncommonBits_T_41, 4, 0) node _source_ok_T_273 = shr(io.in.d.bits.source, 5) node _source_ok_T_274 = eq(_source_ok_T_273, UInt<2>(0h2)) node _source_ok_T_275 = leq(UInt<1>(0h0), source_ok_uncommonBits_41) node _source_ok_T_276 = and(_source_ok_T_274, _source_ok_T_275) node _source_ok_T_277 = leq(source_ok_uncommonBits_41, UInt<5>(0h1f)) node _source_ok_T_278 = and(_source_ok_T_276, _source_ok_T_277) node _source_ok_uncommonBits_T_42 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_42 = bits(_source_ok_uncommonBits_T_42, 4, 0) node _source_ok_T_279 = shr(io.in.d.bits.source, 5) node _source_ok_T_280 = eq(_source_ok_T_279, UInt<1>(0h1)) node _source_ok_T_281 = leq(UInt<1>(0h0), source_ok_uncommonBits_42) node _source_ok_T_282 = and(_source_ok_T_280, _source_ok_T_281) node _source_ok_T_283 = leq(source_ok_uncommonBits_42, UInt<5>(0h1f)) node _source_ok_T_284 = and(_source_ok_T_282, _source_ok_T_283) node _source_ok_uncommonBits_T_43 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_43 = bits(_source_ok_uncommonBits_T_43, 4, 0) node _source_ok_T_285 = shr(io.in.d.bits.source, 5) node _source_ok_T_286 = eq(_source_ok_T_285, UInt<1>(0h0)) node _source_ok_T_287 = leq(UInt<1>(0h0), source_ok_uncommonBits_43) node _source_ok_T_288 = and(_source_ok_T_286, _source_ok_T_287) node _source_ok_T_289 = leq(source_ok_uncommonBits_43, UInt<5>(0h1f)) node _source_ok_T_290 = and(_source_ok_T_288, _source_ok_T_289) node _source_ok_T_291 = eq(io.in.d.bits.source, UInt<9>(0h1e0)) node _source_ok_T_292 = eq(io.in.d.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE_1 : UInt<1>[25] connect _source_ok_WIRE_1[0], _source_ok_T_158 connect _source_ok_WIRE_1[1], _source_ok_T_164 connect _source_ok_WIRE_1[2], _source_ok_T_170 connect _source_ok_WIRE_1[3], _source_ok_T_176 connect _source_ok_WIRE_1[4], _source_ok_T_182 connect _source_ok_WIRE_1[5], _source_ok_T_188 connect _source_ok_WIRE_1[6], _source_ok_T_194 connect _source_ok_WIRE_1[7], _source_ok_T_200 connect _source_ok_WIRE_1[8], _source_ok_T_206 connect _source_ok_WIRE_1[9], _source_ok_T_212 connect _source_ok_WIRE_1[10], _source_ok_T_218 connect _source_ok_WIRE_1[11], _source_ok_T_224 connect _source_ok_WIRE_1[12], _source_ok_T_230 connect _source_ok_WIRE_1[13], _source_ok_T_236 connect _source_ok_WIRE_1[14], _source_ok_T_242 connect _source_ok_WIRE_1[15], _source_ok_T_248 connect _source_ok_WIRE_1[16], _source_ok_T_254 connect _source_ok_WIRE_1[17], _source_ok_T_260 connect _source_ok_WIRE_1[18], _source_ok_T_266 connect _source_ok_WIRE_1[19], _source_ok_T_272 connect _source_ok_WIRE_1[20], _source_ok_T_278 connect _source_ok_WIRE_1[21], _source_ok_T_284 connect _source_ok_WIRE_1[22], _source_ok_T_290 connect _source_ok_WIRE_1[23], _source_ok_T_291 connect _source_ok_WIRE_1[24], _source_ok_T_292 node _source_ok_T_293 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_294 = or(_source_ok_T_293, _source_ok_WIRE_1[2]) node _source_ok_T_295 = or(_source_ok_T_294, _source_ok_WIRE_1[3]) node _source_ok_T_296 = or(_source_ok_T_295, _source_ok_WIRE_1[4]) node _source_ok_T_297 = or(_source_ok_T_296, _source_ok_WIRE_1[5]) node _source_ok_T_298 = or(_source_ok_T_297, _source_ok_WIRE_1[6]) node _source_ok_T_299 = or(_source_ok_T_298, _source_ok_WIRE_1[7]) node _source_ok_T_300 = or(_source_ok_T_299, _source_ok_WIRE_1[8]) node _source_ok_T_301 = or(_source_ok_T_300, _source_ok_WIRE_1[9]) node _source_ok_T_302 = or(_source_ok_T_301, _source_ok_WIRE_1[10]) node _source_ok_T_303 = or(_source_ok_T_302, _source_ok_WIRE_1[11]) node _source_ok_T_304 = or(_source_ok_T_303, _source_ok_WIRE_1[12]) node _source_ok_T_305 = or(_source_ok_T_304, _source_ok_WIRE_1[13]) node _source_ok_T_306 = or(_source_ok_T_305, _source_ok_WIRE_1[14]) node _source_ok_T_307 = or(_source_ok_T_306, _source_ok_WIRE_1[15]) node _source_ok_T_308 = or(_source_ok_T_307, _source_ok_WIRE_1[16]) node _source_ok_T_309 = or(_source_ok_T_308, _source_ok_WIRE_1[17]) node _source_ok_T_310 = or(_source_ok_T_309, _source_ok_WIRE_1[18]) node _source_ok_T_311 = or(_source_ok_T_310, _source_ok_WIRE_1[19]) node _source_ok_T_312 = or(_source_ok_T_311, _source_ok_WIRE_1[20]) node _source_ok_T_313 = or(_source_ok_T_312, _source_ok_WIRE_1[21]) node _source_ok_T_314 = or(_source_ok_T_313, _source_ok_WIRE_1[22]) node _source_ok_T_315 = or(_source_ok_T_314, _source_ok_WIRE_1[23]) node source_ok_1 = or(_source_ok_T_315, _source_ok_WIRE_1[24]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_2387 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2387 : node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(source_ok_1, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2391 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_54 node _T_2395 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_55 node _T_2399 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_56 node _T_2403 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_57 node _T_2407 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2407 : node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(source_ok_1, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(sink_ok, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2414 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_60 node _T_2418 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2419 = asUInt(reset) node _T_2420 = eq(_T_2419, UInt<1>(0h0)) when _T_2420 : node _T_2421 = eq(_T_2418, UInt<1>(0h0)) when _T_2421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2418, UInt<1>(0h1), "") : assert_61 node _T_2422 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2423 = asUInt(reset) node _T_2424 = eq(_T_2423, UInt<1>(0h0)) when _T_2424 : node _T_2425 = eq(_T_2422, UInt<1>(0h0)) when _T_2425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2422, UInt<1>(0h1), "") : assert_62 node _T_2426 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(_T_2426, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2426, UInt<1>(0h1), "") : assert_63 node _T_2430 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2431 = or(UInt<1>(0h1), _T_2430) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_64 node _T_2435 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2435 : node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(source_ok_1, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(sink_ok, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2442 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_67 node _T_2446 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_68 node _T_2450 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2451 = asUInt(reset) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) when _T_2452 : node _T_2453 = eq(_T_2450, UInt<1>(0h0)) when _T_2453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2450, UInt<1>(0h1), "") : assert_69 node _T_2454 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2455 = or(_T_2454, io.in.d.bits.corrupt) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_70 node _T_2459 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2460 = or(UInt<1>(0h1), _T_2459) node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(_T_2460, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2460, UInt<1>(0h1), "") : assert_71 node _T_2464 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2464 : node _T_2465 = asUInt(reset) node _T_2466 = eq(_T_2465, UInt<1>(0h0)) when _T_2466 : node _T_2467 = eq(source_ok_1, UInt<1>(0h0)) when _T_2467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2468 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_73 node _T_2472 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_74 node _T_2476 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2477 = or(UInt<1>(0h1), _T_2476) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_75 node _T_2481 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2481 : node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(source_ok_1, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2485 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2486 = asUInt(reset) node _T_2487 = eq(_T_2486, UInt<1>(0h0)) when _T_2487 : node _T_2488 = eq(_T_2485, UInt<1>(0h0)) when _T_2488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2485, UInt<1>(0h1), "") : assert_77 node _T_2489 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2490 = or(_T_2489, io.in.d.bits.corrupt) node _T_2491 = asUInt(reset) node _T_2492 = eq(_T_2491, UInt<1>(0h0)) when _T_2492 : node _T_2493 = eq(_T_2490, UInt<1>(0h0)) when _T_2493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2490, UInt<1>(0h1), "") : assert_78 node _T_2494 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2495 = or(UInt<1>(0h1), _T_2494) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_79 node _T_2499 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2499 : node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(source_ok_1, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2503 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2504 = asUInt(reset) node _T_2505 = eq(_T_2504, UInt<1>(0h0)) when _T_2505 : node _T_2506 = eq(_T_2503, UInt<1>(0h0)) when _T_2506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2503, UInt<1>(0h1), "") : assert_81 node _T_2507 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2508 = asUInt(reset) node _T_2509 = eq(_T_2508, UInt<1>(0h0)) when _T_2509 : node _T_2510 = eq(_T_2507, UInt<1>(0h0)) when _T_2510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2507, UInt<1>(0h1), "") : assert_82 node _T_2511 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2512 = or(UInt<1>(0h1), _T_2511) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_2516 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_84 node _T_2520 = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) node _T_2522 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2523 = cvt(_T_2522) node _T_2524 = and(_T_2523, asSInt(UInt<1>(0h0))) node _T_2525 = asSInt(_T_2524) node _T_2526 = eq(_T_2525, asSInt(UInt<1>(0h0))) node _T_2527 = or(_T_2521, _T_2526) node _uncommonBits_T_242 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_242 = bits(_uncommonBits_T_242, 1, 0) node _T_2528 = shr(io.in.b.bits.source, 2) node _T_2529 = eq(_T_2528, UInt<7>(0h70)) node _T_2530 = leq(UInt<1>(0h0), uncommonBits_242) node _T_2531 = and(_T_2529, _T_2530) node _T_2532 = leq(uncommonBits_242, UInt<2>(0h3)) node _T_2533 = and(_T_2531, _T_2532) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2536 = cvt(_T_2535) node _T_2537 = and(_T_2536, asSInt(UInt<1>(0h0))) node _T_2538 = asSInt(_T_2537) node _T_2539 = eq(_T_2538, asSInt(UInt<1>(0h0))) node _T_2540 = or(_T_2534, _T_2539) node _uncommonBits_T_243 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_243 = bits(_uncommonBits_T_243, 1, 0) node _T_2541 = shr(io.in.b.bits.source, 2) node _T_2542 = eq(_T_2541, UInt<7>(0h71)) node _T_2543 = leq(UInt<1>(0h0), uncommonBits_243) node _T_2544 = and(_T_2542, _T_2543) node _T_2545 = leq(uncommonBits_243, UInt<2>(0h3)) node _T_2546 = and(_T_2544, _T_2545) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) node _T_2548 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2549 = cvt(_T_2548) node _T_2550 = and(_T_2549, asSInt(UInt<1>(0h0))) node _T_2551 = asSInt(_T_2550) node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0))) node _T_2553 = or(_T_2547, _T_2552) node _uncommonBits_T_244 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_244 = bits(_uncommonBits_T_244, 1, 0) node _T_2554 = shr(io.in.b.bits.source, 2) node _T_2555 = eq(_T_2554, UInt<7>(0h72)) node _T_2556 = leq(UInt<1>(0h0), uncommonBits_244) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = leq(uncommonBits_244, UInt<2>(0h3)) node _T_2559 = and(_T_2557, _T_2558) node _T_2560 = eq(_T_2559, UInt<1>(0h0)) node _T_2561 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2562 = cvt(_T_2561) node _T_2563 = and(_T_2562, asSInt(UInt<1>(0h0))) node _T_2564 = asSInt(_T_2563) node _T_2565 = eq(_T_2564, asSInt(UInt<1>(0h0))) node _T_2566 = or(_T_2560, _T_2565) node _uncommonBits_T_245 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_245 = bits(_uncommonBits_T_245, 1, 0) node _T_2567 = shr(io.in.b.bits.source, 2) node _T_2568 = eq(_T_2567, UInt<7>(0h73)) node _T_2569 = leq(UInt<1>(0h0), uncommonBits_245) node _T_2570 = and(_T_2568, _T_2569) node _T_2571 = leq(uncommonBits_245, UInt<2>(0h3)) node _T_2572 = and(_T_2570, _T_2571) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) node _T_2574 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2575 = cvt(_T_2574) node _T_2576 = and(_T_2575, asSInt(UInt<1>(0h0))) node _T_2577 = asSInt(_T_2576) node _T_2578 = eq(_T_2577, asSInt(UInt<1>(0h0))) node _T_2579 = or(_T_2573, _T_2578) node _uncommonBits_T_246 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_246 = bits(_uncommonBits_T_246, 1, 0) node _T_2580 = shr(io.in.b.bits.source, 2) node _T_2581 = eq(_T_2580, UInt<7>(0h7c)) node _T_2582 = leq(UInt<1>(0h0), uncommonBits_246) node _T_2583 = and(_T_2581, _T_2582) node _T_2584 = leq(uncommonBits_246, UInt<2>(0h3)) node _T_2585 = and(_T_2583, _T_2584) node _T_2586 = eq(_T_2585, UInt<1>(0h0)) node _T_2587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2588 = cvt(_T_2587) node _T_2589 = and(_T_2588, asSInt(UInt<1>(0h0))) node _T_2590 = asSInt(_T_2589) node _T_2591 = eq(_T_2590, asSInt(UInt<1>(0h0))) node _T_2592 = or(_T_2586, _T_2591) node _uncommonBits_T_247 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_247 = bits(_uncommonBits_T_247, 1, 0) node _T_2593 = shr(io.in.b.bits.source, 2) node _T_2594 = eq(_T_2593, UInt<7>(0h7b)) node _T_2595 = leq(UInt<1>(0h0), uncommonBits_247) node _T_2596 = and(_T_2594, _T_2595) node _T_2597 = leq(uncommonBits_247, UInt<2>(0h3)) node _T_2598 = and(_T_2596, _T_2597) node _T_2599 = eq(_T_2598, UInt<1>(0h0)) node _T_2600 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2601 = cvt(_T_2600) node _T_2602 = and(_T_2601, asSInt(UInt<1>(0h0))) node _T_2603 = asSInt(_T_2602) node _T_2604 = eq(_T_2603, asSInt(UInt<1>(0h0))) node _T_2605 = or(_T_2599, _T_2604) node _uncommonBits_T_248 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_248 = bits(_uncommonBits_T_248, 4, 0) node _T_2606 = shr(io.in.b.bits.source, 5) node _T_2607 = eq(_T_2606, UInt<4>(0hd)) node _T_2608 = leq(UInt<1>(0h0), uncommonBits_248) node _T_2609 = and(_T_2607, _T_2608) node _T_2610 = leq(uncommonBits_248, UInt<5>(0h1f)) node _T_2611 = and(_T_2609, _T_2610) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) node _T_2613 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2614 = cvt(_T_2613) node _T_2615 = and(_T_2614, asSInt(UInt<1>(0h0))) node _T_2616 = asSInt(_T_2615) node _T_2617 = eq(_T_2616, asSInt(UInt<1>(0h0))) node _T_2618 = or(_T_2612, _T_2617) node _uncommonBits_T_249 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_249 = bits(_uncommonBits_T_249, 4, 0) node _T_2619 = shr(io.in.b.bits.source, 5) node _T_2620 = eq(_T_2619, UInt<4>(0hc)) node _T_2621 = leq(UInt<1>(0h0), uncommonBits_249) node _T_2622 = and(_T_2620, _T_2621) node _T_2623 = leq(uncommonBits_249, UInt<5>(0h1f)) node _T_2624 = and(_T_2622, _T_2623) node _T_2625 = eq(_T_2624, UInt<1>(0h0)) node _T_2626 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2627 = cvt(_T_2626) node _T_2628 = and(_T_2627, asSInt(UInt<1>(0h0))) node _T_2629 = asSInt(_T_2628) node _T_2630 = eq(_T_2629, asSInt(UInt<1>(0h0))) node _T_2631 = or(_T_2625, _T_2630) node _uncommonBits_T_250 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_250 = bits(_uncommonBits_T_250, 4, 0) node _T_2632 = shr(io.in.b.bits.source, 5) node _T_2633 = eq(_T_2632, UInt<4>(0hb)) node _T_2634 = leq(UInt<1>(0h0), uncommonBits_250) node _T_2635 = and(_T_2633, _T_2634) node _T_2636 = leq(uncommonBits_250, UInt<5>(0h1f)) node _T_2637 = and(_T_2635, _T_2636) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) node _T_2639 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2640 = cvt(_T_2639) node _T_2641 = and(_T_2640, asSInt(UInt<1>(0h0))) node _T_2642 = asSInt(_T_2641) node _T_2643 = eq(_T_2642, asSInt(UInt<1>(0h0))) node _T_2644 = or(_T_2638, _T_2643) node _uncommonBits_T_251 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_251 = bits(_uncommonBits_T_251, 4, 0) node _T_2645 = shr(io.in.b.bits.source, 5) node _T_2646 = eq(_T_2645, UInt<4>(0ha)) node _T_2647 = leq(UInt<1>(0h0), uncommonBits_251) node _T_2648 = and(_T_2646, _T_2647) node _T_2649 = leq(uncommonBits_251, UInt<5>(0h1f)) node _T_2650 = and(_T_2648, _T_2649) node _T_2651 = eq(_T_2650, UInt<1>(0h0)) node _T_2652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2653 = cvt(_T_2652) node _T_2654 = and(_T_2653, asSInt(UInt<1>(0h0))) node _T_2655 = asSInt(_T_2654) node _T_2656 = eq(_T_2655, asSInt(UInt<1>(0h0))) node _T_2657 = or(_T_2651, _T_2656) node _uncommonBits_T_252 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_252 = bits(_uncommonBits_T_252, 4, 0) node _T_2658 = shr(io.in.b.bits.source, 5) node _T_2659 = eq(_T_2658, UInt<4>(0h9)) node _T_2660 = leq(UInt<1>(0h0), uncommonBits_252) node _T_2661 = and(_T_2659, _T_2660) node _T_2662 = leq(uncommonBits_252, UInt<5>(0h1f)) node _T_2663 = and(_T_2661, _T_2662) node _T_2664 = eq(_T_2663, UInt<1>(0h0)) node _T_2665 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2666 = cvt(_T_2665) node _T_2667 = and(_T_2666, asSInt(UInt<1>(0h0))) node _T_2668 = asSInt(_T_2667) node _T_2669 = eq(_T_2668, asSInt(UInt<1>(0h0))) node _T_2670 = or(_T_2664, _T_2669) node _uncommonBits_T_253 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_253 = bits(_uncommonBits_T_253, 4, 0) node _T_2671 = shr(io.in.b.bits.source, 5) node _T_2672 = eq(_T_2671, UInt<4>(0h8)) node _T_2673 = leq(UInt<1>(0h0), uncommonBits_253) node _T_2674 = and(_T_2672, _T_2673) node _T_2675 = leq(uncommonBits_253, UInt<5>(0h1f)) node _T_2676 = and(_T_2674, _T_2675) node _T_2677 = eq(_T_2676, UInt<1>(0h0)) node _T_2678 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2679 = cvt(_T_2678) node _T_2680 = and(_T_2679, asSInt(UInt<1>(0h0))) node _T_2681 = asSInt(_T_2680) node _T_2682 = eq(_T_2681, asSInt(UInt<1>(0h0))) node _T_2683 = or(_T_2677, _T_2682) node _uncommonBits_T_254 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_254 = bits(_uncommonBits_T_254, 1, 0) node _T_2684 = shr(io.in.b.bits.source, 2) node _T_2685 = eq(_T_2684, UInt<7>(0h7a)) node _T_2686 = leq(UInt<1>(0h0), uncommonBits_254) node _T_2687 = and(_T_2685, _T_2686) node _T_2688 = leq(uncommonBits_254, UInt<2>(0h3)) node _T_2689 = and(_T_2687, _T_2688) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) node _T_2691 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2692 = cvt(_T_2691) node _T_2693 = and(_T_2692, asSInt(UInt<1>(0h0))) node _T_2694 = asSInt(_T_2693) node _T_2695 = eq(_T_2694, asSInt(UInt<1>(0h0))) node _T_2696 = or(_T_2690, _T_2695) node _uncommonBits_T_255 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_255 = bits(_uncommonBits_T_255, 1, 0) node _T_2697 = shr(io.in.b.bits.source, 2) node _T_2698 = eq(_T_2697, UInt<7>(0h79)) node _T_2699 = leq(UInt<1>(0h0), uncommonBits_255) node _T_2700 = and(_T_2698, _T_2699) node _T_2701 = leq(uncommonBits_255, UInt<2>(0h3)) node _T_2702 = and(_T_2700, _T_2701) node _T_2703 = eq(_T_2702, UInt<1>(0h0)) node _T_2704 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2705 = cvt(_T_2704) node _T_2706 = and(_T_2705, asSInt(UInt<1>(0h0))) node _T_2707 = asSInt(_T_2706) node _T_2708 = eq(_T_2707, asSInt(UInt<1>(0h0))) node _T_2709 = or(_T_2703, _T_2708) node _uncommonBits_T_256 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_256 = bits(_uncommonBits_T_256, 4, 0) node _T_2710 = shr(io.in.b.bits.source, 5) node _T_2711 = eq(_T_2710, UInt<3>(0h7)) node _T_2712 = leq(UInt<1>(0h0), uncommonBits_256) node _T_2713 = and(_T_2711, _T_2712) node _T_2714 = leq(uncommonBits_256, UInt<5>(0h1f)) node _T_2715 = and(_T_2713, _T_2714) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) node _T_2717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2718 = cvt(_T_2717) node _T_2719 = and(_T_2718, asSInt(UInt<1>(0h0))) node _T_2720 = asSInt(_T_2719) node _T_2721 = eq(_T_2720, asSInt(UInt<1>(0h0))) node _T_2722 = or(_T_2716, _T_2721) node _uncommonBits_T_257 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_257 = bits(_uncommonBits_T_257, 4, 0) node _T_2723 = shr(io.in.b.bits.source, 5) node _T_2724 = eq(_T_2723, UInt<3>(0h6)) node _T_2725 = leq(UInt<1>(0h0), uncommonBits_257) node _T_2726 = and(_T_2724, _T_2725) node _T_2727 = leq(uncommonBits_257, UInt<5>(0h1f)) node _T_2728 = and(_T_2726, _T_2727) node _T_2729 = eq(_T_2728, UInt<1>(0h0)) node _T_2730 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2731 = cvt(_T_2730) node _T_2732 = and(_T_2731, asSInt(UInt<1>(0h0))) node _T_2733 = asSInt(_T_2732) node _T_2734 = eq(_T_2733, asSInt(UInt<1>(0h0))) node _T_2735 = or(_T_2729, _T_2734) node _uncommonBits_T_258 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_258 = bits(_uncommonBits_T_258, 4, 0) node _T_2736 = shr(io.in.b.bits.source, 5) node _T_2737 = eq(_T_2736, UInt<3>(0h5)) node _T_2738 = leq(UInt<1>(0h0), uncommonBits_258) node _T_2739 = and(_T_2737, _T_2738) node _T_2740 = leq(uncommonBits_258, UInt<5>(0h1f)) node _T_2741 = and(_T_2739, _T_2740) node _T_2742 = eq(_T_2741, UInt<1>(0h0)) node _T_2743 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2744 = cvt(_T_2743) node _T_2745 = and(_T_2744, asSInt(UInt<1>(0h0))) node _T_2746 = asSInt(_T_2745) node _T_2747 = eq(_T_2746, asSInt(UInt<1>(0h0))) node _T_2748 = or(_T_2742, _T_2747) node _uncommonBits_T_259 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_259 = bits(_uncommonBits_T_259, 4, 0) node _T_2749 = shr(io.in.b.bits.source, 5) node _T_2750 = eq(_T_2749, UInt<3>(0h4)) node _T_2751 = leq(UInt<1>(0h0), uncommonBits_259) node _T_2752 = and(_T_2750, _T_2751) node _T_2753 = leq(uncommonBits_259, UInt<5>(0h1f)) node _T_2754 = and(_T_2752, _T_2753) node _T_2755 = eq(_T_2754, UInt<1>(0h0)) node _T_2756 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2757 = cvt(_T_2756) node _T_2758 = and(_T_2757, asSInt(UInt<1>(0h0))) node _T_2759 = asSInt(_T_2758) node _T_2760 = eq(_T_2759, asSInt(UInt<1>(0h0))) node _T_2761 = or(_T_2755, _T_2760) node _uncommonBits_T_260 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_260 = bits(_uncommonBits_T_260, 4, 0) node _T_2762 = shr(io.in.b.bits.source, 5) node _T_2763 = eq(_T_2762, UInt<2>(0h3)) node _T_2764 = leq(UInt<1>(0h0), uncommonBits_260) node _T_2765 = and(_T_2763, _T_2764) node _T_2766 = leq(uncommonBits_260, UInt<5>(0h1f)) node _T_2767 = and(_T_2765, _T_2766) node _T_2768 = eq(_T_2767, UInt<1>(0h0)) node _T_2769 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2770 = cvt(_T_2769) node _T_2771 = and(_T_2770, asSInt(UInt<1>(0h0))) node _T_2772 = asSInt(_T_2771) node _T_2773 = eq(_T_2772, asSInt(UInt<1>(0h0))) node _T_2774 = or(_T_2768, _T_2773) node _uncommonBits_T_261 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_261 = bits(_uncommonBits_T_261, 4, 0) node _T_2775 = shr(io.in.b.bits.source, 5) node _T_2776 = eq(_T_2775, UInt<2>(0h2)) node _T_2777 = leq(UInt<1>(0h0), uncommonBits_261) node _T_2778 = and(_T_2776, _T_2777) node _T_2779 = leq(uncommonBits_261, UInt<5>(0h1f)) node _T_2780 = and(_T_2778, _T_2779) node _T_2781 = eq(_T_2780, UInt<1>(0h0)) node _T_2782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2783 = cvt(_T_2782) node _T_2784 = and(_T_2783, asSInt(UInt<1>(0h0))) node _T_2785 = asSInt(_T_2784) node _T_2786 = eq(_T_2785, asSInt(UInt<1>(0h0))) node _T_2787 = or(_T_2781, _T_2786) node _uncommonBits_T_262 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_262 = bits(_uncommonBits_T_262, 4, 0) node _T_2788 = shr(io.in.b.bits.source, 5) node _T_2789 = eq(_T_2788, UInt<1>(0h1)) node _T_2790 = leq(UInt<1>(0h0), uncommonBits_262) node _T_2791 = and(_T_2789, _T_2790) node _T_2792 = leq(uncommonBits_262, UInt<5>(0h1f)) node _T_2793 = and(_T_2791, _T_2792) node _T_2794 = eq(_T_2793, UInt<1>(0h0)) node _T_2795 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2796 = cvt(_T_2795) node _T_2797 = and(_T_2796, asSInt(UInt<1>(0h0))) node _T_2798 = asSInt(_T_2797) node _T_2799 = eq(_T_2798, asSInt(UInt<1>(0h0))) node _T_2800 = or(_T_2794, _T_2799) node _uncommonBits_T_263 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_263 = bits(_uncommonBits_T_263, 4, 0) node _T_2801 = shr(io.in.b.bits.source, 5) node _T_2802 = eq(_T_2801, UInt<1>(0h0)) node _T_2803 = leq(UInt<1>(0h0), uncommonBits_263) node _T_2804 = and(_T_2802, _T_2803) node _T_2805 = leq(uncommonBits_263, UInt<5>(0h1f)) node _T_2806 = and(_T_2804, _T_2805) node _T_2807 = eq(_T_2806, UInt<1>(0h0)) node _T_2808 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2809 = cvt(_T_2808) node _T_2810 = and(_T_2809, asSInt(UInt<1>(0h0))) node _T_2811 = asSInt(_T_2810) node _T_2812 = eq(_T_2811, asSInt(UInt<1>(0h0))) node _T_2813 = or(_T_2807, _T_2812) node _T_2814 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _T_2815 = eq(_T_2814, UInt<1>(0h0)) node _T_2816 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2817 = cvt(_T_2816) node _T_2818 = and(_T_2817, asSInt(UInt<1>(0h0))) node _T_2819 = asSInt(_T_2818) node _T_2820 = eq(_T_2819, asSInt(UInt<1>(0h0))) node _T_2821 = or(_T_2815, _T_2820) node _T_2822 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) node _T_2823 = eq(_T_2822, UInt<1>(0h0)) node _T_2824 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2825 = cvt(_T_2824) node _T_2826 = and(_T_2825, asSInt(UInt<1>(0h0))) node _T_2827 = asSInt(_T_2826) node _T_2828 = eq(_T_2827, asSInt(UInt<1>(0h0))) node _T_2829 = or(_T_2823, _T_2828) node _T_2830 = and(_T_2527, _T_2540) node _T_2831 = and(_T_2830, _T_2553) node _T_2832 = and(_T_2831, _T_2566) node _T_2833 = and(_T_2832, _T_2579) node _T_2834 = and(_T_2833, _T_2592) node _T_2835 = and(_T_2834, _T_2605) node _T_2836 = and(_T_2835, _T_2618) node _T_2837 = and(_T_2836, _T_2631) node _T_2838 = and(_T_2837, _T_2644) node _T_2839 = and(_T_2838, _T_2657) node _T_2840 = and(_T_2839, _T_2670) node _T_2841 = and(_T_2840, _T_2683) node _T_2842 = and(_T_2841, _T_2696) node _T_2843 = and(_T_2842, _T_2709) node _T_2844 = and(_T_2843, _T_2722) node _T_2845 = and(_T_2844, _T_2735) node _T_2846 = and(_T_2845, _T_2748) node _T_2847 = and(_T_2846, _T_2761) node _T_2848 = and(_T_2847, _T_2774) node _T_2849 = and(_T_2848, _T_2787) node _T_2850 = and(_T_2849, _T_2800) node _T_2851 = and(_T_2850, _T_2813) node _T_2852 = and(_T_2851, _T_2821) node _T_2853 = and(_T_2852, _T_2829) node _T_2854 = asUInt(reset) node _T_2855 = eq(_T_2854, UInt<1>(0h0)) when _T_2855 : node _T_2856 = eq(_T_2853, UInt<1>(0h0)) when _T_2856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2853, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<7>(0h70)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<7>(0h71)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<7>(0h72)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<7>(0h73)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 1, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 2) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<7>(0h7c)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<2>(0h3)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_uncommonBits_T_5 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_5 = bits(_legal_source_uncommonBits_T_5, 1, 0) node _legal_source_T_31 = shr(io.in.b.bits.source, 2) node _legal_source_T_32 = eq(_legal_source_T_31, UInt<7>(0h7b)) node _legal_source_T_33 = leq(UInt<1>(0h0), legal_source_uncommonBits_5) node _legal_source_T_34 = and(_legal_source_T_32, _legal_source_T_33) node _legal_source_T_35 = leq(legal_source_uncommonBits_5, UInt<2>(0h3)) node _legal_source_T_36 = and(_legal_source_T_34, _legal_source_T_35) node _legal_source_uncommonBits_T_6 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_6 = bits(_legal_source_uncommonBits_T_6, 4, 0) node _legal_source_T_37 = shr(io.in.b.bits.source, 5) node _legal_source_T_38 = eq(_legal_source_T_37, UInt<4>(0hd)) node _legal_source_T_39 = leq(UInt<1>(0h0), legal_source_uncommonBits_6) node _legal_source_T_40 = and(_legal_source_T_38, _legal_source_T_39) node _legal_source_T_41 = leq(legal_source_uncommonBits_6, UInt<5>(0h1f)) node _legal_source_T_42 = and(_legal_source_T_40, _legal_source_T_41) node _legal_source_uncommonBits_T_7 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_7 = bits(_legal_source_uncommonBits_T_7, 4, 0) node _legal_source_T_43 = shr(io.in.b.bits.source, 5) node _legal_source_T_44 = eq(_legal_source_T_43, UInt<4>(0hc)) node _legal_source_T_45 = leq(UInt<1>(0h0), legal_source_uncommonBits_7) node _legal_source_T_46 = and(_legal_source_T_44, _legal_source_T_45) node _legal_source_T_47 = leq(legal_source_uncommonBits_7, UInt<5>(0h1f)) node _legal_source_T_48 = and(_legal_source_T_46, _legal_source_T_47) node _legal_source_uncommonBits_T_8 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_8 = bits(_legal_source_uncommonBits_T_8, 4, 0) node _legal_source_T_49 = shr(io.in.b.bits.source, 5) node _legal_source_T_50 = eq(_legal_source_T_49, UInt<4>(0hb)) node _legal_source_T_51 = leq(UInt<1>(0h0), legal_source_uncommonBits_8) node _legal_source_T_52 = and(_legal_source_T_50, _legal_source_T_51) node _legal_source_T_53 = leq(legal_source_uncommonBits_8, UInt<5>(0h1f)) node _legal_source_T_54 = and(_legal_source_T_52, _legal_source_T_53) node _legal_source_uncommonBits_T_9 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_9 = bits(_legal_source_uncommonBits_T_9, 4, 0) node _legal_source_T_55 = shr(io.in.b.bits.source, 5) node _legal_source_T_56 = eq(_legal_source_T_55, UInt<4>(0ha)) node _legal_source_T_57 = leq(UInt<1>(0h0), legal_source_uncommonBits_9) node _legal_source_T_58 = and(_legal_source_T_56, _legal_source_T_57) node _legal_source_T_59 = leq(legal_source_uncommonBits_9, UInt<5>(0h1f)) node _legal_source_T_60 = and(_legal_source_T_58, _legal_source_T_59) node _legal_source_uncommonBits_T_10 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_10 = bits(_legal_source_uncommonBits_T_10, 4, 0) node _legal_source_T_61 = shr(io.in.b.bits.source, 5) node _legal_source_T_62 = eq(_legal_source_T_61, UInt<4>(0h9)) node _legal_source_T_63 = leq(UInt<1>(0h0), legal_source_uncommonBits_10) node _legal_source_T_64 = and(_legal_source_T_62, _legal_source_T_63) node _legal_source_T_65 = leq(legal_source_uncommonBits_10, UInt<5>(0h1f)) node _legal_source_T_66 = and(_legal_source_T_64, _legal_source_T_65) node _legal_source_uncommonBits_T_11 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_11 = bits(_legal_source_uncommonBits_T_11, 4, 0) node _legal_source_T_67 = shr(io.in.b.bits.source, 5) node _legal_source_T_68 = eq(_legal_source_T_67, UInt<4>(0h8)) node _legal_source_T_69 = leq(UInt<1>(0h0), legal_source_uncommonBits_11) node _legal_source_T_70 = and(_legal_source_T_68, _legal_source_T_69) node _legal_source_T_71 = leq(legal_source_uncommonBits_11, UInt<5>(0h1f)) node _legal_source_T_72 = and(_legal_source_T_70, _legal_source_T_71) node _legal_source_uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_12 = bits(_legal_source_uncommonBits_T_12, 1, 0) node _legal_source_T_73 = shr(io.in.b.bits.source, 2) node _legal_source_T_74 = eq(_legal_source_T_73, UInt<7>(0h7a)) node _legal_source_T_75 = leq(UInt<1>(0h0), legal_source_uncommonBits_12) node _legal_source_T_76 = and(_legal_source_T_74, _legal_source_T_75) node _legal_source_T_77 = leq(legal_source_uncommonBits_12, UInt<2>(0h3)) node _legal_source_T_78 = and(_legal_source_T_76, _legal_source_T_77) node _legal_source_uncommonBits_T_13 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_13 = bits(_legal_source_uncommonBits_T_13, 1, 0) node _legal_source_T_79 = shr(io.in.b.bits.source, 2) node _legal_source_T_80 = eq(_legal_source_T_79, UInt<7>(0h79)) node _legal_source_T_81 = leq(UInt<1>(0h0), legal_source_uncommonBits_13) node _legal_source_T_82 = and(_legal_source_T_80, _legal_source_T_81) node _legal_source_T_83 = leq(legal_source_uncommonBits_13, UInt<2>(0h3)) node _legal_source_T_84 = and(_legal_source_T_82, _legal_source_T_83) node _legal_source_uncommonBits_T_14 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_14 = bits(_legal_source_uncommonBits_T_14, 4, 0) node _legal_source_T_85 = shr(io.in.b.bits.source, 5) node _legal_source_T_86 = eq(_legal_source_T_85, UInt<3>(0h7)) node _legal_source_T_87 = leq(UInt<1>(0h0), legal_source_uncommonBits_14) node _legal_source_T_88 = and(_legal_source_T_86, _legal_source_T_87) node _legal_source_T_89 = leq(legal_source_uncommonBits_14, UInt<5>(0h1f)) node _legal_source_T_90 = and(_legal_source_T_88, _legal_source_T_89) node _legal_source_uncommonBits_T_15 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_15 = bits(_legal_source_uncommonBits_T_15, 4, 0) node _legal_source_T_91 = shr(io.in.b.bits.source, 5) node _legal_source_T_92 = eq(_legal_source_T_91, UInt<3>(0h6)) node _legal_source_T_93 = leq(UInt<1>(0h0), legal_source_uncommonBits_15) node _legal_source_T_94 = and(_legal_source_T_92, _legal_source_T_93) node _legal_source_T_95 = leq(legal_source_uncommonBits_15, UInt<5>(0h1f)) node _legal_source_T_96 = and(_legal_source_T_94, _legal_source_T_95) node _legal_source_uncommonBits_T_16 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_16 = bits(_legal_source_uncommonBits_T_16, 4, 0) node _legal_source_T_97 = shr(io.in.b.bits.source, 5) node _legal_source_T_98 = eq(_legal_source_T_97, UInt<3>(0h5)) node _legal_source_T_99 = leq(UInt<1>(0h0), legal_source_uncommonBits_16) node _legal_source_T_100 = and(_legal_source_T_98, _legal_source_T_99) node _legal_source_T_101 = leq(legal_source_uncommonBits_16, UInt<5>(0h1f)) node _legal_source_T_102 = and(_legal_source_T_100, _legal_source_T_101) node _legal_source_uncommonBits_T_17 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_17 = bits(_legal_source_uncommonBits_T_17, 4, 0) node _legal_source_T_103 = shr(io.in.b.bits.source, 5) node _legal_source_T_104 = eq(_legal_source_T_103, UInt<3>(0h4)) node _legal_source_T_105 = leq(UInt<1>(0h0), legal_source_uncommonBits_17) node _legal_source_T_106 = and(_legal_source_T_104, _legal_source_T_105) node _legal_source_T_107 = leq(legal_source_uncommonBits_17, UInt<5>(0h1f)) node _legal_source_T_108 = and(_legal_source_T_106, _legal_source_T_107) node _legal_source_uncommonBits_T_18 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_18 = bits(_legal_source_uncommonBits_T_18, 4, 0) node _legal_source_T_109 = shr(io.in.b.bits.source, 5) node _legal_source_T_110 = eq(_legal_source_T_109, UInt<2>(0h3)) node _legal_source_T_111 = leq(UInt<1>(0h0), legal_source_uncommonBits_18) node _legal_source_T_112 = and(_legal_source_T_110, _legal_source_T_111) node _legal_source_T_113 = leq(legal_source_uncommonBits_18, UInt<5>(0h1f)) node _legal_source_T_114 = and(_legal_source_T_112, _legal_source_T_113) node _legal_source_uncommonBits_T_19 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_19 = bits(_legal_source_uncommonBits_T_19, 4, 0) node _legal_source_T_115 = shr(io.in.b.bits.source, 5) node _legal_source_T_116 = eq(_legal_source_T_115, UInt<2>(0h2)) node _legal_source_T_117 = leq(UInt<1>(0h0), legal_source_uncommonBits_19) node _legal_source_T_118 = and(_legal_source_T_116, _legal_source_T_117) node _legal_source_T_119 = leq(legal_source_uncommonBits_19, UInt<5>(0h1f)) node _legal_source_T_120 = and(_legal_source_T_118, _legal_source_T_119) node _legal_source_uncommonBits_T_20 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_20 = bits(_legal_source_uncommonBits_T_20, 4, 0) node _legal_source_T_121 = shr(io.in.b.bits.source, 5) node _legal_source_T_122 = eq(_legal_source_T_121, UInt<1>(0h1)) node _legal_source_T_123 = leq(UInt<1>(0h0), legal_source_uncommonBits_20) node _legal_source_T_124 = and(_legal_source_T_122, _legal_source_T_123) node _legal_source_T_125 = leq(legal_source_uncommonBits_20, UInt<5>(0h1f)) node _legal_source_T_126 = and(_legal_source_T_124, _legal_source_T_125) node _legal_source_uncommonBits_T_21 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_21 = bits(_legal_source_uncommonBits_T_21, 4, 0) node _legal_source_T_127 = shr(io.in.b.bits.source, 5) node _legal_source_T_128 = eq(_legal_source_T_127, UInt<1>(0h0)) node _legal_source_T_129 = leq(UInt<1>(0h0), legal_source_uncommonBits_21) node _legal_source_T_130 = and(_legal_source_T_128, _legal_source_T_129) node _legal_source_T_131 = leq(legal_source_uncommonBits_21, UInt<5>(0h1f)) node _legal_source_T_132 = and(_legal_source_T_130, _legal_source_T_131) node _legal_source_T_133 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _legal_source_T_134 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) wire _legal_source_WIRE : UInt<1>[25] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_36 connect _legal_source_WIRE[7], _legal_source_T_42 connect _legal_source_WIRE[8], _legal_source_T_48 connect _legal_source_WIRE[9], _legal_source_T_54 connect _legal_source_WIRE[10], _legal_source_T_60 connect _legal_source_WIRE[11], _legal_source_T_66 connect _legal_source_WIRE[12], _legal_source_T_72 connect _legal_source_WIRE[13], _legal_source_T_78 connect _legal_source_WIRE[14], _legal_source_T_84 connect _legal_source_WIRE[15], _legal_source_T_90 connect _legal_source_WIRE[16], _legal_source_T_96 connect _legal_source_WIRE[17], _legal_source_T_102 connect _legal_source_WIRE[18], _legal_source_T_108 connect _legal_source_WIRE[19], _legal_source_T_114 connect _legal_source_WIRE[20], _legal_source_T_120 connect _legal_source_WIRE[21], _legal_source_T_126 connect _legal_source_WIRE[22], _legal_source_T_132 connect _legal_source_WIRE[23], _legal_source_T_133 connect _legal_source_WIRE[24], _legal_source_T_134 node _legal_source_T_135 = mux(_legal_source_WIRE[0], UInt<9>(0h1d0), UInt<1>(0h0)) node _legal_source_T_136 = mux(_legal_source_WIRE[1], UInt<9>(0h1c0), UInt<1>(0h0)) node _legal_source_T_137 = mux(_legal_source_WIRE[2], UInt<9>(0h1c4), UInt<1>(0h0)) node _legal_source_T_138 = mux(_legal_source_WIRE[3], UInt<9>(0h1c8), UInt<1>(0h0)) node _legal_source_T_139 = mux(_legal_source_WIRE[4], UInt<9>(0h1cc), UInt<1>(0h0)) node _legal_source_T_140 = mux(_legal_source_WIRE[5], UInt<9>(0h1f0), UInt<1>(0h0)) node _legal_source_T_141 = mux(_legal_source_WIRE[6], UInt<9>(0h1ec), UInt<1>(0h0)) node _legal_source_T_142 = mux(_legal_source_WIRE[7], UInt<9>(0h1a0), UInt<1>(0h0)) node _legal_source_T_143 = mux(_legal_source_WIRE[8], UInt<9>(0h180), UInt<1>(0h0)) node _legal_source_T_144 = mux(_legal_source_WIRE[9], UInt<9>(0h160), UInt<1>(0h0)) node _legal_source_T_145 = mux(_legal_source_WIRE[10], UInt<9>(0h140), UInt<1>(0h0)) node _legal_source_T_146 = mux(_legal_source_WIRE[11], UInt<9>(0h120), UInt<1>(0h0)) node _legal_source_T_147 = mux(_legal_source_WIRE[12], UInt<9>(0h100), UInt<1>(0h0)) node _legal_source_T_148 = mux(_legal_source_WIRE[13], UInt<9>(0h1e8), UInt<1>(0h0)) node _legal_source_T_149 = mux(_legal_source_WIRE[14], UInt<9>(0h1e4), UInt<1>(0h0)) node _legal_source_T_150 = mux(_legal_source_WIRE[15], UInt<8>(0he0), UInt<1>(0h0)) node _legal_source_T_151 = mux(_legal_source_WIRE[16], UInt<8>(0hc0), UInt<1>(0h0)) node _legal_source_T_152 = mux(_legal_source_WIRE[17], UInt<8>(0ha0), UInt<1>(0h0)) node _legal_source_T_153 = mux(_legal_source_WIRE[18], UInt<8>(0h80), UInt<1>(0h0)) node _legal_source_T_154 = mux(_legal_source_WIRE[19], UInt<7>(0h60), UInt<1>(0h0)) node _legal_source_T_155 = mux(_legal_source_WIRE[20], UInt<7>(0h40), UInt<1>(0h0)) node _legal_source_T_156 = mux(_legal_source_WIRE[21], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_157 = mux(_legal_source_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_158 = mux(_legal_source_WIRE[23], UInt<9>(0h1e0), UInt<1>(0h0)) node _legal_source_T_159 = mux(_legal_source_WIRE[24], UInt<9>(0h1e2), UInt<1>(0h0)) node _legal_source_T_160 = or(_legal_source_T_135, _legal_source_T_136) node _legal_source_T_161 = or(_legal_source_T_160, _legal_source_T_137) node _legal_source_T_162 = or(_legal_source_T_161, _legal_source_T_138) node _legal_source_T_163 = or(_legal_source_T_162, _legal_source_T_139) node _legal_source_T_164 = or(_legal_source_T_163, _legal_source_T_140) node _legal_source_T_165 = or(_legal_source_T_164, _legal_source_T_141) node _legal_source_T_166 = or(_legal_source_T_165, _legal_source_T_142) node _legal_source_T_167 = or(_legal_source_T_166, _legal_source_T_143) node _legal_source_T_168 = or(_legal_source_T_167, _legal_source_T_144) node _legal_source_T_169 = or(_legal_source_T_168, _legal_source_T_145) node _legal_source_T_170 = or(_legal_source_T_169, _legal_source_T_146) node _legal_source_T_171 = or(_legal_source_T_170, _legal_source_T_147) node _legal_source_T_172 = or(_legal_source_T_171, _legal_source_T_148) node _legal_source_T_173 = or(_legal_source_T_172, _legal_source_T_149) node _legal_source_T_174 = or(_legal_source_T_173, _legal_source_T_150) node _legal_source_T_175 = or(_legal_source_T_174, _legal_source_T_151) node _legal_source_T_176 = or(_legal_source_T_175, _legal_source_T_152) node _legal_source_T_177 = or(_legal_source_T_176, _legal_source_T_153) node _legal_source_T_178 = or(_legal_source_T_177, _legal_source_T_154) node _legal_source_T_179 = or(_legal_source_T_178, _legal_source_T_155) node _legal_source_T_180 = or(_legal_source_T_179, _legal_source_T_156) node _legal_source_T_181 = or(_legal_source_T_180, _legal_source_T_157) node _legal_source_T_182 = or(_legal_source_T_181, _legal_source_T_158) node _legal_source_T_183 = or(_legal_source_T_182, _legal_source_T_159) wire _legal_source_WIRE_1 : UInt<9> connect _legal_source_WIRE_1, _legal_source_T_183 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_2857 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_2857 : node _T_2858 = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_264 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_264 = bits(_uncommonBits_T_264, 1, 0) node _T_2859 = shr(io.in.b.bits.source, 2) node _T_2860 = eq(_T_2859, UInt<7>(0h70)) node _T_2861 = leq(UInt<1>(0h0), uncommonBits_264) node _T_2862 = and(_T_2860, _T_2861) node _T_2863 = leq(uncommonBits_264, UInt<2>(0h3)) node _T_2864 = and(_T_2862, _T_2863) node _uncommonBits_T_265 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_265 = bits(_uncommonBits_T_265, 1, 0) node _T_2865 = shr(io.in.b.bits.source, 2) node _T_2866 = eq(_T_2865, UInt<7>(0h71)) node _T_2867 = leq(UInt<1>(0h0), uncommonBits_265) node _T_2868 = and(_T_2866, _T_2867) node _T_2869 = leq(uncommonBits_265, UInt<2>(0h3)) node _T_2870 = and(_T_2868, _T_2869) node _uncommonBits_T_266 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_266 = bits(_uncommonBits_T_266, 1, 0) node _T_2871 = shr(io.in.b.bits.source, 2) node _T_2872 = eq(_T_2871, UInt<7>(0h72)) node _T_2873 = leq(UInt<1>(0h0), uncommonBits_266) node _T_2874 = and(_T_2872, _T_2873) node _T_2875 = leq(uncommonBits_266, UInt<2>(0h3)) node _T_2876 = and(_T_2874, _T_2875) node _uncommonBits_T_267 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_267 = bits(_uncommonBits_T_267, 1, 0) node _T_2877 = shr(io.in.b.bits.source, 2) node _T_2878 = eq(_T_2877, UInt<7>(0h73)) node _T_2879 = leq(UInt<1>(0h0), uncommonBits_267) node _T_2880 = and(_T_2878, _T_2879) node _T_2881 = leq(uncommonBits_267, UInt<2>(0h3)) node _T_2882 = and(_T_2880, _T_2881) node _uncommonBits_T_268 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_268 = bits(_uncommonBits_T_268, 1, 0) node _T_2883 = shr(io.in.b.bits.source, 2) node _T_2884 = eq(_T_2883, UInt<7>(0h7c)) node _T_2885 = leq(UInt<1>(0h0), uncommonBits_268) node _T_2886 = and(_T_2884, _T_2885) node _T_2887 = leq(uncommonBits_268, UInt<2>(0h3)) node _T_2888 = and(_T_2886, _T_2887) node _uncommonBits_T_269 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_269 = bits(_uncommonBits_T_269, 1, 0) node _T_2889 = shr(io.in.b.bits.source, 2) node _T_2890 = eq(_T_2889, UInt<7>(0h7b)) node _T_2891 = leq(UInt<1>(0h0), uncommonBits_269) node _T_2892 = and(_T_2890, _T_2891) node _T_2893 = leq(uncommonBits_269, UInt<2>(0h3)) node _T_2894 = and(_T_2892, _T_2893) node _uncommonBits_T_270 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_270 = bits(_uncommonBits_T_270, 4, 0) node _T_2895 = shr(io.in.b.bits.source, 5) node _T_2896 = eq(_T_2895, UInt<4>(0hd)) node _T_2897 = leq(UInt<1>(0h0), uncommonBits_270) node _T_2898 = and(_T_2896, _T_2897) node _T_2899 = leq(uncommonBits_270, UInt<5>(0h1f)) node _T_2900 = and(_T_2898, _T_2899) node _uncommonBits_T_271 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_271 = bits(_uncommonBits_T_271, 4, 0) node _T_2901 = shr(io.in.b.bits.source, 5) node _T_2902 = eq(_T_2901, UInt<4>(0hc)) node _T_2903 = leq(UInt<1>(0h0), uncommonBits_271) node _T_2904 = and(_T_2902, _T_2903) node _T_2905 = leq(uncommonBits_271, UInt<5>(0h1f)) node _T_2906 = and(_T_2904, _T_2905) node _uncommonBits_T_272 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_272 = bits(_uncommonBits_T_272, 4, 0) node _T_2907 = shr(io.in.b.bits.source, 5) node _T_2908 = eq(_T_2907, UInt<4>(0hb)) node _T_2909 = leq(UInt<1>(0h0), uncommonBits_272) node _T_2910 = and(_T_2908, _T_2909) node _T_2911 = leq(uncommonBits_272, UInt<5>(0h1f)) node _T_2912 = and(_T_2910, _T_2911) node _uncommonBits_T_273 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_273 = bits(_uncommonBits_T_273, 4, 0) node _T_2913 = shr(io.in.b.bits.source, 5) node _T_2914 = eq(_T_2913, UInt<4>(0ha)) node _T_2915 = leq(UInt<1>(0h0), uncommonBits_273) node _T_2916 = and(_T_2914, _T_2915) node _T_2917 = leq(uncommonBits_273, UInt<5>(0h1f)) node _T_2918 = and(_T_2916, _T_2917) node _uncommonBits_T_274 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_274 = bits(_uncommonBits_T_274, 4, 0) node _T_2919 = shr(io.in.b.bits.source, 5) node _T_2920 = eq(_T_2919, UInt<4>(0h9)) node _T_2921 = leq(UInt<1>(0h0), uncommonBits_274) node _T_2922 = and(_T_2920, _T_2921) node _T_2923 = leq(uncommonBits_274, UInt<5>(0h1f)) node _T_2924 = and(_T_2922, _T_2923) node _uncommonBits_T_275 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_275 = bits(_uncommonBits_T_275, 4, 0) node _T_2925 = shr(io.in.b.bits.source, 5) node _T_2926 = eq(_T_2925, UInt<4>(0h8)) node _T_2927 = leq(UInt<1>(0h0), uncommonBits_275) node _T_2928 = and(_T_2926, _T_2927) node _T_2929 = leq(uncommonBits_275, UInt<5>(0h1f)) node _T_2930 = and(_T_2928, _T_2929) node _uncommonBits_T_276 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_276 = bits(_uncommonBits_T_276, 1, 0) node _T_2931 = shr(io.in.b.bits.source, 2) node _T_2932 = eq(_T_2931, UInt<7>(0h7a)) node _T_2933 = leq(UInt<1>(0h0), uncommonBits_276) node _T_2934 = and(_T_2932, _T_2933) node _T_2935 = leq(uncommonBits_276, UInt<2>(0h3)) node _T_2936 = and(_T_2934, _T_2935) node _uncommonBits_T_277 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_277 = bits(_uncommonBits_T_277, 1, 0) node _T_2937 = shr(io.in.b.bits.source, 2) node _T_2938 = eq(_T_2937, UInt<7>(0h79)) node _T_2939 = leq(UInt<1>(0h0), uncommonBits_277) node _T_2940 = and(_T_2938, _T_2939) node _T_2941 = leq(uncommonBits_277, UInt<2>(0h3)) node _T_2942 = and(_T_2940, _T_2941) node _uncommonBits_T_278 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_278 = bits(_uncommonBits_T_278, 4, 0) node _T_2943 = shr(io.in.b.bits.source, 5) node _T_2944 = eq(_T_2943, UInt<3>(0h7)) node _T_2945 = leq(UInt<1>(0h0), uncommonBits_278) node _T_2946 = and(_T_2944, _T_2945) node _T_2947 = leq(uncommonBits_278, UInt<5>(0h1f)) node _T_2948 = and(_T_2946, _T_2947) node _uncommonBits_T_279 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_279 = bits(_uncommonBits_T_279, 4, 0) node _T_2949 = shr(io.in.b.bits.source, 5) node _T_2950 = eq(_T_2949, UInt<3>(0h6)) node _T_2951 = leq(UInt<1>(0h0), uncommonBits_279) node _T_2952 = and(_T_2950, _T_2951) node _T_2953 = leq(uncommonBits_279, UInt<5>(0h1f)) node _T_2954 = and(_T_2952, _T_2953) node _uncommonBits_T_280 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_280 = bits(_uncommonBits_T_280, 4, 0) node _T_2955 = shr(io.in.b.bits.source, 5) node _T_2956 = eq(_T_2955, UInt<3>(0h5)) node _T_2957 = leq(UInt<1>(0h0), uncommonBits_280) node _T_2958 = and(_T_2956, _T_2957) node _T_2959 = leq(uncommonBits_280, UInt<5>(0h1f)) node _T_2960 = and(_T_2958, _T_2959) node _uncommonBits_T_281 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_281 = bits(_uncommonBits_T_281, 4, 0) node _T_2961 = shr(io.in.b.bits.source, 5) node _T_2962 = eq(_T_2961, UInt<3>(0h4)) node _T_2963 = leq(UInt<1>(0h0), uncommonBits_281) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = leq(uncommonBits_281, UInt<5>(0h1f)) node _T_2966 = and(_T_2964, _T_2965) node _uncommonBits_T_282 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_282 = bits(_uncommonBits_T_282, 4, 0) node _T_2967 = shr(io.in.b.bits.source, 5) node _T_2968 = eq(_T_2967, UInt<2>(0h3)) node _T_2969 = leq(UInt<1>(0h0), uncommonBits_282) node _T_2970 = and(_T_2968, _T_2969) node _T_2971 = leq(uncommonBits_282, UInt<5>(0h1f)) node _T_2972 = and(_T_2970, _T_2971) node _uncommonBits_T_283 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_283 = bits(_uncommonBits_T_283, 4, 0) node _T_2973 = shr(io.in.b.bits.source, 5) node _T_2974 = eq(_T_2973, UInt<2>(0h2)) node _T_2975 = leq(UInt<1>(0h0), uncommonBits_283) node _T_2976 = and(_T_2974, _T_2975) node _T_2977 = leq(uncommonBits_283, UInt<5>(0h1f)) node _T_2978 = and(_T_2976, _T_2977) node _uncommonBits_T_284 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_284 = bits(_uncommonBits_T_284, 4, 0) node _T_2979 = shr(io.in.b.bits.source, 5) node _T_2980 = eq(_T_2979, UInt<1>(0h1)) node _T_2981 = leq(UInt<1>(0h0), uncommonBits_284) node _T_2982 = and(_T_2980, _T_2981) node _T_2983 = leq(uncommonBits_284, UInt<5>(0h1f)) node _T_2984 = and(_T_2982, _T_2983) node _uncommonBits_T_285 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_285 = bits(_uncommonBits_T_285, 4, 0) node _T_2985 = shr(io.in.b.bits.source, 5) node _T_2986 = eq(_T_2985, UInt<1>(0h0)) node _T_2987 = leq(UInt<1>(0h0), uncommonBits_285) node _T_2988 = and(_T_2986, _T_2987) node _T_2989 = leq(uncommonBits_285, UInt<5>(0h1f)) node _T_2990 = and(_T_2988, _T_2989) node _T_2991 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _T_2992 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) wire _WIRE_4 : UInt<1>[25] connect _WIRE_4[0], _T_2858 connect _WIRE_4[1], _T_2864 connect _WIRE_4[2], _T_2870 connect _WIRE_4[3], _T_2876 connect _WIRE_4[4], _T_2882 connect _WIRE_4[5], _T_2888 connect _WIRE_4[6], _T_2894 connect _WIRE_4[7], _T_2900 connect _WIRE_4[8], _T_2906 connect _WIRE_4[9], _T_2912 connect _WIRE_4[10], _T_2918 connect _WIRE_4[11], _T_2924 connect _WIRE_4[12], _T_2930 connect _WIRE_4[13], _T_2936 connect _WIRE_4[14], _T_2942 connect _WIRE_4[15], _T_2948 connect _WIRE_4[16], _T_2954 connect _WIRE_4[17], _T_2960 connect _WIRE_4[18], _T_2966 connect _WIRE_4[19], _T_2972 connect _WIRE_4[20], _T_2978 connect _WIRE_4[21], _T_2984 connect _WIRE_4[22], _T_2990 connect _WIRE_4[23], _T_2991 connect _WIRE_4[24], _T_2992 node _T_2993 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2994 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2995 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2996 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2997 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2998 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2999 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_3000 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_3001 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_3002 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_3003 = mux(_WIRE_4[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_3004 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_3005 = mux(_WIRE_4[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_3006 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_3007 = mux(_WIRE_4[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_3008 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_3009 = mux(_WIRE_4[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_3010 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_3011 = mux(_WIRE_4[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_3012 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_3013 = mux(_WIRE_4[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_3014 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_3015 = mux(_WIRE_4[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_3016 = mux(_WIRE_4[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_3017 = mux(_WIRE_4[23], _T_2993, UInt<1>(0h0)) node _T_3018 = mux(_WIRE_4[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_3019 = or(_T_2994, _T_2995) node _T_3020 = or(_T_3019, _T_2996) node _T_3021 = or(_T_3020, _T_2997) node _T_3022 = or(_T_3021, _T_2998) node _T_3023 = or(_T_3022, _T_2999) node _T_3024 = or(_T_3023, _T_3000) node _T_3025 = or(_T_3024, _T_3001) node _T_3026 = or(_T_3025, _T_3002) node _T_3027 = or(_T_3026, _T_3003) node _T_3028 = or(_T_3027, _T_3004) node _T_3029 = or(_T_3028, _T_3005) node _T_3030 = or(_T_3029, _T_3006) node _T_3031 = or(_T_3030, _T_3007) node _T_3032 = or(_T_3031, _T_3008) node _T_3033 = or(_T_3032, _T_3009) node _T_3034 = or(_T_3033, _T_3010) node _T_3035 = or(_T_3034, _T_3011) node _T_3036 = or(_T_3035, _T_3012) node _T_3037 = or(_T_3036, _T_3013) node _T_3038 = or(_T_3037, _T_3014) node _T_3039 = or(_T_3038, _T_3015) node _T_3040 = or(_T_3039, _T_3016) node _T_3041 = or(_T_3040, _T_3017) node _T_3042 = or(_T_3041, _T_3018) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_3042 node _T_3043 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3044 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3045 = and(_T_3043, _T_3044) node _T_3046 = or(UInt<1>(0h0), _T_3045) node _T_3047 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3048 = cvt(_T_3047) node _T_3049 = and(_T_3048, asSInt(UInt<17>(0h10000))) node _T_3050 = asSInt(_T_3049) node _T_3051 = eq(_T_3050, asSInt(UInt<1>(0h0))) node _T_3052 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3053 = cvt(_T_3052) node _T_3054 = and(_T_3053, asSInt(UInt<29>(0h10000000))) node _T_3055 = asSInt(_T_3054) node _T_3056 = eq(_T_3055, asSInt(UInt<1>(0h0))) node _T_3057 = or(_T_3051, _T_3056) node _T_3058 = and(_T_3046, _T_3057) node _T_3059 = or(UInt<1>(0h0), _T_3058) node _T_3060 = and(_WIRE_5, _T_3059) node _T_3061 = asUInt(reset) node _T_3062 = eq(_T_3061, UInt<1>(0h0)) when _T_3062 : node _T_3063 = eq(_T_3060, UInt<1>(0h0)) when _T_3063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_3060, UInt<1>(0h1), "") : assert_86 node _T_3064 = asUInt(reset) node _T_3065 = eq(_T_3064, UInt<1>(0h0)) when _T_3065 : node _T_3066 = eq(address_ok, UInt<1>(0h0)) when _T_3066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_3067 = asUInt(reset) node _T_3068 = eq(_T_3067, UInt<1>(0h0)) when _T_3068 : node _T_3069 = eq(legal_source, UInt<1>(0h0)) when _T_3069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_3070 = asUInt(reset) node _T_3071 = eq(_T_3070, UInt<1>(0h0)) when _T_3071 : node _T_3072 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_3073 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_3074 = asUInt(reset) node _T_3075 = eq(_T_3074, UInt<1>(0h0)) when _T_3075 : node _T_3076 = eq(_T_3073, UInt<1>(0h0)) when _T_3076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_3073, UInt<1>(0h1), "") : assert_90 node _T_3077 = eq(io.in.b.bits.mask, mask_1) node _T_3078 = asUInt(reset) node _T_3079 = eq(_T_3078, UInt<1>(0h0)) when _T_3079 : node _T_3080 = eq(_T_3077, UInt<1>(0h0)) when _T_3080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_3077, UInt<1>(0h1), "") : assert_91 node _T_3081 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3082 = asUInt(reset) node _T_3083 = eq(_T_3082, UInt<1>(0h0)) when _T_3083 : node _T_3084 = eq(_T_3081, UInt<1>(0h0)) when _T_3084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_3081, UInt<1>(0h1), "") : assert_92 node _T_3085 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_3085 : node _T_3086 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3087 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3088 = and(_T_3086, _T_3087) node _T_3089 = or(UInt<1>(0h0), _T_3088) node _T_3090 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3091 = cvt(_T_3090) node _T_3092 = and(_T_3091, asSInt(UInt<17>(0h10000))) node _T_3093 = asSInt(_T_3092) node _T_3094 = eq(_T_3093, asSInt(UInt<1>(0h0))) node _T_3095 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3096 = cvt(_T_3095) node _T_3097 = and(_T_3096, asSInt(UInt<29>(0h10000000))) node _T_3098 = asSInt(_T_3097) node _T_3099 = eq(_T_3098, asSInt(UInt<1>(0h0))) node _T_3100 = or(_T_3094, _T_3099) node _T_3101 = and(_T_3089, _T_3100) node _T_3102 = or(UInt<1>(0h0), _T_3101) node _T_3103 = and(UInt<1>(0h0), _T_3102) node _T_3104 = asUInt(reset) node _T_3105 = eq(_T_3104, UInt<1>(0h0)) when _T_3105 : node _T_3106 = eq(_T_3103, UInt<1>(0h0)) when _T_3106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_3103, UInt<1>(0h1), "") : assert_93 node _T_3107 = asUInt(reset) node _T_3108 = eq(_T_3107, UInt<1>(0h0)) when _T_3108 : node _T_3109 = eq(address_ok, UInt<1>(0h0)) when _T_3109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_3110 = asUInt(reset) node _T_3111 = eq(_T_3110, UInt<1>(0h0)) when _T_3111 : node _T_3112 = eq(legal_source, UInt<1>(0h0)) when _T_3112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_3113 = asUInt(reset) node _T_3114 = eq(_T_3113, UInt<1>(0h0)) when _T_3114 : node _T_3115 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_3116 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3117 = asUInt(reset) node _T_3118 = eq(_T_3117, UInt<1>(0h0)) when _T_3118 : node _T_3119 = eq(_T_3116, UInt<1>(0h0)) when _T_3119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_3116, UInt<1>(0h1), "") : assert_97 node _T_3120 = eq(io.in.b.bits.mask, mask_1) node _T_3121 = asUInt(reset) node _T_3122 = eq(_T_3121, UInt<1>(0h0)) when _T_3122 : node _T_3123 = eq(_T_3120, UInt<1>(0h0)) when _T_3123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_3120, UInt<1>(0h1), "") : assert_98 node _T_3124 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3125 = asUInt(reset) node _T_3126 = eq(_T_3125, UInt<1>(0h0)) when _T_3126 : node _T_3127 = eq(_T_3124, UInt<1>(0h0)) when _T_3127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_3124, UInt<1>(0h1), "") : assert_99 node _T_3128 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_3128 : node _T_3129 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3130 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3131 = and(_T_3129, _T_3130) node _T_3132 = or(UInt<1>(0h0), _T_3131) node _T_3133 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3134 = cvt(_T_3133) node _T_3135 = and(_T_3134, asSInt(UInt<17>(0h10000))) node _T_3136 = asSInt(_T_3135) node _T_3137 = eq(_T_3136, asSInt(UInt<1>(0h0))) node _T_3138 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3139 = cvt(_T_3138) node _T_3140 = and(_T_3139, asSInt(UInt<29>(0h10000000))) node _T_3141 = asSInt(_T_3140) node _T_3142 = eq(_T_3141, asSInt(UInt<1>(0h0))) node _T_3143 = or(_T_3137, _T_3142) node _T_3144 = and(_T_3132, _T_3143) node _T_3145 = or(UInt<1>(0h0), _T_3144) node _T_3146 = and(UInt<1>(0h0), _T_3145) node _T_3147 = asUInt(reset) node _T_3148 = eq(_T_3147, UInt<1>(0h0)) when _T_3148 : node _T_3149 = eq(_T_3146, UInt<1>(0h0)) when _T_3149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_3146, UInt<1>(0h1), "") : assert_100 node _T_3150 = asUInt(reset) node _T_3151 = eq(_T_3150, UInt<1>(0h0)) when _T_3151 : node _T_3152 = eq(address_ok, UInt<1>(0h0)) when _T_3152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_3153 = asUInt(reset) node _T_3154 = eq(_T_3153, UInt<1>(0h0)) when _T_3154 : node _T_3155 = eq(legal_source, UInt<1>(0h0)) when _T_3155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_3156 = asUInt(reset) node _T_3157 = eq(_T_3156, UInt<1>(0h0)) when _T_3157 : node _T_3158 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_3159 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3160 = asUInt(reset) node _T_3161 = eq(_T_3160, UInt<1>(0h0)) when _T_3161 : node _T_3162 = eq(_T_3159, UInt<1>(0h0)) when _T_3162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_3159, UInt<1>(0h1), "") : assert_104 node _T_3163 = eq(io.in.b.bits.mask, mask_1) node _T_3164 = asUInt(reset) node _T_3165 = eq(_T_3164, UInt<1>(0h0)) when _T_3165 : node _T_3166 = eq(_T_3163, UInt<1>(0h0)) when _T_3166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_3163, UInt<1>(0h1), "") : assert_105 node _T_3167 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_3167 : node _T_3168 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3169 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3170 = and(_T_3168, _T_3169) node _T_3171 = or(UInt<1>(0h0), _T_3170) node _T_3172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3173 = cvt(_T_3172) node _T_3174 = and(_T_3173, asSInt(UInt<17>(0h10000))) node _T_3175 = asSInt(_T_3174) node _T_3176 = eq(_T_3175, asSInt(UInt<1>(0h0))) node _T_3177 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3178 = cvt(_T_3177) node _T_3179 = and(_T_3178, asSInt(UInt<29>(0h10000000))) node _T_3180 = asSInt(_T_3179) node _T_3181 = eq(_T_3180, asSInt(UInt<1>(0h0))) node _T_3182 = or(_T_3176, _T_3181) node _T_3183 = and(_T_3171, _T_3182) node _T_3184 = or(UInt<1>(0h0), _T_3183) node _T_3185 = and(UInt<1>(0h0), _T_3184) node _T_3186 = asUInt(reset) node _T_3187 = eq(_T_3186, UInt<1>(0h0)) when _T_3187 : node _T_3188 = eq(_T_3185, UInt<1>(0h0)) when _T_3188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_3185, UInt<1>(0h1), "") : assert_106 node _T_3189 = asUInt(reset) node _T_3190 = eq(_T_3189, UInt<1>(0h0)) when _T_3190 : node _T_3191 = eq(address_ok, UInt<1>(0h0)) when _T_3191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_3192 = asUInt(reset) node _T_3193 = eq(_T_3192, UInt<1>(0h0)) when _T_3193 : node _T_3194 = eq(legal_source, UInt<1>(0h0)) when _T_3194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_3195 = asUInt(reset) node _T_3196 = eq(_T_3195, UInt<1>(0h0)) when _T_3196 : node _T_3197 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_3198 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3199 = asUInt(reset) node _T_3200 = eq(_T_3199, UInt<1>(0h0)) when _T_3200 : node _T_3201 = eq(_T_3198, UInt<1>(0h0)) when _T_3201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_3198, UInt<1>(0h1), "") : assert_110 node _T_3202 = not(mask_1) node _T_3203 = and(io.in.b.bits.mask, _T_3202) node _T_3204 = eq(_T_3203, UInt<1>(0h0)) node _T_3205 = asUInt(reset) node _T_3206 = eq(_T_3205, UInt<1>(0h0)) when _T_3206 : node _T_3207 = eq(_T_3204, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_3204, UInt<1>(0h1), "") : assert_111 node _T_3208 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_3208 : node _T_3209 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3210 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3211 = and(_T_3209, _T_3210) node _T_3212 = or(UInt<1>(0h0), _T_3211) node _T_3213 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3214 = cvt(_T_3213) node _T_3215 = and(_T_3214, asSInt(UInt<17>(0h10000))) node _T_3216 = asSInt(_T_3215) node _T_3217 = eq(_T_3216, asSInt(UInt<1>(0h0))) node _T_3218 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3219 = cvt(_T_3218) node _T_3220 = and(_T_3219, asSInt(UInt<29>(0h10000000))) node _T_3221 = asSInt(_T_3220) node _T_3222 = eq(_T_3221, asSInt(UInt<1>(0h0))) node _T_3223 = or(_T_3217, _T_3222) node _T_3224 = and(_T_3212, _T_3223) node _T_3225 = or(UInt<1>(0h0), _T_3224) node _T_3226 = and(UInt<1>(0h0), _T_3225) node _T_3227 = asUInt(reset) node _T_3228 = eq(_T_3227, UInt<1>(0h0)) when _T_3228 : node _T_3229 = eq(_T_3226, UInt<1>(0h0)) when _T_3229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_3226, UInt<1>(0h1), "") : assert_112 node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : node _T_3232 = eq(address_ok, UInt<1>(0h0)) when _T_3232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_3233 = asUInt(reset) node _T_3234 = eq(_T_3233, UInt<1>(0h0)) when _T_3234 : node _T_3235 = eq(legal_source, UInt<1>(0h0)) when _T_3235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_3236 = asUInt(reset) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) when _T_3237 : node _T_3238 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_3239 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : node _T_3242 = eq(_T_3239, UInt<1>(0h0)) when _T_3242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_3239, UInt<1>(0h1), "") : assert_116 node _T_3243 = eq(io.in.b.bits.mask, mask_1) node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : node _T_3246 = eq(_T_3243, UInt<1>(0h0)) when _T_3246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_3243, UInt<1>(0h1), "") : assert_117 node _T_3247 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_3247 : node _T_3248 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3249 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3250 = and(_T_3248, _T_3249) node _T_3251 = or(UInt<1>(0h0), _T_3250) node _T_3252 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3253 = cvt(_T_3252) node _T_3254 = and(_T_3253, asSInt(UInt<17>(0h10000))) node _T_3255 = asSInt(_T_3254) node _T_3256 = eq(_T_3255, asSInt(UInt<1>(0h0))) node _T_3257 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3258 = cvt(_T_3257) node _T_3259 = and(_T_3258, asSInt(UInt<29>(0h10000000))) node _T_3260 = asSInt(_T_3259) node _T_3261 = eq(_T_3260, asSInt(UInt<1>(0h0))) node _T_3262 = or(_T_3256, _T_3261) node _T_3263 = and(_T_3251, _T_3262) node _T_3264 = or(UInt<1>(0h0), _T_3263) node _T_3265 = and(UInt<1>(0h0), _T_3264) node _T_3266 = asUInt(reset) node _T_3267 = eq(_T_3266, UInt<1>(0h0)) when _T_3267 : node _T_3268 = eq(_T_3265, UInt<1>(0h0)) when _T_3268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_3265, UInt<1>(0h1), "") : assert_118 node _T_3269 = asUInt(reset) node _T_3270 = eq(_T_3269, UInt<1>(0h0)) when _T_3270 : node _T_3271 = eq(address_ok, UInt<1>(0h0)) when _T_3271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_3272 = asUInt(reset) node _T_3273 = eq(_T_3272, UInt<1>(0h0)) when _T_3273 : node _T_3274 = eq(legal_source, UInt<1>(0h0)) when _T_3274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_3275 = asUInt(reset) node _T_3276 = eq(_T_3275, UInt<1>(0h0)) when _T_3276 : node _T_3277 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_3278 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_3279 = asUInt(reset) node _T_3280 = eq(_T_3279, UInt<1>(0h0)) when _T_3280 : node _T_3281 = eq(_T_3278, UInt<1>(0h0)) when _T_3281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_3278, UInt<1>(0h1), "") : assert_122 node _T_3282 = eq(io.in.b.bits.mask, mask_1) node _T_3283 = asUInt(reset) node _T_3284 = eq(_T_3283, UInt<1>(0h0)) when _T_3284 : node _T_3285 = eq(_T_3282, UInt<1>(0h0)) when _T_3285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_3282, UInt<1>(0h1), "") : assert_123 node _T_3286 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_3286 : node _T_3287 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3288 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3289 = and(_T_3287, _T_3288) node _T_3290 = or(UInt<1>(0h0), _T_3289) node _T_3291 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3292 = cvt(_T_3291) node _T_3293 = and(_T_3292, asSInt(UInt<17>(0h10000))) node _T_3294 = asSInt(_T_3293) node _T_3295 = eq(_T_3294, asSInt(UInt<1>(0h0))) node _T_3296 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3297 = cvt(_T_3296) node _T_3298 = and(_T_3297, asSInt(UInt<29>(0h10000000))) node _T_3299 = asSInt(_T_3298) node _T_3300 = eq(_T_3299, asSInt(UInt<1>(0h0))) node _T_3301 = or(_T_3295, _T_3300) node _T_3302 = and(_T_3290, _T_3301) node _T_3303 = or(UInt<1>(0h0), _T_3302) node _T_3304 = and(UInt<1>(0h0), _T_3303) node _T_3305 = asUInt(reset) node _T_3306 = eq(_T_3305, UInt<1>(0h0)) when _T_3306 : node _T_3307 = eq(_T_3304, UInt<1>(0h0)) when _T_3307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_3304, UInt<1>(0h1), "") : assert_124 node _T_3308 = asUInt(reset) node _T_3309 = eq(_T_3308, UInt<1>(0h0)) when _T_3309 : node _T_3310 = eq(address_ok, UInt<1>(0h0)) when _T_3310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_3311 = asUInt(reset) node _T_3312 = eq(_T_3311, UInt<1>(0h0)) when _T_3312 : node _T_3313 = eq(legal_source, UInt<1>(0h0)) when _T_3313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_3314 = asUInt(reset) node _T_3315 = eq(_T_3314, UInt<1>(0h0)) when _T_3315 : node _T_3316 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_3317 = eq(io.in.b.bits.mask, mask_1) node _T_3318 = asUInt(reset) node _T_3319 = eq(_T_3318, UInt<1>(0h0)) when _T_3319 : node _T_3320 = eq(_T_3317, UInt<1>(0h0)) when _T_3320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_3317, UInt<1>(0h1), "") : assert_128 node _T_3321 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3322 = asUInt(reset) node _T_3323 = eq(_T_3322, UInt<1>(0h0)) when _T_3323 : node _T_3324 = eq(_T_3321, UInt<1>(0h0)) when _T_3324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_3321, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_3325 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_3326 = asUInt(reset) node _T_3327 = eq(_T_3326, UInt<1>(0h0)) when _T_3327 : node _T_3328 = eq(_T_3325, UInt<1>(0h0)) when _T_3328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_3325, UInt<1>(0h1), "") : assert_130 node _source_ok_T_316 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_44 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_44 = bits(_source_ok_uncommonBits_T_44, 1, 0) node _source_ok_T_317 = shr(io.in.c.bits.source, 2) node _source_ok_T_318 = eq(_source_ok_T_317, UInt<7>(0h70)) node _source_ok_T_319 = leq(UInt<1>(0h0), source_ok_uncommonBits_44) node _source_ok_T_320 = and(_source_ok_T_318, _source_ok_T_319) node _source_ok_T_321 = leq(source_ok_uncommonBits_44, UInt<2>(0h3)) node _source_ok_T_322 = and(_source_ok_T_320, _source_ok_T_321) node _source_ok_uncommonBits_T_45 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_45 = bits(_source_ok_uncommonBits_T_45, 1, 0) node _source_ok_T_323 = shr(io.in.c.bits.source, 2) node _source_ok_T_324 = eq(_source_ok_T_323, UInt<7>(0h71)) node _source_ok_T_325 = leq(UInt<1>(0h0), source_ok_uncommonBits_45) node _source_ok_T_326 = and(_source_ok_T_324, _source_ok_T_325) node _source_ok_T_327 = leq(source_ok_uncommonBits_45, UInt<2>(0h3)) node _source_ok_T_328 = and(_source_ok_T_326, _source_ok_T_327) node _source_ok_uncommonBits_T_46 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_46 = bits(_source_ok_uncommonBits_T_46, 1, 0) node _source_ok_T_329 = shr(io.in.c.bits.source, 2) node _source_ok_T_330 = eq(_source_ok_T_329, UInt<7>(0h72)) node _source_ok_T_331 = leq(UInt<1>(0h0), source_ok_uncommonBits_46) node _source_ok_T_332 = and(_source_ok_T_330, _source_ok_T_331) node _source_ok_T_333 = leq(source_ok_uncommonBits_46, UInt<2>(0h3)) node _source_ok_T_334 = and(_source_ok_T_332, _source_ok_T_333) node _source_ok_uncommonBits_T_47 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_47 = bits(_source_ok_uncommonBits_T_47, 1, 0) node _source_ok_T_335 = shr(io.in.c.bits.source, 2) node _source_ok_T_336 = eq(_source_ok_T_335, UInt<7>(0h73)) node _source_ok_T_337 = leq(UInt<1>(0h0), source_ok_uncommonBits_47) node _source_ok_T_338 = and(_source_ok_T_336, _source_ok_T_337) node _source_ok_T_339 = leq(source_ok_uncommonBits_47, UInt<2>(0h3)) node _source_ok_T_340 = and(_source_ok_T_338, _source_ok_T_339) node _source_ok_uncommonBits_T_48 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_48 = bits(_source_ok_uncommonBits_T_48, 1, 0) node _source_ok_T_341 = shr(io.in.c.bits.source, 2) node _source_ok_T_342 = eq(_source_ok_T_341, UInt<7>(0h7c)) node _source_ok_T_343 = leq(UInt<1>(0h0), source_ok_uncommonBits_48) node _source_ok_T_344 = and(_source_ok_T_342, _source_ok_T_343) node _source_ok_T_345 = leq(source_ok_uncommonBits_48, UInt<2>(0h3)) node _source_ok_T_346 = and(_source_ok_T_344, _source_ok_T_345) node _source_ok_uncommonBits_T_49 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_49 = bits(_source_ok_uncommonBits_T_49, 1, 0) node _source_ok_T_347 = shr(io.in.c.bits.source, 2) node _source_ok_T_348 = eq(_source_ok_T_347, UInt<7>(0h7b)) node _source_ok_T_349 = leq(UInt<1>(0h0), source_ok_uncommonBits_49) node _source_ok_T_350 = and(_source_ok_T_348, _source_ok_T_349) node _source_ok_T_351 = leq(source_ok_uncommonBits_49, UInt<2>(0h3)) node _source_ok_T_352 = and(_source_ok_T_350, _source_ok_T_351) node _source_ok_uncommonBits_T_50 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_50 = bits(_source_ok_uncommonBits_T_50, 4, 0) node _source_ok_T_353 = shr(io.in.c.bits.source, 5) node _source_ok_T_354 = eq(_source_ok_T_353, UInt<4>(0hd)) node _source_ok_T_355 = leq(UInt<1>(0h0), source_ok_uncommonBits_50) node _source_ok_T_356 = and(_source_ok_T_354, _source_ok_T_355) node _source_ok_T_357 = leq(source_ok_uncommonBits_50, UInt<5>(0h1f)) node _source_ok_T_358 = and(_source_ok_T_356, _source_ok_T_357) node _source_ok_uncommonBits_T_51 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_51 = bits(_source_ok_uncommonBits_T_51, 4, 0) node _source_ok_T_359 = shr(io.in.c.bits.source, 5) node _source_ok_T_360 = eq(_source_ok_T_359, UInt<4>(0hc)) node _source_ok_T_361 = leq(UInt<1>(0h0), source_ok_uncommonBits_51) node _source_ok_T_362 = and(_source_ok_T_360, _source_ok_T_361) node _source_ok_T_363 = leq(source_ok_uncommonBits_51, UInt<5>(0h1f)) node _source_ok_T_364 = and(_source_ok_T_362, _source_ok_T_363) node _source_ok_uncommonBits_T_52 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_52 = bits(_source_ok_uncommonBits_T_52, 4, 0) node _source_ok_T_365 = shr(io.in.c.bits.source, 5) node _source_ok_T_366 = eq(_source_ok_T_365, UInt<4>(0hb)) node _source_ok_T_367 = leq(UInt<1>(0h0), source_ok_uncommonBits_52) node _source_ok_T_368 = and(_source_ok_T_366, _source_ok_T_367) node _source_ok_T_369 = leq(source_ok_uncommonBits_52, UInt<5>(0h1f)) node _source_ok_T_370 = and(_source_ok_T_368, _source_ok_T_369) node _source_ok_uncommonBits_T_53 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_53 = bits(_source_ok_uncommonBits_T_53, 4, 0) node _source_ok_T_371 = shr(io.in.c.bits.source, 5) node _source_ok_T_372 = eq(_source_ok_T_371, UInt<4>(0ha)) node _source_ok_T_373 = leq(UInt<1>(0h0), source_ok_uncommonBits_53) node _source_ok_T_374 = and(_source_ok_T_372, _source_ok_T_373) node _source_ok_T_375 = leq(source_ok_uncommonBits_53, UInt<5>(0h1f)) node _source_ok_T_376 = and(_source_ok_T_374, _source_ok_T_375) node _source_ok_uncommonBits_T_54 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_54 = bits(_source_ok_uncommonBits_T_54, 4, 0) node _source_ok_T_377 = shr(io.in.c.bits.source, 5) node _source_ok_T_378 = eq(_source_ok_T_377, UInt<4>(0h9)) node _source_ok_T_379 = leq(UInt<1>(0h0), source_ok_uncommonBits_54) node _source_ok_T_380 = and(_source_ok_T_378, _source_ok_T_379) node _source_ok_T_381 = leq(source_ok_uncommonBits_54, UInt<5>(0h1f)) node _source_ok_T_382 = and(_source_ok_T_380, _source_ok_T_381) node _source_ok_uncommonBits_T_55 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_55 = bits(_source_ok_uncommonBits_T_55, 4, 0) node _source_ok_T_383 = shr(io.in.c.bits.source, 5) node _source_ok_T_384 = eq(_source_ok_T_383, UInt<4>(0h8)) node _source_ok_T_385 = leq(UInt<1>(0h0), source_ok_uncommonBits_55) node _source_ok_T_386 = and(_source_ok_T_384, _source_ok_T_385) node _source_ok_T_387 = leq(source_ok_uncommonBits_55, UInt<5>(0h1f)) node _source_ok_T_388 = and(_source_ok_T_386, _source_ok_T_387) node _source_ok_uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_56 = bits(_source_ok_uncommonBits_T_56, 1, 0) node _source_ok_T_389 = shr(io.in.c.bits.source, 2) node _source_ok_T_390 = eq(_source_ok_T_389, UInt<7>(0h7a)) node _source_ok_T_391 = leq(UInt<1>(0h0), source_ok_uncommonBits_56) node _source_ok_T_392 = and(_source_ok_T_390, _source_ok_T_391) node _source_ok_T_393 = leq(source_ok_uncommonBits_56, UInt<2>(0h3)) node _source_ok_T_394 = and(_source_ok_T_392, _source_ok_T_393) node _source_ok_uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_57 = bits(_source_ok_uncommonBits_T_57, 1, 0) node _source_ok_T_395 = shr(io.in.c.bits.source, 2) node _source_ok_T_396 = eq(_source_ok_T_395, UInt<7>(0h79)) node _source_ok_T_397 = leq(UInt<1>(0h0), source_ok_uncommonBits_57) node _source_ok_T_398 = and(_source_ok_T_396, _source_ok_T_397) node _source_ok_T_399 = leq(source_ok_uncommonBits_57, UInt<2>(0h3)) node _source_ok_T_400 = and(_source_ok_T_398, _source_ok_T_399) node _source_ok_uncommonBits_T_58 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_58 = bits(_source_ok_uncommonBits_T_58, 4, 0) node _source_ok_T_401 = shr(io.in.c.bits.source, 5) node _source_ok_T_402 = eq(_source_ok_T_401, UInt<3>(0h7)) node _source_ok_T_403 = leq(UInt<1>(0h0), source_ok_uncommonBits_58) node _source_ok_T_404 = and(_source_ok_T_402, _source_ok_T_403) node _source_ok_T_405 = leq(source_ok_uncommonBits_58, UInt<5>(0h1f)) node _source_ok_T_406 = and(_source_ok_T_404, _source_ok_T_405) node _source_ok_uncommonBits_T_59 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_59 = bits(_source_ok_uncommonBits_T_59, 4, 0) node _source_ok_T_407 = shr(io.in.c.bits.source, 5) node _source_ok_T_408 = eq(_source_ok_T_407, UInt<3>(0h6)) node _source_ok_T_409 = leq(UInt<1>(0h0), source_ok_uncommonBits_59) node _source_ok_T_410 = and(_source_ok_T_408, _source_ok_T_409) node _source_ok_T_411 = leq(source_ok_uncommonBits_59, UInt<5>(0h1f)) node _source_ok_T_412 = and(_source_ok_T_410, _source_ok_T_411) node _source_ok_uncommonBits_T_60 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_60 = bits(_source_ok_uncommonBits_T_60, 4, 0) node _source_ok_T_413 = shr(io.in.c.bits.source, 5) node _source_ok_T_414 = eq(_source_ok_T_413, UInt<3>(0h5)) node _source_ok_T_415 = leq(UInt<1>(0h0), source_ok_uncommonBits_60) node _source_ok_T_416 = and(_source_ok_T_414, _source_ok_T_415) node _source_ok_T_417 = leq(source_ok_uncommonBits_60, UInt<5>(0h1f)) node _source_ok_T_418 = and(_source_ok_T_416, _source_ok_T_417) node _source_ok_uncommonBits_T_61 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_61 = bits(_source_ok_uncommonBits_T_61, 4, 0) node _source_ok_T_419 = shr(io.in.c.bits.source, 5) node _source_ok_T_420 = eq(_source_ok_T_419, UInt<3>(0h4)) node _source_ok_T_421 = leq(UInt<1>(0h0), source_ok_uncommonBits_61) node _source_ok_T_422 = and(_source_ok_T_420, _source_ok_T_421) node _source_ok_T_423 = leq(source_ok_uncommonBits_61, UInt<5>(0h1f)) node _source_ok_T_424 = and(_source_ok_T_422, _source_ok_T_423) node _source_ok_uncommonBits_T_62 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_62 = bits(_source_ok_uncommonBits_T_62, 4, 0) node _source_ok_T_425 = shr(io.in.c.bits.source, 5) node _source_ok_T_426 = eq(_source_ok_T_425, UInt<2>(0h3)) node _source_ok_T_427 = leq(UInt<1>(0h0), source_ok_uncommonBits_62) node _source_ok_T_428 = and(_source_ok_T_426, _source_ok_T_427) node _source_ok_T_429 = leq(source_ok_uncommonBits_62, UInt<5>(0h1f)) node _source_ok_T_430 = and(_source_ok_T_428, _source_ok_T_429) node _source_ok_uncommonBits_T_63 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_63 = bits(_source_ok_uncommonBits_T_63, 4, 0) node _source_ok_T_431 = shr(io.in.c.bits.source, 5) node _source_ok_T_432 = eq(_source_ok_T_431, UInt<2>(0h2)) node _source_ok_T_433 = leq(UInt<1>(0h0), source_ok_uncommonBits_63) node _source_ok_T_434 = and(_source_ok_T_432, _source_ok_T_433) node _source_ok_T_435 = leq(source_ok_uncommonBits_63, UInt<5>(0h1f)) node _source_ok_T_436 = and(_source_ok_T_434, _source_ok_T_435) node _source_ok_uncommonBits_T_64 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_64 = bits(_source_ok_uncommonBits_T_64, 4, 0) node _source_ok_T_437 = shr(io.in.c.bits.source, 5) node _source_ok_T_438 = eq(_source_ok_T_437, UInt<1>(0h1)) node _source_ok_T_439 = leq(UInt<1>(0h0), source_ok_uncommonBits_64) node _source_ok_T_440 = and(_source_ok_T_438, _source_ok_T_439) node _source_ok_T_441 = leq(source_ok_uncommonBits_64, UInt<5>(0h1f)) node _source_ok_T_442 = and(_source_ok_T_440, _source_ok_T_441) node _source_ok_uncommonBits_T_65 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_65 = bits(_source_ok_uncommonBits_T_65, 4, 0) node _source_ok_T_443 = shr(io.in.c.bits.source, 5) node _source_ok_T_444 = eq(_source_ok_T_443, UInt<1>(0h0)) node _source_ok_T_445 = leq(UInt<1>(0h0), source_ok_uncommonBits_65) node _source_ok_T_446 = and(_source_ok_T_444, _source_ok_T_445) node _source_ok_T_447 = leq(source_ok_uncommonBits_65, UInt<5>(0h1f)) node _source_ok_T_448 = and(_source_ok_T_446, _source_ok_T_447) node _source_ok_T_449 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _source_ok_T_450 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE_2 : UInt<1>[25] connect _source_ok_WIRE_2[0], _source_ok_T_316 connect _source_ok_WIRE_2[1], _source_ok_T_322 connect _source_ok_WIRE_2[2], _source_ok_T_328 connect _source_ok_WIRE_2[3], _source_ok_T_334 connect _source_ok_WIRE_2[4], _source_ok_T_340 connect _source_ok_WIRE_2[5], _source_ok_T_346 connect _source_ok_WIRE_2[6], _source_ok_T_352 connect _source_ok_WIRE_2[7], _source_ok_T_358 connect _source_ok_WIRE_2[8], _source_ok_T_364 connect _source_ok_WIRE_2[9], _source_ok_T_370 connect _source_ok_WIRE_2[10], _source_ok_T_376 connect _source_ok_WIRE_2[11], _source_ok_T_382 connect _source_ok_WIRE_2[12], _source_ok_T_388 connect _source_ok_WIRE_2[13], _source_ok_T_394 connect _source_ok_WIRE_2[14], _source_ok_T_400 connect _source_ok_WIRE_2[15], _source_ok_T_406 connect _source_ok_WIRE_2[16], _source_ok_T_412 connect _source_ok_WIRE_2[17], _source_ok_T_418 connect _source_ok_WIRE_2[18], _source_ok_T_424 connect _source_ok_WIRE_2[19], _source_ok_T_430 connect _source_ok_WIRE_2[20], _source_ok_T_436 connect _source_ok_WIRE_2[21], _source_ok_T_442 connect _source_ok_WIRE_2[22], _source_ok_T_448 connect _source_ok_WIRE_2[23], _source_ok_T_449 connect _source_ok_WIRE_2[24], _source_ok_T_450 node _source_ok_T_451 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_452 = or(_source_ok_T_451, _source_ok_WIRE_2[2]) node _source_ok_T_453 = or(_source_ok_T_452, _source_ok_WIRE_2[3]) node _source_ok_T_454 = or(_source_ok_T_453, _source_ok_WIRE_2[4]) node _source_ok_T_455 = or(_source_ok_T_454, _source_ok_WIRE_2[5]) node _source_ok_T_456 = or(_source_ok_T_455, _source_ok_WIRE_2[6]) node _source_ok_T_457 = or(_source_ok_T_456, _source_ok_WIRE_2[7]) node _source_ok_T_458 = or(_source_ok_T_457, _source_ok_WIRE_2[8]) node _source_ok_T_459 = or(_source_ok_T_458, _source_ok_WIRE_2[9]) node _source_ok_T_460 = or(_source_ok_T_459, _source_ok_WIRE_2[10]) node _source_ok_T_461 = or(_source_ok_T_460, _source_ok_WIRE_2[11]) node _source_ok_T_462 = or(_source_ok_T_461, _source_ok_WIRE_2[12]) node _source_ok_T_463 = or(_source_ok_T_462, _source_ok_WIRE_2[13]) node _source_ok_T_464 = or(_source_ok_T_463, _source_ok_WIRE_2[14]) node _source_ok_T_465 = or(_source_ok_T_464, _source_ok_WIRE_2[15]) node _source_ok_T_466 = or(_source_ok_T_465, _source_ok_WIRE_2[16]) node _source_ok_T_467 = or(_source_ok_T_466, _source_ok_WIRE_2[17]) node _source_ok_T_468 = or(_source_ok_T_467, _source_ok_WIRE_2[18]) node _source_ok_T_469 = or(_source_ok_T_468, _source_ok_WIRE_2[19]) node _source_ok_T_470 = or(_source_ok_T_469, _source_ok_WIRE_2[20]) node _source_ok_T_471 = or(_source_ok_T_470, _source_ok_WIRE_2[21]) node _source_ok_T_472 = or(_source_ok_T_471, _source_ok_WIRE_2[22]) node _source_ok_T_473 = or(_source_ok_T_472, _source_ok_WIRE_2[23]) node source_ok_2 = or(_source_ok_T_473, _source_ok_WIRE_2[24]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_3329 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _T_3330 = eq(_T_3329, UInt<1>(0h0)) node _T_3331 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3332 = cvt(_T_3331) node _T_3333 = and(_T_3332, asSInt(UInt<1>(0h0))) node _T_3334 = asSInt(_T_3333) node _T_3335 = eq(_T_3334, asSInt(UInt<1>(0h0))) node _T_3336 = or(_T_3330, _T_3335) node _uncommonBits_T_286 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_286 = bits(_uncommonBits_T_286, 1, 0) node _T_3337 = shr(io.in.c.bits.source, 2) node _T_3338 = eq(_T_3337, UInt<7>(0h70)) node _T_3339 = leq(UInt<1>(0h0), uncommonBits_286) node _T_3340 = and(_T_3338, _T_3339) node _T_3341 = leq(uncommonBits_286, UInt<2>(0h3)) node _T_3342 = and(_T_3340, _T_3341) node _T_3343 = eq(_T_3342, UInt<1>(0h0)) node _T_3344 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3345 = cvt(_T_3344) node _T_3346 = and(_T_3345, asSInt(UInt<1>(0h0))) node _T_3347 = asSInt(_T_3346) node _T_3348 = eq(_T_3347, asSInt(UInt<1>(0h0))) node _T_3349 = or(_T_3343, _T_3348) node _uncommonBits_T_287 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_287 = bits(_uncommonBits_T_287, 1, 0) node _T_3350 = shr(io.in.c.bits.source, 2) node _T_3351 = eq(_T_3350, UInt<7>(0h71)) node _T_3352 = leq(UInt<1>(0h0), uncommonBits_287) node _T_3353 = and(_T_3351, _T_3352) node _T_3354 = leq(uncommonBits_287, UInt<2>(0h3)) node _T_3355 = and(_T_3353, _T_3354) node _T_3356 = eq(_T_3355, UInt<1>(0h0)) node _T_3357 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3358 = cvt(_T_3357) node _T_3359 = and(_T_3358, asSInt(UInt<1>(0h0))) node _T_3360 = asSInt(_T_3359) node _T_3361 = eq(_T_3360, asSInt(UInt<1>(0h0))) node _T_3362 = or(_T_3356, _T_3361) node _uncommonBits_T_288 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_288 = bits(_uncommonBits_T_288, 1, 0) node _T_3363 = shr(io.in.c.bits.source, 2) node _T_3364 = eq(_T_3363, UInt<7>(0h72)) node _T_3365 = leq(UInt<1>(0h0), uncommonBits_288) node _T_3366 = and(_T_3364, _T_3365) node _T_3367 = leq(uncommonBits_288, UInt<2>(0h3)) node _T_3368 = and(_T_3366, _T_3367) node _T_3369 = eq(_T_3368, UInt<1>(0h0)) node _T_3370 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3371 = cvt(_T_3370) node _T_3372 = and(_T_3371, asSInt(UInt<1>(0h0))) node _T_3373 = asSInt(_T_3372) node _T_3374 = eq(_T_3373, asSInt(UInt<1>(0h0))) node _T_3375 = or(_T_3369, _T_3374) node _uncommonBits_T_289 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_289 = bits(_uncommonBits_T_289, 1, 0) node _T_3376 = shr(io.in.c.bits.source, 2) node _T_3377 = eq(_T_3376, UInt<7>(0h73)) node _T_3378 = leq(UInt<1>(0h0), uncommonBits_289) node _T_3379 = and(_T_3377, _T_3378) node _T_3380 = leq(uncommonBits_289, UInt<2>(0h3)) node _T_3381 = and(_T_3379, _T_3380) node _T_3382 = eq(_T_3381, UInt<1>(0h0)) node _T_3383 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3384 = cvt(_T_3383) node _T_3385 = and(_T_3384, asSInt(UInt<1>(0h0))) node _T_3386 = asSInt(_T_3385) node _T_3387 = eq(_T_3386, asSInt(UInt<1>(0h0))) node _T_3388 = or(_T_3382, _T_3387) node _uncommonBits_T_290 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_290 = bits(_uncommonBits_T_290, 1, 0) node _T_3389 = shr(io.in.c.bits.source, 2) node _T_3390 = eq(_T_3389, UInt<7>(0h7c)) node _T_3391 = leq(UInt<1>(0h0), uncommonBits_290) node _T_3392 = and(_T_3390, _T_3391) node _T_3393 = leq(uncommonBits_290, UInt<2>(0h3)) node _T_3394 = and(_T_3392, _T_3393) node _T_3395 = eq(_T_3394, UInt<1>(0h0)) node _T_3396 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3397 = cvt(_T_3396) node _T_3398 = and(_T_3397, asSInt(UInt<1>(0h0))) node _T_3399 = asSInt(_T_3398) node _T_3400 = eq(_T_3399, asSInt(UInt<1>(0h0))) node _T_3401 = or(_T_3395, _T_3400) node _uncommonBits_T_291 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_291 = bits(_uncommonBits_T_291, 1, 0) node _T_3402 = shr(io.in.c.bits.source, 2) node _T_3403 = eq(_T_3402, UInt<7>(0h7b)) node _T_3404 = leq(UInt<1>(0h0), uncommonBits_291) node _T_3405 = and(_T_3403, _T_3404) node _T_3406 = leq(uncommonBits_291, UInt<2>(0h3)) node _T_3407 = and(_T_3405, _T_3406) node _T_3408 = eq(_T_3407, UInt<1>(0h0)) node _T_3409 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3410 = cvt(_T_3409) node _T_3411 = and(_T_3410, asSInt(UInt<1>(0h0))) node _T_3412 = asSInt(_T_3411) node _T_3413 = eq(_T_3412, asSInt(UInt<1>(0h0))) node _T_3414 = or(_T_3408, _T_3413) node _uncommonBits_T_292 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_292 = bits(_uncommonBits_T_292, 4, 0) node _T_3415 = shr(io.in.c.bits.source, 5) node _T_3416 = eq(_T_3415, UInt<4>(0hd)) node _T_3417 = leq(UInt<1>(0h0), uncommonBits_292) node _T_3418 = and(_T_3416, _T_3417) node _T_3419 = leq(uncommonBits_292, UInt<5>(0h1f)) node _T_3420 = and(_T_3418, _T_3419) node _T_3421 = eq(_T_3420, UInt<1>(0h0)) node _T_3422 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3423 = cvt(_T_3422) node _T_3424 = and(_T_3423, asSInt(UInt<1>(0h0))) node _T_3425 = asSInt(_T_3424) node _T_3426 = eq(_T_3425, asSInt(UInt<1>(0h0))) node _T_3427 = or(_T_3421, _T_3426) node _uncommonBits_T_293 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_293 = bits(_uncommonBits_T_293, 4, 0) node _T_3428 = shr(io.in.c.bits.source, 5) node _T_3429 = eq(_T_3428, UInt<4>(0hc)) node _T_3430 = leq(UInt<1>(0h0), uncommonBits_293) node _T_3431 = and(_T_3429, _T_3430) node _T_3432 = leq(uncommonBits_293, UInt<5>(0h1f)) node _T_3433 = and(_T_3431, _T_3432) node _T_3434 = eq(_T_3433, UInt<1>(0h0)) node _T_3435 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3436 = cvt(_T_3435) node _T_3437 = and(_T_3436, asSInt(UInt<1>(0h0))) node _T_3438 = asSInt(_T_3437) node _T_3439 = eq(_T_3438, asSInt(UInt<1>(0h0))) node _T_3440 = or(_T_3434, _T_3439) node _uncommonBits_T_294 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_294 = bits(_uncommonBits_T_294, 4, 0) node _T_3441 = shr(io.in.c.bits.source, 5) node _T_3442 = eq(_T_3441, UInt<4>(0hb)) node _T_3443 = leq(UInt<1>(0h0), uncommonBits_294) node _T_3444 = and(_T_3442, _T_3443) node _T_3445 = leq(uncommonBits_294, UInt<5>(0h1f)) node _T_3446 = and(_T_3444, _T_3445) node _T_3447 = eq(_T_3446, UInt<1>(0h0)) node _T_3448 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3449 = cvt(_T_3448) node _T_3450 = and(_T_3449, asSInt(UInt<1>(0h0))) node _T_3451 = asSInt(_T_3450) node _T_3452 = eq(_T_3451, asSInt(UInt<1>(0h0))) node _T_3453 = or(_T_3447, _T_3452) node _uncommonBits_T_295 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_295 = bits(_uncommonBits_T_295, 4, 0) node _T_3454 = shr(io.in.c.bits.source, 5) node _T_3455 = eq(_T_3454, UInt<4>(0ha)) node _T_3456 = leq(UInt<1>(0h0), uncommonBits_295) node _T_3457 = and(_T_3455, _T_3456) node _T_3458 = leq(uncommonBits_295, UInt<5>(0h1f)) node _T_3459 = and(_T_3457, _T_3458) node _T_3460 = eq(_T_3459, UInt<1>(0h0)) node _T_3461 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3462 = cvt(_T_3461) node _T_3463 = and(_T_3462, asSInt(UInt<1>(0h0))) node _T_3464 = asSInt(_T_3463) node _T_3465 = eq(_T_3464, asSInt(UInt<1>(0h0))) node _T_3466 = or(_T_3460, _T_3465) node _uncommonBits_T_296 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_296 = bits(_uncommonBits_T_296, 4, 0) node _T_3467 = shr(io.in.c.bits.source, 5) node _T_3468 = eq(_T_3467, UInt<4>(0h9)) node _T_3469 = leq(UInt<1>(0h0), uncommonBits_296) node _T_3470 = and(_T_3468, _T_3469) node _T_3471 = leq(uncommonBits_296, UInt<5>(0h1f)) node _T_3472 = and(_T_3470, _T_3471) node _T_3473 = eq(_T_3472, UInt<1>(0h0)) node _T_3474 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3475 = cvt(_T_3474) node _T_3476 = and(_T_3475, asSInt(UInt<1>(0h0))) node _T_3477 = asSInt(_T_3476) node _T_3478 = eq(_T_3477, asSInt(UInt<1>(0h0))) node _T_3479 = or(_T_3473, _T_3478) node _uncommonBits_T_297 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_297 = bits(_uncommonBits_T_297, 4, 0) node _T_3480 = shr(io.in.c.bits.source, 5) node _T_3481 = eq(_T_3480, UInt<4>(0h8)) node _T_3482 = leq(UInt<1>(0h0), uncommonBits_297) node _T_3483 = and(_T_3481, _T_3482) node _T_3484 = leq(uncommonBits_297, UInt<5>(0h1f)) node _T_3485 = and(_T_3483, _T_3484) node _T_3486 = eq(_T_3485, UInt<1>(0h0)) node _T_3487 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3488 = cvt(_T_3487) node _T_3489 = and(_T_3488, asSInt(UInt<1>(0h0))) node _T_3490 = asSInt(_T_3489) node _T_3491 = eq(_T_3490, asSInt(UInt<1>(0h0))) node _T_3492 = or(_T_3486, _T_3491) node _uncommonBits_T_298 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_298 = bits(_uncommonBits_T_298, 1, 0) node _T_3493 = shr(io.in.c.bits.source, 2) node _T_3494 = eq(_T_3493, UInt<7>(0h7a)) node _T_3495 = leq(UInt<1>(0h0), uncommonBits_298) node _T_3496 = and(_T_3494, _T_3495) node _T_3497 = leq(uncommonBits_298, UInt<2>(0h3)) node _T_3498 = and(_T_3496, _T_3497) node _T_3499 = eq(_T_3498, UInt<1>(0h0)) node _T_3500 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3501 = cvt(_T_3500) node _T_3502 = and(_T_3501, asSInt(UInt<1>(0h0))) node _T_3503 = asSInt(_T_3502) node _T_3504 = eq(_T_3503, asSInt(UInt<1>(0h0))) node _T_3505 = or(_T_3499, _T_3504) node _uncommonBits_T_299 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_299 = bits(_uncommonBits_T_299, 1, 0) node _T_3506 = shr(io.in.c.bits.source, 2) node _T_3507 = eq(_T_3506, UInt<7>(0h79)) node _T_3508 = leq(UInt<1>(0h0), uncommonBits_299) node _T_3509 = and(_T_3507, _T_3508) node _T_3510 = leq(uncommonBits_299, UInt<2>(0h3)) node _T_3511 = and(_T_3509, _T_3510) node _T_3512 = eq(_T_3511, UInt<1>(0h0)) node _T_3513 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3514 = cvt(_T_3513) node _T_3515 = and(_T_3514, asSInt(UInt<1>(0h0))) node _T_3516 = asSInt(_T_3515) node _T_3517 = eq(_T_3516, asSInt(UInt<1>(0h0))) node _T_3518 = or(_T_3512, _T_3517) node _uncommonBits_T_300 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_300 = bits(_uncommonBits_T_300, 4, 0) node _T_3519 = shr(io.in.c.bits.source, 5) node _T_3520 = eq(_T_3519, UInt<3>(0h7)) node _T_3521 = leq(UInt<1>(0h0), uncommonBits_300) node _T_3522 = and(_T_3520, _T_3521) node _T_3523 = leq(uncommonBits_300, UInt<5>(0h1f)) node _T_3524 = and(_T_3522, _T_3523) node _T_3525 = eq(_T_3524, UInt<1>(0h0)) node _T_3526 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3527 = cvt(_T_3526) node _T_3528 = and(_T_3527, asSInt(UInt<1>(0h0))) node _T_3529 = asSInt(_T_3528) node _T_3530 = eq(_T_3529, asSInt(UInt<1>(0h0))) node _T_3531 = or(_T_3525, _T_3530) node _uncommonBits_T_301 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_301 = bits(_uncommonBits_T_301, 4, 0) node _T_3532 = shr(io.in.c.bits.source, 5) node _T_3533 = eq(_T_3532, UInt<3>(0h6)) node _T_3534 = leq(UInt<1>(0h0), uncommonBits_301) node _T_3535 = and(_T_3533, _T_3534) node _T_3536 = leq(uncommonBits_301, UInt<5>(0h1f)) node _T_3537 = and(_T_3535, _T_3536) node _T_3538 = eq(_T_3537, UInt<1>(0h0)) node _T_3539 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3540 = cvt(_T_3539) node _T_3541 = and(_T_3540, asSInt(UInt<1>(0h0))) node _T_3542 = asSInt(_T_3541) node _T_3543 = eq(_T_3542, asSInt(UInt<1>(0h0))) node _T_3544 = or(_T_3538, _T_3543) node _uncommonBits_T_302 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_302 = bits(_uncommonBits_T_302, 4, 0) node _T_3545 = shr(io.in.c.bits.source, 5) node _T_3546 = eq(_T_3545, UInt<3>(0h5)) node _T_3547 = leq(UInt<1>(0h0), uncommonBits_302) node _T_3548 = and(_T_3546, _T_3547) node _T_3549 = leq(uncommonBits_302, UInt<5>(0h1f)) node _T_3550 = and(_T_3548, _T_3549) node _T_3551 = eq(_T_3550, UInt<1>(0h0)) node _T_3552 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3553 = cvt(_T_3552) node _T_3554 = and(_T_3553, asSInt(UInt<1>(0h0))) node _T_3555 = asSInt(_T_3554) node _T_3556 = eq(_T_3555, asSInt(UInt<1>(0h0))) node _T_3557 = or(_T_3551, _T_3556) node _uncommonBits_T_303 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_303 = bits(_uncommonBits_T_303, 4, 0) node _T_3558 = shr(io.in.c.bits.source, 5) node _T_3559 = eq(_T_3558, UInt<3>(0h4)) node _T_3560 = leq(UInt<1>(0h0), uncommonBits_303) node _T_3561 = and(_T_3559, _T_3560) node _T_3562 = leq(uncommonBits_303, UInt<5>(0h1f)) node _T_3563 = and(_T_3561, _T_3562) node _T_3564 = eq(_T_3563, UInt<1>(0h0)) node _T_3565 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3566 = cvt(_T_3565) node _T_3567 = and(_T_3566, asSInt(UInt<1>(0h0))) node _T_3568 = asSInt(_T_3567) node _T_3569 = eq(_T_3568, asSInt(UInt<1>(0h0))) node _T_3570 = or(_T_3564, _T_3569) node _uncommonBits_T_304 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_304 = bits(_uncommonBits_T_304, 4, 0) node _T_3571 = shr(io.in.c.bits.source, 5) node _T_3572 = eq(_T_3571, UInt<2>(0h3)) node _T_3573 = leq(UInt<1>(0h0), uncommonBits_304) node _T_3574 = and(_T_3572, _T_3573) node _T_3575 = leq(uncommonBits_304, UInt<5>(0h1f)) node _T_3576 = and(_T_3574, _T_3575) node _T_3577 = eq(_T_3576, UInt<1>(0h0)) node _T_3578 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3579 = cvt(_T_3578) node _T_3580 = and(_T_3579, asSInt(UInt<1>(0h0))) node _T_3581 = asSInt(_T_3580) node _T_3582 = eq(_T_3581, asSInt(UInt<1>(0h0))) node _T_3583 = or(_T_3577, _T_3582) node _uncommonBits_T_305 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_305 = bits(_uncommonBits_T_305, 4, 0) node _T_3584 = shr(io.in.c.bits.source, 5) node _T_3585 = eq(_T_3584, UInt<2>(0h2)) node _T_3586 = leq(UInt<1>(0h0), uncommonBits_305) node _T_3587 = and(_T_3585, _T_3586) node _T_3588 = leq(uncommonBits_305, UInt<5>(0h1f)) node _T_3589 = and(_T_3587, _T_3588) node _T_3590 = eq(_T_3589, UInt<1>(0h0)) node _T_3591 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3592 = cvt(_T_3591) node _T_3593 = and(_T_3592, asSInt(UInt<1>(0h0))) node _T_3594 = asSInt(_T_3593) node _T_3595 = eq(_T_3594, asSInt(UInt<1>(0h0))) node _T_3596 = or(_T_3590, _T_3595) node _uncommonBits_T_306 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_306 = bits(_uncommonBits_T_306, 4, 0) node _T_3597 = shr(io.in.c.bits.source, 5) node _T_3598 = eq(_T_3597, UInt<1>(0h1)) node _T_3599 = leq(UInt<1>(0h0), uncommonBits_306) node _T_3600 = and(_T_3598, _T_3599) node _T_3601 = leq(uncommonBits_306, UInt<5>(0h1f)) node _T_3602 = and(_T_3600, _T_3601) node _T_3603 = eq(_T_3602, UInt<1>(0h0)) node _T_3604 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3605 = cvt(_T_3604) node _T_3606 = and(_T_3605, asSInt(UInt<1>(0h0))) node _T_3607 = asSInt(_T_3606) node _T_3608 = eq(_T_3607, asSInt(UInt<1>(0h0))) node _T_3609 = or(_T_3603, _T_3608) node _uncommonBits_T_307 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_307 = bits(_uncommonBits_T_307, 4, 0) node _T_3610 = shr(io.in.c.bits.source, 5) node _T_3611 = eq(_T_3610, UInt<1>(0h0)) node _T_3612 = leq(UInt<1>(0h0), uncommonBits_307) node _T_3613 = and(_T_3611, _T_3612) node _T_3614 = leq(uncommonBits_307, UInt<5>(0h1f)) node _T_3615 = and(_T_3613, _T_3614) node _T_3616 = eq(_T_3615, UInt<1>(0h0)) node _T_3617 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3618 = cvt(_T_3617) node _T_3619 = and(_T_3618, asSInt(UInt<1>(0h0))) node _T_3620 = asSInt(_T_3619) node _T_3621 = eq(_T_3620, asSInt(UInt<1>(0h0))) node _T_3622 = or(_T_3616, _T_3621) node _T_3623 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_3624 = eq(_T_3623, UInt<1>(0h0)) node _T_3625 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3626 = cvt(_T_3625) node _T_3627 = and(_T_3626, asSInt(UInt<1>(0h0))) node _T_3628 = asSInt(_T_3627) node _T_3629 = eq(_T_3628, asSInt(UInt<1>(0h0))) node _T_3630 = or(_T_3624, _T_3629) node _T_3631 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_3632 = eq(_T_3631, UInt<1>(0h0)) node _T_3633 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3634 = cvt(_T_3633) node _T_3635 = and(_T_3634, asSInt(UInt<1>(0h0))) node _T_3636 = asSInt(_T_3635) node _T_3637 = eq(_T_3636, asSInt(UInt<1>(0h0))) node _T_3638 = or(_T_3632, _T_3637) node _T_3639 = and(_T_3336, _T_3349) node _T_3640 = and(_T_3639, _T_3362) node _T_3641 = and(_T_3640, _T_3375) node _T_3642 = and(_T_3641, _T_3388) node _T_3643 = and(_T_3642, _T_3401) node _T_3644 = and(_T_3643, _T_3414) node _T_3645 = and(_T_3644, _T_3427) node _T_3646 = and(_T_3645, _T_3440) node _T_3647 = and(_T_3646, _T_3453) node _T_3648 = and(_T_3647, _T_3466) node _T_3649 = and(_T_3648, _T_3479) node _T_3650 = and(_T_3649, _T_3492) node _T_3651 = and(_T_3650, _T_3505) node _T_3652 = and(_T_3651, _T_3518) node _T_3653 = and(_T_3652, _T_3531) node _T_3654 = and(_T_3653, _T_3544) node _T_3655 = and(_T_3654, _T_3557) node _T_3656 = and(_T_3655, _T_3570) node _T_3657 = and(_T_3656, _T_3583) node _T_3658 = and(_T_3657, _T_3596) node _T_3659 = and(_T_3658, _T_3609) node _T_3660 = and(_T_3659, _T_3622) node _T_3661 = and(_T_3660, _T_3630) node _T_3662 = and(_T_3661, _T_3638) node _T_3663 = asUInt(reset) node _T_3664 = eq(_T_3663, UInt<1>(0h0)) when _T_3664 : node _T_3665 = eq(_T_3662, UInt<1>(0h0)) when _T_3665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_3662, UInt<1>(0h1), "") : assert_131 node _T_3666 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_3666 : node _T_3667 = asUInt(reset) node _T_3668 = eq(_T_3667, UInt<1>(0h0)) when _T_3668 : node _T_3669 = eq(address_ok_1, UInt<1>(0h0)) when _T_3669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_3670 = asUInt(reset) node _T_3671 = eq(_T_3670, UInt<1>(0h0)) when _T_3671 : node _T_3672 = eq(source_ok_2, UInt<1>(0h0)) when _T_3672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_3673 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_3674 = asUInt(reset) node _T_3675 = eq(_T_3674, UInt<1>(0h0)) when _T_3675 : node _T_3676 = eq(_T_3673, UInt<1>(0h0)) when _T_3676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_3673, UInt<1>(0h1), "") : assert_134 node _T_3677 = asUInt(reset) node _T_3678 = eq(_T_3677, UInt<1>(0h0)) when _T_3678 : node _T_3679 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_3680 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_3681 = asUInt(reset) node _T_3682 = eq(_T_3681, UInt<1>(0h0)) when _T_3682 : node _T_3683 = eq(_T_3680, UInt<1>(0h0)) when _T_3683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_3680, UInt<1>(0h1), "") : assert_136 node _T_3684 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_3685 = asUInt(reset) node _T_3686 = eq(_T_3685, UInt<1>(0h0)) when _T_3686 : node _T_3687 = eq(_T_3684, UInt<1>(0h0)) when _T_3687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_3684, UInt<1>(0h1), "") : assert_137 node _T_3688 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_3688 : node _T_3689 = asUInt(reset) node _T_3690 = eq(_T_3689, UInt<1>(0h0)) when _T_3690 : node _T_3691 = eq(address_ok_1, UInt<1>(0h0)) when _T_3691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_3692 = asUInt(reset) node _T_3693 = eq(_T_3692, UInt<1>(0h0)) when _T_3693 : node _T_3694 = eq(source_ok_2, UInt<1>(0h0)) when _T_3694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_3695 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_3696 = asUInt(reset) node _T_3697 = eq(_T_3696, UInt<1>(0h0)) when _T_3697 : node _T_3698 = eq(_T_3695, UInt<1>(0h0)) when _T_3698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_3695, UInt<1>(0h1), "") : assert_140 node _T_3699 = asUInt(reset) node _T_3700 = eq(_T_3699, UInt<1>(0h0)) when _T_3700 : node _T_3701 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_3702 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_3703 = asUInt(reset) node _T_3704 = eq(_T_3703, UInt<1>(0h0)) when _T_3704 : node _T_3705 = eq(_T_3702, UInt<1>(0h0)) when _T_3705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_3702, UInt<1>(0h1), "") : assert_142 node _T_3706 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_3706 : node _T_3707 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_3708 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_3709 = and(_T_3707, _T_3708) node _T_3710 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_308 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_308 = bits(_uncommonBits_T_308, 1, 0) node _T_3711 = shr(io.in.c.bits.source, 2) node _T_3712 = eq(_T_3711, UInt<7>(0h70)) node _T_3713 = leq(UInt<1>(0h0), uncommonBits_308) node _T_3714 = and(_T_3712, _T_3713) node _T_3715 = leq(uncommonBits_308, UInt<2>(0h3)) node _T_3716 = and(_T_3714, _T_3715) node _uncommonBits_T_309 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_309 = bits(_uncommonBits_T_309, 1, 0) node _T_3717 = shr(io.in.c.bits.source, 2) node _T_3718 = eq(_T_3717, UInt<7>(0h71)) node _T_3719 = leq(UInt<1>(0h0), uncommonBits_309) node _T_3720 = and(_T_3718, _T_3719) node _T_3721 = leq(uncommonBits_309, UInt<2>(0h3)) node _T_3722 = and(_T_3720, _T_3721) node _uncommonBits_T_310 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_310 = bits(_uncommonBits_T_310, 1, 0) node _T_3723 = shr(io.in.c.bits.source, 2) node _T_3724 = eq(_T_3723, UInt<7>(0h72)) node _T_3725 = leq(UInt<1>(0h0), uncommonBits_310) node _T_3726 = and(_T_3724, _T_3725) node _T_3727 = leq(uncommonBits_310, UInt<2>(0h3)) node _T_3728 = and(_T_3726, _T_3727) node _uncommonBits_T_311 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_311 = bits(_uncommonBits_T_311, 1, 0) node _T_3729 = shr(io.in.c.bits.source, 2) node _T_3730 = eq(_T_3729, UInt<7>(0h73)) node _T_3731 = leq(UInt<1>(0h0), uncommonBits_311) node _T_3732 = and(_T_3730, _T_3731) node _T_3733 = leq(uncommonBits_311, UInt<2>(0h3)) node _T_3734 = and(_T_3732, _T_3733) node _uncommonBits_T_312 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_312 = bits(_uncommonBits_T_312, 1, 0) node _T_3735 = shr(io.in.c.bits.source, 2) node _T_3736 = eq(_T_3735, UInt<7>(0h7c)) node _T_3737 = leq(UInt<1>(0h0), uncommonBits_312) node _T_3738 = and(_T_3736, _T_3737) node _T_3739 = leq(uncommonBits_312, UInt<2>(0h3)) node _T_3740 = and(_T_3738, _T_3739) node _uncommonBits_T_313 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_313 = bits(_uncommonBits_T_313, 1, 0) node _T_3741 = shr(io.in.c.bits.source, 2) node _T_3742 = eq(_T_3741, UInt<7>(0h7b)) node _T_3743 = leq(UInt<1>(0h0), uncommonBits_313) node _T_3744 = and(_T_3742, _T_3743) node _T_3745 = leq(uncommonBits_313, UInt<2>(0h3)) node _T_3746 = and(_T_3744, _T_3745) node _uncommonBits_T_314 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_314 = bits(_uncommonBits_T_314, 4, 0) node _T_3747 = shr(io.in.c.bits.source, 5) node _T_3748 = eq(_T_3747, UInt<4>(0hd)) node _T_3749 = leq(UInt<1>(0h0), uncommonBits_314) node _T_3750 = and(_T_3748, _T_3749) node _T_3751 = leq(uncommonBits_314, UInt<5>(0h1f)) node _T_3752 = and(_T_3750, _T_3751) node _uncommonBits_T_315 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_315 = bits(_uncommonBits_T_315, 4, 0) node _T_3753 = shr(io.in.c.bits.source, 5) node _T_3754 = eq(_T_3753, UInt<4>(0hc)) node _T_3755 = leq(UInt<1>(0h0), uncommonBits_315) node _T_3756 = and(_T_3754, _T_3755) node _T_3757 = leq(uncommonBits_315, UInt<5>(0h1f)) node _T_3758 = and(_T_3756, _T_3757) node _uncommonBits_T_316 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_316 = bits(_uncommonBits_T_316, 4, 0) node _T_3759 = shr(io.in.c.bits.source, 5) node _T_3760 = eq(_T_3759, UInt<4>(0hb)) node _T_3761 = leq(UInt<1>(0h0), uncommonBits_316) node _T_3762 = and(_T_3760, _T_3761) node _T_3763 = leq(uncommonBits_316, UInt<5>(0h1f)) node _T_3764 = and(_T_3762, _T_3763) node _uncommonBits_T_317 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_317 = bits(_uncommonBits_T_317, 4, 0) node _T_3765 = shr(io.in.c.bits.source, 5) node _T_3766 = eq(_T_3765, UInt<4>(0ha)) node _T_3767 = leq(UInt<1>(0h0), uncommonBits_317) node _T_3768 = and(_T_3766, _T_3767) node _T_3769 = leq(uncommonBits_317, UInt<5>(0h1f)) node _T_3770 = and(_T_3768, _T_3769) node _uncommonBits_T_318 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_318 = bits(_uncommonBits_T_318, 4, 0) node _T_3771 = shr(io.in.c.bits.source, 5) node _T_3772 = eq(_T_3771, UInt<4>(0h9)) node _T_3773 = leq(UInt<1>(0h0), uncommonBits_318) node _T_3774 = and(_T_3772, _T_3773) node _T_3775 = leq(uncommonBits_318, UInt<5>(0h1f)) node _T_3776 = and(_T_3774, _T_3775) node _uncommonBits_T_319 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_319 = bits(_uncommonBits_T_319, 4, 0) node _T_3777 = shr(io.in.c.bits.source, 5) node _T_3778 = eq(_T_3777, UInt<4>(0h8)) node _T_3779 = leq(UInt<1>(0h0), uncommonBits_319) node _T_3780 = and(_T_3778, _T_3779) node _T_3781 = leq(uncommonBits_319, UInt<5>(0h1f)) node _T_3782 = and(_T_3780, _T_3781) node _uncommonBits_T_320 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_320 = bits(_uncommonBits_T_320, 1, 0) node _T_3783 = shr(io.in.c.bits.source, 2) node _T_3784 = eq(_T_3783, UInt<7>(0h7a)) node _T_3785 = leq(UInt<1>(0h0), uncommonBits_320) node _T_3786 = and(_T_3784, _T_3785) node _T_3787 = leq(uncommonBits_320, UInt<2>(0h3)) node _T_3788 = and(_T_3786, _T_3787) node _uncommonBits_T_321 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_321 = bits(_uncommonBits_T_321, 1, 0) node _T_3789 = shr(io.in.c.bits.source, 2) node _T_3790 = eq(_T_3789, UInt<7>(0h79)) node _T_3791 = leq(UInt<1>(0h0), uncommonBits_321) node _T_3792 = and(_T_3790, _T_3791) node _T_3793 = leq(uncommonBits_321, UInt<2>(0h3)) node _T_3794 = and(_T_3792, _T_3793) node _uncommonBits_T_322 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_322 = bits(_uncommonBits_T_322, 4, 0) node _T_3795 = shr(io.in.c.bits.source, 5) node _T_3796 = eq(_T_3795, UInt<3>(0h7)) node _T_3797 = leq(UInt<1>(0h0), uncommonBits_322) node _T_3798 = and(_T_3796, _T_3797) node _T_3799 = leq(uncommonBits_322, UInt<5>(0h1f)) node _T_3800 = and(_T_3798, _T_3799) node _uncommonBits_T_323 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_323 = bits(_uncommonBits_T_323, 4, 0) node _T_3801 = shr(io.in.c.bits.source, 5) node _T_3802 = eq(_T_3801, UInt<3>(0h6)) node _T_3803 = leq(UInt<1>(0h0), uncommonBits_323) node _T_3804 = and(_T_3802, _T_3803) node _T_3805 = leq(uncommonBits_323, UInt<5>(0h1f)) node _T_3806 = and(_T_3804, _T_3805) node _uncommonBits_T_324 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_324 = bits(_uncommonBits_T_324, 4, 0) node _T_3807 = shr(io.in.c.bits.source, 5) node _T_3808 = eq(_T_3807, UInt<3>(0h5)) node _T_3809 = leq(UInt<1>(0h0), uncommonBits_324) node _T_3810 = and(_T_3808, _T_3809) node _T_3811 = leq(uncommonBits_324, UInt<5>(0h1f)) node _T_3812 = and(_T_3810, _T_3811) node _uncommonBits_T_325 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_325 = bits(_uncommonBits_T_325, 4, 0) node _T_3813 = shr(io.in.c.bits.source, 5) node _T_3814 = eq(_T_3813, UInt<3>(0h4)) node _T_3815 = leq(UInt<1>(0h0), uncommonBits_325) node _T_3816 = and(_T_3814, _T_3815) node _T_3817 = leq(uncommonBits_325, UInt<5>(0h1f)) node _T_3818 = and(_T_3816, _T_3817) node _uncommonBits_T_326 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_326 = bits(_uncommonBits_T_326, 4, 0) node _T_3819 = shr(io.in.c.bits.source, 5) node _T_3820 = eq(_T_3819, UInt<2>(0h3)) node _T_3821 = leq(UInt<1>(0h0), uncommonBits_326) node _T_3822 = and(_T_3820, _T_3821) node _T_3823 = leq(uncommonBits_326, UInt<5>(0h1f)) node _T_3824 = and(_T_3822, _T_3823) node _uncommonBits_T_327 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_327 = bits(_uncommonBits_T_327, 4, 0) node _T_3825 = shr(io.in.c.bits.source, 5) node _T_3826 = eq(_T_3825, UInt<2>(0h2)) node _T_3827 = leq(UInt<1>(0h0), uncommonBits_327) node _T_3828 = and(_T_3826, _T_3827) node _T_3829 = leq(uncommonBits_327, UInt<5>(0h1f)) node _T_3830 = and(_T_3828, _T_3829) node _uncommonBits_T_328 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_328 = bits(_uncommonBits_T_328, 4, 0) node _T_3831 = shr(io.in.c.bits.source, 5) node _T_3832 = eq(_T_3831, UInt<1>(0h1)) node _T_3833 = leq(UInt<1>(0h0), uncommonBits_328) node _T_3834 = and(_T_3832, _T_3833) node _T_3835 = leq(uncommonBits_328, UInt<5>(0h1f)) node _T_3836 = and(_T_3834, _T_3835) node _uncommonBits_T_329 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_329 = bits(_uncommonBits_T_329, 4, 0) node _T_3837 = shr(io.in.c.bits.source, 5) node _T_3838 = eq(_T_3837, UInt<1>(0h0)) node _T_3839 = leq(UInt<1>(0h0), uncommonBits_329) node _T_3840 = and(_T_3838, _T_3839) node _T_3841 = leq(uncommonBits_329, UInt<5>(0h1f)) node _T_3842 = and(_T_3840, _T_3841) node _T_3843 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_3844 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_3845 = or(_T_3710, _T_3716) node _T_3846 = or(_T_3845, _T_3722) node _T_3847 = or(_T_3846, _T_3728) node _T_3848 = or(_T_3847, _T_3734) node _T_3849 = or(_T_3848, _T_3740) node _T_3850 = or(_T_3849, _T_3746) node _T_3851 = or(_T_3850, _T_3752) node _T_3852 = or(_T_3851, _T_3758) node _T_3853 = or(_T_3852, _T_3764) node _T_3854 = or(_T_3853, _T_3770) node _T_3855 = or(_T_3854, _T_3776) node _T_3856 = or(_T_3855, _T_3782) node _T_3857 = or(_T_3856, _T_3788) node _T_3858 = or(_T_3857, _T_3794) node _T_3859 = or(_T_3858, _T_3800) node _T_3860 = or(_T_3859, _T_3806) node _T_3861 = or(_T_3860, _T_3812) node _T_3862 = or(_T_3861, _T_3818) node _T_3863 = or(_T_3862, _T_3824) node _T_3864 = or(_T_3863, _T_3830) node _T_3865 = or(_T_3864, _T_3836) node _T_3866 = or(_T_3865, _T_3842) node _T_3867 = or(_T_3866, _T_3843) node _T_3868 = or(_T_3867, _T_3844) node _T_3869 = and(_T_3709, _T_3868) node _T_3870 = or(UInt<1>(0h0), _T_3869) node _T_3871 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3872 = or(UInt<1>(0h0), _T_3871) node _T_3873 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_3874 = cvt(_T_3873) node _T_3875 = and(_T_3874, asSInt(UInt<17>(0h10000))) node _T_3876 = asSInt(_T_3875) node _T_3877 = eq(_T_3876, asSInt(UInt<1>(0h0))) node _T_3878 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_3879 = cvt(_T_3878) node _T_3880 = and(_T_3879, asSInt(UInt<29>(0h10000000))) node _T_3881 = asSInt(_T_3880) node _T_3882 = eq(_T_3881, asSInt(UInt<1>(0h0))) node _T_3883 = or(_T_3877, _T_3882) node _T_3884 = and(_T_3872, _T_3883) node _T_3885 = or(UInt<1>(0h0), _T_3884) node _T_3886 = and(_T_3870, _T_3885) node _T_3887 = asUInt(reset) node _T_3888 = eq(_T_3887, UInt<1>(0h0)) when _T_3888 : node _T_3889 = eq(_T_3886, UInt<1>(0h0)) when _T_3889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_3886, UInt<1>(0h1), "") : assert_143 node _T_3890 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_330 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_330 = bits(_uncommonBits_T_330, 1, 0) node _T_3891 = shr(io.in.c.bits.source, 2) node _T_3892 = eq(_T_3891, UInt<7>(0h70)) node _T_3893 = leq(UInt<1>(0h0), uncommonBits_330) node _T_3894 = and(_T_3892, _T_3893) node _T_3895 = leq(uncommonBits_330, UInt<2>(0h3)) node _T_3896 = and(_T_3894, _T_3895) node _uncommonBits_T_331 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_331 = bits(_uncommonBits_T_331, 1, 0) node _T_3897 = shr(io.in.c.bits.source, 2) node _T_3898 = eq(_T_3897, UInt<7>(0h71)) node _T_3899 = leq(UInt<1>(0h0), uncommonBits_331) node _T_3900 = and(_T_3898, _T_3899) node _T_3901 = leq(uncommonBits_331, UInt<2>(0h3)) node _T_3902 = and(_T_3900, _T_3901) node _uncommonBits_T_332 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_332 = bits(_uncommonBits_T_332, 1, 0) node _T_3903 = shr(io.in.c.bits.source, 2) node _T_3904 = eq(_T_3903, UInt<7>(0h72)) node _T_3905 = leq(UInt<1>(0h0), uncommonBits_332) node _T_3906 = and(_T_3904, _T_3905) node _T_3907 = leq(uncommonBits_332, UInt<2>(0h3)) node _T_3908 = and(_T_3906, _T_3907) node _uncommonBits_T_333 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_333 = bits(_uncommonBits_T_333, 1, 0) node _T_3909 = shr(io.in.c.bits.source, 2) node _T_3910 = eq(_T_3909, UInt<7>(0h73)) node _T_3911 = leq(UInt<1>(0h0), uncommonBits_333) node _T_3912 = and(_T_3910, _T_3911) node _T_3913 = leq(uncommonBits_333, UInt<2>(0h3)) node _T_3914 = and(_T_3912, _T_3913) node _uncommonBits_T_334 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_334 = bits(_uncommonBits_T_334, 1, 0) node _T_3915 = shr(io.in.c.bits.source, 2) node _T_3916 = eq(_T_3915, UInt<7>(0h7c)) node _T_3917 = leq(UInt<1>(0h0), uncommonBits_334) node _T_3918 = and(_T_3916, _T_3917) node _T_3919 = leq(uncommonBits_334, UInt<2>(0h3)) node _T_3920 = and(_T_3918, _T_3919) node _uncommonBits_T_335 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_335 = bits(_uncommonBits_T_335, 1, 0) node _T_3921 = shr(io.in.c.bits.source, 2) node _T_3922 = eq(_T_3921, UInt<7>(0h7b)) node _T_3923 = leq(UInt<1>(0h0), uncommonBits_335) node _T_3924 = and(_T_3922, _T_3923) node _T_3925 = leq(uncommonBits_335, UInt<2>(0h3)) node _T_3926 = and(_T_3924, _T_3925) node _uncommonBits_T_336 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_336 = bits(_uncommonBits_T_336, 4, 0) node _T_3927 = shr(io.in.c.bits.source, 5) node _T_3928 = eq(_T_3927, UInt<4>(0hd)) node _T_3929 = leq(UInt<1>(0h0), uncommonBits_336) node _T_3930 = and(_T_3928, _T_3929) node _T_3931 = leq(uncommonBits_336, UInt<5>(0h1f)) node _T_3932 = and(_T_3930, _T_3931) node _uncommonBits_T_337 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_337 = bits(_uncommonBits_T_337, 4, 0) node _T_3933 = shr(io.in.c.bits.source, 5) node _T_3934 = eq(_T_3933, UInt<4>(0hc)) node _T_3935 = leq(UInt<1>(0h0), uncommonBits_337) node _T_3936 = and(_T_3934, _T_3935) node _T_3937 = leq(uncommonBits_337, UInt<5>(0h1f)) node _T_3938 = and(_T_3936, _T_3937) node _uncommonBits_T_338 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_338 = bits(_uncommonBits_T_338, 4, 0) node _T_3939 = shr(io.in.c.bits.source, 5) node _T_3940 = eq(_T_3939, UInt<4>(0hb)) node _T_3941 = leq(UInt<1>(0h0), uncommonBits_338) node _T_3942 = and(_T_3940, _T_3941) node _T_3943 = leq(uncommonBits_338, UInt<5>(0h1f)) node _T_3944 = and(_T_3942, _T_3943) node _uncommonBits_T_339 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_339 = bits(_uncommonBits_T_339, 4, 0) node _T_3945 = shr(io.in.c.bits.source, 5) node _T_3946 = eq(_T_3945, UInt<4>(0ha)) node _T_3947 = leq(UInt<1>(0h0), uncommonBits_339) node _T_3948 = and(_T_3946, _T_3947) node _T_3949 = leq(uncommonBits_339, UInt<5>(0h1f)) node _T_3950 = and(_T_3948, _T_3949) node _uncommonBits_T_340 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_340 = bits(_uncommonBits_T_340, 4, 0) node _T_3951 = shr(io.in.c.bits.source, 5) node _T_3952 = eq(_T_3951, UInt<4>(0h9)) node _T_3953 = leq(UInt<1>(0h0), uncommonBits_340) node _T_3954 = and(_T_3952, _T_3953) node _T_3955 = leq(uncommonBits_340, UInt<5>(0h1f)) node _T_3956 = and(_T_3954, _T_3955) node _uncommonBits_T_341 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_341 = bits(_uncommonBits_T_341, 4, 0) node _T_3957 = shr(io.in.c.bits.source, 5) node _T_3958 = eq(_T_3957, UInt<4>(0h8)) node _T_3959 = leq(UInt<1>(0h0), uncommonBits_341) node _T_3960 = and(_T_3958, _T_3959) node _T_3961 = leq(uncommonBits_341, UInt<5>(0h1f)) node _T_3962 = and(_T_3960, _T_3961) node _uncommonBits_T_342 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_342 = bits(_uncommonBits_T_342, 1, 0) node _T_3963 = shr(io.in.c.bits.source, 2) node _T_3964 = eq(_T_3963, UInt<7>(0h7a)) node _T_3965 = leq(UInt<1>(0h0), uncommonBits_342) node _T_3966 = and(_T_3964, _T_3965) node _T_3967 = leq(uncommonBits_342, UInt<2>(0h3)) node _T_3968 = and(_T_3966, _T_3967) node _uncommonBits_T_343 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_343 = bits(_uncommonBits_T_343, 1, 0) node _T_3969 = shr(io.in.c.bits.source, 2) node _T_3970 = eq(_T_3969, UInt<7>(0h79)) node _T_3971 = leq(UInt<1>(0h0), uncommonBits_343) node _T_3972 = and(_T_3970, _T_3971) node _T_3973 = leq(uncommonBits_343, UInt<2>(0h3)) node _T_3974 = and(_T_3972, _T_3973) node _uncommonBits_T_344 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_344 = bits(_uncommonBits_T_344, 4, 0) node _T_3975 = shr(io.in.c.bits.source, 5) node _T_3976 = eq(_T_3975, UInt<3>(0h7)) node _T_3977 = leq(UInt<1>(0h0), uncommonBits_344) node _T_3978 = and(_T_3976, _T_3977) node _T_3979 = leq(uncommonBits_344, UInt<5>(0h1f)) node _T_3980 = and(_T_3978, _T_3979) node _uncommonBits_T_345 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_345 = bits(_uncommonBits_T_345, 4, 0) node _T_3981 = shr(io.in.c.bits.source, 5) node _T_3982 = eq(_T_3981, UInt<3>(0h6)) node _T_3983 = leq(UInt<1>(0h0), uncommonBits_345) node _T_3984 = and(_T_3982, _T_3983) node _T_3985 = leq(uncommonBits_345, UInt<5>(0h1f)) node _T_3986 = and(_T_3984, _T_3985) node _uncommonBits_T_346 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_346 = bits(_uncommonBits_T_346, 4, 0) node _T_3987 = shr(io.in.c.bits.source, 5) node _T_3988 = eq(_T_3987, UInt<3>(0h5)) node _T_3989 = leq(UInt<1>(0h0), uncommonBits_346) node _T_3990 = and(_T_3988, _T_3989) node _T_3991 = leq(uncommonBits_346, UInt<5>(0h1f)) node _T_3992 = and(_T_3990, _T_3991) node _uncommonBits_T_347 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_347 = bits(_uncommonBits_T_347, 4, 0) node _T_3993 = shr(io.in.c.bits.source, 5) node _T_3994 = eq(_T_3993, UInt<3>(0h4)) node _T_3995 = leq(UInt<1>(0h0), uncommonBits_347) node _T_3996 = and(_T_3994, _T_3995) node _T_3997 = leq(uncommonBits_347, UInt<5>(0h1f)) node _T_3998 = and(_T_3996, _T_3997) node _uncommonBits_T_348 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_348 = bits(_uncommonBits_T_348, 4, 0) node _T_3999 = shr(io.in.c.bits.source, 5) node _T_4000 = eq(_T_3999, UInt<2>(0h3)) node _T_4001 = leq(UInt<1>(0h0), uncommonBits_348) node _T_4002 = and(_T_4000, _T_4001) node _T_4003 = leq(uncommonBits_348, UInt<5>(0h1f)) node _T_4004 = and(_T_4002, _T_4003) node _uncommonBits_T_349 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_349 = bits(_uncommonBits_T_349, 4, 0) node _T_4005 = shr(io.in.c.bits.source, 5) node _T_4006 = eq(_T_4005, UInt<2>(0h2)) node _T_4007 = leq(UInt<1>(0h0), uncommonBits_349) node _T_4008 = and(_T_4006, _T_4007) node _T_4009 = leq(uncommonBits_349, UInt<5>(0h1f)) node _T_4010 = and(_T_4008, _T_4009) node _uncommonBits_T_350 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_350 = bits(_uncommonBits_T_350, 4, 0) node _T_4011 = shr(io.in.c.bits.source, 5) node _T_4012 = eq(_T_4011, UInt<1>(0h1)) node _T_4013 = leq(UInt<1>(0h0), uncommonBits_350) node _T_4014 = and(_T_4012, _T_4013) node _T_4015 = leq(uncommonBits_350, UInt<5>(0h1f)) node _T_4016 = and(_T_4014, _T_4015) node _uncommonBits_T_351 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_351 = bits(_uncommonBits_T_351, 4, 0) node _T_4017 = shr(io.in.c.bits.source, 5) node _T_4018 = eq(_T_4017, UInt<1>(0h0)) node _T_4019 = leq(UInt<1>(0h0), uncommonBits_351) node _T_4020 = and(_T_4018, _T_4019) node _T_4021 = leq(uncommonBits_351, UInt<5>(0h1f)) node _T_4022 = and(_T_4020, _T_4021) node _T_4023 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4024 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _WIRE_6 : UInt<1>[25] connect _WIRE_6[0], _T_3890 connect _WIRE_6[1], _T_3896 connect _WIRE_6[2], _T_3902 connect _WIRE_6[3], _T_3908 connect _WIRE_6[4], _T_3914 connect _WIRE_6[5], _T_3920 connect _WIRE_6[6], _T_3926 connect _WIRE_6[7], _T_3932 connect _WIRE_6[8], _T_3938 connect _WIRE_6[9], _T_3944 connect _WIRE_6[10], _T_3950 connect _WIRE_6[11], _T_3956 connect _WIRE_6[12], _T_3962 connect _WIRE_6[13], _T_3968 connect _WIRE_6[14], _T_3974 connect _WIRE_6[15], _T_3980 connect _WIRE_6[16], _T_3986 connect _WIRE_6[17], _T_3992 connect _WIRE_6[18], _T_3998 connect _WIRE_6[19], _T_4004 connect _WIRE_6[20], _T_4010 connect _WIRE_6[21], _T_4016 connect _WIRE_6[22], _T_4022 connect _WIRE_6[23], _T_4023 connect _WIRE_6[24], _T_4024 node _T_4025 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4026 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_4027 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_4028 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_4029 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_4030 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_4031 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_4032 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_4033 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_4034 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_4035 = mux(_WIRE_6[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_4036 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_4037 = mux(_WIRE_6[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_4038 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_4039 = mux(_WIRE_6[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_4040 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_4041 = mux(_WIRE_6[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_4042 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_4043 = mux(_WIRE_6[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_4044 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_4045 = mux(_WIRE_6[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_4046 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_4047 = mux(_WIRE_6[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_4048 = mux(_WIRE_6[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_4049 = mux(_WIRE_6[23], _T_4025, UInt<1>(0h0)) node _T_4050 = mux(_WIRE_6[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_4051 = or(_T_4026, _T_4027) node _T_4052 = or(_T_4051, _T_4028) node _T_4053 = or(_T_4052, _T_4029) node _T_4054 = or(_T_4053, _T_4030) node _T_4055 = or(_T_4054, _T_4031) node _T_4056 = or(_T_4055, _T_4032) node _T_4057 = or(_T_4056, _T_4033) node _T_4058 = or(_T_4057, _T_4034) node _T_4059 = or(_T_4058, _T_4035) node _T_4060 = or(_T_4059, _T_4036) node _T_4061 = or(_T_4060, _T_4037) node _T_4062 = or(_T_4061, _T_4038) node _T_4063 = or(_T_4062, _T_4039) node _T_4064 = or(_T_4063, _T_4040) node _T_4065 = or(_T_4064, _T_4041) node _T_4066 = or(_T_4065, _T_4042) node _T_4067 = or(_T_4066, _T_4043) node _T_4068 = or(_T_4067, _T_4044) node _T_4069 = or(_T_4068, _T_4045) node _T_4070 = or(_T_4069, _T_4046) node _T_4071 = or(_T_4070, _T_4047) node _T_4072 = or(_T_4071, _T_4048) node _T_4073 = or(_T_4072, _T_4049) node _T_4074 = or(_T_4073, _T_4050) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_4074 node _T_4075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4077 = and(_T_4075, _T_4076) node _T_4078 = or(UInt<1>(0h0), _T_4077) node _T_4079 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4080 = cvt(_T_4079) node _T_4081 = and(_T_4080, asSInt(UInt<17>(0h10000))) node _T_4082 = asSInt(_T_4081) node _T_4083 = eq(_T_4082, asSInt(UInt<1>(0h0))) node _T_4084 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4085 = cvt(_T_4084) node _T_4086 = and(_T_4085, asSInt(UInt<29>(0h10000000))) node _T_4087 = asSInt(_T_4086) node _T_4088 = eq(_T_4087, asSInt(UInt<1>(0h0))) node _T_4089 = or(_T_4083, _T_4088) node _T_4090 = and(_T_4078, _T_4089) node _T_4091 = or(UInt<1>(0h0), _T_4090) node _T_4092 = and(_WIRE_7, _T_4091) node _T_4093 = asUInt(reset) node _T_4094 = eq(_T_4093, UInt<1>(0h0)) when _T_4094 : node _T_4095 = eq(_T_4092, UInt<1>(0h0)) when _T_4095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_4092, UInt<1>(0h1), "") : assert_144 node _T_4096 = asUInt(reset) node _T_4097 = eq(_T_4096, UInt<1>(0h0)) when _T_4097 : node _T_4098 = eq(source_ok_2, UInt<1>(0h0)) when _T_4098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_4099 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_4100 = asUInt(reset) node _T_4101 = eq(_T_4100, UInt<1>(0h0)) when _T_4101 : node _T_4102 = eq(_T_4099, UInt<1>(0h0)) when _T_4102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_4099, UInt<1>(0h1), "") : assert_146 node _T_4103 = asUInt(reset) node _T_4104 = eq(_T_4103, UInt<1>(0h0)) when _T_4104 : node _T_4105 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_4106 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_4107 = asUInt(reset) node _T_4108 = eq(_T_4107, UInt<1>(0h0)) when _T_4108 : node _T_4109 = eq(_T_4106, UInt<1>(0h0)) when _T_4109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_4106, UInt<1>(0h1), "") : assert_148 node _T_4110 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4111 = asUInt(reset) node _T_4112 = eq(_T_4111, UInt<1>(0h0)) when _T_4112 : node _T_4113 = eq(_T_4110, UInt<1>(0h0)) when _T_4113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_4110, UInt<1>(0h1), "") : assert_149 node _T_4114 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_4114 : node _T_4115 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4116 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4117 = and(_T_4115, _T_4116) node _T_4118 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_352 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_352 = bits(_uncommonBits_T_352, 1, 0) node _T_4119 = shr(io.in.c.bits.source, 2) node _T_4120 = eq(_T_4119, UInt<7>(0h70)) node _T_4121 = leq(UInt<1>(0h0), uncommonBits_352) node _T_4122 = and(_T_4120, _T_4121) node _T_4123 = leq(uncommonBits_352, UInt<2>(0h3)) node _T_4124 = and(_T_4122, _T_4123) node _uncommonBits_T_353 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_353 = bits(_uncommonBits_T_353, 1, 0) node _T_4125 = shr(io.in.c.bits.source, 2) node _T_4126 = eq(_T_4125, UInt<7>(0h71)) node _T_4127 = leq(UInt<1>(0h0), uncommonBits_353) node _T_4128 = and(_T_4126, _T_4127) node _T_4129 = leq(uncommonBits_353, UInt<2>(0h3)) node _T_4130 = and(_T_4128, _T_4129) node _uncommonBits_T_354 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_354 = bits(_uncommonBits_T_354, 1, 0) node _T_4131 = shr(io.in.c.bits.source, 2) node _T_4132 = eq(_T_4131, UInt<7>(0h72)) node _T_4133 = leq(UInt<1>(0h0), uncommonBits_354) node _T_4134 = and(_T_4132, _T_4133) node _T_4135 = leq(uncommonBits_354, UInt<2>(0h3)) node _T_4136 = and(_T_4134, _T_4135) node _uncommonBits_T_355 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_355 = bits(_uncommonBits_T_355, 1, 0) node _T_4137 = shr(io.in.c.bits.source, 2) node _T_4138 = eq(_T_4137, UInt<7>(0h73)) node _T_4139 = leq(UInt<1>(0h0), uncommonBits_355) node _T_4140 = and(_T_4138, _T_4139) node _T_4141 = leq(uncommonBits_355, UInt<2>(0h3)) node _T_4142 = and(_T_4140, _T_4141) node _uncommonBits_T_356 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_356 = bits(_uncommonBits_T_356, 1, 0) node _T_4143 = shr(io.in.c.bits.source, 2) node _T_4144 = eq(_T_4143, UInt<7>(0h7c)) node _T_4145 = leq(UInt<1>(0h0), uncommonBits_356) node _T_4146 = and(_T_4144, _T_4145) node _T_4147 = leq(uncommonBits_356, UInt<2>(0h3)) node _T_4148 = and(_T_4146, _T_4147) node _uncommonBits_T_357 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_357 = bits(_uncommonBits_T_357, 1, 0) node _T_4149 = shr(io.in.c.bits.source, 2) node _T_4150 = eq(_T_4149, UInt<7>(0h7b)) node _T_4151 = leq(UInt<1>(0h0), uncommonBits_357) node _T_4152 = and(_T_4150, _T_4151) node _T_4153 = leq(uncommonBits_357, UInt<2>(0h3)) node _T_4154 = and(_T_4152, _T_4153) node _uncommonBits_T_358 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_358 = bits(_uncommonBits_T_358, 4, 0) node _T_4155 = shr(io.in.c.bits.source, 5) node _T_4156 = eq(_T_4155, UInt<4>(0hd)) node _T_4157 = leq(UInt<1>(0h0), uncommonBits_358) node _T_4158 = and(_T_4156, _T_4157) node _T_4159 = leq(uncommonBits_358, UInt<5>(0h1f)) node _T_4160 = and(_T_4158, _T_4159) node _uncommonBits_T_359 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_359 = bits(_uncommonBits_T_359, 4, 0) node _T_4161 = shr(io.in.c.bits.source, 5) node _T_4162 = eq(_T_4161, UInt<4>(0hc)) node _T_4163 = leq(UInt<1>(0h0), uncommonBits_359) node _T_4164 = and(_T_4162, _T_4163) node _T_4165 = leq(uncommonBits_359, UInt<5>(0h1f)) node _T_4166 = and(_T_4164, _T_4165) node _uncommonBits_T_360 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_360 = bits(_uncommonBits_T_360, 4, 0) node _T_4167 = shr(io.in.c.bits.source, 5) node _T_4168 = eq(_T_4167, UInt<4>(0hb)) node _T_4169 = leq(UInt<1>(0h0), uncommonBits_360) node _T_4170 = and(_T_4168, _T_4169) node _T_4171 = leq(uncommonBits_360, UInt<5>(0h1f)) node _T_4172 = and(_T_4170, _T_4171) node _uncommonBits_T_361 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_361 = bits(_uncommonBits_T_361, 4, 0) node _T_4173 = shr(io.in.c.bits.source, 5) node _T_4174 = eq(_T_4173, UInt<4>(0ha)) node _T_4175 = leq(UInt<1>(0h0), uncommonBits_361) node _T_4176 = and(_T_4174, _T_4175) node _T_4177 = leq(uncommonBits_361, UInt<5>(0h1f)) node _T_4178 = and(_T_4176, _T_4177) node _uncommonBits_T_362 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_362 = bits(_uncommonBits_T_362, 4, 0) node _T_4179 = shr(io.in.c.bits.source, 5) node _T_4180 = eq(_T_4179, UInt<4>(0h9)) node _T_4181 = leq(UInt<1>(0h0), uncommonBits_362) node _T_4182 = and(_T_4180, _T_4181) node _T_4183 = leq(uncommonBits_362, UInt<5>(0h1f)) node _T_4184 = and(_T_4182, _T_4183) node _uncommonBits_T_363 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_363 = bits(_uncommonBits_T_363, 4, 0) node _T_4185 = shr(io.in.c.bits.source, 5) node _T_4186 = eq(_T_4185, UInt<4>(0h8)) node _T_4187 = leq(UInt<1>(0h0), uncommonBits_363) node _T_4188 = and(_T_4186, _T_4187) node _T_4189 = leq(uncommonBits_363, UInt<5>(0h1f)) node _T_4190 = and(_T_4188, _T_4189) node _uncommonBits_T_364 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_364 = bits(_uncommonBits_T_364, 1, 0) node _T_4191 = shr(io.in.c.bits.source, 2) node _T_4192 = eq(_T_4191, UInt<7>(0h7a)) node _T_4193 = leq(UInt<1>(0h0), uncommonBits_364) node _T_4194 = and(_T_4192, _T_4193) node _T_4195 = leq(uncommonBits_364, UInt<2>(0h3)) node _T_4196 = and(_T_4194, _T_4195) node _uncommonBits_T_365 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_365 = bits(_uncommonBits_T_365, 1, 0) node _T_4197 = shr(io.in.c.bits.source, 2) node _T_4198 = eq(_T_4197, UInt<7>(0h79)) node _T_4199 = leq(UInt<1>(0h0), uncommonBits_365) node _T_4200 = and(_T_4198, _T_4199) node _T_4201 = leq(uncommonBits_365, UInt<2>(0h3)) node _T_4202 = and(_T_4200, _T_4201) node _uncommonBits_T_366 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_366 = bits(_uncommonBits_T_366, 4, 0) node _T_4203 = shr(io.in.c.bits.source, 5) node _T_4204 = eq(_T_4203, UInt<3>(0h7)) node _T_4205 = leq(UInt<1>(0h0), uncommonBits_366) node _T_4206 = and(_T_4204, _T_4205) node _T_4207 = leq(uncommonBits_366, UInt<5>(0h1f)) node _T_4208 = and(_T_4206, _T_4207) node _uncommonBits_T_367 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_367 = bits(_uncommonBits_T_367, 4, 0) node _T_4209 = shr(io.in.c.bits.source, 5) node _T_4210 = eq(_T_4209, UInt<3>(0h6)) node _T_4211 = leq(UInt<1>(0h0), uncommonBits_367) node _T_4212 = and(_T_4210, _T_4211) node _T_4213 = leq(uncommonBits_367, UInt<5>(0h1f)) node _T_4214 = and(_T_4212, _T_4213) node _uncommonBits_T_368 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_368 = bits(_uncommonBits_T_368, 4, 0) node _T_4215 = shr(io.in.c.bits.source, 5) node _T_4216 = eq(_T_4215, UInt<3>(0h5)) node _T_4217 = leq(UInt<1>(0h0), uncommonBits_368) node _T_4218 = and(_T_4216, _T_4217) node _T_4219 = leq(uncommonBits_368, UInt<5>(0h1f)) node _T_4220 = and(_T_4218, _T_4219) node _uncommonBits_T_369 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_369 = bits(_uncommonBits_T_369, 4, 0) node _T_4221 = shr(io.in.c.bits.source, 5) node _T_4222 = eq(_T_4221, UInt<3>(0h4)) node _T_4223 = leq(UInt<1>(0h0), uncommonBits_369) node _T_4224 = and(_T_4222, _T_4223) node _T_4225 = leq(uncommonBits_369, UInt<5>(0h1f)) node _T_4226 = and(_T_4224, _T_4225) node _uncommonBits_T_370 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_370 = bits(_uncommonBits_T_370, 4, 0) node _T_4227 = shr(io.in.c.bits.source, 5) node _T_4228 = eq(_T_4227, UInt<2>(0h3)) node _T_4229 = leq(UInt<1>(0h0), uncommonBits_370) node _T_4230 = and(_T_4228, _T_4229) node _T_4231 = leq(uncommonBits_370, UInt<5>(0h1f)) node _T_4232 = and(_T_4230, _T_4231) node _uncommonBits_T_371 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_371 = bits(_uncommonBits_T_371, 4, 0) node _T_4233 = shr(io.in.c.bits.source, 5) node _T_4234 = eq(_T_4233, UInt<2>(0h2)) node _T_4235 = leq(UInt<1>(0h0), uncommonBits_371) node _T_4236 = and(_T_4234, _T_4235) node _T_4237 = leq(uncommonBits_371, UInt<5>(0h1f)) node _T_4238 = and(_T_4236, _T_4237) node _uncommonBits_T_372 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_372 = bits(_uncommonBits_T_372, 4, 0) node _T_4239 = shr(io.in.c.bits.source, 5) node _T_4240 = eq(_T_4239, UInt<1>(0h1)) node _T_4241 = leq(UInt<1>(0h0), uncommonBits_372) node _T_4242 = and(_T_4240, _T_4241) node _T_4243 = leq(uncommonBits_372, UInt<5>(0h1f)) node _T_4244 = and(_T_4242, _T_4243) node _uncommonBits_T_373 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_373 = bits(_uncommonBits_T_373, 4, 0) node _T_4245 = shr(io.in.c.bits.source, 5) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) node _T_4247 = leq(UInt<1>(0h0), uncommonBits_373) node _T_4248 = and(_T_4246, _T_4247) node _T_4249 = leq(uncommonBits_373, UInt<5>(0h1f)) node _T_4250 = and(_T_4248, _T_4249) node _T_4251 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4252 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_4253 = or(_T_4118, _T_4124) node _T_4254 = or(_T_4253, _T_4130) node _T_4255 = or(_T_4254, _T_4136) node _T_4256 = or(_T_4255, _T_4142) node _T_4257 = or(_T_4256, _T_4148) node _T_4258 = or(_T_4257, _T_4154) node _T_4259 = or(_T_4258, _T_4160) node _T_4260 = or(_T_4259, _T_4166) node _T_4261 = or(_T_4260, _T_4172) node _T_4262 = or(_T_4261, _T_4178) node _T_4263 = or(_T_4262, _T_4184) node _T_4264 = or(_T_4263, _T_4190) node _T_4265 = or(_T_4264, _T_4196) node _T_4266 = or(_T_4265, _T_4202) node _T_4267 = or(_T_4266, _T_4208) node _T_4268 = or(_T_4267, _T_4214) node _T_4269 = or(_T_4268, _T_4220) node _T_4270 = or(_T_4269, _T_4226) node _T_4271 = or(_T_4270, _T_4232) node _T_4272 = or(_T_4271, _T_4238) node _T_4273 = or(_T_4272, _T_4244) node _T_4274 = or(_T_4273, _T_4250) node _T_4275 = or(_T_4274, _T_4251) node _T_4276 = or(_T_4275, _T_4252) node _T_4277 = and(_T_4117, _T_4276) node _T_4278 = or(UInt<1>(0h0), _T_4277) node _T_4279 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4280 = or(UInt<1>(0h0), _T_4279) node _T_4281 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4282 = cvt(_T_4281) node _T_4283 = and(_T_4282, asSInt(UInt<17>(0h10000))) node _T_4284 = asSInt(_T_4283) node _T_4285 = eq(_T_4284, asSInt(UInt<1>(0h0))) node _T_4286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4287 = cvt(_T_4286) node _T_4288 = and(_T_4287, asSInt(UInt<29>(0h10000000))) node _T_4289 = asSInt(_T_4288) node _T_4290 = eq(_T_4289, asSInt(UInt<1>(0h0))) node _T_4291 = or(_T_4285, _T_4290) node _T_4292 = and(_T_4280, _T_4291) node _T_4293 = or(UInt<1>(0h0), _T_4292) node _T_4294 = and(_T_4278, _T_4293) node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : node _T_4297 = eq(_T_4294, UInt<1>(0h0)) when _T_4297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_4294, UInt<1>(0h1), "") : assert_150 node _T_4298 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_374 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_374 = bits(_uncommonBits_T_374, 1, 0) node _T_4299 = shr(io.in.c.bits.source, 2) node _T_4300 = eq(_T_4299, UInt<7>(0h70)) node _T_4301 = leq(UInt<1>(0h0), uncommonBits_374) node _T_4302 = and(_T_4300, _T_4301) node _T_4303 = leq(uncommonBits_374, UInt<2>(0h3)) node _T_4304 = and(_T_4302, _T_4303) node _uncommonBits_T_375 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_375 = bits(_uncommonBits_T_375, 1, 0) node _T_4305 = shr(io.in.c.bits.source, 2) node _T_4306 = eq(_T_4305, UInt<7>(0h71)) node _T_4307 = leq(UInt<1>(0h0), uncommonBits_375) node _T_4308 = and(_T_4306, _T_4307) node _T_4309 = leq(uncommonBits_375, UInt<2>(0h3)) node _T_4310 = and(_T_4308, _T_4309) node _uncommonBits_T_376 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_376 = bits(_uncommonBits_T_376, 1, 0) node _T_4311 = shr(io.in.c.bits.source, 2) node _T_4312 = eq(_T_4311, UInt<7>(0h72)) node _T_4313 = leq(UInt<1>(0h0), uncommonBits_376) node _T_4314 = and(_T_4312, _T_4313) node _T_4315 = leq(uncommonBits_376, UInt<2>(0h3)) node _T_4316 = and(_T_4314, _T_4315) node _uncommonBits_T_377 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_377 = bits(_uncommonBits_T_377, 1, 0) node _T_4317 = shr(io.in.c.bits.source, 2) node _T_4318 = eq(_T_4317, UInt<7>(0h73)) node _T_4319 = leq(UInt<1>(0h0), uncommonBits_377) node _T_4320 = and(_T_4318, _T_4319) node _T_4321 = leq(uncommonBits_377, UInt<2>(0h3)) node _T_4322 = and(_T_4320, _T_4321) node _uncommonBits_T_378 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_378 = bits(_uncommonBits_T_378, 1, 0) node _T_4323 = shr(io.in.c.bits.source, 2) node _T_4324 = eq(_T_4323, UInt<7>(0h7c)) node _T_4325 = leq(UInt<1>(0h0), uncommonBits_378) node _T_4326 = and(_T_4324, _T_4325) node _T_4327 = leq(uncommonBits_378, UInt<2>(0h3)) node _T_4328 = and(_T_4326, _T_4327) node _uncommonBits_T_379 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_379 = bits(_uncommonBits_T_379, 1, 0) node _T_4329 = shr(io.in.c.bits.source, 2) node _T_4330 = eq(_T_4329, UInt<7>(0h7b)) node _T_4331 = leq(UInt<1>(0h0), uncommonBits_379) node _T_4332 = and(_T_4330, _T_4331) node _T_4333 = leq(uncommonBits_379, UInt<2>(0h3)) node _T_4334 = and(_T_4332, _T_4333) node _uncommonBits_T_380 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_380 = bits(_uncommonBits_T_380, 4, 0) node _T_4335 = shr(io.in.c.bits.source, 5) node _T_4336 = eq(_T_4335, UInt<4>(0hd)) node _T_4337 = leq(UInt<1>(0h0), uncommonBits_380) node _T_4338 = and(_T_4336, _T_4337) node _T_4339 = leq(uncommonBits_380, UInt<5>(0h1f)) node _T_4340 = and(_T_4338, _T_4339) node _uncommonBits_T_381 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_381 = bits(_uncommonBits_T_381, 4, 0) node _T_4341 = shr(io.in.c.bits.source, 5) node _T_4342 = eq(_T_4341, UInt<4>(0hc)) node _T_4343 = leq(UInt<1>(0h0), uncommonBits_381) node _T_4344 = and(_T_4342, _T_4343) node _T_4345 = leq(uncommonBits_381, UInt<5>(0h1f)) node _T_4346 = and(_T_4344, _T_4345) node _uncommonBits_T_382 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_382 = bits(_uncommonBits_T_382, 4, 0) node _T_4347 = shr(io.in.c.bits.source, 5) node _T_4348 = eq(_T_4347, UInt<4>(0hb)) node _T_4349 = leq(UInt<1>(0h0), uncommonBits_382) node _T_4350 = and(_T_4348, _T_4349) node _T_4351 = leq(uncommonBits_382, UInt<5>(0h1f)) node _T_4352 = and(_T_4350, _T_4351) node _uncommonBits_T_383 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_383 = bits(_uncommonBits_T_383, 4, 0) node _T_4353 = shr(io.in.c.bits.source, 5) node _T_4354 = eq(_T_4353, UInt<4>(0ha)) node _T_4355 = leq(UInt<1>(0h0), uncommonBits_383) node _T_4356 = and(_T_4354, _T_4355) node _T_4357 = leq(uncommonBits_383, UInt<5>(0h1f)) node _T_4358 = and(_T_4356, _T_4357) node _uncommonBits_T_384 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_384 = bits(_uncommonBits_T_384, 4, 0) node _T_4359 = shr(io.in.c.bits.source, 5) node _T_4360 = eq(_T_4359, UInt<4>(0h9)) node _T_4361 = leq(UInt<1>(0h0), uncommonBits_384) node _T_4362 = and(_T_4360, _T_4361) node _T_4363 = leq(uncommonBits_384, UInt<5>(0h1f)) node _T_4364 = and(_T_4362, _T_4363) node _uncommonBits_T_385 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_385 = bits(_uncommonBits_T_385, 4, 0) node _T_4365 = shr(io.in.c.bits.source, 5) node _T_4366 = eq(_T_4365, UInt<4>(0h8)) node _T_4367 = leq(UInt<1>(0h0), uncommonBits_385) node _T_4368 = and(_T_4366, _T_4367) node _T_4369 = leq(uncommonBits_385, UInt<5>(0h1f)) node _T_4370 = and(_T_4368, _T_4369) node _uncommonBits_T_386 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_386 = bits(_uncommonBits_T_386, 1, 0) node _T_4371 = shr(io.in.c.bits.source, 2) node _T_4372 = eq(_T_4371, UInt<7>(0h7a)) node _T_4373 = leq(UInt<1>(0h0), uncommonBits_386) node _T_4374 = and(_T_4372, _T_4373) node _T_4375 = leq(uncommonBits_386, UInt<2>(0h3)) node _T_4376 = and(_T_4374, _T_4375) node _uncommonBits_T_387 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_387 = bits(_uncommonBits_T_387, 1, 0) node _T_4377 = shr(io.in.c.bits.source, 2) node _T_4378 = eq(_T_4377, UInt<7>(0h79)) node _T_4379 = leq(UInt<1>(0h0), uncommonBits_387) node _T_4380 = and(_T_4378, _T_4379) node _T_4381 = leq(uncommonBits_387, UInt<2>(0h3)) node _T_4382 = and(_T_4380, _T_4381) node _uncommonBits_T_388 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_388 = bits(_uncommonBits_T_388, 4, 0) node _T_4383 = shr(io.in.c.bits.source, 5) node _T_4384 = eq(_T_4383, UInt<3>(0h7)) node _T_4385 = leq(UInt<1>(0h0), uncommonBits_388) node _T_4386 = and(_T_4384, _T_4385) node _T_4387 = leq(uncommonBits_388, UInt<5>(0h1f)) node _T_4388 = and(_T_4386, _T_4387) node _uncommonBits_T_389 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_389 = bits(_uncommonBits_T_389, 4, 0) node _T_4389 = shr(io.in.c.bits.source, 5) node _T_4390 = eq(_T_4389, UInt<3>(0h6)) node _T_4391 = leq(UInt<1>(0h0), uncommonBits_389) node _T_4392 = and(_T_4390, _T_4391) node _T_4393 = leq(uncommonBits_389, UInt<5>(0h1f)) node _T_4394 = and(_T_4392, _T_4393) node _uncommonBits_T_390 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_390 = bits(_uncommonBits_T_390, 4, 0) node _T_4395 = shr(io.in.c.bits.source, 5) node _T_4396 = eq(_T_4395, UInt<3>(0h5)) node _T_4397 = leq(UInt<1>(0h0), uncommonBits_390) node _T_4398 = and(_T_4396, _T_4397) node _T_4399 = leq(uncommonBits_390, UInt<5>(0h1f)) node _T_4400 = and(_T_4398, _T_4399) node _uncommonBits_T_391 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_391 = bits(_uncommonBits_T_391, 4, 0) node _T_4401 = shr(io.in.c.bits.source, 5) node _T_4402 = eq(_T_4401, UInt<3>(0h4)) node _T_4403 = leq(UInt<1>(0h0), uncommonBits_391) node _T_4404 = and(_T_4402, _T_4403) node _T_4405 = leq(uncommonBits_391, UInt<5>(0h1f)) node _T_4406 = and(_T_4404, _T_4405) node _uncommonBits_T_392 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_392 = bits(_uncommonBits_T_392, 4, 0) node _T_4407 = shr(io.in.c.bits.source, 5) node _T_4408 = eq(_T_4407, UInt<2>(0h3)) node _T_4409 = leq(UInt<1>(0h0), uncommonBits_392) node _T_4410 = and(_T_4408, _T_4409) node _T_4411 = leq(uncommonBits_392, UInt<5>(0h1f)) node _T_4412 = and(_T_4410, _T_4411) node _uncommonBits_T_393 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_393 = bits(_uncommonBits_T_393, 4, 0) node _T_4413 = shr(io.in.c.bits.source, 5) node _T_4414 = eq(_T_4413, UInt<2>(0h2)) node _T_4415 = leq(UInt<1>(0h0), uncommonBits_393) node _T_4416 = and(_T_4414, _T_4415) node _T_4417 = leq(uncommonBits_393, UInt<5>(0h1f)) node _T_4418 = and(_T_4416, _T_4417) node _uncommonBits_T_394 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_394 = bits(_uncommonBits_T_394, 4, 0) node _T_4419 = shr(io.in.c.bits.source, 5) node _T_4420 = eq(_T_4419, UInt<1>(0h1)) node _T_4421 = leq(UInt<1>(0h0), uncommonBits_394) node _T_4422 = and(_T_4420, _T_4421) node _T_4423 = leq(uncommonBits_394, UInt<5>(0h1f)) node _T_4424 = and(_T_4422, _T_4423) node _uncommonBits_T_395 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_395 = bits(_uncommonBits_T_395, 4, 0) node _T_4425 = shr(io.in.c.bits.source, 5) node _T_4426 = eq(_T_4425, UInt<1>(0h0)) node _T_4427 = leq(UInt<1>(0h0), uncommonBits_395) node _T_4428 = and(_T_4426, _T_4427) node _T_4429 = leq(uncommonBits_395, UInt<5>(0h1f)) node _T_4430 = and(_T_4428, _T_4429) node _T_4431 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4432 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _WIRE_8 : UInt<1>[25] connect _WIRE_8[0], _T_4298 connect _WIRE_8[1], _T_4304 connect _WIRE_8[2], _T_4310 connect _WIRE_8[3], _T_4316 connect _WIRE_8[4], _T_4322 connect _WIRE_8[5], _T_4328 connect _WIRE_8[6], _T_4334 connect _WIRE_8[7], _T_4340 connect _WIRE_8[8], _T_4346 connect _WIRE_8[9], _T_4352 connect _WIRE_8[10], _T_4358 connect _WIRE_8[11], _T_4364 connect _WIRE_8[12], _T_4370 connect _WIRE_8[13], _T_4376 connect _WIRE_8[14], _T_4382 connect _WIRE_8[15], _T_4388 connect _WIRE_8[16], _T_4394 connect _WIRE_8[17], _T_4400 connect _WIRE_8[18], _T_4406 connect _WIRE_8[19], _T_4412 connect _WIRE_8[20], _T_4418 connect _WIRE_8[21], _T_4424 connect _WIRE_8[22], _T_4430 connect _WIRE_8[23], _T_4431 connect _WIRE_8[24], _T_4432 node _T_4433 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4434 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_4435 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_4436 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_4437 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_4438 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_4439 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_4440 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_4441 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_4442 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_4443 = mux(_WIRE_8[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_4444 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_4445 = mux(_WIRE_8[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_4446 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_4447 = mux(_WIRE_8[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_4448 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_4449 = mux(_WIRE_8[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_4450 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_4451 = mux(_WIRE_8[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_4452 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_4453 = mux(_WIRE_8[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_4454 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_4455 = mux(_WIRE_8[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_4456 = mux(_WIRE_8[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_4457 = mux(_WIRE_8[23], _T_4433, UInt<1>(0h0)) node _T_4458 = mux(_WIRE_8[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_4459 = or(_T_4434, _T_4435) node _T_4460 = or(_T_4459, _T_4436) node _T_4461 = or(_T_4460, _T_4437) node _T_4462 = or(_T_4461, _T_4438) node _T_4463 = or(_T_4462, _T_4439) node _T_4464 = or(_T_4463, _T_4440) node _T_4465 = or(_T_4464, _T_4441) node _T_4466 = or(_T_4465, _T_4442) node _T_4467 = or(_T_4466, _T_4443) node _T_4468 = or(_T_4467, _T_4444) node _T_4469 = or(_T_4468, _T_4445) node _T_4470 = or(_T_4469, _T_4446) node _T_4471 = or(_T_4470, _T_4447) node _T_4472 = or(_T_4471, _T_4448) node _T_4473 = or(_T_4472, _T_4449) node _T_4474 = or(_T_4473, _T_4450) node _T_4475 = or(_T_4474, _T_4451) node _T_4476 = or(_T_4475, _T_4452) node _T_4477 = or(_T_4476, _T_4453) node _T_4478 = or(_T_4477, _T_4454) node _T_4479 = or(_T_4478, _T_4455) node _T_4480 = or(_T_4479, _T_4456) node _T_4481 = or(_T_4480, _T_4457) node _T_4482 = or(_T_4481, _T_4458) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_4482 node _T_4483 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4484 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4485 = and(_T_4483, _T_4484) node _T_4486 = or(UInt<1>(0h0), _T_4485) node _T_4487 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4488 = cvt(_T_4487) node _T_4489 = and(_T_4488, asSInt(UInt<17>(0h10000))) node _T_4490 = asSInt(_T_4489) node _T_4491 = eq(_T_4490, asSInt(UInt<1>(0h0))) node _T_4492 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4493 = cvt(_T_4492) node _T_4494 = and(_T_4493, asSInt(UInt<29>(0h10000000))) node _T_4495 = asSInt(_T_4494) node _T_4496 = eq(_T_4495, asSInt(UInt<1>(0h0))) node _T_4497 = or(_T_4491, _T_4496) node _T_4498 = and(_T_4486, _T_4497) node _T_4499 = or(UInt<1>(0h0), _T_4498) node _T_4500 = and(_WIRE_9, _T_4499) node _T_4501 = asUInt(reset) node _T_4502 = eq(_T_4501, UInt<1>(0h0)) when _T_4502 : node _T_4503 = eq(_T_4500, UInt<1>(0h0)) when _T_4503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_4500, UInt<1>(0h1), "") : assert_151 node _T_4504 = asUInt(reset) node _T_4505 = eq(_T_4504, UInt<1>(0h0)) when _T_4505 : node _T_4506 = eq(source_ok_2, UInt<1>(0h0)) when _T_4506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_4507 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_4508 = asUInt(reset) node _T_4509 = eq(_T_4508, UInt<1>(0h0)) when _T_4509 : node _T_4510 = eq(_T_4507, UInt<1>(0h0)) when _T_4510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_4507, UInt<1>(0h1), "") : assert_153 node _T_4511 = asUInt(reset) node _T_4512 = eq(_T_4511, UInt<1>(0h0)) when _T_4512 : node _T_4513 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_4514 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_4515 = asUInt(reset) node _T_4516 = eq(_T_4515, UInt<1>(0h0)) when _T_4516 : node _T_4517 = eq(_T_4514, UInt<1>(0h0)) when _T_4517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_4514, UInt<1>(0h1), "") : assert_155 node _T_4518 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_4518 : node _T_4519 = asUInt(reset) node _T_4520 = eq(_T_4519, UInt<1>(0h0)) when _T_4520 : node _T_4521 = eq(address_ok_1, UInt<1>(0h0)) when _T_4521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_4522 = asUInt(reset) node _T_4523 = eq(_T_4522, UInt<1>(0h0)) when _T_4523 : node _T_4524 = eq(source_ok_2, UInt<1>(0h0)) when _T_4524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_4525 = asUInt(reset) node _T_4526 = eq(_T_4525, UInt<1>(0h0)) when _T_4526 : node _T_4527 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_4528 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4529 = asUInt(reset) node _T_4530 = eq(_T_4529, UInt<1>(0h0)) when _T_4530 : node _T_4531 = eq(_T_4528, UInt<1>(0h0)) when _T_4531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_4528, UInt<1>(0h1), "") : assert_159 node _T_4532 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4533 = asUInt(reset) node _T_4534 = eq(_T_4533, UInt<1>(0h0)) when _T_4534 : node _T_4535 = eq(_T_4532, UInt<1>(0h0)) when _T_4535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_4532, UInt<1>(0h1), "") : assert_160 node _T_4536 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_4536 : node _T_4537 = asUInt(reset) node _T_4538 = eq(_T_4537, UInt<1>(0h0)) when _T_4538 : node _T_4539 = eq(address_ok_1, UInt<1>(0h0)) when _T_4539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_4540 = asUInt(reset) node _T_4541 = eq(_T_4540, UInt<1>(0h0)) when _T_4541 : node _T_4542 = eq(source_ok_2, UInt<1>(0h0)) when _T_4542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_4543 = asUInt(reset) node _T_4544 = eq(_T_4543, UInt<1>(0h0)) when _T_4544 : node _T_4545 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_4546 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4547 = asUInt(reset) node _T_4548 = eq(_T_4547, UInt<1>(0h0)) when _T_4548 : node _T_4549 = eq(_T_4546, UInt<1>(0h0)) when _T_4549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_4546, UInt<1>(0h1), "") : assert_164 node _T_4550 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_4550 : node _T_4551 = asUInt(reset) node _T_4552 = eq(_T_4551, UInt<1>(0h0)) when _T_4552 : node _T_4553 = eq(address_ok_1, UInt<1>(0h0)) when _T_4553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_4554 = asUInt(reset) node _T_4555 = eq(_T_4554, UInt<1>(0h0)) when _T_4555 : node _T_4556 = eq(source_ok_2, UInt<1>(0h0)) when _T_4556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_4557 = asUInt(reset) node _T_4558 = eq(_T_4557, UInt<1>(0h0)) when _T_4558 : node _T_4559 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_4560 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4561 = asUInt(reset) node _T_4562 = eq(_T_4561, UInt<1>(0h0)) when _T_4562 : node _T_4563 = eq(_T_4560, UInt<1>(0h0)) when _T_4563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_4560, UInt<1>(0h1), "") : assert_168 node _T_4564 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4565 = asUInt(reset) node _T_4566 = eq(_T_4565, UInt<1>(0h0)) when _T_4566 : node _T_4567 = eq(_T_4564, UInt<1>(0h0)) when _T_4567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_4564, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_4568 = asUInt(reset) node _T_4569 = eq(_T_4568, UInt<1>(0h0)) when _T_4569 : node _T_4570 = eq(sink_ok_1, UInt<1>(0h0)) when _T_4570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_4571 = eq(a_first, UInt<1>(0h0)) node _T_4572 = and(io.in.a.valid, _T_4571) when _T_4572 : node _T_4573 = eq(io.in.a.bits.opcode, opcode) node _T_4574 = asUInt(reset) node _T_4575 = eq(_T_4574, UInt<1>(0h0)) when _T_4575 : node _T_4576 = eq(_T_4573, UInt<1>(0h0)) when _T_4576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_4573, UInt<1>(0h1), "") : assert_171 node _T_4577 = eq(io.in.a.bits.param, param) node _T_4578 = asUInt(reset) node _T_4579 = eq(_T_4578, UInt<1>(0h0)) when _T_4579 : node _T_4580 = eq(_T_4577, UInt<1>(0h0)) when _T_4580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_4577, UInt<1>(0h1), "") : assert_172 node _T_4581 = eq(io.in.a.bits.size, size) node _T_4582 = asUInt(reset) node _T_4583 = eq(_T_4582, UInt<1>(0h0)) when _T_4583 : node _T_4584 = eq(_T_4581, UInt<1>(0h0)) when _T_4584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_4581, UInt<1>(0h1), "") : assert_173 node _T_4585 = eq(io.in.a.bits.source, source) node _T_4586 = asUInt(reset) node _T_4587 = eq(_T_4586, UInt<1>(0h0)) when _T_4587 : node _T_4588 = eq(_T_4585, UInt<1>(0h0)) when _T_4588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_4585, UInt<1>(0h1), "") : assert_174 node _T_4589 = eq(io.in.a.bits.address, address) node _T_4590 = asUInt(reset) node _T_4591 = eq(_T_4590, UInt<1>(0h0)) when _T_4591 : node _T_4592 = eq(_T_4589, UInt<1>(0h0)) when _T_4592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_4589, UInt<1>(0h1), "") : assert_175 node _T_4593 = and(io.in.a.ready, io.in.a.valid) node _T_4594 = and(_T_4593, a_first) when _T_4594 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_4595 = eq(d_first, UInt<1>(0h0)) node _T_4596 = and(io.in.d.valid, _T_4595) when _T_4596 : node _T_4597 = eq(io.in.d.bits.opcode, opcode_1) node _T_4598 = asUInt(reset) node _T_4599 = eq(_T_4598, UInt<1>(0h0)) when _T_4599 : node _T_4600 = eq(_T_4597, UInt<1>(0h0)) when _T_4600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_4597, UInt<1>(0h1), "") : assert_176 node _T_4601 = eq(io.in.d.bits.param, param_1) node _T_4602 = asUInt(reset) node _T_4603 = eq(_T_4602, UInt<1>(0h0)) when _T_4603 : node _T_4604 = eq(_T_4601, UInt<1>(0h0)) when _T_4604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_4601, UInt<1>(0h1), "") : assert_177 node _T_4605 = eq(io.in.d.bits.size, size_1) node _T_4606 = asUInt(reset) node _T_4607 = eq(_T_4606, UInt<1>(0h0)) when _T_4607 : node _T_4608 = eq(_T_4605, UInt<1>(0h0)) when _T_4608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_4605, UInt<1>(0h1), "") : assert_178 node _T_4609 = eq(io.in.d.bits.source, source_1) node _T_4610 = asUInt(reset) node _T_4611 = eq(_T_4610, UInt<1>(0h0)) when _T_4611 : node _T_4612 = eq(_T_4609, UInt<1>(0h0)) when _T_4612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_4609, UInt<1>(0h1), "") : assert_179 node _T_4613 = eq(io.in.d.bits.sink, sink) node _T_4614 = asUInt(reset) node _T_4615 = eq(_T_4614, UInt<1>(0h0)) when _T_4615 : node _T_4616 = eq(_T_4613, UInt<1>(0h0)) when _T_4616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_4613, UInt<1>(0h1), "") : assert_180 node _T_4617 = eq(io.in.d.bits.denied, denied) node _T_4618 = asUInt(reset) node _T_4619 = eq(_T_4618, UInt<1>(0h0)) when _T_4619 : node _T_4620 = eq(_T_4617, UInt<1>(0h0)) when _T_4620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_4617, UInt<1>(0h1), "") : assert_181 node _T_4621 = and(io.in.d.ready, io.in.d.valid) node _T_4622 = and(_T_4621, d_first) when _T_4622 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_4623 = eq(b_first, UInt<1>(0h0)) node _T_4624 = and(io.in.b.valid, _T_4623) when _T_4624 : node _T_4625 = eq(io.in.b.bits.opcode, opcode_2) node _T_4626 = asUInt(reset) node _T_4627 = eq(_T_4626, UInt<1>(0h0)) when _T_4627 : node _T_4628 = eq(_T_4625, UInt<1>(0h0)) when _T_4628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_4625, UInt<1>(0h1), "") : assert_182 node _T_4629 = eq(io.in.b.bits.param, param_2) node _T_4630 = asUInt(reset) node _T_4631 = eq(_T_4630, UInt<1>(0h0)) when _T_4631 : node _T_4632 = eq(_T_4629, UInt<1>(0h0)) when _T_4632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_4629, UInt<1>(0h1), "") : assert_183 node _T_4633 = eq(io.in.b.bits.size, size_2) node _T_4634 = asUInt(reset) node _T_4635 = eq(_T_4634, UInt<1>(0h0)) when _T_4635 : node _T_4636 = eq(_T_4633, UInt<1>(0h0)) when _T_4636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_4633, UInt<1>(0h1), "") : assert_184 node _T_4637 = eq(io.in.b.bits.source, source_2) node _T_4638 = asUInt(reset) node _T_4639 = eq(_T_4638, UInt<1>(0h0)) when _T_4639 : node _T_4640 = eq(_T_4637, UInt<1>(0h0)) when _T_4640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_4637, UInt<1>(0h1), "") : assert_185 node _T_4641 = eq(io.in.b.bits.address, address_1) node _T_4642 = asUInt(reset) node _T_4643 = eq(_T_4642, UInt<1>(0h0)) when _T_4643 : node _T_4644 = eq(_T_4641, UInt<1>(0h0)) when _T_4644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_4641, UInt<1>(0h1), "") : assert_186 node _T_4645 = and(io.in.b.ready, io.in.b.valid) node _T_4646 = and(_T_4645, b_first) when _T_4646 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_4647 = eq(c_first, UInt<1>(0h0)) node _T_4648 = and(io.in.c.valid, _T_4647) when _T_4648 : node _T_4649 = eq(io.in.c.bits.opcode, opcode_3) node _T_4650 = asUInt(reset) node _T_4651 = eq(_T_4650, UInt<1>(0h0)) when _T_4651 : node _T_4652 = eq(_T_4649, UInt<1>(0h0)) when _T_4652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_4649, UInt<1>(0h1), "") : assert_187 node _T_4653 = eq(io.in.c.bits.param, param_3) node _T_4654 = asUInt(reset) node _T_4655 = eq(_T_4654, UInt<1>(0h0)) when _T_4655 : node _T_4656 = eq(_T_4653, UInt<1>(0h0)) when _T_4656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_4653, UInt<1>(0h1), "") : assert_188 node _T_4657 = eq(io.in.c.bits.size, size_3) node _T_4658 = asUInt(reset) node _T_4659 = eq(_T_4658, UInt<1>(0h0)) when _T_4659 : node _T_4660 = eq(_T_4657, UInt<1>(0h0)) when _T_4660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_4657, UInt<1>(0h1), "") : assert_189 node _T_4661 = eq(io.in.c.bits.source, source_3) node _T_4662 = asUInt(reset) node _T_4663 = eq(_T_4662, UInt<1>(0h0)) when _T_4663 : node _T_4664 = eq(_T_4661, UInt<1>(0h0)) when _T_4664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_4661, UInt<1>(0h1), "") : assert_190 node _T_4665 = eq(io.in.c.bits.address, address_2) node _T_4666 = asUInt(reset) node _T_4667 = eq(_T_4666, UInt<1>(0h0)) when _T_4667 : node _T_4668 = eq(_T_4665, UInt<1>(0h0)) when _T_4668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_4665, UInt<1>(0h1), "") : assert_191 node _T_4669 = and(io.in.c.ready, io.in.c.valid) node _T_4670 = and(_T_4669, c_first) when _T_4670 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<500>, clock, reset, UInt<500>(0h0) regreset inflight_opcodes : UInt<2000>, clock, reset, UInt<2000>(0h0) regreset inflight_sizes : UInt<2000>, clock, reset, UInt<2000>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<500> connect a_set, UInt<500>(0h0) wire a_set_wo_ready : UInt<500> connect a_set_wo_ready, UInt<500>(0h0) wire a_opcodes_set : UInt<2000> connect a_opcodes_set, UInt<2000>(0h0) wire a_sizes_set : UInt<2000> connect a_sizes_set, UInt<2000>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_4671 = and(io.in.a.valid, a_first_1) node _T_4672 = and(_T_4671, UInt<1>(0h1)) when _T_4672 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_4673 = and(io.in.a.ready, io.in.a.valid) node _T_4674 = and(_T_4673, a_first_1) node _T_4675 = and(_T_4674, UInt<1>(0h1)) when _T_4675 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_4676 = dshr(inflight, io.in.a.bits.source) node _T_4677 = bits(_T_4676, 0, 0) node _T_4678 = eq(_T_4677, UInt<1>(0h0)) node _T_4679 = asUInt(reset) node _T_4680 = eq(_T_4679, UInt<1>(0h0)) when _T_4680 : node _T_4681 = eq(_T_4678, UInt<1>(0h0)) when _T_4681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_4678, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<500> connect d_clr, UInt<500>(0h0) wire d_clr_wo_ready : UInt<500> connect d_clr_wo_ready, UInt<500>(0h0) wire d_opcodes_clr : UInt<2000> connect d_opcodes_clr, UInt<2000>(0h0) wire d_sizes_clr : UInt<2000> connect d_sizes_clr, UInt<2000>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_4682 = and(io.in.d.valid, d_first_1) node _T_4683 = and(_T_4682, UInt<1>(0h1)) node _T_4684 = eq(d_release_ack, UInt<1>(0h0)) node _T_4685 = and(_T_4683, _T_4684) when _T_4685 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_4686 = and(io.in.d.ready, io.in.d.valid) node _T_4687 = and(_T_4686, d_first_1) node _T_4688 = and(_T_4687, UInt<1>(0h1)) node _T_4689 = eq(d_release_ack, UInt<1>(0h0)) node _T_4690 = and(_T_4688, _T_4689) when _T_4690 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_4691 = and(io.in.d.valid, d_first_1) node _T_4692 = and(_T_4691, UInt<1>(0h1)) node _T_4693 = eq(d_release_ack, UInt<1>(0h0)) node _T_4694 = and(_T_4692, _T_4693) when _T_4694 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_4695 = dshr(inflight, io.in.d.bits.source) node _T_4696 = bits(_T_4695, 0, 0) node _T_4697 = or(_T_4696, same_cycle_resp) node _T_4698 = asUInt(reset) node _T_4699 = eq(_T_4698, UInt<1>(0h0)) when _T_4699 : node _T_4700 = eq(_T_4697, UInt<1>(0h0)) when _T_4700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_4697, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_4701 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_4702 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_4703 = or(_T_4701, _T_4702) node _T_4704 = asUInt(reset) node _T_4705 = eq(_T_4704, UInt<1>(0h0)) when _T_4705 : node _T_4706 = eq(_T_4703, UInt<1>(0h0)) when _T_4706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_4703, UInt<1>(0h1), "") : assert_194 node _T_4707 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_4708 = asUInt(reset) node _T_4709 = eq(_T_4708, UInt<1>(0h0)) when _T_4709 : node _T_4710 = eq(_T_4707, UInt<1>(0h0)) when _T_4710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_4707, UInt<1>(0h1), "") : assert_195 else : node _T_4711 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_4712 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_4713 = or(_T_4711, _T_4712) node _T_4714 = asUInt(reset) node _T_4715 = eq(_T_4714, UInt<1>(0h0)) when _T_4715 : node _T_4716 = eq(_T_4713, UInt<1>(0h0)) when _T_4716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_4713, UInt<1>(0h1), "") : assert_196 node _T_4717 = eq(io.in.d.bits.size, a_size_lookup) node _T_4718 = asUInt(reset) node _T_4719 = eq(_T_4718, UInt<1>(0h0)) when _T_4719 : node _T_4720 = eq(_T_4717, UInt<1>(0h0)) when _T_4720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_4717, UInt<1>(0h1), "") : assert_197 node _T_4721 = and(io.in.d.valid, d_first_1) node _T_4722 = and(_T_4721, a_first_1) node _T_4723 = and(_T_4722, io.in.a.valid) node _T_4724 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_4725 = and(_T_4723, _T_4724) node _T_4726 = eq(d_release_ack, UInt<1>(0h0)) node _T_4727 = and(_T_4725, _T_4726) when _T_4727 : node _T_4728 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_4729 = or(_T_4728, io.in.a.ready) node _T_4730 = asUInt(reset) node _T_4731 = eq(_T_4730, UInt<1>(0h0)) when _T_4731 : node _T_4732 = eq(_T_4729, UInt<1>(0h0)) when _T_4732 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_4729, UInt<1>(0h1), "") : assert_198 node _T_4733 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_4734 = orr(a_set_wo_ready) node _T_4735 = eq(_T_4734, UInt<1>(0h0)) node _T_4736 = or(_T_4733, _T_4735) node _T_4737 = asUInt(reset) node _T_4738 = eq(_T_4737, UInt<1>(0h0)) when _T_4738 : node _T_4739 = eq(_T_4736, UInt<1>(0h0)) when _T_4739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_4736, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_104 node _T_4740 = orr(inflight) node _T_4741 = eq(_T_4740, UInt<1>(0h0)) node _T_4742 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_4743 = or(_T_4741, _T_4742) node _T_4744 = lt(watchdog, plusarg_reader.out) node _T_4745 = or(_T_4743, _T_4744) node _T_4746 = asUInt(reset) node _T_4747 = eq(_T_4746, UInt<1>(0h0)) when _T_4747 : node _T_4748 = eq(_T_4745, UInt<1>(0h0)) when _T_4748 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_4745, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_4749 = and(io.in.a.ready, io.in.a.valid) node _T_4750 = and(io.in.d.ready, io.in.d.valid) node _T_4751 = or(_T_4749, _T_4750) when _T_4751 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<500>, clock, reset, UInt<500>(0h0) regreset inflight_opcodes_1 : UInt<2000>, clock, reset, UInt<2000>(0h0) regreset inflight_sizes_1 : UInt<2000>, clock, reset, UInt<2000>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<500> connect c_set, UInt<500>(0h0) wire c_set_wo_ready : UInt<500> connect c_set_wo_ready, UInt<500>(0h0) wire c_opcodes_set : UInt<2000> connect c_opcodes_set, UInt<2000>(0h0) wire c_sizes_set : UInt<2000> connect c_sizes_set, UInt<2000>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_4752 = and(io.in.c.valid, c_first_1) node _T_4753 = bits(io.in.c.bits.opcode, 2, 2) node _T_4754 = bits(io.in.c.bits.opcode, 1, 1) node _T_4755 = and(_T_4753, _T_4754) node _T_4756 = and(_T_4752, _T_4755) when _T_4756 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_4757 = and(io.in.c.ready, io.in.c.valid) node _T_4758 = and(_T_4757, c_first_1) node _T_4759 = bits(io.in.c.bits.opcode, 2, 2) node _T_4760 = bits(io.in.c.bits.opcode, 1, 1) node _T_4761 = and(_T_4759, _T_4760) node _T_4762 = and(_T_4758, _T_4761) when _T_4762 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_4763 = dshr(inflight_1, io.in.c.bits.source) node _T_4764 = bits(_T_4763, 0, 0) node _T_4765 = eq(_T_4764, UInt<1>(0h0)) node _T_4766 = asUInt(reset) node _T_4767 = eq(_T_4766, UInt<1>(0h0)) when _T_4767 : node _T_4768 = eq(_T_4765, UInt<1>(0h0)) when _T_4768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_4765, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<500> connect d_clr_1, UInt<500>(0h0) wire d_clr_wo_ready_1 : UInt<500> connect d_clr_wo_ready_1, UInt<500>(0h0) wire d_opcodes_clr_1 : UInt<2000> connect d_opcodes_clr_1, UInt<2000>(0h0) wire d_sizes_clr_1 : UInt<2000> connect d_sizes_clr_1, UInt<2000>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_4769 = and(io.in.d.valid, d_first_2) node _T_4770 = and(_T_4769, UInt<1>(0h1)) node _T_4771 = and(_T_4770, d_release_ack_1) when _T_4771 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_4772 = and(io.in.d.ready, io.in.d.valid) node _T_4773 = and(_T_4772, d_first_2) node _T_4774 = and(_T_4773, UInt<1>(0h1)) node _T_4775 = and(_T_4774, d_release_ack_1) when _T_4775 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_4776 = and(io.in.d.valid, d_first_2) node _T_4777 = and(_T_4776, UInt<1>(0h1)) node _T_4778 = and(_T_4777, d_release_ack_1) when _T_4778 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_4779 = dshr(inflight_1, io.in.d.bits.source) node _T_4780 = bits(_T_4779, 0, 0) node _T_4781 = or(_T_4780, same_cycle_resp_1) node _T_4782 = asUInt(reset) node _T_4783 = eq(_T_4782, UInt<1>(0h0)) when _T_4783 : node _T_4784 = eq(_T_4781, UInt<1>(0h0)) when _T_4784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_4781, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_4785 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_4786 = asUInt(reset) node _T_4787 = eq(_T_4786, UInt<1>(0h0)) when _T_4787 : node _T_4788 = eq(_T_4785, UInt<1>(0h0)) when _T_4788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_4785, UInt<1>(0h1), "") : assert_203 else : node _T_4789 = eq(io.in.d.bits.size, c_size_lookup) node _T_4790 = asUInt(reset) node _T_4791 = eq(_T_4790, UInt<1>(0h0)) when _T_4791 : node _T_4792 = eq(_T_4789, UInt<1>(0h0)) when _T_4792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_4789, UInt<1>(0h1), "") : assert_204 node _T_4793 = and(io.in.d.valid, d_first_2) node _T_4794 = and(_T_4793, c_first_1) node _T_4795 = and(_T_4794, io.in.c.valid) node _T_4796 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_4797 = and(_T_4795, _T_4796) node _T_4798 = and(_T_4797, d_release_ack_1) node _T_4799 = eq(c_probe_ack, UInt<1>(0h0)) node _T_4800 = and(_T_4798, _T_4799) when _T_4800 : node _T_4801 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_4802 = or(_T_4801, io.in.c.ready) node _T_4803 = asUInt(reset) node _T_4804 = eq(_T_4803, UInt<1>(0h0)) when _T_4804 : node _T_4805 = eq(_T_4802, UInt<1>(0h0)) when _T_4805 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_4802, UInt<1>(0h1), "") : assert_205 node _T_4806 = orr(c_set_wo_ready) when _T_4806 : node _T_4807 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_4808 = asUInt(reset) node _T_4809 = eq(_T_4808, UInt<1>(0h0)) when _T_4809 : node _T_4810 = eq(_T_4807, UInt<1>(0h0)) when _T_4810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_4807, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_105 node _T_4811 = orr(inflight_1) node _T_4812 = eq(_T_4811, UInt<1>(0h0)) node _T_4813 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_4814 = or(_T_4812, _T_4813) node _T_4815 = lt(watchdog_1, plusarg_reader_1.out) node _T_4816 = or(_T_4814, _T_4815) node _T_4817 = asUInt(reset) node _T_4818 = eq(_T_4817, UInt<1>(0h0)) when _T_4818 : node _T_4819 = eq(_T_4816, UInt<1>(0h0)) when _T_4819 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_4816, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_4820 = and(io.in.c.ready, io.in.c.valid) node _T_4821 = and(io.in.d.ready, io.in.d.valid) node _T_4822 = or(_T_4820, _T_4821) when _T_4822 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_4823 = and(io.in.d.ready, io.in.d.valid) node _T_4824 = and(_T_4823, d_first_3) node _T_4825 = bits(io.in.d.bits.opcode, 2, 2) node _T_4826 = bits(io.in.d.bits.opcode, 1, 1) node _T_4827 = eq(_T_4826, UInt<1>(0h0)) node _T_4828 = and(_T_4825, _T_4827) node _T_4829 = and(_T_4824, _T_4828) when _T_4829 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_4830 = dshr(inflight_2, io.in.d.bits.sink) node _T_4831 = bits(_T_4830, 0, 0) node _T_4832 = eq(_T_4831, UInt<1>(0h0)) node _T_4833 = asUInt(reset) node _T_4834 = eq(_T_4833, UInt<1>(0h0)) when _T_4834 : node _T_4835 = eq(_T_4832, UInt<1>(0h0)) when _T_4835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_4832, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_4836 = and(io.in.e.ready, io.in.e.valid) node _T_4837 = and(_T_4836, UInt<1>(0h1)) node _T_4838 = and(_T_4837, UInt<1>(0h1)) when _T_4838 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_4839 = or(d_set, inflight_2) node _T_4840 = dshr(_T_4839, io.in.e.bits.sink) node _T_4841 = bits(_T_4840, 0, 0) node _T_4842 = asUInt(reset) node _T_4843 = eq(_T_4842, UInt<1>(0h0)) when _T_4843 : node _T_4844 = eq(_T_4841, UInt<1>(0h0)) when _T_4844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_4841, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_161 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_163 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_169 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_175 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_181 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_187 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_193 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_199 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_205 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_211 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_217 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_223 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_229 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_235 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_241 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_247 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_253 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_259 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_265 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_271 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_277 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_283 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_289 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_133 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_23 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_319 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_321 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_325 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_327 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_331 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_333 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_337 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_339 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_343 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_345 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_349 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_351 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_355 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_357 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_361 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_363 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_367 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_369 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_373 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_375 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_379 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_381 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_385 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_387 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_391 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_393 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_397 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_399 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_403 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_405 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_409 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_411 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_415 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_417 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_421 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_423 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_427 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_429 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_433 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_435 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_439 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_441 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_445 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_447 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] io_in_b_bits_source = 9'h1E0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_242 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_243 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_244 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_245 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_246 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_247 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_248 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_249 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_250 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_251 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_252 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_253 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_254 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_255 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_256 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_257 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_258 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_259 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_260 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_261 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_262 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_263 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_1 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_2 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_3 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_4 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_5 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_6 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_7 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_8 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_9 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_10 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_11 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_12 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_13 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_14 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_15 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_16 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_17 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_18 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_19 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_20 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_21 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_T_158 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_182 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_183 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_WIRE_1 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _uncommonBits_T_264 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_265 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_266 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_267 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_268 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_269 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_270 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_271 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_272 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_273 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_274 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_275 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_276 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_277 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_278 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_279 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_280 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_281 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_282 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_283 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_284 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_285 = 9'h1E0; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_34 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_36 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_40 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_42 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_44 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_46 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_48 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_50 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_52 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_54 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_56 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_58 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_60 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_62 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_64 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_66 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_68 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_70 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_72 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_74 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_76 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_78 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_80 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_82 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_84 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_86 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_88 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_90 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_92 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_94 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_96 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_98 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_100 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_102 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_104 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_106 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_108 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_110 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_112 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_114 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_116 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_118 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_120 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_122 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_124 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_126 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_128 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_130 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_132 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_134 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_9 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_10 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_11 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_12 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_13 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_14 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_15 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_16 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_17 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_18 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_19 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_20 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_21 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_22 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_24 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_157 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_156 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] uncommonBits_248 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_249 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_250 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_251 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_252 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_253 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_256 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_257 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_258 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_259 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_260 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_261 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_262 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_263 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_6 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_7 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_8 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_9 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_10 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_11 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_14 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_15 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_16 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_17 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_18 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_19 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_20 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_21 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_270 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_271 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_272 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_273 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_274 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_275 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_278 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_279 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_280 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_281 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_282 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_283 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_284 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_285 = 5'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_242 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_243 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_244 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_245 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_246 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_247 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_254 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_255 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_4 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_5 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_12 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_13 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_264 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_265 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_266 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_267 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_268 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_269 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_276 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_277 = 2'h0; // @[Parameters.scala:52:56] wire [8:0] _legal_source_T_135 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_136 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_137 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_138 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_139 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_140 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_141 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_142 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_143 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_144 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_145 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_146 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_147 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_148 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_149 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_159 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_160 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_161 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_162 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_163 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_164 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_165 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_166 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_167 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_168 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_169 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_170 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_171 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_172 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_173 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_174 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_175 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_176 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_177 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_178 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_179 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_180 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_181 = 9'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_154 = 7'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_155 = 7'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_150 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_151 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_152 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_153 = 8'h0; // @[Mux.scala:30:73] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] _legal_source_T_37 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_43 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_49 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_55 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_61 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_67 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_85 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_91 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_97 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_103 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_109 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_115 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_121 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_127 = 4'hF; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_1 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_7 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_13 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_19 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_25 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_31 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_73 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_79 = 7'h78; // @[Parameters.scala:54:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_44 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_45 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_46 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_47 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_48 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_49 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_50 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_51 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_286 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_287 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_288 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_289 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_290 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_291 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_292 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_293 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_294 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_295 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_296 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_297 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_298 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_299 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_300 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_301 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_302 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_303 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_304 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_305 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_306 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_307 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_308 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_309 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_310 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_311 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_312 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_313 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_314 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_315 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_316 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_317 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_318 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_319 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_320 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_321 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_322 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_323 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_324 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_325 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_326 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_327 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_328 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_329 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_330 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_331 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_332 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_333 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_334 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_335 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_336 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_337 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_338 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_339 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_340 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_341 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_342 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_343 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_344 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_345 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_346 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_347 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_348 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_349 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_350 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_351 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_352 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_353 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_354 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_355 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_356 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_357 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_358 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_359 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_360 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_361 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_362 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_363 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_364 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_365 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_366 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_367 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_368 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_369 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_370 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_371 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_372 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_373 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_374 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_375 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_376 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_377 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_378 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_379 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_380 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_381 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_382 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_383 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_384 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_385 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_386 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_387 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_388 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_389 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_390 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_391 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_392 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_393 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_394 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_395 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_25 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_31 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_73 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_79 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_43 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_49 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_55 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_61 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_67 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_103 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_109 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_115 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_121 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_127 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 \| _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 \| _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 \| _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 \| _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_157 \| _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_158 = io_in_d_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_158; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_159 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_165 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_171 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_177 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_183 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_189 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_231 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_237 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_160 = _source_ok_T_159 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_162 = _source_ok_T_160; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_164 = _source_ok_T_162; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_164; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_166 = _source_ok_T_165 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_170 = _source_ok_T_168; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_170; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_172 = _source_ok_T_171 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_176 = _source_ok_T_174; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_176; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_178 = _source_ok_T_177 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_182 = _source_ok_T_180; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_182; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_184 = _source_ok_T_183 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_188 = _source_ok_T_186; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_188; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_190 = _source_ok_T_189 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_194 = _source_ok_T_192; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_194; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_195 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_201 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_207 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_213 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_219 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_225 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_243 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_249 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_255 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_261 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_267 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_273 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_279 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_285 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_196 = _source_ok_T_195 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_200 = _source_ok_T_198; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_200; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_202 = _source_ok_T_201 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_206 = _source_ok_T_204; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_206; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_208 = _source_ok_T_207 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_212 = _source_ok_T_210; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_212; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_214 = _source_ok_T_213 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_218 = _source_ok_T_216; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_218; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_220 = _source_ok_T_219 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_224 = _source_ok_T_222; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_224; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_226 = _source_ok_T_225 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_230 = _source_ok_T_228; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_230; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_232 = _source_ok_T_231 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_236 = _source_ok_T_234; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_236; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_238 = _source_ok_T_237 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_242 = _source_ok_T_240; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_242; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_244 = _source_ok_T_243 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_248 = _source_ok_T_246; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_248; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_250 = _source_ok_T_249 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_254 = _source_ok_T_252; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_254; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_256 = _source_ok_T_255 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_260 = _source_ok_T_258; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_260; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_262 = _source_ok_T_261 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_266 = _source_ok_T_264; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_266; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_268 = _source_ok_T_267 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_272 = _source_ok_T_270; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_272; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_274 = _source_ok_T_273 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_278 = _source_ok_T_276; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_278; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_280 = _source_ok_T_279 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_284 = _source_ok_T_282; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_284; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_286 = _source_ok_T_285 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_290 = _source_ok_T_288; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_290; // @[Parameters.scala:1138:31] wire _source_ok_T_291 = io_in_d_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_291; // @[Parameters.scala:1138:31] wire _source_ok_T_292 = io_in_d_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_292; // @[Parameters.scala:1138:31] wire _source_ok_T_293 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_294 = _source_ok_T_293 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_295 = _source_ok_T_294 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_296 = _source_ok_T_295 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_297 = _source_ok_T_296 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_298 = _source_ok_T_297 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_299 = _source_ok_T_298 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 \| _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 \| _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 \| _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 \| _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_315 \| _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_316 = io_in_c_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_316; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_44 = _source_ok_uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_317 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_323 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_329 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_335 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_341 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_347 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_389 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_395 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_318 = _source_ok_T_317 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_320 = _source_ok_T_318; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_322 = _source_ok_T_320; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_322; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_45 = _source_ok_uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_324 = _source_ok_T_323 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_326 = _source_ok_T_324; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_328 = _source_ok_T_326; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_328; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_46 = _source_ok_uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_330 = _source_ok_T_329 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_332 = _source_ok_T_330; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_334 = _source_ok_T_332; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_334; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_47 = _source_ok_uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_336 = _source_ok_T_335 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_338 = _source_ok_T_336; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_340 = _source_ok_T_338; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_340; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_48 = _source_ok_uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_342 = _source_ok_T_341 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_344 = _source_ok_T_342; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_346 = _source_ok_T_344; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_346; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_49 = _source_ok_uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_348 = _source_ok_T_347 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_350 = _source_ok_T_348; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_352 = _source_ok_T_350; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_6 = _source_ok_T_352; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_50 = _source_ok_uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_353 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_359 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_365 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_371 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_377 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_383 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_401 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_407 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_413 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_419 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_425 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_431 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_437 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_443 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_354 = _source_ok_T_353 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_356 = _source_ok_T_354; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_358 = _source_ok_T_356; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_7 = _source_ok_T_358; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_51 = _source_ok_uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_360 = _source_ok_T_359 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_362 = _source_ok_T_360; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_364 = _source_ok_T_362; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_8 = _source_ok_T_364; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_52 = _source_ok_uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_366 = _source_ok_T_365 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_368 = _source_ok_T_366; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_370 = _source_ok_T_368; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_9 = _source_ok_T_370; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_53 = _source_ok_uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_372 = _source_ok_T_371 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_374 = _source_ok_T_372; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_376 = _source_ok_T_374; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_10 = _source_ok_T_376; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_54 = _source_ok_uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_378 = _source_ok_T_377 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_380 = _source_ok_T_378; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_382 = _source_ok_T_380; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_11 = _source_ok_T_382; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_55 = _source_ok_uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_384 = _source_ok_T_383 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_386 = _source_ok_T_384; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_388 = _source_ok_T_386; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_12 = _source_ok_T_388; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_56 = _source_ok_uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_390 = _source_ok_T_389 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_392 = _source_ok_T_390; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_394 = _source_ok_T_392; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_13 = _source_ok_T_394; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_57 = _source_ok_uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_396 = _source_ok_T_395 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_398 = _source_ok_T_396; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_400 = _source_ok_T_398; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_14 = _source_ok_T_400; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_58 = _source_ok_uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_402 = _source_ok_T_401 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_404 = _source_ok_T_402; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_406 = _source_ok_T_404; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_15 = _source_ok_T_406; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_59 = _source_ok_uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_408 = _source_ok_T_407 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_410 = _source_ok_T_408; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_412 = _source_ok_T_410; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_16 = _source_ok_T_412; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_60 = _source_ok_uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_414 = _source_ok_T_413 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_416 = _source_ok_T_414; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_418 = _source_ok_T_416; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_17 = _source_ok_T_418; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_61 = _source_ok_uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_420 = _source_ok_T_419 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_422 = _source_ok_T_420; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_424 = _source_ok_T_422; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_18 = _source_ok_T_424; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_62 = _source_ok_uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_426 = _source_ok_T_425 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_428 = _source_ok_T_426; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_430 = _source_ok_T_428; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_19 = _source_ok_T_430; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_63 = _source_ok_uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_432 = _source_ok_T_431 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_434 = _source_ok_T_432; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_436 = _source_ok_T_434; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_20 = _source_ok_T_436; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_64 = _source_ok_uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_438 = _source_ok_T_437 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_440 = _source_ok_T_438; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_442 = _source_ok_T_440; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_21 = _source_ok_T_442; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_65 = _source_ok_uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_444 = _source_ok_T_443 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_446 = _source_ok_T_444; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_448 = _source_ok_T_446; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_22 = _source_ok_T_448; // @[Parameters.scala:1138:31] wire _source_ok_T_449 = io_in_c_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_23 = _source_ok_T_449; // @[Parameters.scala:1138:31] wire _source_ok_T_450 = io_in_c_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_24 = _source_ok_T_450; // @[Parameters.scala:1138:31] wire _source_ok_T_451 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_452 = _source_ok_T_451 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_453 = _source_ok_T_452 \| _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_454 = _source_ok_T_453 \| _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_455 = _source_ok_T_454 \| _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_456 = _source_ok_T_455 \| _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_457 = _source_ok_T_456 \| _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_458 = _source_ok_T_457 \| _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_459 = _source_ok_T_458 \| _source_ok_WIRE_2_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_460 = _source_ok_T_459 \| _source_ok_WIRE_2_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_461 = _source_ok_T_460 \| _source_ok_WIRE_2_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_462 = _source_ok_T_461 \| _source_ok_WIRE_2_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_463 = _source_ok_T_462 \| _source_ok_WIRE_2_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_464 = _source_ok_T_463 \| _source_ok_WIRE_2_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_465 = _source_ok_T_464 \| _source_ok_WIRE_2_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_466 = _source_ok_T_465 \| _source_ok_WIRE_2_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_467 = _source_ok_T_466 \| _source_ok_WIRE_2_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_468 = _source_ok_T_467 \| _source_ok_WIRE_2_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_469 = _source_ok_T_468 \| _source_ok_WIRE_2_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_470 = _source_ok_T_469 \| _source_ok_WIRE_2_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_471 = _source_ok_T_470 \| _source_ok_WIRE_2_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_472 = _source_ok_T_471 \| _source_ok_WIRE_2_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_473 = _source_ok_T_472 \| _source_ok_WIRE_2_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_473 \| _source_ok_WIRE_2_24; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_286 = _uncommonBits_T_286[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_287 = _uncommonBits_T_287[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_288 = _uncommonBits_T_288[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_289 = _uncommonBits_T_289[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_290 = _uncommonBits_T_290[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_291 = _uncommonBits_T_291[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_292 = _uncommonBits_T_292[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_293 = _uncommonBits_T_293[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_294 = _uncommonBits_T_294[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_295 = _uncommonBits_T_295[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_296 = _uncommonBits_T_296[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_297 = _uncommonBits_T_297[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_298 = _uncommonBits_T_298[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_299 = _uncommonBits_T_299[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_300 = _uncommonBits_T_300[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_301 = _uncommonBits_T_301[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_302 = _uncommonBits_T_302[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_303 = _uncommonBits_T_303[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_304 = _uncommonBits_T_304[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_305 = _uncommonBits_T_305[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_306 = _uncommonBits_T_306[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_307 = _uncommonBits_T_307[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_308 = _uncommonBits_T_308[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_309 = _uncommonBits_T_309[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_310 = _uncommonBits_T_310[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_311 = _uncommonBits_T_311[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_312 = _uncommonBits_T_312[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_313 = _uncommonBits_T_313[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_314 = _uncommonBits_T_314[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_315 = _uncommonBits_T_315[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_316 = _uncommonBits_T_316[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_317 = _uncommonBits_T_317[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_318 = _uncommonBits_T_318[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_319 = _uncommonBits_T_319[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_320 = _uncommonBits_T_320[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_321 = _uncommonBits_T_321[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_322 = _uncommonBits_T_322[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_323 = _uncommonBits_T_323[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_324 = _uncommonBits_T_324[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_325 = _uncommonBits_T_325[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_326 = _uncommonBits_T_326[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_327 = _uncommonBits_T_327[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_328 = _uncommonBits_T_328[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_329 = _uncommonBits_T_329[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_330 = _uncommonBits_T_330[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_331 = _uncommonBits_T_331[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_332 = _uncommonBits_T_332[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_333 = _uncommonBits_T_333[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_334 = _uncommonBits_T_334[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_335 = _uncommonBits_T_335[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_336 = _uncommonBits_T_336[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_337 = _uncommonBits_T_337[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_338 = _uncommonBits_T_338[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_339 = _uncommonBits_T_339[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_340 = _uncommonBits_T_340[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_341 = _uncommonBits_T_341[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_342 = _uncommonBits_T_342[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_343 = _uncommonBits_T_343[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_344 = _uncommonBits_T_344[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_345 = _uncommonBits_T_345[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_346 = _uncommonBits_T_346[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_347 = _uncommonBits_T_347[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_348 = _uncommonBits_T_348[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_349 = _uncommonBits_T_349[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_350 = _uncommonBits_T_350[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_351 = _uncommonBits_T_351[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_352 = _uncommonBits_T_352[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_353 = _uncommonBits_T_353[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_354 = _uncommonBits_T_354[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_355 = _uncommonBits_T_355[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_356 = _uncommonBits_T_356[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_357 = _uncommonBits_T_357[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_358 = _uncommonBits_T_358[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_359 = _uncommonBits_T_359[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_360 = _uncommonBits_T_360[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_361 = _uncommonBits_T_361[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_362 = _uncommonBits_T_362[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_363 = _uncommonBits_T_363[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_364 = _uncommonBits_T_364[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_365 = _uncommonBits_T_365[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_366 = _uncommonBits_T_366[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_367 = _uncommonBits_T_367[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_368 = _uncommonBits_T_368[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_369 = _uncommonBits_T_369[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_370 = _uncommonBits_T_370[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_371 = _uncommonBits_T_371[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_372 = _uncommonBits_T_372[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_373 = _uncommonBits_T_373[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_374 = _uncommonBits_T_374[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_375 = _uncommonBits_T_375[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_376 = _uncommonBits_T_376[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_377 = _uncommonBits_T_377[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_378 = _uncommonBits_T_378[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_379 = _uncommonBits_T_379[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_380 = _uncommonBits_T_380[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_381 = _uncommonBits_T_381[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_382 = _uncommonBits_T_382[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_383 = _uncommonBits_T_383[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_384 = _uncommonBits_T_384[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_385 = _uncommonBits_T_385[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_386 = _uncommonBits_T_386[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_387 = _uncommonBits_T_387[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_388 = _uncommonBits_T_388[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_389 = _uncommonBits_T_389[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_390 = _uncommonBits_T_390[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_391 = _uncommonBits_T_391[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_392 = _uncommonBits_T_392[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_393 = _uncommonBits_T_393[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_394 = _uncommonBits_T_394[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_395 = _uncommonBits_T_395[4:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_4749 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_4749; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_4749; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_4823 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_4823; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_4820 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_4820; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_4820; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [8:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [499:0] inflight; // @[Monitor.scala:614:27] reg [1999:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1999:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [499:0] a_set; // @[Monitor.scala:626:34] wire [499:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1999:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1999:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [1999:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1999:0] _a_opcode_lookup_T_6 = {1996'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1999:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1999:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1999:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1999:0] _a_size_lookup_T_6 = {1996'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1999:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1999:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_5 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4675 = _T_4749 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_4675 ? _a_set_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_4675 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_4675 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_4675 ? _a_opcodes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_4675 ? _a_sizes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [499:0] d_clr; // @[Monitor.scala:664:34] wire [499:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1999:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1999:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_4721 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_8 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_4721 & ~d_release_ack ? _d_clr_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4690 = _T_4823 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_4690 ? _d_clr_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_4690 ? _d_opcodes_clr_T_5[1999:0] : 2000'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_4690 ? _d_sizes_clr_T_5[1999:0] : 2000'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [499:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [499:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [499:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1999:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1999:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1999:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1999:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1999:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1999:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [499:0] inflight_1; // @[Monitor.scala:726:35] reg [1999:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [1999:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [499:0] c_set; // @[Monitor.scala:738:34] wire [499:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [1999:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [1999:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1999:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1999:0] _c_opcode_lookup_T_6 = {1996'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1999:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1999:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1999:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1999:0] _c_size_lookup_T_6 = {1996'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1999:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1999:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [511:0] _GEN_9 = 512'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [511:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4762 = _T_4820 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_4762 ? _c_set_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_4762 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_4762 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [11:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [11:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [4098:0] _c_opcodes_set_T_1 = {4095'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_4762 ? _c_opcodes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4098:0] _c_sizes_set_T_1 = {4095'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_4762 ? _c_sizes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [499:0] d_clr_1; // @[Monitor.scala:774:34] wire [499:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1999:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1999:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_4793 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_4793 & d_release_ack_1 ? _d_clr_wo_ready_T_1[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4775 = _T_4823 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_4775 ? _d_clr_T_1[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_4775 ? _d_opcodes_clr_T_11[1999:0] : 2000'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_4775 ? _d_sizes_clr_T_11[1999:0] : 2000'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [499:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [499:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [499:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1999:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [1999:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1999:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1999:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [1999:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1999:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_4829 = _T_4823 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_4829 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_16 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_16 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_16(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_16 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_9 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue2_EgressFlit_9 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31) node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34) node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h9), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h5), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h15), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h3), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h11), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0hf), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h17), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0hb), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37) node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38) node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39) node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40) node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41) node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42) node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43) node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44) node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45) node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46) node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow	module EgressUnit_9( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_91 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_216 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_217 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_218 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_219 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_91( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SourceD_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<128>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip bs_rdat : { data : UInt<128>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_wdat : { data : UInt<128>}, flip evict_req : { set : UInt<11>, way : UInt<4>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<11>, way : UInt<4>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<2> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<2>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<4>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 3, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node s1_mask_sub_0_1 = geq(s1_req.size, UInt<3>(0h4)) node s1_mask_size = bits(s1_mask_sizeOH, 3, 3) node s1_mask_bit = bits(s1_req.offset, 3, 3) node s1_mask_nbit = eq(s1_mask_bit, UInt<1>(0h0)) node s1_mask_eq = and(UInt<1>(0h1), s1_mask_nbit) node _s1_mask_acc_T = and(s1_mask_size, s1_mask_eq) node s1_mask_acc = or(s1_mask_sub_0_1, _s1_mask_acc_T) node s1_mask_eq_1 = and(UInt<1>(0h1), s1_mask_bit) node _s1_mask_acc_T_1 = and(s1_mask_size, s1_mask_eq_1) node s1_mask_acc_1 = or(s1_mask_sub_0_1, _s1_mask_acc_T_1) node _s1_mask_T = cat(s1_mask_acc_1, s1_mask_acc) node _s1_mask_T_1 = not(s1_bypass) node s1_mask = and(_s1_mask_T, _s1_mask_T_1) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 4) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 4) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded_6 connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid \|\| queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<2>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<2>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<16>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<2>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<2>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass, 1, 1) node _s3_rdata_T_2 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_3 = bits(s3_bypass_data, 127, 64) node _s3_rdata_T_4 = bits(queue.io.deq.bits.data, 63, 0) node _s3_rdata_T_5 = bits(queue.io.deq.bits.data, 127, 64) node _s3_rdata_T_6 = mux(_s3_rdata_T, _s3_rdata_T_2, _s3_rdata_T_4) node _s3_rdata_T_7 = mux(_s3_rdata_T_1, _s3_rdata_T_3, _s3_rdata_T_5) node s3_rdata = cat(_s3_rdata_T_7, _s3_rdata_T_6) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<2>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<128>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics_6 connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = bits(s4_pdata.mask, 8, 8) node _io_bs_wadr_bits_mask_T_9 = bits(s4_pdata.mask, 9, 9) node _io_bs_wadr_bits_mask_T_10 = bits(s4_pdata.mask, 10, 10) node _io_bs_wadr_bits_mask_T_11 = bits(s4_pdata.mask, 11, 11) node _io_bs_wadr_bits_mask_T_12 = bits(s4_pdata.mask, 12, 12) node _io_bs_wadr_bits_mask_T_13 = bits(s4_pdata.mask, 13, 13) node _io_bs_wadr_bits_mask_T_14 = bits(s4_pdata.mask, 14, 14) node _io_bs_wadr_bits_mask_T_15 = bits(s4_pdata.mask, 15, 15) node _io_bs_wadr_bits_mask_T_16 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_17 = or(_io_bs_wadr_bits_mask_T_16, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_18 = or(_io_bs_wadr_bits_mask_T_17, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_19 = or(_io_bs_wadr_bits_mask_T_18, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_20 = or(_io_bs_wadr_bits_mask_T_19, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_21 = or(_io_bs_wadr_bits_mask_T_20, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_22 = or(_io_bs_wadr_bits_mask_T_21, _io_bs_wadr_bits_mask_T_7) node _io_bs_wadr_bits_mask_T_23 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_9) node _io_bs_wadr_bits_mask_T_24 = or(_io_bs_wadr_bits_mask_T_23, _io_bs_wadr_bits_mask_T_10) node _io_bs_wadr_bits_mask_T_25 = or(_io_bs_wadr_bits_mask_T_24, _io_bs_wadr_bits_mask_T_11) node _io_bs_wadr_bits_mask_T_26 = or(_io_bs_wadr_bits_mask_T_25, _io_bs_wadr_bits_mask_T_12) node _io_bs_wadr_bits_mask_T_27 = or(_io_bs_wadr_bits_mask_T_26, _io_bs_wadr_bits_mask_T_13) node _io_bs_wadr_bits_mask_T_28 = or(_io_bs_wadr_bits_mask_T_27, _io_bs_wadr_bits_mask_T_14) node _io_bs_wadr_bits_mask_T_29 = or(_io_bs_wadr_bits_mask_T_28, _io_bs_wadr_bits_mask_T_15) node _io_bs_wadr_bits_mask_T_30 = cat(_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_30 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<2>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<128>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<2>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<128>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<128>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<4>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 3, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass_sub_0_1 = geq(pre_s4_req.size, UInt<3>(0h4)) node pre_s3_4_bypass_size = bits(pre_s3_4_bypass_sizeOH, 3, 3) node pre_s3_4_bypass_bit = bits(pre_s4_req.offset, 3, 3) node pre_s3_4_bypass_nbit = eq(pre_s3_4_bypass_bit, UInt<1>(0h0)) node pre_s3_4_bypass_eq = and(UInt<1>(0h1), pre_s3_4_bypass_nbit) node _pre_s3_4_bypass_acc_T = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq) node pre_s3_4_bypass_acc = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T) node pre_s3_4_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_4_bypass_bit) node _pre_s3_4_bypass_acc_T_1 = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq_1) node pre_s3_4_bypass_acc_1 = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T_1) node _pre_s3_4_bypass_T = cat(pre_s3_4_bypass_acc_1, pre_s3_4_bypass_acc) node pre_s3_4_bypass = mux(pre_s3_4_match, _pre_s3_4_bypass_T, UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<4>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 3, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass_sub_0_1 = geq(pre_s5_req.size, UInt<3>(0h4)) node pre_s3_5_bypass_size = bits(pre_s3_5_bypass_sizeOH, 3, 3) node pre_s3_5_bypass_bit = bits(pre_s5_req.offset, 3, 3) node pre_s3_5_bypass_nbit = eq(pre_s3_5_bypass_bit, UInt<1>(0h0)) node pre_s3_5_bypass_eq = and(UInt<1>(0h1), pre_s3_5_bypass_nbit) node _pre_s3_5_bypass_acc_T = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq) node pre_s3_5_bypass_acc = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T) node pre_s3_5_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_5_bypass_bit) node _pre_s3_5_bypass_acc_T_1 = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq_1) node pre_s3_5_bypass_acc_1 = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T_1) node _pre_s3_5_bypass_T = cat(pre_s3_5_bypass_acc_1, pre_s3_5_bypass_acc) node pre_s3_5_bypass = mux(pre_s3_5_match, _pre_s3_5_bypass_T, UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<4>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 3, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass_sub_0_1 = geq(pre_s6_req.size, UInt<3>(0h4)) node pre_s3_6_bypass_size = bits(pre_s3_6_bypass_sizeOH, 3, 3) node pre_s3_6_bypass_bit = bits(pre_s6_req.offset, 3, 3) node pre_s3_6_bypass_nbit = eq(pre_s3_6_bypass_bit, UInt<1>(0h0)) node pre_s3_6_bypass_eq = and(UInt<1>(0h1), pre_s3_6_bypass_nbit) node _pre_s3_6_bypass_acc_T = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq) node pre_s3_6_bypass_acc = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T) node pre_s3_6_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_6_bypass_bit) node _pre_s3_6_bypass_acc_T_1 = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq_1) node pre_s3_6_bypass_acc_1 = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T_1) node _pre_s3_6_bypass_T = cat(pre_s3_6_bypass_acc_1, pre_s3_6_bypass_acc) node pre_s3_6_bypass = mux(pre_s3_6_match, _pre_s3_6_bypass_T, UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s3_6_bypass, 1, 1) node _s3_bypass_data_T_2 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_3 = bits(pre_s6_dat, 127, 64) node _s3_bypass_data_T_4 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_5 = bits(pre_s7_dat, 127, 64) node _s3_bypass_data_T_6 = mux(_s3_bypass_data_T, _s3_bypass_data_T_2, _s3_bypass_data_T_4) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_1, _s3_bypass_data_T_3, _s3_bypass_data_T_5) node _s3_bypass_data_T_8 = cat(_s3_bypass_data_T_7, _s3_bypass_data_T_6) node _s3_bypass_data_T_9 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_10 = bits(pre_s3_5_bypass, 1, 1) node _s3_bypass_data_T_11 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_12 = bits(pre_s5_dat, 127, 64) node _s3_bypass_data_T_13 = bits(_s3_bypass_data_T_8, 63, 0) node _s3_bypass_data_T_14 = bits(_s3_bypass_data_T_8, 127, 64) node _s3_bypass_data_T_15 = mux(_s3_bypass_data_T_9, _s3_bypass_data_T_11, _s3_bypass_data_T_13) node _s3_bypass_data_T_16 = mux(_s3_bypass_data_T_10, _s3_bypass_data_T_12, _s3_bypass_data_T_14) node _s3_bypass_data_T_17 = cat(_s3_bypass_data_T_16, _s3_bypass_data_T_15) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_17 node _s3_bypass_data_T_18 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_19 = bits(s3_bypass_data_REG, 1, 1) node _s3_bypass_data_T_20 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_21 = bits(atomics.io.data_out, 127, 64) node _s3_bypass_data_T_22 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_23 = bits(s3_bypass_data_REG_1, 127, 64) node _s3_bypass_data_T_24 = mux(_s3_bypass_data_T_18, _s3_bypass_data_T_20, _s3_bypass_data_T_22) node _s3_bypass_data_T_25 = mux(_s3_bypass_data_T_19, _s3_bypass_data_T_21, _s3_bypass_data_T_23) node _s3_bypass_data_T_26 = cat(_s3_bypass_data_T_25, _s3_bypass_data_T_24) connect s3_bypass_data, _s3_bypass_data_T_26 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<4>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 3, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass_sub_0_1 = geq(s2_req.size, UInt<3>(0h4)) node s1_2_bypass_size = bits(s1_2_bypass_sizeOH, 3, 3) node s1_2_bypass_bit = bits(s2_req.offset, 3, 3) node s1_2_bypass_nbit = eq(s1_2_bypass_bit, UInt<1>(0h0)) node s1_2_bypass_eq = and(UInt<1>(0h1), s1_2_bypass_nbit) node _s1_2_bypass_acc_T = and(s1_2_bypass_size, s1_2_bypass_eq) node s1_2_bypass_acc = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T) node s1_2_bypass_eq_1 = and(UInt<1>(0h1), s1_2_bypass_bit) node _s1_2_bypass_acc_T_1 = and(s1_2_bypass_size, s1_2_bypass_eq_1) node s1_2_bypass_acc_1 = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T_1) node _s1_2_bypass_T = cat(s1_2_bypass_acc_1, s1_2_bypass_acc) node s1_2_bypass = mux(s1_2_match, _s1_2_bypass_T, UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<4>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 3, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass_sub_0_1 = geq(s3_req.size, UInt<3>(0h4)) node s1_3_bypass_size = bits(s1_3_bypass_sizeOH, 3, 3) node s1_3_bypass_bit = bits(s3_req.offset, 3, 3) node s1_3_bypass_nbit = eq(s1_3_bypass_bit, UInt<1>(0h0)) node s1_3_bypass_eq = and(UInt<1>(0h1), s1_3_bypass_nbit) node _s1_3_bypass_acc_T = and(s1_3_bypass_size, s1_3_bypass_eq) node s1_3_bypass_acc = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T) node s1_3_bypass_eq_1 = and(UInt<1>(0h1), s1_3_bypass_bit) node _s1_3_bypass_acc_T_1 = and(s1_3_bypass_size, s1_3_bypass_eq_1) node s1_3_bypass_acc_1 = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T_1) node _s1_3_bypass_T = cat(s1_3_bypass_acc_1, s1_3_bypass_acc) node s1_3_bypass = mux(s1_3_match, _s1_3_bypass_T, UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<4>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 3, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass_sub_0_1 = geq(s4_req.size, UInt<3>(0h4)) node s1_4_bypass_size = bits(s1_4_bypass_sizeOH, 3, 3) node s1_4_bypass_bit = bits(s4_req.offset, 3, 3) node s1_4_bypass_nbit = eq(s1_4_bypass_bit, UInt<1>(0h0)) node s1_4_bypass_eq = and(UInt<1>(0h1), s1_4_bypass_nbit) node _s1_4_bypass_acc_T = and(s1_4_bypass_size, s1_4_bypass_eq) node s1_4_bypass_acc = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T) node s1_4_bypass_eq_1 = and(UInt<1>(0h1), s1_4_bypass_bit) node _s1_4_bypass_acc_T_1 = and(s1_4_bypass_size, s1_4_bypass_eq_1) node s1_4_bypass_acc_1 = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T_1) node _s1_4_bypass_T = cat(s1_4_bypass_acc_1, s1_4_bypass_acc) node s1_4_bypass = mux(s1_4_match, _s1_4_bypass_T, UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22	module SourceD_6( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [10:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [3:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [10:0] io_evict_req_set, // @[SourceD.scala:50:14] input [3:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [10:0] io_grant_req_set, // @[SourceD.scala:50:14] input [3:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [3:0] s1_req_way; // @[SourceD.scala:88:19] wire [10:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 \| _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 \| _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = \|s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [8:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [10:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [3:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [8:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [10:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [3:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [8:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [10:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [3:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 \| _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 \| _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 \| _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 \| _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 \| _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 \| _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_11 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) connect wentry.conf, UInt<1>(0h0) else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE	module LoopBranchPredictorColumn_11( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_5 \| ~(_T_39 \| ~(_T_44 \| _GEN_4 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_7 \| ~(_T_44 \| _T_47 \| ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_5 \| _T_39 \| ~(_T_44 \| ~(_GEN_4 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_218 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_218( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_32 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_64 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_32 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<1>(0h0), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<1>(0h1), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<4>(0hd), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_65 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_32 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node _c_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi, c_lo) node _c_T_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_1 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_1 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_1, c_lo_1) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node out_channel_oh_0 = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _out_bundle_bits_out_virt_channel_T_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 1) node _out_bundle_bits_out_virt_channel_T_2 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_1, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_3 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_4 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_5 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = or(_out_bundle_bits_out_virt_channel_T_2, _out_bundle_bits_out_virt_channel_T_3) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_4) node _out_bundle_bits_out_virt_channel_T_8 = or(_out_bundle_bits_out_virt_channel_T_7, _out_bundle_bits_out_virt_channel_T_5) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<1> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_8 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_32( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(\|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (\|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_16 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[10], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], chosen_oh : UInt<10>[1]} regreset lock_0 : UInt<10>, clock, reset, UInt<10>(0h0) node unassigned_lo_lo = cat(io.in[1].valid, io.in[0].valid) node unassigned_lo_hi_hi = cat(io.in[4].valid, io.in[3].valid) node unassigned_lo_hi = cat(unassigned_lo_hi_hi, io.in[2].valid) node unassigned_lo = cat(unassigned_lo_hi, unassigned_lo_lo) node unassigned_hi_lo = cat(io.in[6].valid, io.in[5].valid) node unassigned_hi_hi_hi = cat(io.in[9].valid, io.in[8].valid) node unassigned_hi_hi = cat(unassigned_hi_hi_hi, io.in[7].valid) node unassigned_hi = cat(unassigned_hi_hi, unassigned_hi_lo) node _unassigned_T = cat(unassigned_hi, unassigned_lo) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire choices : UInt<10>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = bits(_sel_T_2, 6, 6) node _sel_T_10 = bits(_sel_T_2, 7, 7) node _sel_T_11 = bits(_sel_T_2, 8, 8) node _sel_T_12 = bits(_sel_T_2, 9, 9) node _sel_T_13 = bits(_sel_T_2, 10, 10) node _sel_T_14 = bits(_sel_T_2, 11, 11) node _sel_T_15 = bits(_sel_T_2, 12, 12) node _sel_T_16 = bits(_sel_T_2, 13, 13) node _sel_T_17 = bits(_sel_T_2, 14, 14) node _sel_T_18 = bits(_sel_T_2, 15, 15) node _sel_T_19 = bits(_sel_T_2, 16, 16) node _sel_T_20 = bits(_sel_T_2, 17, 17) node _sel_T_21 = bits(_sel_T_2, 18, 18) node _sel_T_22 = bits(_sel_T_2, 19, 19) node _sel_T_23 = mux(_sel_T_22, UInt<20>(0h80000), UInt<20>(0h0)) node _sel_T_24 = mux(_sel_T_21, UInt<20>(0h40000), _sel_T_23) node _sel_T_25 = mux(_sel_T_20, UInt<20>(0h20000), _sel_T_24) node _sel_T_26 = mux(_sel_T_19, UInt<20>(0h10000), _sel_T_25) node _sel_T_27 = mux(_sel_T_18, UInt<20>(0h8000), _sel_T_26) node _sel_T_28 = mux(_sel_T_17, UInt<20>(0h4000), _sel_T_27) node _sel_T_29 = mux(_sel_T_16, UInt<20>(0h2000), _sel_T_28) node _sel_T_30 = mux(_sel_T_15, UInt<20>(0h1000), _sel_T_29) node _sel_T_31 = mux(_sel_T_14, UInt<20>(0h800), _sel_T_30) node _sel_T_32 = mux(_sel_T_13, UInt<20>(0h400), _sel_T_31) node _sel_T_33 = mux(_sel_T_12, UInt<20>(0h200), _sel_T_32) node _sel_T_34 = mux(_sel_T_11, UInt<20>(0h100), _sel_T_33) node _sel_T_35 = mux(_sel_T_10, UInt<20>(0h80), _sel_T_34) node _sel_T_36 = mux(_sel_T_9, UInt<20>(0h40), _sel_T_35) node _sel_T_37 = mux(_sel_T_8, UInt<20>(0h20), _sel_T_36) node _sel_T_38 = mux(_sel_T_7, UInt<20>(0h10), _sel_T_37) node _sel_T_39 = mux(_sel_T_6, UInt<20>(0h8), _sel_T_38) node _sel_T_40 = mux(_sel_T_5, UInt<20>(0h4), _sel_T_39) node _sel_T_41 = mux(_sel_T_4, UInt<20>(0h2), _sel_T_40) node sel = mux(_sel_T_3, UInt<20>(0h1), _sel_T_41) node _choices_0_T = shr(sel, 10) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = bits(_T_1, 3, 3) node _T_6 = bits(_T_1, 4, 4) node _T_7 = bits(_T_1, 5, 5) node _T_8 = bits(_T_1, 6, 6) node _T_9 = bits(_T_1, 7, 7) node _T_10 = bits(_T_1, 8, 8) node _T_11 = bits(_T_1, 9, 9) node _T_12 = mux(_T_11, UInt<10>(0h200), UInt<10>(0h0)) node _T_13 = mux(_T_10, UInt<10>(0h100), _T_12) node _T_14 = mux(_T_9, UInt<10>(0h80), _T_13) node _T_15 = mux(_T_8, UInt<10>(0h40), _T_14) node _T_16 = mux(_T_7, UInt<10>(0h20), _T_15) node _T_17 = mux(_T_6, UInt<10>(0h10), _T_16) node _T_18 = mux(_T_5, UInt<10>(0h8), _T_17) node _T_19 = mux(_T_4, UInt<10>(0h4), _T_18) node _T_20 = mux(_T_3, UInt<10>(0h2), _T_19) node _T_21 = mux(_T_2, UInt<10>(0h1), _T_20) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) connect io.in[3].ready, UInt<1>(0h0) connect io.in[4].ready, UInt<1>(0h0) connect io.in[5].ready, UInt<1>(0h0) connect io.in[6].ready, UInt<1>(0h0) connect io.in[7].ready, UInt<1>(0h0) connect io.in[8].ready, UInt<1>(0h0) connect io.in[9].ready, UInt<1>(0h0) node in_tails_lo_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail) node in_tails_lo_hi_hi = cat(io.in[4].bits.tail, io.in[3].bits.tail) node in_tails_lo_hi = cat(in_tails_lo_hi_hi, io.in[2].bits.tail) node in_tails_lo = cat(in_tails_lo_hi, in_tails_lo_lo) node in_tails_hi_lo = cat(io.in[6].bits.tail, io.in[5].bits.tail) node in_tails_hi_hi_hi = cat(io.in[9].bits.tail, io.in[8].bits.tail) node in_tails_hi_hi = cat(in_tails_hi_hi_hi, io.in[7].bits.tail) node in_tails_hi = cat(in_tails_hi_hi, in_tails_hi_lo) node in_tails = cat(in_tails_hi, in_tails_lo) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6) node _in_valids_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_9 = and(io.in[4].valid, _in_valids_T_8) node _in_valids_T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_11 = and(io.in[5].valid, _in_valids_T_10) node _in_valids_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_13 = and(io.in[6].valid, _in_valids_T_12) node _in_valids_T_14 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_15 = and(io.in[7].valid, _in_valids_T_14) node _in_valids_T_16 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_17 = and(io.in[8].valid, _in_valids_T_16) node _in_valids_T_18 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_19 = and(io.in[9].valid, _in_valids_T_18) node in_valids_lo_lo = cat(_in_valids_T_3, _in_valids_T_1) node in_valids_lo_hi_hi = cat(_in_valids_T_9, _in_valids_T_7) node in_valids_lo_hi = cat(in_valids_lo_hi_hi, _in_valids_T_5) node in_valids_lo = cat(in_valids_lo_hi, in_valids_lo_lo) node in_valids_hi_lo = cat(_in_valids_T_13, _in_valids_T_11) node in_valids_hi_hi_hi = cat(_in_valids_T_19, _in_valids_T_17) node in_valids_hi_hi = cat(in_valids_hi_hi_hi, _in_valids_T_15) node in_valids_hi = cat(in_valids_hi_hi, in_valids_hi_lo) node in_valids = cat(in_valids_hi, in_valids_lo) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<10>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) node _io_out_0_bits_T_3 = bits(chosen, 3, 3) node _io_out_0_bits_T_4 = bits(chosen, 4, 4) node _io_out_0_bits_T_5 = bits(chosen, 5, 5) node _io_out_0_bits_T_6 = bits(chosen, 6, 6) node _io_out_0_bits_T_7 = bits(chosen, 7, 7) node _io_out_0_bits_T_8 = bits(chosen, 8, 8) node _io_out_0_bits_T_9 = bits(chosen, 9, 9) wire _io_out_0_bits_WIRE : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>} node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_4, io.in[4].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_5, io.in[5].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_16 = mux(_io_out_0_bits_T_6, io.in[6].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T_7, io.in[7].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_8, io.in[8].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_9, io.in[9].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_20 = or(_io_out_0_bits_T_10, _io_out_0_bits_T_11) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_12) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_13) node _io_out_0_bits_T_23 = or(_io_out_0_bits_T_22, _io_out_0_bits_T_14) node _io_out_0_bits_T_24 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_15) node _io_out_0_bits_T_25 = or(_io_out_0_bits_T_24, _io_out_0_bits_T_16) node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_25, _io_out_0_bits_T_17) node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_18) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_27, _io_out_0_bits_T_19) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_28 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_out_0_bits_WIRE_3 : UInt<1>[10] node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_31 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_36 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_37 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_39 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_30) node _io_out_0_bits_T_40 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_31) node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_40, _io_out_0_bits_T_32) node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_33) node _io_out_0_bits_T_43 = or(_io_out_0_bits_T_42, _io_out_0_bits_T_34) node _io_out_0_bits_T_44 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_35) node _io_out_0_bits_T_45 = or(_io_out_0_bits_T_44, _io_out_0_bits_T_36) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_45, _io_out_0_bits_T_37) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_38) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_47 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_51 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_52 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_57 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49) node _io_out_0_bits_T_59 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_50) node _io_out_0_bits_T_60 = or(_io_out_0_bits_T_59, _io_out_0_bits_T_51) node _io_out_0_bits_T_61 = or(_io_out_0_bits_T_60, _io_out_0_bits_T_52) node _io_out_0_bits_T_62 = or(_io_out_0_bits_T_61, _io_out_0_bits_T_53) node _io_out_0_bits_T_63 = or(_io_out_0_bits_T_62, _io_out_0_bits_T_54) node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_63, _io_out_0_bits_T_55) node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_56) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_57) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_66 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_67 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_71 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_72 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_73 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_74 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_75 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_76 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_77 = or(_io_out_0_bits_T_67, _io_out_0_bits_T_68) node _io_out_0_bits_T_78 = or(_io_out_0_bits_T_77, _io_out_0_bits_T_69) node _io_out_0_bits_T_79 = or(_io_out_0_bits_T_78, _io_out_0_bits_T_70) node _io_out_0_bits_T_80 = or(_io_out_0_bits_T_79, _io_out_0_bits_T_71) node _io_out_0_bits_T_81 = or(_io_out_0_bits_T_80, _io_out_0_bits_T_72) node _io_out_0_bits_T_82 = or(_io_out_0_bits_T_81, _io_out_0_bits_T_73) node _io_out_0_bits_T_83 = or(_io_out_0_bits_T_82, _io_out_0_bits_T_74) node _io_out_0_bits_T_84 = or(_io_out_0_bits_T_83, _io_out_0_bits_T_75) node _io_out_0_bits_T_85 = or(_io_out_0_bits_T_84, _io_out_0_bits_T_76) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_85 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_86 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_87 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_91 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_92 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_93 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_94 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_95 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_96 = or(_io_out_0_bits_T_86, _io_out_0_bits_T_87) node _io_out_0_bits_T_97 = or(_io_out_0_bits_T_96, _io_out_0_bits_T_88) node _io_out_0_bits_T_98 = or(_io_out_0_bits_T_97, _io_out_0_bits_T_89) node _io_out_0_bits_T_99 = or(_io_out_0_bits_T_98, _io_out_0_bits_T_90) node _io_out_0_bits_T_100 = or(_io_out_0_bits_T_99, _io_out_0_bits_T_91) node _io_out_0_bits_T_101 = or(_io_out_0_bits_T_100, _io_out_0_bits_T_92) node _io_out_0_bits_T_102 = or(_io_out_0_bits_T_101, _io_out_0_bits_T_93) node _io_out_0_bits_T_103 = or(_io_out_0_bits_T_102, _io_out_0_bits_T_94) node _io_out_0_bits_T_104 = or(_io_out_0_bits_T_103, _io_out_0_bits_T_95) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_104 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_105 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_106 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_107 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_108 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_109 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_110 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_111 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_112 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_113 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_114 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_115 = or(_io_out_0_bits_T_105, _io_out_0_bits_T_106) node _io_out_0_bits_T_116 = or(_io_out_0_bits_T_115, _io_out_0_bits_T_107) node _io_out_0_bits_T_117 = or(_io_out_0_bits_T_116, _io_out_0_bits_T_108) node _io_out_0_bits_T_118 = or(_io_out_0_bits_T_117, _io_out_0_bits_T_109) node _io_out_0_bits_T_119 = or(_io_out_0_bits_T_118, _io_out_0_bits_T_110) node _io_out_0_bits_T_120 = or(_io_out_0_bits_T_119, _io_out_0_bits_T_111) node _io_out_0_bits_T_121 = or(_io_out_0_bits_T_120, _io_out_0_bits_T_112) node _io_out_0_bits_T_122 = or(_io_out_0_bits_T_121, _io_out_0_bits_T_113) node _io_out_0_bits_T_123 = or(_io_out_0_bits_T_122, _io_out_0_bits_T_114) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_123 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_124 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_125 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_126 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_127 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_128 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_129 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_130 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_131 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_132 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_133 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_134 = or(_io_out_0_bits_T_124, _io_out_0_bits_T_125) node _io_out_0_bits_T_135 = or(_io_out_0_bits_T_134, _io_out_0_bits_T_126) node _io_out_0_bits_T_136 = or(_io_out_0_bits_T_135, _io_out_0_bits_T_127) node _io_out_0_bits_T_137 = or(_io_out_0_bits_T_136, _io_out_0_bits_T_128) node _io_out_0_bits_T_138 = or(_io_out_0_bits_T_137, _io_out_0_bits_T_129) node _io_out_0_bits_T_139 = or(_io_out_0_bits_T_138, _io_out_0_bits_T_130) node _io_out_0_bits_T_140 = or(_io_out_0_bits_T_139, _io_out_0_bits_T_131) node _io_out_0_bits_T_141 = or(_io_out_0_bits_T_140, _io_out_0_bits_T_132) node _io_out_0_bits_T_142 = or(_io_out_0_bits_T_141, _io_out_0_bits_T_133) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_142 connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_143 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_144 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_145 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_146 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_147 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_148 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_149 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_150 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_151 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_152 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_153 = or(_io_out_0_bits_T_143, _io_out_0_bits_T_144) node _io_out_0_bits_T_154 = or(_io_out_0_bits_T_153, _io_out_0_bits_T_145) node _io_out_0_bits_T_155 = or(_io_out_0_bits_T_154, _io_out_0_bits_T_146) node _io_out_0_bits_T_156 = or(_io_out_0_bits_T_155, _io_out_0_bits_T_147) node _io_out_0_bits_T_157 = or(_io_out_0_bits_T_156, _io_out_0_bits_T_148) node _io_out_0_bits_T_158 = or(_io_out_0_bits_T_157, _io_out_0_bits_T_149) node _io_out_0_bits_T_159 = or(_io_out_0_bits_T_158, _io_out_0_bits_T_150) node _io_out_0_bits_T_160 = or(_io_out_0_bits_T_159, _io_out_0_bits_T_151) node _io_out_0_bits_T_161 = or(_io_out_0_bits_T_160, _io_out_0_bits_T_152) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_161 connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_162 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_163 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_164 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_165 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_166 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_167 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_168 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_169 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_170 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_171 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_172 = or(_io_out_0_bits_T_162, _io_out_0_bits_T_163) node _io_out_0_bits_T_173 = or(_io_out_0_bits_T_172, _io_out_0_bits_T_164) node _io_out_0_bits_T_174 = or(_io_out_0_bits_T_173, _io_out_0_bits_T_165) node _io_out_0_bits_T_175 = or(_io_out_0_bits_T_174, _io_out_0_bits_T_166) node _io_out_0_bits_T_176 = or(_io_out_0_bits_T_175, _io_out_0_bits_T_167) node _io_out_0_bits_T_177 = or(_io_out_0_bits_T_176, _io_out_0_bits_T_168) node _io_out_0_bits_T_178 = or(_io_out_0_bits_T_177, _io_out_0_bits_T_169) node _io_out_0_bits_T_179 = or(_io_out_0_bits_T_178, _io_out_0_bits_T_170) node _io_out_0_bits_T_180 = or(_io_out_0_bits_T_179, _io_out_0_bits_T_171) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_180 connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11 node _io_out_0_bits_T_181 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_182 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_183 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_184 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_185 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_186 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_187 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_188 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_189 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_190 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_191 = or(_io_out_0_bits_T_181, _io_out_0_bits_T_182) node _io_out_0_bits_T_192 = or(_io_out_0_bits_T_191, _io_out_0_bits_T_183) node _io_out_0_bits_T_193 = or(_io_out_0_bits_T_192, _io_out_0_bits_T_184) node _io_out_0_bits_T_194 = or(_io_out_0_bits_T_193, _io_out_0_bits_T_185) node _io_out_0_bits_T_195 = or(_io_out_0_bits_T_194, _io_out_0_bits_T_186) node _io_out_0_bits_T_196 = or(_io_out_0_bits_T_195, _io_out_0_bits_T_187) node _io_out_0_bits_T_197 = or(_io_out_0_bits_T_196, _io_out_0_bits_T_188) node _io_out_0_bits_T_198 = or(_io_out_0_bits_T_197, _io_out_0_bits_T_189) node _io_out_0_bits_T_199 = or(_io_out_0_bits_T_198, _io_out_0_bits_T_190) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_199 connect _io_out_0_bits_WIRE_3[8], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_200 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_201 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_202 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_203 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_204 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_205 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_206 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_207 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_208 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_209 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_210 = or(_io_out_0_bits_T_200, _io_out_0_bits_T_201) node _io_out_0_bits_T_211 = or(_io_out_0_bits_T_210, _io_out_0_bits_T_202) node _io_out_0_bits_T_212 = or(_io_out_0_bits_T_211, _io_out_0_bits_T_203) node _io_out_0_bits_T_213 = or(_io_out_0_bits_T_212, _io_out_0_bits_T_204) node _io_out_0_bits_T_214 = or(_io_out_0_bits_T_213, _io_out_0_bits_T_205) node _io_out_0_bits_T_215 = or(_io_out_0_bits_T_214, _io_out_0_bits_T_206) node _io_out_0_bits_T_216 = or(_io_out_0_bits_T_215, _io_out_0_bits_T_207) node _io_out_0_bits_T_217 = or(_io_out_0_bits_T_216, _io_out_0_bits_T_208) node _io_out_0_bits_T_218 = or(_io_out_0_bits_T_217, _io_out_0_bits_T_209) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_218 connect _io_out_0_bits_WIRE_3[9], _io_out_0_bits_WIRE_13 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_14 : UInt<1>[1] node _io_out_0_bits_T_219 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_220 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_221 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_222 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_223 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_224 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_225 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_226 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_227 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_228 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_229 = or(_io_out_0_bits_T_219, _io_out_0_bits_T_220) node _io_out_0_bits_T_230 = or(_io_out_0_bits_T_229, _io_out_0_bits_T_221) node _io_out_0_bits_T_231 = or(_io_out_0_bits_T_230, _io_out_0_bits_T_222) node _io_out_0_bits_T_232 = or(_io_out_0_bits_T_231, _io_out_0_bits_T_223) node _io_out_0_bits_T_233 = or(_io_out_0_bits_T_232, _io_out_0_bits_T_224) node _io_out_0_bits_T_234 = or(_io_out_0_bits_T_233, _io_out_0_bits_T_225) node _io_out_0_bits_T_235 = or(_io_out_0_bits_T_234, _io_out_0_bits_T_226) node _io_out_0_bits_T_236 = or(_io_out_0_bits_T_235, _io_out_0_bits_T_227) node _io_out_0_bits_T_237 = or(_io_out_0_bits_T_236, _io_out_0_bits_T_228) wire _io_out_0_bits_WIRE_15 : UInt<1> connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_237 connect _io_out_0_bits_WIRE_14[0], _io_out_0_bits_WIRE_15 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_14 wire _io_out_0_bits_WIRE_16 : UInt<1>[1] node _io_out_0_bits_T_238 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_239 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_240 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_241 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_242 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_243 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_244 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_245 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_246 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_247 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_248 = or(_io_out_0_bits_T_238, _io_out_0_bits_T_239) node _io_out_0_bits_T_249 = or(_io_out_0_bits_T_248, _io_out_0_bits_T_240) node _io_out_0_bits_T_250 = or(_io_out_0_bits_T_249, _io_out_0_bits_T_241) node _io_out_0_bits_T_251 = or(_io_out_0_bits_T_250, _io_out_0_bits_T_242) node _io_out_0_bits_T_252 = or(_io_out_0_bits_T_251, _io_out_0_bits_T_243) node _io_out_0_bits_T_253 = or(_io_out_0_bits_T_252, _io_out_0_bits_T_244) node _io_out_0_bits_T_254 = or(_io_out_0_bits_T_253, _io_out_0_bits_T_245) node _io_out_0_bits_T_255 = or(_io_out_0_bits_T_254, _io_out_0_bits_T_246) node _io_out_0_bits_T_256 = or(_io_out_0_bits_T_255, _io_out_0_bits_T_247) wire _io_out_0_bits_WIRE_17 : UInt<1> connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_256 connect _io_out_0_bits_WIRE_16[0], _io_out_0_bits_WIRE_17 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_16 wire _io_out_0_bits_WIRE_18 : UInt<1>[1] node _io_out_0_bits_T_257 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_258 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_259 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_260 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_261 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_262 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_263 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_264 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_265 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_266 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_267 = or(_io_out_0_bits_T_257, _io_out_0_bits_T_258) node _io_out_0_bits_T_268 = or(_io_out_0_bits_T_267, _io_out_0_bits_T_259) node _io_out_0_bits_T_269 = or(_io_out_0_bits_T_268, _io_out_0_bits_T_260) node _io_out_0_bits_T_270 = or(_io_out_0_bits_T_269, _io_out_0_bits_T_261) node _io_out_0_bits_T_271 = or(_io_out_0_bits_T_270, _io_out_0_bits_T_262) node _io_out_0_bits_T_272 = or(_io_out_0_bits_T_271, _io_out_0_bits_T_263) node _io_out_0_bits_T_273 = or(_io_out_0_bits_T_272, _io_out_0_bits_T_264) node _io_out_0_bits_T_274 = or(_io_out_0_bits_T_273, _io_out_0_bits_T_265) node _io_out_0_bits_T_275 = or(_io_out_0_bits_T_274, _io_out_0_bits_T_266) wire _io_out_0_bits_WIRE_19 : UInt<1> connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_275 connect _io_out_0_bits_WIRE_18[0], _io_out_0_bits_WIRE_19 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_18 wire _io_out_0_bits_WIRE_20 : UInt<1>[1] node _io_out_0_bits_T_276 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_277 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_278 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_279 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_280 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_281 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_282 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_283 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_284 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_285 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_286 = or(_io_out_0_bits_T_276, _io_out_0_bits_T_277) node _io_out_0_bits_T_287 = or(_io_out_0_bits_T_286, _io_out_0_bits_T_278) node _io_out_0_bits_T_288 = or(_io_out_0_bits_T_287, _io_out_0_bits_T_279) node _io_out_0_bits_T_289 = or(_io_out_0_bits_T_288, _io_out_0_bits_T_280) node _io_out_0_bits_T_290 = or(_io_out_0_bits_T_289, _io_out_0_bits_T_281) node _io_out_0_bits_T_291 = or(_io_out_0_bits_T_290, _io_out_0_bits_T_282) node _io_out_0_bits_T_292 = or(_io_out_0_bits_T_291, _io_out_0_bits_T_283) node _io_out_0_bits_T_293 = or(_io_out_0_bits_T_292, _io_out_0_bits_T_284) node _io_out_0_bits_T_294 = or(_io_out_0_bits_T_293, _io_out_0_bits_T_285) wire _io_out_0_bits_WIRE_21 : UInt<1> connect _io_out_0_bits_WIRE_21, _io_out_0_bits_T_294 connect _io_out_0_bits_WIRE_20[0], _io_out_0_bits_WIRE_21 connect _io_out_0_bits_WIRE_2.`4`, _io_out_0_bits_WIRE_20 wire _io_out_0_bits_WIRE_22 : UInt<1>[1] node _io_out_0_bits_T_295 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_296 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_297 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_298 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_299 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_300 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_301 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_302 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_303 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_304 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_305 = or(_io_out_0_bits_T_295, _io_out_0_bits_T_296) node _io_out_0_bits_T_306 = or(_io_out_0_bits_T_305, _io_out_0_bits_T_297) node _io_out_0_bits_T_307 = or(_io_out_0_bits_T_306, _io_out_0_bits_T_298) node _io_out_0_bits_T_308 = or(_io_out_0_bits_T_307, _io_out_0_bits_T_299) node _io_out_0_bits_T_309 = or(_io_out_0_bits_T_308, _io_out_0_bits_T_300) node _io_out_0_bits_T_310 = or(_io_out_0_bits_T_309, _io_out_0_bits_T_301) node _io_out_0_bits_T_311 = or(_io_out_0_bits_T_310, _io_out_0_bits_T_302) node _io_out_0_bits_T_312 = or(_io_out_0_bits_T_311, _io_out_0_bits_T_303) node _io_out_0_bits_T_313 = or(_io_out_0_bits_T_312, _io_out_0_bits_T_304) wire _io_out_0_bits_WIRE_23 : UInt<1> connect _io_out_0_bits_WIRE_23, _io_out_0_bits_T_313 connect _io_out_0_bits_WIRE_22[0], _io_out_0_bits_WIRE_23 connect _io_out_0_bits_WIRE_2.`5`, _io_out_0_bits_WIRE_22 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_22 = bits(chosen, 0, 0) node _T_23 = and(_T_22, io.out[0].ready) when _T_23 : connect io.in[0].ready, UInt<1>(0h1) node _T_24 = bits(chosen, 1, 1) node _T_25 = and(_T_24, io.out[0].ready) when _T_25 : connect io.in[1].ready, UInt<1>(0h1) node _T_26 = bits(chosen, 2, 2) node _T_27 = and(_T_26, io.out[0].ready) when _T_27 : connect io.in[2].ready, UInt<1>(0h1) node _T_28 = bits(chosen, 3, 3) node _T_29 = and(_T_28, io.out[0].ready) when _T_29 : connect io.in[3].ready, UInt<1>(0h1) node _T_30 = bits(chosen, 4, 4) node _T_31 = and(_T_30, io.out[0].ready) when _T_31 : connect io.in[4].ready, UInt<1>(0h1) node _T_32 = bits(chosen, 5, 5) node _T_33 = and(_T_32, io.out[0].ready) when _T_33 : connect io.in[5].ready, UInt<1>(0h1) node _T_34 = bits(chosen, 6, 6) node _T_35 = and(_T_34, io.out[0].ready) when _T_35 : connect io.in[6].ready, UInt<1>(0h1) node _T_36 = bits(chosen, 7, 7) node _T_37 = and(_T_36, io.out[0].ready) when _T_37 : connect io.in[7].ready, UInt<1>(0h1) node _T_38 = bits(chosen, 8, 8) node _T_39 = and(_T_38, io.out[0].ready) when _T_39 : connect io.in[8].ready, UInt<1>(0h1) node _T_40 = bits(chosen, 9, 9) node _T_41 = and(_T_40, io.out[0].ready) when _T_41 : connect io.in[9].ready, UInt<1>(0h1) node _T_42 = or(UInt<10>(0h0), chosen) node _T_43 = and(io.out[0].ready, io.out[0].valid) when _T_43 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_44 = and(io.out[0].ready, io.out[0].valid) when _T_44 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = shr(io.chosen_oh[0], 3) node _mask_T_4 = shr(io.chosen_oh[0], 4) node _mask_T_5 = shr(io.chosen_oh[0], 5) node _mask_T_6 = shr(io.chosen_oh[0], 6) node _mask_T_7 = shr(io.chosen_oh[0], 7) node _mask_T_8 = shr(io.chosen_oh[0], 8) node _mask_T_9 = shr(io.chosen_oh[0], 9) node _mask_T_10 = or(_mask_T, _mask_T_1) node _mask_T_11 = or(_mask_T_10, _mask_T_2) node _mask_T_12 = or(_mask_T_11, _mask_T_3) node _mask_T_13 = or(_mask_T_12, _mask_T_4) node _mask_T_14 = or(_mask_T_13, _mask_T_5) node _mask_T_15 = or(_mask_T_14, _mask_T_6) node _mask_T_16 = or(_mask_T_15, _mask_T_7) node _mask_T_17 = or(_mask_T_16, _mask_T_8) node _mask_T_18 = or(_mask_T_17, _mask_T_9) connect mask, _mask_T_18 else : node _mask_T_19 = not(mask) node _mask_T_20 = eq(_mask_T_19, UInt<1>(0h0)) node _mask_T_21 = shl(mask, 1) node _mask_T_22 = or(_mask_T_21, UInt<1>(0h1)) node _mask_T_23 = mux(_mask_T_20, UInt<1>(0h0), _mask_T_22) connect mask, _mask_T_23	module SwitchArbiter_16( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_8_ready, // @[SwitchAllocator.scala:18:14] input io_in_8_valid, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_9_ready, // @[SwitchAllocator.scala:18:14] input io_in_9_valid, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [9:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [9:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [9:0] unassigned = {io_in_9_valid, io_in_8_valid, 2'h0, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [9:0] mask; // @[SwitchAllocator.scala:27:21] wire [9:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [19:0] sel = _sel_T_1[0] ? 20'h1 : _sel_T_1[1] ? 20'h2 : _sel_T_1[2] ? 20'h4 : _sel_T_1[3] ? 20'h8 : _sel_T_1[4] ? 20'h10 : _sel_T_1[5] ? 20'h20 : _sel_T_1[6] ? 20'h40 : _sel_T_1[7] ? 20'h80 : _sel_T_1[8] ? 20'h100 : _sel_T_1[9] ? 20'h200 : unassigned[0] ? 20'h400 : unassigned[1] ? 20'h800 : unassigned[2] ? 20'h1000 : unassigned[3] ? 20'h2000 : unassigned[4] ? 20'h4000 : unassigned[5] ? 20'h8000 : unassigned[6] ? 20'h10000 : unassigned[7] ? 20'h20000 : unassigned[8] ? 20'h40000 : {unassigned[9], 19'h0}; // @[OneHot.scala:85:71] wire [9:0] in_valids = {io_in_9_valid, io_in_8_valid, 2'h0, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [9:0] _chosen_T_2 = in_valids & lock_0; // @[SwitchAllocator.scala:24:38, :41:24, :42:33] wire [9:0] chosen = (\|{_chosen_T_2[9:8], _chosen_T_2[5:0]}) ? lock_0 : sel[9:0] \| sel[19:10]; // @[Mux.scala:50:70] wire [9:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [7:0] _GEN = {_io_out_0_valid_T[9:8], _io_out_0_valid_T[5:0]}; // @[SwitchAllocator.scala:44:35] wire _GEN_0 = io_out_0_ready & (\|_GEN); // @[Decoupled.scala:51:35] wire [8:0] _GEN_1 = chosen[8:0] \| chosen[9:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [7:0] _GEN_2 = _GEN_1[7:0] \| chosen[9:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [6:0] _GEN_3 = _GEN_2[6:0] \| chosen[9:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_4 = _GEN_3[5:0] \| chosen[9:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_5 = _GEN_4[4:0] \| chosen[9:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_6 = _GEN_5[3:0] \| chosen[9:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_7 = _GEN_6[2:0] \| chosen[9:7]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_8 = _GEN_7[1:0] \| chosen[9:8]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 10'h0; // @[SwitchAllocator.scala:24:38] mask <= 10'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_9_bits_tail, ~io_in_8_bits_tail, 2'h3, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, ~io_in_1_bits_tail, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[9], _GEN_1[8], _GEN_2[7], _GEN_3[6], _GEN_4[5], _GEN_5[4], _GEN_6[3], _GEN_7[2], _GEN_8[1], _GEN_8[0] \| chosen[9]} : (&mask) ? 10'h0 : {mask[8:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_49 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_49( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_47 : input clock : Clock input reset : Reset output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1]}, credit_alloc : { `6` : { alloc : UInt<1>, tail : UInt<1>}[1], `5` : { alloc : UInt<1>, tail : UInt<1>}[1], `4` : { alloc : UInt<1>, tail : UInt<1>}[1], `3` : { alloc : UInt<1>, tail : UInt<1>}[1], `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[10]}, switch_sel : { `6` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `5` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `4` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `3` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_272 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_273 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_274 connect arbs_2.clock, clock connect arbs_2.reset, reset inst arbs_3 of SwitchArbiter_275 connect arbs_3.clock, clock connect arbs_3.reset, reset inst arbs_4 of SwitchArbiter_276 connect arbs_4.clock, clock connect arbs_4.reset, reset inst arbs_5 of SwitchArbiter_277 connect arbs_5.clock, clock connect arbs_5.reset, reset inst arbs_6 of SwitchArbiter_278 connect arbs_6.clock, clock connect arbs_6.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) connect arbs_3.io.out[0].ready, UInt<1>(0h1) connect arbs_4.io.out[0].ready, UInt<1>(0h1) connect arbs_5.io.out[0].ready, UInt<1>(0h1) connect arbs_6.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[7] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_0_valid_T_4 = or(_arbs_0_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_0_valid_T_5 = or(_arbs_0_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_0_valid_T_6 = or(_arbs_0_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_0_valid_T_7 = or(_arbs_0_io_in_0_valid_T_6, io.req.`0`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_0_valid_T_8 = or(_arbs_0_io_in_0_valid_T_7, io.req.`0`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_0_valid_T_9 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_8) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_9 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _arbs_3_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[0].valid, _arbs_3_io_in_0_valid_T connect arbs_3.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_3.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_3_T = and(arbs_3.io.in[0].ready, arbs_3.io.in[0].valid) connect fires[3], _fires_3_T node _arbs_4_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[0].valid, _arbs_4_io_in_0_valid_T connect arbs_4.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_4.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_4_T = and(arbs_4.io.in[0].ready, arbs_4.io.in[0].valid) connect fires[4], _fires_4_T node _arbs_5_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[0].valid, _arbs_5_io_in_0_valid_T connect arbs_5.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_5.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_5_T = and(arbs_5.io.in[0].ready, arbs_5.io.in[0].valid) connect fires[5], _fires_5_T node _arbs_6_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[0].valid, _arbs_6_io_in_0_valid_T connect arbs_6.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_6.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[0].bits.vc_sel.`4`[0], io.req.`0`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[0].bits.vc_sel.`5`[0], io.req.`0`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[0].bits.vc_sel.`6`[0], io.req.`0`[0].bits.vc_sel.`6`[0] node _fires_6_T = and(arbs_6.io.in[0].ready, arbs_6.io.in[0].valid) connect fires[6], _fires_6_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) node _io_req_0_0_ready_T_2 = or(_io_req_0_0_ready_T_1, fires[3]) node _io_req_0_0_ready_T_3 = or(_io_req_0_0_ready_T_2, fires[4]) node _io_req_0_0_ready_T_4 = or(_io_req_0_0_ready_T_3, fires[5]) node _io_req_0_0_ready_T_5 = or(_io_req_0_0_ready_T_4, fires[6]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_5 wire fires_1 : UInt<1>[7] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_1_valid_T_4 = or(_arbs_0_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_1_valid_T_5 = or(_arbs_0_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_1_valid_T_6 = or(_arbs_0_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_1_valid_T_7 = or(_arbs_0_io_in_1_valid_T_6, io.req.`1`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_1_valid_T_8 = or(_arbs_0_io_in_1_valid_T_7, io.req.`1`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_1_valid_T_9 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_8) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_9 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _arbs_3_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[1].valid, _arbs_3_io_in_1_valid_T connect arbs_3.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_3.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_3_T_1 = and(arbs_3.io.in[1].ready, arbs_3.io.in[1].valid) connect fires_1[3], _fires_3_T_1 node _arbs_4_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[1].valid, _arbs_4_io_in_1_valid_T connect arbs_4.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_4.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_4_T_1 = and(arbs_4.io.in[1].ready, arbs_4.io.in[1].valid) connect fires_1[4], _fires_4_T_1 node _arbs_5_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[1].valid, _arbs_5_io_in_1_valid_T connect arbs_5.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_5.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_5_T_1 = and(arbs_5.io.in[1].ready, arbs_5.io.in[1].valid) connect fires_1[5], _fires_5_T_1 node _arbs_6_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[1].valid, _arbs_6_io_in_1_valid_T connect arbs_6.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_6.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[1].bits.vc_sel.`4`[0], io.req.`1`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[1].bits.vc_sel.`5`[0], io.req.`1`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[1].bits.vc_sel.`6`[0], io.req.`1`[0].bits.vc_sel.`6`[0] node _fires_6_T_1 = and(arbs_6.io.in[1].ready, arbs_6.io.in[1].valid) connect fires_1[6], _fires_6_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) node _io_req_1_0_ready_T_2 = or(_io_req_1_0_ready_T_1, fires_1[3]) node _io_req_1_0_ready_T_3 = or(_io_req_1_0_ready_T_2, fires_1[4]) node _io_req_1_0_ready_T_4 = or(_io_req_1_0_ready_T_3, fires_1[5]) node _io_req_1_0_ready_T_5 = or(_io_req_1_0_ready_T_4, fires_1[6]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_5 wire fires_2 : UInt<1>[7] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_2_valid_T_4 = or(_arbs_0_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_2_valid_T_5 = or(_arbs_0_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_2_valid_T_6 = or(_arbs_0_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_2_valid_T_7 = or(_arbs_0_io_in_2_valid_T_6, io.req.`2`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_2_valid_T_8 = or(_arbs_0_io_in_2_valid_T_7, io.req.`2`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_2_valid_T_9 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_8) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_9 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _arbs_3_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[2].valid, _arbs_3_io_in_2_valid_T connect arbs_3.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_3.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_3_T_2 = and(arbs_3.io.in[2].ready, arbs_3.io.in[2].valid) connect fires_2[3], _fires_3_T_2 node _arbs_4_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[2].valid, _arbs_4_io_in_2_valid_T connect arbs_4.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_4.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_4_T_2 = and(arbs_4.io.in[2].ready, arbs_4.io.in[2].valid) connect fires_2[4], _fires_4_T_2 node _arbs_5_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[2].valid, _arbs_5_io_in_2_valid_T connect arbs_5.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_5.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_5_T_2 = and(arbs_5.io.in[2].ready, arbs_5.io.in[2].valid) connect fires_2[5], _fires_5_T_2 node _arbs_6_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[2].valid, _arbs_6_io_in_2_valid_T connect arbs_6.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_6.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[2].bits.vc_sel.`4`[0], io.req.`2`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[2].bits.vc_sel.`5`[0], io.req.`2`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[2].bits.vc_sel.`6`[0], io.req.`2`[0].bits.vc_sel.`6`[0] node _fires_6_T_2 = and(arbs_6.io.in[2].ready, arbs_6.io.in[2].valid) connect fires_2[6], _fires_6_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) node _io_req_2_0_ready_T_2 = or(_io_req_2_0_ready_T_1, fires_2[3]) node _io_req_2_0_ready_T_3 = or(_io_req_2_0_ready_T_2, fires_2[4]) node _io_req_2_0_ready_T_4 = or(_io_req_2_0_ready_T_3, fires_2[5]) node _io_req_2_0_ready_T_5 = or(_io_req_2_0_ready_T_4, fires_2[6]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_5 wire fires_3 : UInt<1>[7] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_3_valid_T_2 = or(_arbs_0_io_in_3_valid_T_1, io.req.`3`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_3_valid_T_3 = or(_arbs_0_io_in_3_valid_T_2, io.req.`3`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_3_valid_T_4 = or(_arbs_0_io_in_3_valid_T_3, io.req.`3`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_3_valid_T_5 = or(_arbs_0_io_in_3_valid_T_4, io.req.`3`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_3_valid_T_6 = or(_arbs_0_io_in_3_valid_T_5, io.req.`3`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_3_valid_T_7 = or(_arbs_0_io_in_3_valid_T_6, io.req.`3`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_3_valid_T_8 = or(_arbs_0_io_in_3_valid_T_7, io.req.`3`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_3_valid_T_9 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_8) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_9 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _arbs_3_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[3].valid, _arbs_3_io_in_3_valid_T connect arbs_3.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_3.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_3_T_3 = and(arbs_3.io.in[3].ready, arbs_3.io.in[3].valid) connect fires_3[3], _fires_3_T_3 node _arbs_4_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[3].valid, _arbs_4_io_in_3_valid_T connect arbs_4.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_4.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_4_T_3 = and(arbs_4.io.in[3].ready, arbs_4.io.in[3].valid) connect fires_3[4], _fires_4_T_3 node _arbs_5_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[3].valid, _arbs_5_io_in_3_valid_T connect arbs_5.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_5.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_5_T_3 = and(arbs_5.io.in[3].ready, arbs_5.io.in[3].valid) connect fires_3[5], _fires_5_T_3 node _arbs_6_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[3].valid, _arbs_6_io_in_3_valid_T connect arbs_6.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_6.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[3].bits.vc_sel.`4`[0], io.req.`3`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[3].bits.vc_sel.`5`[0], io.req.`3`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[3].bits.vc_sel.`6`[0], io.req.`3`[0].bits.vc_sel.`6`[0] node _fires_6_T_3 = and(arbs_6.io.in[3].ready, arbs_6.io.in[3].valid) connect fires_3[6], _fires_6_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) node _io_req_3_0_ready_T_2 = or(_io_req_3_0_ready_T_1, fires_3[3]) node _io_req_3_0_ready_T_3 = or(_io_req_3_0_ready_T_2, fires_3[4]) node _io_req_3_0_ready_T_4 = or(_io_req_3_0_ready_T_3, fires_3[5]) node _io_req_3_0_ready_T_5 = or(_io_req_3_0_ready_T_4, fires_3[6]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_5 wire fires_4 : UInt<1>[7] node _arbs_0_io_in_4_valid_T = or(io.req.`4`[0].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_4_valid_T_1 = or(_arbs_0_io_in_4_valid_T, io.req.`4`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_4_valid_T_2 = or(_arbs_0_io_in_4_valid_T_1, io.req.`4`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_4_valid_T_3 = or(_arbs_0_io_in_4_valid_T_2, io.req.`4`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_4_valid_T_4 = or(_arbs_0_io_in_4_valid_T_3, io.req.`4`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_4_valid_T_5 = or(_arbs_0_io_in_4_valid_T_4, io.req.`4`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_4_valid_T_6 = or(_arbs_0_io_in_4_valid_T_5, io.req.`4`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_4_valid_T_7 = or(_arbs_0_io_in_4_valid_T_6, io.req.`4`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_4_valid_T_8 = or(_arbs_0_io_in_4_valid_T_7, io.req.`4`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_4_valid_T_9 = and(io.req.`4`[0].valid, _arbs_0_io_in_4_valid_T_8) connect arbs_0.io.in[4].valid, _arbs_0_io_in_4_valid_T_9 connect arbs_0.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_0.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_0.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_0.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_0.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_0_T_4 = and(arbs_0.io.in[4].ready, arbs_0.io.in[4].valid) connect fires_4[0], _fires_0_T_4 node _arbs_1_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[4].valid, _arbs_1_io_in_4_valid_T connect arbs_1.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_1.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_1.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_1.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_1.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_1_T_4 = and(arbs_1.io.in[4].ready, arbs_1.io.in[4].valid) connect fires_4[1], _fires_1_T_4 node _arbs_2_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[4].valid, _arbs_2_io_in_4_valid_T connect arbs_2.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_2.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_2.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_2.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_2.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_2_T_4 = and(arbs_2.io.in[4].ready, arbs_2.io.in[4].valid) connect fires_4[2], _fires_2_T_4 node _arbs_3_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[4].valid, _arbs_3_io_in_4_valid_T connect arbs_3.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_3.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_3.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_3.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_3.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_3.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_3.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_3.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_3.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_3.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_3.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_3.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_3.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_3_T_4 = and(arbs_3.io.in[4].ready, arbs_3.io.in[4].valid) connect fires_4[3], _fires_3_T_4 node _arbs_4_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`4`[0]) connect arbs_4.io.in[4].valid, _arbs_4_io_in_4_valid_T connect arbs_4.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_4.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_4.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_4.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_4.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_4.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_4.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_4.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_4.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_4.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_4.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_4.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_4.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_4.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_4.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_4.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_4.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_4_T_4 = and(arbs_4.io.in[4].ready, arbs_4.io.in[4].valid) connect fires_4[4], _fires_4_T_4 node _arbs_5_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`5`[0]) connect arbs_5.io.in[4].valid, _arbs_5_io_in_4_valid_T connect arbs_5.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_5.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_5.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_5.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_5.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_5.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_5.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_5.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_5.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_5.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_5.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_5.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_5.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_5.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_5.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_5.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_5.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_5_T_4 = and(arbs_5.io.in[4].ready, arbs_5.io.in[4].valid) connect fires_4[5], _fires_5_T_4 node _arbs_6_io_in_4_valid_T = and(io.req.`4`[0].valid, io.req.`4`[0].bits.vc_sel.`6`[0]) connect arbs_6.io.in[4].valid, _arbs_6_io_in_4_valid_T connect arbs_6.io.in[4].bits.tail, io.req.`4`[0].bits.tail connect arbs_6.io.in[4].bits.vc_sel.`0`[0], io.req.`4`[0].bits.vc_sel.`0`[0] connect arbs_6.io.in[4].bits.vc_sel.`0`[1], io.req.`4`[0].bits.vc_sel.`0`[1] connect arbs_6.io.in[4].bits.vc_sel.`0`[2], io.req.`4`[0].bits.vc_sel.`0`[2] connect arbs_6.io.in[4].bits.vc_sel.`0`[3], io.req.`4`[0].bits.vc_sel.`0`[3] connect arbs_6.io.in[4].bits.vc_sel.`0`[4], io.req.`4`[0].bits.vc_sel.`0`[4] connect arbs_6.io.in[4].bits.vc_sel.`0`[5], io.req.`4`[0].bits.vc_sel.`0`[5] connect arbs_6.io.in[4].bits.vc_sel.`0`[6], io.req.`4`[0].bits.vc_sel.`0`[6] connect arbs_6.io.in[4].bits.vc_sel.`0`[7], io.req.`4`[0].bits.vc_sel.`0`[7] connect arbs_6.io.in[4].bits.vc_sel.`0`[8], io.req.`4`[0].bits.vc_sel.`0`[8] connect arbs_6.io.in[4].bits.vc_sel.`0`[9], io.req.`4`[0].bits.vc_sel.`0`[9] connect arbs_6.io.in[4].bits.vc_sel.`1`[0], io.req.`4`[0].bits.vc_sel.`1`[0] connect arbs_6.io.in[4].bits.vc_sel.`2`[0], io.req.`4`[0].bits.vc_sel.`2`[0] connect arbs_6.io.in[4].bits.vc_sel.`3`[0], io.req.`4`[0].bits.vc_sel.`3`[0] connect arbs_6.io.in[4].bits.vc_sel.`4`[0], io.req.`4`[0].bits.vc_sel.`4`[0] connect arbs_6.io.in[4].bits.vc_sel.`5`[0], io.req.`4`[0].bits.vc_sel.`5`[0] connect arbs_6.io.in[4].bits.vc_sel.`6`[0], io.req.`4`[0].bits.vc_sel.`6`[0] node _fires_6_T_4 = and(arbs_6.io.in[4].ready, arbs_6.io.in[4].valid) connect fires_4[6], _fires_6_T_4 node _io_req_4_0_ready_T = or(fires_4[0], fires_4[1]) node _io_req_4_0_ready_T_1 = or(_io_req_4_0_ready_T, fires_4[2]) node _io_req_4_0_ready_T_2 = or(_io_req_4_0_ready_T_1, fires_4[3]) node _io_req_4_0_ready_T_3 = or(_io_req_4_0_ready_T_2, fires_4[4]) node _io_req_4_0_ready_T_4 = or(_io_req_4_0_ready_T_3, fires_4[5]) node _io_req_4_0_ready_T_5 = or(_io_req_4_0_ready_T_4, fires_4[6]) connect io.req.`4`[0].ready, _io_req_4_0_ready_T_5 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_0_0_4_0_T = bits(arbs_0.io.chosen_oh[0], 4, 4) node _io_switch_sel_0_0_4_0_T_1 = and(arbs_0.io.in[4].valid, _io_switch_sel_0_0_4_0_T) node _io_switch_sel_0_0_4_0_T_2 = and(_io_switch_sel_0_0_4_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`4`[0], _io_switch_sel_0_0_4_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_1_0_4_0_T = bits(arbs_1.io.chosen_oh[0], 4, 4) node _io_switch_sel_1_0_4_0_T_1 = and(arbs_1.io.in[4].valid, _io_switch_sel_1_0_4_0_T) node _io_switch_sel_1_0_4_0_T_2 = and(_io_switch_sel_1_0_4_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`4`[0], _io_switch_sel_1_0_4_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 node _io_switch_sel_2_0_4_0_T = bits(arbs_2.io.chosen_oh[0], 4, 4) node _io_switch_sel_2_0_4_0_T_1 = and(arbs_2.io.in[4].valid, _io_switch_sel_2_0_4_0_T) node _io_switch_sel_2_0_4_0_T_2 = and(_io_switch_sel_2_0_4_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`4`[0], _io_switch_sel_2_0_4_0_T_2 node _io_switch_sel_3_0_0_0_T = bits(arbs_3.io.chosen_oh[0], 0, 0) node _io_switch_sel_3_0_0_0_T_1 = and(arbs_3.io.in[0].valid, _io_switch_sel_3_0_0_0_T) node _io_switch_sel_3_0_0_0_T_2 = and(_io_switch_sel_3_0_0_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`0`[0], _io_switch_sel_3_0_0_0_T_2 node _io_switch_sel_3_0_1_0_T = bits(arbs_3.io.chosen_oh[0], 1, 1) node _io_switch_sel_3_0_1_0_T_1 = and(arbs_3.io.in[1].valid, _io_switch_sel_3_0_1_0_T) node _io_switch_sel_3_0_1_0_T_2 = and(_io_switch_sel_3_0_1_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`1`[0], _io_switch_sel_3_0_1_0_T_2 node _io_switch_sel_3_0_2_0_T = bits(arbs_3.io.chosen_oh[0], 2, 2) node _io_switch_sel_3_0_2_0_T_1 = and(arbs_3.io.in[2].valid, _io_switch_sel_3_0_2_0_T) node _io_switch_sel_3_0_2_0_T_2 = and(_io_switch_sel_3_0_2_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`2`[0], _io_switch_sel_3_0_2_0_T_2 node _io_switch_sel_3_0_3_0_T = bits(arbs_3.io.chosen_oh[0], 3, 3) node _io_switch_sel_3_0_3_0_T_1 = and(arbs_3.io.in[3].valid, _io_switch_sel_3_0_3_0_T) node _io_switch_sel_3_0_3_0_T_2 = and(_io_switch_sel_3_0_3_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`3`[0], _io_switch_sel_3_0_3_0_T_2 node _io_switch_sel_3_0_4_0_T = bits(arbs_3.io.chosen_oh[0], 4, 4) node _io_switch_sel_3_0_4_0_T_1 = and(arbs_3.io.in[4].valid, _io_switch_sel_3_0_4_0_T) node _io_switch_sel_3_0_4_0_T_2 = and(_io_switch_sel_3_0_4_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`4`[0], _io_switch_sel_3_0_4_0_T_2 node _io_switch_sel_4_0_0_0_T = bits(arbs_4.io.chosen_oh[0], 0, 0) node _io_switch_sel_4_0_0_0_T_1 = and(arbs_4.io.in[0].valid, _io_switch_sel_4_0_0_0_T) node _io_switch_sel_4_0_0_0_T_2 = and(_io_switch_sel_4_0_0_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`0`[0], _io_switch_sel_4_0_0_0_T_2 node _io_switch_sel_4_0_1_0_T = bits(arbs_4.io.chosen_oh[0], 1, 1) node _io_switch_sel_4_0_1_0_T_1 = and(arbs_4.io.in[1].valid, _io_switch_sel_4_0_1_0_T) node _io_switch_sel_4_0_1_0_T_2 = and(_io_switch_sel_4_0_1_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`1`[0], _io_switch_sel_4_0_1_0_T_2 node _io_switch_sel_4_0_2_0_T = bits(arbs_4.io.chosen_oh[0], 2, 2) node _io_switch_sel_4_0_2_0_T_1 = and(arbs_4.io.in[2].valid, _io_switch_sel_4_0_2_0_T) node _io_switch_sel_4_0_2_0_T_2 = and(_io_switch_sel_4_0_2_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`2`[0], _io_switch_sel_4_0_2_0_T_2 node _io_switch_sel_4_0_3_0_T = bits(arbs_4.io.chosen_oh[0], 3, 3) node _io_switch_sel_4_0_3_0_T_1 = and(arbs_4.io.in[3].valid, _io_switch_sel_4_0_3_0_T) node _io_switch_sel_4_0_3_0_T_2 = and(_io_switch_sel_4_0_3_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`3`[0], _io_switch_sel_4_0_3_0_T_2 node _io_switch_sel_4_0_4_0_T = bits(arbs_4.io.chosen_oh[0], 4, 4) node _io_switch_sel_4_0_4_0_T_1 = and(arbs_4.io.in[4].valid, _io_switch_sel_4_0_4_0_T) node _io_switch_sel_4_0_4_0_T_2 = and(_io_switch_sel_4_0_4_0_T_1, arbs_4.io.out[0].valid) connect io.switch_sel.`4`[0].`4`[0], _io_switch_sel_4_0_4_0_T_2 node _io_switch_sel_5_0_0_0_T = bits(arbs_5.io.chosen_oh[0], 0, 0) node _io_switch_sel_5_0_0_0_T_1 = and(arbs_5.io.in[0].valid, _io_switch_sel_5_0_0_0_T) node _io_switch_sel_5_0_0_0_T_2 = and(_io_switch_sel_5_0_0_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`0`[0], _io_switch_sel_5_0_0_0_T_2 node _io_switch_sel_5_0_1_0_T = bits(arbs_5.io.chosen_oh[0], 1, 1) node _io_switch_sel_5_0_1_0_T_1 = and(arbs_5.io.in[1].valid, _io_switch_sel_5_0_1_0_T) node _io_switch_sel_5_0_1_0_T_2 = and(_io_switch_sel_5_0_1_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`1`[0], _io_switch_sel_5_0_1_0_T_2 node _io_switch_sel_5_0_2_0_T = bits(arbs_5.io.chosen_oh[0], 2, 2) node _io_switch_sel_5_0_2_0_T_1 = and(arbs_5.io.in[2].valid, _io_switch_sel_5_0_2_0_T) node _io_switch_sel_5_0_2_0_T_2 = and(_io_switch_sel_5_0_2_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`2`[0], _io_switch_sel_5_0_2_0_T_2 node _io_switch_sel_5_0_3_0_T = bits(arbs_5.io.chosen_oh[0], 3, 3) node _io_switch_sel_5_0_3_0_T_1 = and(arbs_5.io.in[3].valid, _io_switch_sel_5_0_3_0_T) node _io_switch_sel_5_0_3_0_T_2 = and(_io_switch_sel_5_0_3_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`3`[0], _io_switch_sel_5_0_3_0_T_2 node _io_switch_sel_5_0_4_0_T = bits(arbs_5.io.chosen_oh[0], 4, 4) node _io_switch_sel_5_0_4_0_T_1 = and(arbs_5.io.in[4].valid, _io_switch_sel_5_0_4_0_T) node _io_switch_sel_5_0_4_0_T_2 = and(_io_switch_sel_5_0_4_0_T_1, arbs_5.io.out[0].valid) connect io.switch_sel.`5`[0].`4`[0], _io_switch_sel_5_0_4_0_T_2 node _io_switch_sel_6_0_0_0_T = bits(arbs_6.io.chosen_oh[0], 0, 0) node _io_switch_sel_6_0_0_0_T_1 = and(arbs_6.io.in[0].valid, _io_switch_sel_6_0_0_0_T) node _io_switch_sel_6_0_0_0_T_2 = and(_io_switch_sel_6_0_0_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`0`[0], _io_switch_sel_6_0_0_0_T_2 node _io_switch_sel_6_0_1_0_T = bits(arbs_6.io.chosen_oh[0], 1, 1) node _io_switch_sel_6_0_1_0_T_1 = and(arbs_6.io.in[1].valid, _io_switch_sel_6_0_1_0_T) node _io_switch_sel_6_0_1_0_T_2 = and(_io_switch_sel_6_0_1_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`1`[0], _io_switch_sel_6_0_1_0_T_2 node _io_switch_sel_6_0_2_0_T = bits(arbs_6.io.chosen_oh[0], 2, 2) node _io_switch_sel_6_0_2_0_T_1 = and(arbs_6.io.in[2].valid, _io_switch_sel_6_0_2_0_T) node _io_switch_sel_6_0_2_0_T_2 = and(_io_switch_sel_6_0_2_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`2`[0], _io_switch_sel_6_0_2_0_T_2 node _io_switch_sel_6_0_3_0_T = bits(arbs_6.io.chosen_oh[0], 3, 3) node _io_switch_sel_6_0_3_0_T_1 = and(arbs_6.io.in[3].valid, _io_switch_sel_6_0_3_0_T) node _io_switch_sel_6_0_3_0_T_2 = and(_io_switch_sel_6_0_3_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`3`[0], _io_switch_sel_6_0_3_0_T_2 node _io_switch_sel_6_0_4_0_T = bits(arbs_6.io.chosen_oh[0], 4, 4) node _io_switch_sel_6_0_4_0_T_1 = and(arbs_6.io.in[4].valid, _io_switch_sel_6_0_4_0_T) node _io_switch_sel_6_0_4_0_T_2 = and(_io_switch_sel_6_0_4_0_T_1, arbs_6.io.out[0].valid) connect io.switch_sel.`6`[0].`4`[0], _io_switch_sel_6_0_4_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`4`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`5`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`6`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[5].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[6].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[7].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[8].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[9].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`3`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`4`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`5`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`6`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3]) when _T_3 : connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4]) when _T_4 : connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail node _T_5 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[5]) when _T_5 : connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[5].tail, arbs_0.io.out[0].bits.tail node _T_6 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[6]) when _T_6 : connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[6].tail, arbs_0.io.out[0].bits.tail node _T_7 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[7]) when _T_7 : connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[7].tail, arbs_0.io.out[0].bits.tail node _T_8 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[8]) when _T_8 : connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[8].tail, arbs_0.io.out[0].bits.tail node _T_9 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[9]) when _T_9 : connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[9].tail, arbs_0.io.out[0].bits.tail node _T_10 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_10 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_11 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_11 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail node _T_12 = and(arbs_3.io.out[0].valid, arbs_3.io.out[0].bits.vc_sel.`3`[0]) when _T_12 : connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`3`[0].tail, arbs_3.io.out[0].bits.tail node _T_13 = and(arbs_4.io.out[0].valid, arbs_4.io.out[0].bits.vc_sel.`4`[0]) when _T_13 : connect io.credit_alloc.`4`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`4`[0].tail, arbs_4.io.out[0].bits.tail node _T_14 = and(arbs_5.io.out[0].valid, arbs_5.io.out[0].bits.vc_sel.`5`[0]) when _T_14 : connect io.credit_alloc.`5`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`5`[0].tail, arbs_5.io.out[0].bits.tail node _T_15 = and(arbs_6.io.out[0].valid, arbs_6.io.out[0].bits.vc_sel.`6`[0]) when _T_15 : connect io.credit_alloc.`6`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`6`[0].tail, arbs_6.io.out[0].bits.tail

module SwitchAllocator_47( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_4_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_4_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14] input io_req_4_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_6_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_6_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_6_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_5_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_5_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_4_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_4_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_6_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_7_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_8_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_9_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_6_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_5_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_4_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_4_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_6_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:83:45] wire _arbs_6_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_6_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:83:45] wire _arbs_5_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_5_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:83:45] wire _arbs_4_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_4_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_4_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:83:45] wire [4:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2 | io_req_2_0_bits_vc_sel_0_3 | io_req_2_0_bits_vc_sel_0_4 | io_req_2_0_bits_vc_sel_0_5 | io_req_2_0_bits_vc_sel_0_6 | io_req_2_0_bits_vc_sel_0_7 | io_req_2_0_bits_vc_sel_0_8 | io_req_2_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_4_valid = io_req_4_0_valid & (io_req_4_0_bits_vc_sel_0_0 | io_req_4_0_bits_vc_sel_0_1 | io_req_4_0_bits_vc_sel_0_2 | io_req_4_0_bits_vc_sel_0_3 | io_req_4_0_bits_vc_sel_0_4 | io_req_4_0_bits_vc_sel_0_5 | io_req_4_0_bits_vc_sel_0_6 | io_req_4_0_bits_vc_sel_0_7 | io_req_4_0_bits_vc_sel_0_8 | io_req_4_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_4_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:95:37] wire arbs_5_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:95:37] wire arbs_6_io_in_4_valid = io_req_4_0_valid & io_req_4_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_4_0_alloc_0 = _arbs_4_io_out_0_valid & _arbs_4_io_out_0_bits_vc_sel_4_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_5_0_alloc_0 = _arbs_5_io_out_0_valid & _arbs_5_io_out_0_bits_vc_sel_5_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_6_0_alloc_0 = _arbs_6_io_out_0_valid & _arbs_6_io_out_0_bits_vc_sel_6_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_272 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused */), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_0_io_in_4_ready), .io_in_4_valid (arbs_0_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2), .io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5), .io_out_0_bits_vc_sel_0_6 (_arbs_0_io_out_0_bits_vc_sel_0_6), .io_out_0_bits_vc_sel_0_7 (_arbs_0_io_out_0_bits_vc_sel_0_7), .io_out_0_bits_vc_sel_0_8 (_arbs_0_io_out_0_bits_vc_sel_0_8), .io_out_0_bits_vc_sel_0_9 (_arbs_0_io_out_0_bits_vc_sel_0_9), .io_out_0_bits_tail (/* unused */), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_1_io_in_4_ready), .io_in_4_valid (arbs_1_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_2_io_in_4_ready), .io_in_4_valid (arbs_2_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_3 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (arbs_3_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_3_io_in_4_ready), .io_in_4_valid (arbs_3_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_3_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_3_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_4 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_4_io_in_0_ready), .io_in_0_valid (arbs_4_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_4_io_in_2_ready), .io_in_2_valid (arbs_4_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_4_io_in_4_ready), .io_in_4_valid (arbs_4_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_4_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (_arbs_4_io_out_0_bits_vc_sel_4_0), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_4_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_4_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_5 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_5_io_in_0_ready), .io_in_0_valid (arbs_5_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_5_io_in_2_ready), .io_in_2_valid (arbs_5_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_5_io_in_4_ready), .io_in_4_valid (arbs_5_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_5_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (/* unused */), .io_out_0_bits_vc_sel_5_0 (_arbs_5_io_out_0_bits_vc_sel_5_0), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_5_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_5_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_272 arbs_6 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_6_io_in_0_ready), .io_in_0_valid (arbs_6_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_6_0 (io_req_0_0_bits_vc_sel_6_0), .io_in_0_bits_vc_sel_5_0 (io_req_0_0_bits_vc_sel_5_0), .io_in_0_bits_vc_sel_4_0 (io_req_0_0_bits_vc_sel_4_0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_6_io_in_2_ready), .io_in_2_valid (arbs_6_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_6_0 (io_req_2_0_bits_vc_sel_6_0), .io_in_2_bits_vc_sel_5_0 (io_req_2_0_bits_vc_sel_5_0), .io_in_2_bits_vc_sel_4_0 (io_req_2_0_bits_vc_sel_4_0), .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2), .io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3), .io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4), .io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5), .io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6), .io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7), .io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8), .io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_in_4_ready (_arbs_6_io_in_4_ready), .io_in_4_valid (arbs_6_io_in_4_valid), // @[SwitchAllocator.scala:95:37] .io_in_4_bits_vc_sel_6_0 (io_req_4_0_bits_vc_sel_6_0), .io_in_4_bits_vc_sel_5_0 (io_req_4_0_bits_vc_sel_5_0), .io_in_4_bits_vc_sel_4_0 (io_req_4_0_bits_vc_sel_4_0), .io_in_4_bits_vc_sel_3_0 (io_req_4_0_bits_vc_sel_3_0), .io_in_4_bits_vc_sel_2_0 (io_req_4_0_bits_vc_sel_2_0), .io_in_4_bits_vc_sel_1_0 (io_req_4_0_bits_vc_sel_1_0), .io_in_4_bits_vc_sel_0_2 (io_req_4_0_bits_vc_sel_0_2), .io_in_4_bits_vc_sel_0_3 (io_req_4_0_bits_vc_sel_0_3), .io_in_4_bits_vc_sel_0_4 (io_req_4_0_bits_vc_sel_0_4), .io_in_4_bits_vc_sel_0_5 (io_req_4_0_bits_vc_sel_0_5), .io_in_4_bits_vc_sel_0_6 (io_req_4_0_bits_vc_sel_0_6), .io_in_4_bits_vc_sel_0_7 (io_req_4_0_bits_vc_sel_0_7), .io_in_4_bits_vc_sel_0_8 (io_req_4_0_bits_vc_sel_0_8), .io_in_4_bits_vc_sel_0_9 (io_req_4_0_bits_vc_sel_0_9), .io_in_4_bits_tail (io_req_4_0_bits_tail), .io_out_0_valid (_arbs_6_io_out_0_valid), .io_out_0_bits_vc_sel_6_0 (_arbs_6_io_out_0_bits_vc_sel_6_0), .io_out_0_bits_vc_sel_5_0 (/* unused */), .io_out_0_bits_vc_sel_4_0 (/* unused */), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_vc_sel_0_6 (/* unused */), .io_out_0_bits_vc_sel_0_7 (/* unused */), .io_out_0_bits_vc_sel_0_8 (/* unused */), .io_out_0_bits_vc_sel_0_9 (/* unused */), .io_out_0_bits_tail (_arbs_6_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_6_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_4_0_ready = _arbs_0_io_in_4_ready & arbs_0_io_in_4_valid | _arbs_1_io_in_4_ready & arbs_1_io_in_4_valid | _arbs_2_io_in_4_ready & arbs_2_io_in_4_valid | _arbs_3_io_in_4_ready & arbs_3_io_in_4_valid | _arbs_4_io_in_4_ready & arbs_4_io_in_4_valid | _arbs_5_io_in_4_ready & arbs_5_io_in_4_valid | _arbs_6_io_in_4_ready & arbs_6_io_in_4_valid; // @[Decoupled.scala:51:35] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid | _arbs_3_io_in_2_ready & arbs_3_io_in_2_valid | _arbs_4_io_in_2_ready & arbs_4_io_in_2_valid | _arbs_5_io_in_2_ready & arbs_5_io_in_2_valid | _arbs_6_io_in_2_ready & arbs_6_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid | _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid | _arbs_4_io_in_0_ready & arbs_4_io_in_0_valid | _arbs_5_io_in_0_ready & arbs_5_io_in_0_valid | _arbs_6_io_in_0_ready & arbs_6_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_6_0_alloc = io_credit_alloc_6_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_6_0_tail = io_credit_alloc_6_0_alloc_0 & _arbs_6_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_5_0_alloc = io_credit_alloc_5_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_5_0_tail = io_credit_alloc_5_0_alloc_0 & _arbs_5_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_4_0_alloc = io_credit_alloc_4_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_4_0_tail = io_credit_alloc_4_0_alloc_0 & _arbs_4_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_6_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_7_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_8_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_9_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_6_0_4_0 = arbs_6_io_in_4_valid & _arbs_6_io_chosen_oh_0[4] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_6_0_2_0 = arbs_6_io_in_2_valid & _arbs_6_io_chosen_oh_0[2] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_6_0_0_0 = arbs_6_io_in_0_valid & _arbs_6_io_chosen_oh_0[0] & _arbs_6_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_4_0 = arbs_5_io_in_4_valid & _arbs_5_io_chosen_oh_0[4] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_2_0 = arbs_5_io_in_2_valid & _arbs_5_io_chosen_oh_0[2] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_5_0_0_0 = arbs_5_io_in_0_valid & _arbs_5_io_chosen_oh_0[0] & _arbs_5_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_4_0 = arbs_4_io_in_4_valid & _arbs_4_io_chosen_oh_0[4] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_2_0 = arbs_4_io_in_2_valid & _arbs_4_io_chosen_oh_0[2] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_4_0_0_0 = arbs_4_io_in_0_valid & _arbs_4_io_chosen_oh_0[0] & _arbs_4_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_4_0 = arbs_3_io_in_4_valid & _arbs_3_io_chosen_oh_0[4] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_2_0 = arbs_3_io_in_2_valid & _arbs_3_io_chosen_oh_0[2] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_4_0 = arbs_2_io_in_4_valid & _arbs_2_io_chosen_oh_0[4] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_4_0 = arbs_1_io_in_4_valid & _arbs_1_io_chosen_oh_0[4] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_4_0 = arbs_0_io_in_4_valid & _arbs_0_io_chosen_oh_0[4] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<12>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<12>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<12>, source : UInt<5>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<12>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 3, 0) node _req_clientBit_T = shr(request.source, 4) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<1>(0h1)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<4>(0h8)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<4>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 3, 0) node _req_clientBit_T_6 = shr(request.source, 4) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<1>(0h0)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<4>(0h8)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<12>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,false,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,false,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(_T_110, UInt<1>(0h0)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_111, UInt<1>(0h1), "") : assert_14 node _T_115 = eq(before, UInt<4>(0h8)) node _T_116 = eq(after, UInt<3>(0h5)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_118, UInt<1>(0h1), "") : assert_15 node _T_122 = eq(before, UInt<4>(0h8)) node _T_123 = eq(after, UInt<3>(0h4)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_125, UInt<1>(0h1), "") : assert_16 node _T_129 = eq(before, UInt<4>(0h8)) node _T_130 = eq(after, UInt<3>(0h6)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(_T_131, UInt<1>(0h0)) node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_T_132, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_132, UInt<1>(0h1), "") : assert_17 node _T_136 = eq(before, UInt<4>(0h8)) node _T_137 = eq(after, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(before, UInt<4>(0h8)) node _T_140 = eq(after, UInt<2>(0h2)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(_T_141, UInt<1>(0h0)) node _T_143 = asUInt(reset) node _T_144 = eq(_T_143, UInt<1>(0h0)) when _T_144 : node _T_145 = eq(_T_142, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_142, UInt<1>(0h1), "") : assert_18 node _T_146 = eq(before, UInt<1>(0h1)) node _T_147 = eq(after, UInt<4>(0h8)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_149, UInt<1>(0h1), "") : assert_19 node _T_153 = eq(before, UInt<1>(0h1)) node _T_154 = eq(after, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_156, UInt<1>(0h1), "") : assert_20 node _T_160 = eq(before, UInt<1>(0h1)) node _T_161 = eq(after, UInt<3>(0h7)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_163, UInt<1>(0h1), "") : assert_21 node _T_167 = eq(before, UInt<1>(0h1)) node _T_168 = eq(after, UInt<3>(0h5)) node _T_169 = and(_T_167, _T_168) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_170, UInt<1>(0h1), "") : assert_22 node _T_174 = eq(before, UInt<1>(0h1)) node _T_175 = eq(after, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_177, UInt<1>(0h1), "") : assert_23 node _T_181 = eq(before, UInt<1>(0h1)) node _T_182 = eq(after, UInt<3>(0h6)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(_T_184, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_184, UInt<1>(0h1), "") : assert_24 node _T_188 = eq(before, UInt<1>(0h1)) node _T_189 = eq(after, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(_T_190, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(before, UInt<1>(0h1)) node _T_196 = eq(after, UInt<2>(0h2)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(_T_198, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_198, UInt<1>(0h1), "") : assert_26 node _T_202 = eq(before, UInt<1>(0h0)) node _T_203 = eq(after, UInt<4>(0h8)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(_T_205, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_205, UInt<1>(0h1), "") : assert_27 node _T_209 = eq(before, UInt<1>(0h0)) node _T_210 = eq(after, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(_T_212, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_212, UInt<1>(0h1), "") : assert_28 node _T_216 = eq(before, UInt<1>(0h0)) node _T_217 = eq(after, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(_T_218, UInt<1>(0h0)) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_219, UInt<1>(0h1), "") : assert_29 node _T_223 = eq(before, UInt<1>(0h0)) node _T_224 = eq(after, UInt<3>(0h5)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(_T_226, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_226, UInt<1>(0h1), "") : assert_30 node _T_230 = eq(before, UInt<1>(0h0)) node _T_231 = eq(after, UInt<3>(0h6)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_233, UInt<1>(0h1), "") : assert_31 node _T_237 = eq(before, UInt<1>(0h0)) node _T_238 = eq(after, UInt<3>(0h4)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(_T_239, UInt<1>(0h0)) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_240, UInt<1>(0h1), "") : assert_32 node _T_244 = eq(before, UInt<1>(0h0)) node _T_245 = eq(after, UInt<2>(0h3)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(_T_246, UInt<1>(0h0)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_247, UInt<1>(0h1), "") : assert_33 node _T_251 = eq(before, UInt<1>(0h0)) node _T_252 = eq(after, UInt<2>(0h2)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_254, UInt<1>(0h1), "") : assert_34 node _T_258 = eq(before, UInt<3>(0h7)) node _T_259 = eq(after, UInt<4>(0h8)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_261, UInt<1>(0h1), "") : assert_35 node _T_265 = eq(before, UInt<3>(0h7)) node _T_266 = eq(after, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_268, UInt<1>(0h1), "") : assert_36 node _T_272 = eq(before, UInt<3>(0h7)) node _T_273 = eq(after, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_275, UInt<1>(0h1), "") : assert_37 node _T_279 = eq(before, UInt<3>(0h7)) node _T_280 = eq(after, UInt<3>(0h5)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = asUInt(reset) node _T_284 = eq(_T_283, UInt<1>(0h0)) when _T_284 : node _T_285 = eq(_T_282, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_282, UInt<1>(0h1), "") : assert_38 node _T_286 = eq(before, UInt<3>(0h7)) node _T_287 = eq(after, UInt<3>(0h6)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = asUInt(reset) node _T_291 = eq(_T_290, UInt<1>(0h0)) when _T_291 : node _T_292 = eq(_T_289, UInt<1>(0h0)) when _T_292 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_289, UInt<1>(0h1), "") : assert_39 node _T_293 = eq(before, UInt<3>(0h7)) node _T_294 = eq(after, UInt<3>(0h4)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(_T_295, UInt<1>(0h0)) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_296, UInt<1>(0h1), "") : assert_40 node _T_300 = eq(before, UInt<3>(0h7)) node _T_301 = eq(after, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(before, UInt<3>(0h7)) node _T_304 = eq(after, UInt<2>(0h2)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(_T_305, UInt<1>(0h0)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_306, UInt<1>(0h1), "") : assert_41 node _T_310 = eq(before, UInt<3>(0h5)) node _T_311 = eq(after, UInt<4>(0h8)) node _T_312 = and(_T_310, _T_311) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_313, UInt<1>(0h1), "") : assert_42 node _T_317 = eq(before, UInt<3>(0h5)) node _T_318 = eq(after, UInt<1>(0h1)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_T_320, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_320, UInt<1>(0h1), "") : assert_43 node _T_324 = eq(before, UInt<3>(0h5)) node _T_325 = eq(after, UInt<1>(0h0)) node _T_326 = and(_T_324, _T_325) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_327, UInt<1>(0h1), "") : assert_44 node _T_331 = eq(before, UInt<3>(0h5)) node _T_332 = eq(after, UInt<3>(0h7)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(before, UInt<3>(0h5)) node _T_335 = eq(after, UInt<3>(0h6)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_D should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_337, UInt<1>(0h1), "") : assert_45 node _T_341 = eq(before, UInt<3>(0h5)) node _T_342 = eq(after, UInt<3>(0h4)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(_T_343, UInt<1>(0h0)) node _T_345 = asUInt(reset) node _T_346 = eq(_T_345, UInt<1>(0h0)) when _T_346 : node _T_347 = eq(_T_344, UInt<1>(0h0)) when _T_347 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_344, UInt<1>(0h1), "") : assert_46 node _T_348 = eq(before, UInt<3>(0h5)) node _T_349 = eq(after, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(before, UInt<3>(0h5)) node _T_352 = eq(after, UInt<2>(0h2)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_354, UInt<1>(0h1), "") : assert_47 node _T_358 = eq(before, UInt<3>(0h6)) node _T_359 = eq(after, UInt<4>(0h8)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(_T_360, UInt<1>(0h0)) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_361, UInt<1>(0h1), "") : assert_48 node _T_365 = eq(before, UInt<3>(0h6)) node _T_366 = eq(after, UInt<1>(0h1)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(_T_367, UInt<1>(0h0)) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_368, UInt<1>(0h1), "") : assert_49 node _T_372 = eq(before, UInt<3>(0h6)) node _T_373 = eq(after, UInt<1>(0h0)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_375, UInt<1>(0h1), "") : assert_50 node _T_379 = eq(before, UInt<3>(0h6)) node _T_380 = eq(after, UInt<3>(0h7)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(_T_381, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_382, UInt<1>(0h1), "") : assert_51 node _T_386 = eq(before, UInt<3>(0h6)) node _T_387 = eq(after, UInt<3>(0h5)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(_T_388, UInt<1>(0h0)) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_389, UInt<1>(0h1), "") : assert_52 node _T_393 = eq(before, UInt<3>(0h6)) node _T_394 = eq(after, UInt<3>(0h4)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_396, UInt<1>(0h1), "") : assert_53 node _T_400 = eq(before, UInt<3>(0h6)) node _T_401 = eq(after, UInt<2>(0h3)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(_T_402, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_403, UInt<1>(0h1), "") : assert_54 node _T_407 = eq(before, UInt<3>(0h6)) node _T_408 = eq(after, UInt<2>(0h2)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(before, UInt<3>(0h4)) node _T_411 = eq(after, UInt<4>(0h8)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(_T_412, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_413, UInt<1>(0h1), "") : assert_55 node _T_417 = eq(before, UInt<3>(0h4)) node _T_418 = eq(after, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(_T_419, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_420, UInt<1>(0h1), "") : assert_56 node _T_424 = eq(before, UInt<3>(0h4)) node _T_425 = eq(after, UInt<1>(0h0)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_427, UInt<1>(0h1), "") : assert_57 node _T_431 = eq(before, UInt<3>(0h4)) node _T_432 = eq(after, UInt<3>(0h7)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_434, UInt<1>(0h1), "") : assert_58 node _T_438 = eq(before, UInt<3>(0h4)) node _T_439 = eq(after, UInt<3>(0h5)) node _T_440 = and(_T_438, _T_439) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_441, UInt<1>(0h1), "") : assert_59 node _T_445 = eq(before, UInt<3>(0h4)) node _T_446 = eq(after, UInt<3>(0h6)) node _T_447 = and(_T_445, _T_446) node _T_448 = eq(before, UInt<3>(0h4)) node _T_449 = eq(after, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(_T_450, UInt<1>(0h0)) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_451, UInt<1>(0h1), "") : assert_60 node _T_455 = eq(before, UInt<3>(0h4)) node _T_456 = eq(after, UInt<2>(0h2)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(before, UInt<2>(0h3)) node _T_459 = eq(after, UInt<4>(0h8)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(_T_460, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_461, UInt<1>(0h1), "") : assert_61 node _T_465 = eq(before, UInt<2>(0h3)) node _T_466 = eq(after, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(_T_467, UInt<1>(0h0)) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_468, UInt<1>(0h1), "") : assert_62 node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<1>(0h0)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(_T_474, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_475, UInt<1>(0h1), "") : assert_63 node _T_479 = eq(before, UInt<2>(0h3)) node _T_480 = eq(after, UInt<3>(0h7)) node _T_481 = and(_T_479, _T_480) node _T_482 = eq(before, UInt<2>(0h3)) node _T_483 = eq(after, UInt<3>(0h5)) node _T_484 = and(_T_482, _T_483) node _T_485 = eq(before, UInt<2>(0h3)) node _T_486 = eq(after, UInt<3>(0h6)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(before, UInt<2>(0h3)) node _T_489 = eq(after, UInt<3>(0h4)) node _T_490 = and(_T_488, _T_489) node _T_491 = eq(before, UInt<2>(0h3)) node _T_492 = eq(after, UInt<2>(0h2)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(before, UInt<2>(0h2)) node _T_495 = eq(after, UInt<4>(0h8)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(_T_496, UInt<1>(0h0)) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_497, UInt<1>(0h1), "") : assert_64 node _T_501 = eq(before, UInt<2>(0h2)) node _T_502 = eq(after, UInt<1>(0h1)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(_T_503, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_504, UInt<1>(0h1), "") : assert_65 node _T_508 = eq(before, UInt<2>(0h2)) node _T_509 = eq(after, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(_T_510, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_511, UInt<1>(0h1), "") : assert_66 node _T_515 = eq(before, UInt<2>(0h2)) node _T_516 = eq(after, UInt<3>(0h7)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_518, UInt<1>(0h1), "") : assert_67 node _T_522 = eq(before, UInt<2>(0h2)) node _T_523 = eq(after, UInt<3>(0h5)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(_T_524, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_68 assert(clock, _T_525, UInt<1>(0h1), "") : assert_68 node _T_529 = eq(before, UInt<2>(0h2)) node _T_530 = eq(after, UInt<3>(0h6)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(before, UInt<2>(0h2)) node _T_533 = eq(after, UInt<3>(0h4)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(before, UInt<2>(0h2)) node _T_536 = eq(after, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _T_538 = eq(_T_537, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,false,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_69 assert(clock, _T_538, UInt<1>(0h1), "") : assert_69 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 3, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 4) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<1>(0h1)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<4>(0h8)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<4>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 3, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 4) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<1>(0h0)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<4>(0h8)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_542 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_543 = and(probe_toN, _T_542) node _T_544 = eq(probe_toN, UInt<1>(0h0)) node _T_545 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_546 = and(_T_544, _T_545) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_547 = eq(set_pprobeack, UInt<1>(0h0)) node _T_548 = and(_T_547, w_rprobeackfirst) node _T_549 = and(set_pprobeack, w_rprobeackfirst) node _T_550 = neq(meta.state, UInt<2>(0h0)) node _T_551 = eq(io.sinkc.bits.tag, meta.tag) node _T_552 = and(_T_550, _T_551) node _T_553 = and(_T_552, io.sinkc.bits.data) when _T_553 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_554 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_555 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_556 = or(_T_554, _T_555) when _T_556 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_557 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_558 = eq(request.offset, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_561 = neq(request.offset, UInt<1>(0h0)) node _T_562 = and(_T_560, _T_561) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_563 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_563 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, tag : UInt<12>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 3, 0) node _new_clientBit_T = shr(new_request.source, 4) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<1>(0h1)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<4>(0h8)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<4>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 3, 0) node _new_clientBit_T_6 = shr(new_request.source, 4) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<1>(0h0)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<4>(0h8)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_564 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_564 : node _T_565 = eq(prior, UInt<4>(0h8)) node _T_566 = eq(prior, UInt<1>(0h1)) node _T_567 = eq(_T_566, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_70 assert(clock, _T_567, UInt<1>(0h1), "") : assert_70 node _T_571 = eq(prior, UInt<1>(0h0)) node _T_572 = eq(_T_571, UInt<1>(0h0)) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,false,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_71 assert(clock, _T_572, UInt<1>(0h1), "") : assert_71 node _T_576 = eq(prior, UInt<3>(0h7)) node _T_577 = eq(prior, UInt<3>(0h5)) node _T_578 = eq(prior, UInt<3>(0h4)) node _T_579 = eq(prior, UInt<3>(0h6)) node _T_580 = eq(prior, UInt<2>(0h3)) node _T_581 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_582 = eq(request_valid, UInt<1>(0h0)) node _T_583 = and(io.schedule.ready, io.schedule.valid) node _T_584 = and(no_wait, _T_583) node _T_585 = or(_T_582, _T_584) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_72 assert(clock, _T_585, UInt<1>(0h1), "") : assert_72 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_589 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_590 = or(io.directory.valid, _T_589) when _T_590 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_591 = and(new_request.prio[2], UInt<1>(0h1)) when _T_591 : connect s_execute, UInt<1>(0h0) node _T_592 = bits(new_request.opcode, 0, 0) node _T_593 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) when _T_594 : connect s_writeback, UInt<1>(0h0) node _T_595 = eq(new_request.param, UInt<3>(0h0)) node _T_596 = eq(new_request.param, UInt<3>(0h4)) node _T_597 = or(_T_595, _T_596) node _T_598 = eq(new_meta.state, UInt<2>(0h2)) node _T_599 = and(_T_597, _T_598) when _T_599 : connect s_writeback, UInt<1>(0h0) node _T_600 = eq(new_request.param, UInt<3>(0h1)) node _T_601 = eq(new_request.param, UInt<3>(0h2)) node _T_602 = or(_T_600, _T_601) node _T_603 = eq(new_request.param, UInt<3>(0h5)) node _T_604 = or(_T_602, _T_603) node _T_605 = and(new_meta.clients, new_clientBit) node _T_606 = neq(_T_605, UInt<1>(0h0)) node _T_607 = and(_T_604, _T_606) when _T_607 : connect s_writeback, UInt<1>(0h0) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(new_meta.hit, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_73 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_73 else : node _T_611 = and(new_request.control, UInt<1>(0h1)) when _T_611 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_612 = neq(new_meta.clients, UInt<1>(0h0)) node _T_613 = and(UInt<1>(0h1), _T_612) when _T_613 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_614 = eq(new_meta.hit, UInt<1>(0h0)) node _T_615 = neq(new_meta.state, UInt<2>(0h0)) node _T_616 = and(_T_614, _T_615) when _T_616 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_617 = neq(new_meta.clients, UInt<1>(0h0)) node _T_618 = and(UInt<1>(0h1), _T_617) when _T_618 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_619 = eq(new_meta.hit, UInt<1>(0h0)) node _T_620 = eq(new_meta.state, UInt<2>(0h1)) node _T_621 = and(_T_620, new_needT) node _T_622 = or(_T_619, _T_621) when _T_622 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_623 = eq(new_meta.state, UInt<2>(0h2)) node _T_624 = or(new_needT, _T_623) node _T_625 = and(new_meta.hit, _T_624) node _T_626 = not(new_skipProbe) node _T_627 = and(new_meta.clients, _T_626) node _T_628 = neq(_T_627, UInt<1>(0h0)) node _T_629 = and(_T_625, _T_628) node _T_630 = and(UInt<1>(0h1), _T_629) when _T_630 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_631 = eq(new_request.opcode, UInt<3>(0h6)) node _T_632 = eq(new_request.opcode, UInt<3>(0h7)) node _T_633 = or(_T_631, _T_632) when _T_633 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_634 = bits(new_request.opcode, 2, 2) node _T_635 = eq(_T_634, UInt<1>(0h0)) node _T_636 = and(_T_635, new_meta.hit) node _T_637 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_638 = and(_T_636, _T_637) when _T_638 : connect s_writeback, UInt<1>(0h0)

module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [4:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [11:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] reg [11:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_590 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(_T_12, _T_19) node _T_35 = or(_T_34, _T_26) node _T_36 = or(_T_35, _T_33) node _T_37 = or(_T_5, _T_36) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_37, UInt<1>(0h1), "") : assert_1 node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_42 = or(_T_41, UInt<1>(0h0)) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = or(_T_46, UInt<1>(0h0)) node _T_48 = asUInt(reset) node _T_49 = eq(_T_48, UInt<1>(0h0)) when _T_49 : node _T_50 = eq(_T_47, UInt<1>(0h0)) when _T_50 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_47, UInt<1>(0h1), "") : assert_3

module NoCMonitor_9( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_40 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_40( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - 12'h2B; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_470 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_214 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_470( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_214 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_23 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} inst main of BranchKillableQueue_22 connect main.clock, clock connect main.reset, reset reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect main.io.enq, io.enq connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect main.io.brupdate.b2.taken, io.brupdate.b2.taken connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect main.io.flush, io.flush node _io_empty_T = eq(out_valid, UInt<1>(0h0)) node _io_empty_T_1 = and(main.io.empty, _io_empty_T) connect io.empty, _io_empty_T_1 node _io_count_T = add(main.io.count, out_valid) node _io_count_T_1 = tail(_io_count_T, 1) connect io.count, _io_count_T_1 connect io.deq.valid, out_valid connect io.deq.bits, out_reg connect io.deq.bits.uop, out_uop wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out, out_uop node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T) connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1 connect out_uop, out_uop_out node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask) node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0)) node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0)) node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0)) node _out_valid_T_4 = and(out_valid, _out_valid_T_3) node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq) node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0)) node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6) connect out_valid, _out_valid_T_7 connect main.io.deq.ready, UInt<1>(0h0) node _T = and(io.deq.ready, io.deq.valid) node _T_1 = eq(out_valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) when _T_2 : node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask) node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0)) node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0)) node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0)) node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11) node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq) node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0)) node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14) connect out_valid, _out_valid_T_15 connect out_reg, main.io.deq.bits wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out_1, main.io.deq.bits.uop node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2) connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3 connect out_uop, out_uop_out_1 connect main.io.deq.ready, UInt<1>(0h1)

module BranchKillableQueue_23( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _out_valid_T_12; // @[util.scala:496:38] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27] wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94] wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [33:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [33:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22] reg [1:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35] wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}] wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_22 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_out_valid_T_12), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e11_s53_i32_6 : input clock : Clock input reset : Reset output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 11, 11) node posExp = bits(rawIn.sExp, 10, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 51, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 51) node _alignedSig_T_1 = bits(shiftedSig, 50, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) node _roundCarryBut2_T = bits(unroundedInt, 29, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<6>(0h20)) node _common_overflow_T_1 = bits(unroundedInt, 30, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 30, 30) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1

module RecFNToIN_e11_s53_i32_6( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [83:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[83:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [31:0] roundedInt = {_roundedInt_T_3[31:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[10:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_52 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_52( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s6k4z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d128s6k4z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d128s6k4z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d128s6k4z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d128s6k4z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d128s6k4z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready

module TLBuffer_a32d128s6k4z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21] wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21] wire [5:0] auto_out_b_bits_source = 6'h20; // @[Decoupled.scala:362:21] wire [5:0] nodeOut_b_bits_source = 6'h20; // @[Decoupled.scala:362:21] wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire [5:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d128s6k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d128s6k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d128s6k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d128s6k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d128s6k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<18>(0h2f000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = and(_T_192, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_191, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<5>(0h10)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_12) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<5>(0h11)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_13) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<5>(0h12)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_14) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<5>(0h13)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_15) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_231 = shr(io.in.a.bits.source, 4) node _T_232 = eq(_T_231, UInt<1>(0h1)) node _T_233 = leq(UInt<1>(0h0), uncommonBits_16) node _T_234 = and(_T_232, _T_233) node _T_235 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_17) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_236 connect _WIRE[8], _T_242 connect _WIRE[9], _T_243 connect _WIRE[10], _T_244 node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0)) node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = or(_T_246, _T_247) node _T_258 = or(_T_257, _T_248) node _T_259 = or(_T_258, _T_249) node _T_260 = or(_T_259, _T_250) node _T_261 = or(_T_260, _T_251) node _T_262 = or(_T_261, _T_252) node _T_263 = or(_T_262, _T_253) node _T_264 = or(_T_263, _T_254) node _T_265 = or(_T_264, _T_255) node _T_266 = or(_T_265, _T_256) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_266 node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_269 = and(_T_267, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<18>(0h2f000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_WIRE_1, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_278, UInt<1>(0h1), "") : assert_3 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_286 = asUInt(reset) node _T_287 = eq(_T_286, UInt<1>(0h0)) when _T_287 : node _T_288 = eq(_T_285, UInt<1>(0h0)) when _T_288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_285, UInt<1>(0h1), "") : assert_5 node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(is_aligned, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_292, UInt<1>(0h1), "") : assert_7 node _T_296 = not(io.in.a.bits.mask) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_297, UInt<1>(0h1), "") : assert_8 node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_301, UInt<1>(0h1), "") : assert_9 node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_305 : node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_310 = shr(io.in.a.bits.source, 2) node _T_311 = eq(_T_310, UInt<5>(0h10)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_18) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_316 = shr(io.in.a.bits.source, 2) node _T_317 = eq(_T_316, UInt<5>(0h11)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_19) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_322 = shr(io.in.a.bits.source, 2) node _T_323 = eq(_T_322, UInt<5>(0h12)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_20) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_327 = and(_T_325, _T_326) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_328 = shr(io.in.a.bits.source, 2) node _T_329 = eq(_T_328, UInt<5>(0h13)) node _T_330 = leq(UInt<1>(0h0), uncommonBits_21) node _T_331 = and(_T_329, _T_330) node _T_332 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_336 = shr(io.in.a.bits.source, 4) node _T_337 = eq(_T_336, UInt<1>(0h1)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_22) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_342 = shr(io.in.a.bits.source, 4) node _T_343 = eq(_T_342, UInt<1>(0h0)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_23) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_350 = or(_T_309, _T_315) node _T_351 = or(_T_350, _T_321) node _T_352 = or(_T_351, _T_327) node _T_353 = or(_T_352, _T_333) node _T_354 = or(_T_353, _T_334) node _T_355 = or(_T_354, _T_335) node _T_356 = or(_T_355, _T_341) node _T_357 = or(_T_356, _T_347) node _T_358 = or(_T_357, _T_348) node _T_359 = or(_T_358, _T_349) node _T_360 = and(_T_308, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_364 = cvt(_T_363) node _T_365 = and(_T_364, asSInt(UInt<18>(0h2f000))) node _T_366 = asSInt(_T_365) node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) node _T_368 = and(_T_362, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = and(_T_361, _T_369) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_370, UInt<1>(0h1), "") : assert_10 node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<5>(0h10)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_24) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_381 = shr(io.in.a.bits.source, 2) node _T_382 = eq(_T_381, UInt<5>(0h11)) node _T_383 = leq(UInt<1>(0h0), uncommonBits_25) node _T_384 = and(_T_382, _T_383) node _T_385 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_387 = shr(io.in.a.bits.source, 2) node _T_388 = eq(_T_387, UInt<5>(0h12)) node _T_389 = leq(UInt<1>(0h0), uncommonBits_26) node _T_390 = and(_T_388, _T_389) node _T_391 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_392 = and(_T_390, _T_391) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_393 = shr(io.in.a.bits.source, 2) node _T_394 = eq(_T_393, UInt<5>(0h13)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_27) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_401 = shr(io.in.a.bits.source, 4) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_28) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_407 = shr(io.in.a.bits.source, 4) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_29) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_374 connect _WIRE_2[1], _T_380 connect _WIRE_2[2], _T_386 connect _WIRE_2[3], _T_392 connect _WIRE_2[4], _T_398 connect _WIRE_2[5], _T_399 connect _WIRE_2[6], _T_400 connect _WIRE_2[7], _T_406 connect _WIRE_2[8], _T_412 connect _WIRE_2[9], _T_413 connect _WIRE_2[10], _T_414 node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0)) node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = or(_T_416, _T_417) node _T_428 = or(_T_427, _T_418) node _T_429 = or(_T_428, _T_419) node _T_430 = or(_T_429, _T_420) node _T_431 = or(_T_430, _T_421) node _T_432 = or(_T_431, _T_422) node _T_433 = or(_T_432, _T_423) node _T_434 = or(_T_433, _T_424) node _T_435 = or(_T_434, _T_425) node _T_436 = or(_T_435, _T_426) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_436 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<18>(0h2f000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_WIRE_3, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_448, UInt<1>(0h1), "") : assert_11 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_T_455, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_455, UInt<1>(0h1), "") : assert_13 node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(is_aligned, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_462, UInt<1>(0h1), "") : assert_15 node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_466, UInt<1>(0h1), "") : assert_16 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_471, UInt<1>(0h1), "") : assert_17 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_475, UInt<1>(0h1), "") : assert_18 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<5>(0h10)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_30) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<5>(0h11)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_31) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<5>(0h12)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_32) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<5>(0h13)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_33) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_510 = shr(io.in.a.bits.source, 4) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_34) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_516 = shr(io.in.a.bits.source, 4) node _T_517 = eq(_T_516, UInt<1>(0h0)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_35) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_524 = or(_T_483, _T_489) node _T_525 = or(_T_524, _T_495) node _T_526 = or(_T_525, _T_501) node _T_527 = or(_T_526, _T_507) node _T_528 = or(_T_527, _T_508) node _T_529 = or(_T_528, _T_509) node _T_530 = or(_T_529, _T_515) node _T_531 = or(_T_530, _T_521) node _T_532 = or(_T_531, _T_522) node _T_533 = or(_T_532, _T_523) node _T_534 = and(_T_482, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_535, UInt<1>(0h1), "") : assert_19 node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_541 = and(_T_539, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<18>(0h2f000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = and(_T_542, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_549, UInt<1>(0h1), "") : assert_20 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(source_ok, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(is_aligned, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_559, UInt<1>(0h1), "") : assert_23 node _T_563 = eq(io.in.a.bits.mask, mask) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_563, UInt<1>(0h1), "") : assert_24 node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_567, UInt<1>(0h1), "") : assert_25 node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_571 : node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<5>(0h10)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_36) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<5>(0h11)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_37) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<5>(0h12)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_38) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<5>(0h13)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_39) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_602 = shr(io.in.a.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_40) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_608 = shr(io.in.a.bits.source, 4) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_41) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_616 = or(_T_575, _T_581) node _T_617 = or(_T_616, _T_587) node _T_618 = or(_T_617, _T_593) node _T_619 = or(_T_618, _T_599) node _T_620 = or(_T_619, _T_600) node _T_621 = or(_T_620, _T_601) node _T_622 = or(_T_621, _T_607) node _T_623 = or(_T_622, _T_613) node _T_624 = or(_T_623, _T_614) node _T_625 = or(_T_624, _T_615) node _T_626 = and(_T_574, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_630 = and(_T_628, _T_629) node _T_631 = or(UInt<1>(0h0), _T_630) node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_633 = cvt(_T_632) node _T_634 = and(_T_633, asSInt(UInt<18>(0h2f000))) node _T_635 = asSInt(_T_634) node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0))) node _T_637 = and(_T_631, _T_636) node _T_638 = or(UInt<1>(0h0), _T_637) node _T_639 = and(_T_627, _T_638) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_639, UInt<1>(0h1), "") : assert_26 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(source_ok, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(is_aligned, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_650 = asUInt(reset) node _T_651 = eq(_T_650, UInt<1>(0h0)) when _T_651 : node _T_652 = eq(_T_649, UInt<1>(0h0)) when _T_652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_649, UInt<1>(0h1), "") : assert_29 node _T_653 = eq(io.in.a.bits.mask, mask) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_653, UInt<1>(0h1), "") : assert_30 node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_657 : node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_662 = shr(io.in.a.bits.source, 2) node _T_663 = eq(_T_662, UInt<5>(0h10)) node _T_664 = leq(UInt<1>(0h0), uncommonBits_42) node _T_665 = and(_T_663, _T_664) node _T_666 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_667 = and(_T_665, _T_666) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_668 = shr(io.in.a.bits.source, 2) node _T_669 = eq(_T_668, UInt<5>(0h11)) node _T_670 = leq(UInt<1>(0h0), uncommonBits_43) node _T_671 = and(_T_669, _T_670) node _T_672 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_673 = and(_T_671, _T_672) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_674 = shr(io.in.a.bits.source, 2) node _T_675 = eq(_T_674, UInt<5>(0h12)) node _T_676 = leq(UInt<1>(0h0), uncommonBits_44) node _T_677 = and(_T_675, _T_676) node _T_678 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_679 = and(_T_677, _T_678) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_680 = shr(io.in.a.bits.source, 2) node _T_681 = eq(_T_680, UInt<5>(0h13)) node _T_682 = leq(UInt<1>(0h0), uncommonBits_45) node _T_683 = and(_T_681, _T_682) node _T_684 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_688 = shr(io.in.a.bits.source, 4) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_46) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_694 = shr(io.in.a.bits.source, 4) node _T_695 = eq(_T_694, UInt<1>(0h0)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_47) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_702 = or(_T_661, _T_667) node _T_703 = or(_T_702, _T_673) node _T_704 = or(_T_703, _T_679) node _T_705 = or(_T_704, _T_685) node _T_706 = or(_T_705, _T_686) node _T_707 = or(_T_706, _T_687) node _T_708 = or(_T_707, _T_693) node _T_709 = or(_T_708, _T_699) node _T_710 = or(_T_709, _T_700) node _T_711 = or(_T_710, _T_701) node _T_712 = and(_T_660, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_716 = and(_T_714, _T_715) node _T_717 = or(UInt<1>(0h0), _T_716) node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<18>(0h2f000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = and(_T_713, _T_724) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_725, UInt<1>(0h1), "") : assert_31 node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(source_ok, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(is_aligned, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_735, UInt<1>(0h1), "") : assert_34 node _T_739 = not(mask) node _T_740 = and(io.in.a.bits.mask, _T_739) node _T_741 = eq(_T_740, UInt<1>(0h0)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_741, UInt<1>(0h1), "") : assert_35 node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_745 : node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<5>(0h10)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_48) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<5>(0h11)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_49) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<5>(0h12)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_50) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_768 = shr(io.in.a.bits.source, 2) node _T_769 = eq(_T_768, UInt<5>(0h13)) node _T_770 = leq(UInt<1>(0h0), uncommonBits_51) node _T_771 = and(_T_769, _T_770) node _T_772 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_773 = and(_T_771, _T_772) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_776 = shr(io.in.a.bits.source, 4) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_52) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_782 = shr(io.in.a.bits.source, 4) node _T_783 = eq(_T_782, UInt<1>(0h0)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_53) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_787 = and(_T_785, _T_786) node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_790 = or(_T_749, _T_755) node _T_791 = or(_T_790, _T_761) node _T_792 = or(_T_791, _T_767) node _T_793 = or(_T_792, _T_773) node _T_794 = or(_T_793, _T_774) node _T_795 = or(_T_794, _T_775) node _T_796 = or(_T_795, _T_781) node _T_797 = or(_T_796, _T_787) node _T_798 = or(_T_797, _T_788) node _T_799 = or(_T_798, _T_789) node _T_800 = and(_T_748, _T_799) node _T_801 = or(UInt<1>(0h0), _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<18>(0h2f000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = or(UInt<1>(0h0), _T_808) node _T_810 = and(_T_801, _T_809) node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_T_810, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_810, UInt<1>(0h1), "") : assert_36 node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(source_ok, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(is_aligned, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_820, UInt<1>(0h1), "") : assert_39 node _T_824 = eq(io.in.a.bits.mask, mask) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_824, UInt<1>(0h1), "") : assert_40 node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_828 : node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<5>(0h10)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_54) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<5>(0h11)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_55) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<5>(0h12)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_56) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<5>(0h13)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_57) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_859 = shr(io.in.a.bits.source, 4) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_58) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_865 = shr(io.in.a.bits.source, 4) node _T_866 = eq(_T_865, UInt<1>(0h0)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_59) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_873 = or(_T_832, _T_838) node _T_874 = or(_T_873, _T_844) node _T_875 = or(_T_874, _T_850) node _T_876 = or(_T_875, _T_856) node _T_877 = or(_T_876, _T_857) node _T_878 = or(_T_877, _T_858) node _T_879 = or(_T_878, _T_864) node _T_880 = or(_T_879, _T_870) node _T_881 = or(_T_880, _T_871) node _T_882 = or(_T_881, _T_872) node _T_883 = and(_T_831, _T_882) node _T_884 = or(UInt<1>(0h0), _T_883) node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<18>(0h2f000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = and(_T_885, _T_890) node _T_892 = or(UInt<1>(0h0), _T_891) node _T_893 = and(_T_884, _T_892) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_893, UInt<1>(0h1), "") : assert_41 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(source_ok, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(is_aligned, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_903, UInt<1>(0h1), "") : assert_44 node _T_907 = eq(io.in.a.bits.mask, mask) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_907, UInt<1>(0h1), "") : assert_45 node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_911 : node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_914 = and(_T_912, _T_913) node _T_915 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_916 = shr(io.in.a.bits.source, 2) node _T_917 = eq(_T_916, UInt<5>(0h10)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_60) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_922 = shr(io.in.a.bits.source, 2) node _T_923 = eq(_T_922, UInt<5>(0h11)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_61) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_928 = shr(io.in.a.bits.source, 2) node _T_929 = eq(_T_928, UInt<5>(0h12)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_62) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<5>(0h13)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_63) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_942 = shr(io.in.a.bits.source, 4) node _T_943 = eq(_T_942, UInt<1>(0h1)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_64) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_948 = shr(io.in.a.bits.source, 4) node _T_949 = eq(_T_948, UInt<1>(0h0)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_65) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_953 = and(_T_951, _T_952) node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_956 = or(_T_915, _T_921) node _T_957 = or(_T_956, _T_927) node _T_958 = or(_T_957, _T_933) node _T_959 = or(_T_958, _T_939) node _T_960 = or(_T_959, _T_940) node _T_961 = or(_T_960, _T_941) node _T_962 = or(_T_961, _T_947) node _T_963 = or(_T_962, _T_953) node _T_964 = or(_T_963, _T_954) node _T_965 = or(_T_964, _T_955) node _T_966 = and(_T_914, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_970 = cvt(_T_969) node _T_971 = and(_T_970, asSInt(UInt<18>(0h2f000))) node _T_972 = asSInt(_T_971) node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0))) node _T_974 = and(_T_968, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = and(_T_967, _T_975) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_976, UInt<1>(0h1), "") : assert_46 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(source_ok, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(is_aligned, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_986, UInt<1>(0h1), "") : assert_49 node _T_990 = eq(io.in.a.bits.mask, mask) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_990, UInt<1>(0h1), "") : assert_50 node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_994, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_998, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54 node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55 node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57 node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1022 : node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(source_ok_1, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(sink_ok, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60 node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61 node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62 node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64 node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1050 : node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(source_ok_1, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(sink_ok, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67 node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68 node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69 node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1070 = or(_T_1069, io.in.d.bits.corrupt) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70 node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1075 = or(UInt<1>(0h0), _T_1074) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71 node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1079 : node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(_T_1083, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73 node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74 node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1092 = or(UInt<1>(0h0), _T_1091) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75 node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1096 : node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(source_ok_1, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77 node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1105 = or(_T_1104, io.in.d.bits.corrupt) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78 node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1110 = or(UInt<1>(0h0), _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79 node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1114 : node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(source_ok_1, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81 node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82 node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1127 = or(UInt<1>(0h0), _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1143 = eq(a_first, UInt<1>(0h0)) node _T_1144 = and(io.in.a.valid, _T_1143) when _T_1144 : node _T_1145 = eq(io.in.a.bits.opcode, opcode) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87 node _T_1149 = eq(io.in.a.bits.param, param) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88 node _T_1153 = eq(io.in.a.bits.size, size) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89 node _T_1157 = eq(io.in.a.bits.source, source) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90 node _T_1161 = eq(io.in.a.bits.address, address) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91 node _T_1165 = and(io.in.a.ready, io.in.a.valid) node _T_1166 = and(_T_1165, a_first) when _T_1166 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1167 = eq(d_first, UInt<1>(0h0)) node _T_1168 = and(io.in.d.valid, _T_1167) when _T_1168 : node _T_1169 = eq(io.in.d.bits.opcode, opcode_1) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92 node _T_1173 = eq(io.in.d.bits.param, param_1) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93 node _T_1177 = eq(io.in.d.bits.size, size_1) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94 node _T_1181 = eq(io.in.d.bits.source, source_1) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95 node _T_1185 = eq(io.in.d.bits.sink, sink) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96 node _T_1189 = eq(io.in.d.bits.denied, denied) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97 node _T_1193 = and(io.in.d.ready, io.in.d.valid) node _T_1194 = and(_T_1193, d_first) when _T_1194 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1195 = and(io.in.a.valid, a_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) when _T_1196 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1197 = and(io.in.a.ready, io.in.a.valid) node _T_1198 = and(_T_1197, a_first_1) node _T_1199 = and(_T_1198, UInt<1>(0h1)) when _T_1199 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1200 = dshr(inflight, io.in.a.bits.source) node _T_1201 = bits(_T_1200, 0, 0) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1206 = and(io.in.d.valid, d_first_1) node _T_1207 = and(_T_1206, UInt<1>(0h1)) node _T_1208 = eq(d_release_ack, UInt<1>(0h0)) node _T_1209 = and(_T_1207, _T_1208) when _T_1209 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = and(_T_1210, d_first_1) node _T_1212 = and(_T_1211, UInt<1>(0h1)) node _T_1213 = eq(d_release_ack, UInt<1>(0h0)) node _T_1214 = and(_T_1212, _T_1213) when _T_1214 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1215 = and(io.in.d.valid, d_first_1) node _T_1216 = and(_T_1215, UInt<1>(0h1)) node _T_1217 = eq(d_release_ack, UInt<1>(0h0)) node _T_1218 = and(_T_1216, _T_1217) when _T_1218 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1219 = dshr(inflight, io.in.d.bits.source) node _T_1220 = bits(_T_1219, 0, 0) node _T_1221 = or(_T_1220, same_cycle_resp) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1227 = or(_T_1225, _T_1226) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100 node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101 else : node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1237 = or(_T_1235, _T_1236) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102 node _T_1241 = eq(io.in.d.bits.size, a_size_lookup) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103 node _T_1245 = and(io.in.d.valid, d_first_1) node _T_1246 = and(_T_1245, a_first_1) node _T_1247 = and(_T_1246, io.in.a.valid) node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1249 = and(_T_1247, _T_1248) node _T_1250 = eq(d_release_ack, UInt<1>(0h0)) node _T_1251 = and(_T_1249, _T_1250) when _T_1251 : node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1253 = or(_T_1252, io.in.a.ready) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_130 node _T_1257 = orr(inflight) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1260 = or(_T_1258, _T_1259) node _T_1261 = lt(watchdog, plusarg_reader.out) node _T_1262 = or(_T_1260, _T_1261) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1266 = and(io.in.a.ready, io.in.a.valid) node _T_1267 = and(io.in.d.ready, io.in.d.valid) node _T_1268 = or(_T_1266, _T_1267) when _T_1268 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1269 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1270 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1271 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = and(_T_1269, _T_1272) when _T_1273 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1274 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1275 = and(_T_1274, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1276 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1277 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1275, _T_1278) when _T_1279 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1280 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1281 = bits(_T_1280, 0, 0) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1286 = and(io.in.d.valid, d_first_2) node _T_1287 = and(_T_1286, UInt<1>(0h1)) node _T_1288 = and(_T_1287, d_release_ack_1) when _T_1288 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1289 = and(io.in.d.ready, io.in.d.valid) node _T_1290 = and(_T_1289, d_first_2) node _T_1291 = and(_T_1290, UInt<1>(0h1)) node _T_1292 = and(_T_1291, d_release_ack_1) when _T_1292 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1293 = and(io.in.d.valid, d_first_2) node _T_1294 = and(_T_1293, UInt<1>(0h1)) node _T_1295 = and(_T_1294, d_release_ack_1) when _T_1295 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1296 = dshr(inflight_1, io.in.d.bits.source) node _T_1297 = bits(_T_1296, 0, 0) node _T_1298 = or(_T_1297, same_cycle_resp_1) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1302 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_108 else : node _T_1306 = eq(io.in.d.bits.size, c_size_lookup) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_109 node _T_1310 = and(io.in.d.valid, d_first_2) node _T_1311 = and(_T_1310, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1312 = and(_T_1311, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1313 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1314 = and(_T_1312, _T_1313) node _T_1315 = and(_T_1314, d_release_ack_1) node _T_1316 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1317 = and(_T_1315, _T_1316) when _T_1317 : node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1319 = or(_T_1318, _WIRE_27.ready) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_131 node _T_1323 = orr(inflight_1) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) node _T_1325 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1326 = or(_T_1324, _T_1325) node _T_1327 = lt(watchdog_1, plusarg_reader_1.out) node _T_1328 = or(_T_1326, _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:45:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1332 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1333 = and(io.in.d.ready, io.in.d.valid) node _T_1334 = or(_T_1332, _T_1333) when _T_1334 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_63( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_58 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_58( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module Tile_248 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_504 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_248( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_504 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_89 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_89( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_85 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_85( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<17>(0h10000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = and(_T_192, _T_197) node _T_199 = or(UInt<1>(0h0), _T_198) node _T_200 = and(_T_191, _T_199) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_200, UInt<1>(0h1), "") : assert_2 node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_205 = shr(io.in.a.bits.source, 2) node _T_206 = eq(_T_205, UInt<5>(0h10)) node _T_207 = leq(UInt<1>(0h0), uncommonBits_12) node _T_208 = and(_T_206, _T_207) node _T_209 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_210 = and(_T_208, _T_209) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<5>(0h11)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_13) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<5>(0h12)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_14) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<5>(0h13)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_15) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_231 = shr(io.in.a.bits.source, 4) node _T_232 = eq(_T_231, UInt<1>(0h1)) node _T_233 = leq(UInt<1>(0h0), uncommonBits_16) node _T_234 = and(_T_232, _T_233) node _T_235 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_17) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_204 connect _WIRE[1], _T_210 connect _WIRE[2], _T_216 connect _WIRE[3], _T_222 connect _WIRE[4], _T_228 connect _WIRE[5], _T_229 connect _WIRE[6], _T_230 connect _WIRE[7], _T_236 connect _WIRE[8], _T_242 connect _WIRE[9], _T_243 connect _WIRE[10], _T_244 node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0)) node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = or(_T_246, _T_247) node _T_258 = or(_T_257, _T_248) node _T_259 = or(_T_258, _T_249) node _T_260 = or(_T_259, _T_250) node _T_261 = or(_T_260, _T_251) node _T_262 = or(_T_261, _T_252) node _T_263 = or(_T_262, _T_253) node _T_264 = or(_T_263, _T_254) node _T_265 = or(_T_264, _T_255) node _T_266 = or(_T_265, _T_256) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_266 node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_269 = and(_T_267, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<17>(0h10000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = and(_T_270, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = and(_WIRE_1, _T_277) node _T_279 = asUInt(reset) node _T_280 = eq(_T_279, UInt<1>(0h0)) when _T_280 : node _T_281 = eq(_T_278, UInt<1>(0h0)) when _T_281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_278, UInt<1>(0h1), "") : assert_3 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : node _T_284 = eq(source_ok, UInt<1>(0h0)) when _T_284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_286 = asUInt(reset) node _T_287 = eq(_T_286, UInt<1>(0h0)) when _T_287 : node _T_288 = eq(_T_285, UInt<1>(0h0)) when _T_288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_285, UInt<1>(0h1), "") : assert_5 node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(is_aligned, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_292, UInt<1>(0h1), "") : assert_7 node _T_296 = not(io.in.a.bits.mask) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_297, UInt<1>(0h1), "") : assert_8 node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_301, UInt<1>(0h1), "") : assert_9 node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_305 : node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_310 = shr(io.in.a.bits.source, 2) node _T_311 = eq(_T_310, UInt<5>(0h10)) node _T_312 = leq(UInt<1>(0h0), uncommonBits_18) node _T_313 = and(_T_311, _T_312) node _T_314 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_315 = and(_T_313, _T_314) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_316 = shr(io.in.a.bits.source, 2) node _T_317 = eq(_T_316, UInt<5>(0h11)) node _T_318 = leq(UInt<1>(0h0), uncommonBits_19) node _T_319 = and(_T_317, _T_318) node _T_320 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_321 = and(_T_319, _T_320) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_322 = shr(io.in.a.bits.source, 2) node _T_323 = eq(_T_322, UInt<5>(0h12)) node _T_324 = leq(UInt<1>(0h0), uncommonBits_20) node _T_325 = and(_T_323, _T_324) node _T_326 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_327 = and(_T_325, _T_326) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_328 = shr(io.in.a.bits.source, 2) node _T_329 = eq(_T_328, UInt<5>(0h13)) node _T_330 = leq(UInt<1>(0h0), uncommonBits_21) node _T_331 = and(_T_329, _T_330) node _T_332 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_333 = and(_T_331, _T_332) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_336 = shr(io.in.a.bits.source, 4) node _T_337 = eq(_T_336, UInt<1>(0h1)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_22) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_342 = shr(io.in.a.bits.source, 4) node _T_343 = eq(_T_342, UInt<1>(0h0)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_23) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_350 = or(_T_309, _T_315) node _T_351 = or(_T_350, _T_321) node _T_352 = or(_T_351, _T_327) node _T_353 = or(_T_352, _T_333) node _T_354 = or(_T_353, _T_334) node _T_355 = or(_T_354, _T_335) node _T_356 = or(_T_355, _T_341) node _T_357 = or(_T_356, _T_347) node _T_358 = or(_T_357, _T_348) node _T_359 = or(_T_358, _T_349) node _T_360 = and(_T_308, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_364 = cvt(_T_363) node _T_365 = and(_T_364, asSInt(UInt<17>(0h10000))) node _T_366 = asSInt(_T_365) node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) node _T_368 = and(_T_362, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = and(_T_361, _T_369) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_370, UInt<1>(0h1), "") : assert_10 node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<5>(0h10)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_24) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_381 = shr(io.in.a.bits.source, 2) node _T_382 = eq(_T_381, UInt<5>(0h11)) node _T_383 = leq(UInt<1>(0h0), uncommonBits_25) node _T_384 = and(_T_382, _T_383) node _T_385 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_387 = shr(io.in.a.bits.source, 2) node _T_388 = eq(_T_387, UInt<5>(0h12)) node _T_389 = leq(UInt<1>(0h0), uncommonBits_26) node _T_390 = and(_T_388, _T_389) node _T_391 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_392 = and(_T_390, _T_391) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_393 = shr(io.in.a.bits.source, 2) node _T_394 = eq(_T_393, UInt<5>(0h13)) node _T_395 = leq(UInt<1>(0h0), uncommonBits_27) node _T_396 = and(_T_394, _T_395) node _T_397 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_401 = shr(io.in.a.bits.source, 4) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_28) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_407 = shr(io.in.a.bits.source, 4) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_29) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_374 connect _WIRE_2[1], _T_380 connect _WIRE_2[2], _T_386 connect _WIRE_2[3], _T_392 connect _WIRE_2[4], _T_398 connect _WIRE_2[5], _T_399 connect _WIRE_2[6], _T_400 connect _WIRE_2[7], _T_406 connect _WIRE_2[8], _T_412 connect _WIRE_2[9], _T_413 connect _WIRE_2[10], _T_414 node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0)) node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = or(_T_416, _T_417) node _T_428 = or(_T_427, _T_418) node _T_429 = or(_T_428, _T_419) node _T_430 = or(_T_429, _T_420) node _T_431 = or(_T_430, _T_421) node _T_432 = or(_T_431, _T_422) node _T_433 = or(_T_432, _T_423) node _T_434 = or(_T_433, _T_424) node _T_435 = or(_T_434, _T_425) node _T_436 = or(_T_435, _T_426) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_436 node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = and(_T_440, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_WIRE_3, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_448, UInt<1>(0h1), "") : assert_11 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_T_455, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_455, UInt<1>(0h1), "") : assert_13 node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(is_aligned, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_462, UInt<1>(0h1), "") : assert_15 node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_466, UInt<1>(0h1), "") : assert_16 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_471, UInt<1>(0h1), "") : assert_17 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_475, UInt<1>(0h1), "") : assert_18 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<5>(0h10)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_30) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<5>(0h11)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_31) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<5>(0h12)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_32) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<5>(0h13)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_33) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_510 = shr(io.in.a.bits.source, 4) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_34) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_516 = shr(io.in.a.bits.source, 4) node _T_517 = eq(_T_516, UInt<1>(0h0)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_35) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_524 = or(_T_483, _T_489) node _T_525 = or(_T_524, _T_495) node _T_526 = or(_T_525, _T_501) node _T_527 = or(_T_526, _T_507) node _T_528 = or(_T_527, _T_508) node _T_529 = or(_T_528, _T_509) node _T_530 = or(_T_529, _T_515) node _T_531 = or(_T_530, _T_521) node _T_532 = or(_T_531, _T_522) node _T_533 = or(_T_532, _T_523) node _T_534 = and(_T_482, _T_533) node _T_535 = or(UInt<1>(0h0), _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_535, UInt<1>(0h1), "") : assert_19 node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_541 = and(_T_539, _T_540) node _T_542 = or(UInt<1>(0h0), _T_541) node _T_543 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_544 = cvt(_T_543) node _T_545 = and(_T_544, asSInt(UInt<17>(0h10000))) node _T_546 = asSInt(_T_545) node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0))) node _T_548 = and(_T_542, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_549, UInt<1>(0h1), "") : assert_20 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(source_ok, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(is_aligned, UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_559, UInt<1>(0h1), "") : assert_23 node _T_563 = eq(io.in.a.bits.mask, mask) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_563, UInt<1>(0h1), "") : assert_24 node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_567, UInt<1>(0h1), "") : assert_25 node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_571 : node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_574 = and(_T_572, _T_573) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<5>(0h10)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_36) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<5>(0h11)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_37) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<5>(0h12)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_38) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_594 = shr(io.in.a.bits.source, 2) node _T_595 = eq(_T_594, UInt<5>(0h13)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_39) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_602 = shr(io.in.a.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_40) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_608 = shr(io.in.a.bits.source, 4) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_41) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_616 = or(_T_575, _T_581) node _T_617 = or(_T_616, _T_587) node _T_618 = or(_T_617, _T_593) node _T_619 = or(_T_618, _T_599) node _T_620 = or(_T_619, _T_600) node _T_621 = or(_T_620, _T_601) node _T_622 = or(_T_621, _T_607) node _T_623 = or(_T_622, _T_613) node _T_624 = or(_T_623, _T_614) node _T_625 = or(_T_624, _T_615) node _T_626 = and(_T_574, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_629 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<17>(0h10000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = and(_T_628, _T_633) node _T_635 = or(UInt<1>(0h0), _T_634) node _T_636 = and(_T_627, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_636, UInt<1>(0h1), "") : assert_26 node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(source_ok, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(is_aligned, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_646 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_646, UInt<1>(0h1), "") : assert_29 node _T_650 = eq(io.in.a.bits.mask, mask) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_650, UInt<1>(0h1), "") : assert_30 node _T_654 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_654 : node _T_655 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_656 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_657 = and(_T_655, _T_656) node _T_658 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_659 = shr(io.in.a.bits.source, 2) node _T_660 = eq(_T_659, UInt<5>(0h10)) node _T_661 = leq(UInt<1>(0h0), uncommonBits_42) node _T_662 = and(_T_660, _T_661) node _T_663 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_664 = and(_T_662, _T_663) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_665 = shr(io.in.a.bits.source, 2) node _T_666 = eq(_T_665, UInt<5>(0h11)) node _T_667 = leq(UInt<1>(0h0), uncommonBits_43) node _T_668 = and(_T_666, _T_667) node _T_669 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_670 = and(_T_668, _T_669) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_671 = shr(io.in.a.bits.source, 2) node _T_672 = eq(_T_671, UInt<5>(0h12)) node _T_673 = leq(UInt<1>(0h0), uncommonBits_44) node _T_674 = and(_T_672, _T_673) node _T_675 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_676 = and(_T_674, _T_675) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_677 = shr(io.in.a.bits.source, 2) node _T_678 = eq(_T_677, UInt<5>(0h13)) node _T_679 = leq(UInt<1>(0h0), uncommonBits_45) node _T_680 = and(_T_678, _T_679) node _T_681 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_682 = and(_T_680, _T_681) node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_685 = shr(io.in.a.bits.source, 4) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_46) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_691 = shr(io.in.a.bits.source, 4) node _T_692 = eq(_T_691, UInt<1>(0h0)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_47) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_698 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_699 = or(_T_658, _T_664) node _T_700 = or(_T_699, _T_670) node _T_701 = or(_T_700, _T_676) node _T_702 = or(_T_701, _T_682) node _T_703 = or(_T_702, _T_683) node _T_704 = or(_T_703, _T_684) node _T_705 = or(_T_704, _T_690) node _T_706 = or(_T_705, _T_696) node _T_707 = or(_T_706, _T_697) node _T_708 = or(_T_707, _T_698) node _T_709 = and(_T_657, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_712 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_713 = cvt(_T_712) node _T_714 = and(_T_713, asSInt(UInt<17>(0h10000))) node _T_715 = asSInt(_T_714) node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0))) node _T_717 = and(_T_711, _T_716) node _T_718 = or(UInt<1>(0h0), _T_717) node _T_719 = and(_T_710, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_719, UInt<1>(0h1), "") : assert_31 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(source_ok, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(is_aligned, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_729 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_729, UInt<1>(0h1), "") : assert_34 node _T_733 = not(mask) node _T_734 = and(io.in.a.bits.mask, _T_733) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_735, UInt<1>(0h1), "") : assert_35 node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_739 : node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _T_743 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<5>(0h10)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_48) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_750 = shr(io.in.a.bits.source, 2) node _T_751 = eq(_T_750, UInt<5>(0h11)) node _T_752 = leq(UInt<1>(0h0), uncommonBits_49) node _T_753 = and(_T_751, _T_752) node _T_754 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_755 = and(_T_753, _T_754) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_756 = shr(io.in.a.bits.source, 2) node _T_757 = eq(_T_756, UInt<5>(0h12)) node _T_758 = leq(UInt<1>(0h0), uncommonBits_50) node _T_759 = and(_T_757, _T_758) node _T_760 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_761 = and(_T_759, _T_760) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_762 = shr(io.in.a.bits.source, 2) node _T_763 = eq(_T_762, UInt<5>(0h13)) node _T_764 = leq(UInt<1>(0h0), uncommonBits_51) node _T_765 = and(_T_763, _T_764) node _T_766 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_770 = shr(io.in.a.bits.source, 4) node _T_771 = eq(_T_770, UInt<1>(0h1)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_52) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_776 = shr(io.in.a.bits.source, 4) node _T_777 = eq(_T_776, UInt<1>(0h0)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_53) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_783 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_784 = or(_T_743, _T_749) node _T_785 = or(_T_784, _T_755) node _T_786 = or(_T_785, _T_761) node _T_787 = or(_T_786, _T_767) node _T_788 = or(_T_787, _T_768) node _T_789 = or(_T_788, _T_769) node _T_790 = or(_T_789, _T_775) node _T_791 = or(_T_790, _T_781) node _T_792 = or(_T_791, _T_782) node _T_793 = or(_T_792, _T_783) node _T_794 = and(_T_742, _T_793) node _T_795 = or(UInt<1>(0h0), _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), _T_802) node _T_804 = and(_T_795, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<5>(0h10)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_54) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<5>(0h11)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_55) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<5>(0h12)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_56) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<5>(0h13)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_57) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _T_851 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_853 = shr(io.in.a.bits.source, 4) node _T_854 = eq(_T_853, UInt<1>(0h1)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_58) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_859 = shr(io.in.a.bits.source, 4) node _T_860 = eq(_T_859, UInt<1>(0h0)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_59) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_864 = and(_T_862, _T_863) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_866 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_867 = or(_T_826, _T_832) node _T_868 = or(_T_867, _T_838) node _T_869 = or(_T_868, _T_844) node _T_870 = or(_T_869, _T_850) node _T_871 = or(_T_870, _T_851) node _T_872 = or(_T_871, _T_852) node _T_873 = or(_T_872, _T_858) node _T_874 = or(_T_873, _T_864) node _T_875 = or(_T_874, _T_865) node _T_876 = or(_T_875, _T_866) node _T_877 = and(_T_825, _T_876) node _T_878 = or(UInt<1>(0h0), _T_877) node _T_879 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_880 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<17>(0h10000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = and(_T_879, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = and(_T_878, _T_886) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_887, UInt<1>(0h1), "") : assert_41 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(source_ok, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(is_aligned, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_897 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_897, UInt<1>(0h1), "") : assert_44 node _T_901 = eq(io.in.a.bits.mask, mask) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_901, UInt<1>(0h1), "") : assert_45 node _T_905 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_905 : node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_908 = and(_T_906, _T_907) node _T_909 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_910 = shr(io.in.a.bits.source, 2) node _T_911 = eq(_T_910, UInt<5>(0h10)) node _T_912 = leq(UInt<1>(0h0), uncommonBits_60) node _T_913 = and(_T_911, _T_912) node _T_914 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_915 = and(_T_913, _T_914) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_916 = shr(io.in.a.bits.source, 2) node _T_917 = eq(_T_916, UInt<5>(0h11)) node _T_918 = leq(UInt<1>(0h0), uncommonBits_61) node _T_919 = and(_T_917, _T_918) node _T_920 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_921 = and(_T_919, _T_920) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_922 = shr(io.in.a.bits.source, 2) node _T_923 = eq(_T_922, UInt<5>(0h12)) node _T_924 = leq(UInt<1>(0h0), uncommonBits_62) node _T_925 = and(_T_923, _T_924) node _T_926 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_927 = and(_T_925, _T_926) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_928 = shr(io.in.a.bits.source, 2) node _T_929 = eq(_T_928, UInt<5>(0h13)) node _T_930 = leq(UInt<1>(0h0), uncommonBits_63) node _T_931 = and(_T_929, _T_930) node _T_932 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_933 = and(_T_931, _T_932) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_936 = shr(io.in.a.bits.source, 4) node _T_937 = eq(_T_936, UInt<1>(0h1)) node _T_938 = leq(UInt<1>(0h0), uncommonBits_64) node _T_939 = and(_T_937, _T_938) node _T_940 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_941 = and(_T_939, _T_940) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_942 = shr(io.in.a.bits.source, 4) node _T_943 = eq(_T_942, UInt<1>(0h0)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_65) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_947 = and(_T_945, _T_946) node _T_948 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_949 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_950 = or(_T_909, _T_915) node _T_951 = or(_T_950, _T_921) node _T_952 = or(_T_951, _T_927) node _T_953 = or(_T_952, _T_933) node _T_954 = or(_T_953, _T_934) node _T_955 = or(_T_954, _T_935) node _T_956 = or(_T_955, _T_941) node _T_957 = or(_T_956, _T_947) node _T_958 = or(_T_957, _T_948) node _T_959 = or(_T_958, _T_949) node _T_960 = and(_T_908, _T_959) node _T_961 = or(UInt<1>(0h0), _T_960) node _T_962 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_963 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_964 = cvt(_T_963) node _T_965 = and(_T_964, asSInt(UInt<17>(0h10000))) node _T_966 = asSInt(_T_965) node _T_967 = eq(_T_966, asSInt(UInt<1>(0h0))) node _T_968 = and(_T_962, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = and(_T_961, _T_969) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_970, UInt<1>(0h1), "") : assert_46 node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(is_aligned, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_980 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_980, UInt<1>(0h1), "") : assert_49 node _T_984 = eq(io.in.a.bits.mask, mask) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_984, UInt<1>(0h1), "") : assert_50 node _T_988 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_988, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_992 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_T_992, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_992, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_996 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_996 : node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(source_ok_1, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1000 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_54 node _T_1004 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_55 node _T_1008 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_56 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_57 node _T_1016 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1016 : node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(source_ok_1, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(sink_ok, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1023 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_60 node _T_1027 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_61 node _T_1031 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_62 node _T_1035 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_63 node _T_1039 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1040 = or(UInt<1>(0h0), _T_1039) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_64 node _T_1044 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1044 : node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(source_ok_1, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(sink_ok, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1051 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_67 node _T_1055 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_68 node _T_1059 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_69 node _T_1063 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1064 = or(_T_1063, io.in.d.bits.corrupt) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_70 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(UInt<1>(0h0), _T_1068) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_71 node _T_1073 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1073 : node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(source_ok_1, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1077 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_73 node _T_1081 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_74 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h0), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_75 node _T_1090 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_77 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_78 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h0), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_79 node _T_1108 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(source_ok_1, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_81 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_82 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h0), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1125 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1129 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1133 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1137 = eq(a_first, UInt<1>(0h0)) node _T_1138 = and(io.in.a.valid, _T_1137) when _T_1138 : node _T_1139 = eq(io.in.a.bits.opcode, opcode) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_87 node _T_1143 = eq(io.in.a.bits.param, param) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_88 node _T_1147 = eq(io.in.a.bits.size, size) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_89 node _T_1151 = eq(io.in.a.bits.source, source) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_90 node _T_1155 = eq(io.in.a.bits.address, address) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_91 node _T_1159 = and(io.in.a.ready, io.in.a.valid) node _T_1160 = and(_T_1159, a_first) when _T_1160 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1161 = eq(d_first, UInt<1>(0h0)) node _T_1162 = and(io.in.d.valid, _T_1161) when _T_1162 : node _T_1163 = eq(io.in.d.bits.opcode, opcode_1) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_92 node _T_1167 = eq(io.in.d.bits.param, param_1) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_93 node _T_1171 = eq(io.in.d.bits.size, size_1) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_94 node _T_1175 = eq(io.in.d.bits.source, source_1) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_95 node _T_1179 = eq(io.in.d.bits.sink, sink) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_96 node _T_1183 = eq(io.in.d.bits.denied, denied) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_97 node _T_1187 = and(io.in.d.ready, io.in.d.valid) node _T_1188 = and(_T_1187, d_first) when _T_1188 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1189 = and(io.in.a.valid, a_first_1) node _T_1190 = and(_T_1189, UInt<1>(0h1)) when _T_1190 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1191 = and(io.in.a.ready, io.in.a.valid) node _T_1192 = and(_T_1191, a_first_1) node _T_1193 = and(_T_1192, UInt<1>(0h1)) when _T_1193 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1194 = dshr(inflight, io.in.a.bits.source) node _T_1195 = bits(_T_1194, 0, 0) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1200 = and(io.in.d.valid, d_first_1) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = eq(d_release_ack, UInt<1>(0h0)) node _T_1203 = and(_T_1201, _T_1202) when _T_1203 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1204 = and(io.in.d.ready, io.in.d.valid) node _T_1205 = and(_T_1204, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1209 = and(io.in.d.valid, d_first_1) node _T_1210 = and(_T_1209, UInt<1>(0h1)) node _T_1211 = eq(d_release_ack, UInt<1>(0h0)) node _T_1212 = and(_T_1210, _T_1211) when _T_1212 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1213 = dshr(inflight, io.in.d.bits.source) node _T_1214 = bits(_T_1213, 0, 0) node _T_1215 = or(_T_1214, same_cycle_resp) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_100 node _T_1225 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_101 else : node _T_1229 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1230 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1231 = or(_T_1229, _T_1230) node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(_T_1231, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1231, UInt<1>(0h1), "") : assert_102 node _T_1235 = eq(io.in.d.bits.size, a_size_lookup) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_103 node _T_1239 = and(io.in.d.valid, d_first_1) node _T_1240 = and(_T_1239, a_first_1) node _T_1241 = and(_T_1240, io.in.a.valid) node _T_1242 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1243 = and(_T_1241, _T_1242) node _T_1244 = eq(d_release_ack, UInt<1>(0h0)) node _T_1245 = and(_T_1243, _T_1244) when _T_1245 : node _T_1246 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1247 = or(_T_1246, io.in.a.ready) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_56 node _T_1251 = orr(inflight) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) node _T_1253 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1254 = or(_T_1252, _T_1253) node _T_1255 = lt(watchdog, plusarg_reader.out) node _T_1256 = or(_T_1254, _T_1255) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1260 = and(io.in.a.ready, io.in.a.valid) node _T_1261 = and(io.in.d.ready, io.in.d.valid) node _T_1262 = or(_T_1260, _T_1261) when _T_1262 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1263 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1264 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1265 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = and(_T_1263, _T_1266) when _T_1267 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1268 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1269 = and(_T_1268, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1270 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1271 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1272 = and(_T_1270, _T_1271) node _T_1273 = and(_T_1269, _T_1272) when _T_1273 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1274 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1275 = bits(_T_1274, 0, 0) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(_T_1276, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1276, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1280 = and(io.in.d.valid, d_first_2) node _T_1281 = and(_T_1280, UInt<1>(0h1)) node _T_1282 = and(_T_1281, d_release_ack_1) when _T_1282 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1283 = and(io.in.d.ready, io.in.d.valid) node _T_1284 = and(_T_1283, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1287 = and(io.in.d.valid, d_first_2) node _T_1288 = and(_T_1287, UInt<1>(0h1)) node _T_1289 = and(_T_1288, d_release_ack_1) when _T_1289 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1290 = dshr(inflight_1, io.in.d.bits.source) node _T_1291 = bits(_T_1290, 0, 0) node _T_1292 = or(_T_1291, same_cycle_resp_1) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1296 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_108 else : node _T_1300 = eq(io.in.d.bits.size, c_size_lookup) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_109 node _T_1304 = and(io.in.d.valid, d_first_2) node _T_1305 = and(_T_1304, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1306 = and(_T_1305, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1307 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = and(_T_1308, d_release_ack_1) node _T_1310 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1311 = and(_T_1309, _T_1310) when _T_1311 : node _T_1312 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1313 = or(_T_1312, _WIRE_27.ready) node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(_T_1313, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1313, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_57 node _T_1317 = orr(inflight_1) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1320 = or(_T_1318, _T_1319) node _T_1321 = lt(watchdog_1, plusarg_reader_1.out) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1326 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1327 = and(io.in.d.ready, io.in.d.valid) node _T_1328 = or(_T_1326, _T_1327) when _T_1328 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_28( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire d_release_ack = 1'h0; // @[Monitor.scala:673:46] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [515:0] _inflight_opcodes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62] wire [515:0] _inflight_sizes_T_4 = 516'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58] wire [128:0] _inflight_T_4 = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74] wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [515:0] d_opcodes_clr_1 = 516'h0; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1 = 516'h0; // @[Monitor.scala:777:34] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [128:0] d_clr_1 = 129'h0; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1 = 129'h0; // @[Monitor.scala:775:34] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1260 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1260; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1260; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] wire _T_1328 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1328; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1328; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1328; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1193 = _T_1260 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1193 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1193 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1193 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1193 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1193 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _T_1239 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_4 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1239 ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1206 = _T_1328 & d_first_1; // @[Decoupled.scala:51:35] assign d_clr = _T_1206 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1206 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1206 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_33 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_33 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}} wire _in_flight_WIRE : UInt<1>[6] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_71 = and(_T_69, _T_70) node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_138 = and(_T_136, _T_137) node _T_139 = or(_T_12, _T_19) node _T_140 = or(_T_139, _T_26) node _T_141 = or(_T_140, _T_33) node _T_142 = or(_T_141, _T_40) node _T_143 = or(_T_142, _T_47) node _T_144 = or(_T_143, _T_54) node _T_145 = or(_T_144, _T_61) node _T_146 = or(_T_145, _T_68) node _T_147 = or(_T_146, _T_75) node _T_148 = or(_T_147, _T_82) node _T_149 = or(_T_148, _T_89) node _T_150 = or(_T_149, _T_96) node _T_151 = or(_T_150, _T_103) node _T_152 = or(_T_151, _T_110) node _T_153 = or(_T_152, _T_117) node _T_154 = or(_T_153, _T_124) node _T_155 = or(_T_154, _T_131) node _T_156 = or(_T_155, _T_138) node _T_157 = or(_T_5, _T_156) node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(_T_157, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_157, UInt<1>(0h1), "") : assert_1 node _T_161 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_163 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_170 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_177 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_184 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(_T_168, _T_175) node _T_191 = or(_T_190, _T_182) node _T_192 = or(_T_191, _T_189) node _T_193 = or(_T_161, _T_192) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_193, UInt<1>(0h1), "") : assert_2 node _T_197 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_199 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_206 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_213 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_214 = and(_T_212, _T_213) node _T_215 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_220 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_221 = and(_T_219, _T_220) node _T_222 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_227 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_234 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_241 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_248 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_249 = and(_T_247, _T_248) node _T_250 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_255 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_258 = and(_T_256, _T_257) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_262 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_263 = and(_T_261, _T_262) node _T_264 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_269 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_276 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_283 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_286 = and(_T_284, _T_285) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_290 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_291 = and(_T_289, _T_290) node _T_292 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_297 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_304 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_309 = and(_T_307, _T_308) node _T_310 = or(_T_204, _T_211) node _T_311 = or(_T_310, _T_218) node _T_312 = or(_T_311, _T_225) node _T_313 = or(_T_312, _T_232) node _T_314 = or(_T_313, _T_239) node _T_315 = or(_T_314, _T_246) node _T_316 = or(_T_315, _T_253) node _T_317 = or(_T_316, _T_260) node _T_318 = or(_T_317, _T_267) node _T_319 = or(_T_318, _T_274) node _T_320 = or(_T_319, _T_281) node _T_321 = or(_T_320, _T_288) node _T_322 = or(_T_321, _T_295) node _T_323 = or(_T_322, _T_302) node _T_324 = or(_T_323, _T_309) node _T_325 = or(_T_197, _T_324) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_325, UInt<1>(0h1), "") : assert_3 node _T_329 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_339 = and(_T_337, _T_338) node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_346 = and(_T_344, _T_345) node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_352 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_353 = and(_T_351, _T_352) node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_355 = and(_T_353, _T_354) node _T_356 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_362 = and(_T_360, _T_361) node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_364 = and(_T_362, _T_363) node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_369 = and(_T_367, _T_368) node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_371 = and(_T_369, _T_370) node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_376 = and(_T_374, _T_375) node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_385 = and(_T_383, _T_384) node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_387 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_392 = and(_T_390, _T_391) node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_394 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_399 = and(_T_397, _T_398) node _T_400 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_401 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_406 = and(_T_404, _T_405) node _T_407 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_408 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_411 = and(_T_409, _T_410) node _T_412 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_415 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_420 = and(_T_418, _T_419) node _T_421 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_422 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_425 = and(_T_423, _T_424) node _T_426 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_427 = and(_T_425, _T_426) node _T_428 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_429 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_436 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_439 = and(_T_437, _T_438) node _T_440 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_443 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_446 = and(_T_444, _T_445) node _T_447 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_450 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_453 = and(_T_451, _T_452) node _T_454 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_457 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_460 = and(_T_458, _T_459) node _T_461 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_464 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_467 = and(_T_465, _T_466) node _T_468 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(_T_336, _T_343) node _T_471 = or(_T_470, _T_350) node _T_472 = or(_T_471, _T_357) node _T_473 = or(_T_472, _T_364) node _T_474 = or(_T_473, _T_371) node _T_475 = or(_T_474, _T_378) node _T_476 = or(_T_475, _T_385) node _T_477 = or(_T_476, _T_392) node _T_478 = or(_T_477, _T_399) node _T_479 = or(_T_478, _T_406) node _T_480 = or(_T_479, _T_413) node _T_481 = or(_T_480, _T_420) node _T_482 = or(_T_481, _T_427) node _T_483 = or(_T_482, _T_434) node _T_484 = or(_T_483, _T_441) node _T_485 = or(_T_484, _T_448) node _T_486 = or(_T_485, _T_455) node _T_487 = or(_T_486, _T_462) node _T_488 = or(_T_487, _T_469) node _T_489 = or(_T_329, _T_488) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_489, UInt<1>(0h1), "") : assert_4 node _T_493 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_494 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_495 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_500 = and(_T_498, _T_499) node _T_501 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_502 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_509 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_512 = and(_T_510, _T_511) node _T_513 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_514 = and(_T_512, _T_513) node _T_515 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_516 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_519 = and(_T_517, _T_518) node _T_520 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_523 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_526 = and(_T_524, _T_525) node _T_527 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_528 = and(_T_526, _T_527) node _T_529 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_530 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_535 = and(_T_533, _T_534) node _T_536 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_537 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_540 = and(_T_538, _T_539) node _T_541 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_542 = and(_T_540, _T_541) node _T_543 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_544 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_551 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_558 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_559 = and(_T_557, _T_558) node _T_560 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_561 = and(_T_559, _T_560) node _T_562 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_565 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_566 = and(_T_564, _T_565) node _T_567 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_570 = and(_T_568, _T_569) node _T_571 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_572 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_573 = and(_T_571, _T_572) node _T_574 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_575 = and(_T_573, _T_574) node _T_576 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_577 = and(_T_575, _T_576) node _T_578 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_579 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_580 = and(_T_578, _T_579) node _T_581 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_582 = and(_T_580, _T_581) node _T_583 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_586 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_587 = and(_T_585, _T_586) node _T_588 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_589 = and(_T_587, _T_588) node _T_590 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_591 = and(_T_589, _T_590) node _T_592 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_593 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_596 = and(_T_594, _T_595) node _T_597 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_600 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_601 = and(_T_599, _T_600) node _T_602 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_605 = and(_T_603, _T_604) node _T_606 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_607 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_608 = and(_T_606, _T_607) node _T_609 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_612 = and(_T_610, _T_611) node _T_613 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_614 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) node _T_618 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_621 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_622 = and(_T_620, _T_621) node _T_623 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_624 = and(_T_622, _T_623) node _T_625 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_628 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_629 = and(_T_627, _T_628) node _T_630 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_631 = and(_T_629, _T_630) node _T_632 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(_T_500, _T_507) node _T_635 = or(_T_634, _T_514) node _T_636 = or(_T_635, _T_521) node _T_637 = or(_T_636, _T_528) node _T_638 = or(_T_637, _T_535) node _T_639 = or(_T_638, _T_542) node _T_640 = or(_T_639, _T_549) node _T_641 = or(_T_640, _T_556) node _T_642 = or(_T_641, _T_563) node _T_643 = or(_T_642, _T_570) node _T_644 = or(_T_643, _T_577) node _T_645 = or(_T_644, _T_584) node _T_646 = or(_T_645, _T_591) node _T_647 = or(_T_646, _T_598) node _T_648 = or(_T_647, _T_605) node _T_649 = or(_T_648, _T_612) node _T_650 = or(_T_649, _T_619) node _T_651 = or(_T_650, _T_626) node _T_652 = or(_T_651, _T_633) node _T_653 = or(_T_493, _T_652) node _T_654 = asUInt(reset) node _T_655 = eq(_T_654, UInt<1>(0h0)) when _T_655 : node _T_656 = eq(_T_653, UInt<1>(0h0)) when _T_656 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_653, UInt<1>(0h1), "") : assert_5 node _T_657 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_658 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_659 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_660 = and(_T_658, _T_659) node _T_661 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_662 = and(_T_660, _T_661) node _T_663 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_664 = and(_T_662, _T_663) node _T_665 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_666 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_667 = and(_T_665, _T_666) node _T_668 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_669 = and(_T_667, _T_668) node _T_670 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_671 = and(_T_669, _T_670) node _T_672 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_673 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_674 = and(_T_672, _T_673) node _T_675 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_676 = and(_T_674, _T_675) node _T_677 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_678 = and(_T_676, _T_677) node _T_679 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_680 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_681 = and(_T_679, _T_680) node _T_682 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_685 = and(_T_683, _T_684) node _T_686 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_687 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_688 = and(_T_686, _T_687) node _T_689 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_690 = and(_T_688, _T_689) node _T_691 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_692 = and(_T_690, _T_691) node _T_693 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_694 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_695 = and(_T_693, _T_694) node _T_696 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_701 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_702 = and(_T_700, _T_701) node _T_703 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_704 = and(_T_702, _T_703) node _T_705 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_706 = and(_T_704, _T_705) node _T_707 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_708 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_709 = and(_T_707, _T_708) node _T_710 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_715 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_716 = and(_T_714, _T_715) node _T_717 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_718 = and(_T_716, _T_717) node _T_719 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_720 = and(_T_718, _T_719) node _T_721 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_722 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_727 = and(_T_725, _T_726) node _T_728 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_729 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_730 = and(_T_728, _T_729) node _T_731 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_734 = and(_T_732, _T_733) node _T_735 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_736 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_737 = and(_T_735, _T_736) node _T_738 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_741 = and(_T_739, _T_740) node _T_742 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_743 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_744 = and(_T_742, _T_743) node _T_745 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_746 = and(_T_744, _T_745) node _T_747 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_750 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _T_752 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_753 = and(_T_751, _T_752) node _T_754 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_755 = and(_T_753, _T_754) node _T_756 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_757 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_760 = and(_T_758, _T_759) node _T_761 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_762 = and(_T_760, _T_761) node _T_763 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_764 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_765 = and(_T_763, _T_764) node _T_766 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_767 = and(_T_765, _T_766) node _T_768 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_769 = and(_T_767, _T_768) node _T_770 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_771 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_774 = and(_T_772, _T_773) node _T_775 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_776 = and(_T_774, _T_775) node _T_777 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_778 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_779 = and(_T_777, _T_778) node _T_780 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_781 = and(_T_779, _T_780) node _T_782 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) node _T_784 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_785 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_786 = and(_T_784, _T_785) node _T_787 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_788 = and(_T_786, _T_787) node _T_789 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_790 = and(_T_788, _T_789) node _T_791 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_792 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_797 = and(_T_795, _T_796) node _T_798 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_799 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_800 = and(_T_798, _T_799) node _T_801 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) node _T_803 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_804 = and(_T_802, _T_803) node _T_805 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_806 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_809 = and(_T_807, _T_808) node _T_810 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_811 = and(_T_809, _T_810) node _T_812 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_813 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_816 = and(_T_814, _T_815) node _T_817 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_820 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_821 = and(_T_819, _T_820) node _T_822 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_823 = and(_T_821, _T_822) node _T_824 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_825 = and(_T_823, _T_824) node _T_826 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_827 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_830 = and(_T_828, _T_829) node _T_831 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_832 = and(_T_830, _T_831) node _T_833 = or(_T_664, _T_671) node _T_834 = or(_T_833, _T_678) node _T_835 = or(_T_834, _T_685) node _T_836 = or(_T_835, _T_692) node _T_837 = or(_T_836, _T_699) node _T_838 = or(_T_837, _T_706) node _T_839 = or(_T_838, _T_713) node _T_840 = or(_T_839, _T_720) node _T_841 = or(_T_840, _T_727) node _T_842 = or(_T_841, _T_734) node _T_843 = or(_T_842, _T_741) node _T_844 = or(_T_843, _T_748) node _T_845 = or(_T_844, _T_755) node _T_846 = or(_T_845, _T_762) node _T_847 = or(_T_846, _T_769) node _T_848 = or(_T_847, _T_776) node _T_849 = or(_T_848, _T_783) node _T_850 = or(_T_849, _T_790) node _T_851 = or(_T_850, _T_797) node _T_852 = or(_T_851, _T_804) node _T_853 = or(_T_852, _T_811) node _T_854 = or(_T_853, _T_818) node _T_855 = or(_T_854, _T_825) node _T_856 = or(_T_855, _T_832) node _T_857 = or(_T_657, _T_856) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_857, UInt<1>(0h1), "") : assert_6

module NoCMonitor_5( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_41 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_87 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_41 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} input tick : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst clint of CLINT connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 connect intsource.clock, childClock connect intsource.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn connect intsource.auto.in[0], clint.auto.int_out[0] connect intsource.auto.in[1], clint.auto.int_out[1] connect intInClockXingIn, intsource.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out, intInClockXingOut connect clint.auto.in, auto.clint_in connect clint.io.rtcTick, tick connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_103 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_104 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_sync_1, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input tick, // @[CLINT.scala:115:20] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _clint_auto_int_out_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1; // @[CLINT.scala:112:48] CLINT clint ( // @[CLINT.scala:112:48] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_out_0 (_clint_auto_int_out_0), .auto_int_out_1 (_clint_auto_int_out_1), .auto_in_a_ready (auto_clint_in_a_ready), .auto_in_a_valid (auto_clint_in_a_valid), .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode), .auto_in_a_bits_param (auto_clint_in_a_bits_param), .auto_in_a_bits_size (auto_clint_in_a_bits_size), .auto_in_a_bits_source (auto_clint_in_a_bits_source), .auto_in_a_bits_address (auto_clint_in_a_bits_address), .auto_in_a_bits_mask (auto_clint_in_a_bits_mask), .auto_in_a_bits_data (auto_clint_in_a_bits_data), .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt), .auto_in_d_ready (auto_clint_in_d_ready), .auto_in_d_valid (auto_clint_in_d_valid), .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode), .auto_in_d_bits_size (auto_clint_in_d_bits_size), .auto_in_d_bits_source (auto_clint_in_d_bits_source), .auto_in_d_bits_data (auto_clint_in_d_bits_data), .io_rtcTick (tick) ); // @[CLINT.scala:112:48] IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_0 (_clint_auto_int_out_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (auto_int_in_clock_xing_out_sync_0), .auto_out_sync_1 (auto_int_in_clock_xing_out_sync_1) ); // @[Crossing.scala:29:31] assign clock = auto_clock_in_clock; // @[ClockDomain.scala:14:9] assign reset = auto_clock_in_reset; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_52 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_52 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}[1], flip in_b : { bits : UInt<32>}[1], flip in_d : { bits : UInt<32>}[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<4>[1], flip in_last : UInt<1>[1], out_a : { bits : UInt<32>}[1], out_c : { bits : UInt<32>}[1], out_b : { bits : UInt<32>}[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<4>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_16 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a.bits, io.in_a[0].bits connect tile_0_0.io.in_b.bits, io.in_b[0].bits connect tile_0_0.io.in_d.bits, io.in_d[0].bits connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14] input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [3:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14] output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [3:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7] wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7] wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_16 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7] .io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7] .io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7] .io_out_a_bits (io_out_a_0_bits_0), .io_out_b_bits (io_out_b_0_bits_0), .io_out_c_bits (io_out_c_0_bits_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7] assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7] assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_48 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_48( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready

module TLBuffer_a32d64s2k3z4c_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [31:0] _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21] wire [7:0] _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21] wire _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_b_ready (auto_in_b_ready), .io_in_b_valid (_nodeIn_b_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address), // @[Decoupled.scala:362:21] .io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask), // @[Decoupled.scala:362:21] .io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21] .io_in_c_ready (_nodeOut_c_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_c_valid (auto_in_c_valid), .io_in_c_bits_opcode (auto_in_c_bits_opcode), .io_in_c_bits_param (auto_in_c_bits_param), .io_in_c_bits_size (auto_in_c_bits_size), .io_in_c_bits_source (auto_in_c_bits_source), .io_in_c_bits_address (auto_in_c_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21] .io_in_e_ready (_nodeOut_e_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_e_valid (auto_in_e_valid), .io_in_e_bits_sink (auto_in_e_bits_sink) ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_b_ready), .io_enq_valid (auto_out_b_valid), .io_enq_bits_param (auto_out_b_bits_param), .io_enq_bits_address (auto_out_b_bits_address), .io_deq_ready (auto_in_b_ready), .io_deq_valid (_nodeIn_b_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source), .io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address), .io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask), .io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_c_q_io_enq_ready), .io_enq_valid (auto_in_c_valid), .io_enq_bits_opcode (auto_in_c_bits_opcode), .io_enq_bits_param (auto_in_c_bits_param), .io_enq_bits_size (auto_in_c_bits_size), .io_enq_bits_source (auto_in_c_bits_source), .io_enq_bits_address (auto_in_c_bits_address), .io_enq_bits_data (auto_in_c_bits_data), .io_deq_ready (auto_out_c_ready), .io_deq_valid (auto_out_c_valid), .io_deq_bits_opcode (auto_out_c_bits_opcode), .io_deq_bits_param (auto_out_c_bits_param), .io_deq_bits_size (auto_out_c_bits_size), .io_deq_bits_source (auto_out_c_bits_source), .io_deq_bits_address (auto_out_c_bits_address), .io_deq_bits_data (auto_out_c_bits_data), .io_deq_bits_corrupt (auto_out_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_e_q_io_enq_ready), .io_enq_valid (auto_in_e_valid), .io_enq_bits_sink (auto_in_e_bits_sink), .io_deq_valid (auto_out_e_valid), .io_deq_bits_sink (auto_out_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21] assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21] assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<19>(0h40000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_78 = or(UInt<1>(0h0), _T_77) node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = and(_T_78, _T_89) node _T_91 = or(UInt<1>(0h0), _T_76) node _T_92 = or(_T_91, _T_90) node _T_93 = and(_T_21, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_93, UInt<1>(0h1), "") : assert_2 node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(UInt<1>(0h0), _T_99) node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<19>(0h40000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_105, _T_110) node _T_157 = or(_T_156, _T_115) node _T_158 = or(_T_157, _T_120) node _T_159 = or(_T_158, _T_125) node _T_160 = or(_T_159, _T_130) node _T_161 = or(_T_160, _T_135) node _T_162 = or(_T_161, _T_140) node _T_163 = or(_T_162, _T_145) node _T_164 = or(_T_163, _T_150) node _T_165 = or(_T_164, _T_155) node _T_166 = and(_T_100, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(UInt<1>(0h0), _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_168, UInt<1>(0h1), "") : assert_3 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_175 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_175, UInt<1>(0h1), "") : assert_5 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(is_aligned, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_183 = asUInt(reset) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : node _T_185 = eq(_T_182, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_182, UInt<1>(0h1), "") : assert_7 node _T_186 = not(io.in.a.bits.mask) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_187, UInt<1>(0h1), "") : assert_8 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_191, UInt<1>(0h1), "") : assert_9 node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_239 = cvt(_T_238) node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000))) node _T_241 = asSInt(_T_240) node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<19>(0h40000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = or(_T_207, _T_212) node _T_249 = or(_T_248, _T_217) node _T_250 = or(_T_249, _T_222) node _T_251 = or(_T_250, _T_227) node _T_252 = or(_T_251, _T_232) node _T_253 = or(_T_252, _T_237) node _T_254 = or(_T_253, _T_242) node _T_255 = or(_T_254, _T_247) node _T_256 = and(_T_202, _T_255) node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = or(_T_263, _T_268) node _T_270 = and(_T_258, _T_269) node _T_271 = or(UInt<1>(0h0), _T_256) node _T_272 = or(_T_271, _T_270) node _T_273 = and(_T_201, _T_272) node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_T_273, UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_273, UInt<1>(0h1), "") : assert_10 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<19>(0h40000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = or(_T_285, _T_290) node _T_337 = or(_T_336, _T_295) node _T_338 = or(_T_337, _T_300) node _T_339 = or(_T_338, _T_305) node _T_340 = or(_T_339, _T_310) node _T_341 = or(_T_340, _T_315) node _T_342 = or(_T_341, _T_320) node _T_343 = or(_T_342, _T_325) node _T_344 = or(_T_343, _T_330) node _T_345 = or(_T_344, _T_335) node _T_346 = and(_T_280, _T_345) node _T_347 = or(UInt<1>(0h0), _T_346) node _T_348 = and(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_348, UInt<1>(0h1), "") : assert_11 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_355, UInt<1>(0h1), "") : assert_13 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(is_aligned, UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_362, UInt<1>(0h1), "") : assert_15 node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_366, UInt<1>(0h1), "") : assert_16 node _T_370 = not(io.in.a.bits.mask) node _T_371 = eq(_T_370, UInt<1>(0h0)) node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_T_371, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_371, UInt<1>(0h1), "") : assert_17 node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_375, UInt<1>(0h1), "") : assert_18 node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_379 : node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) node _T_385 = or(UInt<1>(0h0), _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_385, UInt<1>(0h1), "") : assert_19 node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_391 = and(_T_389, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_394 = cvt(_T_393) node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000))) node _T_396 = asSInt(_T_395) node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0))) node _T_398 = and(_T_392, _T_397) node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_401 = and(_T_399, _T_400) node _T_402 = or(UInt<1>(0h0), _T_401) node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_404 = cvt(_T_403) node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000))) node _T_406 = asSInt(_T_405) node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0))) node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_409 = cvt(_T_408) node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000))) node _T_411 = asSInt(_T_410) node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0))) node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_414 = cvt(_T_413) node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000))) node _T_416 = asSInt(_T_415) node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0))) node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_419 = cvt(_T_418) node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000))) node _T_421 = asSInt(_T_420) node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0))) node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_424 = cvt(_T_423) node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000))) node _T_426 = asSInt(_T_425) node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0))) node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_429 = cvt(_T_428) node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000))) node _T_431 = asSInt(_T_430) node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0))) node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_434 = cvt(_T_433) node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000))) node _T_436 = asSInt(_T_435) node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0))) node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_439 = cvt(_T_438) node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000))) node _T_441 = asSInt(_T_440) node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0))) node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_444 = cvt(_T_443) node _T_445 = and(_T_444, asSInt(UInt<19>(0h40000))) node _T_446 = asSInt(_T_445) node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0))) node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = or(_T_407, _T_412) node _T_454 = or(_T_453, _T_417) node _T_455 = or(_T_454, _T_422) node _T_456 = or(_T_455, _T_427) node _T_457 = or(_T_456, _T_432) node _T_458 = or(_T_457, _T_437) node _T_459 = or(_T_458, _T_442) node _T_460 = or(_T_459, _T_447) node _T_461 = or(_T_460, _T_452) node _T_462 = and(_T_402, _T_461) node _T_463 = or(UInt<1>(0h0), _T_398) node _T_464 = or(_T_463, _T_462) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_464, UInt<1>(0h1), "") : assert_20 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_471 = asUInt(reset) node _T_472 = eq(_T_471, UInt<1>(0h0)) when _T_472 : node _T_473 = eq(is_aligned, UInt<1>(0h0)) when _T_473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_474, UInt<1>(0h1), "") : assert_23 node _T_478 = eq(io.in.a.bits.mask, mask) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_478, UInt<1>(0h1), "") : assert_24 node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_482, UInt<1>(0h1), "") : assert_25 node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_486 : node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_489 = and(_T_487, _T_488) node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_491 = and(_T_489, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(UInt<1>(0h0), _T_495) node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = and(_T_496, _T_501) node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_505 = and(_T_503, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<19>(0h40000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = or(_T_511, _T_516) node _T_553 = or(_T_552, _T_521) node _T_554 = or(_T_553, _T_526) node _T_555 = or(_T_554, _T_531) node _T_556 = or(_T_555, _T_536) node _T_557 = or(_T_556, _T_541) node _T_558 = or(_T_557, _T_546) node _T_559 = or(_T_558, _T_551) node _T_560 = and(_T_506, _T_559) node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = and(_T_561, _T_566) node _T_568 = or(UInt<1>(0h0), _T_502) node _T_569 = or(_T_568, _T_560) node _T_570 = or(_T_569, _T_567) node _T_571 = and(_T_492, _T_570) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_571, UInt<1>(0h1), "") : assert_26 node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(is_aligned, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_581, UInt<1>(0h1), "") : assert_29 node _T_585 = eq(io.in.a.bits.mask, mask) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_585, UInt<1>(0h1), "") : assert_30 node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_589 : node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_594 = and(_T_592, _T_593) node _T_595 = or(UInt<1>(0h0), _T_594) node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = or(UInt<1>(0h0), _T_598) node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_601 = cvt(_T_600) node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000))) node _T_603 = asSInt(_T_602) node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0))) node _T_605 = and(_T_599, _T_604) node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(UInt<1>(0h0), _T_608) node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<19>(0h40000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = or(_T_614, _T_619) node _T_656 = or(_T_655, _T_624) node _T_657 = or(_T_656, _T_629) node _T_658 = or(_T_657, _T_634) node _T_659 = or(_T_658, _T_639) node _T_660 = or(_T_659, _T_644) node _T_661 = or(_T_660, _T_649) node _T_662 = or(_T_661, _T_654) node _T_663 = and(_T_609, _T_662) node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = and(_T_664, _T_669) node _T_671 = or(UInt<1>(0h0), _T_605) node _T_672 = or(_T_671, _T_663) node _T_673 = or(_T_672, _T_670) node _T_674 = and(_T_595, _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_674, UInt<1>(0h1), "") : assert_31 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(is_aligned, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(_T_684, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_684, UInt<1>(0h1), "") : assert_34 node _T_688 = not(mask) node _T_689 = and(io.in.a.bits.mask, _T_688) node _T_690 = eq(_T_689, UInt<1>(0h0)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_690, UInt<1>(0h1), "") : assert_35 node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_699 = and(_T_697, _T_698) node _T_700 = or(UInt<1>(0h0), _T_699) node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_721 = cvt(_T_720) node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000))) node _T_723 = asSInt(_T_722) node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0))) node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_726 = cvt(_T_725) node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000))) node _T_728 = asSInt(_T_727) node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0))) node _T_730 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_731 = cvt(_T_730) node _T_732 = and(_T_731, asSInt(UInt<17>(0h10000))) node _T_733 = asSInt(_T_732) node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0))) node _T_735 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_736 = cvt(_T_735) node _T_737 = and(_T_736, asSInt(UInt<27>(0h4000000))) node _T_738 = asSInt(_T_737) node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0))) node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<19>(0h40000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<29>(0h10000000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = or(_T_709, _T_714) node _T_756 = or(_T_755, _T_719) node _T_757 = or(_T_756, _T_724) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_734) node _T_760 = or(_T_759, _T_739) node _T_761 = or(_T_760, _T_744) node _T_762 = or(_T_761, _T_749) node _T_763 = or(_T_762, _T_754) node _T_764 = and(_T_704, _T_763) node _T_765 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = and(_T_765, _T_770) node _T_772 = or(UInt<1>(0h0), _T_764) node _T_773 = or(_T_772, _T_771) node _T_774 = and(_T_700, _T_773) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_774, UInt<1>(0h1), "") : assert_36 node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(is_aligned, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_784 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_784, UInt<1>(0h1), "") : assert_39 node _T_788 = eq(io.in.a.bits.mask, mask) node _T_789 = asUInt(reset) node _T_790 = eq(_T_789, UInt<1>(0h0)) when _T_790 : node _T_791 = eq(_T_788, UInt<1>(0h0)) when _T_791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_788, UInt<1>(0h1), "") : assert_40 node _T_792 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_792 : node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_797 = and(_T_795, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_800 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_801 = and(_T_799, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<14>(0h2000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<13>(0h1000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<18>(0h2f000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<17>(0h10000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<13>(0h1000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<17>(0h10000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_834 = cvt(_T_833) node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000))) node _T_836 = asSInt(_T_835) node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<19>(0h40000))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_849 = cvt(_T_848) node _T_850 = and(_T_849, asSInt(UInt<29>(0h10000000))) node _T_851 = asSInt(_T_850) node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) node _T_853 = or(_T_807, _T_812) node _T_854 = or(_T_853, _T_817) node _T_855 = or(_T_854, _T_822) node _T_856 = or(_T_855, _T_827) node _T_857 = or(_T_856, _T_832) node _T_858 = or(_T_857, _T_837) node _T_859 = or(_T_858, _T_842) node _T_860 = or(_T_859, _T_847) node _T_861 = or(_T_860, _T_852) node _T_862 = and(_T_802, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = and(_T_863, _T_868) node _T_870 = or(UInt<1>(0h0), _T_862) node _T_871 = or(_T_870, _T_869) node _T_872 = and(_T_798, _T_871) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_872, UInt<1>(0h1), "") : assert_41 node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(is_aligned, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_882 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_882, UInt<1>(0h1), "") : assert_44 node _T_886 = eq(io.in.a.bits.mask, mask) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_886, UInt<1>(0h1), "") : assert_45 node _T_890 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_890 : node _T_891 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_892 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_893 = and(_T_891, _T_892) node _T_894 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_895 = and(_T_893, _T_894) node _T_896 = or(UInt<1>(0h0), _T_895) node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_898 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_899 = and(_T_897, _T_898) node _T_900 = or(UInt<1>(0h0), _T_899) node _T_901 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = and(_T_900, _T_905) node _T_907 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_908 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_909 = cvt(_T_908) node _T_910 = and(_T_909, asSInt(UInt<14>(0h2000))) node _T_911 = asSInt(_T_910) node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0))) node _T_913 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<17>(0h10000))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<18>(0h2f000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_924 = cvt(_T_923) node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000))) node _T_926 = asSInt(_T_925) node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0))) node _T_928 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_929 = cvt(_T_928) node _T_930 = and(_T_929, asSInt(UInt<13>(0h1000))) node _T_931 = asSInt(_T_930) node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0))) node _T_933 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_934 = cvt(_T_933) node _T_935 = and(_T_934, asSInt(UInt<27>(0h4000000))) node _T_936 = asSInt(_T_935) node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0))) node _T_938 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_939 = cvt(_T_938) node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000))) node _T_941 = asSInt(_T_940) node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0))) node _T_943 = xor(io.in.a.bits.address, UInt<29>(0h10040000)) node _T_944 = cvt(_T_943) node _T_945 = and(_T_944, asSInt(UInt<19>(0h40000))) node _T_946 = asSInt(_T_945) node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0))) node _T_948 = or(_T_912, _T_917) node _T_949 = or(_T_948, _T_922) node _T_950 = or(_T_949, _T_927) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_937) node _T_953 = or(_T_952, _T_942) node _T_954 = or(_T_953, _T_947) node _T_955 = and(_T_907, _T_954) node _T_956 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_957 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_958 = and(_T_956, _T_957) node _T_959 = or(UInt<1>(0h0), _T_958) node _T_960 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_961 = cvt(_T_960) node _T_962 = and(_T_961, asSInt(UInt<17>(0h10000))) node _T_963 = asSInt(_T_962) node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0))) node _T_965 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_966 = cvt(_T_965) node _T_967 = and(_T_966, asSInt(UInt<29>(0h10000000))) node _T_968 = asSInt(_T_967) node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0))) node _T_970 = or(_T_964, _T_969) node _T_971 = and(_T_959, _T_970) node _T_972 = or(UInt<1>(0h0), _T_906) node _T_973 = or(_T_972, _T_955) node _T_974 = or(_T_973, _T_971) node _T_975 = and(_T_896, _T_974) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_975, UInt<1>(0h1), "") : assert_46 node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(is_aligned, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_985 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_985, UInt<1>(0h1), "") : assert_49 node _T_989 = eq(io.in.a.bits.mask, mask) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_989, UInt<1>(0h1), "") : assert_50 node _T_993 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_993, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_997 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_997, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1001 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1001 : node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_54 node _T_1009 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_55 node _T_1013 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_56 node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_57 node _T_1021 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1021 : node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(sink_ok, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1028 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_60 node _T_1032 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_61 node _T_1036 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_62 node _T_1040 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_63 node _T_1044 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1045 = or(UInt<1>(0h1), _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_64 node _T_1049 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1049 : node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(sink_ok, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1056 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_67 node _T_1060 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_68 node _T_1064 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_69 node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1069 = or(_T_1068, io.in.d.bits.corrupt) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_70 node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1074 = or(UInt<1>(0h1), _T_1073) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_71 node _T_1078 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1078 : node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_73 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_74 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = or(UInt<1>(0h1), _T_1090) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_75 node _T_1095 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1095 : node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1099 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_77 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(_T_1103, io.in.d.bits.corrupt) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_78 node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1109 = or(UInt<1>(0h1), _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_79 node _T_1113 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1117 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_81 node _T_1121 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_82 node _T_1125 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1126 = or(UInt<1>(0h1), _T_1125) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1130 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1134 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1138 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1142 = eq(a_first, UInt<1>(0h0)) node _T_1143 = and(io.in.a.valid, _T_1142) when _T_1143 : node _T_1144 = eq(io.in.a.bits.opcode, opcode) node _T_1145 = asUInt(reset) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(_T_1144, UInt<1>(0h0)) when _T_1147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1144, UInt<1>(0h1), "") : assert_87 node _T_1148 = eq(io.in.a.bits.param, param) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_88 node _T_1152 = eq(io.in.a.bits.size, size) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_89 node _T_1156 = eq(io.in.a.bits.source, source) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_90 node _T_1160 = eq(io.in.a.bits.address, address) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_91 node _T_1164 = and(io.in.a.ready, io.in.a.valid) node _T_1165 = and(_T_1164, a_first) when _T_1165 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1166 = eq(d_first, UInt<1>(0h0)) node _T_1167 = and(io.in.d.valid, _T_1166) when _T_1167 : node _T_1168 = eq(io.in.d.bits.opcode, opcode_1) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_92 node _T_1172 = eq(io.in.d.bits.param, param_1) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_93 node _T_1176 = eq(io.in.d.bits.size, size_1) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_94 node _T_1180 = eq(io.in.d.bits.source, source_1) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_95 node _T_1184 = eq(io.in.d.bits.sink, sink) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_96 node _T_1188 = eq(io.in.d.bits.denied, denied) node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(_T_1188, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1188, UInt<1>(0h1), "") : assert_97 node _T_1192 = and(io.in.d.ready, io.in.d.valid) node _T_1193 = and(_T_1192, d_first) when _T_1193 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1194 = and(io.in.a.valid, a_first_1) node _T_1195 = and(_T_1194, UInt<1>(0h1)) when _T_1195 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1196 = and(io.in.a.ready, io.in.a.valid) node _T_1197 = and(_T_1196, a_first_1) node _T_1198 = and(_T_1197, UInt<1>(0h1)) when _T_1198 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1199 = dshr(inflight, io.in.a.bits.source) node _T_1200 = bits(_T_1199, 0, 0) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1205 = and(io.in.d.valid, d_first_1) node _T_1206 = and(_T_1205, UInt<1>(0h1)) node _T_1207 = eq(d_release_ack, UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) when _T_1208 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1209 = and(io.in.d.ready, io.in.d.valid) node _T_1210 = and(_T_1209, d_first_1) node _T_1211 = and(_T_1210, UInt<1>(0h1)) node _T_1212 = eq(d_release_ack, UInt<1>(0h0)) node _T_1213 = and(_T_1211, _T_1212) when _T_1213 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1214 = and(io.in.d.valid, d_first_1) node _T_1215 = and(_T_1214, UInt<1>(0h1)) node _T_1216 = eq(d_release_ack, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1218 = dshr(inflight, io.in.d.bits.source) node _T_1219 = bits(_T_1218, 0, 0) node _T_1220 = or(_T_1219, same_cycle_resp) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1224 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1225 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1226 = or(_T_1224, _T_1225) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_100 node _T_1230 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_101 else : node _T_1234 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1236 = or(_T_1234, _T_1235) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_102 node _T_1240 = eq(io.in.d.bits.size, a_size_lookup) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_103 node _T_1244 = and(io.in.d.valid, d_first_1) node _T_1245 = and(_T_1244, a_first_1) node _T_1246 = and(_T_1245, io.in.a.valid) node _T_1247 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = eq(d_release_ack, UInt<1>(0h0)) node _T_1250 = and(_T_1248, _T_1249) when _T_1250 : node _T_1251 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1252 = or(_T_1251, io.in.a.ready) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_104 node _T_1256 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1257 = orr(a_set_wo_ready) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) node _T_1259 = or(_T_1256, _T_1258) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_1263 = orr(inflight) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1266 = or(_T_1264, _T_1265) node _T_1267 = lt(watchdog, plusarg_reader.out) node _T_1268 = or(_T_1266, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1272 = and(io.in.a.ready, io.in.a.valid) node _T_1273 = and(io.in.d.ready, io.in.d.valid) node _T_1274 = or(_T_1272, _T_1273) when _T_1274 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1275 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1276 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1277 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1275, _T_1278) when _T_1279 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1280 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1281 = and(_T_1280, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1282 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1283 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1284 = and(_T_1282, _T_1283) node _T_1285 = and(_T_1281, _T_1284) when _T_1285 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1286 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1287 = bits(_T_1286, 0, 0) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1292 = and(io.in.d.valid, d_first_2) node _T_1293 = and(_T_1292, UInt<1>(0h1)) node _T_1294 = and(_T_1293, d_release_ack_1) when _T_1294 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1295 = and(io.in.d.ready, io.in.d.valid) node _T_1296 = and(_T_1295, d_first_2) node _T_1297 = and(_T_1296, UInt<1>(0h1)) node _T_1298 = and(_T_1297, d_release_ack_1) when _T_1298 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1299 = and(io.in.d.valid, d_first_2) node _T_1300 = and(_T_1299, UInt<1>(0h1)) node _T_1301 = and(_T_1300, d_release_ack_1) when _T_1301 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1302 = dshr(inflight_1, io.in.d.bits.source) node _T_1303 = bits(_T_1302, 0, 0) node _T_1304 = or(_T_1303, same_cycle_resp_1) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1308 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_109 else : node _T_1312 = eq(io.in.d.bits.size, c_size_lookup) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110 node _T_1316 = and(io.in.d.valid, d_first_2) node _T_1317 = and(_T_1316, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1318 = and(_T_1317, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1319 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = and(_T_1320, d_release_ack_1) node _T_1322 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1323 = and(_T_1321, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1325 = or(_T_1324, _WIRE_23.ready) node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(_T_1325, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1325, UInt<1>(0h1), "") : assert_111 node _T_1329 = orr(c_set_wo_ready) when _T_1329 : node _T_1330 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_1334 = orr(inflight_1) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) node _T_1336 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1337 = or(_T_1335, _T_1336) node _T_1338 = lt(watchdog_1, plusarg_reader_1.out) node _T_1339 = or(_T_1337, _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1343 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1344 = and(io.in.d.ready, io.in.d.valid) node _T_1345 = or(_T_1343, _T_1344) when _T_1345 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_451 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_451( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_116 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_116( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_170 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_170( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Router_13 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_13 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_30 of InputUnit_13 connect input_unit_0_from_30.clock, clock connect input_unit_0_from_30.reset, reset inst ingress_unit_1_from_24 of IngressUnit_34 connect ingress_unit_1_from_24.clock, clock connect ingress_unit_1_from_24.reset, reset inst ingress_unit_2_from_25 of IngressUnit_35 connect ingress_unit_2_from_25.clock, clock connect ingress_unit_2_from_25.reset, reset inst ingress_unit_3_from_26 of IngressUnit_36 connect ingress_unit_3_from_26.clock, clock connect ingress_unit_3_from_26.reset, reset inst output_unit_0_to_30 of OutputUnit_13 connect output_unit_0_to_30.clock, clock connect output_unit_0_to_30.reset, reset inst egress_unit_1_to_16 of EgressUnit_31 connect egress_unit_1_to_16.clock, clock connect egress_unit_1_to_16.reset, reset inst egress_unit_2_to_17 of EgressUnit_32 connect egress_unit_2_to_17.clock, clock connect egress_unit_2_to_17.reset, reset inst switch of Switch_13 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_13 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_13 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_13 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_30.io.in, destNodesIn connect ingress_unit_1_from_24.io.in, ingressNodesIn.flit connect ingress_unit_2_from_25.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_26.io.in, ingressNodesIn_2.flit connect output_unit_0_to_30.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_30.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_30.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_16.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_16.io.out.valid connect egress_unit_1_to_16.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_17.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_17.io.out.valid connect egress_unit_2_to_17.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_30.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_24.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_25.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_26.io.router_req connect input_unit_0_from_30.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_24.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_25.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_26.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_30.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_24.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_25.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_26.io.vcalloc_req connect input_unit_0_from_30.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_24.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_25.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_26.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_30.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_16.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_17.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_30.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_30.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_30.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_30.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_30.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_30.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_30.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_30.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_30.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_30.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_30.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_30.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_30.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_30.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_30.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_30.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_30.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_30.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_30.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_30.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_30.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_30.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_30.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_30.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_30.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_30.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_30.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_30.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_30.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_30.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_30.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_30.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_30.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_30.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_30.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_30.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_30.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_30.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_30.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_30.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_30.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_16.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_16.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_16.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_16.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_16.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_16.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_17.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_17.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_17.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_17.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_17.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_17.io.channel_status[0].occupied connect input_unit_0_from_30.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect input_unit_0_from_30.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect input_unit_0_from_30.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect input_unit_0_from_30.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect input_unit_0_from_30.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect input_unit_0_from_30.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect input_unit_0_from_30.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect input_unit_0_from_30.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect input_unit_0_from_30.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect input_unit_0_from_30.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_1_from_24.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_1_from_24.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_1_from_24.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_1_from_24.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_1_from_24.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_1_from_24.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_1_from_24.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_1_from_24.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_2_from_25.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_2_from_25.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_2_from_25.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_2_from_25.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_2_from_25.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_2_from_25.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_2_from_25.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_2_from_25.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`0`[0], output_unit_0_to_30.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`0`[1], output_unit_0_to_30.io.credit_available[1] connect ingress_unit_3_from_26.io.out_credit_available.`0`[2], output_unit_0_to_30.io.credit_available[2] connect ingress_unit_3_from_26.io.out_credit_available.`0`[3], output_unit_0_to_30.io.credit_available[3] connect ingress_unit_3_from_26.io.out_credit_available.`0`[4], output_unit_0_to_30.io.credit_available[4] connect ingress_unit_3_from_26.io.out_credit_available.`0`[5], output_unit_0_to_30.io.credit_available[5] connect ingress_unit_3_from_26.io.out_credit_available.`0`[6], output_unit_0_to_30.io.credit_available[6] connect ingress_unit_3_from_26.io.out_credit_available.`0`[7], output_unit_0_to_30.io.credit_available[7] connect ingress_unit_3_from_26.io.out_credit_available.`1`[0], egress_unit_1_to_16.io.credit_available[0] connect ingress_unit_3_from_26.io.out_credit_available.`2`[0], egress_unit_2_to_17.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_30.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_24.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_25.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_26.io.salloc_req[0] connect output_unit_0_to_30.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_30.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_30.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_30.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_30.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_30.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_30.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_30.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_30.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_30.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_30.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_30.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_30.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_30.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_30.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_30.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_16.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_16.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_17.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_17.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_30.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_24.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_25.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_26.io.out[0] connect output_unit_0_to_30.io.in, switch.io.out.`0` connect egress_unit_1_to_16.io.in, switch.io.out.`1` connect egress_unit_2_to_17.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_30.io.block, UInt<1>(0h0) connect ingress_unit_1_from_24.io.block, UInt<1>(0h0) connect ingress_unit_2_from_25.io.block, UInt<1>(0h0) connect ingress_unit_3_from_26.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_30.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_24.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_25.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_26.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_30.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_24.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_25.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_26.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_31 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 30 14 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i24 14 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i25 14 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i26 14 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 14 e16 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 14 e17 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47

module Router_13( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_17_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_17_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_17_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_16_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_30_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_30_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_26_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_26_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_26_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_26_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_25_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_25_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_25_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_25_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_24_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_24_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_24_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_24_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_30_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_30_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_30_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_30_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_30_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_24_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_25_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_26_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module PE_215 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg

module PE_215( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DTLB_18 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) node memIdx = bits(vpn, 1, 0) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4][4], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[1], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<0>, clock reg r_sectored_repl_addr : UInt<2>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_140 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_18 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_18 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _sector_hits_T_1 = shr(_sector_hits_T, 0) node _sector_hits_T_2 = eq(_sector_hits_T_1, UInt<1>(0h0)) node _sector_hits_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _sector_hits_T_4 = and(_sector_hits_T_2, _sector_hits_T_3) node sector_hits_0 = and(sectored_entries[memIdx][0].valid[0], _sector_hits_T_4) node _sector_hits_T_5 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _sector_hits_T_6 = shr(_sector_hits_T_5, 0) node _sector_hits_T_7 = eq(_sector_hits_T_6, UInt<1>(0h0)) node _sector_hits_T_8 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _sector_hits_T_9 = and(_sector_hits_T_7, _sector_hits_T_8) node sector_hits_1 = and(sectored_entries[memIdx][1].valid[0], _sector_hits_T_9) node _sector_hits_T_10 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _sector_hits_T_11 = shr(_sector_hits_T_10, 0) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _sector_hits_T_14 = and(_sector_hits_T_12, _sector_hits_T_13) node sector_hits_2 = and(sectored_entries[memIdx][2].valid[0], _sector_hits_T_14) node _sector_hits_T_15 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _sector_hits_T_16 = shr(_sector_hits_T_15, 0) node _sector_hits_T_17 = eq(_sector_hits_T_16, UInt<1>(0h0)) node _sector_hits_T_18 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _sector_hits_T_19 = and(_sector_hits_T_17, _sector_hits_T_18) node sector_hits_3 = and(sectored_entries[memIdx][3].valid[0], _sector_hits_T_19) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _hitsVec_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 0) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[memIdx][0].valid[0], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_T_6 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[memIdx][1].valid[0], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node _hitsVec_T_12 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[memIdx][2].valid[0], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node _hitsVec_T_18 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[memIdx][3].valid[0], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_24 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_25 = bits(_hitsVec_T_24, 26, 18) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = or(hitsVec_ignore, _hitsVec_T_26) node _hitsVec_T_28 = and(hitsVec_tagMatch, _hitsVec_T_27) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_29 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_30 = bits(_hitsVec_T_29, 17, 9) node _hitsVec_T_31 = eq(_hitsVec_T_30, UInt<1>(0h0)) node _hitsVec_T_32 = or(hitsVec_ignore_1, _hitsVec_T_31) node _hitsVec_T_33 = and(_hitsVec_T_28, _hitsVec_T_32) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_34 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_35 = bits(_hitsVec_T_34, 8, 0) node _hitsVec_T_36 = eq(_hitsVec_T_35, UInt<1>(0h0)) node _hitsVec_T_37 = or(hitsVec_ignore_2, _hitsVec_T_36) node _hitsVec_T_38 = and(_hitsVec_T_33, _hitsVec_T_37) node hitsVec_4 = and(vm_enabled, _hitsVec_T_38) node _hitsVec_tagMatch_T_1 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_1 = and(special_entry.valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_39 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_40 = bits(_hitsVec_T_39, 26, 18) node _hitsVec_T_41 = eq(_hitsVec_T_40, UInt<1>(0h0)) node _hitsVec_T_42 = or(hitsVec_ignore_3, _hitsVec_T_41) node _hitsVec_T_43 = and(hitsVec_tagMatch_1, _hitsVec_T_42) node _hitsVec_ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_44 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_45 = bits(_hitsVec_T_44, 17, 9) node _hitsVec_T_46 = eq(_hitsVec_T_45, UInt<1>(0h0)) node _hitsVec_T_47 = or(hitsVec_ignore_4, _hitsVec_T_46) node _hitsVec_T_48 = and(_hitsVec_T_43, _hitsVec_T_47) node _hitsVec_ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h0)) node _hitsVec_T_49 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_50 = bits(_hitsVec_T_49, 8, 0) node _hitsVec_T_51 = eq(_hitsVec_T_50, UInt<1>(0h0)) node _hitsVec_T_52 = or(hitsVec_ignore_5, _hitsVec_T_51) node _hitsVec_T_53 = and(_hitsVec_T_48, _hitsVec_T_52) node hitsVec_5 = and(vm_enabled, _hitsVec_T_53) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node r_memIdx = bits(r_refill_tag, 1, 0) node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_4 = eq(waddr_1, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_5 : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][0].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][0].tag_v, refill_v connect sectored_entries[r_memIdx][0].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h1) node sectored_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_0_lo_lo_hi = cat(sectored_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_data_0_lo_lo = cat(sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo) node sectored_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_0_lo_hi_lo = cat(sectored_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_data_0_lo_hi_hi = cat(sectored_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_data_0_lo_hi = cat(sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo) node sectored_entries_0_data_0_lo = cat(sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo) node sectored_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_data_0_hi_lo_lo = cat(sectored_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_data_0_hi_lo_hi = cat(sectored_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_data_0_hi_lo = cat(sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo) node sectored_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_data_0_hi_hi_lo = cat(sectored_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_0_hi_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_data_0_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo) node sectored_entries_0_data_0_hi = cat(sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo) node _sectored_entries_0_data_0_T = cat(sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo) connect sectored_entries[r_memIdx][0].data[0], _sectored_entries_0_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) node _T_6 = eq(waddr_1, UInt<1>(0h1)) when _T_6 : node _T_7 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_7 : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][1].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][1].tag_v, refill_v connect sectored_entries[r_memIdx][1].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h1) node sectored_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_0_lo_lo_hi = cat(sectored_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_1_data_0_lo_lo = cat(sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo) node sectored_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_0_lo_hi_lo = cat(sectored_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_1_data_0_lo_hi_hi = cat(sectored_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_1_data_0_lo_hi = cat(sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo) node sectored_entries_1_data_0_lo = cat(sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo) node sectored_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_1_data_0_hi_lo_lo = cat(sectored_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_1_data_0_hi_lo_hi = cat(sectored_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_1_data_0_hi_lo = cat(sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo) node sectored_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_1_data_0_hi_hi_lo = cat(sectored_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_0_hi_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_1_data_0_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo) node sectored_entries_1_data_0_hi = cat(sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo) node _sectored_entries_1_data_0_T = cat(sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo) connect sectored_entries[r_memIdx][1].data[0], _sectored_entries_1_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) node _T_8 = eq(waddr_1, UInt<2>(0h2)) when _T_8 : node _T_9 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_9 : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][2].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][2].tag_v, refill_v connect sectored_entries[r_memIdx][2].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h1) node sectored_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_0_lo_lo_hi = cat(sectored_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_2_data_0_lo_lo = cat(sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo) node sectored_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_0_lo_hi_lo = cat(sectored_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_2_data_0_lo_hi_hi = cat(sectored_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_2_data_0_lo_hi = cat(sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo) node sectored_entries_2_data_0_lo = cat(sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo) node sectored_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_2_data_0_hi_lo_lo = cat(sectored_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_2_data_0_hi_lo_hi = cat(sectored_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_2_data_0_hi_lo = cat(sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo) node sectored_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_2_data_0_hi_hi_lo = cat(sectored_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_0_hi_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_2_data_0_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo) node sectored_entries_2_data_0_hi = cat(sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo) node _sectored_entries_2_data_0_T = cat(sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo) connect sectored_entries[r_memIdx][2].data[0], _sectored_entries_2_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) node _T_10 = eq(waddr_1, UInt<2>(0h3)) when _T_10 : node _T_11 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_11 : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][3].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][3].tag_v, refill_v connect sectored_entries[r_memIdx][3].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h1) node sectored_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_0_lo_lo_hi = cat(sectored_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_3_data_0_lo_lo = cat(sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo) node sectored_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_0_lo_hi_lo = cat(sectored_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_3_data_0_lo_hi_hi = cat(sectored_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_3_data_0_lo_hi = cat(sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo) node sectored_entries_3_data_0_lo = cat(sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo) node sectored_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_3_data_0_hi_lo_lo = cat(sectored_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_3_data_0_hi_lo_hi = cat(sectored_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_3_data_0_hi_lo = cat(sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo) node sectored_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_3_data_0_hi_hi_lo = cat(sectored_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_0_hi_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_3_data_0_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo) node sectored_entries_3_data_0_hi = cat(sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo) node _sectored_entries_3_data_0_T = cat(sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo) connect sectored_entries[r_memIdx][3].data[0], _sectored_entries_3_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[memIdx][0].data[0] node _entries_T = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T node _entries_T_1 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_22 inst entries_barrier of OptimizationBarrier_TLBEntryData_141 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[memIdx][1].data[0] node _entries_T_23 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_45 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_142 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[memIdx][2].data[0] node _entries_T_46 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_68 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_143 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[memIdx][3].data[0] node _entries_T_69 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_91 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_144 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[0].data[0] node _entries_T_92 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_114 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_145 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_115 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_137 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_146 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_4.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_4.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_5.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h0)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_5.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node _ppn_T_17 = bits(vpn, 19, 0) node _ppn_T_18 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_19 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_20 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_21 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_22 = mux(hitsVec_4, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_23 = mux(hitsVec_5, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_24 = mux(_ppn_T, _ppn_T_17, UInt<1>(0h0)) node _ppn_T_25 = or(_ppn_T_18, _ppn_T_19) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_20) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_21) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_22) node _ppn_T_29 = or(_ppn_T_28, _ppn_T_23) node _ppn_T_30 = or(_ppn_T_29, _ppn_T_24) wire ppn : UInt<20> connect ppn, _ppn_T_30 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<3>, clock, reset, UInt<3>(0h0) wire _state_vec_WIRE : UInt<3>[4] connect _state_vec_WIRE[0], UInt<3>(0h0) connect _state_vec_WIRE[1], UInt<3>(0h0) connect _state_vec_WIRE[2], UInt<3>(0h0) connect _state_vec_WIRE[3], UInt<3>(0h0) regreset state_vec : UInt<3>[4], clock, reset, _state_vec_WIRE reg state_reg_1 : UInt<0>, clock node _T_12 = and(io.req.valid, vm_enabled) when _T_12 : node _T_13 = or(sector_hits_0, sector_hits_1) node _T_14 = or(_T_13, sector_hits_2) node _T_15 = or(_T_14, sector_hits_3) when _T_15 : node lo = cat(sector_hits_1, sector_hits_0) node hi = cat(sector_hits_3, sector_hits_2) node _T_16 = cat(hi, lo) node hi_1 = bits(_T_16, 3, 2) node lo_1 = bits(_T_16, 1, 0) node _T_17 = orr(hi_1) node _T_18 = or(hi_1, lo_1) node _T_19 = bits(_T_18, 1, 1) node _T_20 = cat(_T_17, _T_19) node state_vec_touch_way_sized = bits(_T_20, 1, 0) node _state_vec_set_left_older_T = bits(state_vec_touch_way_sized, 1, 1) node state_vec_set_left_older = eq(_state_vec_set_left_older_T, UInt<1>(0h0)) node state_vec_left_subtree_state = bits(state_vec[memIdx], 1, 1) node state_vec_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _state_vec_T = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_1 = bits(_state_vec_T, 0, 0) node _state_vec_T_2 = eq(_state_vec_T_1, UInt<1>(0h0)) node _state_vec_T_3 = mux(state_vec_set_left_older, state_vec_left_subtree_state, _state_vec_T_2) node _state_vec_T_4 = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_5 = bits(_state_vec_T_4, 0, 0) node _state_vec_T_6 = eq(_state_vec_T_5, UInt<1>(0h0)) node _state_vec_T_7 = mux(state_vec_set_left_older, _state_vec_T_6, state_vec_right_subtree_state) node state_vec_hi = cat(state_vec_set_left_older, _state_vec_T_3) node _state_vec_T_8 = cat(state_vec_hi, _state_vec_T_7) connect state_vec[memIdx], _state_vec_T_8 when superpage_hits_0 : connect state_reg_1, UInt<1>(0h0) node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_21 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_22 = and(_T_21, io.ptw.req.bits.valid) when _T_22 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_23 = and(io.req.ready, io.req.valid) node _T_24 = and(_T_23, tlb_miss) when _T_24 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node _r_superpage_repl_addr_T = andr(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_1 = not(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_2 = bits(_r_superpage_repl_addr_T_1, 0, 0) node _r_superpage_repl_addr_T_3 = mux(_r_superpage_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_3 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[memIdx], 2, 2) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[memIdx], 1, 1) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_valids_lo = cat(sectored_entries[memIdx][1].valid[0], sectored_entries[memIdx][0].valid[0]) node r_sectored_repl_addr_valids_hi = cat(sectored_entries[memIdx][3].valid[0], sectored_entries[memIdx][2].valid[0]) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_4 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_5 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_6 = bits(_r_sectored_repl_addr_T_5, 0, 0) node _r_sectored_repl_addr_T_7 = bits(_r_sectored_repl_addr_T_5, 1, 1) node _r_sectored_repl_addr_T_8 = bits(_r_sectored_repl_addr_T_5, 2, 2) node _r_sectored_repl_addr_T_9 = bits(_r_sectored_repl_addr_T_5, 3, 3) node _r_sectored_repl_addr_T_10 = mux(_r_sectored_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_sectored_repl_addr_T_11 = mux(_r_sectored_repl_addr_T_7, UInt<1>(0h1), _r_sectored_repl_addr_T_10) node _r_sectored_repl_addr_T_12 = mux(_r_sectored_repl_addr_T_6, UInt<1>(0h0), _r_sectored_repl_addr_T_11) node _r_sectored_repl_addr_T_13 = mux(_r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_12) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_13 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_2 node r_sectored_hit_bits_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_hi = cat(sector_hits_3, sector_hits_2) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 3, 2) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 1, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node _r_sectored_hit_bits_T_3 = bits(_r_sectored_hit_bits_T_2, 1, 1) node _r_sectored_hit_bits_T_4 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_4 connect r_superpage_hit.valid, superpage_hits_0 connect r_superpage_hit.bits, UInt<1>(0h0) node _T_25 = eq(state, UInt<2>(0h1)) when _T_25 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_26 = eq(state, UInt<2>(0h2)) node _T_27 = and(_T_26, io.sfence.valid) when _T_27 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_28 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_29 = shr(io.sfence.bits.addr, 12) node _T_30 = eq(_T_29, vpn) node _T_31 = or(_T_28, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_35 = eq(hg, UInt<1>(0h0)) node _T_36 = and(_T_35, io.sfence.bits.rs1) when _T_36 : node _T_37 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_38 = shr(_T_37, 0) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = eq(sectored_entries[0][0].tag_v, hv) node _T_41 = and(_T_39, _T_40) when _T_41 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_42 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_42 node _T_43 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_43 node _T_44 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_44 node _T_45 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_45 node _T_46 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_46 node _T_47 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_47 node _T_48 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_48 node _T_49 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_49 node _T_50 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_50 node _T_51 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_51 node _T_52 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_52 node _T_53 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_53 node _T_54 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_54 node _T_55 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_55 node _T_56 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_56 node _T_57 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_57 node _T_58 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_58 node _T_59 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_59 node _T_60 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_60 node _T_61 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_61 node _T_62 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_62 node _T_63 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_63 node _T_64 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_64 node _T_65 = eq(sectored_entries[0][0].tag_v, hv) node _T_66 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_68 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_69 = shr(_T_68, 18) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[0] node _T_71 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_71 node _T_72 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_72 node _T_73 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_73 node _T_74 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_74 node _T_75 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_75 node _T_76 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_76 node _T_77 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_77 node _T_78 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_78 node _T_79 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_79 node _T_80 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_80 node _T_81 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_81 node _T_82 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_82 node _T_83 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_83 node _T_84 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_84 node _T_85 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_85 node _T_86 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_86 node _T_87 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_87 node _T_88 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_88 node _T_89 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_89 node _T_90 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_90 node _T_91 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_91 node _T_92 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_92 node _T_93 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_93 node _T_94 = eq(sectored_entries[0][0].tag_v, hv) node _T_95 = and(_T_94, _WIRE_2.fragmented_superpage) when _T_95 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_96 = eq(hg, UInt<1>(0h0)) node _T_97 = and(_T_96, io.sfence.bits.rs2) when _T_97 : wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[0] node _T_98 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_98 node _T_99 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_99 node _T_100 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_100 node _T_101 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_101 node _T_102 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_102 node _T_103 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_103 node _T_104 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_104 node _T_105 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_105 node _T_106 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_106 node _T_107 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_107 node _T_108 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_108 node _T_109 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_109 node _T_110 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_110 node _T_111 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_111 node _T_112 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_112 node _T_113 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_113 node _T_114 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_114 node _T_115 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_115 node _T_116 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_116 node _T_117 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_117 node _T_118 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_118 node _T_119 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_119 node _T_120 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_120 node _T_121 = eq(sectored_entries[0][0].tag_v, hv) node _T_122 = eq(_WIRE_4.g, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) when _T_123 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_124 = or(hv, hg) wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[0] node _T_125 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_125 node _T_126 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_126 node _T_127 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_127 node _T_128 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_128 node _T_129 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_129 node _T_130 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_130 node _T_131 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_131 node _T_132 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_132 node _T_133 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_133 node _T_134 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_134 node _T_135 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_135 node _T_136 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_136 node _T_137 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_137 node _T_138 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_138 node _T_139 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_139 node _T_140 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_140 node _T_141 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_141 node _T_142 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_142 node _T_143 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_143 node _T_144 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_144 node _T_145 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_145 node _T_146 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_146 node _T_147 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_147 node _T_148 = eq(sectored_entries[0][0].tag_v, _T_124) when _T_148 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_149 = eq(hg_1, UInt<1>(0h0)) node _T_150 = and(_T_149, io.sfence.bits.rs1) when _T_150 : node _T_151 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_152 = shr(_T_151, 0) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_155 = and(_T_153, _T_154) when _T_155 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][1].data[0] node _T_156 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_156 node _T_157 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_157 node _T_158 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_158 node _T_159 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_159 node _T_160 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_160 node _T_161 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_161 node _T_162 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_162 node _T_163 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_163 node _T_164 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_164 node _T_165 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_165 node _T_166 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_166 node _T_167 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_167 node _T_168 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_168 node _T_169 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_169 node _T_170 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_170 node _T_171 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_171 node _T_172 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_172 node _T_173 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_173 node _T_174 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_174 node _T_175 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_175 node _T_176 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_176 node _T_177 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_177 node _T_178 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_178 node _T_179 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = and(_T_179, _T_180) when _T_181 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_182 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_183 = shr(_T_182, 18) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][1].data[0] node _T_185 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_185 node _T_186 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_186 node _T_187 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_187 node _T_188 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_188 node _T_189 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_189 node _T_190 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_190 node _T_191 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_191 node _T_192 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_192 node _T_193 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_193 node _T_194 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_194 node _T_195 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_195 node _T_196 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_196 node _T_197 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_197 node _T_198 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_198 node _T_199 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_199 node _T_200 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_200 node _T_201 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_201 node _T_202 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_202 node _T_203 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_203 node _T_204 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_204 node _T_205 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_205 node _T_206 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_206 node _T_207 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_207 node _T_208 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_209 = and(_T_208, _WIRE_10.fragmented_superpage) when _T_209 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_210 = eq(hg_1, UInt<1>(0h0)) node _T_211 = and(_T_210, io.sfence.bits.rs2) when _T_211 : wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][1].data[0] node _T_212 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_212 node _T_213 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_213 node _T_214 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_214 node _T_215 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_215 node _T_216 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_216 node _T_217 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_217 node _T_218 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_218 node _T_219 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_219 node _T_220 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_220 node _T_221 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_221 node _T_222 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_222 node _T_223 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_223 node _T_224 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_224 node _T_225 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_225 node _T_226 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_226 node _T_227 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_227 node _T_228 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_228 node _T_229 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_229 node _T_230 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_230 node _T_231 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_231 node _T_232 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_232 node _T_233 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_233 node _T_234 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_234 node _T_235 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_236 = eq(_WIRE_12.g, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) when _T_237 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_238 = or(hv_1, hg_1) wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][1].data[0] node _T_239 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_239 node _T_240 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_240 node _T_241 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_241 node _T_242 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_242 node _T_243 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_243 node _T_244 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_244 node _T_245 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_245 node _T_246 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_246 node _T_247 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_247 node _T_248 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_248 node _T_249 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_249 node _T_250 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_250 node _T_251 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_251 node _T_252 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_252 node _T_253 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_253 node _T_254 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_254 node _T_255 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_255 node _T_256 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_256 node _T_257 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_257 node _T_258 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_258 node _T_259 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_259 node _T_260 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_260 node _T_261 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_261 node _T_262 = eq(sectored_entries[0][1].tag_v, _T_238) when _T_262 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_263 = eq(hg_2, UInt<1>(0h0)) node _T_264 = and(_T_263, io.sfence.bits.rs1) when _T_264 : node _T_265 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_266 = shr(_T_265, 0) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_269 = and(_T_267, _T_268) when _T_269 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][2].data[0] node _T_270 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_270 node _T_271 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_271 node _T_272 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_272 node _T_273 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_273 node _T_274 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_274 node _T_275 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_275 node _T_276 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_276 node _T_277 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_277 node _T_278 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_278 node _T_279 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_279 node _T_280 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_280 node _T_281 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_281 node _T_282 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_282 node _T_283 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_283 node _T_284 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_284 node _T_285 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_285 node _T_286 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_286 node _T_287 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_287 node _T_288 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_288 node _T_289 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_289 node _T_290 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_290 node _T_291 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_291 node _T_292 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_292 node _T_293 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_294 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) when _T_295 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_296 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_297 = shr(_T_296, 18) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][2].data[0] node _T_299 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_299 node _T_300 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_300 node _T_301 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_301 node _T_302 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_302 node _T_303 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_303 node _T_304 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_304 node _T_305 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_305 node _T_306 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_306 node _T_307 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_307 node _T_308 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_308 node _T_309 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_309 node _T_310 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_310 node _T_311 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_311 node _T_312 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_312 node _T_313 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_313 node _T_314 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_314 node _T_315 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_315 node _T_316 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_316 node _T_317 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_317 node _T_318 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_318 node _T_319 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_319 node _T_320 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_320 node _T_321 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_321 node _T_322 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_323 = and(_T_322, _WIRE_18.fragmented_superpage) when _T_323 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_324 = eq(hg_2, UInt<1>(0h0)) node _T_325 = and(_T_324, io.sfence.bits.rs2) when _T_325 : wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][2].data[0] node _T_326 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_326 node _T_327 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_327 node _T_328 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_328 node _T_329 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_329 node _T_330 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_330 node _T_331 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_331 node _T_332 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_332 node _T_333 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_333 node _T_334 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_334 node _T_335 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_335 node _T_336 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_336 node _T_337 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_337 node _T_338 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_338 node _T_339 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_339 node _T_340 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_340 node _T_341 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_341 node _T_342 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_342 node _T_343 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_343 node _T_344 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_344 node _T_345 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_345 node _T_346 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_346 node _T_347 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_347 node _T_348 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_348 node _T_349 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_350 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) when _T_351 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_352 = or(hv_2, hg_2) wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][2].data[0] node _T_353 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_353 node _T_354 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_354 node _T_355 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_355 node _T_356 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_356 node _T_357 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_357 node _T_358 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_358 node _T_359 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_359 node _T_360 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_360 node _T_361 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_361 node _T_362 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_362 node _T_363 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_363 node _T_364 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_364 node _T_365 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_365 node _T_366 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_366 node _T_367 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_367 node _T_368 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_368 node _T_369 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_369 node _T_370 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_370 node _T_371 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_371 node _T_372 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_372 node _T_373 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_373 node _T_374 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_374 node _T_375 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_375 node _T_376 = eq(sectored_entries[0][2].tag_v, _T_352) when _T_376 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_377 = eq(hg_3, UInt<1>(0h0)) node _T_378 = and(_T_377, io.sfence.bits.rs1) when _T_378 : node _T_379 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_380 = shr(_T_379, 0) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_383 = and(_T_381, _T_382) when _T_383 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][3].data[0] node _T_384 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_384 node _T_385 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_385 node _T_386 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_386 node _T_387 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_387 node _T_388 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_388 node _T_389 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_389 node _T_390 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_390 node _T_391 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_391 node _T_392 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_392 node _T_393 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_393 node _T_394 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_394 node _T_395 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_395 node _T_396 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_396 node _T_397 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_397 node _T_398 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_398 node _T_399 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_399 node _T_400 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_400 node _T_401 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_401 node _T_402 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_402 node _T_403 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_403 node _T_404 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_404 node _T_405 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_405 node _T_406 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_406 node _T_407 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_408 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = and(_T_407, _T_408) when _T_409 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_410 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_411 = shr(_T_410, 18) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][3].data[0] node _T_413 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_413 node _T_414 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_414 node _T_415 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_415 node _T_416 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_416 node _T_417 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_417 node _T_418 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_418 node _T_419 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_419 node _T_420 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_420 node _T_421 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_421 node _T_422 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_422 node _T_423 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_423 node _T_424 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_424 node _T_425 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_425 node _T_426 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_426 node _T_427 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_427 node _T_428 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_428 node _T_429 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_429 node _T_430 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_430 node _T_431 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_431 node _T_432 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_432 node _T_433 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_433 node _T_434 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_434 node _T_435 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_435 node _T_436 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_437 = and(_T_436, _WIRE_26.fragmented_superpage) when _T_437 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_438 = eq(hg_3, UInt<1>(0h0)) node _T_439 = and(_T_438, io.sfence.bits.rs2) when _T_439 : wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][3].data[0] node _T_440 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_440 node _T_441 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_441 node _T_442 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_442 node _T_443 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_443 node _T_444 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_444 node _T_445 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_445 node _T_446 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_446 node _T_447 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_447 node _T_448 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_448 node _T_449 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_449 node _T_450 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_450 node _T_451 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_451 node _T_452 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_452 node _T_453 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_453 node _T_454 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_454 node _T_455 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_455 node _T_456 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_456 node _T_457 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_457 node _T_458 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_458 node _T_459 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_459 node _T_460 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_460 node _T_461 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_461 node _T_462 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_462 node _T_463 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_464 = eq(_WIRE_28.g, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) when _T_465 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_466 = or(hv_3, hg_3) wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][3].data[0] node _T_467 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_467 node _T_468 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_468 node _T_469 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_469 node _T_470 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_470 node _T_471 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_471 node _T_472 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_472 node _T_473 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_473 node _T_474 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_474 node _T_475 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_475 node _T_476 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_476 node _T_477 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_477 node _T_478 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_478 node _T_479 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_479 node _T_480 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_480 node _T_481 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_481 node _T_482 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_482 node _T_483 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_483 node _T_484 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_484 node _T_485 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_485 node _T_486 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_486 node _T_487 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_487 node _T_488 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_488 node _T_489 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_489 node _T_490 = eq(sectored_entries[0][3].tag_v, _T_466) when _T_490 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_491 = eq(hg_4, UInt<1>(0h0)) node _T_492 = and(_T_491, io.sfence.bits.rs1) when _T_492 : node _T_493 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_494 = shr(_T_493, 0) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_497 = and(_T_495, _T_496) when _T_497 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[1][0].data[0] node _T_498 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_498 node _T_499 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_499 node _T_500 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_500 node _T_501 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_501 node _T_502 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_502 node _T_503 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_503 node _T_504 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_504 node _T_505 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_505 node _T_506 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_506 node _T_507 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_507 node _T_508 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_508 node _T_509 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_509 node _T_510 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_510 node _T_511 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_511 node _T_512 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_512 node _T_513 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_513 node _T_514 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_514 node _T_515 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_515 node _T_516 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_516 node _T_517 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_517 node _T_518 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_518 node _T_519 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_519 node _T_520 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_520 node _T_521 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) when _T_523 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node _T_524 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_525 = shr(_T_524, 18) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[1][0].data[0] node _T_527 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_528 node _T_529 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_529 node _T_530 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_530 node _T_531 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_531 node _T_532 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_532 node _T_533 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_533 node _T_534 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_534 node _T_535 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_535 node _T_536 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_536 node _T_537 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_537 node _T_538 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_538 node _T_539 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_539 node _T_540 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_540 node _T_541 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_541 node _T_542 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_542 node _T_543 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_543 node _T_544 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_544 node _T_545 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_545 node _T_546 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_546 node _T_547 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_547 node _T_548 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_548 node _T_549 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_549 node _T_550 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_551 = and(_T_550, _WIRE_34.fragmented_superpage) when _T_551 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_552 = eq(hg_4, UInt<1>(0h0)) node _T_553 = and(_T_552, io.sfence.bits.rs2) when _T_553 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[1][0].data[0] node _T_554 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_554 node _T_555 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_555 node _T_556 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_556 node _T_557 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_557 node _T_558 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_558 node _T_559 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_559 node _T_560 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_560 node _T_561 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_561 node _T_562 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_562 node _T_563 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_563 node _T_564 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_564 node _T_565 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_565 node _T_566 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_566 node _T_567 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_567 node _T_568 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_568 node _T_569 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_569 node _T_570 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_570 node _T_571 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_571 node _T_572 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_572 node _T_573 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_573 node _T_574 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_574 node _T_575 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_575 node _T_576 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_576 node _T_577 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_578 = eq(_WIRE_36.g, UInt<1>(0h0)) node _T_579 = and(_T_577, _T_578) when _T_579 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_580 = or(hv_4, hg_4) wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[1][0].data[0] node _T_581 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_581 node _T_582 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_582 node _T_583 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_583 node _T_584 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_584 node _T_585 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_585 node _T_586 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_586 node _T_587 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_587 node _T_588 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_588 node _T_589 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_589 node _T_590 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_590 node _T_591 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_591 node _T_592 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_592 node _T_593 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_593 node _T_594 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_594 node _T_595 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_595 node _T_596 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_596 node _T_597 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_597 node _T_598 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_598 node _T_599 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_599 node _T_600 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_600 node _T_601 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_601 node _T_602 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_602 node _T_603 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_603 node _T_604 = eq(sectored_entries[1][0].tag_v, _T_580) when _T_604 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_605 = eq(hg_5, UInt<1>(0h0)) node _T_606 = and(_T_605, io.sfence.bits.rs1) when _T_606 : node _T_607 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_608 = shr(_T_607, 0) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_611 = and(_T_609, _T_610) when _T_611 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[1][1].data[0] node _T_612 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_612 node _T_613 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_613 node _T_614 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_614 node _T_615 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_615 node _T_616 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_616 node _T_617 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_617 node _T_618 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_618 node _T_619 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_619 node _T_620 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_620 node _T_621 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_621 node _T_622 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_622 node _T_623 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_623 node _T_624 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_624 node _T_625 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_625 node _T_626 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_626 node _T_627 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_627 node _T_628 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_628 node _T_629 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_629 node _T_630 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_630 node _T_631 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_631 node _T_632 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_632 node _T_633 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_633 node _T_634 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_634 node _T_635 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_636 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = and(_T_635, _T_636) when _T_637 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node _T_638 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_639 = shr(_T_638, 18) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[1][1].data[0] node _T_641 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_641 node _T_642 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_642 node _T_643 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_643 node _T_644 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_644 node _T_645 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_645 node _T_646 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_646 node _T_647 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_647 node _T_648 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_648 node _T_649 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_649 node _T_650 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_650 node _T_651 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_651 node _T_652 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_652 node _T_653 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_653 node _T_654 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_654 node _T_655 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_655 node _T_656 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_656 node _T_657 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_657 node _T_658 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_658 node _T_659 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_659 node _T_660 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_660 node _T_661 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_661 node _T_662 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_662 node _T_663 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_663 node _T_664 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_665 = and(_T_664, _WIRE_42.fragmented_superpage) when _T_665 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_666 = eq(hg_5, UInt<1>(0h0)) node _T_667 = and(_T_666, io.sfence.bits.rs2) when _T_667 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[1][1].data[0] node _T_668 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_668 node _T_669 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_669 node _T_670 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_670 node _T_671 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_671 node _T_672 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_672 node _T_673 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_673 node _T_674 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_674 node _T_675 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_675 node _T_676 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_676 node _T_677 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_677 node _T_678 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_678 node _T_679 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_679 node _T_680 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_680 node _T_681 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_681 node _T_682 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_682 node _T_683 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_683 node _T_684 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_684 node _T_685 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_685 node _T_686 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_686 node _T_687 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_687 node _T_688 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_688 node _T_689 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_689 node _T_690 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_690 node _T_691 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_692 = eq(_WIRE_44.g, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) when _T_693 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_694 = or(hv_5, hg_5) wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[1][1].data[0] node _T_695 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_695 node _T_696 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_696 node _T_697 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_697 node _T_698 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_698 node _T_699 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_699 node _T_700 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_700 node _T_701 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_701 node _T_702 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_702 node _T_703 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_703 node _T_704 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_704 node _T_705 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_705 node _T_706 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_706 node _T_707 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_707 node _T_708 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_708 node _T_709 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_709 node _T_710 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_710 node _T_711 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_711 node _T_712 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_712 node _T_713 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_713 node _T_714 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_714 node _T_715 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_715 node _T_716 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_716 node _T_717 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_717 node _T_718 = eq(sectored_entries[1][1].tag_v, _T_694) when _T_718 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_719 = eq(hg_6, UInt<1>(0h0)) node _T_720 = and(_T_719, io.sfence.bits.rs1) when _T_720 : node _T_721 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_722 = shr(_T_721, 0) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_725 = and(_T_723, _T_724) when _T_725 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[1][2].data[0] node _T_726 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_726 node _T_727 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_727 node _T_728 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_728 node _T_729 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_729 node _T_730 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_730 node _T_731 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_731 node _T_732 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_732 node _T_733 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_733 node _T_734 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_734 node _T_735 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_735 node _T_736 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_736 node _T_737 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_737 node _T_738 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_738 node _T_739 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_739 node _T_740 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_740 node _T_741 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_741 node _T_742 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_742 node _T_743 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_743 node _T_744 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_744 node _T_745 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_745 node _T_746 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_746 node _T_747 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_747 node _T_748 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_748 node _T_749 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_750 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = and(_T_749, _T_750) when _T_751 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node _T_752 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_753 = shr(_T_752, 18) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[1][2].data[0] node _T_755 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_755 node _T_756 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_756 node _T_757 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_757 node _T_758 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_758 node _T_759 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_759 node _T_760 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_760 node _T_761 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_761 node _T_762 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_762 node _T_763 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_763 node _T_764 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_764 node _T_765 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_765 node _T_766 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_766 node _T_767 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_767 node _T_768 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_768 node _T_769 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_769 node _T_770 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_770 node _T_771 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_771 node _T_772 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_772 node _T_773 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_773 node _T_774 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_774 node _T_775 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_775 node _T_776 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_776 node _T_777 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_777 node _T_778 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_779 = and(_T_778, _WIRE_50.fragmented_superpage) when _T_779 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_780 = eq(hg_6, UInt<1>(0h0)) node _T_781 = and(_T_780, io.sfence.bits.rs2) when _T_781 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[1][2].data[0] node _T_782 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_782 node _T_783 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_783 node _T_784 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_784 node _T_785 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_785 node _T_786 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_786 node _T_787 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_787 node _T_788 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_788 node _T_789 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_789 node _T_790 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_790 node _T_791 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_791 node _T_792 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_792 node _T_793 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_793 node _T_794 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_794 node _T_795 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_795 node _T_796 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_796 node _T_797 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_797 node _T_798 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_798 node _T_799 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_799 node _T_800 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_800 node _T_801 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_801 node _T_802 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_802 node _T_803 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_803 node _T_804 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_804 node _T_805 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_806 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_807 = and(_T_805, _T_806) when _T_807 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_808 = or(hv_6, hg_6) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[1][2].data[0] node _T_809 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_809 node _T_810 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_810 node _T_811 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_811 node _T_812 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_812 node _T_813 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_813 node _T_814 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_814 node _T_815 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_815 node _T_816 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_816 node _T_817 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_817 node _T_818 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_818 node _T_819 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_819 node _T_820 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_820 node _T_821 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_821 node _T_822 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_822 node _T_823 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_823 node _T_824 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_824 node _T_825 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_825 node _T_826 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_826 node _T_827 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_827 node _T_828 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_828 node _T_829 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_829 node _T_830 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_830 node _T_831 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_831 node _T_832 = eq(sectored_entries[1][2].tag_v, _T_808) when _T_832 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_833 = eq(hg_7, UInt<1>(0h0)) node _T_834 = and(_T_833, io.sfence.bits.rs1) when _T_834 : node _T_835 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_836 = shr(_T_835, 0) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_839 = and(_T_837, _T_838) when _T_839 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[1][3].data[0] node _T_840 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_840 node _T_841 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_841 node _T_842 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_842 node _T_843 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_843 node _T_844 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_844 node _T_845 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_845 node _T_846 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_846 node _T_847 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_847 node _T_848 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_848 node _T_849 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_849 node _T_850 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_850 node _T_851 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_851 node _T_852 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_852 node _T_853 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_853 node _T_854 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_854 node _T_855 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_855 node _T_856 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_856 node _T_857 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_857 node _T_858 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_858 node _T_859 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_859 node _T_860 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_860 node _T_861 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_861 node _T_862 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_862 node _T_863 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_864 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_865 = and(_T_863, _T_864) when _T_865 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node _T_866 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_867 = shr(_T_866, 18) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[1][3].data[0] node _T_869 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_869 node _T_870 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_870 node _T_871 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_871 node _T_872 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_872 node _T_873 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_873 node _T_874 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_874 node _T_875 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_875 node _T_876 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_876 node _T_877 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_877 node _T_878 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_878 node _T_879 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_879 node _T_880 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_880 node _T_881 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_881 node _T_882 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_882 node _T_883 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_883 node _T_884 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_884 node _T_885 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_885 node _T_886 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_886 node _T_887 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_887 node _T_888 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_888 node _T_889 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_889 node _T_890 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_890 node _T_891 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_891 node _T_892 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_893 = and(_T_892, _WIRE_58.fragmented_superpage) when _T_893 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_894 = eq(hg_7, UInt<1>(0h0)) node _T_895 = and(_T_894, io.sfence.bits.rs2) when _T_895 : wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[1][3].data[0] node _T_896 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_896 node _T_897 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_897 node _T_898 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_898 node _T_899 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_899 node _T_900 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_900 node _T_901 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_901 node _T_902 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_902 node _T_903 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_903 node _T_904 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_904 node _T_905 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_905 node _T_906 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_906 node _T_907 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_907 node _T_908 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_908 node _T_909 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_909 node _T_910 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_910 node _T_911 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_911 node _T_912 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_912 node _T_913 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_913 node _T_914 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_914 node _T_915 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_915 node _T_916 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_916 node _T_917 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_917 node _T_918 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_918 node _T_919 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_920 = eq(_WIRE_60.g, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_922 = or(hv_7, hg_7) wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[1][3].data[0] node _T_923 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_923 node _T_924 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_924 node _T_925 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_925 node _T_926 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_926 node _T_927 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_927 node _T_928 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_928 node _T_929 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_929 node _T_930 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_930 node _T_931 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_931 node _T_932 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_932 node _T_933 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_933 node _T_934 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_934 node _T_935 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_935 node _T_936 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_936 node _T_937 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_937 node _T_938 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_938 node _T_939 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_939 node _T_940 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_940 node _T_941 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_941 node _T_942 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_942 node _T_943 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_943 node _T_944 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_944 node _T_945 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_945 node _T_946 = eq(sectored_entries[1][3].tag_v, _T_922) when _T_946 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_947 = eq(hg_8, UInt<1>(0h0)) node _T_948 = and(_T_947, io.sfence.bits.rs1) when _T_948 : node _T_949 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_950 = shr(_T_949, 0) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_953 = and(_T_951, _T_952) when _T_953 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[2][0].data[0] node _T_954 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_954 node _T_955 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_955 node _T_956 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_956 node _T_957 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_957 node _T_958 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_958 node _T_959 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_959 node _T_960 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_960 node _T_961 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_961 node _T_962 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_962 node _T_963 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_963 node _T_964 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_964 node _T_965 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_965 node _T_966 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_966 node _T_967 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_967 node _T_968 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_968 node _T_969 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_969 node _T_970 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_970 node _T_971 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_971 node _T_972 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_972 node _T_973 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_973 node _T_974 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_974 node _T_975 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_975 node _T_976 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_976 node _T_977 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_978 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = and(_T_977, _T_978) when _T_979 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node _T_980 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_981 = shr(_T_980, 18) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[2][0].data[0] node _T_983 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_983 node _T_984 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_984 node _T_985 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_985 node _T_986 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_986 node _T_987 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_987 node _T_988 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_988 node _T_989 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_989 node _T_990 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_990 node _T_991 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_991 node _T_992 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_992 node _T_993 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_993 node _T_994 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_994 node _T_995 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_995 node _T_996 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_996 node _T_997 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_997 node _T_998 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_998 node _T_999 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_999 node _T_1000 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1000 node _T_1001 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1001 node _T_1002 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1002 node _T_1003 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1003 node _T_1004 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1004 node _T_1005 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1005 node _T_1006 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1007 = and(_T_1006, _WIRE_66.fragmented_superpage) when _T_1007 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1008 = eq(hg_8, UInt<1>(0h0)) node _T_1009 = and(_T_1008, io.sfence.bits.rs2) when _T_1009 : wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[2][0].data[0] node _T_1010 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1010 node _T_1011 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1011 node _T_1012 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1012 node _T_1013 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1013 node _T_1014 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1014 node _T_1015 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1015 node _T_1016 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1016 node _T_1017 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1017 node _T_1018 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1018 node _T_1019 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1019 node _T_1020 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1020 node _T_1021 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1021 node _T_1022 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1022 node _T_1023 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1023 node _T_1024 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1024 node _T_1025 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1025 node _T_1026 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1026 node _T_1027 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1027 node _T_1028 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1028 node _T_1029 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1029 node _T_1030 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1030 node _T_1031 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1031 node _T_1032 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1032 node _T_1033 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1034 = eq(_WIRE_68.g, UInt<1>(0h0)) node _T_1035 = and(_T_1033, _T_1034) when _T_1035 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1036 = or(hv_8, hg_8) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[2][0].data[0] node _T_1037 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1037 node _T_1038 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1038 node _T_1039 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1039 node _T_1040 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1040 node _T_1041 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1041 node _T_1042 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1042 node _T_1043 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1043 node _T_1044 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1044 node _T_1045 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1045 node _T_1046 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1046 node _T_1047 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1047 node _T_1048 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1048 node _T_1049 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1049 node _T_1050 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1050 node _T_1051 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1051 node _T_1052 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1052 node _T_1053 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1053 node _T_1054 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1054 node _T_1055 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1055 node _T_1056 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1056 node _T_1057 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1057 node _T_1058 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1058 node _T_1059 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1059 node _T_1060 = eq(sectored_entries[2][0].tag_v, _T_1036) when _T_1060 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1061 = eq(hg_9, UInt<1>(0h0)) node _T_1062 = and(_T_1061, io.sfence.bits.rs1) when _T_1062 : node _T_1063 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1064 = shr(_T_1063, 0) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[2][1].data[0] node _T_1068 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1068 node _T_1069 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1069 node _T_1070 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1070 node _T_1071 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1071 node _T_1072 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1072 node _T_1073 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1073 node _T_1074 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1074 node _T_1075 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1075 node _T_1076 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1076 node _T_1077 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1077 node _T_1078 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1078 node _T_1079 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1079 node _T_1080 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1080 node _T_1081 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1081 node _T_1082 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1082 node _T_1083 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1083 node _T_1084 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1084 node _T_1085 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1085 node _T_1086 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1086 node _T_1087 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1087 node _T_1088 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1088 node _T_1089 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1089 node _T_1090 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1090 node _T_1091 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1092 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = and(_T_1091, _T_1092) when _T_1093 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node _T_1094 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1095 = shr(_T_1094, 18) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[2][1].data[0] node _T_1097 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1097 node _T_1098 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1098 node _T_1099 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1099 node _T_1100 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1100 node _T_1101 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1101 node _T_1102 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1102 node _T_1103 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1103 node _T_1104 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1104 node _T_1105 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1105 node _T_1106 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1106 node _T_1107 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1107 node _T_1108 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1108 node _T_1109 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1109 node _T_1110 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1110 node _T_1111 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1111 node _T_1112 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1112 node _T_1113 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1113 node _T_1114 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1114 node _T_1115 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1115 node _T_1116 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1116 node _T_1117 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1117 node _T_1118 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1118 node _T_1119 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1119 node _T_1120 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1121 = and(_T_1120, _WIRE_74.fragmented_superpage) when _T_1121 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1122 = eq(hg_9, UInt<1>(0h0)) node _T_1123 = and(_T_1122, io.sfence.bits.rs2) when _T_1123 : wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[2][1].data[0] node _T_1124 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1124 node _T_1125 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1125 node _T_1126 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1126 node _T_1127 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1127 node _T_1128 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1128 node _T_1129 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1129 node _T_1130 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1130 node _T_1131 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1131 node _T_1132 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1132 node _T_1133 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1133 node _T_1134 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1134 node _T_1135 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1135 node _T_1136 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1136 node _T_1137 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1137 node _T_1138 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1138 node _T_1139 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1139 node _T_1140 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1140 node _T_1141 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1141 node _T_1142 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1142 node _T_1143 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1143 node _T_1144 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1144 node _T_1145 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1145 node _T_1146 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1146 node _T_1147 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1148 = eq(_WIRE_76.g, UInt<1>(0h0)) node _T_1149 = and(_T_1147, _T_1148) when _T_1149 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1150 = or(hv_9, hg_9) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[2][1].data[0] node _T_1151 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1151 node _T_1152 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1152 node _T_1153 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1153 node _T_1154 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1154 node _T_1155 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1155 node _T_1156 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1156 node _T_1157 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1157 node _T_1158 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1158 node _T_1159 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1159 node _T_1160 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1160 node _T_1161 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1161 node _T_1162 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1162 node _T_1163 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1163 node _T_1164 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1164 node _T_1165 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1165 node _T_1166 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1166 node _T_1167 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1167 node _T_1168 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1168 node _T_1169 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1169 node _T_1170 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1170 node _T_1171 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1171 node _T_1172 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1172 node _T_1173 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1173 node _T_1174 = eq(sectored_entries[2][1].tag_v, _T_1150) when _T_1174 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1175 = eq(hg_10, UInt<1>(0h0)) node _T_1176 = and(_T_1175, io.sfence.bits.rs1) when _T_1176 : node _T_1177 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1178 = shr(_T_1177, 0) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1181 = and(_T_1179, _T_1180) when _T_1181 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[2][2].data[0] node _T_1182 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1182 node _T_1183 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1183 node _T_1184 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1184 node _T_1185 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1185 node _T_1186 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1186 node _T_1187 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1187 node _T_1188 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1188 node _T_1189 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1189 node _T_1190 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1190 node _T_1191 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1191 node _T_1192 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1192 node _T_1193 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1193 node _T_1194 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1194 node _T_1195 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1195 node _T_1196 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1196 node _T_1197 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1197 node _T_1198 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1198 node _T_1199 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1199 node _T_1200 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1200 node _T_1201 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1201 node _T_1202 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1202 node _T_1203 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1203 node _T_1204 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1204 node _T_1205 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1206 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node _T_1208 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1209 = shr(_T_1208, 18) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[2][2].data[0] node _T_1211 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1211 node _T_1212 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1212 node _T_1213 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1213 node _T_1214 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1214 node _T_1215 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1215 node _T_1216 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1216 node _T_1217 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1217 node _T_1218 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1218 node _T_1219 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1219 node _T_1220 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1220 node _T_1221 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1221 node _T_1222 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1222 node _T_1223 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1223 node _T_1224 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1224 node _T_1225 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1225 node _T_1226 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1226 node _T_1227 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1227 node _T_1228 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1228 node _T_1229 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1229 node _T_1230 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1230 node _T_1231 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1231 node _T_1232 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1232 node _T_1233 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1233 node _T_1234 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1235 = and(_T_1234, _WIRE_82.fragmented_superpage) when _T_1235 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1236 = eq(hg_10, UInt<1>(0h0)) node _T_1237 = and(_T_1236, io.sfence.bits.rs2) when _T_1237 : wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[2][2].data[0] node _T_1238 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1238 node _T_1239 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1239 node _T_1240 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1240 node _T_1241 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1241 node _T_1242 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1242 node _T_1243 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1243 node _T_1244 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1244 node _T_1245 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1245 node _T_1246 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1246 node _T_1247 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1247 node _T_1248 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1248 node _T_1249 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1249 node _T_1250 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1250 node _T_1251 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1251 node _T_1252 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1252 node _T_1253 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1253 node _T_1254 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1254 node _T_1255 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1255 node _T_1256 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1256 node _T_1257 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1257 node _T_1258 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1258 node _T_1259 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1259 node _T_1260 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1260 node _T_1261 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1262 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1264 = or(hv_10, hg_10) wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[2][2].data[0] node _T_1265 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1265 node _T_1266 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1266 node _T_1267 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1267 node _T_1268 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1268 node _T_1269 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1269 node _T_1270 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1270 node _T_1271 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1271 node _T_1272 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1272 node _T_1273 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1273 node _T_1274 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1274 node _T_1275 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1275 node _T_1276 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1276 node _T_1277 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1277 node _T_1278 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1278 node _T_1279 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1279 node _T_1280 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1280 node _T_1281 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1281 node _T_1282 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1282 node _T_1283 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1283 node _T_1284 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1284 node _T_1285 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1285 node _T_1286 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1286 node _T_1287 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1287 node _T_1288 = eq(sectored_entries[2][2].tag_v, _T_1264) when _T_1288 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1289 = eq(hg_11, UInt<1>(0h0)) node _T_1290 = and(_T_1289, io.sfence.bits.rs1) when _T_1290 : node _T_1291 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1292 = shr(_T_1291, 0) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) node _T_1294 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1295 = and(_T_1293, _T_1294) when _T_1295 : wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[2][3].data[0] node _T_1296 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1296 node _T_1297 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1297 node _T_1298 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1298 node _T_1299 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1299 node _T_1300 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1300 node _T_1301 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1301 node _T_1302 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1302 node _T_1303 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1303 node _T_1304 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1304 node _T_1305 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1305 node _T_1306 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1306 node _T_1307 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1307 node _T_1308 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1308 node _T_1309 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1309 node _T_1310 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1310 node _T_1311 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1311 node _T_1312 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1312 node _T_1313 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1313 node _T_1314 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1314 node _T_1315 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1315 node _T_1316 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1316 node _T_1317 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1317 node _T_1318 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1318 node _T_1319 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1320 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1321 = and(_T_1319, _T_1320) when _T_1321 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node _T_1322 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1323 = shr(_T_1322, 18) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[2][3].data[0] node _T_1325 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1325 node _T_1326 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1326 node _T_1327 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1327 node _T_1328 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1328 node _T_1329 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1329 node _T_1330 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1330 node _T_1331 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1331 node _T_1332 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1332 node _T_1333 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1333 node _T_1334 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1334 node _T_1335 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1335 node _T_1336 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1336 node _T_1337 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1337 node _T_1338 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1338 node _T_1339 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1339 node _T_1340 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1340 node _T_1341 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1341 node _T_1342 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1342 node _T_1343 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1343 node _T_1344 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1344 node _T_1345 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1345 node _T_1346 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1346 node _T_1347 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1347 node _T_1348 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1349 = and(_T_1348, _WIRE_90.fragmented_superpage) when _T_1349 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1350 = eq(hg_11, UInt<1>(0h0)) node _T_1351 = and(_T_1350, io.sfence.bits.rs2) when _T_1351 : wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[2][3].data[0] node _T_1352 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1352 node _T_1353 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1353 node _T_1354 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1354 node _T_1355 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1355 node _T_1356 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1356 node _T_1357 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1357 node _T_1358 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1358 node _T_1359 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1359 node _T_1360 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1360 node _T_1361 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1361 node _T_1362 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1362 node _T_1363 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1363 node _T_1364 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1364 node _T_1365 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1365 node _T_1366 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1366 node _T_1367 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1367 node _T_1368 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1368 node _T_1369 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1369 node _T_1370 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1370 node _T_1371 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1371 node _T_1372 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1372 node _T_1373 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1373 node _T_1374 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1374 node _T_1375 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1376 = eq(_WIRE_92.g, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1378 = or(hv_11, hg_11) wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[2][3].data[0] node _T_1379 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1379 node _T_1380 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1380 node _T_1381 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1381 node _T_1382 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1382 node _T_1383 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1383 node _T_1384 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1384 node _T_1385 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1385 node _T_1386 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1386 node _T_1387 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1387 node _T_1388 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1388 node _T_1389 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1389 node _T_1390 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1390 node _T_1391 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1391 node _T_1392 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1392 node _T_1393 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1393 node _T_1394 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1394 node _T_1395 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1395 node _T_1396 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1396 node _T_1397 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1397 node _T_1398 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1398 node _T_1399 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1399 node _T_1400 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1400 node _T_1401 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1401 node _T_1402 = eq(sectored_entries[2][3].tag_v, _T_1378) when _T_1402 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1403 = eq(hg_12, UInt<1>(0h0)) node _T_1404 = and(_T_1403, io.sfence.bits.rs1) when _T_1404 : node _T_1405 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1406 = shr(_T_1405, 0) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) node _T_1408 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1409 = and(_T_1407, _T_1408) when _T_1409 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[3][0].data[0] node _T_1410 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1410 node _T_1411 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1411 node _T_1412 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1412 node _T_1413 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1413 node _T_1414 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1414 node _T_1415 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1415 node _T_1416 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1416 node _T_1417 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1417 node _T_1418 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1418 node _T_1419 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1419 node _T_1420 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1420 node _T_1421 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1421 node _T_1422 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1422 node _T_1423 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1423 node _T_1424 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1424 node _T_1425 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1425 node _T_1426 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1426 node _T_1427 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1427 node _T_1428 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1428 node _T_1429 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1429 node _T_1430 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1430 node _T_1431 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1431 node _T_1432 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1432 node _T_1433 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1435 = and(_T_1433, _T_1434) when _T_1435 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node _T_1436 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1437 = shr(_T_1436, 18) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[3][0].data[0] node _T_1439 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1439 node _T_1440 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1440 node _T_1441 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1441 node _T_1442 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1442 node _T_1443 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1443 node _T_1444 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1444 node _T_1445 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1445 node _T_1446 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1446 node _T_1447 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1447 node _T_1448 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1448 node _T_1449 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1449 node _T_1450 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1450 node _T_1451 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1451 node _T_1452 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1452 node _T_1453 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1453 node _T_1454 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1454 node _T_1455 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1455 node _T_1456 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1456 node _T_1457 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1457 node _T_1458 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1458 node _T_1459 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1459 node _T_1460 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1460 node _T_1461 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1461 node _T_1462 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1463 = and(_T_1462, _WIRE_98.fragmented_superpage) when _T_1463 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1464 = eq(hg_12, UInt<1>(0h0)) node _T_1465 = and(_T_1464, io.sfence.bits.rs2) when _T_1465 : wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[3][0].data[0] node _T_1466 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1466 node _T_1467 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1467 node _T_1468 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1468 node _T_1469 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1469 node _T_1470 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1470 node _T_1471 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1471 node _T_1472 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1472 node _T_1473 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1473 node _T_1474 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1474 node _T_1475 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1475 node _T_1476 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1476 node _T_1477 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1477 node _T_1478 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1478 node _T_1479 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1479 node _T_1480 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1480 node _T_1481 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1481 node _T_1482 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1482 node _T_1483 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1483 node _T_1484 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1484 node _T_1485 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1485 node _T_1486 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1486 node _T_1487 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1487 node _T_1488 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1488 node _T_1489 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1490 = eq(_WIRE_100.g, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1492 = or(hv_12, hg_12) wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[3][0].data[0] node _T_1493 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1493 node _T_1494 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1494 node _T_1495 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1495 node _T_1496 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1496 node _T_1497 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1497 node _T_1498 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1498 node _T_1499 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1499 node _T_1500 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1500 node _T_1501 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1501 node _T_1502 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1502 node _T_1503 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1503 node _T_1504 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1504 node _T_1505 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1505 node _T_1506 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1506 node _T_1507 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1507 node _T_1508 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1508 node _T_1509 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1509 node _T_1510 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1510 node _T_1511 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1511 node _T_1512 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1512 node _T_1513 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1513 node _T_1514 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1514 node _T_1515 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1515 node _T_1516 = eq(sectored_entries[3][0].tag_v, _T_1492) when _T_1516 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node hv_13 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_13 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1517 = eq(hg_13, UInt<1>(0h0)) node _T_1518 = and(_T_1517, io.sfence.bits.rs1) when _T_1518 : node _T_1519 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1520 = shr(_T_1519, 0) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1523 = and(_T_1521, _T_1522) when _T_1523 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[3][1].data[0] node _T_1524 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1524 node _T_1525 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1525 node _T_1526 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1526 node _T_1527 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1527 node _T_1528 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1528 node _T_1529 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1529 node _T_1530 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1530 node _T_1531 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1531 node _T_1532 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1532 node _T_1533 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1533 node _T_1534 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1534 node _T_1535 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1535 node _T_1536 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1536 node _T_1537 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1537 node _T_1538 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1538 node _T_1539 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1539 node _T_1540 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1540 node _T_1541 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1541 node _T_1542 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1542 node _T_1543 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1543 node _T_1544 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1544 node _T_1545 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1545 node _T_1546 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1546 node _T_1547 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1548 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1549 = and(_T_1547, _T_1548) when _T_1549 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node _T_1550 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1551 = shr(_T_1550, 18) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[3][1].data[0] node _T_1553 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1553 node _T_1554 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1554 node _T_1555 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1555 node _T_1556 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1556 node _T_1557 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1557 node _T_1558 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1558 node _T_1559 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1559 node _T_1560 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1560 node _T_1561 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1561 node _T_1562 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1562 node _T_1563 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1563 node _T_1564 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1564 node _T_1565 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1565 node _T_1566 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1566 node _T_1567 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1567 node _T_1568 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1568 node _T_1569 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1569 node _T_1570 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1570 node _T_1571 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1571 node _T_1572 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1572 node _T_1573 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1573 node _T_1574 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1574 node _T_1575 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1575 node _T_1576 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1577 = and(_T_1576, _WIRE_106.fragmented_superpage) when _T_1577 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1578 = eq(hg_13, UInt<1>(0h0)) node _T_1579 = and(_T_1578, io.sfence.bits.rs2) when _T_1579 : wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[3][1].data[0] node _T_1580 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1580 node _T_1581 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1581 node _T_1582 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1582 node _T_1583 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1583 node _T_1584 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1584 node _T_1585 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1585 node _T_1586 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1586 node _T_1587 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1587 node _T_1588 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1588 node _T_1589 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1589 node _T_1590 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1590 node _T_1591 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1591 node _T_1592 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1592 node _T_1593 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1593 node _T_1594 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1594 node _T_1595 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1595 node _T_1596 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1596 node _T_1597 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1597 node _T_1598 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1598 node _T_1599 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1599 node _T_1600 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1600 node _T_1601 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1601 node _T_1602 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1602 node _T_1603 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1604 = eq(_WIRE_108.g, UInt<1>(0h0)) node _T_1605 = and(_T_1603, _T_1604) when _T_1605 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1606 = or(hv_13, hg_13) wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[3][1].data[0] node _T_1607 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1607 node _T_1608 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1608 node _T_1609 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1609 node _T_1610 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1610 node _T_1611 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1611 node _T_1612 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1612 node _T_1613 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1613 node _T_1614 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1614 node _T_1615 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1615 node _T_1616 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1616 node _T_1617 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1617 node _T_1618 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1618 node _T_1619 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1619 node _T_1620 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1620 node _T_1621 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1621 node _T_1622 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1622 node _T_1623 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1623 node _T_1624 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1624 node _T_1625 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1625 node _T_1626 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1626 node _T_1627 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1627 node _T_1628 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1628 node _T_1629 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1629 node _T_1630 = eq(sectored_entries[3][1].tag_v, _T_1606) when _T_1630 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node hv_14 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_14 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1631 = eq(hg_14, UInt<1>(0h0)) node _T_1632 = and(_T_1631, io.sfence.bits.rs1) when _T_1632 : node _T_1633 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1634 = shr(_T_1633, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[3][2].data[0] node _T_1638 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1638 node _T_1639 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1639 node _T_1640 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1640 node _T_1641 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1641 node _T_1642 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1642 node _T_1643 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1643 node _T_1644 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1644 node _T_1645 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1645 node _T_1646 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1646 node _T_1647 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1647 node _T_1648 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1648 node _T_1649 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1649 node _T_1650 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1650 node _T_1651 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1651 node _T_1652 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1652 node _T_1653 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1653 node _T_1654 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1654 node _T_1655 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1655 node _T_1656 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1656 node _T_1657 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1657 node _T_1658 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1658 node _T_1659 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1659 node _T_1660 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1660 node _T_1661 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1662 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node _T_1664 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1665 = shr(_T_1664, 18) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[3][2].data[0] node _T_1667 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1667 node _T_1668 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1668 node _T_1669 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1669 node _T_1670 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1670 node _T_1671 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1671 node _T_1672 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1672 node _T_1673 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1673 node _T_1674 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1674 node _T_1675 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1675 node _T_1676 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1676 node _T_1677 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1677 node _T_1678 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1678 node _T_1679 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1679 node _T_1680 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1680 node _T_1681 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1681 node _T_1682 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1682 node _T_1683 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1683 node _T_1684 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1684 node _T_1685 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1685 node _T_1686 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1686 node _T_1687 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1687 node _T_1688 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1688 node _T_1689 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1689 node _T_1690 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1691 = and(_T_1690, _WIRE_114.fragmented_superpage) when _T_1691 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1692 = eq(hg_14, UInt<1>(0h0)) node _T_1693 = and(_T_1692, io.sfence.bits.rs2) when _T_1693 : wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[3][2].data[0] node _T_1694 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1694 node _T_1695 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1695 node _T_1696 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1696 node _T_1697 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1697 node _T_1698 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1698 node _T_1699 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1699 node _T_1700 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1700 node _T_1701 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1701 node _T_1702 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1702 node _T_1703 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1703 node _T_1704 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1704 node _T_1705 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1705 node _T_1706 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1706 node _T_1707 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1707 node _T_1708 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1708 node _T_1709 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1709 node _T_1710 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1710 node _T_1711 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1711 node _T_1712 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1712 node _T_1713 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1713 node _T_1714 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1714 node _T_1715 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1715 node _T_1716 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1716 node _T_1717 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1718 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1719 = and(_T_1717, _T_1718) when _T_1719 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1720 = or(hv_14, hg_14) wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[3][2].data[0] node _T_1721 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1721 node _T_1722 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1722 node _T_1723 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1723 node _T_1724 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1724 node _T_1725 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1725 node _T_1726 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1726 node _T_1727 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1727 node _T_1728 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1728 node _T_1729 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1729 node _T_1730 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1730 node _T_1731 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1731 node _T_1732 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1732 node _T_1733 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1733 node _T_1734 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1734 node _T_1735 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1735 node _T_1736 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1736 node _T_1737 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1737 node _T_1738 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1738 node _T_1739 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1739 node _T_1740 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1740 node _T_1741 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1741 node _T_1742 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1742 node _T_1743 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1743 node _T_1744 = eq(sectored_entries[3][2].tag_v, _T_1720) when _T_1744 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node hv_15 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_15 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_15, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 0) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[3][3].data[0] node _T_1752 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1753 node _T_1754 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1754 node _T_1755 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1755 node _T_1756 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1756 node _T_1757 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1757 node _T_1758 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1758 node _T_1759 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1759 node _T_1760 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1760 node _T_1761 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1761 node _T_1762 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1762 node _T_1763 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1763 node _T_1764 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1764 node _T_1765 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1765 node _T_1766 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1766 node _T_1767 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1767 node _T_1768 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1768 node _T_1769 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1770 node _T_1771 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1772 node _T_1773 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1773 node _T_1774 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1774 node _T_1775 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1776 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node _T_1778 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1779 = shr(_T_1778, 18) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[3][3].data[0] node _T_1781 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1781 node _T_1782 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1782 node _T_1783 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1783 node _T_1784 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1784 node _T_1785 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1785 node _T_1786 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1786 node _T_1787 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1787 node _T_1788 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1788 node _T_1789 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1789 node _T_1790 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1790 node _T_1791 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1791 node _T_1792 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1792 node _T_1793 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1793 node _T_1794 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1794 node _T_1795 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1795 node _T_1796 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1796 node _T_1797 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1797 node _T_1798 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1798 node _T_1799 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1799 node _T_1800 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1800 node _T_1801 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1801 node _T_1802 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1802 node _T_1803 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1803 node _T_1804 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1805 = and(_T_1804, _WIRE_122.fragmented_superpage) when _T_1805 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1806 = eq(hg_15, UInt<1>(0h0)) node _T_1807 = and(_T_1806, io.sfence.bits.rs2) when _T_1807 : wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[3][3].data[0] node _T_1808 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1808 node _T_1809 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1809 node _T_1810 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1810 node _T_1811 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1811 node _T_1812 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1812 node _T_1813 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1813 node _T_1814 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1814 node _T_1815 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1815 node _T_1816 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1816 node _T_1817 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1817 node _T_1818 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1818 node _T_1819 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1819 node _T_1820 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1820 node _T_1821 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1821 node _T_1822 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1822 node _T_1823 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1823 node _T_1824 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1824 node _T_1825 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1825 node _T_1826 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1826 node _T_1827 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1827 node _T_1828 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1828 node _T_1829 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1829 node _T_1830 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1830 node _T_1831 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1832 = eq(_WIRE_124.g, UInt<1>(0h0)) node _T_1833 = and(_T_1831, _T_1832) when _T_1833 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1834 = or(hv_15, hg_15) wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[3][3].data[0] node _T_1835 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1835 node _T_1836 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1836 node _T_1837 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1837 node _T_1838 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1838 node _T_1839 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1839 node _T_1840 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1840 node _T_1841 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1841 node _T_1842 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1842 node _T_1843 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1843 node _T_1844 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1844 node _T_1845 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1845 node _T_1846 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1846 node _T_1847 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1847 node _T_1848 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1848 node _T_1849 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1849 node _T_1850 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1850 node _T_1851 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1851 node _T_1852 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1852 node _T_1853 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1853 node _T_1854 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1854 node _T_1855 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1855 node _T_1856 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1856 node _T_1857 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1857 node _T_1858 = eq(sectored_entries[3][3].tag_v, _T_1834) when _T_1858 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node hv_16 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_16 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1859 = eq(hg_16, UInt<1>(0h0)) node _T_1860 = and(_T_1859, io.sfence.bits.rs1) when _T_1860 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_16) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_1861 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1862 = bits(_T_1861, 26, 18) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(ignore, _T_1863) node _T_1865 = and(tagMatch, _T_1864) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_1866 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1867 = bits(_T_1866, 17, 9) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) node _T_1869 = or(ignore_1, _T_1868) node _T_1870 = and(_T_1865, _T_1869) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_1871 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1872 = bits(_T_1871, 8, 0) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = or(ignore_2, _T_1873) node _T_1875 = and(_T_1870, _T_1874) when _T_1875 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_1876 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1877 = shr(_T_1876, 18) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, superpage_entries[0].data[0] node _T_1879 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1879 node _T_1880 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1880 node _T_1881 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1881 node _T_1882 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1882 node _T_1883 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1883 node _T_1884 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1884 node _T_1885 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1885 node _T_1886 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1886 node _T_1887 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1887 node _T_1888 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1888 node _T_1889 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1889 node _T_1890 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1890 node _T_1891 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1891 node _T_1892 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1892 node _T_1893 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1893 node _T_1894 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1894 node _T_1895 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1895 node _T_1896 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1896 node _T_1897 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1897 node _T_1898 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1898 node _T_1899 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1899 node _T_1900 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1900 node _T_1901 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1901 node _T_1902 = eq(superpage_entries[0].tag_v, hv_16) node _T_1903 = and(_T_1902, _WIRE_128.fragmented_superpage) when _T_1903 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1904 = eq(hg_16, UInt<1>(0h0)) node _T_1905 = and(_T_1904, io.sfence.bits.rs2) when _T_1905 : wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, superpage_entries[0].data[0] node _T_1906 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1906 node _T_1907 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1907 node _T_1908 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1908 node _T_1909 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1909 node _T_1910 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1910 node _T_1911 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1911 node _T_1912 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1912 node _T_1913 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1913 node _T_1914 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1914 node _T_1915 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1915 node _T_1916 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1916 node _T_1917 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1917 node _T_1918 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1918 node _T_1919 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1919 node _T_1920 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1920 node _T_1921 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1921 node _T_1922 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1922 node _T_1923 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1923 node _T_1924 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1924 node _T_1925 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1925 node _T_1926 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1926 node _T_1927 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1927 node _T_1928 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1928 node _T_1929 = eq(superpage_entries[0].tag_v, hv_16) node _T_1930 = eq(_WIRE_130.g, UInt<1>(0h0)) node _T_1931 = and(_T_1929, _T_1930) when _T_1931 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1932 = or(hv_16, hg_16) wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, superpage_entries[0].data[0] node _T_1933 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1933 node _T_1934 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1934 node _T_1935 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1935 node _T_1936 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1936 node _T_1937 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1937 node _T_1938 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1938 node _T_1939 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1939 node _T_1940 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1940 node _T_1941 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1941 node _T_1942 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1942 node _T_1943 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1943 node _T_1944 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1944 node _T_1945 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1945 node _T_1946 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1946 node _T_1947 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1947 node _T_1948 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1948 node _T_1949 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1949 node _T_1950 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1950 node _T_1951 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1951 node _T_1952 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1952 node _T_1953 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1953 node _T_1954 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1954 node _T_1955 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1955 node _T_1956 = eq(superpage_entries[0].tag_v, _T_1932) when _T_1956 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_17 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_17 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1957 = eq(hg_17, UInt<1>(0h0)) node _T_1958 = and(_T_1957, io.sfence.bits.rs1) when _T_1958 : node _tagMatch_T_1 = eq(special_entry.tag_v, hv_17) node tagMatch_1 = and(special_entry.valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_1959 = xor(special_entry.tag_vpn, vpn) node _T_1960 = bits(_T_1959, 26, 18) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) node _T_1962 = or(ignore_3, _T_1961) node _T_1963 = and(tagMatch_1, _T_1962) node _ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_1964 = xor(special_entry.tag_vpn, vpn) node _T_1965 = bits(_T_1964, 17, 9) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = or(ignore_4, _T_1966) node _T_1968 = and(_T_1963, _T_1967) node _ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h0)) node _T_1969 = xor(special_entry.tag_vpn, vpn) node _T_1970 = bits(_T_1969, 8, 0) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(ignore_5, _T_1971) node _T_1973 = and(_T_1968, _T_1972) when _T_1973 : connect special_entry.valid[0], UInt<1>(0h0) node _T_1974 = xor(special_entry.tag_vpn, vpn) node _T_1975 = shr(_T_1974, 18) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, special_entry.data[0] node _T_1977 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1977 node _T_1978 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1978 node _T_1979 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1979 node _T_1980 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1980 node _T_1981 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1981 node _T_1982 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1982 node _T_1983 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1983 node _T_1984 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1984 node _T_1985 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1985 node _T_1986 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1986 node _T_1987 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1987 node _T_1988 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1988 node _T_1989 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1989 node _T_1990 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1990 node _T_1991 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1991 node _T_1992 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1992 node _T_1993 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1993 node _T_1994 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1994 node _T_1995 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1995 node _T_1996 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1996 node _T_1997 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1997 node _T_1998 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1998 node _T_1999 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1999 node _T_2000 = eq(special_entry.tag_v, hv_17) node _T_2001 = and(_T_2000, _WIRE_134.fragmented_superpage) when _T_2001 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2002 = eq(hg_17, UInt<1>(0h0)) node _T_2003 = and(_T_2002, io.sfence.bits.rs2) when _T_2003 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, special_entry.data[0] node _T_2004 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_2004 node _T_2005 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_2005 node _T_2006 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_2006 node _T_2007 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_2007 node _T_2008 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_2008 node _T_2009 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_2009 node _T_2010 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_2010 node _T_2011 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_2011 node _T_2012 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_2012 node _T_2013 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_2013 node _T_2014 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_2014 node _T_2015 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_2015 node _T_2016 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_2016 node _T_2017 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_2017 node _T_2018 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_2018 node _T_2019 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_2019 node _T_2020 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_2020 node _T_2021 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_2021 node _T_2022 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_2022 node _T_2023 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_2023 node _T_2024 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_2024 node _T_2025 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_2025 node _T_2026 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_2026 node _T_2027 = eq(special_entry.tag_v, hv_17) node _T_2028 = eq(_WIRE_136.g, UInt<1>(0h0)) node _T_2029 = and(_T_2027, _T_2028) when _T_2029 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2030 = or(hv_17, hg_17) wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, special_entry.data[0] node _T_2031 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_2031 node _T_2032 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_2032 node _T_2033 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_2033 node _T_2034 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_2034 node _T_2035 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_2035 node _T_2036 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_2036 node _T_2037 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_2037 node _T_2038 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_2038 node _T_2039 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_2039 node _T_2040 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_2040 node _T_2041 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_2041 node _T_2042 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_2042 node _T_2043 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_2043 node _T_2044 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_2044 node _T_2045 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_2045 node _T_2046 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_2046 node _T_2047 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_2047 node _T_2048 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_2048 node _T_2049 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_2049 node _T_2050 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_2050 node _T_2051 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_2051 node _T_2052 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_2052 node _T_2053 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_2053 node _T_2054 = eq(special_entry.tag_v, _T_2030) when _T_2054 : connect special_entry.valid[0], UInt<1>(0h0) node _T_2055 = and(io.req.ready, io.req.valid) node _T_2056 = and(_T_2055, vsatp_mode_mismatch) when _T_2056 : wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][0].data[0] node _T_2057 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_2057 node _T_2058 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_2058 node _T_2059 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_2059 node _T_2060 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_2060 node _T_2061 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_2061 node _T_2062 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_2062 node _T_2063 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_2063 node _T_2064 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_2064 node _T_2065 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_2065 node _T_2066 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_2066 node _T_2067 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_2067 node _T_2068 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_2068 node _T_2069 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_2069 node _T_2070 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_2070 node _T_2071 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_2071 node _T_2072 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_2072 node _T_2073 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_2073 node _T_2074 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_2074 node _T_2075 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_2075 node _T_2076 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_2076 node _T_2077 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_2077 node _T_2078 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_2078 node _T_2079 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_2079 node _T_2080 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_2080 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][1].data[0] node _T_2081 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_2081 node _T_2082 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_2082 node _T_2083 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_2083 node _T_2084 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_2084 node _T_2085 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_2085 node _T_2086 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_2086 node _T_2087 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_2087 node _T_2088 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_2088 node _T_2089 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_2089 node _T_2090 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_2090 node _T_2091 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_2091 node _T_2092 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_2092 node _T_2093 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_2093 node _T_2094 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_2094 node _T_2095 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_2095 node _T_2096 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_2096 node _T_2097 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_2097 node _T_2098 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_2098 node _T_2099 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_2099 node _T_2100 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_2100 node _T_2101 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_2101 node _T_2102 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_2102 node _T_2103 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_2103 node _T_2104 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_2104 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][2].data[0] node _T_2105 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_2105 node _T_2106 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_2106 node _T_2107 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_2107 node _T_2108 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_2108 node _T_2109 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_2109 node _T_2110 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_2110 node _T_2111 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_2111 node _T_2112 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_2112 node _T_2113 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_2113 node _T_2114 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_2114 node _T_2115 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_2115 node _T_2116 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_2116 node _T_2117 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_2117 node _T_2118 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_2118 node _T_2119 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_2119 node _T_2120 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_2120 node _T_2121 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_2121 node _T_2122 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_2122 node _T_2123 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_2123 node _T_2124 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_2124 node _T_2125 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_2125 node _T_2126 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_2126 node _T_2127 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_2127 node _T_2128 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_2128 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][3].data[0] node _T_2129 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_2129 node _T_2130 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_2130 node _T_2131 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_2131 node _T_2132 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_2132 node _T_2133 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_2133 node _T_2134 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_2134 node _T_2135 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_2135 node _T_2136 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_2136 node _T_2137 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_2137 node _T_2138 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_2138 node _T_2139 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_2139 node _T_2140 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_2140 node _T_2141 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2141 node _T_2142 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2142 node _T_2143 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2143 node _T_2144 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2144 node _T_2145 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2145 node _T_2146 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2146 node _T_2147 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2147 node _T_2148 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2148 node _T_2149 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2149 node _T_2150 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2150 node _T_2151 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2151 node _T_2152 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_2152 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[1][0].data[0] node _T_2153 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2153 node _T_2154 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2154 node _T_2155 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2155 node _T_2156 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2156 node _T_2157 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2157 node _T_2158 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2158 node _T_2159 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2159 node _T_2160 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2160 node _T_2161 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2161 node _T_2162 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2162 node _T_2163 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2163 node _T_2164 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2164 node _T_2165 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2165 node _T_2166 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2166 node _T_2167 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2167 node _T_2168 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2168 node _T_2169 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2169 node _T_2170 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2170 node _T_2171 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2171 node _T_2172 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2172 node _T_2173 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2173 node _T_2174 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2174 node _T_2175 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2175 node _T_2176 = eq(sectored_entries[1][0].tag_v, UInt<1>(0h1)) when _T_2176 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[1][1].data[0] node _T_2177 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2177 node _T_2178 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2178 node _T_2179 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2179 node _T_2180 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2180 node _T_2181 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2181 node _T_2182 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2182 node _T_2183 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2183 node _T_2184 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2184 node _T_2185 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2185 node _T_2186 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2186 node _T_2187 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2187 node _T_2188 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2188 node _T_2189 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2189 node _T_2190 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2190 node _T_2191 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2191 node _T_2192 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2192 node _T_2193 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2193 node _T_2194 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2194 node _T_2195 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2195 node _T_2196 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2196 node _T_2197 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2197 node _T_2198 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2198 node _T_2199 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2199 node _T_2200 = eq(sectored_entries[1][1].tag_v, UInt<1>(0h1)) when _T_2200 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[1][2].data[0] node _T_2201 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2201 node _T_2202 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2202 node _T_2203 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2203 node _T_2204 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2204 node _T_2205 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2205 node _T_2206 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2206 node _T_2207 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2207 node _T_2208 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2208 node _T_2209 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2209 node _T_2210 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2210 node _T_2211 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2211 node _T_2212 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2212 node _T_2213 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2213 node _T_2214 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2214 node _T_2215 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2215 node _T_2216 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2216 node _T_2217 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2217 node _T_2218 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2218 node _T_2219 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2219 node _T_2220 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2220 node _T_2221 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2221 node _T_2222 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2222 node _T_2223 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2223 node _T_2224 = eq(sectored_entries[1][2].tag_v, UInt<1>(0h1)) when _T_2224 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[1][3].data[0] node _T_2225 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2225 node _T_2226 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2226 node _T_2227 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2227 node _T_2228 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2228 node _T_2229 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2229 node _T_2230 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2230 node _T_2231 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2231 node _T_2232 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2232 node _T_2233 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2233 node _T_2234 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2234 node _T_2235 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2235 node _T_2236 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2236 node _T_2237 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2237 node _T_2238 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2238 node _T_2239 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2239 node _T_2240 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2240 node _T_2241 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2241 node _T_2242 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2242 node _T_2243 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2243 node _T_2244 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2244 node _T_2245 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2245 node _T_2246 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2246 node _T_2247 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2247 node _T_2248 = eq(sectored_entries[1][3].tag_v, UInt<1>(0h1)) when _T_2248 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[2][0].data[0] node _T_2249 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2249 node _T_2250 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2250 node _T_2251 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2251 node _T_2252 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2252 node _T_2253 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2253 node _T_2254 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2254 node _T_2255 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2255 node _T_2256 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2256 node _T_2257 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2257 node _T_2258 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2258 node _T_2259 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2259 node _T_2260 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2260 node _T_2261 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2261 node _T_2262 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2262 node _T_2263 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2263 node _T_2264 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2264 node _T_2265 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2265 node _T_2266 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2266 node _T_2267 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2267 node _T_2268 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2268 node _T_2269 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2269 node _T_2270 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2270 node _T_2271 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2271 node _T_2272 = eq(sectored_entries[2][0].tag_v, UInt<1>(0h1)) when _T_2272 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[2][1].data[0] node _T_2273 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2273 node _T_2274 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2274 node _T_2275 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2275 node _T_2276 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2276 node _T_2277 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2277 node _T_2278 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2278 node _T_2279 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2279 node _T_2280 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2280 node _T_2281 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2281 node _T_2282 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2282 node _T_2283 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2283 node _T_2284 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2284 node _T_2285 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2285 node _T_2286 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2286 node _T_2287 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2287 node _T_2288 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2288 node _T_2289 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2289 node _T_2290 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2290 node _T_2291 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2291 node _T_2292 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2292 node _T_2293 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2293 node _T_2294 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2294 node _T_2295 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2295 node _T_2296 = eq(sectored_entries[2][1].tag_v, UInt<1>(0h1)) when _T_2296 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[2][2].data[0] node _T_2297 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2297 node _T_2298 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2298 node _T_2299 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2299 node _T_2300 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2300 node _T_2301 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2301 node _T_2302 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2302 node _T_2303 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2303 node _T_2304 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2304 node _T_2305 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2305 node _T_2306 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2306 node _T_2307 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2307 node _T_2308 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2308 node _T_2309 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2309 node _T_2310 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2310 node _T_2311 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2311 node _T_2312 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2312 node _T_2313 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2313 node _T_2314 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2314 node _T_2315 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2315 node _T_2316 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2316 node _T_2317 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2317 node _T_2318 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2318 node _T_2319 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2319 node _T_2320 = eq(sectored_entries[2][2].tag_v, UInt<1>(0h1)) when _T_2320 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[2][3].data[0] node _T_2321 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2321 node _T_2322 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2322 node _T_2323 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2323 node _T_2324 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2324 node _T_2325 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2325 node _T_2326 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2326 node _T_2327 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2327 node _T_2328 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2328 node _T_2329 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2329 node _T_2330 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2330 node _T_2331 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2331 node _T_2332 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2332 node _T_2333 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2333 node _T_2334 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2334 node _T_2335 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2335 node _T_2336 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2336 node _T_2337 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2337 node _T_2338 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2338 node _T_2339 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2339 node _T_2340 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2340 node _T_2341 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2341 node _T_2342 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2342 node _T_2343 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2343 node _T_2344 = eq(sectored_entries[2][3].tag_v, UInt<1>(0h1)) when _T_2344 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[3][0].data[0] node _T_2345 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2345 node _T_2346 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2346 node _T_2347 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2347 node _T_2348 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2348 node _T_2349 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2349 node _T_2350 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2350 node _T_2351 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2351 node _T_2352 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2352 node _T_2353 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2353 node _T_2354 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2354 node _T_2355 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2355 node _T_2356 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2356 node _T_2357 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2357 node _T_2358 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2358 node _T_2359 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2359 node _T_2360 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2360 node _T_2361 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2361 node _T_2362 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2362 node _T_2363 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2363 node _T_2364 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2364 node _T_2365 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2365 node _T_2366 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2366 node _T_2367 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2367 node _T_2368 = eq(sectored_entries[3][0].tag_v, UInt<1>(0h1)) when _T_2368 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[3][1].data[0] node _T_2369 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2369 node _T_2370 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2370 node _T_2371 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2371 node _T_2372 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2372 node _T_2373 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2373 node _T_2374 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2374 node _T_2375 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2375 node _T_2376 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2376 node _T_2377 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2377 node _T_2378 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2378 node _T_2379 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2379 node _T_2380 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2380 node _T_2381 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2381 node _T_2382 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2382 node _T_2383 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2383 node _T_2384 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2384 node _T_2385 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2385 node _T_2386 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2386 node _T_2387 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2387 node _T_2388 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2388 node _T_2389 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2389 node _T_2390 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2390 node _T_2391 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2391 node _T_2392 = eq(sectored_entries[3][1].tag_v, UInt<1>(0h1)) when _T_2392 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[3][2].data[0] node _T_2393 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2393 node _T_2394 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2394 node _T_2395 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2395 node _T_2396 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2396 node _T_2397 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2397 node _T_2398 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2398 node _T_2399 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2399 node _T_2400 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2400 node _T_2401 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2401 node _T_2402 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2402 node _T_2403 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2403 node _T_2404 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2404 node _T_2405 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2405 node _T_2406 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2406 node _T_2407 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2407 node _T_2408 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2408 node _T_2409 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2409 node _T_2410 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2410 node _T_2411 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2411 node _T_2412 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2412 node _T_2413 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2413 node _T_2414 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2414 node _T_2415 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2415 node _T_2416 = eq(sectored_entries[3][2].tag_v, UInt<1>(0h1)) when _T_2416 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[3][3].data[0] node _T_2417 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2417 node _T_2418 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2418 node _T_2419 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2419 node _T_2420 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2420 node _T_2421 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2421 node _T_2422 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2422 node _T_2423 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2423 node _T_2424 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2424 node _T_2425 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2425 node _T_2426 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2426 node _T_2427 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2427 node _T_2428 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2428 node _T_2429 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2429 node _T_2430 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2430 node _T_2431 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2431 node _T_2432 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2432 node _T_2433 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2433 node _T_2434 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2434 node _T_2435 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2435 node _T_2436 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2436 node _T_2437 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2437 node _T_2438 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2438 node _T_2439 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2439 node _T_2440 = eq(sectored_entries[3][3].tag_v, UInt<1>(0h1)) when _T_2440 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, superpage_entries[0].data[0] node _T_2441 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2441 node _T_2442 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2442 node _T_2443 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2443 node _T_2444 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2444 node _T_2445 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2445 node _T_2446 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2446 node _T_2447 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2447 node _T_2448 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2448 node _T_2449 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2449 node _T_2450 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2450 node _T_2451 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2451 node _T_2452 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2452 node _T_2453 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2453 node _T_2454 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2454 node _T_2455 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2455 node _T_2456 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2456 node _T_2457 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2457 node _T_2458 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2458 node _T_2459 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2459 node _T_2460 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2460 node _T_2461 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2461 node _T_2462 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2462 node _T_2463 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2463 node _T_2464 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_2464 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, special_entry.data[0] node _T_2465 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2465 node _T_2466 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2466 node _T_2467 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2467 node _T_2468 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2468 node _T_2469 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2469 node _T_2470 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2470 node _T_2471 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2471 node _T_2472 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2472 node _T_2473 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2473 node _T_2474 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2474 node _T_2475 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2475 node _T_2476 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2476 node _T_2477 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2477 node _T_2478 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2478 node _T_2479 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2479 node _T_2480 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2480 node _T_2481 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2481 node _T_2482 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2482 node _T_2483 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2483 node _T_2484 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2484 node _T_2485 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2485 node _T_2486 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2486 node _T_2487 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2487 node _T_2488 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_2488 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_2489 = asUInt(reset) node _T_2490 = or(multipleHits, _T_2489) when _T_2490 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[1][0].valid[0], UInt<1>(0h0) connect sectored_entries[1][1].valid[0], UInt<1>(0h0) connect sectored_entries[1][2].valid[0], UInt<1>(0h0) connect sectored_entries[1][3].valid[0], UInt<1>(0h0) connect sectored_entries[2][0].valid[0], UInt<1>(0h0) connect sectored_entries[2][1].valid[0], UInt<1>(0h0) connect sectored_entries[2][2].valid[0], UInt<1>(0h0) connect sectored_entries[2][3].valid[0], UInt<1>(0h0) connect sectored_entries[3][0].valid[0], UInt<1>(0h0) connect sectored_entries[3][1].valid[0], UInt<1>(0h0) connect sectored_entries[3][2].valid[0], UInt<1>(0h0) connect sectored_entries[3][3].valid[0], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_2491 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_2492 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_2493 = and(io.ptw.req.valid, _T_2492) node _T_2494 = eq(state, UInt<2>(0h3)) node _T_2495 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2496 = and(io.sfence.valid, _T_2495) node _T_2497 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2498 = and(_T_2496, _T_2497) node _T_2499 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2500 = and(io.sfence.valid, _T_2499) node _T_2501 = and(_T_2500, io.sfence.bits.rs2) node _T_2502 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2503 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2504 = and(_T_2502, _T_2503) node _T_2505 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2506 = and(_T_2505, io.sfence.bits.rs2)

module DTLB_18( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [3:0] _misaligned_T = 4'h2; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = 5'h1; // @[TLB.scala:550:69] wire [3:0] _misaligned_T_2 = 4'h1; // @[TLB.scala:550:69] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _ae_array_T_2 = 7'h0; // @[TLB.scala:583:8] wire [6:0] _ae_st_array_T_2 = 7'h0; // @[TLB.scala:588:8] wire [6:0] _ae_st_array_T_4 = 7'h0; // @[TLB.scala:589:8] wire [6:0] _ae_st_array_T_5 = 7'h0; // @[TLB.scala:588:53] wire [6:0] _ae_st_array_T_7 = 7'h0; // @[TLB.scala:590:8] wire [6:0] _ae_st_array_T_8 = 7'h0; // @[TLB.scala:589:53] wire [6:0] _ae_st_array_T_10 = 7'h0; // @[TLB.scala:591:8] wire [6:0] ae_st_array = 7'h0; // @[TLB.scala:590:53] wire [6:0] _must_alloc_array_T_1 = 7'h0; // @[TLB.scala:593:8] wire [6:0] _must_alloc_array_T_3 = 7'h0; // @[TLB.scala:594:8] wire [6:0] _must_alloc_array_T_4 = 7'h0; // @[TLB.scala:593:43] wire [6:0] _must_alloc_array_T_6 = 7'h0; // @[TLB.scala:595:8] wire [6:0] _must_alloc_array_T_7 = 7'h0; // @[TLB.scala:594:43] wire [6:0] _must_alloc_array_T_9 = 7'h0; // @[TLB.scala:596:8] wire [6:0] must_alloc_array = 7'h0; // @[TLB.scala:595:46] wire [6:0] pf_st_array = 7'h0; // @[TLB.scala:598:24] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_pf_st_T_1 = 7'h0; // @[TLB.scala:634:64] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [6:0] _io_resp_ae_st_T = 7'h0; // @[TLB.scala:642:33] wire [6:0] _io_resp_must_alloc_T = 7'h0; // @[TLB.scala:649:43] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h1; // @[TLB.scala:197:28, :318:7] wire [1:0] io_resp_size = 2'h1; // @[TLB.scala:197:28, :318:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 | _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 | _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 | _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 | _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 | _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 | _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 | _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 | _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 | _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {39'h0, io_req_bits_vaddr_0[0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_42 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_42; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_43 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_43; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_43; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {|hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_44 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_44[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_44[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_44[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_44[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 | _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 | _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_44[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 | sector_hits_1 | sector_hits_2 | sector_hits_3; // @[package.scala:81:59] wire _GEN_45 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_46 = ~do_refill | ~io_ptw_resp_bits_homogeneous_0 | io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_47 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_48 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_49 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_50 = ~io_ptw_resp_bits_homogeneous_0 | ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_51 = ~do_refill | _GEN_50 | ~(_T_4 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_52 = ~do_refill | _GEN_50 | ~(_T_4 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_53 = ~do_refill | _GEN_50 | ~(_T_4 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_54 = ~do_refill | _GEN_50 | ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_55 = invalidate_refill & _GEN_47; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_56 = ~do_refill | _GEN_50 | ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_57 = invalidate_refill & _GEN_48; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_58 = invalidate_refill & _GEN_49; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_59 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_60 = ~do_refill | _GEN_50 | ~(_T_6 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_61 = ~do_refill | _GEN_50 | ~(_T_6 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_62 = ~do_refill | _GEN_50 | ~(_T_6 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_63 = ~do_refill | _GEN_50 | ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_64 = ~do_refill | _GEN_50 | ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_65 = ~do_refill | _GEN_50 | ~(_T_8 & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill | _GEN_50 | ~(_T_8 & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill | _GEN_50 | ~(_T_8 & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_68 = ~do_refill | _GEN_50 | ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_69 = ~do_refill | _GEN_50 | ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = ~do_refill | _GEN_50 | ~((&waddr_1) & _GEN_47); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_71 = ~do_refill | _GEN_50 | ~((&waddr_1) & _GEN_48); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_72 = ~do_refill | _GEN_50 | ~((&waddr_1) & _GEN_49); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_73 = ~do_refill | _GEN_50 | ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_74 = ~do_refill | _GEN_50 | ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits | reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_51) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_51 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_51) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_56 ? sectored_entries_0_0_valid_0 : ~_GEN_55 & (_GEN_47 | ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_60) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_60 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_60) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_64 ? sectored_entries_0_1_valid_0 : ~_GEN_55 & (_GEN_47 | ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_65 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_69 ? sectored_entries_0_2_valid_0 : ~_GEN_55 & (_GEN_47 | ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_70) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_70 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_70) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_74 ? sectored_entries_0_3_valid_0 : ~_GEN_55 & (_GEN_47 | ~(~r_sectored_hit_valid & _GEN_47) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_52) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_52 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_52) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_56 ? sectored_entries_1_0_valid_0 : ~_GEN_57 & (_GEN_48 | ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_61) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_61 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_61) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_64 ? sectored_entries_1_1_valid_0 : ~_GEN_57 & (_GEN_48 | ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_66 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_69 ? sectored_entries_1_2_valid_0 : ~_GEN_57 & (_GEN_48 | ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_71) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_71 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_71) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_74 ? sectored_entries_1_3_valid_0 : ~_GEN_57 & (_GEN_48 | ~(~r_sectored_hit_valid & _GEN_48) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_53) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_53 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_53) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_56 ? sectored_entries_2_0_valid_0 : ~_GEN_58 & (_GEN_49 | ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_62) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_62 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_62) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_64 ? sectored_entries_2_1_valid_0 : ~_GEN_58 & (_GEN_49 | ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_67 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_69 ? sectored_entries_2_2_valid_0 : ~_GEN_58 & (_GEN_49 | ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_72) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_72 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_72) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_74 ? sectored_entries_2_3_valid_0 : ~_GEN_58 & (_GEN_49 | ~(~r_sectored_hit_valid & _GEN_49) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_54) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_54 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_54) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_56 ? sectored_entries_3_0_valid_0 : ~_GEN_59 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_63) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_63 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_63) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_64 ? sectored_entries_3_1_valid_0 : ~_GEN_59 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_68) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_68 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_68) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_69 ? sectored_entries_3_2_valid_0 : ~_GEN_59 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_73 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_74 ? sectored_entries_3_3_valid_0 : ~_GEN_59 & ((&r_memIdx) | ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_46) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_46 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_46) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_46 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_45) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_45 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 | io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_45 | special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_140 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_18 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_18 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_141 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_142 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_143 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_144 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_145 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_146 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_438 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_438( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_48 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[10]}} regreset mask : UInt<4>, clock, reset, UInt<4>(0h0) wire in_arb_reqs : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}[4] wire in_arb_vals : UInt<1>[4] node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo) node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0]) node in_arb_filter_hi_1 = cat(in_arb_vals[3], in_arb_vals[2]) node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1) node _in_arb_filter_T_2 = not(mask) node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2) node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3) node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0) node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1) node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2) node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3) node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4) node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5) node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6) node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7) node _in_arb_filter_T_13 = mux(_in_arb_filter_T_12, UInt<8>(0h80), UInt<8>(0h0)) node _in_arb_filter_T_14 = mux(_in_arb_filter_T_11, UInt<8>(0h40), _in_arb_filter_T_13) node _in_arb_filter_T_15 = mux(_in_arb_filter_T_10, UInt<8>(0h20), _in_arb_filter_T_14) node _in_arb_filter_T_16 = mux(_in_arb_filter_T_9, UInt<8>(0h10), _in_arb_filter_T_15) node _in_arb_filter_T_17 = mux(_in_arb_filter_T_8, UInt<8>(0h8), _in_arb_filter_T_16) node _in_arb_filter_T_18 = mux(_in_arb_filter_T_7, UInt<8>(0h4), _in_arb_filter_T_17) node _in_arb_filter_T_19 = mux(_in_arb_filter_T_6, UInt<8>(0h2), _in_arb_filter_T_18) node in_arb_filter = mux(_in_arb_filter_T_5, UInt<8>(0h1), _in_arb_filter_T_19) node _in_arb_sel_T = bits(in_arb_filter, 3, 0) node _in_arb_sel_T_1 = shr(in_arb_filter, 4) node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1) node _T = or(in_arb_vals[0], in_arb_vals[1]) node _T_1 = or(_T, in_arb_vals[2]) node _T_2 = or(_T_1, in_arb_vals[3]) when _T_2 : node _mask_T = not(UInt<1>(0h0)) node _mask_T_1 = not(UInt<2>(0h0)) node _mask_T_2 = not(UInt<3>(0h0)) node _mask_T_3 = not(UInt<4>(0h0)) node _mask_T_4 = bits(in_arb_sel, 0, 0) node _mask_T_5 = bits(in_arb_sel, 1, 1) node _mask_T_6 = bits(in_arb_sel, 2, 2) node _mask_T_7 = bits(in_arb_sel, 3, 3) node _mask_T_8 = mux(_mask_T_4, _mask_T, UInt<1>(0h0)) node _mask_T_9 = mux(_mask_T_5, _mask_T_1, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_6, _mask_T_2, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_7, _mask_T_3, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_8, _mask_T_9) node _mask_T_13 = or(_mask_T_12, _mask_T_10) node _mask_T_14 = or(_mask_T_13, _mask_T_11) wire _mask_WIRE : UInt<4> connect _mask_WIRE, _mask_T_14 connect mask, _mask_WIRE node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T) connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1 node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T) connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1 node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T) connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1 node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T) connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1 node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T) connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1 node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T) connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1 node _in_arb_reqs_0_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_6_T_1 = and(io.req.`0`.bits.vc_sel.`0`[6], _in_arb_reqs_0_0_6_T) connect in_arb_reqs[0].`0`[6], _in_arb_reqs_0_0_6_T_1 node _in_arb_reqs_0_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_7_T_1 = and(io.req.`0`.bits.vc_sel.`0`[7], _in_arb_reqs_0_0_7_T) connect in_arb_reqs[0].`0`[7], _in_arb_reqs_0_0_7_T_1 node _in_arb_reqs_0_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_8_T_1 = and(io.req.`0`.bits.vc_sel.`0`[8], _in_arb_reqs_0_0_8_T) connect in_arb_reqs[0].`0`[8], _in_arb_reqs_0_0_8_T_1 node _in_arb_reqs_0_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_0_9_T_1 = and(io.req.`0`.bits.vc_sel.`0`[9], _in_arb_reqs_0_0_9_T) connect in_arb_reqs[0].`0`[9], _in_arb_reqs_0_0_9_T_1 node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T) connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1 node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T) connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1 node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1]) node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2]) node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3]) node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4]) node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5]) node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`0`[6]) node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`0`[7]) node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`0`[8]) node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_7, in_arb_reqs[0].`0`[9]) node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, in_arb_reqs[0].`1`[0]) node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, in_arb_reqs[0].`2`[0]) node _in_arb_vals_0_T_11 = and(io.req.`0`.valid, _in_arb_vals_0_T_10) connect in_arb_vals[0], _in_arb_vals_0_T_11 node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T) connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1 node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T) connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1 node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T) connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1 node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T) connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1 node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T) connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1 node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T) connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1 node _in_arb_reqs_1_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_6_T_1 = and(io.req.`1`.bits.vc_sel.`0`[6], _in_arb_reqs_1_0_6_T) connect in_arb_reqs[1].`0`[6], _in_arb_reqs_1_0_6_T_1 node _in_arb_reqs_1_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_7_T_1 = and(io.req.`1`.bits.vc_sel.`0`[7], _in_arb_reqs_1_0_7_T) connect in_arb_reqs[1].`0`[7], _in_arb_reqs_1_0_7_T_1 node _in_arb_reqs_1_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_8_T_1 = and(io.req.`1`.bits.vc_sel.`0`[8], _in_arb_reqs_1_0_8_T) connect in_arb_reqs[1].`0`[8], _in_arb_reqs_1_0_8_T_1 node _in_arb_reqs_1_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_0_9_T_1 = and(io.req.`1`.bits.vc_sel.`0`[9], _in_arb_reqs_1_0_9_T) connect in_arb_reqs[1].`0`[9], _in_arb_reqs_1_0_9_T_1 node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T) connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1 node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T) connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1 node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1]) node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2]) node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3]) node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4]) node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5]) node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`0`[6]) node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`0`[7]) node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`0`[8]) node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_7, in_arb_reqs[1].`0`[9]) node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, in_arb_reqs[1].`1`[0]) node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, in_arb_reqs[1].`2`[0]) node _in_arb_vals_1_T_11 = and(io.req.`1`.valid, _in_arb_vals_1_T_10) connect in_arb_vals[1], _in_arb_vals_1_T_11 node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T) connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1 node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T) connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1 node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T) connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1 node _in_arb_reqs_2_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_3_T_1 = and(io.req.`2`.bits.vc_sel.`0`[3], _in_arb_reqs_2_0_3_T) connect in_arb_reqs[2].`0`[3], _in_arb_reqs_2_0_3_T_1 node _in_arb_reqs_2_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_4_T_1 = and(io.req.`2`.bits.vc_sel.`0`[4], _in_arb_reqs_2_0_4_T) connect in_arb_reqs[2].`0`[4], _in_arb_reqs_2_0_4_T_1 node _in_arb_reqs_2_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_5_T_1 = and(io.req.`2`.bits.vc_sel.`0`[5], _in_arb_reqs_2_0_5_T) connect in_arb_reqs[2].`0`[5], _in_arb_reqs_2_0_5_T_1 node _in_arb_reqs_2_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_6_T_1 = and(io.req.`2`.bits.vc_sel.`0`[6], _in_arb_reqs_2_0_6_T) connect in_arb_reqs[2].`0`[6], _in_arb_reqs_2_0_6_T_1 node _in_arb_reqs_2_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_7_T_1 = and(io.req.`2`.bits.vc_sel.`0`[7], _in_arb_reqs_2_0_7_T) connect in_arb_reqs[2].`0`[7], _in_arb_reqs_2_0_7_T_1 node _in_arb_reqs_2_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_8_T_1 = and(io.req.`2`.bits.vc_sel.`0`[8], _in_arb_reqs_2_0_8_T) connect in_arb_reqs[2].`0`[8], _in_arb_reqs_2_0_8_T_1 node _in_arb_reqs_2_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_0_9_T_1 = and(io.req.`2`.bits.vc_sel.`0`[9], _in_arb_reqs_2_0_9_T) connect in_arb_reqs[2].`0`[9], _in_arb_reqs_2_0_9_T_1 node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T) connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1 node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T) connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1 node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1]) node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2]) node _in_arb_vals_2_T_2 = or(_in_arb_vals_2_T_1, in_arb_reqs[2].`0`[3]) node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`0`[4]) node _in_arb_vals_2_T_4 = or(_in_arb_vals_2_T_3, in_arb_reqs[2].`0`[5]) node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`0`[6]) node _in_arb_vals_2_T_6 = or(_in_arb_vals_2_T_5, in_arb_reqs[2].`0`[7]) node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`0`[8]) node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_7, in_arb_reqs[2].`0`[9]) node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, in_arb_reqs[2].`1`[0]) node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, in_arb_reqs[2].`2`[0]) node _in_arb_vals_2_T_11 = and(io.req.`2`.valid, _in_arb_vals_2_T_10) connect in_arb_vals[2], _in_arb_vals_2_T_11 node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T) connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1 node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T) connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1 node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T) connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1 node _in_arb_reqs_3_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_3_T_1 = and(io.req.`3`.bits.vc_sel.`0`[3], _in_arb_reqs_3_0_3_T) connect in_arb_reqs[3].`0`[3], _in_arb_reqs_3_0_3_T_1 node _in_arb_reqs_3_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_4_T_1 = and(io.req.`3`.bits.vc_sel.`0`[4], _in_arb_reqs_3_0_4_T) connect in_arb_reqs[3].`0`[4], _in_arb_reqs_3_0_4_T_1 node _in_arb_reqs_3_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_5_T_1 = and(io.req.`3`.bits.vc_sel.`0`[5], _in_arb_reqs_3_0_5_T) connect in_arb_reqs[3].`0`[5], _in_arb_reqs_3_0_5_T_1 node _in_arb_reqs_3_0_6_T = eq(io.channel_status.`0`[6].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_6_T_1 = and(io.req.`3`.bits.vc_sel.`0`[6], _in_arb_reqs_3_0_6_T) connect in_arb_reqs[3].`0`[6], _in_arb_reqs_3_0_6_T_1 node _in_arb_reqs_3_0_7_T = eq(io.channel_status.`0`[7].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_7_T_1 = and(io.req.`3`.bits.vc_sel.`0`[7], _in_arb_reqs_3_0_7_T) connect in_arb_reqs[3].`0`[7], _in_arb_reqs_3_0_7_T_1 node _in_arb_reqs_3_0_8_T = eq(io.channel_status.`0`[8].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_8_T_1 = and(io.req.`3`.bits.vc_sel.`0`[8], _in_arb_reqs_3_0_8_T) connect in_arb_reqs[3].`0`[8], _in_arb_reqs_3_0_8_T_1 node _in_arb_reqs_3_0_9_T = eq(io.channel_status.`0`[9].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_0_9_T_1 = and(io.req.`3`.bits.vc_sel.`0`[9], _in_arb_reqs_3_0_9_T) connect in_arb_reqs[3].`0`[9], _in_arb_reqs_3_0_9_T_1 node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T) connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1 node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0)) node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T) connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1 node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1]) node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2]) node _in_arb_vals_3_T_2 = or(_in_arb_vals_3_T_1, in_arb_reqs[3].`0`[3]) node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`0`[4]) node _in_arb_vals_3_T_4 = or(_in_arb_vals_3_T_3, in_arb_reqs[3].`0`[5]) node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`0`[6]) node _in_arb_vals_3_T_6 = or(_in_arb_vals_3_T_5, in_arb_reqs[3].`0`[7]) node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`0`[8]) node _in_arb_vals_3_T_8 = or(_in_arb_vals_3_T_7, in_arb_reqs[3].`0`[9]) node _in_arb_vals_3_T_9 = or(_in_arb_vals_3_T_8, in_arb_reqs[3].`1`[0]) node _in_arb_vals_3_T_10 = or(_in_arb_vals_3_T_9, in_arb_reqs[3].`2`[0]) node _in_arb_vals_3_T_11 = and(io.req.`3`.valid, _in_arb_vals_3_T_10) connect in_arb_vals[3], _in_arb_vals_3_T_11 connect io.req.`0`.ready, UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h0) wire in_alloc : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} node _in_flow_T = bits(in_arb_sel, 0, 0) node _in_flow_T_1 = bits(in_arb_sel, 1, 1) node _in_flow_T_2 = bits(in_arb_sel, 2, 2) node _in_flow_T_3 = bits(in_arb_sel, 3, 3) wire in_flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _in_flow_T_4 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_5 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_6 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_7 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0)) node _in_flow_T_8 = or(_in_flow_T_4, _in_flow_T_5) node _in_flow_T_9 = or(_in_flow_T_8, _in_flow_T_6) node _in_flow_T_10 = or(_in_flow_T_9, _in_flow_T_7) wire _in_flow_WIRE : UInt<3> connect _in_flow_WIRE, _in_flow_T_10 connect in_flow.egress_node_id, _in_flow_WIRE node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_13 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_14 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0)) node _in_flow_T_15 = or(_in_flow_T_11, _in_flow_T_12) node _in_flow_T_16 = or(_in_flow_T_15, _in_flow_T_13) node _in_flow_T_17 = or(_in_flow_T_16, _in_flow_T_14) wire _in_flow_WIRE_1 : UInt<4> connect _in_flow_WIRE_1, _in_flow_T_17 connect in_flow.egress_node, _in_flow_WIRE_1 node _in_flow_T_18 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_19 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_20 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_21 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0)) node _in_flow_T_22 = or(_in_flow_T_18, _in_flow_T_19) node _in_flow_T_23 = or(_in_flow_T_22, _in_flow_T_20) node _in_flow_T_24 = or(_in_flow_T_23, _in_flow_T_21) wire _in_flow_WIRE_2 : UInt<2> connect _in_flow_WIRE_2, _in_flow_T_24 connect in_flow.ingress_node_id, _in_flow_WIRE_2 node _in_flow_T_25 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_26 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_27 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_28 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0)) node _in_flow_T_29 = or(_in_flow_T_25, _in_flow_T_26) node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_27) node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_28) wire _in_flow_WIRE_3 : UInt<4> connect _in_flow_WIRE_3, _in_flow_T_31 connect in_flow.ingress_node, _in_flow_WIRE_3 node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0)) node _in_flow_T_36 = or(_in_flow_T_32, _in_flow_T_33) node _in_flow_T_37 = or(_in_flow_T_36, _in_flow_T_34) node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_35) wire _in_flow_WIRE_4 : UInt<3> connect _in_flow_WIRE_4, _in_flow_T_38 connect in_flow.vnet_id, _in_flow_WIRE_4 node _in_vc_T = bits(in_arb_sel, 0, 0) node _in_vc_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_T_3 = bits(in_arb_sel, 3, 3) node _in_vc_T_4 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_5 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_6 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_7 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0)) node _in_vc_T_8 = or(_in_vc_T_4, _in_vc_T_5) node _in_vc_T_9 = or(_in_vc_T_8, _in_vc_T_6) node _in_vc_T_10 = or(_in_vc_T_9, _in_vc_T_7) wire in_vc : UInt<4> connect in_vc, _in_vc_T_10 node _in_vc_sel_T = bits(in_arb_sel, 0, 0) node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1) node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2) node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3) wire in_vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _in_vc_sel_WIRE : UInt<1>[10] node _in_vc_sel_T_4 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_5 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_6 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_7 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0)) node _in_vc_sel_T_8 = or(_in_vc_sel_T_4, _in_vc_sel_T_5) node _in_vc_sel_T_9 = or(_in_vc_sel_T_8, _in_vc_sel_T_6) node _in_vc_sel_T_10 = or(_in_vc_sel_T_9, _in_vc_sel_T_7) wire _in_vc_sel_WIRE_1 : UInt<1> connect _in_vc_sel_WIRE_1, _in_vc_sel_T_10 connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1 node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_13 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_14 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0)) node _in_vc_sel_T_15 = or(_in_vc_sel_T_11, _in_vc_sel_T_12) node _in_vc_sel_T_16 = or(_in_vc_sel_T_15, _in_vc_sel_T_13) node _in_vc_sel_T_17 = or(_in_vc_sel_T_16, _in_vc_sel_T_14) wire _in_vc_sel_WIRE_2 : UInt<1> connect _in_vc_sel_WIRE_2, _in_vc_sel_T_17 connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2 node _in_vc_sel_T_18 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_19 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_20 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_21 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0)) node _in_vc_sel_T_22 = or(_in_vc_sel_T_18, _in_vc_sel_T_19) node _in_vc_sel_T_23 = or(_in_vc_sel_T_22, _in_vc_sel_T_20) node _in_vc_sel_T_24 = or(_in_vc_sel_T_23, _in_vc_sel_T_21) wire _in_vc_sel_WIRE_3 : UInt<1> connect _in_vc_sel_WIRE_3, _in_vc_sel_T_24 connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3 node _in_vc_sel_T_25 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_26 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_27 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_28 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[3], UInt<1>(0h0)) node _in_vc_sel_T_29 = or(_in_vc_sel_T_25, _in_vc_sel_T_26) node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_27) node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_28) wire _in_vc_sel_WIRE_4 : UInt<1> connect _in_vc_sel_WIRE_4, _in_vc_sel_T_31 connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4 node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[4], UInt<1>(0h0)) node _in_vc_sel_T_36 = or(_in_vc_sel_T_32, _in_vc_sel_T_33) node _in_vc_sel_T_37 = or(_in_vc_sel_T_36, _in_vc_sel_T_34) node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_35) wire _in_vc_sel_WIRE_5 : UInt<1> connect _in_vc_sel_WIRE_5, _in_vc_sel_T_38 connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5 node _in_vc_sel_T_39 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_40 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_41 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_42 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[5], UInt<1>(0h0)) node _in_vc_sel_T_43 = or(_in_vc_sel_T_39, _in_vc_sel_T_40) node _in_vc_sel_T_44 = or(_in_vc_sel_T_43, _in_vc_sel_T_41) node _in_vc_sel_T_45 = or(_in_vc_sel_T_44, _in_vc_sel_T_42) wire _in_vc_sel_WIRE_6 : UInt<1> connect _in_vc_sel_WIRE_6, _in_vc_sel_T_45 connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6 node _in_vc_sel_T_46 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_47 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_48 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_49 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[6], UInt<1>(0h0)) node _in_vc_sel_T_50 = or(_in_vc_sel_T_46, _in_vc_sel_T_47) node _in_vc_sel_T_51 = or(_in_vc_sel_T_50, _in_vc_sel_T_48) node _in_vc_sel_T_52 = or(_in_vc_sel_T_51, _in_vc_sel_T_49) wire _in_vc_sel_WIRE_7 : UInt<1> connect _in_vc_sel_WIRE_7, _in_vc_sel_T_52 connect _in_vc_sel_WIRE[6], _in_vc_sel_WIRE_7 node _in_vc_sel_T_53 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_54 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_55 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_56 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[7], UInt<1>(0h0)) node _in_vc_sel_T_57 = or(_in_vc_sel_T_53, _in_vc_sel_T_54) node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_55) node _in_vc_sel_T_59 = or(_in_vc_sel_T_58, _in_vc_sel_T_56) wire _in_vc_sel_WIRE_8 : UInt<1> connect _in_vc_sel_WIRE_8, _in_vc_sel_T_59 connect _in_vc_sel_WIRE[7], _in_vc_sel_WIRE_8 node _in_vc_sel_T_60 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_61 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_62 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_63 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[8], UInt<1>(0h0)) node _in_vc_sel_T_64 = or(_in_vc_sel_T_60, _in_vc_sel_T_61) node _in_vc_sel_T_65 = or(_in_vc_sel_T_64, _in_vc_sel_T_62) node _in_vc_sel_T_66 = or(_in_vc_sel_T_65, _in_vc_sel_T_63) wire _in_vc_sel_WIRE_9 : UInt<1> connect _in_vc_sel_WIRE_9, _in_vc_sel_T_66 connect _in_vc_sel_WIRE[8], _in_vc_sel_WIRE_9 node _in_vc_sel_T_67 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_68 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_69 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_70 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[9], UInt<1>(0h0)) node _in_vc_sel_T_71 = or(_in_vc_sel_T_67, _in_vc_sel_T_68) node _in_vc_sel_T_72 = or(_in_vc_sel_T_71, _in_vc_sel_T_69) node _in_vc_sel_T_73 = or(_in_vc_sel_T_72, _in_vc_sel_T_70) wire _in_vc_sel_WIRE_10 : UInt<1> connect _in_vc_sel_WIRE_10, _in_vc_sel_T_73 connect _in_vc_sel_WIRE[9], _in_vc_sel_WIRE_10 connect in_vc_sel.`0`, _in_vc_sel_WIRE wire _in_vc_sel_WIRE_11 : UInt<1>[1] node _in_vc_sel_T_74 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_75 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_76 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_77 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0)) node _in_vc_sel_T_78 = or(_in_vc_sel_T_74, _in_vc_sel_T_75) node _in_vc_sel_T_79 = or(_in_vc_sel_T_78, _in_vc_sel_T_76) node _in_vc_sel_T_80 = or(_in_vc_sel_T_79, _in_vc_sel_T_77) wire _in_vc_sel_WIRE_12 : UInt<1> connect _in_vc_sel_WIRE_12, _in_vc_sel_T_80 connect _in_vc_sel_WIRE_11[0], _in_vc_sel_WIRE_12 connect in_vc_sel.`1`, _in_vc_sel_WIRE_11 wire _in_vc_sel_WIRE_13 : UInt<1>[1] node _in_vc_sel_T_81 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_82 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_83 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_84 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0)) node _in_vc_sel_T_85 = or(_in_vc_sel_T_81, _in_vc_sel_T_82) node _in_vc_sel_T_86 = or(_in_vc_sel_T_85, _in_vc_sel_T_83) node _in_vc_sel_T_87 = or(_in_vc_sel_T_86, _in_vc_sel_T_84) wire _in_vc_sel_WIRE_14 : UInt<1> connect _in_vc_sel_WIRE_14, _in_vc_sel_T_87 connect _in_vc_sel_WIRE_13[0], _in_vc_sel_WIRE_14 connect in_vc_sel.`2`, _in_vc_sel_WIRE_13 node _T_3 = or(in_arb_vals[0], in_arb_vals[1]) node _T_4 = or(_T_3, in_arb_vals[2]) node _T_5 = or(_T_4, in_arb_vals[3]) node hi = bits(in_arb_sel, 3, 2) node lo = bits(in_arb_sel, 1, 0) node _T_6 = orr(hi) node _T_7 = or(hi, lo) node _T_8 = bits(_T_7, 1, 1) node _T_9 = cat(_T_6, _T_8) node _T_10 = and(io.req.`0`.ready, io.req.`0`.valid) node _T_11 = and(io.req.`1`.ready, io.req.`1`.valid) node _T_12 = and(io.req.`2`.ready, io.req.`2`.valid) node _T_13 = and(io.req.`3`.ready, io.req.`3`.valid) node _T_14 = or(_T_10, _T_11) node _T_15 = or(_T_14, _T_12) node _T_16 = or(_T_15, _T_13) node lo_lo = cat(in_vc_sel.`0`[1], in_vc_sel.`0`[0]) node lo_hi_hi = cat(in_vc_sel.`0`[4], in_vc_sel.`0`[3]) node lo_hi = cat(lo_hi_hi, in_vc_sel.`0`[2]) node lo_1 = cat(lo_hi, lo_lo) node hi_lo = cat(in_vc_sel.`0`[6], in_vc_sel.`0`[5]) node hi_hi_hi = cat(in_vc_sel.`0`[9], in_vc_sel.`0`[8]) node hi_hi = cat(hi_hi_hi, in_vc_sel.`0`[7]) node hi_1 = cat(hi_hi, hi_lo) node _T_17 = cat(hi_1, lo_1) node hi_2 = cat(in_vc_sel.`2`[0], in_vc_sel.`1`[0]) node _T_18 = cat(hi_2, _T_17) regreset mask_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _full_T = not(mask_1) node _full_T_1 = and(_T_18, _full_T) node full = cat(_T_18, _full_T_1) node _oh_T = bits(full, 0, 0) node _oh_T_1 = bits(full, 1, 1) node _oh_T_2 = bits(full, 2, 2) node _oh_T_3 = bits(full, 3, 3) node _oh_T_4 = bits(full, 4, 4) node _oh_T_5 = bits(full, 5, 5) node _oh_T_6 = bits(full, 6, 6) node _oh_T_7 = bits(full, 7, 7) node _oh_T_8 = bits(full, 8, 8) node _oh_T_9 = bits(full, 9, 9) node _oh_T_10 = bits(full, 10, 10) node _oh_T_11 = bits(full, 11, 11) node _oh_T_12 = bits(full, 12, 12) node _oh_T_13 = bits(full, 13, 13) node _oh_T_14 = bits(full, 14, 14) node _oh_T_15 = bits(full, 15, 15) node _oh_T_16 = bits(full, 16, 16) node _oh_T_17 = bits(full, 17, 17) node _oh_T_18 = bits(full, 18, 18) node _oh_T_19 = bits(full, 19, 19) node _oh_T_20 = bits(full, 20, 20) node _oh_T_21 = bits(full, 21, 21) node _oh_T_22 = bits(full, 22, 22) node _oh_T_23 = bits(full, 23, 23) node _oh_T_24 = mux(_oh_T_23, UInt<24>(0h800000), UInt<24>(0h0)) node _oh_T_25 = mux(_oh_T_22, UInt<24>(0h400000), _oh_T_24) node _oh_T_26 = mux(_oh_T_21, UInt<24>(0h200000), _oh_T_25) node _oh_T_27 = mux(_oh_T_20, UInt<24>(0h100000), _oh_T_26) node _oh_T_28 = mux(_oh_T_19, UInt<24>(0h80000), _oh_T_27) node _oh_T_29 = mux(_oh_T_18, UInt<24>(0h40000), _oh_T_28) node _oh_T_30 = mux(_oh_T_17, UInt<24>(0h20000), _oh_T_29) node _oh_T_31 = mux(_oh_T_16, UInt<24>(0h10000), _oh_T_30) node _oh_T_32 = mux(_oh_T_15, UInt<24>(0h8000), _oh_T_31) node _oh_T_33 = mux(_oh_T_14, UInt<24>(0h4000), _oh_T_32) node _oh_T_34 = mux(_oh_T_13, UInt<24>(0h2000), _oh_T_33) node _oh_T_35 = mux(_oh_T_12, UInt<24>(0h1000), _oh_T_34) node _oh_T_36 = mux(_oh_T_11, UInt<24>(0h800), _oh_T_35) node _oh_T_37 = mux(_oh_T_10, UInt<24>(0h400), _oh_T_36) node _oh_T_38 = mux(_oh_T_9, UInt<24>(0h200), _oh_T_37) node _oh_T_39 = mux(_oh_T_8, UInt<24>(0h100), _oh_T_38) node _oh_T_40 = mux(_oh_T_7, UInt<24>(0h80), _oh_T_39) node _oh_T_41 = mux(_oh_T_6, UInt<24>(0h40), _oh_T_40) node _oh_T_42 = mux(_oh_T_5, UInt<24>(0h20), _oh_T_41) node _oh_T_43 = mux(_oh_T_4, UInt<24>(0h10), _oh_T_42) node _oh_T_44 = mux(_oh_T_3, UInt<24>(0h8), _oh_T_43) node _oh_T_45 = mux(_oh_T_2, UInt<24>(0h4), _oh_T_44) node _oh_T_46 = mux(_oh_T_1, UInt<24>(0h2), _oh_T_45) node oh = mux(_oh_T, UInt<24>(0h1), _oh_T_46) node _sel_T = bits(oh, 11, 0) node _sel_T_1 = shr(oh, 12) node sel = or(_sel_T, _sel_T_1) when _T_16 : node _mask_T_15 = bits(sel, 0, 0) node _mask_T_16 = not(UInt<1>(0h0)) node _mask_T_17 = bits(sel, 1, 1) node _mask_T_18 = not(UInt<2>(0h0)) node _mask_T_19 = bits(sel, 2, 2) node _mask_T_20 = not(UInt<3>(0h0)) node _mask_T_21 = bits(sel, 3, 3) node _mask_T_22 = not(UInt<4>(0h0)) node _mask_T_23 = bits(sel, 4, 4) node _mask_T_24 = not(UInt<5>(0h0)) node _mask_T_25 = bits(sel, 5, 5) node _mask_T_26 = not(UInt<6>(0h0)) node _mask_T_27 = bits(sel, 6, 6) node _mask_T_28 = not(UInt<7>(0h0)) node _mask_T_29 = bits(sel, 7, 7) node _mask_T_30 = not(UInt<8>(0h0)) node _mask_T_31 = bits(sel, 8, 8) node _mask_T_32 = not(UInt<9>(0h0)) node _mask_T_33 = bits(sel, 9, 9) node _mask_T_34 = not(UInt<10>(0h0)) node _mask_T_35 = bits(sel, 10, 10) node _mask_T_36 = not(UInt<11>(0h0)) node _mask_T_37 = bits(sel, 11, 11) node _mask_T_38 = not(UInt<12>(0h0)) node _mask_T_39 = mux(_mask_T_37, _mask_T_38, UInt<1>(0h0)) node _mask_T_40 = mux(_mask_T_35, _mask_T_36, _mask_T_39) node _mask_T_41 = mux(_mask_T_33, _mask_T_34, _mask_T_40) node _mask_T_42 = mux(_mask_T_31, _mask_T_32, _mask_T_41) node _mask_T_43 = mux(_mask_T_29, _mask_T_30, _mask_T_42) node _mask_T_44 = mux(_mask_T_27, _mask_T_28, _mask_T_43) node _mask_T_45 = mux(_mask_T_25, _mask_T_26, _mask_T_44) node _mask_T_46 = mux(_mask_T_23, _mask_T_24, _mask_T_45) node _mask_T_47 = mux(_mask_T_21, _mask_T_22, _mask_T_46) node _mask_T_48 = mux(_mask_T_19, _mask_T_20, _mask_T_47) node _mask_T_49 = mux(_mask_T_17, _mask_T_18, _mask_T_48) node _mask_T_50 = mux(_mask_T_15, _mask_T_16, _mask_T_49) connect mask_1, _mask_T_50 wire _WIRE : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _WIRE_1 : UInt<12> connect _WIRE_1, sel node _T_19 = bits(_WIRE_1, 0, 0) connect _WIRE.`0`[0], _T_19 node _T_20 = bits(_WIRE_1, 1, 1) connect _WIRE.`0`[1], _T_20 node _T_21 = bits(_WIRE_1, 2, 2) connect _WIRE.`0`[2], _T_21 node _T_22 = bits(_WIRE_1, 3, 3) connect _WIRE.`0`[3], _T_22 node _T_23 = bits(_WIRE_1, 4, 4) connect _WIRE.`0`[4], _T_23 node _T_24 = bits(_WIRE_1, 5, 5) connect _WIRE.`0`[5], _T_24 node _T_25 = bits(_WIRE_1, 6, 6) connect _WIRE.`0`[6], _T_25 node _T_26 = bits(_WIRE_1, 7, 7) connect _WIRE.`0`[7], _T_26 node _T_27 = bits(_WIRE_1, 8, 8) connect _WIRE.`0`[8], _T_27 node _T_28 = bits(_WIRE_1, 9, 9) connect _WIRE.`0`[9], _T_28 node _T_29 = bits(_WIRE_1, 10, 10) connect _WIRE.`1`[0], _T_29 node _T_30 = bits(_WIRE_1, 11, 11) connect _WIRE.`2`[0], _T_30 wire _WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} connect _WIRE_2.`0`[0], UInt<1>(0h0) connect _WIRE_2.`0`[1], UInt<1>(0h0) connect _WIRE_2.`0`[2], UInt<1>(0h0) connect _WIRE_2.`0`[3], UInt<1>(0h0) connect _WIRE_2.`0`[4], UInt<1>(0h0) connect _WIRE_2.`0`[5], UInt<1>(0h0) connect _WIRE_2.`0`[6], UInt<1>(0h0) connect _WIRE_2.`0`[7], UInt<1>(0h0) connect _WIRE_2.`0`[8], UInt<1>(0h0) connect _WIRE_2.`0`[9], UInt<1>(0h0) connect _WIRE_2.`1`[0], UInt<1>(0h0) connect _WIRE_2.`2`[0], UInt<1>(0h0) node _T_31 = mux(_T_5, _WIRE, _WIRE_2) connect in_alloc.`0`, _T_31.`0` connect in_alloc.`1`, _T_31.`1` connect in_alloc.`2`, _T_31.`2` node _io_req_0_ready_T = bits(in_arb_sel, 0, 0) connect io.req.`0`.ready, _io_req_0_ready_T connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`0`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`0`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`0`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`0`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_1 = cat(io.resp.`0`.vc_sel.`0`[1], io.resp.`0`.vc_sel.`0`[0]) node lo_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[4], io.resp.`0`.vc_sel.`0`[3]) node lo_hi_1 = cat(lo_hi_hi_1, io.resp.`0`.vc_sel.`0`[2]) node lo_2 = cat(lo_hi_1, lo_lo_1) node hi_lo_1 = cat(io.resp.`0`.vc_sel.`0`[6], io.resp.`0`.vc_sel.`0`[5]) node hi_hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[9], io.resp.`0`.vc_sel.`0`[8]) node hi_hi_1 = cat(hi_hi_hi_1, io.resp.`0`.vc_sel.`0`[7]) node hi_3 = cat(hi_hi_1, hi_lo_1) node _T_32 = cat(hi_3, lo_2) node hi_4 = cat(io.resp.`0`.vc_sel.`2`[0], io.resp.`0`.vc_sel.`1`[0]) node _T_33 = cat(hi_4, _T_32) node _T_34 = bits(_T_33, 0, 0) node _T_35 = bits(_T_33, 1, 1) node _T_36 = bits(_T_33, 2, 2) node _T_37 = bits(_T_33, 3, 3) node _T_38 = bits(_T_33, 4, 4) node _T_39 = bits(_T_33, 5, 5) node _T_40 = bits(_T_33, 6, 6) node _T_41 = bits(_T_33, 7, 7) node _T_42 = bits(_T_33, 8, 8) node _T_43 = bits(_T_33, 9, 9) node _T_44 = bits(_T_33, 10, 10) node _T_45 = bits(_T_33, 11, 11) node _T_46 = add(_T_35, _T_36) node _T_47 = bits(_T_46, 1, 0) node _T_48 = add(_T_34, _T_47) node _T_49 = bits(_T_48, 1, 0) node _T_50 = add(_T_38, _T_39) node _T_51 = bits(_T_50, 1, 0) node _T_52 = add(_T_37, _T_51) node _T_53 = bits(_T_52, 1, 0) node _T_54 = add(_T_49, _T_53) node _T_55 = bits(_T_54, 2, 0) node _T_56 = add(_T_41, _T_42) node _T_57 = bits(_T_56, 1, 0) node _T_58 = add(_T_40, _T_57) node _T_59 = bits(_T_58, 1, 0) node _T_60 = add(_T_44, _T_45) node _T_61 = bits(_T_60, 1, 0) node _T_62 = add(_T_43, _T_61) node _T_63 = bits(_T_62, 1, 0) node _T_64 = add(_T_59, _T_63) node _T_65 = bits(_T_64, 2, 0) node _T_66 = add(_T_55, _T_65) node _T_67 = bits(_T_66, 3, 0) node _T_68 = leq(_T_67, UInt<1>(0h1)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf assert(clock, _T_68, UInt<1>(0h1), "") : assert node _io_req_1_ready_T = bits(in_arb_sel, 1, 1) connect io.req.`1`.ready, _io_req_1_ready_T connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`1`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`1`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`1`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`1`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_2 = cat(io.resp.`1`.vc_sel.`0`[1], io.resp.`1`.vc_sel.`0`[0]) node lo_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[4], io.resp.`1`.vc_sel.`0`[3]) node lo_hi_2 = cat(lo_hi_hi_2, io.resp.`1`.vc_sel.`0`[2]) node lo_3 = cat(lo_hi_2, lo_lo_2) node hi_lo_2 = cat(io.resp.`1`.vc_sel.`0`[6], io.resp.`1`.vc_sel.`0`[5]) node hi_hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[9], io.resp.`1`.vc_sel.`0`[8]) node hi_hi_2 = cat(hi_hi_hi_2, io.resp.`1`.vc_sel.`0`[7]) node hi_5 = cat(hi_hi_2, hi_lo_2) node _T_72 = cat(hi_5, lo_3) node hi_6 = cat(io.resp.`1`.vc_sel.`2`[0], io.resp.`1`.vc_sel.`1`[0]) node _T_73 = cat(hi_6, _T_72) node _T_74 = bits(_T_73, 0, 0) node _T_75 = bits(_T_73, 1, 1) node _T_76 = bits(_T_73, 2, 2) node _T_77 = bits(_T_73, 3, 3) node _T_78 = bits(_T_73, 4, 4) node _T_79 = bits(_T_73, 5, 5) node _T_80 = bits(_T_73, 6, 6) node _T_81 = bits(_T_73, 7, 7) node _T_82 = bits(_T_73, 8, 8) node _T_83 = bits(_T_73, 9, 9) node _T_84 = bits(_T_73, 10, 10) node _T_85 = bits(_T_73, 11, 11) node _T_86 = add(_T_75, _T_76) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_74, _T_87) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_78, _T_79) node _T_91 = bits(_T_90, 1, 0) node _T_92 = add(_T_77, _T_91) node _T_93 = bits(_T_92, 1, 0) node _T_94 = add(_T_89, _T_93) node _T_95 = bits(_T_94, 2, 0) node _T_96 = add(_T_81, _T_82) node _T_97 = bits(_T_96, 1, 0) node _T_98 = add(_T_80, _T_97) node _T_99 = bits(_T_98, 1, 0) node _T_100 = add(_T_84, _T_85) node _T_101 = bits(_T_100, 1, 0) node _T_102 = add(_T_83, _T_101) node _T_103 = bits(_T_102, 1, 0) node _T_104 = add(_T_99, _T_103) node _T_105 = bits(_T_104, 2, 0) node _T_106 = add(_T_95, _T_105) node _T_107 = bits(_T_106, 3, 0) node _T_108 = leq(_T_107, UInt<1>(0h1)) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _io_req_2_ready_T = bits(in_arb_sel, 2, 2) connect io.req.`2`.ready, _io_req_2_ready_T connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`2`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`2`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`2`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`2`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`2`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`2`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`2`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_3 = cat(io.resp.`2`.vc_sel.`0`[1], io.resp.`2`.vc_sel.`0`[0]) node lo_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[4], io.resp.`2`.vc_sel.`0`[3]) node lo_hi_3 = cat(lo_hi_hi_3, io.resp.`2`.vc_sel.`0`[2]) node lo_4 = cat(lo_hi_3, lo_lo_3) node hi_lo_3 = cat(io.resp.`2`.vc_sel.`0`[6], io.resp.`2`.vc_sel.`0`[5]) node hi_hi_hi_3 = cat(io.resp.`2`.vc_sel.`0`[9], io.resp.`2`.vc_sel.`0`[8]) node hi_hi_3 = cat(hi_hi_hi_3, io.resp.`2`.vc_sel.`0`[7]) node hi_7 = cat(hi_hi_3, hi_lo_3) node _T_112 = cat(hi_7, lo_4) node hi_8 = cat(io.resp.`2`.vc_sel.`2`[0], io.resp.`2`.vc_sel.`1`[0]) node _T_113 = cat(hi_8, _T_112) node _T_114 = bits(_T_113, 0, 0) node _T_115 = bits(_T_113, 1, 1) node _T_116 = bits(_T_113, 2, 2) node _T_117 = bits(_T_113, 3, 3) node _T_118 = bits(_T_113, 4, 4) node _T_119 = bits(_T_113, 5, 5) node _T_120 = bits(_T_113, 6, 6) node _T_121 = bits(_T_113, 7, 7) node _T_122 = bits(_T_113, 8, 8) node _T_123 = bits(_T_113, 9, 9) node _T_124 = bits(_T_113, 10, 10) node _T_125 = bits(_T_113, 11, 11) node _T_126 = add(_T_115, _T_116) node _T_127 = bits(_T_126, 1, 0) node _T_128 = add(_T_114, _T_127) node _T_129 = bits(_T_128, 1, 0) node _T_130 = add(_T_118, _T_119) node _T_131 = bits(_T_130, 1, 0) node _T_132 = add(_T_117, _T_131) node _T_133 = bits(_T_132, 1, 0) node _T_134 = add(_T_129, _T_133) node _T_135 = bits(_T_134, 2, 0) node _T_136 = add(_T_121, _T_122) node _T_137 = bits(_T_136, 1, 0) node _T_138 = add(_T_120, _T_137) node _T_139 = bits(_T_138, 1, 0) node _T_140 = add(_T_124, _T_125) node _T_141 = bits(_T_140, 1, 0) node _T_142 = add(_T_123, _T_141) node _T_143 = bits(_T_142, 1, 0) node _T_144 = add(_T_139, _T_143) node _T_145 = bits(_T_144, 2, 0) node _T_146 = add(_T_135, _T_145) node _T_147 = bits(_T_146, 3, 0) node _T_148 = leq(_T_147, UInt<1>(0h1)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2 assert(clock, _T_148, UInt<1>(0h1), "") : assert_2 node _io_req_3_ready_T = bits(in_arb_sel, 3, 3) connect io.req.`3`.ready, _io_req_3_ready_T connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0] connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1] connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2] connect io.resp.`3`.vc_sel.`0`[3], in_alloc.`0`[3] connect io.resp.`3`.vc_sel.`0`[4], in_alloc.`0`[4] connect io.resp.`3`.vc_sel.`0`[5], in_alloc.`0`[5] connect io.resp.`3`.vc_sel.`0`[6], in_alloc.`0`[6] connect io.resp.`3`.vc_sel.`0`[7], in_alloc.`0`[7] connect io.resp.`3`.vc_sel.`0`[8], in_alloc.`0`[8] connect io.resp.`3`.vc_sel.`0`[9], in_alloc.`0`[9] connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0] connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0] node lo_lo_4 = cat(io.resp.`3`.vc_sel.`0`[1], io.resp.`3`.vc_sel.`0`[0]) node lo_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[4], io.resp.`3`.vc_sel.`0`[3]) node lo_hi_4 = cat(lo_hi_hi_4, io.resp.`3`.vc_sel.`0`[2]) node lo_5 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(io.resp.`3`.vc_sel.`0`[6], io.resp.`3`.vc_sel.`0`[5]) node hi_hi_hi_4 = cat(io.resp.`3`.vc_sel.`0`[9], io.resp.`3`.vc_sel.`0`[8]) node hi_hi_4 = cat(hi_hi_hi_4, io.resp.`3`.vc_sel.`0`[7]) node hi_9 = cat(hi_hi_4, hi_lo_4) node _T_152 = cat(hi_9, lo_5) node hi_10 = cat(io.resp.`3`.vc_sel.`2`[0], io.resp.`3`.vc_sel.`1`[0]) node _T_153 = cat(hi_10, _T_152) node _T_154 = bits(_T_153, 0, 0) node _T_155 = bits(_T_153, 1, 1) node _T_156 = bits(_T_153, 2, 2) node _T_157 = bits(_T_153, 3, 3) node _T_158 = bits(_T_153, 4, 4) node _T_159 = bits(_T_153, 5, 5) node _T_160 = bits(_T_153, 6, 6) node _T_161 = bits(_T_153, 7, 7) node _T_162 = bits(_T_153, 8, 8) node _T_163 = bits(_T_153, 9, 9) node _T_164 = bits(_T_153, 10, 10) node _T_165 = bits(_T_153, 11, 11) node _T_166 = add(_T_155, _T_156) node _T_167 = bits(_T_166, 1, 0) node _T_168 = add(_T_154, _T_167) node _T_169 = bits(_T_168, 1, 0) node _T_170 = add(_T_158, _T_159) node _T_171 = bits(_T_170, 1, 0) node _T_172 = add(_T_157, _T_171) node _T_173 = bits(_T_172, 1, 0) node _T_174 = add(_T_169, _T_173) node _T_175 = bits(_T_174, 2, 0) node _T_176 = add(_T_161, _T_162) node _T_177 = bits(_T_176, 1, 0) node _T_178 = add(_T_160, _T_177) node _T_179 = bits(_T_178, 1, 0) node _T_180 = add(_T_164, _T_165) node _T_181 = bits(_T_180, 1, 0) node _T_182 = add(_T_163, _T_181) node _T_183 = bits(_T_182, 1, 0) node _T_184 = add(_T_179, _T_183) node _T_185 = bits(_T_184, 2, 0) node _T_186 = add(_T_175, _T_185) node _T_187 = bits(_T_186, 3, 0) node _T_188 = leq(_T_187, UInt<1>(0h1)) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0] connect io.out_allocs.`0`[0].flow, in_flow connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1] connect io.out_allocs.`0`[1].flow, in_flow connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2] connect io.out_allocs.`0`[2].flow, in_flow connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3] connect io.out_allocs.`0`[3].flow, in_flow connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4] connect io.out_allocs.`0`[4].flow, in_flow connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5] connect io.out_allocs.`0`[5].flow, in_flow connect io.out_allocs.`0`[6].alloc, in_alloc.`0`[6] connect io.out_allocs.`0`[6].flow, in_flow connect io.out_allocs.`0`[7].alloc, in_alloc.`0`[7] connect io.out_allocs.`0`[7].flow, in_flow connect io.out_allocs.`0`[8].alloc, in_alloc.`0`[8] connect io.out_allocs.`0`[8].flow, in_flow connect io.out_allocs.`0`[9].alloc, in_alloc.`0`[9] connect io.out_allocs.`0`[9].flow, in_flow connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0] connect io.out_allocs.`1`[0].flow, in_flow connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0] connect io.out_allocs.`2`[0].flow, in_flow

module RotatingSingleVCAllocator_48( // @[ISLIP.scala:43:7] input clock, // @[ISLIP.scala:43:7] input reset, // @[ISLIP.scala:43:7] output io_req_1_ready, // @[VCAllocator.scala:49:14] input io_req_1_valid, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_6, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_7, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_8, // @[VCAllocator.scala:49:14] input io_req_1_bits_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_req_0_ready, // @[VCAllocator.scala:49:14] input io_req_0_valid, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14] input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_6, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_7, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_8, // @[VCAllocator.scala:49:14] output io_resp_1_vc_sel_0_9, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14] output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14] input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_8_occupied, // @[VCAllocator.scala:49:14] input io_channel_status_0_9_occupied, // @[VCAllocator.scala:49:14] output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_8_alloc, // @[VCAllocator.scala:49:14] output io_out_allocs_0_9_alloc // @[VCAllocator.scala:49:14] ); wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39] wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39] reg [3:0] mask; // @[SingleVCAllocator.scala:16:21] wire [3:0] _in_arb_filter_T_3 = {2'h0, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39] wire [7:0] in_arb_filter = _in_arb_filter_T_3[0] ? 8'h1 : _in_arb_filter_T_3[1] ? 8'h2 : _in_arb_filter_T_3[2] ? 8'h4 : _in_arb_filter_T_3[3] ? 8'h8 : in_arb_vals_0 ? 8'h10 : {2'h0, in_arb_vals_1, 5'h0}; // @[OneHot.scala:85:71] wire [3:0] in_arb_sel = in_arb_filter[3:0] | in_arb_filter[7:4]; // @[Mux.scala:50:70] wire _GEN = in_arb_vals_0 | in_arb_vals_1; // @[package.scala:81:59] wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0); // @[package.scala:81:59] wire in_arb_reqs_1_0_8 = io_req_1_bits_vc_sel_0_8 & ~io_channel_status_0_8_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_0_9 = io_req_1_bits_vc_sel_0_9 & ~io_channel_status_0_9_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}] assign in_arb_vals_1 = io_req_1_valid & (io_req_1_bits_vc_sel_0_0 | io_req_1_bits_vc_sel_0_1 | io_req_1_bits_vc_sel_0_2 | io_req_1_bits_vc_sel_0_3 | io_req_1_bits_vc_sel_0_4 | io_req_1_bits_vc_sel_0_5 | io_req_1_bits_vc_sel_0_6 | io_req_1_bits_vc_sel_0_7 | in_arb_reqs_1_0_8 | in_arb_reqs_1_0_9 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0); // @[package.scala:81:59] wire _in_vc_sel_T_5 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_12 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_1; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_19 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_2; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_26 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_3; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_33 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_4; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_40 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_5; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_47 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_6; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_54 = in_arb_sel[1] & io_req_1_bits_vc_sel_0_7; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_61 = in_arb_sel[1] & in_arb_reqs_1_0_8; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_68 = in_arb_sel[1] & in_arb_reqs_1_0_9; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_78 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0; // @[Mux.scala:30:73, :32:36] wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36] reg [11:0] mask_1; // @[ISLIP.scala:17:25] wire [11:0] _full_T_1 = {_in_vc_sel_T_85, _in_vc_sel_T_78, _in_vc_sel_T_68, _in_vc_sel_T_61, _in_vc_sel_T_54, _in_vc_sel_T_47, _in_vc_sel_T_40, _in_vc_sel_T_33, _in_vc_sel_T_26, _in_vc_sel_T_19, _in_vc_sel_T_12, _in_vc_sel_T_5} & ~mask_1; // @[Mux.scala:30:73] wire [23:0] oh = _full_T_1[0] ? 24'h1 : _full_T_1[1] ? 24'h2 : _full_T_1[2] ? 24'h4 : _full_T_1[3] ? 24'h8 : _full_T_1[4] ? 24'h10 : _full_T_1[5] ? 24'h20 : _full_T_1[6] ? 24'h40 : _full_T_1[7] ? 24'h80 : _full_T_1[8] ? 24'h100 : _full_T_1[9] ? 24'h200 : _full_T_1[10] ? 24'h400 : _full_T_1[11] ? 24'h800 : _in_vc_sel_T_5 ? 24'h1000 : _in_vc_sel_T_12 ? 24'h2000 : _in_vc_sel_T_19 ? 24'h4000 : _in_vc_sel_T_26 ? 24'h8000 : _in_vc_sel_T_33 ? 24'h10000 : _in_vc_sel_T_40 ? 24'h20000 : _in_vc_sel_T_47 ? 24'h40000 : _in_vc_sel_T_54 ? 24'h80000 : _in_vc_sel_T_61 ? 24'h100000 : _in_vc_sel_T_68 ? 24'h200000 : _in_vc_sel_T_78 ? 24'h400000 : {_in_vc_sel_T_85, 23'h0}; // @[OneHot.scala:85:71] wire [11:0] sel = oh[11:0] | oh[23:12]; // @[Mux.scala:50:70] wire in_alloc_2_0 = _GEN & sel[11]; // @[package.scala:81:59] wire in_alloc_1_0 = _GEN & sel[10]; // @[package.scala:81:59] wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59] wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59] wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59] wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59] wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] wire in_alloc_0_6 = _GEN & sel[6]; // @[package.scala:81:59] wire in_alloc_0_7 = _GEN & sel[7]; // @[package.scala:81:59] wire in_alloc_0_8 = _GEN & sel[8]; // @[package.scala:81:59] wire in_alloc_0_9 = _GEN & sel[9]; // @[package.scala:81:59]

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_35 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_35 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_35( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_35 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_8 : input clock : Clock input reset : Reset output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire source_ready : UInt<1> connect source_ready, UInt<1>(0h1) node _ridx_T = asAsyncReset(reset) node _ridx_T_1 = and(io.deq.ready, io.deq.valid) node _ridx_T_2 = eq(source_ready, UInt<1>(0h0)) wire ridx_incremented : UInt<4> regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0) connect ridx_ridx_bin, ridx_incremented node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1) node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1) node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1) connect ridx_incremented, _ridx_incremented_T_2 node _ridx_T_3 = shr(ridx_incremented, 1) node ridx = xor(ridx_incremented, _ridx_T_3) inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_17 connect widx_widx_gray.clock, clock connect widx_widx_gray.reset, reset connect widx_widx_gray.io.d, io.async.widx wire widx : UInt<4> connect widx, widx_widx_gray.io.q node _valid_T = neq(ridx, widx) node valid = and(source_ready, _valid_T) node _index_T = bits(ridx, 2, 0) node _index_T_1 = bits(ridx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_8 connect io_deq_bits_deq_bits_reg.clock, clock connect io_deq_bits_deq_bits_reg.reset, reset connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit connect io_deq_bits_deq_bits_reg.io.en, valid wire _io_deq_bits_WIRE : { phit : UInt<32>} wire _io_deq_bits_WIRE_1 : UInt<32> connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0) connect _io_deq_bits_WIRE.phit, _io_deq_bits_T connect io.deq.bits, _io_deq_bits_WIRE node _valid_reg_T = asAsyncReset(reset) regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0) connect valid_reg, valid node _io_deq_valid_T = and(valid_reg, source_ready) connect io.deq.valid, _io_deq_valid_T node _ridx_reg_T = asAsyncReset(reset) regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0) connect ridx_gray, ridx connect io.async.ridx, ridx_gray inst sink_valid_0 of AsyncValidSync_92 inst sink_valid_1 of AsyncValidSync_93 inst source_extend of AsyncValidSync_94 inst source_valid of AsyncValidSync_95 node _sink_valid_0_reset_T = asUInt(reset) node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1) node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2) connect sink_valid_0.reset, _sink_valid_0_reset_T_3 node _sink_valid_1_reset_T = asUInt(reset) node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1) node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2) connect sink_valid_1.reset, _sink_valid_1_reset_T_3 node _source_extend_reset_T = asUInt(reset) node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0)) node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1) node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2) connect source_extend.reset, _source_extend_reset_T_3 node _source_valid_reset_T = asAsyncReset(reset) connect source_valid.reset, _source_valid_reset_T connect sink_valid_0.clock, clock connect sink_valid_1.clock, clock connect source_extend.clock, clock connect source_valid.clock, clock connect sink_valid_0.io.in, UInt<1>(0h1) connect sink_valid_1.io.in, sink_valid_0.io.out connect io.async.safe.ridx_valid, sink_valid_1.io.out connect source_extend.io.in, io.async.safe.widx_valid connect source_valid.io.in, source_extend.io.out connect source_ready, source_valid.io.out node _io_async_safe_sink_reset_n_T = asUInt(reset) node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0)) connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1

module AsyncQueueSink_Phit_8( // @[AsyncQueue.scala:136:7] input clock, // @[AsyncQueue.scala:136:7] input reset, // @[AsyncQueue.scala:136:7] input io_deq_ready, // @[AsyncQueue.scala:139:14] output io_deq_valid, // @[AsyncQueue.scala:139:14] output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14] input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14] output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14] input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14] output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14] input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14] output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14] ); wire _source_extend_io_out; // @[AsyncQueue.scala:175:31] wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33] wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7] wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7] wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7] wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7] wire _ridx_T = reset; // @[AsyncQueue.scala:148:30] wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35] wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34] wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35] wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35] wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35] wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34] wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32] wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29] wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25] wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7] wire io_deq_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7] wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7] wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7] wire source_ready; // @[AsyncQueue.scala:147:30] wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35] wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77] wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77] assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] widx; // @[ShiftReg.scala:48:24] wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24] wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}] wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43] wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}] wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18] wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26] wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26] assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26] reg valid_reg; // @[AsyncQueue.scala:165:56] assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29] assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29] reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55] assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55] wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45] wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}] wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}] wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45] wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}] wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}] wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45] wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}] wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}] assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}] assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25] always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30] if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30] ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:136:7] ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35] if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35] valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56] else // @[AsyncQueue.scala:136:7] valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56] always @(posedge, posedge) always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34] if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34] ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55] else // @[AsyncQueue.scala:136:7] ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55] always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w3 : input clock : Clock input reset : Reset output io : { flip d : UInt<3>, q : UInt<3>, flip en : UInt<1>} reg cdc_reg : UInt<3>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg

module ClockCrossingReg_w3( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [2:0] io_d, // @[SynchronizerReg.scala:195:14] output [2:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [2:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [2:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [2:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MemWriter : input clock : Clock input reset : Reset output io : { flip addr : UInt<21>, flip data : UInt<32>, flip size : UInt<2>, flip en : UInt<1>, mem_addr : UInt<19>, mem_data : UInt<8>[4], mem_masks : UInt<1>[4]} node offset = bits(io.addr, 1, 0) node _shiftedVec_T = shl(offset, 3) node _shiftedVec_T_1 = dshl(io.data, _shiftedVec_T) node _shiftedVec_T_2 = bits(_shiftedVec_T_1, 31, 0) node _shiftedVec_T_3 = bits(_shiftedVec_T_2, 0, 0) node _shiftedVec_T_4 = bits(_shiftedVec_T_2, 1, 1) node _shiftedVec_T_5 = bits(_shiftedVec_T_2, 2, 2) node _shiftedVec_T_6 = bits(_shiftedVec_T_2, 3, 3) node _shiftedVec_T_7 = bits(_shiftedVec_T_2, 4, 4) node _shiftedVec_T_8 = bits(_shiftedVec_T_2, 5, 5) node _shiftedVec_T_9 = bits(_shiftedVec_T_2, 6, 6) node _shiftedVec_T_10 = bits(_shiftedVec_T_2, 7, 7) node _shiftedVec_T_11 = bits(_shiftedVec_T_2, 8, 8) node _shiftedVec_T_12 = bits(_shiftedVec_T_2, 9, 9) node _shiftedVec_T_13 = bits(_shiftedVec_T_2, 10, 10) node _shiftedVec_T_14 = bits(_shiftedVec_T_2, 11, 11) node _shiftedVec_T_15 = bits(_shiftedVec_T_2, 12, 12) node _shiftedVec_T_16 = bits(_shiftedVec_T_2, 13, 13) node _shiftedVec_T_17 = bits(_shiftedVec_T_2, 14, 14) node _shiftedVec_T_18 = bits(_shiftedVec_T_2, 15, 15) node _shiftedVec_T_19 = bits(_shiftedVec_T_2, 16, 16) node _shiftedVec_T_20 = bits(_shiftedVec_T_2, 17, 17) node _shiftedVec_T_21 = bits(_shiftedVec_T_2, 18, 18) node _shiftedVec_T_22 = bits(_shiftedVec_T_2, 19, 19) node _shiftedVec_T_23 = bits(_shiftedVec_T_2, 20, 20) node _shiftedVec_T_24 = bits(_shiftedVec_T_2, 21, 21) node _shiftedVec_T_25 = bits(_shiftedVec_T_2, 22, 22) node _shiftedVec_T_26 = bits(_shiftedVec_T_2, 23, 23) node _shiftedVec_T_27 = bits(_shiftedVec_T_2, 24, 24) node _shiftedVec_T_28 = bits(_shiftedVec_T_2, 25, 25) node _shiftedVec_T_29 = bits(_shiftedVec_T_2, 26, 26) node _shiftedVec_T_30 = bits(_shiftedVec_T_2, 27, 27) node _shiftedVec_T_31 = bits(_shiftedVec_T_2, 28, 28) node _shiftedVec_T_32 = bits(_shiftedVec_T_2, 29, 29) node _shiftedVec_T_33 = bits(_shiftedVec_T_2, 30, 30) node _shiftedVec_T_34 = bits(_shiftedVec_T_2, 31, 31) node shiftedVec_lo_lo = cat(_shiftedVec_T_28, _shiftedVec_T_27) node shiftedVec_lo_hi = cat(_shiftedVec_T_30, _shiftedVec_T_29) node shiftedVec_lo = cat(shiftedVec_lo_hi, shiftedVec_lo_lo) node shiftedVec_hi_lo = cat(_shiftedVec_T_32, _shiftedVec_T_31) node shiftedVec_hi_hi = cat(_shiftedVec_T_34, _shiftedVec_T_33) node shiftedVec_hi = cat(shiftedVec_hi_hi, shiftedVec_hi_lo) node _shiftedVec_T_35 = cat(shiftedVec_hi, shiftedVec_lo) node shiftedVec_lo_lo_1 = cat(_shiftedVec_T_20, _shiftedVec_T_19) node shiftedVec_lo_hi_1 = cat(_shiftedVec_T_22, _shiftedVec_T_21) node shiftedVec_lo_1 = cat(shiftedVec_lo_hi_1, shiftedVec_lo_lo_1) node shiftedVec_hi_lo_1 = cat(_shiftedVec_T_24, _shiftedVec_T_23) node shiftedVec_hi_hi_1 = cat(_shiftedVec_T_26, _shiftedVec_T_25) node shiftedVec_hi_1 = cat(shiftedVec_hi_hi_1, shiftedVec_hi_lo_1) node _shiftedVec_T_36 = cat(shiftedVec_hi_1, shiftedVec_lo_1) node shiftedVec_lo_lo_2 = cat(_shiftedVec_T_12, _shiftedVec_T_11) node shiftedVec_lo_hi_2 = cat(_shiftedVec_T_14, _shiftedVec_T_13) node shiftedVec_lo_2 = cat(shiftedVec_lo_hi_2, shiftedVec_lo_lo_2) node shiftedVec_hi_lo_2 = cat(_shiftedVec_T_16, _shiftedVec_T_15) node shiftedVec_hi_hi_2 = cat(_shiftedVec_T_18, _shiftedVec_T_17) node shiftedVec_hi_2 = cat(shiftedVec_hi_hi_2, shiftedVec_hi_lo_2) node _shiftedVec_T_37 = cat(shiftedVec_hi_2, shiftedVec_lo_2) node shiftedVec_lo_lo_3 = cat(_shiftedVec_T_4, _shiftedVec_T_3) node shiftedVec_lo_hi_3 = cat(_shiftedVec_T_6, _shiftedVec_T_5) node shiftedVec_lo_3 = cat(shiftedVec_lo_hi_3, shiftedVec_lo_lo_3) node shiftedVec_hi_lo_3 = cat(_shiftedVec_T_8, _shiftedVec_T_7) node shiftedVec_hi_hi_3 = cat(_shiftedVec_T_10, _shiftedVec_T_9) node shiftedVec_hi_3 = cat(shiftedVec_hi_hi_3, shiftedVec_hi_lo_3) node _shiftedVec_T_38 = cat(shiftedVec_hi_3, shiftedVec_lo_3) wire shiftedVec : UInt<8>[4] connect shiftedVec[0], _shiftedVec_T_35 connect shiftedVec[1], _shiftedVec_T_36 connect shiftedVec[2], _shiftedVec_T_37 connect shiftedVec[3], _shiftedVec_T_38 node _masks_T = eq(UInt<1>(0h0), io.size) node _masks_T_1 = mux(_masks_T, UInt<1>(0h0), UInt<2>(0h3)) node _masks_T_2 = eq(UInt<1>(0h1), io.size) node _masks_T_3 = mux(_masks_T_2, UInt<1>(0h1), _masks_T_1) node _masks_T_4 = eq(UInt<2>(0h2), io.size) node _masks_T_5 = mux(_masks_T_4, UInt<2>(0h3), _masks_T_3) node _masks_mask_T = dshl(UInt<8>(0h1f), _masks_T_5) node masks_mask = bits(_masks_mask_T, 7, 4) node _masks_maskWithOffset_T = dshl(masks_mask, offset) node masks_maskWithOffset = bits(_masks_maskWithOffset_T, 3, 0) node masks_3 = bits(masks_maskWithOffset, 0, 0) node masks_2 = bits(masks_maskWithOffset, 1, 1) node masks_1 = bits(masks_maskWithOffset, 2, 2) node masks_0 = bits(masks_maskWithOffset, 3, 3) node _io_mem_addr_T = bits(io.addr, 20, 2) connect io.mem_addr, _io_mem_addr_T connect io.mem_data, shiftedVec node _T = and(masks_0, io.en) node _T_1 = and(masks_1, io.en) node _T_2 = and(masks_2, io.en) node _T_3 = and(masks_3, io.en) wire _WIRE : UInt<1>[4] connect _WIRE[0], _T connect _WIRE[1], _T_1 connect _WIRE[2], _T_2 connect _WIRE[3], _T_3 connect io.mem_masks, _WIRE

module MemWriter( // @[memory.scala:133:13] input clock, // @[memory.scala:133:13] input reset, // @[memory.scala:133:13] input [20:0] io_addr, // @[memory.scala:134:21] input [31:0] io_data, // @[memory.scala:134:21] input [1:0] io_size, // @[memory.scala:134:21] input io_en, // @[memory.scala:134:21] output [18:0] io_mem_addr, // @[memory.scala:134:21] output [7:0] io_mem_data_0, // @[memory.scala:134:21] output [7:0] io_mem_data_1, // @[memory.scala:134:21] output [7:0] io_mem_data_2, // @[memory.scala:134:21] output [7:0] io_mem_data_3, // @[memory.scala:134:21] output io_mem_masks_0, // @[memory.scala:134:21] output io_mem_masks_1, // @[memory.scala:134:21] output io_mem_masks_2, // @[memory.scala:134:21] output io_mem_masks_3 // @[memory.scala:134:21] ); wire [20:0] io_addr_0 = io_addr; // @[memory.scala:133:13] wire [31:0] io_data_0 = io_data; // @[memory.scala:133:13] wire [1:0] io_size_0 = io_size; // @[memory.scala:133:13] wire io_en_0 = io_en; // @[memory.scala:133:13] wire [18:0] _io_mem_addr_T; // @[memory.scala:151:32] wire [7:0] shiftedVec_0; // @[memory.scala:84:47] wire [7:0] shiftedVec_1; // @[memory.scala:84:47] wire [7:0] shiftedVec_2; // @[memory.scala:84:47] wire [7:0] shiftedVec_3; // @[memory.scala:84:47] wire [7:0] io_mem_data_0_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_1_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_2_0; // @[memory.scala:133:13] wire [7:0] io_mem_data_3_0; // @[memory.scala:133:13] wire io_mem_masks_0_0; // @[memory.scala:133:13] wire io_mem_masks_1_0; // @[memory.scala:133:13] wire io_mem_masks_2_0; // @[memory.scala:133:13] wire io_mem_masks_3_0; // @[memory.scala:133:13] wire [18:0] io_mem_addr_0; // @[memory.scala:133:13] wire [1:0] offset = io_addr_0[1:0]; // @[memory.scala:133:13, :146:30] wire [4:0] _shiftedVec_T = {offset, 3'h0}; // @[memory.scala:146:30, :147:56] wire [62:0] _shiftedVec_T_1 = {31'h0, io_data_0} << _shiftedVec_T; // @[memory.scala:133:13, :147:{45,56}] wire [31:0] _shiftedVec_T_2 = _shiftedVec_T_1[31:0]; // @[memory.scala:84:54, :147:45] wire _shiftedVec_T_3 = _shiftedVec_T_2[0]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_4 = _shiftedVec_T_2[1]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_5 = _shiftedVec_T_2[2]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_6 = _shiftedVec_T_2[3]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_7 = _shiftedVec_T_2[4]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_8 = _shiftedVec_T_2[5]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_9 = _shiftedVec_T_2[6]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_10 = _shiftedVec_T_2[7]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_11 = _shiftedVec_T_2[8]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_12 = _shiftedVec_T_2[9]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_13 = _shiftedVec_T_2[10]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_14 = _shiftedVec_T_2[11]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_15 = _shiftedVec_T_2[12]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_16 = _shiftedVec_T_2[13]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_17 = _shiftedVec_T_2[14]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_18 = _shiftedVec_T_2[15]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_19 = _shiftedVec_T_2[16]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_20 = _shiftedVec_T_2[17]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_21 = _shiftedVec_T_2[18]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_22 = _shiftedVec_T_2[19]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_23 = _shiftedVec_T_2[20]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_24 = _shiftedVec_T_2[21]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_25 = _shiftedVec_T_2[22]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_26 = _shiftedVec_T_2[23]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_27 = _shiftedVec_T_2[24]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_28 = _shiftedVec_T_2[25]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_29 = _shiftedVec_T_2[26]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_30 = _shiftedVec_T_2[27]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_31 = _shiftedVec_T_2[28]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_32 = _shiftedVec_T_2[29]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_33 = _shiftedVec_T_2[30]; // @[memory.scala:84:{54,62}] wire _shiftedVec_T_34 = _shiftedVec_T_2[31]; // @[memory.scala:84:{54,62}] wire [1:0] shiftedVec_lo_lo = {_shiftedVec_T_28, _shiftedVec_T_27}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi = {_shiftedVec_T_30, _shiftedVec_T_29}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo = {shiftedVec_lo_hi, shiftedVec_lo_lo}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo = {_shiftedVec_T_32, _shiftedVec_T_31}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi = {_shiftedVec_T_34, _shiftedVec_T_33}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi = {shiftedVec_hi_hi, shiftedVec_hi_lo}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_35 = {shiftedVec_hi, shiftedVec_lo}; // @[memory.scala:84:106] assign shiftedVec_0 = _shiftedVec_T_35; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_1 = {_shiftedVec_T_20, _shiftedVec_T_19}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_1 = {_shiftedVec_T_22, _shiftedVec_T_21}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_1 = {shiftedVec_lo_hi_1, shiftedVec_lo_lo_1}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_1 = {_shiftedVec_T_24, _shiftedVec_T_23}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_1 = {_shiftedVec_T_26, _shiftedVec_T_25}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_1 = {shiftedVec_hi_hi_1, shiftedVec_hi_lo_1}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_36 = {shiftedVec_hi_1, shiftedVec_lo_1}; // @[memory.scala:84:106] assign shiftedVec_1 = _shiftedVec_T_36; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_2 = {_shiftedVec_T_12, _shiftedVec_T_11}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_2 = {_shiftedVec_T_14, _shiftedVec_T_13}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_2 = {shiftedVec_lo_hi_2, shiftedVec_lo_lo_2}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_2 = {_shiftedVec_T_16, _shiftedVec_T_15}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_2 = {_shiftedVec_T_18, _shiftedVec_T_17}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_2 = {shiftedVec_hi_hi_2, shiftedVec_hi_lo_2}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_37 = {shiftedVec_hi_2, shiftedVec_lo_2}; // @[memory.scala:84:106] assign shiftedVec_2 = _shiftedVec_T_37; // @[memory.scala:84:{47,106}] wire [1:0] shiftedVec_lo_lo_3 = {_shiftedVec_T_4, _shiftedVec_T_3}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_lo_hi_3 = {_shiftedVec_T_6, _shiftedVec_T_5}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_lo_3 = {shiftedVec_lo_hi_3, shiftedVec_lo_lo_3}; // @[memory.scala:84:106] wire [1:0] shiftedVec_hi_lo_3 = {_shiftedVec_T_8, _shiftedVec_T_7}; // @[memory.scala:84:{62,106}] wire [1:0] shiftedVec_hi_hi_3 = {_shiftedVec_T_10, _shiftedVec_T_9}; // @[memory.scala:84:{62,106}] wire [3:0] shiftedVec_hi_3 = {shiftedVec_hi_hi_3, shiftedVec_hi_lo_3}; // @[memory.scala:84:106] wire [7:0] _shiftedVec_T_38 = {shiftedVec_hi_3, shiftedVec_lo_3}; // @[memory.scala:84:106] assign shiftedVec_3 = _shiftedVec_T_38; // @[memory.scala:84:{47,106}] assign io_mem_data_0_0 = shiftedVec_0; // @[memory.scala:84:47, :133:13] assign io_mem_data_1_0 = shiftedVec_1; // @[memory.scala:84:47, :133:13] assign io_mem_data_2_0 = shiftedVec_2; // @[memory.scala:84:47, :133:13] assign io_mem_data_3_0 = shiftedVec_3; // @[memory.scala:84:47, :133:13] wire _masks_T = io_size_0 == 2'h0; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_1 = _masks_T ? 2'h0 : 2'h3; // @[memory.scala:76:62] wire _masks_T_2 = io_size_0 == 2'h1; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_3 = _masks_T_2 ? 2'h1 : _masks_T_1; // @[memory.scala:76:62] wire _masks_T_4 = io_size_0 == 2'h2; // @[memory.scala:76:62, :133:13] wire [1:0] _masks_T_5 = _masks_T_4 ? 2'h3 : _masks_T_3; // @[memory.scala:76:62] wire [10:0] _masks_mask_T = 11'h1F << _masks_T_5; // @[memory.scala:76:62, :79:38] wire [3:0] masks_mask = _masks_mask_T[7:4]; // @[memory.scala:79:{38,53}] wire [6:0] _masks_maskWithOffset_T = {3'h0, masks_mask} << offset; // @[memory.scala:79:53, :80:34, :146:30, :147:56] wire [3:0] masks_maskWithOffset = _masks_maskWithOffset_T[3:0]; // @[memory.scala:80:{34,55}] wire masks_3 = masks_maskWithOffset[0]; // @[memory.scala:80:55, :81:22] wire masks_2 = masks_maskWithOffset[1]; // @[memory.scala:80:55, :81:22] wire masks_1 = masks_maskWithOffset[2]; // @[memory.scala:80:55, :81:22] wire masks_0 = masks_maskWithOffset[3]; // @[memory.scala:80:55, :81:22] assign _io_mem_addr_T = io_addr_0[20:2]; // @[memory.scala:133:13, :151:32] assign io_mem_addr_0 = _io_mem_addr_T; // @[memory.scala:133:13, :151:32] assign io_mem_masks_0_0 = masks_0 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_1_0 = masks_1 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_2_0 = masks_2 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_masks_3_0 = masks_3 & io_en_0; // @[memory.scala:81:22, :133:13, :153:58] assign io_mem_addr = io_mem_addr_0; // @[memory.scala:133:13] assign io_mem_data_0 = io_mem_data_0_0; // @[memory.scala:133:13] assign io_mem_data_1 = io_mem_data_1_0; // @[memory.scala:133:13] assign io_mem_data_2 = io_mem_data_2_0; // @[memory.scala:133:13] assign io_mem_data_3 = io_mem_data_3_0; // @[memory.scala:133:13] assign io_mem_masks_0 = io_mem_masks_0_0; // @[memory.scala:133:13] assign io_mem_masks_1 = io_mem_masks_1_0; // @[memory.scala:133:13] assign io_mem_masks_2 = io_mem_masks_2_0; // @[memory.scala:133:13] assign io_mem_masks_3 = io_mem_masks_3_0; // @[memory.scala:133:13] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_46 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_46( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_16 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1]}, credit_alloc : { `3` : { alloc : UInt<1>, tail : UInt<1>}[1], `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[2]}, switch_sel : { `3` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_116 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_117 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_118 connect arbs_2.clock, clock connect arbs_2.reset, reset inst arbs_3 of SwitchArbiter_119 connect arbs_3.clock, clock connect arbs_3.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) connect arbs_3.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[4] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_1 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _arbs_3_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[0].valid, _arbs_3_io_in_0_valid_T connect arbs_3.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_3.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0] node _fires_3_T = and(arbs_3.io.in[0].ready, arbs_3.io.in[0].valid) connect fires[3], _fires_3_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) node _io_req_0_0_ready_T_2 = or(_io_req_0_0_ready_T_1, fires[3]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_2 wire fires_1 : UInt<1>[4] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_1 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _arbs_3_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[1].valid, _arbs_3_io_in_1_valid_T connect arbs_3.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_3.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0] node _fires_3_T_1 = and(arbs_3.io.in[1].ready, arbs_3.io.in[1].valid) connect fires_1[3], _fires_3_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) node _io_req_1_0_ready_T_2 = or(_io_req_1_0_ready_T_1, fires_1[3]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_2 wire fires_2 : UInt<1>[4] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_1 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _arbs_3_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[2].valid, _arbs_3_io_in_2_valid_T connect arbs_3.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_3.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0] node _fires_3_T_2 = and(arbs_3.io.in[2].ready, arbs_3.io.in[2].valid) connect fires_2[3], _fires_3_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) node _io_req_2_0_ready_T_2 = or(_io_req_2_0_ready_T_1, fires_2[3]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_2 wire fires_3 : UInt<1>[4] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_1 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_0.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_1.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_2.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _arbs_3_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`3`[0]) connect arbs_3.io.in[3].valid, _arbs_3_io_in_3_valid_T connect arbs_3.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_3.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_3.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_3.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_3.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] connect arbs_3.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0] node _fires_3_T_3 = and(arbs_3.io.in[3].ready, arbs_3.io.in[3].valid) connect fires_3[3], _fires_3_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) node _io_req_3_0_ready_T_2 = or(_io_req_3_0_ready_T_1, fires_3[3]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_2 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 node _io_switch_sel_3_0_0_0_T = bits(arbs_3.io.chosen_oh[0], 0, 0) node _io_switch_sel_3_0_0_0_T_1 = and(arbs_3.io.in[0].valid, _io_switch_sel_3_0_0_0_T) node _io_switch_sel_3_0_0_0_T_2 = and(_io_switch_sel_3_0_0_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`0`[0], _io_switch_sel_3_0_0_0_T_2 node _io_switch_sel_3_0_1_0_T = bits(arbs_3.io.chosen_oh[0], 1, 1) node _io_switch_sel_3_0_1_0_T_1 = and(arbs_3.io.in[1].valid, _io_switch_sel_3_0_1_0_T) node _io_switch_sel_3_0_1_0_T_2 = and(_io_switch_sel_3_0_1_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`1`[0], _io_switch_sel_3_0_1_0_T_2 node _io_switch_sel_3_0_2_0_T = bits(arbs_3.io.chosen_oh[0], 2, 2) node _io_switch_sel_3_0_2_0_T_1 = and(arbs_3.io.in[2].valid, _io_switch_sel_3_0_2_0_T) node _io_switch_sel_3_0_2_0_T_2 = and(_io_switch_sel_3_0_2_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`2`[0], _io_switch_sel_3_0_2_0_T_2 node _io_switch_sel_3_0_3_0_T = bits(arbs_3.io.chosen_oh[0], 3, 3) node _io_switch_sel_3_0_3_0_T_1 = and(arbs_3.io.in[3].valid, _io_switch_sel_3_0_3_0_T) node _io_switch_sel_3_0_3_0_T_2 = and(_io_switch_sel_3_0_3_0_T_1, arbs_3.io.out[0].valid) connect io.switch_sel.`3`[0].`3`[0], _io_switch_sel_3_0_3_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`3`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_2 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_3 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_3 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail node _T_4 = and(arbs_3.io.out[0].valid, arbs_3.io.out[0].bits.vc_sel.`3`[0]) when _T_4 : connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`3`[0].tail, arbs_3.io.out[0].bits.tail

module SwitchAllocator_16( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_2_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_116 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused */), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_0_io_in_2_ready), .io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0), .io_out_0_bits_tail (/* unused */), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_1_io_in_2_ready), .io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_0 (/* unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_2_io_in_2_ready), .io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_0 (/* unused */), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_116 arbs_3 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_2_ready (_arbs_3_io_in_2_ready), .io_in_2_valid (arbs_3_io_in_2_valid), // @[SwitchAllocator.scala:95:37] .io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0), .io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0), .io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0), .io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0), .io_in_2_bits_tail (io_req_2_0_bits_tail), .io_out_0_valid (_arbs_3_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_0 (/* unused */), .io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_3_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid | _arbs_3_io_in_2_ready & arbs_3_io_in_2_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid | _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_3_0_2_0 = arbs_3_io_in_2_valid & _arbs_3_io_chosen_oh_0[2] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule

Generate the Verilog code corresponding to this FIRRTL code module StreamWriter : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, data : UInt<512>, len : UInt<7>, block : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, pool_en : UInt<1>, store_en : UInt<1>}}, tlb : { req : { valid : UInt<1>, bits : { tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, flip resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}}, busy : UInt<1>, flip flush : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg req : { vaddr : UInt<40>, data : UInt<512>, len : UInt<7>, block : UInt<8>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, pool_en : UInt<1>, store_en : UInt<1>}, clock reg data_blocks : UInt<128>[4], clock reg data_single_block : UInt<512>, clock node _data_T = eq(req.block, UInt<1>(0h0)) node data_lo = cat(data_blocks[1], data_blocks[0]) node data_hi = cat(data_blocks[3], data_blocks[2]) node _data_T_1 = cat(data_hi, data_lo) node data = mux(_data_T, data_single_block, _data_T_1) reg bytesSent : UInt<7>, clock node _bytesLeft_T = sub(req.len, bytesSent) node bytesLeft = tail(_bytesLeft_T, 1) regreset xactBusy : UInt<16>, clock, reset, UInt<16>(0h0) node _xactOnehot_T = not(xactBusy) node _xactOnehot_T_1 = bits(_xactOnehot_T, 0, 0) node _xactOnehot_T_2 = bits(_xactOnehot_T, 1, 1) node _xactOnehot_T_3 = bits(_xactOnehot_T, 2, 2) node _xactOnehot_T_4 = bits(_xactOnehot_T, 3, 3) node _xactOnehot_T_5 = bits(_xactOnehot_T, 4, 4) node _xactOnehot_T_6 = bits(_xactOnehot_T, 5, 5) node _xactOnehot_T_7 = bits(_xactOnehot_T, 6, 6) node _xactOnehot_T_8 = bits(_xactOnehot_T, 7, 7) node _xactOnehot_T_9 = bits(_xactOnehot_T, 8, 8) node _xactOnehot_T_10 = bits(_xactOnehot_T, 9, 9) node _xactOnehot_T_11 = bits(_xactOnehot_T, 10, 10) node _xactOnehot_T_12 = bits(_xactOnehot_T, 11, 11) node _xactOnehot_T_13 = bits(_xactOnehot_T, 12, 12) node _xactOnehot_T_14 = bits(_xactOnehot_T, 13, 13) node _xactOnehot_T_15 = bits(_xactOnehot_T, 14, 14) node _xactOnehot_T_16 = bits(_xactOnehot_T, 15, 15) node _xactOnehot_T_17 = mux(_xactOnehot_T_16, UInt<16>(0h8000), UInt<16>(0h0)) node _xactOnehot_T_18 = mux(_xactOnehot_T_15, UInt<16>(0h4000), _xactOnehot_T_17) node _xactOnehot_T_19 = mux(_xactOnehot_T_14, UInt<16>(0h2000), _xactOnehot_T_18) node _xactOnehot_T_20 = mux(_xactOnehot_T_13, UInt<16>(0h1000), _xactOnehot_T_19) node _xactOnehot_T_21 = mux(_xactOnehot_T_12, UInt<16>(0h800), _xactOnehot_T_20) node _xactOnehot_T_22 = mux(_xactOnehot_T_11, UInt<16>(0h400), _xactOnehot_T_21) node _xactOnehot_T_23 = mux(_xactOnehot_T_10, UInt<16>(0h200), _xactOnehot_T_22) node _xactOnehot_T_24 = mux(_xactOnehot_T_9, UInt<16>(0h100), _xactOnehot_T_23) node _xactOnehot_T_25 = mux(_xactOnehot_T_8, UInt<16>(0h80), _xactOnehot_T_24) node _xactOnehot_T_26 = mux(_xactOnehot_T_7, UInt<16>(0h40), _xactOnehot_T_25) node _xactOnehot_T_27 = mux(_xactOnehot_T_6, UInt<16>(0h20), _xactOnehot_T_26) node _xactOnehot_T_28 = mux(_xactOnehot_T_5, UInt<16>(0h10), _xactOnehot_T_27) node _xactOnehot_T_29 = mux(_xactOnehot_T_4, UInt<16>(0h8), _xactOnehot_T_28) node _xactOnehot_T_30 = mux(_xactOnehot_T_3, UInt<16>(0h4), _xactOnehot_T_29) node _xactOnehot_T_31 = mux(_xactOnehot_T_2, UInt<16>(0h2), _xactOnehot_T_30) node xactOnehot = mux(_xactOnehot_T_1, UInt<16>(0h1), _xactOnehot_T_31) node xactId_hi = bits(xactOnehot, 15, 8) node xactId_lo = bits(xactOnehot, 7, 0) node _xactId_T = orr(xactId_hi) node _xactId_T_1 = or(xactId_hi, xactId_lo) node xactId_hi_1 = bits(_xactId_T_1, 7, 4) node xactId_lo_1 = bits(_xactId_T_1, 3, 0) node _xactId_T_2 = orr(xactId_hi_1) node _xactId_T_3 = or(xactId_hi_1, xactId_lo_1) node xactId_hi_2 = bits(_xactId_T_3, 3, 2) node xactId_lo_2 = bits(_xactId_T_3, 1, 0) node _xactId_T_4 = orr(xactId_hi_2) node _xactId_T_5 = or(xactId_hi_2, xactId_lo_2) node _xactId_T_6 = bits(_xactId_T_5, 1, 1) node _xactId_T_7 = cat(_xactId_T_4, _xactId_T_6) node _xactId_T_8 = cat(_xactId_T_2, _xactId_T_7) node xactId = cat(_xactId_T, _xactId_T_8) wire xactBusy_fire : UInt<1> connect xactBusy_fire, UInt<1>(0h0) node _xactBusy_add_T = dshl(UInt<1>(0h1), xactId) node xactBusy_add = mux(xactBusy_fire, _xactBusy_add_T, UInt<1>(0h0)) node _xactBusy_remove_T = and(nodeOut.d.ready, nodeOut.d.valid) node _xactBusy_remove_T_1 = dshl(UInt<1>(0h1), nodeOut.d.bits.source) node _xactBusy_remove_T_2 = mux(_xactBusy_remove_T, _xactBusy_remove_T_1, UInt<1>(0h0)) node xactBusy_remove = not(_xactBusy_remove_T_2) node _xactBusy_T = or(xactBusy, xactBusy_add) node _xactBusy_T_1 = and(_xactBusy_T, xactBusy_remove) connect xactBusy, _xactBusy_T_1 node _state_machine_ready_for_req_T = eq(state, UInt<2>(0h0)) wire state_machine_ready_for_req : UInt<1> connect state_machine_ready_for_req, _state_machine_ready_for_req_T connect io.req.ready, state_machine_ready_for_req node _io_busy_T = orr(xactBusy) node _io_busy_T_1 = neq(state, UInt<2>(0h0)) node _io_busy_T_2 = or(_io_busy_T, _io_busy_T_1) connect io.busy, _io_busy_T_2 node _write_packets_vaddr_aligned_to_size_T = bits(req.vaddr, 38, 4) node write_packets_vaddr_aligned_to_size = cat(_write_packets_vaddr_aligned_to_size_T, UInt<4>(0h0)) node write_packets_vaddr_offset = bits(req.vaddr, 3, 0) node _write_packets_mask_T = geq(UInt<1>(0h0), write_packets_vaddr_offset) node _write_packets_mask_T_1 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_2 = lt(UInt<1>(0h0), _write_packets_mask_T_1) node _write_packets_mask_T_3 = and(_write_packets_mask_T, _write_packets_mask_T_2) node write_packets_mask_0 = and(_write_packets_mask_T_3, UInt<1>(0h1)) node _write_packets_mask_T_4 = geq(UInt<1>(0h1), write_packets_vaddr_offset) node _write_packets_mask_T_5 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_6 = lt(UInt<1>(0h1), _write_packets_mask_T_5) node _write_packets_mask_T_7 = and(_write_packets_mask_T_4, _write_packets_mask_T_6) node write_packets_mask_1 = and(_write_packets_mask_T_7, UInt<1>(0h1)) node _write_packets_mask_T_8 = geq(UInt<2>(0h2), write_packets_vaddr_offset) node _write_packets_mask_T_9 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_10 = lt(UInt<2>(0h2), _write_packets_mask_T_9) node _write_packets_mask_T_11 = and(_write_packets_mask_T_8, _write_packets_mask_T_10) node write_packets_mask_2 = and(_write_packets_mask_T_11, UInt<1>(0h1)) node _write_packets_mask_T_12 = geq(UInt<2>(0h3), write_packets_vaddr_offset) node _write_packets_mask_T_13 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_14 = lt(UInt<2>(0h3), _write_packets_mask_T_13) node _write_packets_mask_T_15 = and(_write_packets_mask_T_12, _write_packets_mask_T_14) node write_packets_mask_3 = and(_write_packets_mask_T_15, UInt<1>(0h1)) node _write_packets_mask_T_16 = geq(UInt<3>(0h4), write_packets_vaddr_offset) node _write_packets_mask_T_17 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_18 = lt(UInt<3>(0h4), _write_packets_mask_T_17) node _write_packets_mask_T_19 = and(_write_packets_mask_T_16, _write_packets_mask_T_18) node write_packets_mask_4 = and(_write_packets_mask_T_19, UInt<1>(0h1)) node _write_packets_mask_T_20 = geq(UInt<3>(0h5), write_packets_vaddr_offset) node _write_packets_mask_T_21 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_22 = lt(UInt<3>(0h5), _write_packets_mask_T_21) node _write_packets_mask_T_23 = and(_write_packets_mask_T_20, _write_packets_mask_T_22) node write_packets_mask_5 = and(_write_packets_mask_T_23, UInt<1>(0h1)) node _write_packets_mask_T_24 = geq(UInt<3>(0h6), write_packets_vaddr_offset) node _write_packets_mask_T_25 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_26 = lt(UInt<3>(0h6), _write_packets_mask_T_25) node _write_packets_mask_T_27 = and(_write_packets_mask_T_24, _write_packets_mask_T_26) node write_packets_mask_6 = and(_write_packets_mask_T_27, UInt<1>(0h1)) node _write_packets_mask_T_28 = geq(UInt<3>(0h7), write_packets_vaddr_offset) node _write_packets_mask_T_29 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_30 = lt(UInt<3>(0h7), _write_packets_mask_T_29) node _write_packets_mask_T_31 = and(_write_packets_mask_T_28, _write_packets_mask_T_30) node write_packets_mask_7 = and(_write_packets_mask_T_31, UInt<1>(0h1)) node _write_packets_mask_T_32 = geq(UInt<4>(0h8), write_packets_vaddr_offset) node _write_packets_mask_T_33 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_34 = lt(UInt<4>(0h8), _write_packets_mask_T_33) node _write_packets_mask_T_35 = and(_write_packets_mask_T_32, _write_packets_mask_T_34) node write_packets_mask_8 = and(_write_packets_mask_T_35, UInt<1>(0h1)) node _write_packets_mask_T_36 = geq(UInt<4>(0h9), write_packets_vaddr_offset) node _write_packets_mask_T_37 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_38 = lt(UInt<4>(0h9), _write_packets_mask_T_37) node _write_packets_mask_T_39 = and(_write_packets_mask_T_36, _write_packets_mask_T_38) node write_packets_mask_9 = and(_write_packets_mask_T_39, UInt<1>(0h1)) node _write_packets_mask_T_40 = geq(UInt<4>(0ha), write_packets_vaddr_offset) node _write_packets_mask_T_41 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_42 = lt(UInt<4>(0ha), _write_packets_mask_T_41) node _write_packets_mask_T_43 = and(_write_packets_mask_T_40, _write_packets_mask_T_42) node write_packets_mask_10 = and(_write_packets_mask_T_43, UInt<1>(0h1)) node _write_packets_mask_T_44 = geq(UInt<4>(0hb), write_packets_vaddr_offset) node _write_packets_mask_T_45 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_46 = lt(UInt<4>(0hb), _write_packets_mask_T_45) node _write_packets_mask_T_47 = and(_write_packets_mask_T_44, _write_packets_mask_T_46) node write_packets_mask_11 = and(_write_packets_mask_T_47, UInt<1>(0h1)) node _write_packets_mask_T_48 = geq(UInt<4>(0hc), write_packets_vaddr_offset) node _write_packets_mask_T_49 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_50 = lt(UInt<4>(0hc), _write_packets_mask_T_49) node _write_packets_mask_T_51 = and(_write_packets_mask_T_48, _write_packets_mask_T_50) node write_packets_mask_12 = and(_write_packets_mask_T_51, UInt<1>(0h1)) node _write_packets_mask_T_52 = geq(UInt<4>(0hd), write_packets_vaddr_offset) node _write_packets_mask_T_53 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_54 = lt(UInt<4>(0hd), _write_packets_mask_T_53) node _write_packets_mask_T_55 = and(_write_packets_mask_T_52, _write_packets_mask_T_54) node write_packets_mask_13 = and(_write_packets_mask_T_55, UInt<1>(0h1)) node _write_packets_mask_T_56 = geq(UInt<4>(0he), write_packets_vaddr_offset) node _write_packets_mask_T_57 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_58 = lt(UInt<4>(0he), _write_packets_mask_T_57) node _write_packets_mask_T_59 = and(_write_packets_mask_T_56, _write_packets_mask_T_58) node write_packets_mask_14 = and(_write_packets_mask_T_59, UInt<1>(0h1)) node _write_packets_mask_T_60 = geq(UInt<4>(0hf), write_packets_vaddr_offset) node _write_packets_mask_T_61 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_62 = lt(UInt<4>(0hf), _write_packets_mask_T_61) node _write_packets_mask_T_63 = and(_write_packets_mask_T_60, _write_packets_mask_T_62) node write_packets_mask_15 = and(_write_packets_mask_T_63, UInt<1>(0h1)) node _write_packets_mask_T_64 = geq(UInt<5>(0h10), write_packets_vaddr_offset) node _write_packets_mask_T_65 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_66 = lt(UInt<5>(0h10), _write_packets_mask_T_65) node _write_packets_mask_T_67 = and(_write_packets_mask_T_64, _write_packets_mask_T_66) node write_packets_mask_16 = and(_write_packets_mask_T_67, UInt<1>(0h0)) node _write_packets_mask_T_68 = geq(UInt<5>(0h11), write_packets_vaddr_offset) node _write_packets_mask_T_69 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_70 = lt(UInt<5>(0h11), _write_packets_mask_T_69) node _write_packets_mask_T_71 = and(_write_packets_mask_T_68, _write_packets_mask_T_70) node write_packets_mask_17 = and(_write_packets_mask_T_71, UInt<1>(0h0)) node _write_packets_mask_T_72 = geq(UInt<5>(0h12), write_packets_vaddr_offset) node _write_packets_mask_T_73 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_74 = lt(UInt<5>(0h12), _write_packets_mask_T_73) node _write_packets_mask_T_75 = and(_write_packets_mask_T_72, _write_packets_mask_T_74) node write_packets_mask_18 = and(_write_packets_mask_T_75, UInt<1>(0h0)) node _write_packets_mask_T_76 = geq(UInt<5>(0h13), write_packets_vaddr_offset) node _write_packets_mask_T_77 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_78 = lt(UInt<5>(0h13), _write_packets_mask_T_77) node _write_packets_mask_T_79 = and(_write_packets_mask_T_76, _write_packets_mask_T_78) node write_packets_mask_19 = and(_write_packets_mask_T_79, UInt<1>(0h0)) node _write_packets_mask_T_80 = geq(UInt<5>(0h14), write_packets_vaddr_offset) node _write_packets_mask_T_81 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_82 = lt(UInt<5>(0h14), _write_packets_mask_T_81) node _write_packets_mask_T_83 = and(_write_packets_mask_T_80, _write_packets_mask_T_82) node write_packets_mask_20 = and(_write_packets_mask_T_83, UInt<1>(0h0)) node _write_packets_mask_T_84 = geq(UInt<5>(0h15), write_packets_vaddr_offset) node _write_packets_mask_T_85 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_86 = lt(UInt<5>(0h15), _write_packets_mask_T_85) node _write_packets_mask_T_87 = and(_write_packets_mask_T_84, _write_packets_mask_T_86) node write_packets_mask_21 = and(_write_packets_mask_T_87, UInt<1>(0h0)) node _write_packets_mask_T_88 = geq(UInt<5>(0h16), write_packets_vaddr_offset) node _write_packets_mask_T_89 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_90 = lt(UInt<5>(0h16), _write_packets_mask_T_89) node _write_packets_mask_T_91 = and(_write_packets_mask_T_88, _write_packets_mask_T_90) node write_packets_mask_22 = and(_write_packets_mask_T_91, UInt<1>(0h0)) node _write_packets_mask_T_92 = geq(UInt<5>(0h17), write_packets_vaddr_offset) node _write_packets_mask_T_93 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_94 = lt(UInt<5>(0h17), _write_packets_mask_T_93) node _write_packets_mask_T_95 = and(_write_packets_mask_T_92, _write_packets_mask_T_94) node write_packets_mask_23 = and(_write_packets_mask_T_95, UInt<1>(0h0)) node _write_packets_mask_T_96 = geq(UInt<5>(0h18), write_packets_vaddr_offset) node _write_packets_mask_T_97 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_98 = lt(UInt<5>(0h18), _write_packets_mask_T_97) node _write_packets_mask_T_99 = and(_write_packets_mask_T_96, _write_packets_mask_T_98) node write_packets_mask_24 = and(_write_packets_mask_T_99, UInt<1>(0h0)) node _write_packets_mask_T_100 = geq(UInt<5>(0h19), write_packets_vaddr_offset) node _write_packets_mask_T_101 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_102 = lt(UInt<5>(0h19), _write_packets_mask_T_101) node _write_packets_mask_T_103 = and(_write_packets_mask_T_100, _write_packets_mask_T_102) node write_packets_mask_25 = and(_write_packets_mask_T_103, UInt<1>(0h0)) node _write_packets_mask_T_104 = geq(UInt<5>(0h1a), write_packets_vaddr_offset) node _write_packets_mask_T_105 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_106 = lt(UInt<5>(0h1a), _write_packets_mask_T_105) node _write_packets_mask_T_107 = and(_write_packets_mask_T_104, _write_packets_mask_T_106) node write_packets_mask_26 = and(_write_packets_mask_T_107, UInt<1>(0h0)) node _write_packets_mask_T_108 = geq(UInt<5>(0h1b), write_packets_vaddr_offset) node _write_packets_mask_T_109 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_110 = lt(UInt<5>(0h1b), _write_packets_mask_T_109) node _write_packets_mask_T_111 = and(_write_packets_mask_T_108, _write_packets_mask_T_110) node write_packets_mask_27 = and(_write_packets_mask_T_111, UInt<1>(0h0)) node _write_packets_mask_T_112 = geq(UInt<5>(0h1c), write_packets_vaddr_offset) node _write_packets_mask_T_113 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_114 = lt(UInt<5>(0h1c), _write_packets_mask_T_113) node _write_packets_mask_T_115 = and(_write_packets_mask_T_112, _write_packets_mask_T_114) node write_packets_mask_28 = and(_write_packets_mask_T_115, UInt<1>(0h0)) node _write_packets_mask_T_116 = geq(UInt<5>(0h1d), write_packets_vaddr_offset) node _write_packets_mask_T_117 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_118 = lt(UInt<5>(0h1d), _write_packets_mask_T_117) node _write_packets_mask_T_119 = and(_write_packets_mask_T_116, _write_packets_mask_T_118) node write_packets_mask_29 = and(_write_packets_mask_T_119, UInt<1>(0h0)) node _write_packets_mask_T_120 = geq(UInt<5>(0h1e), write_packets_vaddr_offset) node _write_packets_mask_T_121 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_122 = lt(UInt<5>(0h1e), _write_packets_mask_T_121) node _write_packets_mask_T_123 = and(_write_packets_mask_T_120, _write_packets_mask_T_122) node write_packets_mask_30 = and(_write_packets_mask_T_123, UInt<1>(0h0)) node _write_packets_mask_T_124 = geq(UInt<5>(0h1f), write_packets_vaddr_offset) node _write_packets_mask_T_125 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_126 = lt(UInt<5>(0h1f), _write_packets_mask_T_125) node _write_packets_mask_T_127 = and(_write_packets_mask_T_124, _write_packets_mask_T_126) node write_packets_mask_31 = and(_write_packets_mask_T_127, UInt<1>(0h0)) node _write_packets_mask_T_128 = geq(UInt<6>(0h20), write_packets_vaddr_offset) node _write_packets_mask_T_129 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_130 = lt(UInt<6>(0h20), _write_packets_mask_T_129) node _write_packets_mask_T_131 = and(_write_packets_mask_T_128, _write_packets_mask_T_130) node write_packets_mask_32 = and(_write_packets_mask_T_131, UInt<1>(0h0)) node _write_packets_mask_T_132 = geq(UInt<6>(0h21), write_packets_vaddr_offset) node _write_packets_mask_T_133 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_134 = lt(UInt<6>(0h21), _write_packets_mask_T_133) node _write_packets_mask_T_135 = and(_write_packets_mask_T_132, _write_packets_mask_T_134) node write_packets_mask_33 = and(_write_packets_mask_T_135, UInt<1>(0h0)) node _write_packets_mask_T_136 = geq(UInt<6>(0h22), write_packets_vaddr_offset) node _write_packets_mask_T_137 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_138 = lt(UInt<6>(0h22), _write_packets_mask_T_137) node _write_packets_mask_T_139 = and(_write_packets_mask_T_136, _write_packets_mask_T_138) node write_packets_mask_34 = and(_write_packets_mask_T_139, UInt<1>(0h0)) node _write_packets_mask_T_140 = geq(UInt<6>(0h23), write_packets_vaddr_offset) node _write_packets_mask_T_141 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_142 = lt(UInt<6>(0h23), _write_packets_mask_T_141) node _write_packets_mask_T_143 = and(_write_packets_mask_T_140, _write_packets_mask_T_142) node write_packets_mask_35 = and(_write_packets_mask_T_143, UInt<1>(0h0)) node _write_packets_mask_T_144 = geq(UInt<6>(0h24), write_packets_vaddr_offset) node _write_packets_mask_T_145 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_146 = lt(UInt<6>(0h24), _write_packets_mask_T_145) node _write_packets_mask_T_147 = and(_write_packets_mask_T_144, _write_packets_mask_T_146) node write_packets_mask_36 = and(_write_packets_mask_T_147, UInt<1>(0h0)) node _write_packets_mask_T_148 = geq(UInt<6>(0h25), write_packets_vaddr_offset) node _write_packets_mask_T_149 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_150 = lt(UInt<6>(0h25), _write_packets_mask_T_149) node _write_packets_mask_T_151 = and(_write_packets_mask_T_148, _write_packets_mask_T_150) node write_packets_mask_37 = and(_write_packets_mask_T_151, UInt<1>(0h0)) node _write_packets_mask_T_152 = geq(UInt<6>(0h26), write_packets_vaddr_offset) node _write_packets_mask_T_153 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_154 = lt(UInt<6>(0h26), _write_packets_mask_T_153) node _write_packets_mask_T_155 = and(_write_packets_mask_T_152, _write_packets_mask_T_154) node write_packets_mask_38 = and(_write_packets_mask_T_155, UInt<1>(0h0)) node _write_packets_mask_T_156 = geq(UInt<6>(0h27), write_packets_vaddr_offset) node _write_packets_mask_T_157 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_158 = lt(UInt<6>(0h27), _write_packets_mask_T_157) node _write_packets_mask_T_159 = and(_write_packets_mask_T_156, _write_packets_mask_T_158) node write_packets_mask_39 = and(_write_packets_mask_T_159, UInt<1>(0h0)) node _write_packets_mask_T_160 = geq(UInt<6>(0h28), write_packets_vaddr_offset) node _write_packets_mask_T_161 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_162 = lt(UInt<6>(0h28), _write_packets_mask_T_161) node _write_packets_mask_T_163 = and(_write_packets_mask_T_160, _write_packets_mask_T_162) node write_packets_mask_40 = and(_write_packets_mask_T_163, UInt<1>(0h0)) node _write_packets_mask_T_164 = geq(UInt<6>(0h29), write_packets_vaddr_offset) node _write_packets_mask_T_165 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_166 = lt(UInt<6>(0h29), _write_packets_mask_T_165) node _write_packets_mask_T_167 = and(_write_packets_mask_T_164, _write_packets_mask_T_166) node write_packets_mask_41 = and(_write_packets_mask_T_167, UInt<1>(0h0)) node _write_packets_mask_T_168 = geq(UInt<6>(0h2a), write_packets_vaddr_offset) node _write_packets_mask_T_169 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_170 = lt(UInt<6>(0h2a), _write_packets_mask_T_169) node _write_packets_mask_T_171 = and(_write_packets_mask_T_168, _write_packets_mask_T_170) node write_packets_mask_42 = and(_write_packets_mask_T_171, UInt<1>(0h0)) node _write_packets_mask_T_172 = geq(UInt<6>(0h2b), write_packets_vaddr_offset) node _write_packets_mask_T_173 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_174 = lt(UInt<6>(0h2b), _write_packets_mask_T_173) node _write_packets_mask_T_175 = and(_write_packets_mask_T_172, _write_packets_mask_T_174) node write_packets_mask_43 = and(_write_packets_mask_T_175, UInt<1>(0h0)) node _write_packets_mask_T_176 = geq(UInt<6>(0h2c), write_packets_vaddr_offset) node _write_packets_mask_T_177 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_178 = lt(UInt<6>(0h2c), _write_packets_mask_T_177) node _write_packets_mask_T_179 = and(_write_packets_mask_T_176, _write_packets_mask_T_178) node write_packets_mask_44 = and(_write_packets_mask_T_179, UInt<1>(0h0)) node _write_packets_mask_T_180 = geq(UInt<6>(0h2d), write_packets_vaddr_offset) node _write_packets_mask_T_181 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_182 = lt(UInt<6>(0h2d), _write_packets_mask_T_181) node _write_packets_mask_T_183 = and(_write_packets_mask_T_180, _write_packets_mask_T_182) node write_packets_mask_45 = and(_write_packets_mask_T_183, UInt<1>(0h0)) node _write_packets_mask_T_184 = geq(UInt<6>(0h2e), write_packets_vaddr_offset) node _write_packets_mask_T_185 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_186 = lt(UInt<6>(0h2e), _write_packets_mask_T_185) node _write_packets_mask_T_187 = and(_write_packets_mask_T_184, _write_packets_mask_T_186) node write_packets_mask_46 = and(_write_packets_mask_T_187, UInt<1>(0h0)) node _write_packets_mask_T_188 = geq(UInt<6>(0h2f), write_packets_vaddr_offset) node _write_packets_mask_T_189 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_190 = lt(UInt<6>(0h2f), _write_packets_mask_T_189) node _write_packets_mask_T_191 = and(_write_packets_mask_T_188, _write_packets_mask_T_190) node write_packets_mask_47 = and(_write_packets_mask_T_191, UInt<1>(0h0)) node _write_packets_mask_T_192 = geq(UInt<6>(0h30), write_packets_vaddr_offset) node _write_packets_mask_T_193 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_194 = lt(UInt<6>(0h30), _write_packets_mask_T_193) node _write_packets_mask_T_195 = and(_write_packets_mask_T_192, _write_packets_mask_T_194) node write_packets_mask_48 = and(_write_packets_mask_T_195, UInt<1>(0h0)) node _write_packets_mask_T_196 = geq(UInt<6>(0h31), write_packets_vaddr_offset) node _write_packets_mask_T_197 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_198 = lt(UInt<6>(0h31), _write_packets_mask_T_197) node _write_packets_mask_T_199 = and(_write_packets_mask_T_196, _write_packets_mask_T_198) node write_packets_mask_49 = and(_write_packets_mask_T_199, UInt<1>(0h0)) node _write_packets_mask_T_200 = geq(UInt<6>(0h32), write_packets_vaddr_offset) node _write_packets_mask_T_201 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_202 = lt(UInt<6>(0h32), _write_packets_mask_T_201) node _write_packets_mask_T_203 = and(_write_packets_mask_T_200, _write_packets_mask_T_202) node write_packets_mask_50 = and(_write_packets_mask_T_203, UInt<1>(0h0)) node _write_packets_mask_T_204 = geq(UInt<6>(0h33), write_packets_vaddr_offset) node _write_packets_mask_T_205 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_206 = lt(UInt<6>(0h33), _write_packets_mask_T_205) node _write_packets_mask_T_207 = and(_write_packets_mask_T_204, _write_packets_mask_T_206) node write_packets_mask_51 = and(_write_packets_mask_T_207, UInt<1>(0h0)) node _write_packets_mask_T_208 = geq(UInt<6>(0h34), write_packets_vaddr_offset) node _write_packets_mask_T_209 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_210 = lt(UInt<6>(0h34), _write_packets_mask_T_209) node _write_packets_mask_T_211 = and(_write_packets_mask_T_208, _write_packets_mask_T_210) node write_packets_mask_52 = and(_write_packets_mask_T_211, UInt<1>(0h0)) node _write_packets_mask_T_212 = geq(UInt<6>(0h35), write_packets_vaddr_offset) node _write_packets_mask_T_213 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_214 = lt(UInt<6>(0h35), _write_packets_mask_T_213) node _write_packets_mask_T_215 = and(_write_packets_mask_T_212, _write_packets_mask_T_214) node write_packets_mask_53 = and(_write_packets_mask_T_215, UInt<1>(0h0)) node _write_packets_mask_T_216 = geq(UInt<6>(0h36), write_packets_vaddr_offset) node _write_packets_mask_T_217 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_218 = lt(UInt<6>(0h36), _write_packets_mask_T_217) node _write_packets_mask_T_219 = and(_write_packets_mask_T_216, _write_packets_mask_T_218) node write_packets_mask_54 = and(_write_packets_mask_T_219, UInt<1>(0h0)) node _write_packets_mask_T_220 = geq(UInt<6>(0h37), write_packets_vaddr_offset) node _write_packets_mask_T_221 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_222 = lt(UInt<6>(0h37), _write_packets_mask_T_221) node _write_packets_mask_T_223 = and(_write_packets_mask_T_220, _write_packets_mask_T_222) node write_packets_mask_55 = and(_write_packets_mask_T_223, UInt<1>(0h0)) node _write_packets_mask_T_224 = geq(UInt<6>(0h38), write_packets_vaddr_offset) node _write_packets_mask_T_225 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_226 = lt(UInt<6>(0h38), _write_packets_mask_T_225) node _write_packets_mask_T_227 = and(_write_packets_mask_T_224, _write_packets_mask_T_226) node write_packets_mask_56 = and(_write_packets_mask_T_227, UInt<1>(0h0)) node _write_packets_mask_T_228 = geq(UInt<6>(0h39), write_packets_vaddr_offset) node _write_packets_mask_T_229 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_230 = lt(UInt<6>(0h39), _write_packets_mask_T_229) node _write_packets_mask_T_231 = and(_write_packets_mask_T_228, _write_packets_mask_T_230) node write_packets_mask_57 = and(_write_packets_mask_T_231, UInt<1>(0h0)) node _write_packets_mask_T_232 = geq(UInt<6>(0h3a), write_packets_vaddr_offset) node _write_packets_mask_T_233 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_234 = lt(UInt<6>(0h3a), _write_packets_mask_T_233) node _write_packets_mask_T_235 = and(_write_packets_mask_T_232, _write_packets_mask_T_234) node write_packets_mask_58 = and(_write_packets_mask_T_235, UInt<1>(0h0)) node _write_packets_mask_T_236 = geq(UInt<6>(0h3b), write_packets_vaddr_offset) node _write_packets_mask_T_237 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_238 = lt(UInt<6>(0h3b), _write_packets_mask_T_237) node _write_packets_mask_T_239 = and(_write_packets_mask_T_236, _write_packets_mask_T_238) node write_packets_mask_59 = and(_write_packets_mask_T_239, UInt<1>(0h0)) node _write_packets_mask_T_240 = geq(UInt<6>(0h3c), write_packets_vaddr_offset) node _write_packets_mask_T_241 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_242 = lt(UInt<6>(0h3c), _write_packets_mask_T_241) node _write_packets_mask_T_243 = and(_write_packets_mask_T_240, _write_packets_mask_T_242) node write_packets_mask_60 = and(_write_packets_mask_T_243, UInt<1>(0h0)) node _write_packets_mask_T_244 = geq(UInt<6>(0h3d), write_packets_vaddr_offset) node _write_packets_mask_T_245 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_246 = lt(UInt<6>(0h3d), _write_packets_mask_T_245) node _write_packets_mask_T_247 = and(_write_packets_mask_T_244, _write_packets_mask_T_246) node write_packets_mask_61 = and(_write_packets_mask_T_247, UInt<1>(0h0)) node _write_packets_mask_T_248 = geq(UInt<6>(0h3e), write_packets_vaddr_offset) node _write_packets_mask_T_249 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_250 = lt(UInt<6>(0h3e), _write_packets_mask_T_249) node _write_packets_mask_T_251 = and(_write_packets_mask_T_248, _write_packets_mask_T_250) node write_packets_mask_62 = and(_write_packets_mask_T_251, UInt<1>(0h0)) node _write_packets_mask_T_252 = geq(UInt<6>(0h3f), write_packets_vaddr_offset) node _write_packets_mask_T_253 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_mask_T_254 = lt(UInt<6>(0h3f), _write_packets_mask_T_253) node _write_packets_mask_T_255 = and(_write_packets_mask_T_252, _write_packets_mask_T_254) node write_packets_mask_63 = and(_write_packets_mask_T_255, UInt<1>(0h0)) node _write_packets_bytes_written_T = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_bytes_written_T_1 = gt(_write_packets_bytes_written_T, UInt<5>(0h10)) node _write_packets_bytes_written_T_2 = sub(UInt<5>(0h10), write_packets_vaddr_offset) node _write_packets_bytes_written_T_3 = tail(_write_packets_bytes_written_T_2, 1) node write_packets_bytes_written = mux(_write_packets_bytes_written_T_1, _write_packets_bytes_written_T_3, bytesLeft) wire write_packets_0 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_0.size, UInt<5>(0h10) connect write_packets_0.lg_size, UInt<3>(0h4) wire _write_packets_WIRE : UInt<1>[16] connect _write_packets_WIRE[0], write_packets_mask_0 connect _write_packets_WIRE[1], write_packets_mask_1 connect _write_packets_WIRE[2], write_packets_mask_2 connect _write_packets_WIRE[3], write_packets_mask_3 connect _write_packets_WIRE[4], write_packets_mask_4 connect _write_packets_WIRE[5], write_packets_mask_5 connect _write_packets_WIRE[6], write_packets_mask_6 connect _write_packets_WIRE[7], write_packets_mask_7 connect _write_packets_WIRE[8], write_packets_mask_8 connect _write_packets_WIRE[9], write_packets_mask_9 connect _write_packets_WIRE[10], write_packets_mask_10 connect _write_packets_WIRE[11], write_packets_mask_11 connect _write_packets_WIRE[12], write_packets_mask_12 connect _write_packets_WIRE[13], write_packets_mask_13 connect _write_packets_WIRE[14], write_packets_mask_14 connect _write_packets_WIRE[15], write_packets_mask_15 wire _write_packets_WIRE_1 : UInt<1>[16] connect _write_packets_WIRE_1[0], write_packets_mask_16 connect _write_packets_WIRE_1[1], write_packets_mask_17 connect _write_packets_WIRE_1[2], write_packets_mask_18 connect _write_packets_WIRE_1[3], write_packets_mask_19 connect _write_packets_WIRE_1[4], write_packets_mask_20 connect _write_packets_WIRE_1[5], write_packets_mask_21 connect _write_packets_WIRE_1[6], write_packets_mask_22 connect _write_packets_WIRE_1[7], write_packets_mask_23 connect _write_packets_WIRE_1[8], write_packets_mask_24 connect _write_packets_WIRE_1[9], write_packets_mask_25 connect _write_packets_WIRE_1[10], write_packets_mask_26 connect _write_packets_WIRE_1[11], write_packets_mask_27 connect _write_packets_WIRE_1[12], write_packets_mask_28 connect _write_packets_WIRE_1[13], write_packets_mask_29 connect _write_packets_WIRE_1[14], write_packets_mask_30 connect _write_packets_WIRE_1[15], write_packets_mask_31 wire _write_packets_WIRE_2 : UInt<1>[16] connect _write_packets_WIRE_2[0], write_packets_mask_32 connect _write_packets_WIRE_2[1], write_packets_mask_33 connect _write_packets_WIRE_2[2], write_packets_mask_34 connect _write_packets_WIRE_2[3], write_packets_mask_35 connect _write_packets_WIRE_2[4], write_packets_mask_36 connect _write_packets_WIRE_2[5], write_packets_mask_37 connect _write_packets_WIRE_2[6], write_packets_mask_38 connect _write_packets_WIRE_2[7], write_packets_mask_39 connect _write_packets_WIRE_2[8], write_packets_mask_40 connect _write_packets_WIRE_2[9], write_packets_mask_41 connect _write_packets_WIRE_2[10], write_packets_mask_42 connect _write_packets_WIRE_2[11], write_packets_mask_43 connect _write_packets_WIRE_2[12], write_packets_mask_44 connect _write_packets_WIRE_2[13], write_packets_mask_45 connect _write_packets_WIRE_2[14], write_packets_mask_46 connect _write_packets_WIRE_2[15], write_packets_mask_47 wire _write_packets_WIRE_3 : UInt<1>[16] connect _write_packets_WIRE_3[0], write_packets_mask_48 connect _write_packets_WIRE_3[1], write_packets_mask_49 connect _write_packets_WIRE_3[2], write_packets_mask_50 connect _write_packets_WIRE_3[3], write_packets_mask_51 connect _write_packets_WIRE_3[4], write_packets_mask_52 connect _write_packets_WIRE_3[5], write_packets_mask_53 connect _write_packets_WIRE_3[6], write_packets_mask_54 connect _write_packets_WIRE_3[7], write_packets_mask_55 connect _write_packets_WIRE_3[8], write_packets_mask_56 connect _write_packets_WIRE_3[9], write_packets_mask_57 connect _write_packets_WIRE_3[10], write_packets_mask_58 connect _write_packets_WIRE_3[11], write_packets_mask_59 connect _write_packets_WIRE_3[12], write_packets_mask_60 connect _write_packets_WIRE_3[13], write_packets_mask_61 connect _write_packets_WIRE_3[14], write_packets_mask_62 connect _write_packets_WIRE_3[15], write_packets_mask_63 wire _write_packets_WIRE_4 : UInt<1>[16][4] connect _write_packets_WIRE_4[0], _write_packets_WIRE connect _write_packets_WIRE_4[1], _write_packets_WIRE_1 connect _write_packets_WIRE_4[2], _write_packets_WIRE_2 connect _write_packets_WIRE_4[3], _write_packets_WIRE_3 connect write_packets_0.mask, _write_packets_WIRE_4 connect write_packets_0.vaddr, write_packets_vaddr_aligned_to_size node _write_packets_packet_is_full_T = and(write_packets_mask_0, write_packets_mask_1) node _write_packets_packet_is_full_T_1 = and(_write_packets_packet_is_full_T, write_packets_mask_2) node _write_packets_packet_is_full_T_2 = and(_write_packets_packet_is_full_T_1, write_packets_mask_3) node _write_packets_packet_is_full_T_3 = and(_write_packets_packet_is_full_T_2, write_packets_mask_4) node _write_packets_packet_is_full_T_4 = and(_write_packets_packet_is_full_T_3, write_packets_mask_5) node _write_packets_packet_is_full_T_5 = and(_write_packets_packet_is_full_T_4, write_packets_mask_6) node _write_packets_packet_is_full_T_6 = and(_write_packets_packet_is_full_T_5, write_packets_mask_7) node _write_packets_packet_is_full_T_7 = and(_write_packets_packet_is_full_T_6, write_packets_mask_8) node _write_packets_packet_is_full_T_8 = and(_write_packets_packet_is_full_T_7, write_packets_mask_9) node _write_packets_packet_is_full_T_9 = and(_write_packets_packet_is_full_T_8, write_packets_mask_10) node _write_packets_packet_is_full_T_10 = and(_write_packets_packet_is_full_T_9, write_packets_mask_11) node _write_packets_packet_is_full_T_11 = and(_write_packets_packet_is_full_T_10, write_packets_mask_12) node _write_packets_packet_is_full_T_12 = and(_write_packets_packet_is_full_T_11, write_packets_mask_13) node _write_packets_packet_is_full_T_13 = and(_write_packets_packet_is_full_T_12, write_packets_mask_14) node _write_packets_packet_is_full_T_14 = and(_write_packets_packet_is_full_T_13, write_packets_mask_15) connect write_packets_0.is_full, _write_packets_packet_is_full_T_14 connect write_packets_0.bytes_written, write_packets_bytes_written node _write_packets_left_shift_T = geq(write_packets_vaddr_offset, UInt<1>(0h0)) node _write_packets_left_shift_T_1 = lt(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_2 = and(_write_packets_left_shift_T, _write_packets_left_shift_T_1) node _write_packets_left_shift_T_3 = sub(write_packets_vaddr_offset, UInt<1>(0h0)) node _write_packets_left_shift_T_4 = tail(_write_packets_left_shift_T_3, 1) node write_packets_left_shift = mux(_write_packets_left_shift_T_2, _write_packets_left_shift_T_4, UInt<1>(0h0)) node _write_packets_right_shift_T = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_1 = geq(_write_packets_right_shift_T, UInt<1>(0h0)) node _write_packets_right_shift_T_2 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_3 = lt(_write_packets_right_shift_T_2, UInt<5>(0h10)) node _write_packets_right_shift_T_4 = and(_write_packets_right_shift_T_1, _write_packets_right_shift_T_3) node _write_packets_right_shift_T_5 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_6 = sub(UInt<5>(0h10), _write_packets_right_shift_T_5) node _write_packets_right_shift_T_7 = tail(_write_packets_right_shift_T_6, 1) node write_packets_right_shift = mux(_write_packets_right_shift_T_4, _write_packets_right_shift_T_7, UInt<1>(0h0)) node write_packets_too_early = geq(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_too_late_T = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late = leq(_write_packets_too_late_T, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T = or(write_packets_too_early, write_packets_too_late) node _write_packets_packet_bytes_written_per_beat_0_T_1 = add(write_packets_left_shift, write_packets_right_shift) node _write_packets_packet_bytes_written_per_beat_0_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_1) node _write_packets_packet_bytes_written_per_beat_0_T_3 = tail(_write_packets_packet_bytes_written_per_beat_0_T_2, 1) node _write_packets_packet_bytes_written_per_beat_0_T_4 = mux(_write_packets_packet_bytes_written_per_beat_0_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_3) connect write_packets_0.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_4 node _write_packets_left_shift_T_5 = geq(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_6 = lt(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_7 = and(_write_packets_left_shift_T_5, _write_packets_left_shift_T_6) node _write_packets_left_shift_T_8 = sub(write_packets_vaddr_offset, UInt<5>(0h10)) node _write_packets_left_shift_T_9 = tail(_write_packets_left_shift_T_8, 1) node write_packets_left_shift_1 = mux(_write_packets_left_shift_T_7, _write_packets_left_shift_T_9, UInt<1>(0h0)) node _write_packets_right_shift_T_8 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_9 = geq(_write_packets_right_shift_T_8, UInt<5>(0h10)) node _write_packets_right_shift_T_10 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_11 = lt(_write_packets_right_shift_T_10, UInt<6>(0h20)) node _write_packets_right_shift_T_12 = and(_write_packets_right_shift_T_9, _write_packets_right_shift_T_11) node _write_packets_right_shift_T_13 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_14 = sub(UInt<6>(0h20), _write_packets_right_shift_T_13) node _write_packets_right_shift_T_15 = tail(_write_packets_right_shift_T_14, 1) node write_packets_right_shift_1 = mux(_write_packets_right_shift_T_12, _write_packets_right_shift_T_15, UInt<1>(0h0)) node write_packets_too_early_1 = geq(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_too_late_T_1 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_1 = leq(_write_packets_too_late_T_1, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T = or(write_packets_too_early_1, write_packets_too_late_1) node _write_packets_packet_bytes_written_per_beat_1_T_1 = add(write_packets_left_shift_1, write_packets_right_shift_1) node _write_packets_packet_bytes_written_per_beat_1_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_1) node _write_packets_packet_bytes_written_per_beat_1_T_3 = tail(_write_packets_packet_bytes_written_per_beat_1_T_2, 1) node _write_packets_packet_bytes_written_per_beat_1_T_4 = mux(_write_packets_packet_bytes_written_per_beat_1_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_3) connect write_packets_0.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_4 node _write_packets_left_shift_T_10 = geq(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_11 = lt(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_12 = and(_write_packets_left_shift_T_10, _write_packets_left_shift_T_11) node _write_packets_left_shift_T_13 = sub(write_packets_vaddr_offset, UInt<6>(0h20)) node _write_packets_left_shift_T_14 = tail(_write_packets_left_shift_T_13, 1) node write_packets_left_shift_2 = mux(_write_packets_left_shift_T_12, _write_packets_left_shift_T_14, UInt<1>(0h0)) node _write_packets_right_shift_T_16 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_17 = geq(_write_packets_right_shift_T_16, UInt<6>(0h20)) node _write_packets_right_shift_T_18 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_19 = lt(_write_packets_right_shift_T_18, UInt<6>(0h30)) node _write_packets_right_shift_T_20 = and(_write_packets_right_shift_T_17, _write_packets_right_shift_T_19) node _write_packets_right_shift_T_21 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_22 = sub(UInt<6>(0h30), _write_packets_right_shift_T_21) node _write_packets_right_shift_T_23 = tail(_write_packets_right_shift_T_22, 1) node write_packets_right_shift_2 = mux(_write_packets_right_shift_T_20, _write_packets_right_shift_T_23, UInt<1>(0h0)) node write_packets_too_early_2 = geq(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_too_late_T_2 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_2 = leq(_write_packets_too_late_T_2, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T = or(write_packets_too_early_2, write_packets_too_late_2) node _write_packets_packet_bytes_written_per_beat_2_T_1 = add(write_packets_left_shift_2, write_packets_right_shift_2) node _write_packets_packet_bytes_written_per_beat_2_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_1) node _write_packets_packet_bytes_written_per_beat_2_T_3 = tail(_write_packets_packet_bytes_written_per_beat_2_T_2, 1) node _write_packets_packet_bytes_written_per_beat_2_T_4 = mux(_write_packets_packet_bytes_written_per_beat_2_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_3) connect write_packets_0.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_4 node _write_packets_left_shift_T_15 = geq(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_16 = lt(write_packets_vaddr_offset, UInt<7>(0h40)) node _write_packets_left_shift_T_17 = and(_write_packets_left_shift_T_15, _write_packets_left_shift_T_16) node _write_packets_left_shift_T_18 = sub(write_packets_vaddr_offset, UInt<6>(0h30)) node _write_packets_left_shift_T_19 = tail(_write_packets_left_shift_T_18, 1) node write_packets_left_shift_3 = mux(_write_packets_left_shift_T_17, _write_packets_left_shift_T_19, UInt<1>(0h0)) node _write_packets_right_shift_T_24 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_25 = geq(_write_packets_right_shift_T_24, UInt<6>(0h30)) node _write_packets_right_shift_T_26 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_27 = lt(_write_packets_right_shift_T_26, UInt<7>(0h40)) node _write_packets_right_shift_T_28 = and(_write_packets_right_shift_T_25, _write_packets_right_shift_T_27) node _write_packets_right_shift_T_29 = add(write_packets_vaddr_offset, bytesLeft) node _write_packets_right_shift_T_30 = sub(UInt<7>(0h40), _write_packets_right_shift_T_29) node _write_packets_right_shift_T_31 = tail(_write_packets_right_shift_T_30, 1) node write_packets_right_shift_3 = mux(_write_packets_right_shift_T_28, _write_packets_right_shift_T_31, UInt<1>(0h0)) node write_packets_too_early_3 = geq(write_packets_vaddr_offset, UInt<7>(0h40)) node _write_packets_too_late_T_3 = add(write_packets_vaddr_offset, bytesLeft) node write_packets_too_late_3 = leq(_write_packets_too_late_T_3, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T = or(write_packets_too_early_3, write_packets_too_late_3) node _write_packets_packet_bytes_written_per_beat_3_T_1 = add(write_packets_left_shift_3, write_packets_right_shift_3) node _write_packets_packet_bytes_written_per_beat_3_T_2 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_1) node _write_packets_packet_bytes_written_per_beat_3_T_3 = tail(_write_packets_packet_bytes_written_per_beat_3_T_2, 1) node _write_packets_packet_bytes_written_per_beat_3_T_4 = mux(_write_packets_packet_bytes_written_per_beat_3_T, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_3) connect write_packets_0.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_4 node _write_packets_vaddr_aligned_to_size_T_1 = bits(req.vaddr, 38, 5) node write_packets_vaddr_aligned_to_size_1 = cat(_write_packets_vaddr_aligned_to_size_T_1, UInt<5>(0h0)) node write_packets_vaddr_offset_1 = bits(req.vaddr, 4, 0) node _write_packets_mask_T_256 = geq(UInt<1>(0h0), write_packets_vaddr_offset_1) node _write_packets_mask_T_257 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_258 = lt(UInt<1>(0h0), _write_packets_mask_T_257) node _write_packets_mask_T_259 = and(_write_packets_mask_T_256, _write_packets_mask_T_258) node write_packets_mask_0_1 = and(_write_packets_mask_T_259, UInt<1>(0h1)) node _write_packets_mask_T_260 = geq(UInt<1>(0h1), write_packets_vaddr_offset_1) node _write_packets_mask_T_261 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_262 = lt(UInt<1>(0h1), _write_packets_mask_T_261) node _write_packets_mask_T_263 = and(_write_packets_mask_T_260, _write_packets_mask_T_262) node write_packets_mask_1_1 = and(_write_packets_mask_T_263, UInt<1>(0h1)) node _write_packets_mask_T_264 = geq(UInt<2>(0h2), write_packets_vaddr_offset_1) node _write_packets_mask_T_265 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_266 = lt(UInt<2>(0h2), _write_packets_mask_T_265) node _write_packets_mask_T_267 = and(_write_packets_mask_T_264, _write_packets_mask_T_266) node write_packets_mask_2_1 = and(_write_packets_mask_T_267, UInt<1>(0h1)) node _write_packets_mask_T_268 = geq(UInt<2>(0h3), write_packets_vaddr_offset_1) node _write_packets_mask_T_269 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_270 = lt(UInt<2>(0h3), _write_packets_mask_T_269) node _write_packets_mask_T_271 = and(_write_packets_mask_T_268, _write_packets_mask_T_270) node write_packets_mask_3_1 = and(_write_packets_mask_T_271, UInt<1>(0h1)) node _write_packets_mask_T_272 = geq(UInt<3>(0h4), write_packets_vaddr_offset_1) node _write_packets_mask_T_273 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_274 = lt(UInt<3>(0h4), _write_packets_mask_T_273) node _write_packets_mask_T_275 = and(_write_packets_mask_T_272, _write_packets_mask_T_274) node write_packets_mask_4_1 = and(_write_packets_mask_T_275, UInt<1>(0h1)) node _write_packets_mask_T_276 = geq(UInt<3>(0h5), write_packets_vaddr_offset_1) node _write_packets_mask_T_277 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_278 = lt(UInt<3>(0h5), _write_packets_mask_T_277) node _write_packets_mask_T_279 = and(_write_packets_mask_T_276, _write_packets_mask_T_278) node write_packets_mask_5_1 = and(_write_packets_mask_T_279, UInt<1>(0h1)) node _write_packets_mask_T_280 = geq(UInt<3>(0h6), write_packets_vaddr_offset_1) node _write_packets_mask_T_281 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_282 = lt(UInt<3>(0h6), _write_packets_mask_T_281) node _write_packets_mask_T_283 = and(_write_packets_mask_T_280, _write_packets_mask_T_282) node write_packets_mask_6_1 = and(_write_packets_mask_T_283, UInt<1>(0h1)) node _write_packets_mask_T_284 = geq(UInt<3>(0h7), write_packets_vaddr_offset_1) node _write_packets_mask_T_285 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_286 = lt(UInt<3>(0h7), _write_packets_mask_T_285) node _write_packets_mask_T_287 = and(_write_packets_mask_T_284, _write_packets_mask_T_286) node write_packets_mask_7_1 = and(_write_packets_mask_T_287, UInt<1>(0h1)) node _write_packets_mask_T_288 = geq(UInt<4>(0h8), write_packets_vaddr_offset_1) node _write_packets_mask_T_289 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_290 = lt(UInt<4>(0h8), _write_packets_mask_T_289) node _write_packets_mask_T_291 = and(_write_packets_mask_T_288, _write_packets_mask_T_290) node write_packets_mask_8_1 = and(_write_packets_mask_T_291, UInt<1>(0h1)) node _write_packets_mask_T_292 = geq(UInt<4>(0h9), write_packets_vaddr_offset_1) node _write_packets_mask_T_293 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_294 = lt(UInt<4>(0h9), _write_packets_mask_T_293) node _write_packets_mask_T_295 = and(_write_packets_mask_T_292, _write_packets_mask_T_294) node write_packets_mask_9_1 = and(_write_packets_mask_T_295, UInt<1>(0h1)) node _write_packets_mask_T_296 = geq(UInt<4>(0ha), write_packets_vaddr_offset_1) node _write_packets_mask_T_297 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_298 = lt(UInt<4>(0ha), _write_packets_mask_T_297) node _write_packets_mask_T_299 = and(_write_packets_mask_T_296, _write_packets_mask_T_298) node write_packets_mask_10_1 = and(_write_packets_mask_T_299, UInt<1>(0h1)) node _write_packets_mask_T_300 = geq(UInt<4>(0hb), write_packets_vaddr_offset_1) node _write_packets_mask_T_301 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_302 = lt(UInt<4>(0hb), _write_packets_mask_T_301) node _write_packets_mask_T_303 = and(_write_packets_mask_T_300, _write_packets_mask_T_302) node write_packets_mask_11_1 = and(_write_packets_mask_T_303, UInt<1>(0h1)) node _write_packets_mask_T_304 = geq(UInt<4>(0hc), write_packets_vaddr_offset_1) node _write_packets_mask_T_305 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_306 = lt(UInt<4>(0hc), _write_packets_mask_T_305) node _write_packets_mask_T_307 = and(_write_packets_mask_T_304, _write_packets_mask_T_306) node write_packets_mask_12_1 = and(_write_packets_mask_T_307, UInt<1>(0h1)) node _write_packets_mask_T_308 = geq(UInt<4>(0hd), write_packets_vaddr_offset_1) node _write_packets_mask_T_309 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_310 = lt(UInt<4>(0hd), _write_packets_mask_T_309) node _write_packets_mask_T_311 = and(_write_packets_mask_T_308, _write_packets_mask_T_310) node write_packets_mask_13_1 = and(_write_packets_mask_T_311, UInt<1>(0h1)) node _write_packets_mask_T_312 = geq(UInt<4>(0he), write_packets_vaddr_offset_1) node _write_packets_mask_T_313 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_314 = lt(UInt<4>(0he), _write_packets_mask_T_313) node _write_packets_mask_T_315 = and(_write_packets_mask_T_312, _write_packets_mask_T_314) node write_packets_mask_14_1 = and(_write_packets_mask_T_315, UInt<1>(0h1)) node _write_packets_mask_T_316 = geq(UInt<4>(0hf), write_packets_vaddr_offset_1) node _write_packets_mask_T_317 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_318 = lt(UInt<4>(0hf), _write_packets_mask_T_317) node _write_packets_mask_T_319 = and(_write_packets_mask_T_316, _write_packets_mask_T_318) node write_packets_mask_15_1 = and(_write_packets_mask_T_319, UInt<1>(0h1)) node _write_packets_mask_T_320 = geq(UInt<5>(0h10), write_packets_vaddr_offset_1) node _write_packets_mask_T_321 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_322 = lt(UInt<5>(0h10), _write_packets_mask_T_321) node _write_packets_mask_T_323 = and(_write_packets_mask_T_320, _write_packets_mask_T_322) node write_packets_mask_16_1 = and(_write_packets_mask_T_323, UInt<1>(0h1)) node _write_packets_mask_T_324 = geq(UInt<5>(0h11), write_packets_vaddr_offset_1) node _write_packets_mask_T_325 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_326 = lt(UInt<5>(0h11), _write_packets_mask_T_325) node _write_packets_mask_T_327 = and(_write_packets_mask_T_324, _write_packets_mask_T_326) node write_packets_mask_17_1 = and(_write_packets_mask_T_327, UInt<1>(0h1)) node _write_packets_mask_T_328 = geq(UInt<5>(0h12), write_packets_vaddr_offset_1) node _write_packets_mask_T_329 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_330 = lt(UInt<5>(0h12), _write_packets_mask_T_329) node _write_packets_mask_T_331 = and(_write_packets_mask_T_328, _write_packets_mask_T_330) node write_packets_mask_18_1 = and(_write_packets_mask_T_331, UInt<1>(0h1)) node _write_packets_mask_T_332 = geq(UInt<5>(0h13), write_packets_vaddr_offset_1) node _write_packets_mask_T_333 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_334 = lt(UInt<5>(0h13), _write_packets_mask_T_333) node _write_packets_mask_T_335 = and(_write_packets_mask_T_332, _write_packets_mask_T_334) node write_packets_mask_19_1 = and(_write_packets_mask_T_335, UInt<1>(0h1)) node _write_packets_mask_T_336 = geq(UInt<5>(0h14), write_packets_vaddr_offset_1) node _write_packets_mask_T_337 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_338 = lt(UInt<5>(0h14), _write_packets_mask_T_337) node _write_packets_mask_T_339 = and(_write_packets_mask_T_336, _write_packets_mask_T_338) node write_packets_mask_20_1 = and(_write_packets_mask_T_339, UInt<1>(0h1)) node _write_packets_mask_T_340 = geq(UInt<5>(0h15), write_packets_vaddr_offset_1) node _write_packets_mask_T_341 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_342 = lt(UInt<5>(0h15), _write_packets_mask_T_341) node _write_packets_mask_T_343 = and(_write_packets_mask_T_340, _write_packets_mask_T_342) node write_packets_mask_21_1 = and(_write_packets_mask_T_343, UInt<1>(0h1)) node _write_packets_mask_T_344 = geq(UInt<5>(0h16), write_packets_vaddr_offset_1) node _write_packets_mask_T_345 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_346 = lt(UInt<5>(0h16), _write_packets_mask_T_345) node _write_packets_mask_T_347 = and(_write_packets_mask_T_344, _write_packets_mask_T_346) node write_packets_mask_22_1 = and(_write_packets_mask_T_347, UInt<1>(0h1)) node _write_packets_mask_T_348 = geq(UInt<5>(0h17), write_packets_vaddr_offset_1) node _write_packets_mask_T_349 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_350 = lt(UInt<5>(0h17), _write_packets_mask_T_349) node _write_packets_mask_T_351 = and(_write_packets_mask_T_348, _write_packets_mask_T_350) node write_packets_mask_23_1 = and(_write_packets_mask_T_351, UInt<1>(0h1)) node _write_packets_mask_T_352 = geq(UInt<5>(0h18), write_packets_vaddr_offset_1) node _write_packets_mask_T_353 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_354 = lt(UInt<5>(0h18), _write_packets_mask_T_353) node _write_packets_mask_T_355 = and(_write_packets_mask_T_352, _write_packets_mask_T_354) node write_packets_mask_24_1 = and(_write_packets_mask_T_355, UInt<1>(0h1)) node _write_packets_mask_T_356 = geq(UInt<5>(0h19), write_packets_vaddr_offset_1) node _write_packets_mask_T_357 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_358 = lt(UInt<5>(0h19), _write_packets_mask_T_357) node _write_packets_mask_T_359 = and(_write_packets_mask_T_356, _write_packets_mask_T_358) node write_packets_mask_25_1 = and(_write_packets_mask_T_359, UInt<1>(0h1)) node _write_packets_mask_T_360 = geq(UInt<5>(0h1a), write_packets_vaddr_offset_1) node _write_packets_mask_T_361 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_362 = lt(UInt<5>(0h1a), _write_packets_mask_T_361) node _write_packets_mask_T_363 = and(_write_packets_mask_T_360, _write_packets_mask_T_362) node write_packets_mask_26_1 = and(_write_packets_mask_T_363, UInt<1>(0h1)) node _write_packets_mask_T_364 = geq(UInt<5>(0h1b), write_packets_vaddr_offset_1) node _write_packets_mask_T_365 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_366 = lt(UInt<5>(0h1b), _write_packets_mask_T_365) node _write_packets_mask_T_367 = and(_write_packets_mask_T_364, _write_packets_mask_T_366) node write_packets_mask_27_1 = and(_write_packets_mask_T_367, UInt<1>(0h1)) node _write_packets_mask_T_368 = geq(UInt<5>(0h1c), write_packets_vaddr_offset_1) node _write_packets_mask_T_369 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_370 = lt(UInt<5>(0h1c), _write_packets_mask_T_369) node _write_packets_mask_T_371 = and(_write_packets_mask_T_368, _write_packets_mask_T_370) node write_packets_mask_28_1 = and(_write_packets_mask_T_371, UInt<1>(0h1)) node _write_packets_mask_T_372 = geq(UInt<5>(0h1d), write_packets_vaddr_offset_1) node _write_packets_mask_T_373 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_374 = lt(UInt<5>(0h1d), _write_packets_mask_T_373) node _write_packets_mask_T_375 = and(_write_packets_mask_T_372, _write_packets_mask_T_374) node write_packets_mask_29_1 = and(_write_packets_mask_T_375, UInt<1>(0h1)) node _write_packets_mask_T_376 = geq(UInt<5>(0h1e), write_packets_vaddr_offset_1) node _write_packets_mask_T_377 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_378 = lt(UInt<5>(0h1e), _write_packets_mask_T_377) node _write_packets_mask_T_379 = and(_write_packets_mask_T_376, _write_packets_mask_T_378) node write_packets_mask_30_1 = and(_write_packets_mask_T_379, UInt<1>(0h1)) node _write_packets_mask_T_380 = geq(UInt<5>(0h1f), write_packets_vaddr_offset_1) node _write_packets_mask_T_381 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_382 = lt(UInt<5>(0h1f), _write_packets_mask_T_381) node _write_packets_mask_T_383 = and(_write_packets_mask_T_380, _write_packets_mask_T_382) node write_packets_mask_31_1 = and(_write_packets_mask_T_383, UInt<1>(0h1)) node _write_packets_mask_T_384 = geq(UInt<6>(0h20), write_packets_vaddr_offset_1) node _write_packets_mask_T_385 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_386 = lt(UInt<6>(0h20), _write_packets_mask_T_385) node _write_packets_mask_T_387 = and(_write_packets_mask_T_384, _write_packets_mask_T_386) node write_packets_mask_32_1 = and(_write_packets_mask_T_387, UInt<1>(0h0)) node _write_packets_mask_T_388 = geq(UInt<6>(0h21), write_packets_vaddr_offset_1) node _write_packets_mask_T_389 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_390 = lt(UInt<6>(0h21), _write_packets_mask_T_389) node _write_packets_mask_T_391 = and(_write_packets_mask_T_388, _write_packets_mask_T_390) node write_packets_mask_33_1 = and(_write_packets_mask_T_391, UInt<1>(0h0)) node _write_packets_mask_T_392 = geq(UInt<6>(0h22), write_packets_vaddr_offset_1) node _write_packets_mask_T_393 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_394 = lt(UInt<6>(0h22), _write_packets_mask_T_393) node _write_packets_mask_T_395 = and(_write_packets_mask_T_392, _write_packets_mask_T_394) node write_packets_mask_34_1 = and(_write_packets_mask_T_395, UInt<1>(0h0)) node _write_packets_mask_T_396 = geq(UInt<6>(0h23), write_packets_vaddr_offset_1) node _write_packets_mask_T_397 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_398 = lt(UInt<6>(0h23), _write_packets_mask_T_397) node _write_packets_mask_T_399 = and(_write_packets_mask_T_396, _write_packets_mask_T_398) node write_packets_mask_35_1 = and(_write_packets_mask_T_399, UInt<1>(0h0)) node _write_packets_mask_T_400 = geq(UInt<6>(0h24), write_packets_vaddr_offset_1) node _write_packets_mask_T_401 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_402 = lt(UInt<6>(0h24), _write_packets_mask_T_401) node _write_packets_mask_T_403 = and(_write_packets_mask_T_400, _write_packets_mask_T_402) node write_packets_mask_36_1 = and(_write_packets_mask_T_403, UInt<1>(0h0)) node _write_packets_mask_T_404 = geq(UInt<6>(0h25), write_packets_vaddr_offset_1) node _write_packets_mask_T_405 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_406 = lt(UInt<6>(0h25), _write_packets_mask_T_405) node _write_packets_mask_T_407 = and(_write_packets_mask_T_404, _write_packets_mask_T_406) node write_packets_mask_37_1 = and(_write_packets_mask_T_407, UInt<1>(0h0)) node _write_packets_mask_T_408 = geq(UInt<6>(0h26), write_packets_vaddr_offset_1) node _write_packets_mask_T_409 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_410 = lt(UInt<6>(0h26), _write_packets_mask_T_409) node _write_packets_mask_T_411 = and(_write_packets_mask_T_408, _write_packets_mask_T_410) node write_packets_mask_38_1 = and(_write_packets_mask_T_411, UInt<1>(0h0)) node _write_packets_mask_T_412 = geq(UInt<6>(0h27), write_packets_vaddr_offset_1) node _write_packets_mask_T_413 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_414 = lt(UInt<6>(0h27), _write_packets_mask_T_413) node _write_packets_mask_T_415 = and(_write_packets_mask_T_412, _write_packets_mask_T_414) node write_packets_mask_39_1 = and(_write_packets_mask_T_415, UInt<1>(0h0)) node _write_packets_mask_T_416 = geq(UInt<6>(0h28), write_packets_vaddr_offset_1) node _write_packets_mask_T_417 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_418 = lt(UInt<6>(0h28), _write_packets_mask_T_417) node _write_packets_mask_T_419 = and(_write_packets_mask_T_416, _write_packets_mask_T_418) node write_packets_mask_40_1 = and(_write_packets_mask_T_419, UInt<1>(0h0)) node _write_packets_mask_T_420 = geq(UInt<6>(0h29), write_packets_vaddr_offset_1) node _write_packets_mask_T_421 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_422 = lt(UInt<6>(0h29), _write_packets_mask_T_421) node _write_packets_mask_T_423 = and(_write_packets_mask_T_420, _write_packets_mask_T_422) node write_packets_mask_41_1 = and(_write_packets_mask_T_423, UInt<1>(0h0)) node _write_packets_mask_T_424 = geq(UInt<6>(0h2a), write_packets_vaddr_offset_1) node _write_packets_mask_T_425 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_426 = lt(UInt<6>(0h2a), _write_packets_mask_T_425) node _write_packets_mask_T_427 = and(_write_packets_mask_T_424, _write_packets_mask_T_426) node write_packets_mask_42_1 = and(_write_packets_mask_T_427, UInt<1>(0h0)) node _write_packets_mask_T_428 = geq(UInt<6>(0h2b), write_packets_vaddr_offset_1) node _write_packets_mask_T_429 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_430 = lt(UInt<6>(0h2b), _write_packets_mask_T_429) node _write_packets_mask_T_431 = and(_write_packets_mask_T_428, _write_packets_mask_T_430) node write_packets_mask_43_1 = and(_write_packets_mask_T_431, UInt<1>(0h0)) node _write_packets_mask_T_432 = geq(UInt<6>(0h2c), write_packets_vaddr_offset_1) node _write_packets_mask_T_433 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_434 = lt(UInt<6>(0h2c), _write_packets_mask_T_433) node _write_packets_mask_T_435 = and(_write_packets_mask_T_432, _write_packets_mask_T_434) node write_packets_mask_44_1 = and(_write_packets_mask_T_435, UInt<1>(0h0)) node _write_packets_mask_T_436 = geq(UInt<6>(0h2d), write_packets_vaddr_offset_1) node _write_packets_mask_T_437 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_438 = lt(UInt<6>(0h2d), _write_packets_mask_T_437) node _write_packets_mask_T_439 = and(_write_packets_mask_T_436, _write_packets_mask_T_438) node write_packets_mask_45_1 = and(_write_packets_mask_T_439, UInt<1>(0h0)) node _write_packets_mask_T_440 = geq(UInt<6>(0h2e), write_packets_vaddr_offset_1) node _write_packets_mask_T_441 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_442 = lt(UInt<6>(0h2e), _write_packets_mask_T_441) node _write_packets_mask_T_443 = and(_write_packets_mask_T_440, _write_packets_mask_T_442) node write_packets_mask_46_1 = and(_write_packets_mask_T_443, UInt<1>(0h0)) node _write_packets_mask_T_444 = geq(UInt<6>(0h2f), write_packets_vaddr_offset_1) node _write_packets_mask_T_445 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_446 = lt(UInt<6>(0h2f), _write_packets_mask_T_445) node _write_packets_mask_T_447 = and(_write_packets_mask_T_444, _write_packets_mask_T_446) node write_packets_mask_47_1 = and(_write_packets_mask_T_447, UInt<1>(0h0)) node _write_packets_mask_T_448 = geq(UInt<6>(0h30), write_packets_vaddr_offset_1) node _write_packets_mask_T_449 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_450 = lt(UInt<6>(0h30), _write_packets_mask_T_449) node _write_packets_mask_T_451 = and(_write_packets_mask_T_448, _write_packets_mask_T_450) node write_packets_mask_48_1 = and(_write_packets_mask_T_451, UInt<1>(0h0)) node _write_packets_mask_T_452 = geq(UInt<6>(0h31), write_packets_vaddr_offset_1) node _write_packets_mask_T_453 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_454 = lt(UInt<6>(0h31), _write_packets_mask_T_453) node _write_packets_mask_T_455 = and(_write_packets_mask_T_452, _write_packets_mask_T_454) node write_packets_mask_49_1 = and(_write_packets_mask_T_455, UInt<1>(0h0)) node _write_packets_mask_T_456 = geq(UInt<6>(0h32), write_packets_vaddr_offset_1) node _write_packets_mask_T_457 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_458 = lt(UInt<6>(0h32), _write_packets_mask_T_457) node _write_packets_mask_T_459 = and(_write_packets_mask_T_456, _write_packets_mask_T_458) node write_packets_mask_50_1 = and(_write_packets_mask_T_459, UInt<1>(0h0)) node _write_packets_mask_T_460 = geq(UInt<6>(0h33), write_packets_vaddr_offset_1) node _write_packets_mask_T_461 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_462 = lt(UInt<6>(0h33), _write_packets_mask_T_461) node _write_packets_mask_T_463 = and(_write_packets_mask_T_460, _write_packets_mask_T_462) node write_packets_mask_51_1 = and(_write_packets_mask_T_463, UInt<1>(0h0)) node _write_packets_mask_T_464 = geq(UInt<6>(0h34), write_packets_vaddr_offset_1) node _write_packets_mask_T_465 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_466 = lt(UInt<6>(0h34), _write_packets_mask_T_465) node _write_packets_mask_T_467 = and(_write_packets_mask_T_464, _write_packets_mask_T_466) node write_packets_mask_52_1 = and(_write_packets_mask_T_467, UInt<1>(0h0)) node _write_packets_mask_T_468 = geq(UInt<6>(0h35), write_packets_vaddr_offset_1) node _write_packets_mask_T_469 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_470 = lt(UInt<6>(0h35), _write_packets_mask_T_469) node _write_packets_mask_T_471 = and(_write_packets_mask_T_468, _write_packets_mask_T_470) node write_packets_mask_53_1 = and(_write_packets_mask_T_471, UInt<1>(0h0)) node _write_packets_mask_T_472 = geq(UInt<6>(0h36), write_packets_vaddr_offset_1) node _write_packets_mask_T_473 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_474 = lt(UInt<6>(0h36), _write_packets_mask_T_473) node _write_packets_mask_T_475 = and(_write_packets_mask_T_472, _write_packets_mask_T_474) node write_packets_mask_54_1 = and(_write_packets_mask_T_475, UInt<1>(0h0)) node _write_packets_mask_T_476 = geq(UInt<6>(0h37), write_packets_vaddr_offset_1) node _write_packets_mask_T_477 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_478 = lt(UInt<6>(0h37), _write_packets_mask_T_477) node _write_packets_mask_T_479 = and(_write_packets_mask_T_476, _write_packets_mask_T_478) node write_packets_mask_55_1 = and(_write_packets_mask_T_479, UInt<1>(0h0)) node _write_packets_mask_T_480 = geq(UInt<6>(0h38), write_packets_vaddr_offset_1) node _write_packets_mask_T_481 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_482 = lt(UInt<6>(0h38), _write_packets_mask_T_481) node _write_packets_mask_T_483 = and(_write_packets_mask_T_480, _write_packets_mask_T_482) node write_packets_mask_56_1 = and(_write_packets_mask_T_483, UInt<1>(0h0)) node _write_packets_mask_T_484 = geq(UInt<6>(0h39), write_packets_vaddr_offset_1) node _write_packets_mask_T_485 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_486 = lt(UInt<6>(0h39), _write_packets_mask_T_485) node _write_packets_mask_T_487 = and(_write_packets_mask_T_484, _write_packets_mask_T_486) node write_packets_mask_57_1 = and(_write_packets_mask_T_487, UInt<1>(0h0)) node _write_packets_mask_T_488 = geq(UInt<6>(0h3a), write_packets_vaddr_offset_1) node _write_packets_mask_T_489 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_490 = lt(UInt<6>(0h3a), _write_packets_mask_T_489) node _write_packets_mask_T_491 = and(_write_packets_mask_T_488, _write_packets_mask_T_490) node write_packets_mask_58_1 = and(_write_packets_mask_T_491, UInt<1>(0h0)) node _write_packets_mask_T_492 = geq(UInt<6>(0h3b), write_packets_vaddr_offset_1) node _write_packets_mask_T_493 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_494 = lt(UInt<6>(0h3b), _write_packets_mask_T_493) node _write_packets_mask_T_495 = and(_write_packets_mask_T_492, _write_packets_mask_T_494) node write_packets_mask_59_1 = and(_write_packets_mask_T_495, UInt<1>(0h0)) node _write_packets_mask_T_496 = geq(UInt<6>(0h3c), write_packets_vaddr_offset_1) node _write_packets_mask_T_497 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_498 = lt(UInt<6>(0h3c), _write_packets_mask_T_497) node _write_packets_mask_T_499 = and(_write_packets_mask_T_496, _write_packets_mask_T_498) node write_packets_mask_60_1 = and(_write_packets_mask_T_499, UInt<1>(0h0)) node _write_packets_mask_T_500 = geq(UInt<6>(0h3d), write_packets_vaddr_offset_1) node _write_packets_mask_T_501 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_502 = lt(UInt<6>(0h3d), _write_packets_mask_T_501) node _write_packets_mask_T_503 = and(_write_packets_mask_T_500, _write_packets_mask_T_502) node write_packets_mask_61_1 = and(_write_packets_mask_T_503, UInt<1>(0h0)) node _write_packets_mask_T_504 = geq(UInt<6>(0h3e), write_packets_vaddr_offset_1) node _write_packets_mask_T_505 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_506 = lt(UInt<6>(0h3e), _write_packets_mask_T_505) node _write_packets_mask_T_507 = and(_write_packets_mask_T_504, _write_packets_mask_T_506) node write_packets_mask_62_1 = and(_write_packets_mask_T_507, UInt<1>(0h0)) node _write_packets_mask_T_508 = geq(UInt<6>(0h3f), write_packets_vaddr_offset_1) node _write_packets_mask_T_509 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_mask_T_510 = lt(UInt<6>(0h3f), _write_packets_mask_T_509) node _write_packets_mask_T_511 = and(_write_packets_mask_T_508, _write_packets_mask_T_510) node write_packets_mask_63_1 = and(_write_packets_mask_T_511, UInt<1>(0h0)) node _write_packets_bytes_written_T_4 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_bytes_written_T_5 = gt(_write_packets_bytes_written_T_4, UInt<6>(0h20)) node _write_packets_bytes_written_T_6 = sub(UInt<6>(0h20), write_packets_vaddr_offset_1) node _write_packets_bytes_written_T_7 = tail(_write_packets_bytes_written_T_6, 1) node write_packets_bytes_written_1 = mux(_write_packets_bytes_written_T_5, _write_packets_bytes_written_T_7, bytesLeft) wire write_packets_1 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_1.size, UInt<6>(0h20) connect write_packets_1.lg_size, UInt<3>(0h5) wire _write_packets_WIRE_5 : UInt<1>[16] connect _write_packets_WIRE_5[0], write_packets_mask_0_1 connect _write_packets_WIRE_5[1], write_packets_mask_1_1 connect _write_packets_WIRE_5[2], write_packets_mask_2_1 connect _write_packets_WIRE_5[3], write_packets_mask_3_1 connect _write_packets_WIRE_5[4], write_packets_mask_4_1 connect _write_packets_WIRE_5[5], write_packets_mask_5_1 connect _write_packets_WIRE_5[6], write_packets_mask_6_1 connect _write_packets_WIRE_5[7], write_packets_mask_7_1 connect _write_packets_WIRE_5[8], write_packets_mask_8_1 connect _write_packets_WIRE_5[9], write_packets_mask_9_1 connect _write_packets_WIRE_5[10], write_packets_mask_10_1 connect _write_packets_WIRE_5[11], write_packets_mask_11_1 connect _write_packets_WIRE_5[12], write_packets_mask_12_1 connect _write_packets_WIRE_5[13], write_packets_mask_13_1 connect _write_packets_WIRE_5[14], write_packets_mask_14_1 connect _write_packets_WIRE_5[15], write_packets_mask_15_1 wire _write_packets_WIRE_6 : UInt<1>[16] connect _write_packets_WIRE_6[0], write_packets_mask_16_1 connect _write_packets_WIRE_6[1], write_packets_mask_17_1 connect _write_packets_WIRE_6[2], write_packets_mask_18_1 connect _write_packets_WIRE_6[3], write_packets_mask_19_1 connect _write_packets_WIRE_6[4], write_packets_mask_20_1 connect _write_packets_WIRE_6[5], write_packets_mask_21_1 connect _write_packets_WIRE_6[6], write_packets_mask_22_1 connect _write_packets_WIRE_6[7], write_packets_mask_23_1 connect _write_packets_WIRE_6[8], write_packets_mask_24_1 connect _write_packets_WIRE_6[9], write_packets_mask_25_1 connect _write_packets_WIRE_6[10], write_packets_mask_26_1 connect _write_packets_WIRE_6[11], write_packets_mask_27_1 connect _write_packets_WIRE_6[12], write_packets_mask_28_1 connect _write_packets_WIRE_6[13], write_packets_mask_29_1 connect _write_packets_WIRE_6[14], write_packets_mask_30_1 connect _write_packets_WIRE_6[15], write_packets_mask_31_1 wire _write_packets_WIRE_7 : UInt<1>[16] connect _write_packets_WIRE_7[0], write_packets_mask_32_1 connect _write_packets_WIRE_7[1], write_packets_mask_33_1 connect _write_packets_WIRE_7[2], write_packets_mask_34_1 connect _write_packets_WIRE_7[3], write_packets_mask_35_1 connect _write_packets_WIRE_7[4], write_packets_mask_36_1 connect _write_packets_WIRE_7[5], write_packets_mask_37_1 connect _write_packets_WIRE_7[6], write_packets_mask_38_1 connect _write_packets_WIRE_7[7], write_packets_mask_39_1 connect _write_packets_WIRE_7[8], write_packets_mask_40_1 connect _write_packets_WIRE_7[9], write_packets_mask_41_1 connect _write_packets_WIRE_7[10], write_packets_mask_42_1 connect _write_packets_WIRE_7[11], write_packets_mask_43_1 connect _write_packets_WIRE_7[12], write_packets_mask_44_1 connect _write_packets_WIRE_7[13], write_packets_mask_45_1 connect _write_packets_WIRE_7[14], write_packets_mask_46_1 connect _write_packets_WIRE_7[15], write_packets_mask_47_1 wire _write_packets_WIRE_8 : UInt<1>[16] connect _write_packets_WIRE_8[0], write_packets_mask_48_1 connect _write_packets_WIRE_8[1], write_packets_mask_49_1 connect _write_packets_WIRE_8[2], write_packets_mask_50_1 connect _write_packets_WIRE_8[3], write_packets_mask_51_1 connect _write_packets_WIRE_8[4], write_packets_mask_52_1 connect _write_packets_WIRE_8[5], write_packets_mask_53_1 connect _write_packets_WIRE_8[6], write_packets_mask_54_1 connect _write_packets_WIRE_8[7], write_packets_mask_55_1 connect _write_packets_WIRE_8[8], write_packets_mask_56_1 connect _write_packets_WIRE_8[9], write_packets_mask_57_1 connect _write_packets_WIRE_8[10], write_packets_mask_58_1 connect _write_packets_WIRE_8[11], write_packets_mask_59_1 connect _write_packets_WIRE_8[12], write_packets_mask_60_1 connect _write_packets_WIRE_8[13], write_packets_mask_61_1 connect _write_packets_WIRE_8[14], write_packets_mask_62_1 connect _write_packets_WIRE_8[15], write_packets_mask_63_1 wire _write_packets_WIRE_9 : UInt<1>[16][4] connect _write_packets_WIRE_9[0], _write_packets_WIRE_5 connect _write_packets_WIRE_9[1], _write_packets_WIRE_6 connect _write_packets_WIRE_9[2], _write_packets_WIRE_7 connect _write_packets_WIRE_9[3], _write_packets_WIRE_8 connect write_packets_1.mask, _write_packets_WIRE_9 connect write_packets_1.vaddr, write_packets_vaddr_aligned_to_size_1 node _write_packets_packet_is_full_T_15 = and(write_packets_mask_0_1, write_packets_mask_1_1) node _write_packets_packet_is_full_T_16 = and(_write_packets_packet_is_full_T_15, write_packets_mask_2_1) node _write_packets_packet_is_full_T_17 = and(_write_packets_packet_is_full_T_16, write_packets_mask_3_1) node _write_packets_packet_is_full_T_18 = and(_write_packets_packet_is_full_T_17, write_packets_mask_4_1) node _write_packets_packet_is_full_T_19 = and(_write_packets_packet_is_full_T_18, write_packets_mask_5_1) node _write_packets_packet_is_full_T_20 = and(_write_packets_packet_is_full_T_19, write_packets_mask_6_1) node _write_packets_packet_is_full_T_21 = and(_write_packets_packet_is_full_T_20, write_packets_mask_7_1) node _write_packets_packet_is_full_T_22 = and(_write_packets_packet_is_full_T_21, write_packets_mask_8_1) node _write_packets_packet_is_full_T_23 = and(_write_packets_packet_is_full_T_22, write_packets_mask_9_1) node _write_packets_packet_is_full_T_24 = and(_write_packets_packet_is_full_T_23, write_packets_mask_10_1) node _write_packets_packet_is_full_T_25 = and(_write_packets_packet_is_full_T_24, write_packets_mask_11_1) node _write_packets_packet_is_full_T_26 = and(_write_packets_packet_is_full_T_25, write_packets_mask_12_1) node _write_packets_packet_is_full_T_27 = and(_write_packets_packet_is_full_T_26, write_packets_mask_13_1) node _write_packets_packet_is_full_T_28 = and(_write_packets_packet_is_full_T_27, write_packets_mask_14_1) node _write_packets_packet_is_full_T_29 = and(_write_packets_packet_is_full_T_28, write_packets_mask_15_1) node _write_packets_packet_is_full_T_30 = and(_write_packets_packet_is_full_T_29, write_packets_mask_16_1) node _write_packets_packet_is_full_T_31 = and(_write_packets_packet_is_full_T_30, write_packets_mask_17_1) node _write_packets_packet_is_full_T_32 = and(_write_packets_packet_is_full_T_31, write_packets_mask_18_1) node _write_packets_packet_is_full_T_33 = and(_write_packets_packet_is_full_T_32, write_packets_mask_19_1) node _write_packets_packet_is_full_T_34 = and(_write_packets_packet_is_full_T_33, write_packets_mask_20_1) node _write_packets_packet_is_full_T_35 = and(_write_packets_packet_is_full_T_34, write_packets_mask_21_1) node _write_packets_packet_is_full_T_36 = and(_write_packets_packet_is_full_T_35, write_packets_mask_22_1) node _write_packets_packet_is_full_T_37 = and(_write_packets_packet_is_full_T_36, write_packets_mask_23_1) node _write_packets_packet_is_full_T_38 = and(_write_packets_packet_is_full_T_37, write_packets_mask_24_1) node _write_packets_packet_is_full_T_39 = and(_write_packets_packet_is_full_T_38, write_packets_mask_25_1) node _write_packets_packet_is_full_T_40 = and(_write_packets_packet_is_full_T_39, write_packets_mask_26_1) node _write_packets_packet_is_full_T_41 = and(_write_packets_packet_is_full_T_40, write_packets_mask_27_1) node _write_packets_packet_is_full_T_42 = and(_write_packets_packet_is_full_T_41, write_packets_mask_28_1) node _write_packets_packet_is_full_T_43 = and(_write_packets_packet_is_full_T_42, write_packets_mask_29_1) node _write_packets_packet_is_full_T_44 = and(_write_packets_packet_is_full_T_43, write_packets_mask_30_1) node _write_packets_packet_is_full_T_45 = and(_write_packets_packet_is_full_T_44, write_packets_mask_31_1) connect write_packets_1.is_full, _write_packets_packet_is_full_T_45 connect write_packets_1.bytes_written, write_packets_bytes_written_1 node _write_packets_left_shift_T_20 = geq(write_packets_vaddr_offset_1, UInt<1>(0h0)) node _write_packets_left_shift_T_21 = lt(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_22 = and(_write_packets_left_shift_T_20, _write_packets_left_shift_T_21) node _write_packets_left_shift_T_23 = sub(write_packets_vaddr_offset_1, UInt<1>(0h0)) node _write_packets_left_shift_T_24 = tail(_write_packets_left_shift_T_23, 1) node write_packets_left_shift_4 = mux(_write_packets_left_shift_T_22, _write_packets_left_shift_T_24, UInt<1>(0h0)) node _write_packets_right_shift_T_32 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_33 = geq(_write_packets_right_shift_T_32, UInt<1>(0h0)) node _write_packets_right_shift_T_34 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_35 = lt(_write_packets_right_shift_T_34, UInt<5>(0h10)) node _write_packets_right_shift_T_36 = and(_write_packets_right_shift_T_33, _write_packets_right_shift_T_35) node _write_packets_right_shift_T_37 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_38 = sub(UInt<5>(0h10), _write_packets_right_shift_T_37) node _write_packets_right_shift_T_39 = tail(_write_packets_right_shift_T_38, 1) node write_packets_right_shift_4 = mux(_write_packets_right_shift_T_36, _write_packets_right_shift_T_39, UInt<1>(0h0)) node write_packets_too_early_4 = geq(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_too_late_T_4 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_4 = leq(_write_packets_too_late_T_4, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T_5 = or(write_packets_too_early_4, write_packets_too_late_4) node _write_packets_packet_bytes_written_per_beat_0_T_6 = add(write_packets_left_shift_4, write_packets_right_shift_4) node _write_packets_packet_bytes_written_per_beat_0_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_6) node _write_packets_packet_bytes_written_per_beat_0_T_8 = tail(_write_packets_packet_bytes_written_per_beat_0_T_7, 1) node _write_packets_packet_bytes_written_per_beat_0_T_9 = mux(_write_packets_packet_bytes_written_per_beat_0_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_8) connect write_packets_1.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_9 node _write_packets_left_shift_T_25 = geq(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_26 = lt(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_27 = and(_write_packets_left_shift_T_25, _write_packets_left_shift_T_26) node _write_packets_left_shift_T_28 = sub(write_packets_vaddr_offset_1, UInt<5>(0h10)) node _write_packets_left_shift_T_29 = tail(_write_packets_left_shift_T_28, 1) node write_packets_left_shift_5 = mux(_write_packets_left_shift_T_27, _write_packets_left_shift_T_29, UInt<1>(0h0)) node _write_packets_right_shift_T_40 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_41 = geq(_write_packets_right_shift_T_40, UInt<5>(0h10)) node _write_packets_right_shift_T_42 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_43 = lt(_write_packets_right_shift_T_42, UInt<6>(0h20)) node _write_packets_right_shift_T_44 = and(_write_packets_right_shift_T_41, _write_packets_right_shift_T_43) node _write_packets_right_shift_T_45 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_46 = sub(UInt<6>(0h20), _write_packets_right_shift_T_45) node _write_packets_right_shift_T_47 = tail(_write_packets_right_shift_T_46, 1) node write_packets_right_shift_5 = mux(_write_packets_right_shift_T_44, _write_packets_right_shift_T_47, UInt<1>(0h0)) node write_packets_too_early_5 = geq(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_too_late_T_5 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_5 = leq(_write_packets_too_late_T_5, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T_5 = or(write_packets_too_early_5, write_packets_too_late_5) node _write_packets_packet_bytes_written_per_beat_1_T_6 = add(write_packets_left_shift_5, write_packets_right_shift_5) node _write_packets_packet_bytes_written_per_beat_1_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_6) node _write_packets_packet_bytes_written_per_beat_1_T_8 = tail(_write_packets_packet_bytes_written_per_beat_1_T_7, 1) node _write_packets_packet_bytes_written_per_beat_1_T_9 = mux(_write_packets_packet_bytes_written_per_beat_1_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_8) connect write_packets_1.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_9 node _write_packets_left_shift_T_30 = geq(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_31 = lt(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_32 = and(_write_packets_left_shift_T_30, _write_packets_left_shift_T_31) node _write_packets_left_shift_T_33 = sub(write_packets_vaddr_offset_1, UInt<6>(0h20)) node _write_packets_left_shift_T_34 = tail(_write_packets_left_shift_T_33, 1) node write_packets_left_shift_6 = mux(_write_packets_left_shift_T_32, _write_packets_left_shift_T_34, UInt<1>(0h0)) node _write_packets_right_shift_T_48 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_49 = geq(_write_packets_right_shift_T_48, UInt<6>(0h20)) node _write_packets_right_shift_T_50 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_51 = lt(_write_packets_right_shift_T_50, UInt<6>(0h30)) node _write_packets_right_shift_T_52 = and(_write_packets_right_shift_T_49, _write_packets_right_shift_T_51) node _write_packets_right_shift_T_53 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_54 = sub(UInt<6>(0h30), _write_packets_right_shift_T_53) node _write_packets_right_shift_T_55 = tail(_write_packets_right_shift_T_54, 1) node write_packets_right_shift_6 = mux(_write_packets_right_shift_T_52, _write_packets_right_shift_T_55, UInt<1>(0h0)) node write_packets_too_early_6 = geq(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_too_late_T_6 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_6 = leq(_write_packets_too_late_T_6, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T_5 = or(write_packets_too_early_6, write_packets_too_late_6) node _write_packets_packet_bytes_written_per_beat_2_T_6 = add(write_packets_left_shift_6, write_packets_right_shift_6) node _write_packets_packet_bytes_written_per_beat_2_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_6) node _write_packets_packet_bytes_written_per_beat_2_T_8 = tail(_write_packets_packet_bytes_written_per_beat_2_T_7, 1) node _write_packets_packet_bytes_written_per_beat_2_T_9 = mux(_write_packets_packet_bytes_written_per_beat_2_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_8) connect write_packets_1.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_9 node _write_packets_left_shift_T_35 = geq(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_36 = lt(write_packets_vaddr_offset_1, UInt<7>(0h40)) node _write_packets_left_shift_T_37 = and(_write_packets_left_shift_T_35, _write_packets_left_shift_T_36) node _write_packets_left_shift_T_38 = sub(write_packets_vaddr_offset_1, UInt<6>(0h30)) node _write_packets_left_shift_T_39 = tail(_write_packets_left_shift_T_38, 1) node write_packets_left_shift_7 = mux(_write_packets_left_shift_T_37, _write_packets_left_shift_T_39, UInt<1>(0h0)) node _write_packets_right_shift_T_56 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_57 = geq(_write_packets_right_shift_T_56, UInt<6>(0h30)) node _write_packets_right_shift_T_58 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_59 = lt(_write_packets_right_shift_T_58, UInt<7>(0h40)) node _write_packets_right_shift_T_60 = and(_write_packets_right_shift_T_57, _write_packets_right_shift_T_59) node _write_packets_right_shift_T_61 = add(write_packets_vaddr_offset_1, bytesLeft) node _write_packets_right_shift_T_62 = sub(UInt<7>(0h40), _write_packets_right_shift_T_61) node _write_packets_right_shift_T_63 = tail(_write_packets_right_shift_T_62, 1) node write_packets_right_shift_7 = mux(_write_packets_right_shift_T_60, _write_packets_right_shift_T_63, UInt<1>(0h0)) node write_packets_too_early_7 = geq(write_packets_vaddr_offset_1, UInt<7>(0h40)) node _write_packets_too_late_T_7 = add(write_packets_vaddr_offset_1, bytesLeft) node write_packets_too_late_7 = leq(_write_packets_too_late_T_7, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T_5 = or(write_packets_too_early_7, write_packets_too_late_7) node _write_packets_packet_bytes_written_per_beat_3_T_6 = add(write_packets_left_shift_7, write_packets_right_shift_7) node _write_packets_packet_bytes_written_per_beat_3_T_7 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_6) node _write_packets_packet_bytes_written_per_beat_3_T_8 = tail(_write_packets_packet_bytes_written_per_beat_3_T_7, 1) node _write_packets_packet_bytes_written_per_beat_3_T_9 = mux(_write_packets_packet_bytes_written_per_beat_3_T_5, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_8) connect write_packets_1.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_9 node _write_packets_vaddr_aligned_to_size_T_2 = bits(req.vaddr, 38, 6) node write_packets_vaddr_aligned_to_size_2 = cat(_write_packets_vaddr_aligned_to_size_T_2, UInt<6>(0h0)) node write_packets_vaddr_offset_2 = bits(req.vaddr, 5, 0) node _write_packets_mask_T_512 = geq(UInt<1>(0h0), write_packets_vaddr_offset_2) node _write_packets_mask_T_513 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_514 = lt(UInt<1>(0h0), _write_packets_mask_T_513) node _write_packets_mask_T_515 = and(_write_packets_mask_T_512, _write_packets_mask_T_514) node write_packets_mask_0_2 = and(_write_packets_mask_T_515, UInt<1>(0h1)) node _write_packets_mask_T_516 = geq(UInt<1>(0h1), write_packets_vaddr_offset_2) node _write_packets_mask_T_517 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_518 = lt(UInt<1>(0h1), _write_packets_mask_T_517) node _write_packets_mask_T_519 = and(_write_packets_mask_T_516, _write_packets_mask_T_518) node write_packets_mask_1_2 = and(_write_packets_mask_T_519, UInt<1>(0h1)) node _write_packets_mask_T_520 = geq(UInt<2>(0h2), write_packets_vaddr_offset_2) node _write_packets_mask_T_521 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_522 = lt(UInt<2>(0h2), _write_packets_mask_T_521) node _write_packets_mask_T_523 = and(_write_packets_mask_T_520, _write_packets_mask_T_522) node write_packets_mask_2_2 = and(_write_packets_mask_T_523, UInt<1>(0h1)) node _write_packets_mask_T_524 = geq(UInt<2>(0h3), write_packets_vaddr_offset_2) node _write_packets_mask_T_525 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_526 = lt(UInt<2>(0h3), _write_packets_mask_T_525) node _write_packets_mask_T_527 = and(_write_packets_mask_T_524, _write_packets_mask_T_526) node write_packets_mask_3_2 = and(_write_packets_mask_T_527, UInt<1>(0h1)) node _write_packets_mask_T_528 = geq(UInt<3>(0h4), write_packets_vaddr_offset_2) node _write_packets_mask_T_529 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_530 = lt(UInt<3>(0h4), _write_packets_mask_T_529) node _write_packets_mask_T_531 = and(_write_packets_mask_T_528, _write_packets_mask_T_530) node write_packets_mask_4_2 = and(_write_packets_mask_T_531, UInt<1>(0h1)) node _write_packets_mask_T_532 = geq(UInt<3>(0h5), write_packets_vaddr_offset_2) node _write_packets_mask_T_533 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_534 = lt(UInt<3>(0h5), _write_packets_mask_T_533) node _write_packets_mask_T_535 = and(_write_packets_mask_T_532, _write_packets_mask_T_534) node write_packets_mask_5_2 = and(_write_packets_mask_T_535, UInt<1>(0h1)) node _write_packets_mask_T_536 = geq(UInt<3>(0h6), write_packets_vaddr_offset_2) node _write_packets_mask_T_537 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_538 = lt(UInt<3>(0h6), _write_packets_mask_T_537) node _write_packets_mask_T_539 = and(_write_packets_mask_T_536, _write_packets_mask_T_538) node write_packets_mask_6_2 = and(_write_packets_mask_T_539, UInt<1>(0h1)) node _write_packets_mask_T_540 = geq(UInt<3>(0h7), write_packets_vaddr_offset_2) node _write_packets_mask_T_541 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_542 = lt(UInt<3>(0h7), _write_packets_mask_T_541) node _write_packets_mask_T_543 = and(_write_packets_mask_T_540, _write_packets_mask_T_542) node write_packets_mask_7_2 = and(_write_packets_mask_T_543, UInt<1>(0h1)) node _write_packets_mask_T_544 = geq(UInt<4>(0h8), write_packets_vaddr_offset_2) node _write_packets_mask_T_545 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_546 = lt(UInt<4>(0h8), _write_packets_mask_T_545) node _write_packets_mask_T_547 = and(_write_packets_mask_T_544, _write_packets_mask_T_546) node write_packets_mask_8_2 = and(_write_packets_mask_T_547, UInt<1>(0h1)) node _write_packets_mask_T_548 = geq(UInt<4>(0h9), write_packets_vaddr_offset_2) node _write_packets_mask_T_549 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_550 = lt(UInt<4>(0h9), _write_packets_mask_T_549) node _write_packets_mask_T_551 = and(_write_packets_mask_T_548, _write_packets_mask_T_550) node write_packets_mask_9_2 = and(_write_packets_mask_T_551, UInt<1>(0h1)) node _write_packets_mask_T_552 = geq(UInt<4>(0ha), write_packets_vaddr_offset_2) node _write_packets_mask_T_553 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_554 = lt(UInt<4>(0ha), _write_packets_mask_T_553) node _write_packets_mask_T_555 = and(_write_packets_mask_T_552, _write_packets_mask_T_554) node write_packets_mask_10_2 = and(_write_packets_mask_T_555, UInt<1>(0h1)) node _write_packets_mask_T_556 = geq(UInt<4>(0hb), write_packets_vaddr_offset_2) node _write_packets_mask_T_557 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_558 = lt(UInt<4>(0hb), _write_packets_mask_T_557) node _write_packets_mask_T_559 = and(_write_packets_mask_T_556, _write_packets_mask_T_558) node write_packets_mask_11_2 = and(_write_packets_mask_T_559, UInt<1>(0h1)) node _write_packets_mask_T_560 = geq(UInt<4>(0hc), write_packets_vaddr_offset_2) node _write_packets_mask_T_561 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_562 = lt(UInt<4>(0hc), _write_packets_mask_T_561) node _write_packets_mask_T_563 = and(_write_packets_mask_T_560, _write_packets_mask_T_562) node write_packets_mask_12_2 = and(_write_packets_mask_T_563, UInt<1>(0h1)) node _write_packets_mask_T_564 = geq(UInt<4>(0hd), write_packets_vaddr_offset_2) node _write_packets_mask_T_565 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_566 = lt(UInt<4>(0hd), _write_packets_mask_T_565) node _write_packets_mask_T_567 = and(_write_packets_mask_T_564, _write_packets_mask_T_566) node write_packets_mask_13_2 = and(_write_packets_mask_T_567, UInt<1>(0h1)) node _write_packets_mask_T_568 = geq(UInt<4>(0he), write_packets_vaddr_offset_2) node _write_packets_mask_T_569 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_570 = lt(UInt<4>(0he), _write_packets_mask_T_569) node _write_packets_mask_T_571 = and(_write_packets_mask_T_568, _write_packets_mask_T_570) node write_packets_mask_14_2 = and(_write_packets_mask_T_571, UInt<1>(0h1)) node _write_packets_mask_T_572 = geq(UInt<4>(0hf), write_packets_vaddr_offset_2) node _write_packets_mask_T_573 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_574 = lt(UInt<4>(0hf), _write_packets_mask_T_573) node _write_packets_mask_T_575 = and(_write_packets_mask_T_572, _write_packets_mask_T_574) node write_packets_mask_15_2 = and(_write_packets_mask_T_575, UInt<1>(0h1)) node _write_packets_mask_T_576 = geq(UInt<5>(0h10), write_packets_vaddr_offset_2) node _write_packets_mask_T_577 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_578 = lt(UInt<5>(0h10), _write_packets_mask_T_577) node _write_packets_mask_T_579 = and(_write_packets_mask_T_576, _write_packets_mask_T_578) node write_packets_mask_16_2 = and(_write_packets_mask_T_579, UInt<1>(0h1)) node _write_packets_mask_T_580 = geq(UInt<5>(0h11), write_packets_vaddr_offset_2) node _write_packets_mask_T_581 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_582 = lt(UInt<5>(0h11), _write_packets_mask_T_581) node _write_packets_mask_T_583 = and(_write_packets_mask_T_580, _write_packets_mask_T_582) node write_packets_mask_17_2 = and(_write_packets_mask_T_583, UInt<1>(0h1)) node _write_packets_mask_T_584 = geq(UInt<5>(0h12), write_packets_vaddr_offset_2) node _write_packets_mask_T_585 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_586 = lt(UInt<5>(0h12), _write_packets_mask_T_585) node _write_packets_mask_T_587 = and(_write_packets_mask_T_584, _write_packets_mask_T_586) node write_packets_mask_18_2 = and(_write_packets_mask_T_587, UInt<1>(0h1)) node _write_packets_mask_T_588 = geq(UInt<5>(0h13), write_packets_vaddr_offset_2) node _write_packets_mask_T_589 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_590 = lt(UInt<5>(0h13), _write_packets_mask_T_589) node _write_packets_mask_T_591 = and(_write_packets_mask_T_588, _write_packets_mask_T_590) node write_packets_mask_19_2 = and(_write_packets_mask_T_591, UInt<1>(0h1)) node _write_packets_mask_T_592 = geq(UInt<5>(0h14), write_packets_vaddr_offset_2) node _write_packets_mask_T_593 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_594 = lt(UInt<5>(0h14), _write_packets_mask_T_593) node _write_packets_mask_T_595 = and(_write_packets_mask_T_592, _write_packets_mask_T_594) node write_packets_mask_20_2 = and(_write_packets_mask_T_595, UInt<1>(0h1)) node _write_packets_mask_T_596 = geq(UInt<5>(0h15), write_packets_vaddr_offset_2) node _write_packets_mask_T_597 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_598 = lt(UInt<5>(0h15), _write_packets_mask_T_597) node _write_packets_mask_T_599 = and(_write_packets_mask_T_596, _write_packets_mask_T_598) node write_packets_mask_21_2 = and(_write_packets_mask_T_599, UInt<1>(0h1)) node _write_packets_mask_T_600 = geq(UInt<5>(0h16), write_packets_vaddr_offset_2) node _write_packets_mask_T_601 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_602 = lt(UInt<5>(0h16), _write_packets_mask_T_601) node _write_packets_mask_T_603 = and(_write_packets_mask_T_600, _write_packets_mask_T_602) node write_packets_mask_22_2 = and(_write_packets_mask_T_603, UInt<1>(0h1)) node _write_packets_mask_T_604 = geq(UInt<5>(0h17), write_packets_vaddr_offset_2) node _write_packets_mask_T_605 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_606 = lt(UInt<5>(0h17), _write_packets_mask_T_605) node _write_packets_mask_T_607 = and(_write_packets_mask_T_604, _write_packets_mask_T_606) node write_packets_mask_23_2 = and(_write_packets_mask_T_607, UInt<1>(0h1)) node _write_packets_mask_T_608 = geq(UInt<5>(0h18), write_packets_vaddr_offset_2) node _write_packets_mask_T_609 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_610 = lt(UInt<5>(0h18), _write_packets_mask_T_609) node _write_packets_mask_T_611 = and(_write_packets_mask_T_608, _write_packets_mask_T_610) node write_packets_mask_24_2 = and(_write_packets_mask_T_611, UInt<1>(0h1)) node _write_packets_mask_T_612 = geq(UInt<5>(0h19), write_packets_vaddr_offset_2) node _write_packets_mask_T_613 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_614 = lt(UInt<5>(0h19), _write_packets_mask_T_613) node _write_packets_mask_T_615 = and(_write_packets_mask_T_612, _write_packets_mask_T_614) node write_packets_mask_25_2 = and(_write_packets_mask_T_615, UInt<1>(0h1)) node _write_packets_mask_T_616 = geq(UInt<5>(0h1a), write_packets_vaddr_offset_2) node _write_packets_mask_T_617 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_618 = lt(UInt<5>(0h1a), _write_packets_mask_T_617) node _write_packets_mask_T_619 = and(_write_packets_mask_T_616, _write_packets_mask_T_618) node write_packets_mask_26_2 = and(_write_packets_mask_T_619, UInt<1>(0h1)) node _write_packets_mask_T_620 = geq(UInt<5>(0h1b), write_packets_vaddr_offset_2) node _write_packets_mask_T_621 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_622 = lt(UInt<5>(0h1b), _write_packets_mask_T_621) node _write_packets_mask_T_623 = and(_write_packets_mask_T_620, _write_packets_mask_T_622) node write_packets_mask_27_2 = and(_write_packets_mask_T_623, UInt<1>(0h1)) node _write_packets_mask_T_624 = geq(UInt<5>(0h1c), write_packets_vaddr_offset_2) node _write_packets_mask_T_625 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_626 = lt(UInt<5>(0h1c), _write_packets_mask_T_625) node _write_packets_mask_T_627 = and(_write_packets_mask_T_624, _write_packets_mask_T_626) node write_packets_mask_28_2 = and(_write_packets_mask_T_627, UInt<1>(0h1)) node _write_packets_mask_T_628 = geq(UInt<5>(0h1d), write_packets_vaddr_offset_2) node _write_packets_mask_T_629 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_630 = lt(UInt<5>(0h1d), _write_packets_mask_T_629) node _write_packets_mask_T_631 = and(_write_packets_mask_T_628, _write_packets_mask_T_630) node write_packets_mask_29_2 = and(_write_packets_mask_T_631, UInt<1>(0h1)) node _write_packets_mask_T_632 = geq(UInt<5>(0h1e), write_packets_vaddr_offset_2) node _write_packets_mask_T_633 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_634 = lt(UInt<5>(0h1e), _write_packets_mask_T_633) node _write_packets_mask_T_635 = and(_write_packets_mask_T_632, _write_packets_mask_T_634) node write_packets_mask_30_2 = and(_write_packets_mask_T_635, UInt<1>(0h1)) node _write_packets_mask_T_636 = geq(UInt<5>(0h1f), write_packets_vaddr_offset_2) node _write_packets_mask_T_637 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_638 = lt(UInt<5>(0h1f), _write_packets_mask_T_637) node _write_packets_mask_T_639 = and(_write_packets_mask_T_636, _write_packets_mask_T_638) node write_packets_mask_31_2 = and(_write_packets_mask_T_639, UInt<1>(0h1)) node _write_packets_mask_T_640 = geq(UInt<6>(0h20), write_packets_vaddr_offset_2) node _write_packets_mask_T_641 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_642 = lt(UInt<6>(0h20), _write_packets_mask_T_641) node _write_packets_mask_T_643 = and(_write_packets_mask_T_640, _write_packets_mask_T_642) node write_packets_mask_32_2 = and(_write_packets_mask_T_643, UInt<1>(0h1)) node _write_packets_mask_T_644 = geq(UInt<6>(0h21), write_packets_vaddr_offset_2) node _write_packets_mask_T_645 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_646 = lt(UInt<6>(0h21), _write_packets_mask_T_645) node _write_packets_mask_T_647 = and(_write_packets_mask_T_644, _write_packets_mask_T_646) node write_packets_mask_33_2 = and(_write_packets_mask_T_647, UInt<1>(0h1)) node _write_packets_mask_T_648 = geq(UInt<6>(0h22), write_packets_vaddr_offset_2) node _write_packets_mask_T_649 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_650 = lt(UInt<6>(0h22), _write_packets_mask_T_649) node _write_packets_mask_T_651 = and(_write_packets_mask_T_648, _write_packets_mask_T_650) node write_packets_mask_34_2 = and(_write_packets_mask_T_651, UInt<1>(0h1)) node _write_packets_mask_T_652 = geq(UInt<6>(0h23), write_packets_vaddr_offset_2) node _write_packets_mask_T_653 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_654 = lt(UInt<6>(0h23), _write_packets_mask_T_653) node _write_packets_mask_T_655 = and(_write_packets_mask_T_652, _write_packets_mask_T_654) node write_packets_mask_35_2 = and(_write_packets_mask_T_655, UInt<1>(0h1)) node _write_packets_mask_T_656 = geq(UInt<6>(0h24), write_packets_vaddr_offset_2) node _write_packets_mask_T_657 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_658 = lt(UInt<6>(0h24), _write_packets_mask_T_657) node _write_packets_mask_T_659 = and(_write_packets_mask_T_656, _write_packets_mask_T_658) node write_packets_mask_36_2 = and(_write_packets_mask_T_659, UInt<1>(0h1)) node _write_packets_mask_T_660 = geq(UInt<6>(0h25), write_packets_vaddr_offset_2) node _write_packets_mask_T_661 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_662 = lt(UInt<6>(0h25), _write_packets_mask_T_661) node _write_packets_mask_T_663 = and(_write_packets_mask_T_660, _write_packets_mask_T_662) node write_packets_mask_37_2 = and(_write_packets_mask_T_663, UInt<1>(0h1)) node _write_packets_mask_T_664 = geq(UInt<6>(0h26), write_packets_vaddr_offset_2) node _write_packets_mask_T_665 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_666 = lt(UInt<6>(0h26), _write_packets_mask_T_665) node _write_packets_mask_T_667 = and(_write_packets_mask_T_664, _write_packets_mask_T_666) node write_packets_mask_38_2 = and(_write_packets_mask_T_667, UInt<1>(0h1)) node _write_packets_mask_T_668 = geq(UInt<6>(0h27), write_packets_vaddr_offset_2) node _write_packets_mask_T_669 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_670 = lt(UInt<6>(0h27), _write_packets_mask_T_669) node _write_packets_mask_T_671 = and(_write_packets_mask_T_668, _write_packets_mask_T_670) node write_packets_mask_39_2 = and(_write_packets_mask_T_671, UInt<1>(0h1)) node _write_packets_mask_T_672 = geq(UInt<6>(0h28), write_packets_vaddr_offset_2) node _write_packets_mask_T_673 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_674 = lt(UInt<6>(0h28), _write_packets_mask_T_673) node _write_packets_mask_T_675 = and(_write_packets_mask_T_672, _write_packets_mask_T_674) node write_packets_mask_40_2 = and(_write_packets_mask_T_675, UInt<1>(0h1)) node _write_packets_mask_T_676 = geq(UInt<6>(0h29), write_packets_vaddr_offset_2) node _write_packets_mask_T_677 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_678 = lt(UInt<6>(0h29), _write_packets_mask_T_677) node _write_packets_mask_T_679 = and(_write_packets_mask_T_676, _write_packets_mask_T_678) node write_packets_mask_41_2 = and(_write_packets_mask_T_679, UInt<1>(0h1)) node _write_packets_mask_T_680 = geq(UInt<6>(0h2a), write_packets_vaddr_offset_2) node _write_packets_mask_T_681 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_682 = lt(UInt<6>(0h2a), _write_packets_mask_T_681) node _write_packets_mask_T_683 = and(_write_packets_mask_T_680, _write_packets_mask_T_682) node write_packets_mask_42_2 = and(_write_packets_mask_T_683, UInt<1>(0h1)) node _write_packets_mask_T_684 = geq(UInt<6>(0h2b), write_packets_vaddr_offset_2) node _write_packets_mask_T_685 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_686 = lt(UInt<6>(0h2b), _write_packets_mask_T_685) node _write_packets_mask_T_687 = and(_write_packets_mask_T_684, _write_packets_mask_T_686) node write_packets_mask_43_2 = and(_write_packets_mask_T_687, UInt<1>(0h1)) node _write_packets_mask_T_688 = geq(UInt<6>(0h2c), write_packets_vaddr_offset_2) node _write_packets_mask_T_689 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_690 = lt(UInt<6>(0h2c), _write_packets_mask_T_689) node _write_packets_mask_T_691 = and(_write_packets_mask_T_688, _write_packets_mask_T_690) node write_packets_mask_44_2 = and(_write_packets_mask_T_691, UInt<1>(0h1)) node _write_packets_mask_T_692 = geq(UInt<6>(0h2d), write_packets_vaddr_offset_2) node _write_packets_mask_T_693 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_694 = lt(UInt<6>(0h2d), _write_packets_mask_T_693) node _write_packets_mask_T_695 = and(_write_packets_mask_T_692, _write_packets_mask_T_694) node write_packets_mask_45_2 = and(_write_packets_mask_T_695, UInt<1>(0h1)) node _write_packets_mask_T_696 = geq(UInt<6>(0h2e), write_packets_vaddr_offset_2) node _write_packets_mask_T_697 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_698 = lt(UInt<6>(0h2e), _write_packets_mask_T_697) node _write_packets_mask_T_699 = and(_write_packets_mask_T_696, _write_packets_mask_T_698) node write_packets_mask_46_2 = and(_write_packets_mask_T_699, UInt<1>(0h1)) node _write_packets_mask_T_700 = geq(UInt<6>(0h2f), write_packets_vaddr_offset_2) node _write_packets_mask_T_701 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_702 = lt(UInt<6>(0h2f), _write_packets_mask_T_701) node _write_packets_mask_T_703 = and(_write_packets_mask_T_700, _write_packets_mask_T_702) node write_packets_mask_47_2 = and(_write_packets_mask_T_703, UInt<1>(0h1)) node _write_packets_mask_T_704 = geq(UInt<6>(0h30), write_packets_vaddr_offset_2) node _write_packets_mask_T_705 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_706 = lt(UInt<6>(0h30), _write_packets_mask_T_705) node _write_packets_mask_T_707 = and(_write_packets_mask_T_704, _write_packets_mask_T_706) node write_packets_mask_48_2 = and(_write_packets_mask_T_707, UInt<1>(0h1)) node _write_packets_mask_T_708 = geq(UInt<6>(0h31), write_packets_vaddr_offset_2) node _write_packets_mask_T_709 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_710 = lt(UInt<6>(0h31), _write_packets_mask_T_709) node _write_packets_mask_T_711 = and(_write_packets_mask_T_708, _write_packets_mask_T_710) node write_packets_mask_49_2 = and(_write_packets_mask_T_711, UInt<1>(0h1)) node _write_packets_mask_T_712 = geq(UInt<6>(0h32), write_packets_vaddr_offset_2) node _write_packets_mask_T_713 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_714 = lt(UInt<6>(0h32), _write_packets_mask_T_713) node _write_packets_mask_T_715 = and(_write_packets_mask_T_712, _write_packets_mask_T_714) node write_packets_mask_50_2 = and(_write_packets_mask_T_715, UInt<1>(0h1)) node _write_packets_mask_T_716 = geq(UInt<6>(0h33), write_packets_vaddr_offset_2) node _write_packets_mask_T_717 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_718 = lt(UInt<6>(0h33), _write_packets_mask_T_717) node _write_packets_mask_T_719 = and(_write_packets_mask_T_716, _write_packets_mask_T_718) node write_packets_mask_51_2 = and(_write_packets_mask_T_719, UInt<1>(0h1)) node _write_packets_mask_T_720 = geq(UInt<6>(0h34), write_packets_vaddr_offset_2) node _write_packets_mask_T_721 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_722 = lt(UInt<6>(0h34), _write_packets_mask_T_721) node _write_packets_mask_T_723 = and(_write_packets_mask_T_720, _write_packets_mask_T_722) node write_packets_mask_52_2 = and(_write_packets_mask_T_723, UInt<1>(0h1)) node _write_packets_mask_T_724 = geq(UInt<6>(0h35), write_packets_vaddr_offset_2) node _write_packets_mask_T_725 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_726 = lt(UInt<6>(0h35), _write_packets_mask_T_725) node _write_packets_mask_T_727 = and(_write_packets_mask_T_724, _write_packets_mask_T_726) node write_packets_mask_53_2 = and(_write_packets_mask_T_727, UInt<1>(0h1)) node _write_packets_mask_T_728 = geq(UInt<6>(0h36), write_packets_vaddr_offset_2) node _write_packets_mask_T_729 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_730 = lt(UInt<6>(0h36), _write_packets_mask_T_729) node _write_packets_mask_T_731 = and(_write_packets_mask_T_728, _write_packets_mask_T_730) node write_packets_mask_54_2 = and(_write_packets_mask_T_731, UInt<1>(0h1)) node _write_packets_mask_T_732 = geq(UInt<6>(0h37), write_packets_vaddr_offset_2) node _write_packets_mask_T_733 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_734 = lt(UInt<6>(0h37), _write_packets_mask_T_733) node _write_packets_mask_T_735 = and(_write_packets_mask_T_732, _write_packets_mask_T_734) node write_packets_mask_55_2 = and(_write_packets_mask_T_735, UInt<1>(0h1)) node _write_packets_mask_T_736 = geq(UInt<6>(0h38), write_packets_vaddr_offset_2) node _write_packets_mask_T_737 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_738 = lt(UInt<6>(0h38), _write_packets_mask_T_737) node _write_packets_mask_T_739 = and(_write_packets_mask_T_736, _write_packets_mask_T_738) node write_packets_mask_56_2 = and(_write_packets_mask_T_739, UInt<1>(0h1)) node _write_packets_mask_T_740 = geq(UInt<6>(0h39), write_packets_vaddr_offset_2) node _write_packets_mask_T_741 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_742 = lt(UInt<6>(0h39), _write_packets_mask_T_741) node _write_packets_mask_T_743 = and(_write_packets_mask_T_740, _write_packets_mask_T_742) node write_packets_mask_57_2 = and(_write_packets_mask_T_743, UInt<1>(0h1)) node _write_packets_mask_T_744 = geq(UInt<6>(0h3a), write_packets_vaddr_offset_2) node _write_packets_mask_T_745 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_746 = lt(UInt<6>(0h3a), _write_packets_mask_T_745) node _write_packets_mask_T_747 = and(_write_packets_mask_T_744, _write_packets_mask_T_746) node write_packets_mask_58_2 = and(_write_packets_mask_T_747, UInt<1>(0h1)) node _write_packets_mask_T_748 = geq(UInt<6>(0h3b), write_packets_vaddr_offset_2) node _write_packets_mask_T_749 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_750 = lt(UInt<6>(0h3b), _write_packets_mask_T_749) node _write_packets_mask_T_751 = and(_write_packets_mask_T_748, _write_packets_mask_T_750) node write_packets_mask_59_2 = and(_write_packets_mask_T_751, UInt<1>(0h1)) node _write_packets_mask_T_752 = geq(UInt<6>(0h3c), write_packets_vaddr_offset_2) node _write_packets_mask_T_753 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_754 = lt(UInt<6>(0h3c), _write_packets_mask_T_753) node _write_packets_mask_T_755 = and(_write_packets_mask_T_752, _write_packets_mask_T_754) node write_packets_mask_60_2 = and(_write_packets_mask_T_755, UInt<1>(0h1)) node _write_packets_mask_T_756 = geq(UInt<6>(0h3d), write_packets_vaddr_offset_2) node _write_packets_mask_T_757 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_758 = lt(UInt<6>(0h3d), _write_packets_mask_T_757) node _write_packets_mask_T_759 = and(_write_packets_mask_T_756, _write_packets_mask_T_758) node write_packets_mask_61_2 = and(_write_packets_mask_T_759, UInt<1>(0h1)) node _write_packets_mask_T_760 = geq(UInt<6>(0h3e), write_packets_vaddr_offset_2) node _write_packets_mask_T_761 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_762 = lt(UInt<6>(0h3e), _write_packets_mask_T_761) node _write_packets_mask_T_763 = and(_write_packets_mask_T_760, _write_packets_mask_T_762) node write_packets_mask_62_2 = and(_write_packets_mask_T_763, UInt<1>(0h1)) node _write_packets_mask_T_764 = geq(UInt<6>(0h3f), write_packets_vaddr_offset_2) node _write_packets_mask_T_765 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_mask_T_766 = lt(UInt<6>(0h3f), _write_packets_mask_T_765) node _write_packets_mask_T_767 = and(_write_packets_mask_T_764, _write_packets_mask_T_766) node write_packets_mask_63_2 = and(_write_packets_mask_T_767, UInt<1>(0h1)) node _write_packets_bytes_written_T_8 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_bytes_written_T_9 = gt(_write_packets_bytes_written_T_8, UInt<7>(0h40)) node _write_packets_bytes_written_T_10 = sub(UInt<7>(0h40), write_packets_vaddr_offset_2) node _write_packets_bytes_written_T_11 = tail(_write_packets_bytes_written_T_10, 1) node write_packets_bytes_written_2 = mux(_write_packets_bytes_written_T_9, _write_packets_bytes_written_T_11, bytesLeft) wire write_packets_2 : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]} connect write_packets_2.size, UInt<7>(0h40) connect write_packets_2.lg_size, UInt<3>(0h6) wire _write_packets_WIRE_10 : UInt<1>[16] connect _write_packets_WIRE_10[0], write_packets_mask_0_2 connect _write_packets_WIRE_10[1], write_packets_mask_1_2 connect _write_packets_WIRE_10[2], write_packets_mask_2_2 connect _write_packets_WIRE_10[3], write_packets_mask_3_2 connect _write_packets_WIRE_10[4], write_packets_mask_4_2 connect _write_packets_WIRE_10[5], write_packets_mask_5_2 connect _write_packets_WIRE_10[6], write_packets_mask_6_2 connect _write_packets_WIRE_10[7], write_packets_mask_7_2 connect _write_packets_WIRE_10[8], write_packets_mask_8_2 connect _write_packets_WIRE_10[9], write_packets_mask_9_2 connect _write_packets_WIRE_10[10], write_packets_mask_10_2 connect _write_packets_WIRE_10[11], write_packets_mask_11_2 connect _write_packets_WIRE_10[12], write_packets_mask_12_2 connect _write_packets_WIRE_10[13], write_packets_mask_13_2 connect _write_packets_WIRE_10[14], write_packets_mask_14_2 connect _write_packets_WIRE_10[15], write_packets_mask_15_2 wire _write_packets_WIRE_11 : UInt<1>[16] connect _write_packets_WIRE_11[0], write_packets_mask_16_2 connect _write_packets_WIRE_11[1], write_packets_mask_17_2 connect _write_packets_WIRE_11[2], write_packets_mask_18_2 connect _write_packets_WIRE_11[3], write_packets_mask_19_2 connect _write_packets_WIRE_11[4], write_packets_mask_20_2 connect _write_packets_WIRE_11[5], write_packets_mask_21_2 connect _write_packets_WIRE_11[6], write_packets_mask_22_2 connect _write_packets_WIRE_11[7], write_packets_mask_23_2 connect _write_packets_WIRE_11[8], write_packets_mask_24_2 connect _write_packets_WIRE_11[9], write_packets_mask_25_2 connect _write_packets_WIRE_11[10], write_packets_mask_26_2 connect _write_packets_WIRE_11[11], write_packets_mask_27_2 connect _write_packets_WIRE_11[12], write_packets_mask_28_2 connect _write_packets_WIRE_11[13], write_packets_mask_29_2 connect _write_packets_WIRE_11[14], write_packets_mask_30_2 connect _write_packets_WIRE_11[15], write_packets_mask_31_2 wire _write_packets_WIRE_12 : UInt<1>[16] connect _write_packets_WIRE_12[0], write_packets_mask_32_2 connect _write_packets_WIRE_12[1], write_packets_mask_33_2 connect _write_packets_WIRE_12[2], write_packets_mask_34_2 connect _write_packets_WIRE_12[3], write_packets_mask_35_2 connect _write_packets_WIRE_12[4], write_packets_mask_36_2 connect _write_packets_WIRE_12[5], write_packets_mask_37_2 connect _write_packets_WIRE_12[6], write_packets_mask_38_2 connect _write_packets_WIRE_12[7], write_packets_mask_39_2 connect _write_packets_WIRE_12[8], write_packets_mask_40_2 connect _write_packets_WIRE_12[9], write_packets_mask_41_2 connect _write_packets_WIRE_12[10], write_packets_mask_42_2 connect _write_packets_WIRE_12[11], write_packets_mask_43_2 connect _write_packets_WIRE_12[12], write_packets_mask_44_2 connect _write_packets_WIRE_12[13], write_packets_mask_45_2 connect _write_packets_WIRE_12[14], write_packets_mask_46_2 connect _write_packets_WIRE_12[15], write_packets_mask_47_2 wire _write_packets_WIRE_13 : UInt<1>[16] connect _write_packets_WIRE_13[0], write_packets_mask_48_2 connect _write_packets_WIRE_13[1], write_packets_mask_49_2 connect _write_packets_WIRE_13[2], write_packets_mask_50_2 connect _write_packets_WIRE_13[3], write_packets_mask_51_2 connect _write_packets_WIRE_13[4], write_packets_mask_52_2 connect _write_packets_WIRE_13[5], write_packets_mask_53_2 connect _write_packets_WIRE_13[6], write_packets_mask_54_2 connect _write_packets_WIRE_13[7], write_packets_mask_55_2 connect _write_packets_WIRE_13[8], write_packets_mask_56_2 connect _write_packets_WIRE_13[9], write_packets_mask_57_2 connect _write_packets_WIRE_13[10], write_packets_mask_58_2 connect _write_packets_WIRE_13[11], write_packets_mask_59_2 connect _write_packets_WIRE_13[12], write_packets_mask_60_2 connect _write_packets_WIRE_13[13], write_packets_mask_61_2 connect _write_packets_WIRE_13[14], write_packets_mask_62_2 connect _write_packets_WIRE_13[15], write_packets_mask_63_2 wire _write_packets_WIRE_14 : UInt<1>[16][4] connect _write_packets_WIRE_14[0], _write_packets_WIRE_10 connect _write_packets_WIRE_14[1], _write_packets_WIRE_11 connect _write_packets_WIRE_14[2], _write_packets_WIRE_12 connect _write_packets_WIRE_14[3], _write_packets_WIRE_13 connect write_packets_2.mask, _write_packets_WIRE_14 connect write_packets_2.vaddr, write_packets_vaddr_aligned_to_size_2 node _write_packets_packet_is_full_T_46 = and(write_packets_mask_0_2, write_packets_mask_1_2) node _write_packets_packet_is_full_T_47 = and(_write_packets_packet_is_full_T_46, write_packets_mask_2_2) node _write_packets_packet_is_full_T_48 = and(_write_packets_packet_is_full_T_47, write_packets_mask_3_2) node _write_packets_packet_is_full_T_49 = and(_write_packets_packet_is_full_T_48, write_packets_mask_4_2) node _write_packets_packet_is_full_T_50 = and(_write_packets_packet_is_full_T_49, write_packets_mask_5_2) node _write_packets_packet_is_full_T_51 = and(_write_packets_packet_is_full_T_50, write_packets_mask_6_2) node _write_packets_packet_is_full_T_52 = and(_write_packets_packet_is_full_T_51, write_packets_mask_7_2) node _write_packets_packet_is_full_T_53 = and(_write_packets_packet_is_full_T_52, write_packets_mask_8_2) node _write_packets_packet_is_full_T_54 = and(_write_packets_packet_is_full_T_53, write_packets_mask_9_2) node _write_packets_packet_is_full_T_55 = and(_write_packets_packet_is_full_T_54, write_packets_mask_10_2) node _write_packets_packet_is_full_T_56 = and(_write_packets_packet_is_full_T_55, write_packets_mask_11_2) node _write_packets_packet_is_full_T_57 = and(_write_packets_packet_is_full_T_56, write_packets_mask_12_2) node _write_packets_packet_is_full_T_58 = and(_write_packets_packet_is_full_T_57, write_packets_mask_13_2) node _write_packets_packet_is_full_T_59 = and(_write_packets_packet_is_full_T_58, write_packets_mask_14_2) node _write_packets_packet_is_full_T_60 = and(_write_packets_packet_is_full_T_59, write_packets_mask_15_2) node _write_packets_packet_is_full_T_61 = and(_write_packets_packet_is_full_T_60, write_packets_mask_16_2) node _write_packets_packet_is_full_T_62 = and(_write_packets_packet_is_full_T_61, write_packets_mask_17_2) node _write_packets_packet_is_full_T_63 = and(_write_packets_packet_is_full_T_62, write_packets_mask_18_2) node _write_packets_packet_is_full_T_64 = and(_write_packets_packet_is_full_T_63, write_packets_mask_19_2) node _write_packets_packet_is_full_T_65 = and(_write_packets_packet_is_full_T_64, write_packets_mask_20_2) node _write_packets_packet_is_full_T_66 = and(_write_packets_packet_is_full_T_65, write_packets_mask_21_2) node _write_packets_packet_is_full_T_67 = and(_write_packets_packet_is_full_T_66, write_packets_mask_22_2) node _write_packets_packet_is_full_T_68 = and(_write_packets_packet_is_full_T_67, write_packets_mask_23_2) node _write_packets_packet_is_full_T_69 = and(_write_packets_packet_is_full_T_68, write_packets_mask_24_2) node _write_packets_packet_is_full_T_70 = and(_write_packets_packet_is_full_T_69, write_packets_mask_25_2) node _write_packets_packet_is_full_T_71 = and(_write_packets_packet_is_full_T_70, write_packets_mask_26_2) node _write_packets_packet_is_full_T_72 = and(_write_packets_packet_is_full_T_71, write_packets_mask_27_2) node _write_packets_packet_is_full_T_73 = and(_write_packets_packet_is_full_T_72, write_packets_mask_28_2) node _write_packets_packet_is_full_T_74 = and(_write_packets_packet_is_full_T_73, write_packets_mask_29_2) node _write_packets_packet_is_full_T_75 = and(_write_packets_packet_is_full_T_74, write_packets_mask_30_2) node _write_packets_packet_is_full_T_76 = and(_write_packets_packet_is_full_T_75, write_packets_mask_31_2) node _write_packets_packet_is_full_T_77 = and(_write_packets_packet_is_full_T_76, write_packets_mask_32_2) node _write_packets_packet_is_full_T_78 = and(_write_packets_packet_is_full_T_77, write_packets_mask_33_2) node _write_packets_packet_is_full_T_79 = and(_write_packets_packet_is_full_T_78, write_packets_mask_34_2) node _write_packets_packet_is_full_T_80 = and(_write_packets_packet_is_full_T_79, write_packets_mask_35_2) node _write_packets_packet_is_full_T_81 = and(_write_packets_packet_is_full_T_80, write_packets_mask_36_2) node _write_packets_packet_is_full_T_82 = and(_write_packets_packet_is_full_T_81, write_packets_mask_37_2) node _write_packets_packet_is_full_T_83 = and(_write_packets_packet_is_full_T_82, write_packets_mask_38_2) node _write_packets_packet_is_full_T_84 = and(_write_packets_packet_is_full_T_83, write_packets_mask_39_2) node _write_packets_packet_is_full_T_85 = and(_write_packets_packet_is_full_T_84, write_packets_mask_40_2) node _write_packets_packet_is_full_T_86 = and(_write_packets_packet_is_full_T_85, write_packets_mask_41_2) node _write_packets_packet_is_full_T_87 = and(_write_packets_packet_is_full_T_86, write_packets_mask_42_2) node _write_packets_packet_is_full_T_88 = and(_write_packets_packet_is_full_T_87, write_packets_mask_43_2) node _write_packets_packet_is_full_T_89 = and(_write_packets_packet_is_full_T_88, write_packets_mask_44_2) node _write_packets_packet_is_full_T_90 = and(_write_packets_packet_is_full_T_89, write_packets_mask_45_2) node _write_packets_packet_is_full_T_91 = and(_write_packets_packet_is_full_T_90, write_packets_mask_46_2) node _write_packets_packet_is_full_T_92 = and(_write_packets_packet_is_full_T_91, write_packets_mask_47_2) node _write_packets_packet_is_full_T_93 = and(_write_packets_packet_is_full_T_92, write_packets_mask_48_2) node _write_packets_packet_is_full_T_94 = and(_write_packets_packet_is_full_T_93, write_packets_mask_49_2) node _write_packets_packet_is_full_T_95 = and(_write_packets_packet_is_full_T_94, write_packets_mask_50_2) node _write_packets_packet_is_full_T_96 = and(_write_packets_packet_is_full_T_95, write_packets_mask_51_2) node _write_packets_packet_is_full_T_97 = and(_write_packets_packet_is_full_T_96, write_packets_mask_52_2) node _write_packets_packet_is_full_T_98 = and(_write_packets_packet_is_full_T_97, write_packets_mask_53_2) node _write_packets_packet_is_full_T_99 = and(_write_packets_packet_is_full_T_98, write_packets_mask_54_2) node _write_packets_packet_is_full_T_100 = and(_write_packets_packet_is_full_T_99, write_packets_mask_55_2) node _write_packets_packet_is_full_T_101 = and(_write_packets_packet_is_full_T_100, write_packets_mask_56_2) node _write_packets_packet_is_full_T_102 = and(_write_packets_packet_is_full_T_101, write_packets_mask_57_2) node _write_packets_packet_is_full_T_103 = and(_write_packets_packet_is_full_T_102, write_packets_mask_58_2) node _write_packets_packet_is_full_T_104 = and(_write_packets_packet_is_full_T_103, write_packets_mask_59_2) node _write_packets_packet_is_full_T_105 = and(_write_packets_packet_is_full_T_104, write_packets_mask_60_2) node _write_packets_packet_is_full_T_106 = and(_write_packets_packet_is_full_T_105, write_packets_mask_61_2) node _write_packets_packet_is_full_T_107 = and(_write_packets_packet_is_full_T_106, write_packets_mask_62_2) node _write_packets_packet_is_full_T_108 = and(_write_packets_packet_is_full_T_107, write_packets_mask_63_2) connect write_packets_2.is_full, _write_packets_packet_is_full_T_108 connect write_packets_2.bytes_written, write_packets_bytes_written_2 node _write_packets_left_shift_T_40 = geq(write_packets_vaddr_offset_2, UInt<1>(0h0)) node _write_packets_left_shift_T_41 = lt(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_42 = and(_write_packets_left_shift_T_40, _write_packets_left_shift_T_41) node _write_packets_left_shift_T_43 = sub(write_packets_vaddr_offset_2, UInt<1>(0h0)) node _write_packets_left_shift_T_44 = tail(_write_packets_left_shift_T_43, 1) node write_packets_left_shift_8 = mux(_write_packets_left_shift_T_42, _write_packets_left_shift_T_44, UInt<1>(0h0)) node _write_packets_right_shift_T_64 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_65 = geq(_write_packets_right_shift_T_64, UInt<1>(0h0)) node _write_packets_right_shift_T_66 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_67 = lt(_write_packets_right_shift_T_66, UInt<5>(0h10)) node _write_packets_right_shift_T_68 = and(_write_packets_right_shift_T_65, _write_packets_right_shift_T_67) node _write_packets_right_shift_T_69 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_70 = sub(UInt<5>(0h10), _write_packets_right_shift_T_69) node _write_packets_right_shift_T_71 = tail(_write_packets_right_shift_T_70, 1) node write_packets_right_shift_8 = mux(_write_packets_right_shift_T_68, _write_packets_right_shift_T_71, UInt<1>(0h0)) node write_packets_too_early_8 = geq(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_too_late_T_8 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_8 = leq(_write_packets_too_late_T_8, UInt<1>(0h0)) node _write_packets_packet_bytes_written_per_beat_0_T_10 = or(write_packets_too_early_8, write_packets_too_late_8) node _write_packets_packet_bytes_written_per_beat_0_T_11 = add(write_packets_left_shift_8, write_packets_right_shift_8) node _write_packets_packet_bytes_written_per_beat_0_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_0_T_11) node _write_packets_packet_bytes_written_per_beat_0_T_13 = tail(_write_packets_packet_bytes_written_per_beat_0_T_12, 1) node _write_packets_packet_bytes_written_per_beat_0_T_14 = mux(_write_packets_packet_bytes_written_per_beat_0_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_0_T_13) connect write_packets_2.bytes_written_per_beat[0], _write_packets_packet_bytes_written_per_beat_0_T_14 node _write_packets_left_shift_T_45 = geq(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_46 = lt(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_47 = and(_write_packets_left_shift_T_45, _write_packets_left_shift_T_46) node _write_packets_left_shift_T_48 = sub(write_packets_vaddr_offset_2, UInt<5>(0h10)) node _write_packets_left_shift_T_49 = tail(_write_packets_left_shift_T_48, 1) node write_packets_left_shift_9 = mux(_write_packets_left_shift_T_47, _write_packets_left_shift_T_49, UInt<1>(0h0)) node _write_packets_right_shift_T_72 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_73 = geq(_write_packets_right_shift_T_72, UInt<5>(0h10)) node _write_packets_right_shift_T_74 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_75 = lt(_write_packets_right_shift_T_74, UInt<6>(0h20)) node _write_packets_right_shift_T_76 = and(_write_packets_right_shift_T_73, _write_packets_right_shift_T_75) node _write_packets_right_shift_T_77 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_78 = sub(UInt<6>(0h20), _write_packets_right_shift_T_77) node _write_packets_right_shift_T_79 = tail(_write_packets_right_shift_T_78, 1) node write_packets_right_shift_9 = mux(_write_packets_right_shift_T_76, _write_packets_right_shift_T_79, UInt<1>(0h0)) node write_packets_too_early_9 = geq(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_too_late_T_9 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_9 = leq(_write_packets_too_late_T_9, UInt<5>(0h10)) node _write_packets_packet_bytes_written_per_beat_1_T_10 = or(write_packets_too_early_9, write_packets_too_late_9) node _write_packets_packet_bytes_written_per_beat_1_T_11 = add(write_packets_left_shift_9, write_packets_right_shift_9) node _write_packets_packet_bytes_written_per_beat_1_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_1_T_11) node _write_packets_packet_bytes_written_per_beat_1_T_13 = tail(_write_packets_packet_bytes_written_per_beat_1_T_12, 1) node _write_packets_packet_bytes_written_per_beat_1_T_14 = mux(_write_packets_packet_bytes_written_per_beat_1_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_1_T_13) connect write_packets_2.bytes_written_per_beat[1], _write_packets_packet_bytes_written_per_beat_1_T_14 node _write_packets_left_shift_T_50 = geq(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_51 = lt(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_52 = and(_write_packets_left_shift_T_50, _write_packets_left_shift_T_51) node _write_packets_left_shift_T_53 = sub(write_packets_vaddr_offset_2, UInt<6>(0h20)) node _write_packets_left_shift_T_54 = tail(_write_packets_left_shift_T_53, 1) node write_packets_left_shift_10 = mux(_write_packets_left_shift_T_52, _write_packets_left_shift_T_54, UInt<1>(0h0)) node _write_packets_right_shift_T_80 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_81 = geq(_write_packets_right_shift_T_80, UInt<6>(0h20)) node _write_packets_right_shift_T_82 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_83 = lt(_write_packets_right_shift_T_82, UInt<6>(0h30)) node _write_packets_right_shift_T_84 = and(_write_packets_right_shift_T_81, _write_packets_right_shift_T_83) node _write_packets_right_shift_T_85 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_86 = sub(UInt<6>(0h30), _write_packets_right_shift_T_85) node _write_packets_right_shift_T_87 = tail(_write_packets_right_shift_T_86, 1) node write_packets_right_shift_10 = mux(_write_packets_right_shift_T_84, _write_packets_right_shift_T_87, UInt<1>(0h0)) node write_packets_too_early_10 = geq(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_too_late_T_10 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_10 = leq(_write_packets_too_late_T_10, UInt<6>(0h20)) node _write_packets_packet_bytes_written_per_beat_2_T_10 = or(write_packets_too_early_10, write_packets_too_late_10) node _write_packets_packet_bytes_written_per_beat_2_T_11 = add(write_packets_left_shift_10, write_packets_right_shift_10) node _write_packets_packet_bytes_written_per_beat_2_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_2_T_11) node _write_packets_packet_bytes_written_per_beat_2_T_13 = tail(_write_packets_packet_bytes_written_per_beat_2_T_12, 1) node _write_packets_packet_bytes_written_per_beat_2_T_14 = mux(_write_packets_packet_bytes_written_per_beat_2_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_2_T_13) connect write_packets_2.bytes_written_per_beat[2], _write_packets_packet_bytes_written_per_beat_2_T_14 node _write_packets_left_shift_T_55 = geq(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_56 = lt(write_packets_vaddr_offset_2, UInt<7>(0h40)) node _write_packets_left_shift_T_57 = and(_write_packets_left_shift_T_55, _write_packets_left_shift_T_56) node _write_packets_left_shift_T_58 = sub(write_packets_vaddr_offset_2, UInt<6>(0h30)) node _write_packets_left_shift_T_59 = tail(_write_packets_left_shift_T_58, 1) node write_packets_left_shift_11 = mux(_write_packets_left_shift_T_57, _write_packets_left_shift_T_59, UInt<1>(0h0)) node _write_packets_right_shift_T_88 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_89 = geq(_write_packets_right_shift_T_88, UInt<6>(0h30)) node _write_packets_right_shift_T_90 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_91 = lt(_write_packets_right_shift_T_90, UInt<7>(0h40)) node _write_packets_right_shift_T_92 = and(_write_packets_right_shift_T_89, _write_packets_right_shift_T_91) node _write_packets_right_shift_T_93 = add(write_packets_vaddr_offset_2, bytesLeft) node _write_packets_right_shift_T_94 = sub(UInt<7>(0h40), _write_packets_right_shift_T_93) node _write_packets_right_shift_T_95 = tail(_write_packets_right_shift_T_94, 1) node write_packets_right_shift_11 = mux(_write_packets_right_shift_T_92, _write_packets_right_shift_T_95, UInt<1>(0h0)) node write_packets_too_early_11 = geq(write_packets_vaddr_offset_2, UInt<7>(0h40)) node _write_packets_too_late_T_11 = add(write_packets_vaddr_offset_2, bytesLeft) node write_packets_too_late_11 = leq(_write_packets_too_late_T_11, UInt<6>(0h30)) node _write_packets_packet_bytes_written_per_beat_3_T_10 = or(write_packets_too_early_11, write_packets_too_late_11) node _write_packets_packet_bytes_written_per_beat_3_T_11 = add(write_packets_left_shift_11, write_packets_right_shift_11) node _write_packets_packet_bytes_written_per_beat_3_T_12 = sub(UInt<5>(0h10), _write_packets_packet_bytes_written_per_beat_3_T_11) node _write_packets_packet_bytes_written_per_beat_3_T_13 = tail(_write_packets_packet_bytes_written_per_beat_3_T_12, 1) node _write_packets_packet_bytes_written_per_beat_3_T_14 = mux(_write_packets_packet_bytes_written_per_beat_3_T_10, UInt<1>(0h0), _write_packets_packet_bytes_written_per_beat_3_T_13) connect write_packets_2.bytes_written_per_beat[3], _write_packets_packet_bytes_written_per_beat_3_T_14 node _best_write_packet_T = gt(write_packets_1.bytes_written, write_packets_0.bytes_written) node _best_write_packet_T_1 = mux(_best_write_packet_T, write_packets_1, write_packets_0) node _best_write_packet_T_2 = gt(write_packets_2.bytes_written, _best_write_packet_T_1.bytes_written) node best_write_packet = mux(_best_write_packet_T_2, write_packets_2, _best_write_packet_T_1) node _write_packet_T = eq(state, UInt<2>(0h1)) reg write_packet_buf : { size : UInt<7>, lg_size : UInt<3>, mask : UInt<1>[16][4], vaddr : UInt<39>, is_full : UInt<1>, bytes_written : UInt<7>, bytes_written_per_beat : UInt<5>[4]}, clock when _write_packet_T : connect write_packet_buf, best_write_packet node write_packet = mux(_write_packet_T, best_write_packet, write_packet_buf) node _write_beats_T = lt(write_packet.size, UInt<5>(0h10)) node _write_beats_T_1 = div(write_packet.size, UInt<7>(0h10)) node write_beats = mux(_write_beats_T, UInt<1>(0h1), _write_beats_T_1) reg beatsLeft : UInt<6>, clock node _beatsSent_T = eq(state, UInt<2>(0h1)) node _beatsSent_T_1 = sub(write_beats, beatsLeft) node _beatsSent_T_2 = tail(_beatsSent_T_1, 1) node beatsSent = mux(_beatsSent_T, UInt<1>(0h0), _beatsSent_T_2) node _write_mask_T = bits(beatsSent, 1, 0) node _write_shift_T = mux(write_packet.mask[_write_mask_T][14], UInt<4>(0he), UInt<4>(0hf)) node _write_shift_T_1 = mux(write_packet.mask[_write_mask_T][13], UInt<4>(0hd), _write_shift_T) node _write_shift_T_2 = mux(write_packet.mask[_write_mask_T][12], UInt<4>(0hc), _write_shift_T_1) node _write_shift_T_3 = mux(write_packet.mask[_write_mask_T][11], UInt<4>(0hb), _write_shift_T_2) node _write_shift_T_4 = mux(write_packet.mask[_write_mask_T][10], UInt<4>(0ha), _write_shift_T_3) node _write_shift_T_5 = mux(write_packet.mask[_write_mask_T][9], UInt<4>(0h9), _write_shift_T_4) node _write_shift_T_6 = mux(write_packet.mask[_write_mask_T][8], UInt<4>(0h8), _write_shift_T_5) node _write_shift_T_7 = mux(write_packet.mask[_write_mask_T][7], UInt<3>(0h7), _write_shift_T_6) node _write_shift_T_8 = mux(write_packet.mask[_write_mask_T][6], UInt<3>(0h6), _write_shift_T_7) node _write_shift_T_9 = mux(write_packet.mask[_write_mask_T][5], UInt<3>(0h5), _write_shift_T_8) node _write_shift_T_10 = mux(write_packet.mask[_write_mask_T][4], UInt<3>(0h4), _write_shift_T_9) node _write_shift_T_11 = mux(write_packet.mask[_write_mask_T][3], UInt<2>(0h3), _write_shift_T_10) node _write_shift_T_12 = mux(write_packet.mask[_write_mask_T][2], UInt<2>(0h2), _write_shift_T_11) node _write_shift_T_13 = mux(write_packet.mask[_write_mask_T][1], UInt<1>(0h1), _write_shift_T_12) node write_shift = mux(write_packet.mask[_write_mask_T][0], UInt<1>(0h0), _write_shift_T_13) node _bytes_written_this_beat_T = bits(beatsSent, 1, 0) node _putFull_T = eq(state, UInt<2>(0h1)) reg putFull_buf : UInt<4>, clock when _putFull_T : connect putFull_buf, xactId node _putFull_T_1 = mux(_putFull_T, xactId, putFull_buf) node _putFull_T_2 = mul(bytesSent, UInt<4>(0h8)) node _putFull_T_3 = dshr(data, _putFull_T_2) node _putFull_legal_T = leq(UInt<1>(0h0), write_packet.lg_size) node _putFull_legal_T_1 = leq(write_packet.lg_size, UInt<4>(0hc)) node _putFull_legal_T_2 = and(_putFull_legal_T, _putFull_legal_T_1) node _putFull_legal_T_3 = or(UInt<1>(0h0), _putFull_legal_T_2) node _putFull_legal_T_4 = xor(UInt<1>(0h0), UInt<14>(0h3000)) node _putFull_legal_T_5 = cvt(_putFull_legal_T_4) node _putFull_legal_T_6 = and(_putFull_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_7 = asSInt(_putFull_legal_T_6) node _putFull_legal_T_8 = eq(_putFull_legal_T_7, asSInt(UInt<1>(0h0))) node _putFull_legal_T_9 = and(_putFull_legal_T_3, _putFull_legal_T_8) node _putFull_legal_T_10 = leq(UInt<1>(0h0), write_packet.lg_size) node _putFull_legal_T_11 = leq(write_packet.lg_size, UInt<3>(0h6)) node _putFull_legal_T_12 = and(_putFull_legal_T_10, _putFull_legal_T_11) node _putFull_legal_T_13 = or(UInt<1>(0h0), _putFull_legal_T_12) node _putFull_legal_T_14 = xor(UInt<1>(0h0), UInt<1>(0h0)) node _putFull_legal_T_15 = cvt(_putFull_legal_T_14) node _putFull_legal_T_16 = and(_putFull_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _putFull_legal_T_17 = asSInt(_putFull_legal_T_16) node _putFull_legal_T_18 = eq(_putFull_legal_T_17, asSInt(UInt<1>(0h0))) node _putFull_legal_T_19 = xor(UInt<1>(0h0), UInt<21>(0h100000)) node _putFull_legal_T_20 = cvt(_putFull_legal_T_19) node _putFull_legal_T_21 = and(_putFull_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _putFull_legal_T_22 = asSInt(_putFull_legal_T_21) node _putFull_legal_T_23 = eq(_putFull_legal_T_22, asSInt(UInt<1>(0h0))) node _putFull_legal_T_24 = xor(UInt<1>(0h0), UInt<26>(0h2000000)) node _putFull_legal_T_25 = cvt(_putFull_legal_T_24) node _putFull_legal_T_26 = and(_putFull_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_27 = asSInt(_putFull_legal_T_26) node _putFull_legal_T_28 = eq(_putFull_legal_T_27, asSInt(UInt<1>(0h0))) node _putFull_legal_T_29 = xor(UInt<1>(0h0), UInt<26>(0h2010000)) node _putFull_legal_T_30 = cvt(_putFull_legal_T_29) node _putFull_legal_T_31 = and(_putFull_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_32 = asSInt(_putFull_legal_T_31) node _putFull_legal_T_33 = eq(_putFull_legal_T_32, asSInt(UInt<1>(0h0))) node _putFull_legal_T_34 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putFull_legal_T_35 = cvt(_putFull_legal_T_34) node _putFull_legal_T_36 = and(_putFull_legal_T_35, asSInt(UInt<33>(0h98000000))) node _putFull_legal_T_37 = asSInt(_putFull_legal_T_36) node _putFull_legal_T_38 = eq(_putFull_legal_T_37, asSInt(UInt<1>(0h0))) node _putFull_legal_T_39 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putFull_legal_T_40 = cvt(_putFull_legal_T_39) node _putFull_legal_T_41 = and(_putFull_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_42 = asSInt(_putFull_legal_T_41) node _putFull_legal_T_43 = eq(_putFull_legal_T_42, asSInt(UInt<1>(0h0))) node _putFull_legal_T_44 = xor(UInt<1>(0h0), UInt<29>(0h10000000)) node _putFull_legal_T_45 = cvt(_putFull_legal_T_44) node _putFull_legal_T_46 = and(_putFull_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _putFull_legal_T_47 = asSInt(_putFull_legal_T_46) node _putFull_legal_T_48 = eq(_putFull_legal_T_47, asSInt(UInt<1>(0h0))) node _putFull_legal_T_49 = xor(UInt<1>(0h0), UInt<32>(0h80000000)) node _putFull_legal_T_50 = cvt(_putFull_legal_T_49) node _putFull_legal_T_51 = and(_putFull_legal_T_50, asSInt(UInt<33>(0h90000000))) node _putFull_legal_T_52 = asSInt(_putFull_legal_T_51) node _putFull_legal_T_53 = eq(_putFull_legal_T_52, asSInt(UInt<1>(0h0))) node _putFull_legal_T_54 = or(_putFull_legal_T_18, _putFull_legal_T_23) node _putFull_legal_T_55 = or(_putFull_legal_T_54, _putFull_legal_T_28) node _putFull_legal_T_56 = or(_putFull_legal_T_55, _putFull_legal_T_33) node _putFull_legal_T_57 = or(_putFull_legal_T_56, _putFull_legal_T_38) node _putFull_legal_T_58 = or(_putFull_legal_T_57, _putFull_legal_T_43) node _putFull_legal_T_59 = or(_putFull_legal_T_58, _putFull_legal_T_48) node _putFull_legal_T_60 = or(_putFull_legal_T_59, _putFull_legal_T_53) node _putFull_legal_T_61 = and(_putFull_legal_T_13, _putFull_legal_T_60) node _putFull_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _putFull_legal_T_63 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _putFull_legal_T_64 = cvt(_putFull_legal_T_63) node _putFull_legal_T_65 = and(_putFull_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _putFull_legal_T_66 = asSInt(_putFull_legal_T_65) node _putFull_legal_T_67 = eq(_putFull_legal_T_66, asSInt(UInt<1>(0h0))) node _putFull_legal_T_68 = and(_putFull_legal_T_62, _putFull_legal_T_67) node _putFull_legal_T_69 = or(UInt<1>(0h0), _putFull_legal_T_9) node _putFull_legal_T_70 = or(_putFull_legal_T_69, _putFull_legal_T_61) node putFull_legal = or(_putFull_legal_T_70, _putFull_legal_T_68) wire putFull : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect putFull.opcode, UInt<1>(0h0) connect putFull.param, UInt<1>(0h0) connect putFull.size, write_packet.lg_size connect putFull.source, _putFull_T_1 connect putFull.address, UInt<1>(0h0) node _putFull_a_mask_sizeOH_T = or(write_packet.lg_size, UInt<4>(0h0)) node putFull_a_mask_sizeOH_shiftAmount = bits(_putFull_a_mask_sizeOH_T, 1, 0) node _putFull_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), putFull_a_mask_sizeOH_shiftAmount) node _putFull_a_mask_sizeOH_T_2 = bits(_putFull_a_mask_sizeOH_T_1, 3, 0) node putFull_a_mask_sizeOH = or(_putFull_a_mask_sizeOH_T_2, UInt<1>(0h1)) node putFull_a_mask_sub_sub_sub_sub_0_1 = geq(write_packet.lg_size, UInt<3>(0h4)) node putFull_a_mask_sub_sub_sub_size = bits(putFull_a_mask_sizeOH, 3, 3) node putFull_a_mask_sub_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), putFull_a_mask_sub_sub_sub_nbit) node _putFull_a_mask_sub_sub_sub_acc_T = and(putFull_a_mask_sub_sub_sub_size, putFull_a_mask_sub_sub_sub_0_2) node putFull_a_mask_sub_sub_sub_0_1 = or(putFull_a_mask_sub_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_sub_acc_T) node putFull_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node _putFull_a_mask_sub_sub_sub_acc_T_1 = and(putFull_a_mask_sub_sub_sub_size, putFull_a_mask_sub_sub_sub_1_2) node putFull_a_mask_sub_sub_sub_1_1 = or(putFull_a_mask_sub_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_sub_acc_T_1) node putFull_a_mask_sub_sub_size = bits(putFull_a_mask_sizeOH, 2, 2) node putFull_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_sub_0_2 = and(putFull_a_mask_sub_sub_sub_0_2, putFull_a_mask_sub_sub_nbit) node _putFull_a_mask_sub_sub_acc_T = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_0_2) node putFull_a_mask_sub_sub_0_1 = or(putFull_a_mask_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_acc_T) node putFull_a_mask_sub_sub_1_2 = and(putFull_a_mask_sub_sub_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_sub_sub_acc_T_1 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_1_2) node putFull_a_mask_sub_sub_1_1 = or(putFull_a_mask_sub_sub_sub_0_1, _putFull_a_mask_sub_sub_acc_T_1) node putFull_a_mask_sub_sub_2_2 = and(putFull_a_mask_sub_sub_sub_1_2, putFull_a_mask_sub_sub_nbit) node _putFull_a_mask_sub_sub_acc_T_2 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_2_2) node putFull_a_mask_sub_sub_2_1 = or(putFull_a_mask_sub_sub_sub_1_1, _putFull_a_mask_sub_sub_acc_T_2) node putFull_a_mask_sub_sub_3_2 = and(putFull_a_mask_sub_sub_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_sub_sub_acc_T_3 = and(putFull_a_mask_sub_sub_size, putFull_a_mask_sub_sub_3_2) node putFull_a_mask_sub_sub_3_1 = or(putFull_a_mask_sub_sub_sub_1_1, _putFull_a_mask_sub_sub_acc_T_3) node putFull_a_mask_sub_size = bits(putFull_a_mask_sizeOH, 1, 1) node putFull_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_sub_0_2 = and(putFull_a_mask_sub_sub_0_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T = and(putFull_a_mask_sub_size, putFull_a_mask_sub_0_2) node putFull_a_mask_sub_0_1 = or(putFull_a_mask_sub_sub_0_1, _putFull_a_mask_sub_acc_T) node putFull_a_mask_sub_1_2 = and(putFull_a_mask_sub_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_1 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_1_2) node putFull_a_mask_sub_1_1 = or(putFull_a_mask_sub_sub_0_1, _putFull_a_mask_sub_acc_T_1) node putFull_a_mask_sub_2_2 = and(putFull_a_mask_sub_sub_1_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_2 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_2_2) node putFull_a_mask_sub_2_1 = or(putFull_a_mask_sub_sub_1_1, _putFull_a_mask_sub_acc_T_2) node putFull_a_mask_sub_3_2 = and(putFull_a_mask_sub_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_3 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_3_2) node putFull_a_mask_sub_3_1 = or(putFull_a_mask_sub_sub_1_1, _putFull_a_mask_sub_acc_T_3) node putFull_a_mask_sub_4_2 = and(putFull_a_mask_sub_sub_2_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_4 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_4_2) node putFull_a_mask_sub_4_1 = or(putFull_a_mask_sub_sub_2_1, _putFull_a_mask_sub_acc_T_4) node putFull_a_mask_sub_5_2 = and(putFull_a_mask_sub_sub_2_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_5 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_5_2) node putFull_a_mask_sub_5_1 = or(putFull_a_mask_sub_sub_2_1, _putFull_a_mask_sub_acc_T_5) node putFull_a_mask_sub_6_2 = and(putFull_a_mask_sub_sub_3_2, putFull_a_mask_sub_nbit) node _putFull_a_mask_sub_acc_T_6 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_6_2) node putFull_a_mask_sub_6_1 = or(putFull_a_mask_sub_sub_3_1, _putFull_a_mask_sub_acc_T_6) node putFull_a_mask_sub_7_2 = and(putFull_a_mask_sub_sub_3_2, UInt<1>(0h0)) node _putFull_a_mask_sub_acc_T_7 = and(putFull_a_mask_sub_size, putFull_a_mask_sub_7_2) node putFull_a_mask_sub_7_1 = or(putFull_a_mask_sub_sub_3_1, _putFull_a_mask_sub_acc_T_7) node putFull_a_mask_size = bits(putFull_a_mask_sizeOH, 0, 0) node putFull_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0)) node putFull_a_mask_eq = and(putFull_a_mask_sub_0_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T = and(putFull_a_mask_size, putFull_a_mask_eq) node putFull_a_mask_acc = or(putFull_a_mask_sub_0_1, _putFull_a_mask_acc_T) node putFull_a_mask_eq_1 = and(putFull_a_mask_sub_0_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_1 = and(putFull_a_mask_size, putFull_a_mask_eq_1) node putFull_a_mask_acc_1 = or(putFull_a_mask_sub_0_1, _putFull_a_mask_acc_T_1) node putFull_a_mask_eq_2 = and(putFull_a_mask_sub_1_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_2 = and(putFull_a_mask_size, putFull_a_mask_eq_2) node putFull_a_mask_acc_2 = or(putFull_a_mask_sub_1_1, _putFull_a_mask_acc_T_2) node putFull_a_mask_eq_3 = and(putFull_a_mask_sub_1_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_3 = and(putFull_a_mask_size, putFull_a_mask_eq_3) node putFull_a_mask_acc_3 = or(putFull_a_mask_sub_1_1, _putFull_a_mask_acc_T_3) node putFull_a_mask_eq_4 = and(putFull_a_mask_sub_2_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_4 = and(putFull_a_mask_size, putFull_a_mask_eq_4) node putFull_a_mask_acc_4 = or(putFull_a_mask_sub_2_1, _putFull_a_mask_acc_T_4) node putFull_a_mask_eq_5 = and(putFull_a_mask_sub_2_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_5 = and(putFull_a_mask_size, putFull_a_mask_eq_5) node putFull_a_mask_acc_5 = or(putFull_a_mask_sub_2_1, _putFull_a_mask_acc_T_5) node putFull_a_mask_eq_6 = and(putFull_a_mask_sub_3_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_6 = and(putFull_a_mask_size, putFull_a_mask_eq_6) node putFull_a_mask_acc_6 = or(putFull_a_mask_sub_3_1, _putFull_a_mask_acc_T_6) node putFull_a_mask_eq_7 = and(putFull_a_mask_sub_3_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_7 = and(putFull_a_mask_size, putFull_a_mask_eq_7) node putFull_a_mask_acc_7 = or(putFull_a_mask_sub_3_1, _putFull_a_mask_acc_T_7) node putFull_a_mask_eq_8 = and(putFull_a_mask_sub_4_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_8 = and(putFull_a_mask_size, putFull_a_mask_eq_8) node putFull_a_mask_acc_8 = or(putFull_a_mask_sub_4_1, _putFull_a_mask_acc_T_8) node putFull_a_mask_eq_9 = and(putFull_a_mask_sub_4_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_9 = and(putFull_a_mask_size, putFull_a_mask_eq_9) node putFull_a_mask_acc_9 = or(putFull_a_mask_sub_4_1, _putFull_a_mask_acc_T_9) node putFull_a_mask_eq_10 = and(putFull_a_mask_sub_5_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_10 = and(putFull_a_mask_size, putFull_a_mask_eq_10) node putFull_a_mask_acc_10 = or(putFull_a_mask_sub_5_1, _putFull_a_mask_acc_T_10) node putFull_a_mask_eq_11 = and(putFull_a_mask_sub_5_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_11 = and(putFull_a_mask_size, putFull_a_mask_eq_11) node putFull_a_mask_acc_11 = or(putFull_a_mask_sub_5_1, _putFull_a_mask_acc_T_11) node putFull_a_mask_eq_12 = and(putFull_a_mask_sub_6_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_12 = and(putFull_a_mask_size, putFull_a_mask_eq_12) node putFull_a_mask_acc_12 = or(putFull_a_mask_sub_6_1, _putFull_a_mask_acc_T_12) node putFull_a_mask_eq_13 = and(putFull_a_mask_sub_6_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_13 = and(putFull_a_mask_size, putFull_a_mask_eq_13) node putFull_a_mask_acc_13 = or(putFull_a_mask_sub_6_1, _putFull_a_mask_acc_T_13) node putFull_a_mask_eq_14 = and(putFull_a_mask_sub_7_2, putFull_a_mask_nbit) node _putFull_a_mask_acc_T_14 = and(putFull_a_mask_size, putFull_a_mask_eq_14) node putFull_a_mask_acc_14 = or(putFull_a_mask_sub_7_1, _putFull_a_mask_acc_T_14) node putFull_a_mask_eq_15 = and(putFull_a_mask_sub_7_2, UInt<1>(0h0)) node _putFull_a_mask_acc_T_15 = and(putFull_a_mask_size, putFull_a_mask_eq_15) node putFull_a_mask_acc_15 = or(putFull_a_mask_sub_7_1, _putFull_a_mask_acc_T_15) node putFull_a_mask_lo_lo_lo = cat(putFull_a_mask_acc_1, putFull_a_mask_acc) node putFull_a_mask_lo_lo_hi = cat(putFull_a_mask_acc_3, putFull_a_mask_acc_2) node putFull_a_mask_lo_lo = cat(putFull_a_mask_lo_lo_hi, putFull_a_mask_lo_lo_lo) node putFull_a_mask_lo_hi_lo = cat(putFull_a_mask_acc_5, putFull_a_mask_acc_4) node putFull_a_mask_lo_hi_hi = cat(putFull_a_mask_acc_7, putFull_a_mask_acc_6) node putFull_a_mask_lo_hi = cat(putFull_a_mask_lo_hi_hi, putFull_a_mask_lo_hi_lo) node putFull_a_mask_lo = cat(putFull_a_mask_lo_hi, putFull_a_mask_lo_lo) node putFull_a_mask_hi_lo_lo = cat(putFull_a_mask_acc_9, putFull_a_mask_acc_8) node putFull_a_mask_hi_lo_hi = cat(putFull_a_mask_acc_11, putFull_a_mask_acc_10) node putFull_a_mask_hi_lo = cat(putFull_a_mask_hi_lo_hi, putFull_a_mask_hi_lo_lo) node putFull_a_mask_hi_hi_lo = cat(putFull_a_mask_acc_13, putFull_a_mask_acc_12) node putFull_a_mask_hi_hi_hi = cat(putFull_a_mask_acc_15, putFull_a_mask_acc_14) node putFull_a_mask_hi_hi = cat(putFull_a_mask_hi_hi_hi, putFull_a_mask_hi_hi_lo) node putFull_a_mask_hi = cat(putFull_a_mask_hi_hi, putFull_a_mask_hi_lo) node _putFull_a_mask_T = cat(putFull_a_mask_hi, putFull_a_mask_lo) connect putFull.mask, _putFull_a_mask_T connect putFull.data, _putFull_T_3 connect putFull.corrupt, UInt<1>(0h0) node _putPartial_T = eq(state, UInt<2>(0h1)) reg putPartial_buf : UInt<4>, clock when _putPartial_T : connect putPartial_buf, xactId node _putPartial_T_1 = mux(_putPartial_T, xactId, putPartial_buf) node _putPartial_T_2 = mul(bytesSent, UInt<4>(0h8)) node _putPartial_T_3 = dshr(data, _putPartial_T_2) node _putPartial_T_4 = mul(write_shift, UInt<4>(0h8)) node _putPartial_T_5 = dshl(_putPartial_T_3, _putPartial_T_4) node putPartial_lo_lo_lo = cat(write_packet.mask[_write_mask_T][1], write_packet.mask[_write_mask_T][0]) node putPartial_lo_lo_hi = cat(write_packet.mask[_write_mask_T][3], write_packet.mask[_write_mask_T][2]) node putPartial_lo_lo = cat(putPartial_lo_lo_hi, putPartial_lo_lo_lo) node putPartial_lo_hi_lo = cat(write_packet.mask[_write_mask_T][5], write_packet.mask[_write_mask_T][4]) node putPartial_lo_hi_hi = cat(write_packet.mask[_write_mask_T][7], write_packet.mask[_write_mask_T][6]) node putPartial_lo_hi = cat(putPartial_lo_hi_hi, putPartial_lo_hi_lo) node putPartial_lo = cat(putPartial_lo_hi, putPartial_lo_lo) node putPartial_hi_lo_lo = cat(write_packet.mask[_write_mask_T][9], write_packet.mask[_write_mask_T][8]) node putPartial_hi_lo_hi = cat(write_packet.mask[_write_mask_T][11], write_packet.mask[_write_mask_T][10]) node putPartial_hi_lo = cat(putPartial_hi_lo_hi, putPartial_hi_lo_lo) node putPartial_hi_hi_lo = cat(write_packet.mask[_write_mask_T][13], write_packet.mask[_write_mask_T][12]) node putPartial_hi_hi_hi = cat(write_packet.mask[_write_mask_T][15], write_packet.mask[_write_mask_T][14]) node putPartial_hi_hi = cat(putPartial_hi_hi_hi, putPartial_hi_hi_lo) node putPartial_hi = cat(putPartial_hi_hi, putPartial_hi_lo) node _putPartial_T_6 = cat(putPartial_hi, putPartial_lo) node _putPartial_legal_T = leq(UInt<1>(0h0), write_packet.lg_size) node _putPartial_legal_T_1 = leq(write_packet.lg_size, UInt<4>(0hc)) node _putPartial_legal_T_2 = and(_putPartial_legal_T, _putPartial_legal_T_1) node _putPartial_legal_T_3 = or(UInt<1>(0h0), _putPartial_legal_T_2) node _putPartial_legal_T_4 = xor(UInt<1>(0h0), UInt<14>(0h3000)) node _putPartial_legal_T_5 = cvt(_putPartial_legal_T_4) node _putPartial_legal_T_6 = and(_putPartial_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_7 = asSInt(_putPartial_legal_T_6) node _putPartial_legal_T_8 = eq(_putPartial_legal_T_7, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_9 = and(_putPartial_legal_T_3, _putPartial_legal_T_8) node _putPartial_legal_T_10 = leq(UInt<1>(0h0), write_packet.lg_size) node _putPartial_legal_T_11 = leq(write_packet.lg_size, UInt<3>(0h6)) node _putPartial_legal_T_12 = and(_putPartial_legal_T_10, _putPartial_legal_T_11) node _putPartial_legal_T_13 = or(UInt<1>(0h0), _putPartial_legal_T_12) node _putPartial_legal_T_14 = xor(UInt<1>(0h0), UInt<1>(0h0)) node _putPartial_legal_T_15 = cvt(_putPartial_legal_T_14) node _putPartial_legal_T_16 = and(_putPartial_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _putPartial_legal_T_17 = asSInt(_putPartial_legal_T_16) node _putPartial_legal_T_18 = eq(_putPartial_legal_T_17, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_19 = xor(UInt<1>(0h0), UInt<21>(0h100000)) node _putPartial_legal_T_20 = cvt(_putPartial_legal_T_19) node _putPartial_legal_T_21 = and(_putPartial_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _putPartial_legal_T_22 = asSInt(_putPartial_legal_T_21) node _putPartial_legal_T_23 = eq(_putPartial_legal_T_22, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_24 = xor(UInt<1>(0h0), UInt<26>(0h2000000)) node _putPartial_legal_T_25 = cvt(_putPartial_legal_T_24) node _putPartial_legal_T_26 = and(_putPartial_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_27 = asSInt(_putPartial_legal_T_26) node _putPartial_legal_T_28 = eq(_putPartial_legal_T_27, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_29 = xor(UInt<1>(0h0), UInt<26>(0h2010000)) node _putPartial_legal_T_30 = cvt(_putPartial_legal_T_29) node _putPartial_legal_T_31 = and(_putPartial_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_32 = asSInt(_putPartial_legal_T_31) node _putPartial_legal_T_33 = eq(_putPartial_legal_T_32, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_34 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putPartial_legal_T_35 = cvt(_putPartial_legal_T_34) node _putPartial_legal_T_36 = and(_putPartial_legal_T_35, asSInt(UInt<33>(0h98000000))) node _putPartial_legal_T_37 = asSInt(_putPartial_legal_T_36) node _putPartial_legal_T_38 = eq(_putPartial_legal_T_37, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_39 = xor(UInt<1>(0h0), UInt<28>(0h8000000)) node _putPartial_legal_T_40 = cvt(_putPartial_legal_T_39) node _putPartial_legal_T_41 = and(_putPartial_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_42 = asSInt(_putPartial_legal_T_41) node _putPartial_legal_T_43 = eq(_putPartial_legal_T_42, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_44 = xor(UInt<1>(0h0), UInt<29>(0h10000000)) node _putPartial_legal_T_45 = cvt(_putPartial_legal_T_44) node _putPartial_legal_T_46 = and(_putPartial_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _putPartial_legal_T_47 = asSInt(_putPartial_legal_T_46) node _putPartial_legal_T_48 = eq(_putPartial_legal_T_47, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_49 = xor(UInt<1>(0h0), UInt<32>(0h80000000)) node _putPartial_legal_T_50 = cvt(_putPartial_legal_T_49) node _putPartial_legal_T_51 = and(_putPartial_legal_T_50, asSInt(UInt<33>(0h90000000))) node _putPartial_legal_T_52 = asSInt(_putPartial_legal_T_51) node _putPartial_legal_T_53 = eq(_putPartial_legal_T_52, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_54 = or(_putPartial_legal_T_18, _putPartial_legal_T_23) node _putPartial_legal_T_55 = or(_putPartial_legal_T_54, _putPartial_legal_T_28) node _putPartial_legal_T_56 = or(_putPartial_legal_T_55, _putPartial_legal_T_33) node _putPartial_legal_T_57 = or(_putPartial_legal_T_56, _putPartial_legal_T_38) node _putPartial_legal_T_58 = or(_putPartial_legal_T_57, _putPartial_legal_T_43) node _putPartial_legal_T_59 = or(_putPartial_legal_T_58, _putPartial_legal_T_48) node _putPartial_legal_T_60 = or(_putPartial_legal_T_59, _putPartial_legal_T_53) node _putPartial_legal_T_61 = and(_putPartial_legal_T_13, _putPartial_legal_T_60) node _putPartial_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _putPartial_legal_T_63 = xor(UInt<1>(0h0), UInt<17>(0h10000)) node _putPartial_legal_T_64 = cvt(_putPartial_legal_T_63) node _putPartial_legal_T_65 = and(_putPartial_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _putPartial_legal_T_66 = asSInt(_putPartial_legal_T_65) node _putPartial_legal_T_67 = eq(_putPartial_legal_T_66, asSInt(UInt<1>(0h0))) node _putPartial_legal_T_68 = and(_putPartial_legal_T_62, _putPartial_legal_T_67) node _putPartial_legal_T_69 = or(UInt<1>(0h0), _putPartial_legal_T_9) node _putPartial_legal_T_70 = or(_putPartial_legal_T_69, _putPartial_legal_T_61) node putPartial_legal = or(_putPartial_legal_T_70, _putPartial_legal_T_68) wire putPartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect putPartial.opcode, UInt<1>(0h1) connect putPartial.param, UInt<1>(0h0) connect putPartial.size, write_packet.lg_size connect putPartial.source, _putPartial_T_1 connect putPartial.address, UInt<1>(0h0) connect putPartial.mask, _putPartial_T_6 connect putPartial.data, _putPartial_T_5 connect putPartial.corrupt, UInt<1>(0h0) wire untranslated_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} node _xactBusy_fire_T = and(untranslated_a.ready, untranslated_a.valid) node _xactBusy_fire_T_1 = eq(state, UInt<2>(0h1)) node _xactBusy_fire_T_2 = and(_xactBusy_fire_T, _xactBusy_fire_T_1) connect xactBusy_fire, _xactBusy_fire_T_2 node _untranslated_a_valid_T = eq(state, UInt<2>(0h1)) node _untranslated_a_valid_T_1 = eq(state, UInt<2>(0h2)) node _untranslated_a_valid_T_2 = or(_untranslated_a_valid_T, _untranslated_a_valid_T_1) node _untranslated_a_valid_T_3 = andr(xactBusy) node _untranslated_a_valid_T_4 = eq(_untranslated_a_valid_T_3, UInt<1>(0h0)) node _untranslated_a_valid_T_5 = and(_untranslated_a_valid_T_2, _untranslated_a_valid_T_4) connect untranslated_a.valid, _untranslated_a_valid_T_5 node _untranslated_a_bits_tl_a_T = mux(write_packet.is_full, putFull, putPartial) connect untranslated_a.bits.tl_a, _untranslated_a_bits_tl_a_T connect untranslated_a.bits.vaddr, write_packet.vaddr connect untranslated_a.bits.status, req.status wire retry_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { tl_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, vaddr : UInt<39>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} inst shadow_retry_a of Queue1_TLBundleAWithInfo_2 connect shadow_retry_a.clock, clock connect shadow_retry_a.reset, reset connect shadow_retry_a.io.enq.valid, UInt<1>(0h0) invalidate shadow_retry_a.io.enq.bits.status.uie invalidate shadow_retry_a.io.enq.bits.status.sie invalidate shadow_retry_a.io.enq.bits.status.hie invalidate shadow_retry_a.io.enq.bits.status.mie invalidate shadow_retry_a.io.enq.bits.status.upie invalidate shadow_retry_a.io.enq.bits.status.spie invalidate shadow_retry_a.io.enq.bits.status.ube invalidate shadow_retry_a.io.enq.bits.status.mpie invalidate shadow_retry_a.io.enq.bits.status.spp invalidate shadow_retry_a.io.enq.bits.status.vs invalidate shadow_retry_a.io.enq.bits.status.mpp invalidate shadow_retry_a.io.enq.bits.status.fs invalidate shadow_retry_a.io.enq.bits.status.xs invalidate shadow_retry_a.io.enq.bits.status.mprv invalidate shadow_retry_a.io.enq.bits.status.sum invalidate shadow_retry_a.io.enq.bits.status.mxr invalidate shadow_retry_a.io.enq.bits.status.tvm invalidate shadow_retry_a.io.enq.bits.status.tw invalidate shadow_retry_a.io.enq.bits.status.tsr invalidate shadow_retry_a.io.enq.bits.status.zero1 invalidate shadow_retry_a.io.enq.bits.status.sd_rv32 invalidate shadow_retry_a.io.enq.bits.status.uxl invalidate shadow_retry_a.io.enq.bits.status.sxl invalidate shadow_retry_a.io.enq.bits.status.sbe invalidate shadow_retry_a.io.enq.bits.status.mbe invalidate shadow_retry_a.io.enq.bits.status.gva invalidate shadow_retry_a.io.enq.bits.status.mpv invalidate shadow_retry_a.io.enq.bits.status.zero2 invalidate shadow_retry_a.io.enq.bits.status.sd invalidate shadow_retry_a.io.enq.bits.status.v invalidate shadow_retry_a.io.enq.bits.status.prv invalidate shadow_retry_a.io.enq.bits.status.dv invalidate shadow_retry_a.io.enq.bits.status.dprv invalidate shadow_retry_a.io.enq.bits.status.isa invalidate shadow_retry_a.io.enq.bits.status.wfi invalidate shadow_retry_a.io.enq.bits.status.cease invalidate shadow_retry_a.io.enq.bits.status.debug invalidate shadow_retry_a.io.enq.bits.vaddr invalidate shadow_retry_a.io.enq.bits.tl_a.corrupt invalidate shadow_retry_a.io.enq.bits.tl_a.data invalidate shadow_retry_a.io.enq.bits.tl_a.mask invalidate shadow_retry_a.io.enq.bits.tl_a.address invalidate shadow_retry_a.io.enq.bits.tl_a.source invalidate shadow_retry_a.io.enq.bits.tl_a.size invalidate shadow_retry_a.io.enq.bits.tl_a.param invalidate shadow_retry_a.io.enq.bits.tl_a.opcode inst tlb_arb of Arbiter3_TLBundleAWithInfo connect tlb_arb.clock, clock connect tlb_arb.reset, reset connect tlb_arb.io.in[0], retry_a connect tlb_arb.io.in[1], shadow_retry_a.io.deq connect tlb_arb.io.in[2], untranslated_a inst tlb_q of Queue1_TLBundleAWithInfo_3 connect tlb_q.clock, clock connect tlb_q.reset, reset connect tlb_q.io.enq, tlb_arb.io.out node _io_tlb_req_valid_T = and(tlb_q.io.deq.ready, tlb_q.io.deq.valid) connect io.tlb.req.valid, _io_tlb_req_valid_T invalidate io.tlb.req.bits.status.uie invalidate io.tlb.req.bits.status.sie invalidate io.tlb.req.bits.status.hie invalidate io.tlb.req.bits.status.mie invalidate io.tlb.req.bits.status.upie invalidate io.tlb.req.bits.status.spie invalidate io.tlb.req.bits.status.ube invalidate io.tlb.req.bits.status.mpie invalidate io.tlb.req.bits.status.spp invalidate io.tlb.req.bits.status.vs invalidate io.tlb.req.bits.status.mpp invalidate io.tlb.req.bits.status.fs invalidate io.tlb.req.bits.status.xs invalidate io.tlb.req.bits.status.mprv invalidate io.tlb.req.bits.status.sum invalidate io.tlb.req.bits.status.mxr invalidate io.tlb.req.bits.status.tvm invalidate io.tlb.req.bits.status.tw invalidate io.tlb.req.bits.status.tsr invalidate io.tlb.req.bits.status.zero1 invalidate io.tlb.req.bits.status.sd_rv32 invalidate io.tlb.req.bits.status.uxl invalidate io.tlb.req.bits.status.sxl invalidate io.tlb.req.bits.status.sbe invalidate io.tlb.req.bits.status.mbe invalidate io.tlb.req.bits.status.gva invalidate io.tlb.req.bits.status.mpv invalidate io.tlb.req.bits.status.zero2 invalidate io.tlb.req.bits.status.sd invalidate io.tlb.req.bits.status.v invalidate io.tlb.req.bits.status.prv invalidate io.tlb.req.bits.status.dv invalidate io.tlb.req.bits.status.dprv invalidate io.tlb.req.bits.status.isa invalidate io.tlb.req.bits.status.wfi invalidate io.tlb.req.bits.status.cease invalidate io.tlb.req.bits.status.debug invalidate io.tlb.req.bits.tlb_req.v invalidate io.tlb.req.bits.tlb_req.prv invalidate io.tlb.req.bits.tlb_req.cmd invalidate io.tlb.req.bits.tlb_req.size invalidate io.tlb.req.bits.tlb_req.passthrough invalidate io.tlb.req.bits.tlb_req.vaddr connect io.tlb.req.bits.tlb_req.vaddr, tlb_q.io.deq.bits.vaddr connect io.tlb.req.bits.tlb_req.passthrough, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.size, UInt<1>(0h0) connect io.tlb.req.bits.tlb_req.cmd, UInt<1>(0h1) connect io.tlb.req.bits.status, tlb_q.io.deq.bits.status inst translate_q of Queue1_TLBundleAWithInfo_4 connect translate_q.clock, clock connect translate_q.reset, reset connect translate_q.io.enq, tlb_q.io.deq when retry_a.valid : connect translate_q.io.enq.valid, UInt<1>(0h0) connect shadow_retry_a.io.enq.valid, tlb_q.io.deq.valid connect shadow_retry_a.io.enq.bits.status.uie, tlb_q.io.deq.bits.status.uie connect shadow_retry_a.io.enq.bits.status.sie, tlb_q.io.deq.bits.status.sie connect shadow_retry_a.io.enq.bits.status.hie, tlb_q.io.deq.bits.status.hie connect shadow_retry_a.io.enq.bits.status.mie, tlb_q.io.deq.bits.status.mie connect shadow_retry_a.io.enq.bits.status.upie, tlb_q.io.deq.bits.status.upie connect shadow_retry_a.io.enq.bits.status.spie, tlb_q.io.deq.bits.status.spie connect shadow_retry_a.io.enq.bits.status.ube, tlb_q.io.deq.bits.status.ube connect shadow_retry_a.io.enq.bits.status.mpie, tlb_q.io.deq.bits.status.mpie connect shadow_retry_a.io.enq.bits.status.spp, tlb_q.io.deq.bits.status.spp connect shadow_retry_a.io.enq.bits.status.vs, tlb_q.io.deq.bits.status.vs connect shadow_retry_a.io.enq.bits.status.mpp, tlb_q.io.deq.bits.status.mpp connect shadow_retry_a.io.enq.bits.status.fs, tlb_q.io.deq.bits.status.fs connect shadow_retry_a.io.enq.bits.status.xs, tlb_q.io.deq.bits.status.xs connect shadow_retry_a.io.enq.bits.status.mprv, tlb_q.io.deq.bits.status.mprv connect shadow_retry_a.io.enq.bits.status.sum, tlb_q.io.deq.bits.status.sum connect shadow_retry_a.io.enq.bits.status.mxr, tlb_q.io.deq.bits.status.mxr connect shadow_retry_a.io.enq.bits.status.tvm, tlb_q.io.deq.bits.status.tvm connect shadow_retry_a.io.enq.bits.status.tw, tlb_q.io.deq.bits.status.tw connect shadow_retry_a.io.enq.bits.status.tsr, tlb_q.io.deq.bits.status.tsr connect shadow_retry_a.io.enq.bits.status.zero1, tlb_q.io.deq.bits.status.zero1 connect shadow_retry_a.io.enq.bits.status.sd_rv32, tlb_q.io.deq.bits.status.sd_rv32 connect shadow_retry_a.io.enq.bits.status.uxl, tlb_q.io.deq.bits.status.uxl connect shadow_retry_a.io.enq.bits.status.sxl, tlb_q.io.deq.bits.status.sxl connect shadow_retry_a.io.enq.bits.status.sbe, tlb_q.io.deq.bits.status.sbe connect shadow_retry_a.io.enq.bits.status.mbe, tlb_q.io.deq.bits.status.mbe connect shadow_retry_a.io.enq.bits.status.gva, tlb_q.io.deq.bits.status.gva connect shadow_retry_a.io.enq.bits.status.mpv, tlb_q.io.deq.bits.status.mpv connect shadow_retry_a.io.enq.bits.status.zero2, tlb_q.io.deq.bits.status.zero2 connect shadow_retry_a.io.enq.bits.status.sd, tlb_q.io.deq.bits.status.sd connect shadow_retry_a.io.enq.bits.status.v, tlb_q.io.deq.bits.status.v connect shadow_retry_a.io.enq.bits.status.prv, tlb_q.io.deq.bits.status.prv connect shadow_retry_a.io.enq.bits.status.dv, tlb_q.io.deq.bits.status.dv connect shadow_retry_a.io.enq.bits.status.dprv, tlb_q.io.deq.bits.status.dprv connect shadow_retry_a.io.enq.bits.status.isa, tlb_q.io.deq.bits.status.isa connect shadow_retry_a.io.enq.bits.status.wfi, tlb_q.io.deq.bits.status.wfi connect shadow_retry_a.io.enq.bits.status.cease, tlb_q.io.deq.bits.status.cease connect shadow_retry_a.io.enq.bits.status.debug, tlb_q.io.deq.bits.status.debug connect shadow_retry_a.io.enq.bits.vaddr, tlb_q.io.deq.bits.vaddr connect shadow_retry_a.io.enq.bits.tl_a.corrupt, tlb_q.io.deq.bits.tl_a.corrupt connect shadow_retry_a.io.enq.bits.tl_a.data, tlb_q.io.deq.bits.tl_a.data connect shadow_retry_a.io.enq.bits.tl_a.mask, tlb_q.io.deq.bits.tl_a.mask connect shadow_retry_a.io.enq.bits.tl_a.address, tlb_q.io.deq.bits.tl_a.address connect shadow_retry_a.io.enq.bits.tl_a.source, tlb_q.io.deq.bits.tl_a.source connect shadow_retry_a.io.enq.bits.tl_a.size, tlb_q.io.deq.bits.tl_a.size connect shadow_retry_a.io.enq.bits.tl_a.param, tlb_q.io.deq.bits.tl_a.param connect shadow_retry_a.io.enq.bits.tl_a.opcode, tlb_q.io.deq.bits.tl_a.opcode node _translate_q_io_deq_ready_T = or(nodeOut.a.ready, io.tlb.resp.miss) connect translate_q.io.deq.ready, _translate_q_io_deq_ready_T node _retry_a_valid_T = and(translate_q.io.deq.valid, io.tlb.resp.miss) connect retry_a.valid, _retry_a_valid_T connect retry_a.bits, translate_q.io.deq.bits node _T = eq(retry_a.ready, UInt<1>(0h0)) node _T_1 = and(retry_a.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at DMA.scala:545 assert(!(retry_a.valid && !retry_a.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _nodeOut_a_valid_T = eq(io.tlb.resp.miss, UInt<1>(0h0)) node _nodeOut_a_valid_T_1 = and(translate_q.io.deq.valid, _nodeOut_a_valid_T) connect nodeOut.a.valid, _nodeOut_a_valid_T_1 connect nodeOut.a.bits, translate_q.io.deq.bits.tl_a reg nodeOut_a_bits_address_REG : UInt<1>, clock connect nodeOut_a_bits_address_REG, io.tlb.req.valid reg nodeOut_a_bits_address_buf : UInt<32>, clock when nodeOut_a_bits_address_REG : connect nodeOut_a_bits_address_buf, io.tlb.resp.paddr node _nodeOut_a_bits_address_T = mux(nodeOut_a_bits_address_REG, io.tlb.resp.paddr, nodeOut_a_bits_address_buf) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeOut_d_ready_T = orr(xactBusy) connect nodeOut.d.ready, _nodeOut_d_ready_T node _T_6 = and(untranslated_a.ready, untranslated_a.valid) when _T_6 : node _T_7 = eq(state, UInt<2>(0h1)) when _T_7 : node _beatsLeft_T = sub(write_beats, UInt<1>(0h1)) node _beatsLeft_T_1 = tail(_beatsLeft_T, 1) connect beatsLeft, _beatsLeft_T_1 node _next_vaddr_T = add(req.vaddr, write_packet.bytes_written) node next_vaddr = tail(_next_vaddr_T, 1) connect req.vaddr, next_vaddr node _bytesSent_T = add(bytesSent, write_packet.bytes_written_per_beat[_bytes_written_this_beat_T]) node _bytesSent_T_1 = tail(_bytesSent_T, 1) connect bytesSent, _bytesSent_T_1 node _T_8 = eq(write_beats, UInt<1>(0h1)) when _T_8 : node _T_9 = geq(write_packet.bytes_written_per_beat[_bytes_written_this_beat_T], bytesLeft) when _T_9 : connect state_machine_ready_for_req, UInt<1>(0h1) connect state, UInt<2>(0h0) else : connect state, UInt<2>(0h2) else : node _T_10 = eq(state, UInt<2>(0h2)) when _T_10 : node _beatsLeft_T_2 = sub(beatsLeft, UInt<1>(0h1)) node _beatsLeft_T_3 = tail(_beatsLeft_T_2, 1) connect beatsLeft, _beatsLeft_T_3 node _bytesSent_T_2 = add(bytesSent, write_packet.bytes_written_per_beat[_bytes_written_this_beat_T]) node _bytesSent_T_3 = tail(_bytesSent_T_2, 1) connect bytesSent, _bytesSent_T_3 node _T_11 = gt(beatsLeft, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at DMA.scala:575 assert(beatsLeft > 0.U)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(beatsLeft, UInt<1>(0h1)) when _T_15 : node _T_16 = geq(write_packet.bytes_written_per_beat[_bytes_written_this_beat_T], bytesLeft) when _T_16 : connect state_machine_ready_for_req, UInt<1>(0h1) connect state, UInt<2>(0h0) else : connect state, UInt<2>(0h1) node _T_17 = and(io.req.ready, io.req.valid) when _T_17 : wire pooled_v1 : SInt<8>[64] wire _pooled_v1_WIRE : UInt<512> connect _pooled_v1_WIRE, io.req.bits.data node _pooled_v1_T = bits(_pooled_v1_WIRE, 7, 0) node _pooled_v1_T_1 = asSInt(_pooled_v1_T) connect pooled_v1[0], _pooled_v1_T_1 node _pooled_v1_T_2 = bits(_pooled_v1_WIRE, 15, 8) node _pooled_v1_T_3 = asSInt(_pooled_v1_T_2) connect pooled_v1[1], _pooled_v1_T_3 node _pooled_v1_T_4 = bits(_pooled_v1_WIRE, 23, 16) node _pooled_v1_T_5 = asSInt(_pooled_v1_T_4) connect pooled_v1[2], _pooled_v1_T_5 node _pooled_v1_T_6 = bits(_pooled_v1_WIRE, 31, 24) node _pooled_v1_T_7 = asSInt(_pooled_v1_T_6) connect pooled_v1[3], _pooled_v1_T_7 node _pooled_v1_T_8 = bits(_pooled_v1_WIRE, 39, 32) node _pooled_v1_T_9 = asSInt(_pooled_v1_T_8) connect pooled_v1[4], _pooled_v1_T_9 node _pooled_v1_T_10 = bits(_pooled_v1_WIRE, 47, 40) node _pooled_v1_T_11 = asSInt(_pooled_v1_T_10) connect pooled_v1[5], _pooled_v1_T_11 node _pooled_v1_T_12 = bits(_pooled_v1_WIRE, 55, 48) node _pooled_v1_T_13 = asSInt(_pooled_v1_T_12) connect pooled_v1[6], _pooled_v1_T_13 node _pooled_v1_T_14 = bits(_pooled_v1_WIRE, 63, 56) node _pooled_v1_T_15 = asSInt(_pooled_v1_T_14) connect pooled_v1[7], _pooled_v1_T_15 node _pooled_v1_T_16 = bits(_pooled_v1_WIRE, 71, 64) node _pooled_v1_T_17 = asSInt(_pooled_v1_T_16) connect pooled_v1[8], _pooled_v1_T_17 node _pooled_v1_T_18 = bits(_pooled_v1_WIRE, 79, 72) node _pooled_v1_T_19 = asSInt(_pooled_v1_T_18) connect pooled_v1[9], _pooled_v1_T_19 node _pooled_v1_T_20 = bits(_pooled_v1_WIRE, 87, 80) node _pooled_v1_T_21 = asSInt(_pooled_v1_T_20) connect pooled_v1[10], _pooled_v1_T_21 node _pooled_v1_T_22 = bits(_pooled_v1_WIRE, 95, 88) node _pooled_v1_T_23 = asSInt(_pooled_v1_T_22) connect pooled_v1[11], _pooled_v1_T_23 node _pooled_v1_T_24 = bits(_pooled_v1_WIRE, 103, 96) node _pooled_v1_T_25 = asSInt(_pooled_v1_T_24) connect pooled_v1[12], _pooled_v1_T_25 node _pooled_v1_T_26 = bits(_pooled_v1_WIRE, 111, 104) node _pooled_v1_T_27 = asSInt(_pooled_v1_T_26) connect pooled_v1[13], _pooled_v1_T_27 node _pooled_v1_T_28 = bits(_pooled_v1_WIRE, 119, 112) node _pooled_v1_T_29 = asSInt(_pooled_v1_T_28) connect pooled_v1[14], _pooled_v1_T_29 node _pooled_v1_T_30 = bits(_pooled_v1_WIRE, 127, 120) node _pooled_v1_T_31 = asSInt(_pooled_v1_T_30) connect pooled_v1[15], _pooled_v1_T_31 node _pooled_v1_T_32 = bits(_pooled_v1_WIRE, 135, 128) node _pooled_v1_T_33 = asSInt(_pooled_v1_T_32) connect pooled_v1[16], _pooled_v1_T_33 node _pooled_v1_T_34 = bits(_pooled_v1_WIRE, 143, 136) node _pooled_v1_T_35 = asSInt(_pooled_v1_T_34) connect pooled_v1[17], _pooled_v1_T_35 node _pooled_v1_T_36 = bits(_pooled_v1_WIRE, 151, 144) node _pooled_v1_T_37 = asSInt(_pooled_v1_T_36) connect pooled_v1[18], _pooled_v1_T_37 node _pooled_v1_T_38 = bits(_pooled_v1_WIRE, 159, 152) node _pooled_v1_T_39 = asSInt(_pooled_v1_T_38) connect pooled_v1[19], _pooled_v1_T_39 node _pooled_v1_T_40 = bits(_pooled_v1_WIRE, 167, 160) node _pooled_v1_T_41 = asSInt(_pooled_v1_T_40) connect pooled_v1[20], _pooled_v1_T_41 node _pooled_v1_T_42 = bits(_pooled_v1_WIRE, 175, 168) node _pooled_v1_T_43 = asSInt(_pooled_v1_T_42) connect pooled_v1[21], _pooled_v1_T_43 node _pooled_v1_T_44 = bits(_pooled_v1_WIRE, 183, 176) node _pooled_v1_T_45 = asSInt(_pooled_v1_T_44) connect pooled_v1[22], _pooled_v1_T_45 node _pooled_v1_T_46 = bits(_pooled_v1_WIRE, 191, 184) node _pooled_v1_T_47 = asSInt(_pooled_v1_T_46) connect pooled_v1[23], _pooled_v1_T_47 node _pooled_v1_T_48 = bits(_pooled_v1_WIRE, 199, 192) node _pooled_v1_T_49 = asSInt(_pooled_v1_T_48) connect pooled_v1[24], _pooled_v1_T_49 node _pooled_v1_T_50 = bits(_pooled_v1_WIRE, 207, 200) node _pooled_v1_T_51 = asSInt(_pooled_v1_T_50) connect pooled_v1[25], _pooled_v1_T_51 node _pooled_v1_T_52 = bits(_pooled_v1_WIRE, 215, 208) node _pooled_v1_T_53 = asSInt(_pooled_v1_T_52) connect pooled_v1[26], _pooled_v1_T_53 node _pooled_v1_T_54 = bits(_pooled_v1_WIRE, 223, 216) node _pooled_v1_T_55 = asSInt(_pooled_v1_T_54) connect pooled_v1[27], _pooled_v1_T_55 node _pooled_v1_T_56 = bits(_pooled_v1_WIRE, 231, 224) node _pooled_v1_T_57 = asSInt(_pooled_v1_T_56) connect pooled_v1[28], _pooled_v1_T_57 node _pooled_v1_T_58 = bits(_pooled_v1_WIRE, 239, 232) node _pooled_v1_T_59 = asSInt(_pooled_v1_T_58) connect pooled_v1[29], _pooled_v1_T_59 node _pooled_v1_T_60 = bits(_pooled_v1_WIRE, 247, 240) node _pooled_v1_T_61 = asSInt(_pooled_v1_T_60) connect pooled_v1[30], _pooled_v1_T_61 node _pooled_v1_T_62 = bits(_pooled_v1_WIRE, 255, 248) node _pooled_v1_T_63 = asSInt(_pooled_v1_T_62) connect pooled_v1[31], _pooled_v1_T_63 node _pooled_v1_T_64 = bits(_pooled_v1_WIRE, 263, 256) node _pooled_v1_T_65 = asSInt(_pooled_v1_T_64) connect pooled_v1[32], _pooled_v1_T_65 node _pooled_v1_T_66 = bits(_pooled_v1_WIRE, 271, 264) node _pooled_v1_T_67 = asSInt(_pooled_v1_T_66) connect pooled_v1[33], _pooled_v1_T_67 node _pooled_v1_T_68 = bits(_pooled_v1_WIRE, 279, 272) node _pooled_v1_T_69 = asSInt(_pooled_v1_T_68) connect pooled_v1[34], _pooled_v1_T_69 node _pooled_v1_T_70 = bits(_pooled_v1_WIRE, 287, 280) node _pooled_v1_T_71 = asSInt(_pooled_v1_T_70) connect pooled_v1[35], _pooled_v1_T_71 node _pooled_v1_T_72 = bits(_pooled_v1_WIRE, 295, 288) node _pooled_v1_T_73 = asSInt(_pooled_v1_T_72) connect pooled_v1[36], _pooled_v1_T_73 node _pooled_v1_T_74 = bits(_pooled_v1_WIRE, 303, 296) node _pooled_v1_T_75 = asSInt(_pooled_v1_T_74) connect pooled_v1[37], _pooled_v1_T_75 node _pooled_v1_T_76 = bits(_pooled_v1_WIRE, 311, 304) node _pooled_v1_T_77 = asSInt(_pooled_v1_T_76) connect pooled_v1[38], _pooled_v1_T_77 node _pooled_v1_T_78 = bits(_pooled_v1_WIRE, 319, 312) node _pooled_v1_T_79 = asSInt(_pooled_v1_T_78) connect pooled_v1[39], _pooled_v1_T_79 node _pooled_v1_T_80 = bits(_pooled_v1_WIRE, 327, 320) node _pooled_v1_T_81 = asSInt(_pooled_v1_T_80) connect pooled_v1[40], _pooled_v1_T_81 node _pooled_v1_T_82 = bits(_pooled_v1_WIRE, 335, 328) node _pooled_v1_T_83 = asSInt(_pooled_v1_T_82) connect pooled_v1[41], _pooled_v1_T_83 node _pooled_v1_T_84 = bits(_pooled_v1_WIRE, 343, 336) node _pooled_v1_T_85 = asSInt(_pooled_v1_T_84) connect pooled_v1[42], _pooled_v1_T_85 node _pooled_v1_T_86 = bits(_pooled_v1_WIRE, 351, 344) node _pooled_v1_T_87 = asSInt(_pooled_v1_T_86) connect pooled_v1[43], _pooled_v1_T_87 node _pooled_v1_T_88 = bits(_pooled_v1_WIRE, 359, 352) node _pooled_v1_T_89 = asSInt(_pooled_v1_T_88) connect pooled_v1[44], _pooled_v1_T_89 node _pooled_v1_T_90 = bits(_pooled_v1_WIRE, 367, 360) node _pooled_v1_T_91 = asSInt(_pooled_v1_T_90) connect pooled_v1[45], _pooled_v1_T_91 node _pooled_v1_T_92 = bits(_pooled_v1_WIRE, 375, 368) node _pooled_v1_T_93 = asSInt(_pooled_v1_T_92) connect pooled_v1[46], _pooled_v1_T_93 node _pooled_v1_T_94 = bits(_pooled_v1_WIRE, 383, 376) node _pooled_v1_T_95 = asSInt(_pooled_v1_T_94) connect pooled_v1[47], _pooled_v1_T_95 node _pooled_v1_T_96 = bits(_pooled_v1_WIRE, 391, 384) node _pooled_v1_T_97 = asSInt(_pooled_v1_T_96) connect pooled_v1[48], _pooled_v1_T_97 node _pooled_v1_T_98 = bits(_pooled_v1_WIRE, 399, 392) node _pooled_v1_T_99 = asSInt(_pooled_v1_T_98) connect pooled_v1[49], _pooled_v1_T_99 node _pooled_v1_T_100 = bits(_pooled_v1_WIRE, 407, 400) node _pooled_v1_T_101 = asSInt(_pooled_v1_T_100) connect pooled_v1[50], _pooled_v1_T_101 node _pooled_v1_T_102 = bits(_pooled_v1_WIRE, 415, 408) node _pooled_v1_T_103 = asSInt(_pooled_v1_T_102) connect pooled_v1[51], _pooled_v1_T_103 node _pooled_v1_T_104 = bits(_pooled_v1_WIRE, 423, 416) node _pooled_v1_T_105 = asSInt(_pooled_v1_T_104) connect pooled_v1[52], _pooled_v1_T_105 node _pooled_v1_T_106 = bits(_pooled_v1_WIRE, 431, 424) node _pooled_v1_T_107 = asSInt(_pooled_v1_T_106) connect pooled_v1[53], _pooled_v1_T_107 node _pooled_v1_T_108 = bits(_pooled_v1_WIRE, 439, 432) node _pooled_v1_T_109 = asSInt(_pooled_v1_T_108) connect pooled_v1[54], _pooled_v1_T_109 node _pooled_v1_T_110 = bits(_pooled_v1_WIRE, 447, 440) node _pooled_v1_T_111 = asSInt(_pooled_v1_T_110) connect pooled_v1[55], _pooled_v1_T_111 node _pooled_v1_T_112 = bits(_pooled_v1_WIRE, 455, 448) node _pooled_v1_T_113 = asSInt(_pooled_v1_T_112) connect pooled_v1[56], _pooled_v1_T_113 node _pooled_v1_T_114 = bits(_pooled_v1_WIRE, 463, 456) node _pooled_v1_T_115 = asSInt(_pooled_v1_T_114) connect pooled_v1[57], _pooled_v1_T_115 node _pooled_v1_T_116 = bits(_pooled_v1_WIRE, 471, 464) node _pooled_v1_T_117 = asSInt(_pooled_v1_T_116) connect pooled_v1[58], _pooled_v1_T_117 node _pooled_v1_T_118 = bits(_pooled_v1_WIRE, 479, 472) node _pooled_v1_T_119 = asSInt(_pooled_v1_T_118) connect pooled_v1[59], _pooled_v1_T_119 node _pooled_v1_T_120 = bits(_pooled_v1_WIRE, 487, 480) node _pooled_v1_T_121 = asSInt(_pooled_v1_T_120) connect pooled_v1[60], _pooled_v1_T_121 node _pooled_v1_T_122 = bits(_pooled_v1_WIRE, 495, 488) node _pooled_v1_T_123 = asSInt(_pooled_v1_T_122) connect pooled_v1[61], _pooled_v1_T_123 node _pooled_v1_T_124 = bits(_pooled_v1_WIRE, 503, 496) node _pooled_v1_T_125 = asSInt(_pooled_v1_T_124) connect pooled_v1[62], _pooled_v1_T_125 node _pooled_v1_T_126 = bits(_pooled_v1_WIRE, 511, 504) node _pooled_v1_T_127 = asSInt(_pooled_v1_T_126) connect pooled_v1[63], _pooled_v1_T_127 wire pooled_v2 : SInt<8>[64] wire _pooled_v2_WIRE : UInt<512> connect _pooled_v2_WIRE, data_single_block node _pooled_v2_T = bits(_pooled_v2_WIRE, 7, 0) node _pooled_v2_T_1 = asSInt(_pooled_v2_T) connect pooled_v2[0], _pooled_v2_T_1 node _pooled_v2_T_2 = bits(_pooled_v2_WIRE, 15, 8) node _pooled_v2_T_3 = asSInt(_pooled_v2_T_2) connect pooled_v2[1], _pooled_v2_T_3 node _pooled_v2_T_4 = bits(_pooled_v2_WIRE, 23, 16) node _pooled_v2_T_5 = asSInt(_pooled_v2_T_4) connect pooled_v2[2], _pooled_v2_T_5 node _pooled_v2_T_6 = bits(_pooled_v2_WIRE, 31, 24) node _pooled_v2_T_7 = asSInt(_pooled_v2_T_6) connect pooled_v2[3], _pooled_v2_T_7 node _pooled_v2_T_8 = bits(_pooled_v2_WIRE, 39, 32) node _pooled_v2_T_9 = asSInt(_pooled_v2_T_8) connect pooled_v2[4], _pooled_v2_T_9 node _pooled_v2_T_10 = bits(_pooled_v2_WIRE, 47, 40) node _pooled_v2_T_11 = asSInt(_pooled_v2_T_10) connect pooled_v2[5], _pooled_v2_T_11 node _pooled_v2_T_12 = bits(_pooled_v2_WIRE, 55, 48) node _pooled_v2_T_13 = asSInt(_pooled_v2_T_12) connect pooled_v2[6], _pooled_v2_T_13 node _pooled_v2_T_14 = bits(_pooled_v2_WIRE, 63, 56) node _pooled_v2_T_15 = asSInt(_pooled_v2_T_14) connect pooled_v2[7], _pooled_v2_T_15 node _pooled_v2_T_16 = bits(_pooled_v2_WIRE, 71, 64) node _pooled_v2_T_17 = asSInt(_pooled_v2_T_16) connect pooled_v2[8], _pooled_v2_T_17 node _pooled_v2_T_18 = bits(_pooled_v2_WIRE, 79, 72) node _pooled_v2_T_19 = asSInt(_pooled_v2_T_18) connect pooled_v2[9], _pooled_v2_T_19 node _pooled_v2_T_20 = bits(_pooled_v2_WIRE, 87, 80) node _pooled_v2_T_21 = asSInt(_pooled_v2_T_20) connect pooled_v2[10], _pooled_v2_T_21 node _pooled_v2_T_22 = bits(_pooled_v2_WIRE, 95, 88) node _pooled_v2_T_23 = asSInt(_pooled_v2_T_22) connect pooled_v2[11], _pooled_v2_T_23 node _pooled_v2_T_24 = bits(_pooled_v2_WIRE, 103, 96) node _pooled_v2_T_25 = asSInt(_pooled_v2_T_24) connect pooled_v2[12], _pooled_v2_T_25 node _pooled_v2_T_26 = bits(_pooled_v2_WIRE, 111, 104) node _pooled_v2_T_27 = asSInt(_pooled_v2_T_26) connect pooled_v2[13], _pooled_v2_T_27 node _pooled_v2_T_28 = bits(_pooled_v2_WIRE, 119, 112) node _pooled_v2_T_29 = asSInt(_pooled_v2_T_28) connect pooled_v2[14], _pooled_v2_T_29 node _pooled_v2_T_30 = bits(_pooled_v2_WIRE, 127, 120) node _pooled_v2_T_31 = asSInt(_pooled_v2_T_30) connect pooled_v2[15], _pooled_v2_T_31 node _pooled_v2_T_32 = bits(_pooled_v2_WIRE, 135, 128) node _pooled_v2_T_33 = asSInt(_pooled_v2_T_32) connect pooled_v2[16], _pooled_v2_T_33 node _pooled_v2_T_34 = bits(_pooled_v2_WIRE, 143, 136) node _pooled_v2_T_35 = asSInt(_pooled_v2_T_34) connect pooled_v2[17], _pooled_v2_T_35 node _pooled_v2_T_36 = bits(_pooled_v2_WIRE, 151, 144) node _pooled_v2_T_37 = asSInt(_pooled_v2_T_36) connect pooled_v2[18], _pooled_v2_T_37 node _pooled_v2_T_38 = bits(_pooled_v2_WIRE, 159, 152) node _pooled_v2_T_39 = asSInt(_pooled_v2_T_38) connect pooled_v2[19], _pooled_v2_T_39 node _pooled_v2_T_40 = bits(_pooled_v2_WIRE, 167, 160) node _pooled_v2_T_41 = asSInt(_pooled_v2_T_40) connect pooled_v2[20], _pooled_v2_T_41 node _pooled_v2_T_42 = bits(_pooled_v2_WIRE, 175, 168) node _pooled_v2_T_43 = asSInt(_pooled_v2_T_42) connect pooled_v2[21], _pooled_v2_T_43 node _pooled_v2_T_44 = bits(_pooled_v2_WIRE, 183, 176) node _pooled_v2_T_45 = asSInt(_pooled_v2_T_44) connect pooled_v2[22], _pooled_v2_T_45 node _pooled_v2_T_46 = bits(_pooled_v2_WIRE, 191, 184) node _pooled_v2_T_47 = asSInt(_pooled_v2_T_46) connect pooled_v2[23], _pooled_v2_T_47 node _pooled_v2_T_48 = bits(_pooled_v2_WIRE, 199, 192) node _pooled_v2_T_49 = asSInt(_pooled_v2_T_48) connect pooled_v2[24], _pooled_v2_T_49 node _pooled_v2_T_50 = bits(_pooled_v2_WIRE, 207, 200) node _pooled_v2_T_51 = asSInt(_pooled_v2_T_50) connect pooled_v2[25], _pooled_v2_T_51 node _pooled_v2_T_52 = bits(_pooled_v2_WIRE, 215, 208) node _pooled_v2_T_53 = asSInt(_pooled_v2_T_52) connect pooled_v2[26], _pooled_v2_T_53 node _pooled_v2_T_54 = bits(_pooled_v2_WIRE, 223, 216) node _pooled_v2_T_55 = asSInt(_pooled_v2_T_54) connect pooled_v2[27], _pooled_v2_T_55 node _pooled_v2_T_56 = bits(_pooled_v2_WIRE, 231, 224) node _pooled_v2_T_57 = asSInt(_pooled_v2_T_56) connect pooled_v2[28], _pooled_v2_T_57 node _pooled_v2_T_58 = bits(_pooled_v2_WIRE, 239, 232) node _pooled_v2_T_59 = asSInt(_pooled_v2_T_58) connect pooled_v2[29], _pooled_v2_T_59 node _pooled_v2_T_60 = bits(_pooled_v2_WIRE, 247, 240) node _pooled_v2_T_61 = asSInt(_pooled_v2_T_60) connect pooled_v2[30], _pooled_v2_T_61 node _pooled_v2_T_62 = bits(_pooled_v2_WIRE, 255, 248) node _pooled_v2_T_63 = asSInt(_pooled_v2_T_62) connect pooled_v2[31], _pooled_v2_T_63 node _pooled_v2_T_64 = bits(_pooled_v2_WIRE, 263, 256) node _pooled_v2_T_65 = asSInt(_pooled_v2_T_64) connect pooled_v2[32], _pooled_v2_T_65 node _pooled_v2_T_66 = bits(_pooled_v2_WIRE, 271, 264) node _pooled_v2_T_67 = asSInt(_pooled_v2_T_66) connect pooled_v2[33], _pooled_v2_T_67 node _pooled_v2_T_68 = bits(_pooled_v2_WIRE, 279, 272) node _pooled_v2_T_69 = asSInt(_pooled_v2_T_68) connect pooled_v2[34], _pooled_v2_T_69 node _pooled_v2_T_70 = bits(_pooled_v2_WIRE, 287, 280) node _pooled_v2_T_71 = asSInt(_pooled_v2_T_70) connect pooled_v2[35], _pooled_v2_T_71 node _pooled_v2_T_72 = bits(_pooled_v2_WIRE, 295, 288) node _pooled_v2_T_73 = asSInt(_pooled_v2_T_72) connect pooled_v2[36], _pooled_v2_T_73 node _pooled_v2_T_74 = bits(_pooled_v2_WIRE, 303, 296) node _pooled_v2_T_75 = asSInt(_pooled_v2_T_74) connect pooled_v2[37], _pooled_v2_T_75 node _pooled_v2_T_76 = bits(_pooled_v2_WIRE, 311, 304) node _pooled_v2_T_77 = asSInt(_pooled_v2_T_76) connect pooled_v2[38], _pooled_v2_T_77 node _pooled_v2_T_78 = bits(_pooled_v2_WIRE, 319, 312) node _pooled_v2_T_79 = asSInt(_pooled_v2_T_78) connect pooled_v2[39], _pooled_v2_T_79 node _pooled_v2_T_80 = bits(_pooled_v2_WIRE, 327, 320) node _pooled_v2_T_81 = asSInt(_pooled_v2_T_80) connect pooled_v2[40], _pooled_v2_T_81 node _pooled_v2_T_82 = bits(_pooled_v2_WIRE, 335, 328) node _pooled_v2_T_83 = asSInt(_pooled_v2_T_82) connect pooled_v2[41], _pooled_v2_T_83 node _pooled_v2_T_84 = bits(_pooled_v2_WIRE, 343, 336) node _pooled_v2_T_85 = asSInt(_pooled_v2_T_84) connect pooled_v2[42], _pooled_v2_T_85 node _pooled_v2_T_86 = bits(_pooled_v2_WIRE, 351, 344) node _pooled_v2_T_87 = asSInt(_pooled_v2_T_86) connect pooled_v2[43], _pooled_v2_T_87 node _pooled_v2_T_88 = bits(_pooled_v2_WIRE, 359, 352) node _pooled_v2_T_89 = asSInt(_pooled_v2_T_88) connect pooled_v2[44], _pooled_v2_T_89 node _pooled_v2_T_90 = bits(_pooled_v2_WIRE, 367, 360) node _pooled_v2_T_91 = asSInt(_pooled_v2_T_90) connect pooled_v2[45], _pooled_v2_T_91 node _pooled_v2_T_92 = bits(_pooled_v2_WIRE, 375, 368) node _pooled_v2_T_93 = asSInt(_pooled_v2_T_92) connect pooled_v2[46], _pooled_v2_T_93 node _pooled_v2_T_94 = bits(_pooled_v2_WIRE, 383, 376) node _pooled_v2_T_95 = asSInt(_pooled_v2_T_94) connect pooled_v2[47], _pooled_v2_T_95 node _pooled_v2_T_96 = bits(_pooled_v2_WIRE, 391, 384) node _pooled_v2_T_97 = asSInt(_pooled_v2_T_96) connect pooled_v2[48], _pooled_v2_T_97 node _pooled_v2_T_98 = bits(_pooled_v2_WIRE, 399, 392) node _pooled_v2_T_99 = asSInt(_pooled_v2_T_98) connect pooled_v2[49], _pooled_v2_T_99 node _pooled_v2_T_100 = bits(_pooled_v2_WIRE, 407, 400) node _pooled_v2_T_101 = asSInt(_pooled_v2_T_100) connect pooled_v2[50], _pooled_v2_T_101 node _pooled_v2_T_102 = bits(_pooled_v2_WIRE, 415, 408) node _pooled_v2_T_103 = asSInt(_pooled_v2_T_102) connect pooled_v2[51], _pooled_v2_T_103 node _pooled_v2_T_104 = bits(_pooled_v2_WIRE, 423, 416) node _pooled_v2_T_105 = asSInt(_pooled_v2_T_104) connect pooled_v2[52], _pooled_v2_T_105 node _pooled_v2_T_106 = bits(_pooled_v2_WIRE, 431, 424) node _pooled_v2_T_107 = asSInt(_pooled_v2_T_106) connect pooled_v2[53], _pooled_v2_T_107 node _pooled_v2_T_108 = bits(_pooled_v2_WIRE, 439, 432) node _pooled_v2_T_109 = asSInt(_pooled_v2_T_108) connect pooled_v2[54], _pooled_v2_T_109 node _pooled_v2_T_110 = bits(_pooled_v2_WIRE, 447, 440) node _pooled_v2_T_111 = asSInt(_pooled_v2_T_110) connect pooled_v2[55], _pooled_v2_T_111 node _pooled_v2_T_112 = bits(_pooled_v2_WIRE, 455, 448) node _pooled_v2_T_113 = asSInt(_pooled_v2_T_112) connect pooled_v2[56], _pooled_v2_T_113 node _pooled_v2_T_114 = bits(_pooled_v2_WIRE, 463, 456) node _pooled_v2_T_115 = asSInt(_pooled_v2_T_114) connect pooled_v2[57], _pooled_v2_T_115 node _pooled_v2_T_116 = bits(_pooled_v2_WIRE, 471, 464) node _pooled_v2_T_117 = asSInt(_pooled_v2_T_116) connect pooled_v2[58], _pooled_v2_T_117 node _pooled_v2_T_118 = bits(_pooled_v2_WIRE, 479, 472) node _pooled_v2_T_119 = asSInt(_pooled_v2_T_118) connect pooled_v2[59], _pooled_v2_T_119 node _pooled_v2_T_120 = bits(_pooled_v2_WIRE, 487, 480) node _pooled_v2_T_121 = asSInt(_pooled_v2_T_120) connect pooled_v2[60], _pooled_v2_T_121 node _pooled_v2_T_122 = bits(_pooled_v2_WIRE, 495, 488) node _pooled_v2_T_123 = asSInt(_pooled_v2_T_122) connect pooled_v2[61], _pooled_v2_T_123 node _pooled_v2_T_124 = bits(_pooled_v2_WIRE, 503, 496) node _pooled_v2_T_125 = asSInt(_pooled_v2_T_124) connect pooled_v2[62], _pooled_v2_T_125 node _pooled_v2_T_126 = bits(_pooled_v2_WIRE, 511, 504) node _pooled_v2_T_127 = asSInt(_pooled_v2_T_126) connect pooled_v2[63], _pooled_v2_T_127 node _pooled_T = gt(pooled_v1[0], pooled_v2[0]) node _pooled_T_1 = mux(_pooled_T, pooled_v1[0], pooled_v2[0]) node _pooled_T_2 = gt(pooled_v1[1], pooled_v2[1]) node _pooled_T_3 = mux(_pooled_T_2, pooled_v1[1], pooled_v2[1]) node _pooled_T_4 = gt(pooled_v1[2], pooled_v2[2]) node _pooled_T_5 = mux(_pooled_T_4, pooled_v1[2], pooled_v2[2]) node _pooled_T_6 = gt(pooled_v1[3], pooled_v2[3]) node _pooled_T_7 = mux(_pooled_T_6, pooled_v1[3], pooled_v2[3]) node _pooled_T_8 = gt(pooled_v1[4], pooled_v2[4]) node _pooled_T_9 = mux(_pooled_T_8, pooled_v1[4], pooled_v2[4]) node _pooled_T_10 = gt(pooled_v1[5], pooled_v2[5]) node _pooled_T_11 = mux(_pooled_T_10, pooled_v1[5], pooled_v2[5]) node _pooled_T_12 = gt(pooled_v1[6], pooled_v2[6]) node _pooled_T_13 = mux(_pooled_T_12, pooled_v1[6], pooled_v2[6]) node _pooled_T_14 = gt(pooled_v1[7], pooled_v2[7]) node _pooled_T_15 = mux(_pooled_T_14, pooled_v1[7], pooled_v2[7]) node _pooled_T_16 = gt(pooled_v1[8], pooled_v2[8]) node _pooled_T_17 = mux(_pooled_T_16, pooled_v1[8], pooled_v2[8]) node _pooled_T_18 = gt(pooled_v1[9], pooled_v2[9]) node _pooled_T_19 = mux(_pooled_T_18, pooled_v1[9], pooled_v2[9]) node _pooled_T_20 = gt(pooled_v1[10], pooled_v2[10]) node _pooled_T_21 = mux(_pooled_T_20, pooled_v1[10], pooled_v2[10]) node _pooled_T_22 = gt(pooled_v1[11], pooled_v2[11]) node _pooled_T_23 = mux(_pooled_T_22, pooled_v1[11], pooled_v2[11]) node _pooled_T_24 = gt(pooled_v1[12], pooled_v2[12]) node _pooled_T_25 = mux(_pooled_T_24, pooled_v1[12], pooled_v2[12]) node _pooled_T_26 = gt(pooled_v1[13], pooled_v2[13]) node _pooled_T_27 = mux(_pooled_T_26, pooled_v1[13], pooled_v2[13]) node _pooled_T_28 = gt(pooled_v1[14], pooled_v2[14]) node _pooled_T_29 = mux(_pooled_T_28, pooled_v1[14], pooled_v2[14]) node _pooled_T_30 = gt(pooled_v1[15], pooled_v2[15]) node _pooled_T_31 = mux(_pooled_T_30, pooled_v1[15], pooled_v2[15]) wire _pooled_WIRE : SInt<8>[64] connect _pooled_WIRE[0], _pooled_T_1 connect _pooled_WIRE[1], _pooled_T_3 connect _pooled_WIRE[2], _pooled_T_5 connect _pooled_WIRE[3], _pooled_T_7 connect _pooled_WIRE[4], _pooled_T_9 connect _pooled_WIRE[5], _pooled_T_11 connect _pooled_WIRE[6], _pooled_T_13 connect _pooled_WIRE[7], _pooled_T_15 connect _pooled_WIRE[8], _pooled_T_17 connect _pooled_WIRE[9], _pooled_T_19 connect _pooled_WIRE[10], _pooled_T_21 connect _pooled_WIRE[11], _pooled_T_23 connect _pooled_WIRE[12], _pooled_T_25 connect _pooled_WIRE[13], _pooled_T_27 connect _pooled_WIRE[14], _pooled_T_29 connect _pooled_WIRE[15], _pooled_T_31 connect _pooled_WIRE[16], pooled_v2[16] connect _pooled_WIRE[17], pooled_v2[17] connect _pooled_WIRE[18], pooled_v2[18] connect _pooled_WIRE[19], pooled_v2[19] connect _pooled_WIRE[20], pooled_v2[20] connect _pooled_WIRE[21], pooled_v2[21] connect _pooled_WIRE[22], pooled_v2[22] connect _pooled_WIRE[23], pooled_v2[23] connect _pooled_WIRE[24], pooled_v2[24] connect _pooled_WIRE[25], pooled_v2[25] connect _pooled_WIRE[26], pooled_v2[26] connect _pooled_WIRE[27], pooled_v2[27] connect _pooled_WIRE[28], pooled_v2[28] connect _pooled_WIRE[29], pooled_v2[29] connect _pooled_WIRE[30], pooled_v2[30] connect _pooled_WIRE[31], pooled_v2[31] connect _pooled_WIRE[32], pooled_v2[32] connect _pooled_WIRE[33], pooled_v2[33] connect _pooled_WIRE[34], pooled_v2[34] connect _pooled_WIRE[35], pooled_v2[35] connect _pooled_WIRE[36], pooled_v2[36] connect _pooled_WIRE[37], pooled_v2[37] connect _pooled_WIRE[38], pooled_v2[38] connect _pooled_WIRE[39], pooled_v2[39] connect _pooled_WIRE[40], pooled_v2[40] connect _pooled_WIRE[41], pooled_v2[41] connect _pooled_WIRE[42], pooled_v2[42] connect _pooled_WIRE[43], pooled_v2[43] connect _pooled_WIRE[44], pooled_v2[44] connect _pooled_WIRE[45], pooled_v2[45] connect _pooled_WIRE[46], pooled_v2[46] connect _pooled_WIRE[47], pooled_v2[47] connect _pooled_WIRE[48], pooled_v2[48] connect _pooled_WIRE[49], pooled_v2[49] connect _pooled_WIRE[50], pooled_v2[50] connect _pooled_WIRE[51], pooled_v2[51] connect _pooled_WIRE[52], pooled_v2[52] connect _pooled_WIRE[53], pooled_v2[53] connect _pooled_WIRE[54], pooled_v2[54] connect _pooled_WIRE[55], pooled_v2[55] connect _pooled_WIRE[56], pooled_v2[56] connect _pooled_WIRE[57], pooled_v2[57] connect _pooled_WIRE[58], pooled_v2[58] connect _pooled_WIRE[59], pooled_v2[59] connect _pooled_WIRE[60], pooled_v2[60] connect _pooled_WIRE[61], pooled_v2[61] connect _pooled_WIRE[62], pooled_v2[62] connect _pooled_WIRE[63], pooled_v2[63] node _pooled_T_32 = asUInt(_pooled_WIRE[0]) node _pooled_T_33 = asUInt(_pooled_WIRE[1]) node _pooled_T_34 = asUInt(_pooled_WIRE[2]) node _pooled_T_35 = asUInt(_pooled_WIRE[3]) node _pooled_T_36 = asUInt(_pooled_WIRE[4]) node _pooled_T_37 = asUInt(_pooled_WIRE[5]) node _pooled_T_38 = asUInt(_pooled_WIRE[6]) node _pooled_T_39 = asUInt(_pooled_WIRE[7]) node _pooled_T_40 = asUInt(_pooled_WIRE[8]) node _pooled_T_41 = asUInt(_pooled_WIRE[9]) node _pooled_T_42 = asUInt(_pooled_WIRE[10]) node _pooled_T_43 = asUInt(_pooled_WIRE[11]) node _pooled_T_44 = asUInt(_pooled_WIRE[12]) node _pooled_T_45 = asUInt(_pooled_WIRE[13]) node _pooled_T_46 = asUInt(_pooled_WIRE[14]) node _pooled_T_47 = asUInt(_pooled_WIRE[15]) node _pooled_T_48 = asUInt(_pooled_WIRE[16]) node _pooled_T_49 = asUInt(_pooled_WIRE[17]) node _pooled_T_50 = asUInt(_pooled_WIRE[18]) node _pooled_T_51 = asUInt(_pooled_WIRE[19]) node _pooled_T_52 = asUInt(_pooled_WIRE[20]) node _pooled_T_53 = asUInt(_pooled_WIRE[21]) node _pooled_T_54 = asUInt(_pooled_WIRE[22]) node _pooled_T_55 = asUInt(_pooled_WIRE[23]) node _pooled_T_56 = asUInt(_pooled_WIRE[24]) node _pooled_T_57 = asUInt(_pooled_WIRE[25]) node _pooled_T_58 = asUInt(_pooled_WIRE[26]) node _pooled_T_59 = asUInt(_pooled_WIRE[27]) node _pooled_T_60 = asUInt(_pooled_WIRE[28]) node _pooled_T_61 = asUInt(_pooled_WIRE[29]) node _pooled_T_62 = asUInt(_pooled_WIRE[30]) node _pooled_T_63 = asUInt(_pooled_WIRE[31]) node _pooled_T_64 = asUInt(_pooled_WIRE[32]) node _pooled_T_65 = asUInt(_pooled_WIRE[33]) node _pooled_T_66 = asUInt(_pooled_WIRE[34]) node _pooled_T_67 = asUInt(_pooled_WIRE[35]) node _pooled_T_68 = asUInt(_pooled_WIRE[36]) node _pooled_T_69 = asUInt(_pooled_WIRE[37]) node _pooled_T_70 = asUInt(_pooled_WIRE[38]) node _pooled_T_71 = asUInt(_pooled_WIRE[39]) node _pooled_T_72 = asUInt(_pooled_WIRE[40]) node _pooled_T_73 = asUInt(_pooled_WIRE[41]) node _pooled_T_74 = asUInt(_pooled_WIRE[42]) node _pooled_T_75 = asUInt(_pooled_WIRE[43]) node _pooled_T_76 = asUInt(_pooled_WIRE[44]) node _pooled_T_77 = asUInt(_pooled_WIRE[45]) node _pooled_T_78 = asUInt(_pooled_WIRE[46]) node _pooled_T_79 = asUInt(_pooled_WIRE[47]) node _pooled_T_80 = asUInt(_pooled_WIRE[48]) node _pooled_T_81 = asUInt(_pooled_WIRE[49]) node _pooled_T_82 = asUInt(_pooled_WIRE[50]) node _pooled_T_83 = asUInt(_pooled_WIRE[51]) node _pooled_T_84 = asUInt(_pooled_WIRE[52]) node _pooled_T_85 = asUInt(_pooled_WIRE[53]) node _pooled_T_86 = asUInt(_pooled_WIRE[54]) node _pooled_T_87 = asUInt(_pooled_WIRE[55]) node _pooled_T_88 = asUInt(_pooled_WIRE[56]) node _pooled_T_89 = asUInt(_pooled_WIRE[57]) node _pooled_T_90 = asUInt(_pooled_WIRE[58]) node _pooled_T_91 = asUInt(_pooled_WIRE[59]) node _pooled_T_92 = asUInt(_pooled_WIRE[60]) node _pooled_T_93 = asUInt(_pooled_WIRE[61]) node _pooled_T_94 = asUInt(_pooled_WIRE[62]) node _pooled_T_95 = asUInt(_pooled_WIRE[63]) node pooled_lo_lo_lo_lo_lo = cat(_pooled_T_33, _pooled_T_32) node pooled_lo_lo_lo_lo_hi = cat(_pooled_T_35, _pooled_T_34) node pooled_lo_lo_lo_lo = cat(pooled_lo_lo_lo_lo_hi, pooled_lo_lo_lo_lo_lo) node pooled_lo_lo_lo_hi_lo = cat(_pooled_T_37, _pooled_T_36) node pooled_lo_lo_lo_hi_hi = cat(_pooled_T_39, _pooled_T_38) node pooled_lo_lo_lo_hi = cat(pooled_lo_lo_lo_hi_hi, pooled_lo_lo_lo_hi_lo) node pooled_lo_lo_lo = cat(pooled_lo_lo_lo_hi, pooled_lo_lo_lo_lo) node pooled_lo_lo_hi_lo_lo = cat(_pooled_T_41, _pooled_T_40) node pooled_lo_lo_hi_lo_hi = cat(_pooled_T_43, _pooled_T_42) node pooled_lo_lo_hi_lo = cat(pooled_lo_lo_hi_lo_hi, pooled_lo_lo_hi_lo_lo) node pooled_lo_lo_hi_hi_lo = cat(_pooled_T_45, _pooled_T_44) node pooled_lo_lo_hi_hi_hi = cat(_pooled_T_47, _pooled_T_46) node pooled_lo_lo_hi_hi = cat(pooled_lo_lo_hi_hi_hi, pooled_lo_lo_hi_hi_lo) node pooled_lo_lo_hi = cat(pooled_lo_lo_hi_hi, pooled_lo_lo_hi_lo) node pooled_lo_lo = cat(pooled_lo_lo_hi, pooled_lo_lo_lo) node pooled_lo_hi_lo_lo_lo = cat(_pooled_T_49, _pooled_T_48) node pooled_lo_hi_lo_lo_hi = cat(_pooled_T_51, _pooled_T_50) node pooled_lo_hi_lo_lo = cat(pooled_lo_hi_lo_lo_hi, pooled_lo_hi_lo_lo_lo) node pooled_lo_hi_lo_hi_lo = cat(_pooled_T_53, _pooled_T_52) node pooled_lo_hi_lo_hi_hi = cat(_pooled_T_55, _pooled_T_54) node pooled_lo_hi_lo_hi = cat(pooled_lo_hi_lo_hi_hi, pooled_lo_hi_lo_hi_lo) node pooled_lo_hi_lo = cat(pooled_lo_hi_lo_hi, pooled_lo_hi_lo_lo) node pooled_lo_hi_hi_lo_lo = cat(_pooled_T_57, _pooled_T_56) node pooled_lo_hi_hi_lo_hi = cat(_pooled_T_59, _pooled_T_58) node pooled_lo_hi_hi_lo = cat(pooled_lo_hi_hi_lo_hi, pooled_lo_hi_hi_lo_lo) node pooled_lo_hi_hi_hi_lo = cat(_pooled_T_61, _pooled_T_60) node pooled_lo_hi_hi_hi_hi = cat(_pooled_T_63, _pooled_T_62) node pooled_lo_hi_hi_hi = cat(pooled_lo_hi_hi_hi_hi, pooled_lo_hi_hi_hi_lo) node pooled_lo_hi_hi = cat(pooled_lo_hi_hi_hi, pooled_lo_hi_hi_lo) node pooled_lo_hi = cat(pooled_lo_hi_hi, pooled_lo_hi_lo) node pooled_lo = cat(pooled_lo_hi, pooled_lo_lo) node pooled_hi_lo_lo_lo_lo = cat(_pooled_T_65, _pooled_T_64) node pooled_hi_lo_lo_lo_hi = cat(_pooled_T_67, _pooled_T_66) node pooled_hi_lo_lo_lo = cat(pooled_hi_lo_lo_lo_hi, pooled_hi_lo_lo_lo_lo) node pooled_hi_lo_lo_hi_lo = cat(_pooled_T_69, _pooled_T_68) node pooled_hi_lo_lo_hi_hi = cat(_pooled_T_71, _pooled_T_70) node pooled_hi_lo_lo_hi = cat(pooled_hi_lo_lo_hi_hi, pooled_hi_lo_lo_hi_lo) node pooled_hi_lo_lo = cat(pooled_hi_lo_lo_hi, pooled_hi_lo_lo_lo) node pooled_hi_lo_hi_lo_lo = cat(_pooled_T_73, _pooled_T_72) node pooled_hi_lo_hi_lo_hi = cat(_pooled_T_75, _pooled_T_74) node pooled_hi_lo_hi_lo = cat(pooled_hi_lo_hi_lo_hi, pooled_hi_lo_hi_lo_lo) node pooled_hi_lo_hi_hi_lo = cat(_pooled_T_77, _pooled_T_76) node pooled_hi_lo_hi_hi_hi = cat(_pooled_T_79, _pooled_T_78) node pooled_hi_lo_hi_hi = cat(pooled_hi_lo_hi_hi_hi, pooled_hi_lo_hi_hi_lo) node pooled_hi_lo_hi = cat(pooled_hi_lo_hi_hi, pooled_hi_lo_hi_lo) node pooled_hi_lo = cat(pooled_hi_lo_hi, pooled_hi_lo_lo) node pooled_hi_hi_lo_lo_lo = cat(_pooled_T_81, _pooled_T_80) node pooled_hi_hi_lo_lo_hi = cat(_pooled_T_83, _pooled_T_82) node pooled_hi_hi_lo_lo = cat(pooled_hi_hi_lo_lo_hi, pooled_hi_hi_lo_lo_lo) node pooled_hi_hi_lo_hi_lo = cat(_pooled_T_85, _pooled_T_84) node pooled_hi_hi_lo_hi_hi = cat(_pooled_T_87, _pooled_T_86) node pooled_hi_hi_lo_hi = cat(pooled_hi_hi_lo_hi_hi, pooled_hi_hi_lo_hi_lo) node pooled_hi_hi_lo = cat(pooled_hi_hi_lo_hi, pooled_hi_hi_lo_lo) node pooled_hi_hi_hi_lo_lo = cat(_pooled_T_89, _pooled_T_88) node pooled_hi_hi_hi_lo_hi = cat(_pooled_T_91, _pooled_T_90) node pooled_hi_hi_hi_lo = cat(pooled_hi_hi_hi_lo_hi, pooled_hi_hi_hi_lo_lo) node pooled_hi_hi_hi_hi_lo = cat(_pooled_T_93, _pooled_T_92) node pooled_hi_hi_hi_hi_hi = cat(_pooled_T_95, _pooled_T_94) node pooled_hi_hi_hi_hi = cat(pooled_hi_hi_hi_hi_hi, pooled_hi_hi_hi_hi_lo) node pooled_hi_hi_hi = cat(pooled_hi_hi_hi_hi, pooled_hi_hi_hi_lo) node pooled_hi_hi = cat(pooled_hi_hi_hi, pooled_hi_hi_lo) node pooled_hi = cat(pooled_hi_hi, pooled_hi_lo) node pooled = cat(pooled_hi, pooled_lo) connect req, io.req.bits node _req_len_T = mul(io.req.bits.block, UInt<5>(0h10)) node _req_len_T_1 = add(_req_len_T, io.req.bits.len) node _req_len_T_2 = tail(_req_len_T_1, 1) connect req.len, _req_len_T_2 node _data_single_block_T = mux(io.req.bits.pool_en, pooled, io.req.bits.data) connect data_single_block, _data_single_block_T node _T_18 = bits(io.req.bits.block, 1, 0) connect data_blocks[_T_18], io.req.bits.data connect bytesSent, UInt<1>(0h0) node _state_T = mux(io.req.bits.store_en, UInt<2>(0h1), UInt<2>(0h0)) connect state, _state_T node _T_19 = leq(io.req.bits.len, UInt<5>(0h10)) node _T_20 = eq(io.req.bits.block, UInt<1>(0h0)) node _T_21 = or(_T_19, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed: DMA can't write multiple blocks to main memory when writing full accumulator output\n at DMA.scala:609 assert(io.req.bits.len <= (block_cols * inputType.getWidth / 8).U || io.req.bits.block === 0.U, \"DMA can't write multiple blocks to main memory when writing full accumulator output\")\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2 node _T_25 = eq(io.req.bits.pool_en, UInt<1>(0h0)) node _T_26 = eq(io.req.bits.block, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed: Can't pool with block-mvout\n at DMA.scala:610 assert(!io.req.bits.pool_en || io.req.bits.block === 0.U, \"Can't pool with block-mvout\")\n") : printf_3 assert(clock, _T_27, UInt<1>(0h1), "") : assert_3 wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 node _T_31 = neq(state, UInt<2>(0h0)) connect io.counter.event_signal[21], _T_31 connect io.counter.event_signal[22], io.tlb.resp.miss node _T_32 = eq(nodeOut.a.ready, UInt<1>(0h0)) node _T_33 = and(nodeOut.a.valid, _T_32) connect io.counter.event_signal[23], _T_33 regreset total_bytes_sent : UInt<32>, clock, reset, UInt<32>(0h0) node _T_34 = and(nodeOut.d.ready, nodeOut.d.valid) when _T_34 : node _total_bytes_sent_T = dshl(UInt<1>(0h1), nodeOut.d.bits.size) node _total_bytes_sent_T_1 = add(total_bytes_sent, _total_bytes_sent_T) node _total_bytes_sent_T_2 = tail(_total_bytes_sent_T_1, 1) connect total_bytes_sent, _total_bytes_sent_T_2 regreset total_latency : UInt<32>, clock, reset, UInt<32>(0h0) node _total_latency_T = bits(xactBusy, 0, 0) node _total_latency_T_1 = bits(xactBusy, 1, 1) node _total_latency_T_2 = bits(xactBusy, 2, 2) node _total_latency_T_3 = bits(xactBusy, 3, 3) node _total_latency_T_4 = bits(xactBusy, 4, 4) node _total_latency_T_5 = bits(xactBusy, 5, 5) node _total_latency_T_6 = bits(xactBusy, 6, 6) node _total_latency_T_7 = bits(xactBusy, 7, 7) node _total_latency_T_8 = bits(xactBusy, 8, 8) node _total_latency_T_9 = bits(xactBusy, 9, 9) node _total_latency_T_10 = bits(xactBusy, 10, 10) node _total_latency_T_11 = bits(xactBusy, 11, 11) node _total_latency_T_12 = bits(xactBusy, 12, 12) node _total_latency_T_13 = bits(xactBusy, 13, 13) node _total_latency_T_14 = bits(xactBusy, 14, 14) node _total_latency_T_15 = bits(xactBusy, 15, 15) node _total_latency_T_16 = add(_total_latency_T, _total_latency_T_1) node _total_latency_T_17 = bits(_total_latency_T_16, 1, 0) node _total_latency_T_18 = add(_total_latency_T_2, _total_latency_T_3) node _total_latency_T_19 = bits(_total_latency_T_18, 1, 0) node _total_latency_T_20 = add(_total_latency_T_17, _total_latency_T_19) node _total_latency_T_21 = bits(_total_latency_T_20, 2, 0) node _total_latency_T_22 = add(_total_latency_T_4, _total_latency_T_5) node _total_latency_T_23 = bits(_total_latency_T_22, 1, 0) node _total_latency_T_24 = add(_total_latency_T_6, _total_latency_T_7) node _total_latency_T_25 = bits(_total_latency_T_24, 1, 0) node _total_latency_T_26 = add(_total_latency_T_23, _total_latency_T_25) node _total_latency_T_27 = bits(_total_latency_T_26, 2, 0) node _total_latency_T_28 = add(_total_latency_T_21, _total_latency_T_27) node _total_latency_T_29 = bits(_total_latency_T_28, 3, 0) node _total_latency_T_30 = add(_total_latency_T_8, _total_latency_T_9) node _total_latency_T_31 = bits(_total_latency_T_30, 1, 0) node _total_latency_T_32 = add(_total_latency_T_10, _total_latency_T_11) node _total_latency_T_33 = bits(_total_latency_T_32, 1, 0) node _total_latency_T_34 = add(_total_latency_T_31, _total_latency_T_33) node _total_latency_T_35 = bits(_total_latency_T_34, 2, 0) node _total_latency_T_36 = add(_total_latency_T_12, _total_latency_T_13) node _total_latency_T_37 = bits(_total_latency_T_36, 1, 0) node _total_latency_T_38 = add(_total_latency_T_14, _total_latency_T_15) node _total_latency_T_39 = bits(_total_latency_T_38, 1, 0) node _total_latency_T_40 = add(_total_latency_T_37, _total_latency_T_39) node _total_latency_T_41 = bits(_total_latency_T_40, 2, 0) node _total_latency_T_42 = add(_total_latency_T_35, _total_latency_T_41) node _total_latency_T_43 = bits(_total_latency_T_42, 3, 0) node _total_latency_T_44 = add(_total_latency_T_29, _total_latency_T_43) node _total_latency_T_45 = bits(_total_latency_T_44, 4, 0) node _total_latency_T_46 = add(total_latency, _total_latency_T_45) node _total_latency_T_47 = tail(_total_latency_T_46, 1) connect total_latency, _total_latency_T_47 when io.counter.external_reset : connect total_bytes_sent, UInt<1>(0h0) connect total_latency, UInt<1>(0h0) connect io.counter.external_values[5], total_bytes_sent connect io.counter.external_values[7], total_latency extmodule plusarg_reader_90 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_91 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module StreamWriter( // @[DMA.scala:360:9] input clock, // @[DMA.scala:360:9] input reset, // @[DMA.scala:360:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_req_ready, // @[DMA.scala:371:16] input io_req_valid, // @[DMA.scala:371:16] input [39:0] io_req_bits_vaddr, // @[DMA.scala:371:16] input [511:0] io_req_bits_data, // @[DMA.scala:371:16] input [6:0] io_req_bits_len, // @[DMA.scala:371:16] input [7:0] io_req_bits_block, // @[DMA.scala:371:16] input io_req_bits_status_debug, // @[DMA.scala:371:16] input io_req_bits_status_cease, // @[DMA.scala:371:16] input io_req_bits_status_wfi, // @[DMA.scala:371:16] input [31:0] io_req_bits_status_isa, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_dprv, // @[DMA.scala:371:16] input io_req_bits_status_dv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_prv, // @[DMA.scala:371:16] input io_req_bits_status_v, // @[DMA.scala:371:16] input io_req_bits_status_sd, // @[DMA.scala:371:16] input [22:0] io_req_bits_status_zero2, // @[DMA.scala:371:16] input io_req_bits_status_mpv, // @[DMA.scala:371:16] input io_req_bits_status_gva, // @[DMA.scala:371:16] input io_req_bits_status_mbe, // @[DMA.scala:371:16] input io_req_bits_status_sbe, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_sxl, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_uxl, // @[DMA.scala:371:16] input io_req_bits_status_sd_rv32, // @[DMA.scala:371:16] input [7:0] io_req_bits_status_zero1, // @[DMA.scala:371:16] input io_req_bits_status_tsr, // @[DMA.scala:371:16] input io_req_bits_status_tw, // @[DMA.scala:371:16] input io_req_bits_status_tvm, // @[DMA.scala:371:16] input io_req_bits_status_mxr, // @[DMA.scala:371:16] input io_req_bits_status_sum, // @[DMA.scala:371:16] input io_req_bits_status_mprv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_xs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_fs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_mpp, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_vs, // @[DMA.scala:371:16] input io_req_bits_status_spp, // @[DMA.scala:371:16] input io_req_bits_status_mpie, // @[DMA.scala:371:16] input io_req_bits_status_ube, // @[DMA.scala:371:16] input io_req_bits_status_spie, // @[DMA.scala:371:16] input io_req_bits_status_upie, // @[DMA.scala:371:16] input io_req_bits_status_mie, // @[DMA.scala:371:16] input io_req_bits_status_hie, // @[DMA.scala:371:16] input io_req_bits_status_sie, // @[DMA.scala:371:16] input io_req_bits_status_uie, // @[DMA.scala:371:16] input io_req_bits_pool_en, // @[DMA.scala:371:16] input io_req_bits_store_en, // @[DMA.scala:371:16] output io_tlb_req_valid, // @[DMA.scala:371:16] output [39:0] io_tlb_req_bits_tlb_req_vaddr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_debug, // @[DMA.scala:371:16] output io_tlb_req_bits_status_cease, // @[DMA.scala:371:16] output io_tlb_req_bits_status_wfi, // @[DMA.scala:371:16] output [31:0] io_tlb_req_bits_status_isa, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_dprv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_dv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_prv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_v, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd, // @[DMA.scala:371:16] output [22:0] io_tlb_req_bits_status_zero2, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_gva, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mbe, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sbe, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_sxl, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_uxl, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd_rv32, // @[DMA.scala:371:16] output [7:0] io_tlb_req_bits_status_zero1, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tsr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tw, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tvm, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mxr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sum, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mprv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_xs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_fs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_mpp, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_vs, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spp, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_ube, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_upie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_hie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_uie, // @[DMA.scala:371:16] input io_tlb_resp_miss, // @[DMA.scala:371:16] input [31:0] io_tlb_resp_paddr, // @[DMA.scala:371:16] input [39:0] io_tlb_resp_gpa, // @[DMA.scala:371:16] input io_tlb_resp_pf_ld, // @[DMA.scala:371:16] input io_tlb_resp_pf_st, // @[DMA.scala:371:16] input io_tlb_resp_pf_inst, // @[DMA.scala:371:16] input io_tlb_resp_ae_ld, // @[DMA.scala:371:16] input io_tlb_resp_ae_st, // @[DMA.scala:371:16] input io_tlb_resp_ae_inst, // @[DMA.scala:371:16] input io_tlb_resp_cacheable, // @[DMA.scala:371:16] input io_tlb_resp_must_alloc, // @[DMA.scala:371:16] input io_tlb_resp_prefetchable, // @[DMA.scala:371:16] input [4:0] io_tlb_resp_cmd, // @[DMA.scala:371:16] output io_busy, // @[DMA.scala:371:16] input io_flush, // @[DMA.scala:371:16] output io_counter_event_signal_21, // @[DMA.scala:371:16] output io_counter_event_signal_22, // @[DMA.scala:371:16] output io_counter_event_signal_23, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_5, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_7, // @[DMA.scala:371:16] input io_counter_external_reset // @[DMA.scala:371:16] ); wire [7:0] pooled_v2_62; // @[DMA.scala:594:44] wire [7:0] pooled_v2_61; // @[DMA.scala:594:44] wire [7:0] pooled_v2_60; // @[DMA.scala:594:44] wire [7:0] pooled_v2_59; // @[DMA.scala:594:44] wire [7:0] pooled_v2_58; // @[DMA.scala:594:44] wire [7:0] pooled_v2_57; // @[DMA.scala:594:44] wire [7:0] pooled_v2_56; // @[DMA.scala:594:44] wire [7:0] pooled_v2_55; // @[DMA.scala:594:44] wire [7:0] pooled_v2_54; // @[DMA.scala:594:44] wire [7:0] pooled_v2_53; // @[DMA.scala:594:44] wire [7:0] pooled_v2_52; // @[DMA.scala:594:44] wire [7:0] pooled_v2_51; // @[DMA.scala:594:44] wire [7:0] pooled_v2_50; // @[DMA.scala:594:44] wire [7:0] pooled_v2_49; // @[DMA.scala:594:44] wire [7:0] pooled_v2_48; // @[DMA.scala:594:44] wire [7:0] pooled_v2_47; // @[DMA.scala:594:44] wire [7:0] pooled_v2_46; // @[DMA.scala:594:44] wire [7:0] pooled_v2_45; // @[DMA.scala:594:44] wire [7:0] pooled_v2_44; // @[DMA.scala:594:44] wire [7:0] pooled_v2_43; // @[DMA.scala:594:44] wire [7:0] pooled_v2_42; // @[DMA.scala:594:44] wire [7:0] pooled_v2_41; // @[DMA.scala:594:44] wire [7:0] pooled_v2_40; // @[DMA.scala:594:44] wire [7:0] pooled_v2_39; // @[DMA.scala:594:44] wire [7:0] pooled_v2_38; // @[DMA.scala:594:44] wire [7:0] pooled_v2_37; // @[DMA.scala:594:44] wire [7:0] pooled_v2_36; // @[DMA.scala:594:44] wire [7:0] pooled_v2_35; // @[DMA.scala:594:44] wire [7:0] pooled_v2_34; // @[DMA.scala:594:44] wire [7:0] pooled_v2_33; // @[DMA.scala:594:44] wire [7:0] pooled_v2_32; // @[DMA.scala:594:44] wire [7:0] pooled_v2_31; // @[DMA.scala:594:44] wire [7:0] pooled_v2_30; // @[DMA.scala:594:44] wire [7:0] pooled_v2_29; // @[DMA.scala:594:44] wire [7:0] pooled_v2_28; // @[DMA.scala:594:44] wire [7:0] pooled_v2_27; // @[DMA.scala:594:44] wire [7:0] pooled_v2_26; // @[DMA.scala:594:44] wire [7:0] pooled_v2_25; // @[DMA.scala:594:44] wire [7:0] pooled_v2_24; // @[DMA.scala:594:44] wire [7:0] pooled_v2_23; // @[DMA.scala:594:44] wire [7:0] pooled_v2_22; // @[DMA.scala:594:44] wire [7:0] pooled_v2_21; // @[DMA.scala:594:44] wire [7:0] pooled_v2_20; // @[DMA.scala:594:44] wire [7:0] pooled_v2_19; // @[DMA.scala:594:44] wire [7:0] pooled_v2_18; // @[DMA.scala:594:44] wire [7:0] pooled_v2_17; // @[DMA.scala:594:44] wire [7:0] pooled_v2_16; // @[DMA.scala:594:44] reg [1:0] state; // @[DMA.scala:380:24] wire _translate_q_io_enq_ready; // @[DMA.scala:534:29] wire _translate_q_io_deq_valid; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:534:29] wire [3:0] _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:534:29] wire [3:0] _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:534:29] wire [15:0] _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:534:29] wire [127:0] _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:534:29] wire _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:534:29] wire _tlb_q_io_enq_ready; // @[DMA.scala:523:23] wire _tlb_q_io_deq_valid; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_param; // @[DMA.scala:523:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_size; // @[DMA.scala:523:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_source; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_tl_a_address; // @[DMA.scala:523:23] wire [15:0] _tlb_q_io_deq_bits_tl_a_mask; // @[DMA.scala:523:23] wire [127:0] _tlb_q_io_deq_bits_tl_a_data; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:523:23] wire [38:0] _tlb_q_io_deq_bits_vaddr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_v; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:523:23] wire [22:0] _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:523:23] wire [7:0] _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:523:23] wire _tlb_arb_io_in_1_ready; // @[DMA.scala:518:25] wire _tlb_arb_io_out_valid; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_opcode; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_param; // @[DMA.scala:518:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_size; // @[DMA.scala:518:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_source; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_tl_a_address; // @[DMA.scala:518:25] wire [15:0] _tlb_arb_io_out_bits_tl_a_mask; // @[DMA.scala:518:25] wire [127:0] _tlb_arb_io_out_bits_tl_a_data; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_tl_a_corrupt; // @[DMA.scala:518:25] wire [38:0] _tlb_arb_io_out_bits_vaddr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_debug; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_cease; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_wfi; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_status_isa; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_dprv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_dv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_prv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_v; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd; // @[DMA.scala:518:25] wire [22:0] _tlb_arb_io_out_bits_status_zero2; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_gva; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mbe; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sbe; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_sxl; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_uxl; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd_rv32; // @[DMA.scala:518:25] wire [7:0] _tlb_arb_io_out_bits_status_zero1; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tsr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tw; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tvm; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mxr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sum; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mprv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_xs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_fs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_mpp; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_vs; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spp; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_ube; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_upie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_hie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_uie; // @[DMA.scala:518:25] wire _shadow_retry_a_io_deq_valid; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_opcode; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_param; // @[DMA.scala:515:32] wire [3:0] _shadow_retry_a_io_deq_bits_tl_a_size; // @[DMA.scala:515:32] wire [3:0] _shadow_retry_a_io_deq_bits_tl_a_source; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_tl_a_address; // @[DMA.scala:515:32] wire [15:0] _shadow_retry_a_io_deq_bits_tl_a_mask; // @[DMA.scala:515:32] wire [127:0] _shadow_retry_a_io_deq_bits_tl_a_data; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_tl_a_corrupt; // @[DMA.scala:515:32] wire [38:0] _shadow_retry_a_io_deq_bits_vaddr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_debug; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_cease; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_wfi; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_status_isa; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_dprv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_dv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_prv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_v; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd; // @[DMA.scala:515:32] wire [22:0] _shadow_retry_a_io_deq_bits_status_zero2; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_gva; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mbe; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sbe; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_sxl; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_uxl; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd_rv32; // @[DMA.scala:515:32] wire [7:0] _shadow_retry_a_io_deq_bits_status_zero1; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tsr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tw; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tvm; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mxr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sum; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mprv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_xs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_fs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_mpp; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_vs; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spp; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_ube; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_upie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_hie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_uie; // @[DMA.scala:515:32] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:360:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:360:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:360:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:360:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:360:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:360:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:360:9] wire io_req_valid_0 = io_req_valid; // @[DMA.scala:360:9] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[DMA.scala:360:9] wire [511:0] io_req_bits_data_0 = io_req_bits_data; // @[DMA.scala:360:9] wire [6:0] io_req_bits_len_0 = io_req_bits_len; // @[DMA.scala:360:9] wire [7:0] io_req_bits_block_0 = io_req_bits_block; // @[DMA.scala:360:9] wire io_req_bits_status_debug_0 = io_req_bits_status_debug; // @[DMA.scala:360:9] wire io_req_bits_status_cease_0 = io_req_bits_status_cease; // @[DMA.scala:360:9] wire io_req_bits_status_wfi_0 = io_req_bits_status_wfi; // @[DMA.scala:360:9] wire [31:0] io_req_bits_status_isa_0 = io_req_bits_status_isa; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_dprv_0 = io_req_bits_status_dprv; // @[DMA.scala:360:9] wire io_req_bits_status_dv_0 = io_req_bits_status_dv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_prv_0 = io_req_bits_status_prv; // @[DMA.scala:360:9] wire io_req_bits_status_v_0 = io_req_bits_status_v; // @[DMA.scala:360:9] wire io_req_bits_status_sd_0 = io_req_bits_status_sd; // @[DMA.scala:360:9] wire [22:0] io_req_bits_status_zero2_0 = io_req_bits_status_zero2; // @[DMA.scala:360:9] wire io_req_bits_status_mpv_0 = io_req_bits_status_mpv; // @[DMA.scala:360:9] wire io_req_bits_status_gva_0 = io_req_bits_status_gva; // @[DMA.scala:360:9] wire io_req_bits_status_mbe_0 = io_req_bits_status_mbe; // @[DMA.scala:360:9] wire io_req_bits_status_sbe_0 = io_req_bits_status_sbe; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_sxl_0 = io_req_bits_status_sxl; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_uxl_0 = io_req_bits_status_uxl; // @[DMA.scala:360:9] wire io_req_bits_status_sd_rv32_0 = io_req_bits_status_sd_rv32; // @[DMA.scala:360:9] wire [7:0] io_req_bits_status_zero1_0 = io_req_bits_status_zero1; // @[DMA.scala:360:9] wire io_req_bits_status_tsr_0 = io_req_bits_status_tsr; // @[DMA.scala:360:9] wire io_req_bits_status_tw_0 = io_req_bits_status_tw; // @[DMA.scala:360:9] wire io_req_bits_status_tvm_0 = io_req_bits_status_tvm; // @[DMA.scala:360:9] wire io_req_bits_status_mxr_0 = io_req_bits_status_mxr; // @[DMA.scala:360:9] wire io_req_bits_status_sum_0 = io_req_bits_status_sum; // @[DMA.scala:360:9] wire io_req_bits_status_mprv_0 = io_req_bits_status_mprv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_xs_0 = io_req_bits_status_xs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_fs_0 = io_req_bits_status_fs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_mpp_0 = io_req_bits_status_mpp; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_vs_0 = io_req_bits_status_vs; // @[DMA.scala:360:9] wire io_req_bits_status_spp_0 = io_req_bits_status_spp; // @[DMA.scala:360:9] wire io_req_bits_status_mpie_0 = io_req_bits_status_mpie; // @[DMA.scala:360:9] wire io_req_bits_status_ube_0 = io_req_bits_status_ube; // @[DMA.scala:360:9] wire io_req_bits_status_spie_0 = io_req_bits_status_spie; // @[DMA.scala:360:9] wire io_req_bits_status_upie_0 = io_req_bits_status_upie; // @[DMA.scala:360:9] wire io_req_bits_status_mie_0 = io_req_bits_status_mie; // @[DMA.scala:360:9] wire io_req_bits_status_hie_0 = io_req_bits_status_hie; // @[DMA.scala:360:9] wire io_req_bits_status_sie_0 = io_req_bits_status_sie; // @[DMA.scala:360:9] wire io_req_bits_status_uie_0 = io_req_bits_status_uie; // @[DMA.scala:360:9] wire io_req_bits_pool_en_0 = io_req_bits_pool_en; // @[DMA.scala:360:9] wire io_req_bits_store_en_0 = io_req_bits_store_en; // @[DMA.scala:360:9] wire io_tlb_resp_miss_0 = io_tlb_resp_miss; // @[DMA.scala:360:9] wire [31:0] io_tlb_resp_paddr_0 = io_tlb_resp_paddr; // @[DMA.scala:360:9] wire [39:0] io_tlb_resp_gpa_0 = io_tlb_resp_gpa; // @[DMA.scala:360:9] wire io_tlb_resp_pf_ld_0 = io_tlb_resp_pf_ld; // @[DMA.scala:360:9] wire io_tlb_resp_pf_st_0 = io_tlb_resp_pf_st; // @[DMA.scala:360:9] wire io_tlb_resp_pf_inst_0 = io_tlb_resp_pf_inst; // @[DMA.scala:360:9] wire io_tlb_resp_ae_ld_0 = io_tlb_resp_ae_ld; // @[DMA.scala:360:9] wire io_tlb_resp_ae_st_0 = io_tlb_resp_ae_st; // @[DMA.scala:360:9] wire io_tlb_resp_ae_inst_0 = io_tlb_resp_ae_inst; // @[DMA.scala:360:9] wire io_tlb_resp_cacheable_0 = io_tlb_resp_cacheable; // @[DMA.scala:360:9] wire io_tlb_resp_must_alloc_0 = io_tlb_resp_must_alloc; // @[DMA.scala:360:9] wire io_tlb_resp_prefetchable_0 = io_tlb_resp_prefetchable; // @[DMA.scala:360:9] wire [4:0] io_tlb_resp_cmd_0 = io_tlb_resp_cmd; // @[DMA.scala:360:9] wire io_flush_0 = io_flush; // @[DMA.scala:360:9] wire io_counter_external_reset_0 = io_counter_external_reset; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_passthrough = 1'h0; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_v = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gpa_is_pte = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_inst = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_inst = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_0 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_1 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_2 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_3 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_4 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_5 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_6 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_7 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_8 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_9 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_10 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_11 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_12 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_13 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_14 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_15 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_16 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_17 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_18 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_19 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_20 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_24 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_25 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_26 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_27 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_28 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_29 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_30 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_31 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_32 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_33 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_34 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_35 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_36 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_37 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_38 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_39 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_40 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_41 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_42 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_43 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_44 = 1'h0; // @[DMA.scala:360:9] wire write_packets_mask_16 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_17 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_18 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_19 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_20 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_21 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_22 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_23 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_24 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_25 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_26 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_27 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_28 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_29 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_30 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_31 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_32 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63 = 1'h0; // @[DMA.scala:431:103] wire write_packets_0_mask_1_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_1_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_4_1_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_5 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_7 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_1 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_10 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_12 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_2 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_15 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_17 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_3 = 1'h0; // @[DMA.scala:457:38] wire write_packets_mask_32_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_1_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_7_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_9_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early_5 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_30 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_32 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_6 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_35 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_37 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_7 = 1'h0; // @[DMA.scala:457:38] wire write_packets_too_early_11 = 1'h0; // @[DMA.scala:457:38] wire _best_write_packet_T_1_mask_2_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_15 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_15 = 1'h0; // @[DMA.scala:466:10] wire _putFull_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putFull_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putFull_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putFull_corrupt = 1'h0; // @[Edges.scala:480:17] wire putFull_a_mask_sub_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_4_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_5_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_6_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_7_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_8 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _putPartial_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putPartial_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putPartial_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putPartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire untranslated_a_bits_tl_a_corrupt = 1'h0; // @[DMA.scala:506:30] wire _untranslated_a_bits_tl_a_T_corrupt = 1'h0; // @[DMA.scala:509:36] wire [1:0] io_tlb_req_bits_tlb_req_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_tlb_req_prv = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_resp_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] _putFull_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _putPartial_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [4:0] io_tlb_req_bits_tlb_req_cmd = 5'h1; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_0 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_1 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_2 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_3 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_4 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_6 = 32'h0; // @[DMA.scala:360:9] wire [31:0] putFull_address = 32'h0; // @[Edges.scala:480:17] wire [31:0] putPartial_address = 32'h0; // @[Edges.scala:500:17] wire [31:0] untranslated_a_bits_tl_a_address = 32'h0; // @[DMA.scala:506:30] wire [31:0] _untranslated_a_bits_tl_a_T_address = 32'h0; // @[DMA.scala:509:36] wire [2:0] putFull_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] putFull_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putPartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] untranslated_a_bits_tl_a_param = 3'h0; // @[DMA.scala:506:30] wire [2:0] _untranslated_a_bits_tl_a_T_param = 3'h0; // @[DMA.scala:509:36] wire [2:0] putPartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [32:0] _putFull_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _putFull_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _putPartial_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire _write_packets_mask_T_60 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_64 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_68 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_72 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_76 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_80 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_84 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_88 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_92 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_96 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_100 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_104 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_108 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_112 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_116 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_120 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_124 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_128 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_132 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_136 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_140 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_144 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_148 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_152 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_156 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_160 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_164 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_168 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_172 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_176 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_180 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_184 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_188 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_192 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_196 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_200 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_204 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_208 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_212 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_216 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_220 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_224 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_228 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_232 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_236 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_240 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_244 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_248 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_252 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T = 1'h1; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_1 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_2 = 1'h1; // @[DMA.scala:449:62] wire _write_packets_right_shift_T_1 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_6 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_11 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_16 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_380 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_384 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_388 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_392 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_396 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_400 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_404 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_408 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_412 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_416 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_420 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_424 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_428 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_432 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_436 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_440 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_444 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_448 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_452 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_456 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_460 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_464 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_468 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_472 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_476 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_480 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_484 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_488 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_492 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_496 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_500 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_504 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_508 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_20 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_33 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_26 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_31 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_36 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_764 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_40 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_65 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_56 = 1'h1; // @[DMA.scala:449:78] wire _putFull_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putFull_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putFull_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putFull_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putFull_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire putFull_a_mask_sub_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _putPartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putPartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putPartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putPartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putPartial_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire [32:0] _putFull_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putPartial_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [29:0] _putFull_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [29:0] _putPartial_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _putFull_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putFull_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [21:0] _putFull_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [21:0] _putPartial_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [14:0] _putFull_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [14:0] _putPartial_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [2:0] write_packets_2_lg_size = 3'h6; // @[DMA.scala:437:24] wire [6:0] write_packets_2_size = 7'h40; // @[DMA.scala:437:24] wire [5:0] write_packets_left_shift_2 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_3 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_6 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_7 = 6'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_1_lg_size = 3'h5; // @[DMA.scala:437:24] wire [6:0] write_packets_1_size = 7'h20; // @[DMA.scala:437:24] wire [4:0] write_packets_left_shift_1 = 5'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_0_lg_size = 3'h4; // @[DMA.scala:437:24] wire [6:0] write_packets_0_size = 7'h10; // @[DMA.scala:437:24] wire [16:0] _putFull_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _putPartial_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [31:0] _putFull_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _putPartial_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [28:0] _putFull_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [28:0] _putPartial_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [20:0] _putFull_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [20:0] _putPartial_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [13:0] _putFull_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire [13:0] _putPartial_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:360:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:360:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:360:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:360:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:360:9] wire state_machine_ready_for_req; // @[DMA.scala:401:47] wire [511:0] _pooled_v1_WIRE = io_req_bits_data_0; // @[DMA.scala:360:9, :593:43] wire _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] wire io_counter_event_signal_22_0 = io_tlb_resp_miss_0; // @[DMA.scala:360:9] wire _io_busy_T_2; // @[DMA.scala:403:29] wire io_counter_event_signal_21_0 = |state; // @[DMA.scala:360:9, :380:24, :403:39] wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:360:9] wire [2:0] auto_out_a_bits_param_0; // @[DMA.scala:360:9] wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:360:9] wire [3:0] auto_out_a_bits_source_0; // @[DMA.scala:360:9] wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:360:9] wire [15:0] auto_out_a_bits_mask_0; // @[DMA.scala:360:9] wire [127:0] auto_out_a_bits_data_0; // @[DMA.scala:360:9] wire auto_out_a_bits_corrupt_0; // @[DMA.scala:360:9] wire auto_out_a_valid_0; // @[DMA.scala:360:9] wire auto_out_d_ready_0; // @[DMA.scala:360:9] wire io_req_ready_0; // @[DMA.scala:360:9] wire [39:0] io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_debug_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_cease_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_wfi_0; // @[DMA.scala:360:9] wire [31:0] io_tlb_req_bits_status_isa_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_dprv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_dv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_prv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_v_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_0; // @[DMA.scala:360:9] wire [22:0] io_tlb_req_bits_status_zero2_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_gva_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mbe_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sbe_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_sxl_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_uxl_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:360:9] wire [7:0] io_tlb_req_bits_status_zero1_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tsr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tw_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tvm_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mxr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sum_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mprv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_xs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_fs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_mpp_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_vs_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spp_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_ube_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_upie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_hie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_uie_0; // @[DMA.scala:360:9] wire io_tlb_req_valid_0; // @[DMA.scala:360:9] wire io_counter_event_signal_23_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_5_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_7_0; // @[DMA.scala:360:9] wire io_busy_0; // @[DMA.scala:360:9] wire _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:360:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:360:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DMA.scala:360:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:360:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:360:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:360:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:360:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:360:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[DMA.scala:360:9] wire _nodeOut_d_ready_T; // @[DMA.scala:551:28] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:360:9] reg [39:0] req_vaddr; // @[DMA.scala:382:18] reg [511:0] req_data; // @[DMA.scala:382:18] reg [6:0] req_len; // @[DMA.scala:382:18] reg [7:0] req_block; // @[DMA.scala:382:18] reg req_status_debug; // @[DMA.scala:382:18] wire untranslated_a_bits_status_debug = req_status_debug; // @[DMA.scala:382:18, :506:30] reg req_status_cease; // @[DMA.scala:382:18] wire untranslated_a_bits_status_cease = req_status_cease; // @[DMA.scala:382:18, :506:30] reg req_status_wfi; // @[DMA.scala:382:18] wire untranslated_a_bits_status_wfi = req_status_wfi; // @[DMA.scala:382:18, :506:30] reg [31:0] req_status_isa; // @[DMA.scala:382:18] wire [31:0] untranslated_a_bits_status_isa = req_status_isa; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_dprv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_dprv = req_status_dprv; // @[DMA.scala:382:18, :506:30] reg req_status_dv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_dv = req_status_dv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_prv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_prv = req_status_prv; // @[DMA.scala:382:18, :506:30] reg req_status_v; // @[DMA.scala:382:18] wire untranslated_a_bits_status_v = req_status_v; // @[DMA.scala:382:18, :506:30] reg req_status_sd; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd = req_status_sd; // @[DMA.scala:382:18, :506:30] reg [22:0] req_status_zero2; // @[DMA.scala:382:18] wire [22:0] untranslated_a_bits_status_zero2 = req_status_zero2; // @[DMA.scala:382:18, :506:30] reg req_status_mpv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpv = req_status_mpv; // @[DMA.scala:382:18, :506:30] reg req_status_gva; // @[DMA.scala:382:18] wire untranslated_a_bits_status_gva = req_status_gva; // @[DMA.scala:382:18, :506:30] reg req_status_mbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mbe = req_status_mbe; // @[DMA.scala:382:18, :506:30] reg req_status_sbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sbe = req_status_sbe; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_sxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_sxl = req_status_sxl; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_uxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_uxl = req_status_uxl; // @[DMA.scala:382:18, :506:30] reg req_status_sd_rv32; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd_rv32 = req_status_sd_rv32; // @[DMA.scala:382:18, :506:30] reg [7:0] req_status_zero1; // @[DMA.scala:382:18] wire [7:0] untranslated_a_bits_status_zero1 = req_status_zero1; // @[DMA.scala:382:18, :506:30] reg req_status_tsr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tsr = req_status_tsr; // @[DMA.scala:382:18, :506:30] reg req_status_tw; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tw = req_status_tw; // @[DMA.scala:382:18, :506:30] reg req_status_tvm; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tvm = req_status_tvm; // @[DMA.scala:382:18, :506:30] reg req_status_mxr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mxr = req_status_mxr; // @[DMA.scala:382:18, :506:30] reg req_status_sum; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sum = req_status_sum; // @[DMA.scala:382:18, :506:30] reg req_status_mprv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mprv = req_status_mprv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_xs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_xs = req_status_xs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_fs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_fs = req_status_fs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_mpp; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_mpp = req_status_mpp; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_vs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_vs = req_status_vs; // @[DMA.scala:382:18, :506:30] reg req_status_spp; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spp = req_status_spp; // @[DMA.scala:382:18, :506:30] reg req_status_mpie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpie = req_status_mpie; // @[DMA.scala:382:18, :506:30] reg req_status_ube; // @[DMA.scala:382:18] wire untranslated_a_bits_status_ube = req_status_ube; // @[DMA.scala:382:18, :506:30] reg req_status_spie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spie = req_status_spie; // @[DMA.scala:382:18, :506:30] reg req_status_upie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_upie = req_status_upie; // @[DMA.scala:382:18, :506:30] reg req_status_mie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mie = req_status_mie; // @[DMA.scala:382:18, :506:30] reg req_status_hie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_hie = req_status_hie; // @[DMA.scala:382:18, :506:30] reg req_status_sie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sie = req_status_sie; // @[DMA.scala:382:18, :506:30] reg req_status_uie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_uie = req_status_uie; // @[DMA.scala:382:18, :506:30] reg req_pool_en; // @[DMA.scala:382:18] reg req_store_en; // @[DMA.scala:382:18] reg [127:0] data_blocks_0; // @[DMA.scala:385:26] reg [127:0] data_blocks_1; // @[DMA.scala:385:26] reg [127:0] data_blocks_2; // @[DMA.scala:385:26] reg [127:0] data_blocks_3; // @[DMA.scala:385:26] reg [511:0] data_single_block; // @[DMA.scala:386:32] wire [511:0] _pooled_v2_WIRE = data_single_block; // @[DMA.scala:386:32, :594:44] wire _data_T = req_block == 8'h0; // @[DMA.scala:382:18, :387:30] wire [255:0] data_lo = {data_blocks_1, data_blocks_0}; // @[DMA.scala:385:26, :387:70] wire [255:0] data_hi = {data_blocks_3, data_blocks_2}; // @[DMA.scala:385:26, :387:70] wire [511:0] _data_T_1 = {data_hi, data_lo}; // @[DMA.scala:387:70] wire [511:0] data = _data_T ? data_single_block : _data_T_1; // @[DMA.scala:386:32, :387:{19,30,70}] reg [6:0] bytesSent; // @[DMA.scala:389:24] wire [7:0] _GEN = {1'h0, bytesSent}; // @[DMA.scala:389:24, :390:29] wire [7:0] _bytesLeft_T = {1'h0, req_len} - _GEN; // @[DMA.scala:382:18, :390:29] wire [6:0] bytesLeft = _bytesLeft_T[6:0]; // @[DMA.scala:390:29] reg [15:0] xactBusy; // @[DMA.scala:392:27] wire [15:0] _xactOnehot_T = ~xactBusy; // @[DMA.scala:392:27, :393:40] wire _xactOnehot_T_1 = _xactOnehot_T[0]; // @[OneHot.scala:85:71] wire _xactOnehot_T_2 = _xactOnehot_T[1]; // @[OneHot.scala:85:71] wire _xactOnehot_T_3 = _xactOnehot_T[2]; // @[OneHot.scala:85:71] wire _xactOnehot_T_4 = _xactOnehot_T[3]; // @[OneHot.scala:85:71] wire _xactOnehot_T_5 = _xactOnehot_T[4]; // @[OneHot.scala:85:71] wire _xactOnehot_T_6 = _xactOnehot_T[5]; // @[OneHot.scala:85:71] wire _xactOnehot_T_7 = _xactOnehot_T[6]; // @[OneHot.scala:85:71] wire _xactOnehot_T_8 = _xactOnehot_T[7]; // @[OneHot.scala:85:71] wire _xactOnehot_T_9 = _xactOnehot_T[8]; // @[OneHot.scala:85:71] wire _xactOnehot_T_10 = _xactOnehot_T[9]; // @[OneHot.scala:85:71] wire _xactOnehot_T_11 = _xactOnehot_T[10]; // @[OneHot.scala:85:71] wire _xactOnehot_T_12 = _xactOnehot_T[11]; // @[OneHot.scala:85:71] wire _xactOnehot_T_13 = _xactOnehot_T[12]; // @[OneHot.scala:85:71] wire _xactOnehot_T_14 = _xactOnehot_T[13]; // @[OneHot.scala:85:71] wire _xactOnehot_T_15 = _xactOnehot_T[14]; // @[OneHot.scala:85:71] wire _xactOnehot_T_16 = _xactOnehot_T[15]; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_17 = {_xactOnehot_T_16, 15'h0}; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_18 = _xactOnehot_T_15 ? 16'h4000 : _xactOnehot_T_17; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_19 = _xactOnehot_T_14 ? 16'h2000 : _xactOnehot_T_18; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_20 = _xactOnehot_T_13 ? 16'h1000 : _xactOnehot_T_19; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_21 = _xactOnehot_T_12 ? 16'h800 : _xactOnehot_T_20; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_22 = _xactOnehot_T_11 ? 16'h400 : _xactOnehot_T_21; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_23 = _xactOnehot_T_10 ? 16'h200 : _xactOnehot_T_22; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_24 = _xactOnehot_T_9 ? 16'h100 : _xactOnehot_T_23; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_25 = _xactOnehot_T_8 ? 16'h80 : _xactOnehot_T_24; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_26 = _xactOnehot_T_7 ? 16'h40 : _xactOnehot_T_25; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_27 = _xactOnehot_T_6 ? 16'h20 : _xactOnehot_T_26; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_28 = _xactOnehot_T_5 ? 16'h10 : _xactOnehot_T_27; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_29 = _xactOnehot_T_4 ? 16'h8 : _xactOnehot_T_28; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_30 = _xactOnehot_T_3 ? 16'h4 : _xactOnehot_T_29; // @[OneHot.scala:85:71] wire [15:0] _xactOnehot_T_31 = _xactOnehot_T_2 ? 16'h2 : _xactOnehot_T_30; // @[OneHot.scala:85:71] wire [15:0] xactOnehot = _xactOnehot_T_1 ? 16'h1 : _xactOnehot_T_31; // @[OneHot.scala:85:71] wire [7:0] xactId_hi = xactOnehot[15:8]; // @[OneHot.scala:30:18] wire [7:0] xactId_lo = xactOnehot[7:0]; // @[OneHot.scala:31:18] wire _xactId_T = |xactId_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _xactId_T_1 = xactId_hi | xactId_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] xactId_hi_1 = _xactId_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] xactId_lo_1 = _xactId_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_2 = |xactId_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _xactId_T_3 = xactId_hi_1 | xactId_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] xactId_hi_2 = _xactId_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] xactId_lo_2 = _xactId_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_4 = |xactId_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _xactId_T_5 = xactId_hi_2 | xactId_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _xactId_T_6 = _xactId_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _xactId_T_7 = {_xactId_T_4, _xactId_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _xactId_T_8 = {_xactId_T_2, _xactId_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] xactId = {_xactId_T, _xactId_T_8}; // @[OneHot.scala:32:{10,14}] wire _xactBusy_fire_T_2; // @[DMA.scala:507:42] wire xactBusy_fire; // @[DMA.scala:396:33] wire [15:0] _xactBusy_add_T = 16'h1 << xactId; // @[OneHot.scala:32:10] wire [15:0] xactBusy_add = xactBusy_fire ? _xactBusy_add_T : 16'h0; // @[DMA.scala:396:33, :397:{27,48}] wire _xactBusy_remove_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire [15:0] _xactBusy_remove_T_1 = 16'h1 << nodeOut_d_bits_source; // @[DMA.scala:398:48] wire [15:0] _xactBusy_remove_T_2 = _xactBusy_remove_T ? _xactBusy_remove_T_1 : 16'h0; // @[Decoupled.scala:51:35] wire [15:0] xactBusy_remove = ~_xactBusy_remove_T_2; // @[DMA.scala:398:{27,31}] wire [15:0] _xactBusy_T = xactBusy | xactBusy_add; // @[DMA.scala:392:27, :397:27, :399:27] wire [15:0] _xactBusy_T_1 = _xactBusy_T & xactBusy_remove; // @[DMA.scala:398:27, :399:{27,43}] wire _state_machine_ready_for_req_T = state == 2'h0; // @[DMA.scala:380:24, :401:54] assign io_req_ready_0 = state_machine_ready_for_req; // @[DMA.scala:360:9, :401:47] wire _io_busy_T = |xactBusy; // @[DMA.scala:392:27, :403:25] wire _io_busy_T_1 = |state; // @[DMA.scala:380:24, :403:39] assign _io_busy_T_2 = _io_busy_T | _io_busy_T_1; // @[DMA.scala:403:{25,29,39}] assign io_busy_0 = _io_busy_T_2; // @[DMA.scala:360:9, :403:29] wire [34:0] _write_packets_vaddr_aligned_to_size_T = req_vaddr[38:4]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size = {_write_packets_vaddr_aligned_to_size_T, 4'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_0_vaddr = write_packets_vaddr_aligned_to_size; // @[DMA.scala:428:61, :437:24] wire [3:0] write_packets_vaddr_offset = req_vaddr[3:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T = write_packets_vaddr_offset == 4'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_0 = {1'h0, bytesLeft}; // @[DMA.scala:390:29, :431:90] wire [7:0] _GEN_1 = {4'h0, write_packets_vaddr_offset} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_1; // @[DMA.scala:431:90] assign _write_packets_mask_T_1 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_5; // @[DMA.scala:431:90] assign _write_packets_mask_T_5 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_9; // @[DMA.scala:431:90] assign _write_packets_mask_T_9 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_13; // @[DMA.scala:431:90] assign _write_packets_mask_T_13 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_17; // @[DMA.scala:431:90] assign _write_packets_mask_T_17 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_21; // @[DMA.scala:431:90] assign _write_packets_mask_T_21 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_25; // @[DMA.scala:431:90] assign _write_packets_mask_T_25 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_29; // @[DMA.scala:431:90] assign _write_packets_mask_T_29 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_33; // @[DMA.scala:431:90] assign _write_packets_mask_T_33 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_37; // @[DMA.scala:431:90] assign _write_packets_mask_T_37 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_41; // @[DMA.scala:431:90] assign _write_packets_mask_T_41 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_45; // @[DMA.scala:431:90] assign _write_packets_mask_T_45 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_49; // @[DMA.scala:431:90] assign _write_packets_mask_T_49 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_53; // @[DMA.scala:431:90] assign _write_packets_mask_T_53 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_57; // @[DMA.scala:431:90] assign _write_packets_mask_T_57 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_61; // @[DMA.scala:431:90] assign _write_packets_mask_T_61 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_65; // @[DMA.scala:431:90] assign _write_packets_mask_T_65 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_69; // @[DMA.scala:431:90] assign _write_packets_mask_T_69 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_73; // @[DMA.scala:431:90] assign _write_packets_mask_T_73 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_77; // @[DMA.scala:431:90] assign _write_packets_mask_T_77 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_81; // @[DMA.scala:431:90] assign _write_packets_mask_T_81 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_85; // @[DMA.scala:431:90] assign _write_packets_mask_T_85 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_89; // @[DMA.scala:431:90] assign _write_packets_mask_T_89 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_93; // @[DMA.scala:431:90] assign _write_packets_mask_T_93 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_97; // @[DMA.scala:431:90] assign _write_packets_mask_T_97 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_101; // @[DMA.scala:431:90] assign _write_packets_mask_T_101 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_105; // @[DMA.scala:431:90] assign _write_packets_mask_T_105 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_109; // @[DMA.scala:431:90] assign _write_packets_mask_T_109 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_113; // @[DMA.scala:431:90] assign _write_packets_mask_T_113 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_117; // @[DMA.scala:431:90] assign _write_packets_mask_T_117 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_121; // @[DMA.scala:431:90] assign _write_packets_mask_T_121 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_125; // @[DMA.scala:431:90] assign _write_packets_mask_T_125 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_129; // @[DMA.scala:431:90] assign _write_packets_mask_T_129 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_133; // @[DMA.scala:431:90] assign _write_packets_mask_T_133 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_137; // @[DMA.scala:431:90] assign _write_packets_mask_T_137 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_141; // @[DMA.scala:431:90] assign _write_packets_mask_T_141 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_145; // @[DMA.scala:431:90] assign _write_packets_mask_T_145 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_149; // @[DMA.scala:431:90] assign _write_packets_mask_T_149 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_153; // @[DMA.scala:431:90] assign _write_packets_mask_T_153 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_157; // @[DMA.scala:431:90] assign _write_packets_mask_T_157 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_161; // @[DMA.scala:431:90] assign _write_packets_mask_T_161 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_165; // @[DMA.scala:431:90] assign _write_packets_mask_T_165 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_169; // @[DMA.scala:431:90] assign _write_packets_mask_T_169 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_173; // @[DMA.scala:431:90] assign _write_packets_mask_T_173 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_177; // @[DMA.scala:431:90] assign _write_packets_mask_T_177 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_181; // @[DMA.scala:431:90] assign _write_packets_mask_T_181 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_185; // @[DMA.scala:431:90] assign _write_packets_mask_T_185 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_189; // @[DMA.scala:431:90] assign _write_packets_mask_T_189 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_193; // @[DMA.scala:431:90] assign _write_packets_mask_T_193 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_197; // @[DMA.scala:431:90] assign _write_packets_mask_T_197 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_201; // @[DMA.scala:431:90] assign _write_packets_mask_T_201 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_205; // @[DMA.scala:431:90] assign _write_packets_mask_T_205 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_209; // @[DMA.scala:431:90] assign _write_packets_mask_T_209 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_213; // @[DMA.scala:431:90] assign _write_packets_mask_T_213 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_217; // @[DMA.scala:431:90] assign _write_packets_mask_T_217 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_221; // @[DMA.scala:431:90] assign _write_packets_mask_T_221 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_225; // @[DMA.scala:431:90] assign _write_packets_mask_T_225 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_229; // @[DMA.scala:431:90] assign _write_packets_mask_T_229 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_233; // @[DMA.scala:431:90] assign _write_packets_mask_T_233 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_237; // @[DMA.scala:431:90] assign _write_packets_mask_T_237 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_241; // @[DMA.scala:431:90] assign _write_packets_mask_T_241 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_245; // @[DMA.scala:431:90] assign _write_packets_mask_T_245 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_249; // @[DMA.scala:431:90] assign _write_packets_mask_T_249 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_253; // @[DMA.scala:431:90] assign _write_packets_mask_T_253 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T = _GEN_1; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T; // @[DMA.scala:453:44] assign _write_packets_right_shift_T = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_2; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_2 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_5; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_5 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T; // @[DMA.scala:458:37] assign _write_packets_too_late_T = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_8; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_8 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_10; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_10 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_13; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_13 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_1; // @[DMA.scala:458:37] assign _write_packets_too_late_T_1 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_16; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_16 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_18; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_18 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_21; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_21 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_2; // @[DMA.scala:458:37] assign _write_packets_too_late_T_2 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_24; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_24 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_26; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_26 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_29; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_29 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_3; // @[DMA.scala:458:37] assign _write_packets_too_late_T_3 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_2 = |_write_packets_mask_T_1; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_3 = _write_packets_mask_T & _write_packets_mask_T_2; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0 = _write_packets_mask_T_3; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_0 = write_packets_mask_0; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_4 = write_packets_vaddr_offset < 4'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_6 = |(_write_packets_mask_T_5[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_7 = _write_packets_mask_T_4 & _write_packets_mask_T_6; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1 = _write_packets_mask_T_7; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_1 = write_packets_mask_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_8 = write_packets_vaddr_offset < 4'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_10 = _write_packets_mask_T_9 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_11 = _write_packets_mask_T_8 & _write_packets_mask_T_10; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2 = _write_packets_mask_T_11; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_2 = write_packets_mask_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_12 = write_packets_vaddr_offset < 4'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_14 = |(_write_packets_mask_T_13[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_15 = _write_packets_mask_T_12 & _write_packets_mask_T_14; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3 = _write_packets_mask_T_15; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_3 = write_packets_mask_3; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_16 = write_packets_vaddr_offset < 4'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_18 = _write_packets_mask_T_17 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_19 = _write_packets_mask_T_16 & _write_packets_mask_T_18; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4 = _write_packets_mask_T_19; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_4 = write_packets_mask_4; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_20 = write_packets_vaddr_offset < 4'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_22 = _write_packets_mask_T_21 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_23 = _write_packets_mask_T_20 & _write_packets_mask_T_22; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5 = _write_packets_mask_T_23; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5 = write_packets_mask_5; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_24 = write_packets_vaddr_offset < 4'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_26 = _write_packets_mask_T_25 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_27 = _write_packets_mask_T_24 & _write_packets_mask_T_26; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6 = _write_packets_mask_T_27; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6 = write_packets_mask_6; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_28 = ~(write_packets_vaddr_offset[3]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_30 = |(_write_packets_mask_T_29[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_31 = _write_packets_mask_T_28 & _write_packets_mask_T_30; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7 = _write_packets_mask_T_31; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_7 = write_packets_mask_7; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_32 = write_packets_vaddr_offset < 4'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_34 = _write_packets_mask_T_33 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_35 = _write_packets_mask_T_32 & _write_packets_mask_T_34; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8 = _write_packets_mask_T_35; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_8 = write_packets_mask_8; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_36 = write_packets_vaddr_offset < 4'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_38 = _write_packets_mask_T_37 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_39 = _write_packets_mask_T_36 & _write_packets_mask_T_38; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9 = _write_packets_mask_T_39; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_9 = write_packets_mask_9; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_40 = write_packets_vaddr_offset < 4'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_42 = _write_packets_mask_T_41 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_43 = _write_packets_mask_T_40 & _write_packets_mask_T_42; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10 = _write_packets_mask_T_43; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10 = write_packets_mask_10; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_44 = write_packets_vaddr_offset[3:2] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_46 = _write_packets_mask_T_45 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_47 = _write_packets_mask_T_44 & _write_packets_mask_T_46; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11 = _write_packets_mask_T_47; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11 = write_packets_mask_11; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_48 = write_packets_vaddr_offset < 4'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_50 = _write_packets_mask_T_49 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_51 = _write_packets_mask_T_48 & _write_packets_mask_T_50; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12 = _write_packets_mask_T_51; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12 = write_packets_mask_12; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_52 = write_packets_vaddr_offset[3:1] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_54 = _write_packets_mask_T_53 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_55 = _write_packets_mask_T_52 & _write_packets_mask_T_54; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13 = _write_packets_mask_T_55; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13 = write_packets_mask_13; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_56 = write_packets_vaddr_offset != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_58 = _write_packets_mask_T_57 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_59 = _write_packets_mask_T_56 & _write_packets_mask_T_58; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14 = _write_packets_mask_T_59; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_14 = write_packets_mask_14; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_62 = |(_write_packets_mask_T_61[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_63 = _write_packets_mask_T_62; // @[DMA.scala:431:{68,75}] wire write_packets_mask_15 = _write_packets_mask_T_63; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_15 = write_packets_mask_15; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_66 = _write_packets_mask_T_65 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_67 = _write_packets_mask_T_66; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_70 = _write_packets_mask_T_69 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_71 = _write_packets_mask_T_70; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_74 = _write_packets_mask_T_73 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_75 = _write_packets_mask_T_74; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_78 = _write_packets_mask_T_77 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_79 = _write_packets_mask_T_78; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_82 = _write_packets_mask_T_81 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_83 = _write_packets_mask_T_82; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_86 = _write_packets_mask_T_85 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_87 = _write_packets_mask_T_86; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_90 = _write_packets_mask_T_89 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_91 = _write_packets_mask_T_90; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_94 = _write_packets_mask_T_93 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_95 = _write_packets_mask_T_94; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_98 = _write_packets_mask_T_97 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_99 = _write_packets_mask_T_98; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_102 = _write_packets_mask_T_101 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_103 = _write_packets_mask_T_102; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_106 = _write_packets_mask_T_105 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_107 = _write_packets_mask_T_106; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_110 = _write_packets_mask_T_109 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_111 = _write_packets_mask_T_110; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_114 = _write_packets_mask_T_113 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_115 = _write_packets_mask_T_114; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_118 = _write_packets_mask_T_117 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_119 = _write_packets_mask_T_118; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_122 = _write_packets_mask_T_121 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_123 = _write_packets_mask_T_122; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_126 = |(_write_packets_mask_T_125[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_127 = _write_packets_mask_T_126; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_130 = _write_packets_mask_T_129 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_131 = _write_packets_mask_T_130; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_134 = _write_packets_mask_T_133 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_135 = _write_packets_mask_T_134; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_138 = _write_packets_mask_T_137 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_139 = _write_packets_mask_T_138; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_142 = _write_packets_mask_T_141 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_143 = _write_packets_mask_T_142; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_146 = _write_packets_mask_T_145 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_147 = _write_packets_mask_T_146; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_150 = _write_packets_mask_T_149 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_151 = _write_packets_mask_T_150; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_154 = _write_packets_mask_T_153 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_155 = _write_packets_mask_T_154; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_158 = _write_packets_mask_T_157 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_159 = _write_packets_mask_T_158; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_162 = _write_packets_mask_T_161 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_163 = _write_packets_mask_T_162; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_166 = _write_packets_mask_T_165 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_167 = _write_packets_mask_T_166; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_170 = _write_packets_mask_T_169 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_171 = _write_packets_mask_T_170; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_174 = _write_packets_mask_T_173 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_175 = _write_packets_mask_T_174; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_178 = _write_packets_mask_T_177 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_179 = _write_packets_mask_T_178; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_182 = _write_packets_mask_T_181 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_183 = _write_packets_mask_T_182; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_186 = _write_packets_mask_T_185 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_187 = _write_packets_mask_T_186; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_190 = _write_packets_mask_T_189 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_191 = _write_packets_mask_T_190; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_194 = _write_packets_mask_T_193 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_195 = _write_packets_mask_T_194; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_198 = _write_packets_mask_T_197 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_199 = _write_packets_mask_T_198; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_202 = _write_packets_mask_T_201 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_203 = _write_packets_mask_T_202; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_206 = _write_packets_mask_T_205 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_207 = _write_packets_mask_T_206; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_210 = _write_packets_mask_T_209 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_211 = _write_packets_mask_T_210; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_214 = _write_packets_mask_T_213 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_215 = _write_packets_mask_T_214; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_218 = _write_packets_mask_T_217 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_219 = _write_packets_mask_T_218; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_222 = _write_packets_mask_T_221 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_223 = _write_packets_mask_T_222; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_226 = _write_packets_mask_T_225 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_227 = _write_packets_mask_T_226; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_230 = _write_packets_mask_T_229 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_231 = _write_packets_mask_T_230; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_234 = _write_packets_mask_T_233 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_235 = _write_packets_mask_T_234; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_238 = _write_packets_mask_T_237 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_239 = _write_packets_mask_T_238; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_242 = _write_packets_mask_T_241 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_243 = _write_packets_mask_T_242; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_246 = _write_packets_mask_T_245 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_247 = _write_packets_mask_T_246; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_250 = _write_packets_mask_T_249 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_251 = _write_packets_mask_T_250; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_254 = |(_write_packets_mask_T_253[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_255 = _write_packets_mask_T_254; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_1 = _write_packets_bytes_written_T > 8'h10; // @[DMA.scala:434:{26,39}] wire [5:0] _GEN_2 = {2'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :434:50] wire [5:0] _write_packets_bytes_written_T_2 = 6'h10 - _GEN_2; // @[DMA.scala:434:50] wire [4:0] _write_packets_bytes_written_T_3 = _write_packets_bytes_written_T_2[4:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written = _write_packets_bytes_written_T_1 ? {2'h0, _write_packets_bytes_written_T_3} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_0_bytes_written = write_packets_bytes_written; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_4_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_14; // @[DMA.scala:442:47] wire write_packets_0_mask_0_0; // @[DMA.scala:437:24] wire write_packets_0_mask_0_1; // @[DMA.scala:437:24] wire write_packets_0_mask_0_2; // @[DMA.scala:437:24] wire write_packets_0_mask_0_3; // @[DMA.scala:437:24] wire write_packets_0_mask_0_4; // @[DMA.scala:437:24] wire write_packets_0_mask_0_5; // @[DMA.scala:437:24] wire write_packets_0_mask_0_6; // @[DMA.scala:437:24] wire write_packets_0_mask_0_7; // @[DMA.scala:437:24] wire write_packets_0_mask_0_8; // @[DMA.scala:437:24] wire write_packets_0_mask_0_9; // @[DMA.scala:437:24] wire write_packets_0_mask_0_10; // @[DMA.scala:437:24] wire write_packets_0_mask_0_11; // @[DMA.scala:437:24] wire write_packets_0_mask_0_12; // @[DMA.scala:437:24] wire write_packets_0_mask_0_13; // @[DMA.scala:437:24] wire write_packets_0_mask_0_14; // @[DMA.scala:437:24] wire write_packets_0_mask_0_15; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_0_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_4_0_0 = _write_packets_WIRE_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_1 = _write_packets_WIRE_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_2 = _write_packets_WIRE_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_3 = _write_packets_WIRE_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_4 = _write_packets_WIRE_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_5 = _write_packets_WIRE_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_6 = _write_packets_WIRE_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_7 = _write_packets_WIRE_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_8 = _write_packets_WIRE_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_9 = _write_packets_WIRE_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_10 = _write_packets_WIRE_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_11 = _write_packets_WIRE_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_12 = _write_packets_WIRE_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_13 = _write_packets_WIRE_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_14 = _write_packets_WIRE_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_15 = _write_packets_WIRE_15; // @[DMA.scala:440:{29,70}] assign write_packets_0_mask_0_0 = _write_packets_WIRE_4_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_1 = _write_packets_WIRE_4_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_2 = _write_packets_WIRE_4_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_3 = _write_packets_WIRE_4_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_4 = _write_packets_WIRE_4_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_5 = _write_packets_WIRE_4_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_6 = _write_packets_WIRE_4_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_7 = _write_packets_WIRE_4_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_8 = _write_packets_WIRE_4_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_9 = _write_packets_WIRE_4_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_10 = _write_packets_WIRE_4_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_11 = _write_packets_WIRE_4_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_12 = _write_packets_WIRE_4_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_13 = _write_packets_WIRE_4_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_14 = _write_packets_WIRE_4_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_15 = _write_packets_WIRE_4_0_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T = write_packets_mask_0 & write_packets_mask_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_1 = _write_packets_packet_is_full_T & write_packets_mask_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_2 = _write_packets_packet_is_full_T_1 & write_packets_mask_3; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_3 = _write_packets_packet_is_full_T_2 & write_packets_mask_4; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_4 = _write_packets_packet_is_full_T_3 & write_packets_mask_5; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_5 = _write_packets_packet_is_full_T_4 & write_packets_mask_6; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_6 = _write_packets_packet_is_full_T_5 & write_packets_mask_7; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_7 = _write_packets_packet_is_full_T_6 & write_packets_mask_8; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_8 = _write_packets_packet_is_full_T_7 & write_packets_mask_9; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_9 = _write_packets_packet_is_full_T_8 & write_packets_mask_10; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_10 = _write_packets_packet_is_full_T_9 & write_packets_mask_11; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_11 = _write_packets_packet_is_full_T_10 & write_packets_mask_12; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_12 = _write_packets_packet_is_full_T_11 & write_packets_mask_13; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_13 = _write_packets_packet_is_full_T_12 & write_packets_mask_14; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_14 = _write_packets_packet_is_full_T_13 & write_packets_mask_15; // @[DMA.scala:431:103, :442:47] assign write_packets_0_is_full = _write_packets_packet_is_full_T_14; // @[DMA.scala:437:24, :442:47] wire [4:0] _write_packets_left_shift_T_3 = {1'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [3:0] _write_packets_left_shift_T_4 = _write_packets_left_shift_T_3[3:0]; // @[DMA.scala:450:24] wire [3:0] write_packets_left_shift = _write_packets_left_shift_T_4; // @[DMA.scala:449:29, :450:24] wire _write_packets_right_shift_T_3 = _write_packets_right_shift_T_2 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_4 = _write_packets_right_shift_T_3; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_6 = 9'h10 - {1'h0, _write_packets_right_shift_T_5}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_7 = _write_packets_right_shift_T_6[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift = _write_packets_right_shift_T_4 ? _write_packets_right_shift_T_7 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late = _write_packets_too_late_T == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T = write_packets_too_late; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_1 = {5'h0, write_packets_left_shift} + {1'h0, write_packets_right_shift}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_3 = _write_packets_packet_bytes_written_per_beat_0_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_4 = _write_packets_packet_bytes_written_per_beat_0_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [5:0] _write_packets_left_shift_T_8 = _GEN_2 - 6'h10; // @[DMA.scala:434:50, :450:24] wire [4:0] _write_packets_left_shift_T_9 = _write_packets_left_shift_T_8[4:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_9 = |(_write_packets_right_shift_T_8[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_11 = _write_packets_right_shift_T_10 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_12 = _write_packets_right_shift_T_9 & _write_packets_right_shift_T_11; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_14 = 9'h20 - {1'h0, _write_packets_right_shift_T_13}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_15 = _write_packets_right_shift_T_14[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_1 = _write_packets_right_shift_T_12 ? _write_packets_right_shift_T_15 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_1 = _write_packets_too_late_T_1 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T = write_packets_too_late_1; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_1 = {1'h0, write_packets_right_shift_1}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_3 = _write_packets_packet_bytes_written_per_beat_1_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_4 = _write_packets_packet_bytes_written_per_beat_1_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _GEN_3 = {3'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [6:0] _write_packets_left_shift_T_13 = _GEN_3 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_14 = _write_packets_left_shift_T_13[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_17 = |(_write_packets_right_shift_T_16[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_19 = _write_packets_right_shift_T_18 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_20 = _write_packets_right_shift_T_17 & _write_packets_right_shift_T_19; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_22 = 9'h30 - {1'h0, _write_packets_right_shift_T_21}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_23 = _write_packets_right_shift_T_22[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_2 = _write_packets_right_shift_T_20 ? _write_packets_right_shift_T_23 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_2 = _write_packets_too_late_T_2 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T = write_packets_too_late_2; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_1 = {1'h0, write_packets_right_shift_2}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_3 = _write_packets_packet_bytes_written_per_beat_2_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_4 = _write_packets_packet_bytes_written_per_beat_2_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_18 = _GEN_3 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_19 = _write_packets_left_shift_T_18[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_25 = _write_packets_right_shift_T_24 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_27 = _write_packets_right_shift_T_26 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_28 = _write_packets_right_shift_T_25 & _write_packets_right_shift_T_27; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_30 = 9'h40 - {1'h0, _write_packets_right_shift_T_29}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_31 = _write_packets_right_shift_T_30[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_3 = _write_packets_right_shift_T_28 ? _write_packets_right_shift_T_31 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_3 = _write_packets_too_late_T_3 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T = write_packets_too_late_3; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_1 = {1'h0, write_packets_right_shift_3}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_3 = _write_packets_packet_bytes_written_per_beat_3_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_4 = _write_packets_packet_bytes_written_per_beat_3_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [33:0] _write_packets_vaddr_aligned_to_size_T_1 = req_vaddr[38:5]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_1 = {_write_packets_vaddr_aligned_to_size_T_1, 5'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_1_vaddr = write_packets_vaddr_aligned_to_size_1; // @[DMA.scala:428:61, :437:24] wire [4:0] write_packets_vaddr_offset_1 = req_vaddr[4:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_256 = write_packets_vaddr_offset_1 == 5'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_4 = {3'h0, write_packets_vaddr_offset_1} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_257; // @[DMA.scala:431:90] assign _write_packets_mask_T_257 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_261; // @[DMA.scala:431:90] assign _write_packets_mask_T_261 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_265; // @[DMA.scala:431:90] assign _write_packets_mask_T_265 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_269; // @[DMA.scala:431:90] assign _write_packets_mask_T_269 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_273; // @[DMA.scala:431:90] assign _write_packets_mask_T_273 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_277; // @[DMA.scala:431:90] assign _write_packets_mask_T_277 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_281; // @[DMA.scala:431:90] assign _write_packets_mask_T_281 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_285; // @[DMA.scala:431:90] assign _write_packets_mask_T_285 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_289; // @[DMA.scala:431:90] assign _write_packets_mask_T_289 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_293; // @[DMA.scala:431:90] assign _write_packets_mask_T_293 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_297; // @[DMA.scala:431:90] assign _write_packets_mask_T_297 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_301; // @[DMA.scala:431:90] assign _write_packets_mask_T_301 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_305; // @[DMA.scala:431:90] assign _write_packets_mask_T_305 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_309; // @[DMA.scala:431:90] assign _write_packets_mask_T_309 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_313; // @[DMA.scala:431:90] assign _write_packets_mask_T_313 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_317; // @[DMA.scala:431:90] assign _write_packets_mask_T_317 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_321; // @[DMA.scala:431:90] assign _write_packets_mask_T_321 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_325; // @[DMA.scala:431:90] assign _write_packets_mask_T_325 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_329; // @[DMA.scala:431:90] assign _write_packets_mask_T_329 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_333; // @[DMA.scala:431:90] assign _write_packets_mask_T_333 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_337; // @[DMA.scala:431:90] assign _write_packets_mask_T_337 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_341; // @[DMA.scala:431:90] assign _write_packets_mask_T_341 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_345; // @[DMA.scala:431:90] assign _write_packets_mask_T_345 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_349; // @[DMA.scala:431:90] assign _write_packets_mask_T_349 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_353; // @[DMA.scala:431:90] assign _write_packets_mask_T_353 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_357; // @[DMA.scala:431:90] assign _write_packets_mask_T_357 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_361; // @[DMA.scala:431:90] assign _write_packets_mask_T_361 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_365; // @[DMA.scala:431:90] assign _write_packets_mask_T_365 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_369; // @[DMA.scala:431:90] assign _write_packets_mask_T_369 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_373; // @[DMA.scala:431:90] assign _write_packets_mask_T_373 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_377; // @[DMA.scala:431:90] assign _write_packets_mask_T_377 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_381; // @[DMA.scala:431:90] assign _write_packets_mask_T_381 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_385; // @[DMA.scala:431:90] assign _write_packets_mask_T_385 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_389; // @[DMA.scala:431:90] assign _write_packets_mask_T_389 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_393; // @[DMA.scala:431:90] assign _write_packets_mask_T_393 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_397; // @[DMA.scala:431:90] assign _write_packets_mask_T_397 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_401; // @[DMA.scala:431:90] assign _write_packets_mask_T_401 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_405; // @[DMA.scala:431:90] assign _write_packets_mask_T_405 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_409; // @[DMA.scala:431:90] assign _write_packets_mask_T_409 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_413; // @[DMA.scala:431:90] assign _write_packets_mask_T_413 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_417; // @[DMA.scala:431:90] assign _write_packets_mask_T_417 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_421; // @[DMA.scala:431:90] assign _write_packets_mask_T_421 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_425; // @[DMA.scala:431:90] assign _write_packets_mask_T_425 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_429; // @[DMA.scala:431:90] assign _write_packets_mask_T_429 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_433; // @[DMA.scala:431:90] assign _write_packets_mask_T_433 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_437; // @[DMA.scala:431:90] assign _write_packets_mask_T_437 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_441; // @[DMA.scala:431:90] assign _write_packets_mask_T_441 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_445; // @[DMA.scala:431:90] assign _write_packets_mask_T_445 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_449; // @[DMA.scala:431:90] assign _write_packets_mask_T_449 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_453; // @[DMA.scala:431:90] assign _write_packets_mask_T_453 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_457; // @[DMA.scala:431:90] assign _write_packets_mask_T_457 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_461; // @[DMA.scala:431:90] assign _write_packets_mask_T_461 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_465; // @[DMA.scala:431:90] assign _write_packets_mask_T_465 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_469; // @[DMA.scala:431:90] assign _write_packets_mask_T_469 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_473; // @[DMA.scala:431:90] assign _write_packets_mask_T_473 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_477; // @[DMA.scala:431:90] assign _write_packets_mask_T_477 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_481; // @[DMA.scala:431:90] assign _write_packets_mask_T_481 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_485; // @[DMA.scala:431:90] assign _write_packets_mask_T_485 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_489; // @[DMA.scala:431:90] assign _write_packets_mask_T_489 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_493; // @[DMA.scala:431:90] assign _write_packets_mask_T_493 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_497; // @[DMA.scala:431:90] assign _write_packets_mask_T_497 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_501; // @[DMA.scala:431:90] assign _write_packets_mask_T_501 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_505; // @[DMA.scala:431:90] assign _write_packets_mask_T_505 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_509; // @[DMA.scala:431:90] assign _write_packets_mask_T_509 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_4; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_4 = _GEN_4; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_32; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_32 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_34; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_34 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_37; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_37 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_4; // @[DMA.scala:458:37] assign _write_packets_too_late_T_4 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_40; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_40 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_42; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_42 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_45; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_45 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_5; // @[DMA.scala:458:37] assign _write_packets_too_late_T_5 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_48; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_48 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_50; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_50 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_53; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_53 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_6; // @[DMA.scala:458:37] assign _write_packets_too_late_T_6 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_56; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_56 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_58; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_58 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_61; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_61 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_7; // @[DMA.scala:458:37] assign _write_packets_too_late_T_7 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_258 = |_write_packets_mask_T_257; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_259 = _write_packets_mask_T_256 & _write_packets_mask_T_258; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_1 = _write_packets_mask_T_259; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_0 = write_packets_mask_0_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_260 = write_packets_vaddr_offset_1 < 5'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_262 = |(_write_packets_mask_T_261[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_263 = _write_packets_mask_T_260 & _write_packets_mask_T_262; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_1 = _write_packets_mask_T_263; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_1 = write_packets_mask_1_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_264 = write_packets_vaddr_offset_1 < 5'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_266 = _write_packets_mask_T_265 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_267 = _write_packets_mask_T_264 & _write_packets_mask_T_266; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_1 = _write_packets_mask_T_267; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_2 = write_packets_mask_2_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_268 = write_packets_vaddr_offset_1 < 5'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_270 = |(_write_packets_mask_T_269[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_271 = _write_packets_mask_T_268 & _write_packets_mask_T_270; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_1 = _write_packets_mask_T_271; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_3 = write_packets_mask_3_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_272 = write_packets_vaddr_offset_1 < 5'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_274 = _write_packets_mask_T_273 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_275 = _write_packets_mask_T_272 & _write_packets_mask_T_274; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_1 = _write_packets_mask_T_275; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_4 = write_packets_mask_4_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_276 = write_packets_vaddr_offset_1 < 5'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_278 = _write_packets_mask_T_277 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_279 = _write_packets_mask_T_276 & _write_packets_mask_T_278; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_1 = _write_packets_mask_T_279; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_5 = write_packets_mask_5_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_280 = write_packets_vaddr_offset_1 < 5'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_282 = _write_packets_mask_T_281 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_283 = _write_packets_mask_T_280 & _write_packets_mask_T_282; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_1 = _write_packets_mask_T_283; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_6 = write_packets_mask_6_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_284 = write_packets_vaddr_offset_1 < 5'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_286 = |(_write_packets_mask_T_285[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_287 = _write_packets_mask_T_284 & _write_packets_mask_T_286; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_1 = _write_packets_mask_T_287; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_7 = write_packets_mask_7_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_288 = write_packets_vaddr_offset_1 < 5'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_290 = _write_packets_mask_T_289 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_291 = _write_packets_mask_T_288 & _write_packets_mask_T_290; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_1 = _write_packets_mask_T_291; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_8 = write_packets_mask_8_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_292 = write_packets_vaddr_offset_1 < 5'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_294 = _write_packets_mask_T_293 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_295 = _write_packets_mask_T_292 & _write_packets_mask_T_294; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_1 = _write_packets_mask_T_295; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_9 = write_packets_mask_9_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_296 = write_packets_vaddr_offset_1 < 5'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_298 = _write_packets_mask_T_297 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_299 = _write_packets_mask_T_296 & _write_packets_mask_T_298; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_1 = _write_packets_mask_T_299; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_10 = write_packets_mask_10_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_300 = write_packets_vaddr_offset_1 < 5'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_302 = _write_packets_mask_T_301 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_303 = _write_packets_mask_T_300 & _write_packets_mask_T_302; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_1 = _write_packets_mask_T_303; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_11 = write_packets_mask_11_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_304 = write_packets_vaddr_offset_1 < 5'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_306 = _write_packets_mask_T_305 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_307 = _write_packets_mask_T_304 & _write_packets_mask_T_306; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_1 = _write_packets_mask_T_307; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_12 = write_packets_mask_12_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_308 = write_packets_vaddr_offset_1 < 5'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_310 = _write_packets_mask_T_309 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_311 = _write_packets_mask_T_308 & _write_packets_mask_T_310; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_1 = _write_packets_mask_T_311; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_13 = write_packets_mask_13_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_312 = write_packets_vaddr_offset_1 < 5'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_314 = _write_packets_mask_T_313 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_315 = _write_packets_mask_T_312 & _write_packets_mask_T_314; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_1 = _write_packets_mask_T_315; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_14 = write_packets_mask_14_1; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_4 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_25 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_316 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_318 = |(_write_packets_mask_T_317[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_319 = _write_packets_mask_T_316 & _write_packets_mask_T_318; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_1 = _write_packets_mask_T_319; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_15 = write_packets_mask_15_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_320 = write_packets_vaddr_offset_1 < 5'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_322 = _write_packets_mask_T_321 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_323 = _write_packets_mask_T_320 & _write_packets_mask_T_322; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_1 = _write_packets_mask_T_323; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_0 = write_packets_mask_16_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_324 = write_packets_vaddr_offset_1 < 5'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_326 = _write_packets_mask_T_325 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_327 = _write_packets_mask_T_324 & _write_packets_mask_T_326; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_1 = _write_packets_mask_T_327; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_1 = write_packets_mask_17_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_328 = write_packets_vaddr_offset_1 < 5'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_330 = _write_packets_mask_T_329 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_331 = _write_packets_mask_T_328 & _write_packets_mask_T_330; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_1 = _write_packets_mask_T_331; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_2 = write_packets_mask_18_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_332 = write_packets_vaddr_offset_1 < 5'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_334 = _write_packets_mask_T_333 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_335 = _write_packets_mask_T_332 & _write_packets_mask_T_334; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_1 = _write_packets_mask_T_335; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_3 = write_packets_mask_19_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_336 = write_packets_vaddr_offset_1 < 5'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_338 = _write_packets_mask_T_337 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_339 = _write_packets_mask_T_336 & _write_packets_mask_T_338; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_1 = _write_packets_mask_T_339; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_4 = write_packets_mask_20_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_340 = write_packets_vaddr_offset_1 < 5'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_342 = _write_packets_mask_T_341 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_343 = _write_packets_mask_T_340 & _write_packets_mask_T_342; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_1 = _write_packets_mask_T_343; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_5 = write_packets_mask_21_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_344 = write_packets_vaddr_offset_1 < 5'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_346 = _write_packets_mask_T_345 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_347 = _write_packets_mask_T_344 & _write_packets_mask_T_346; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_1 = _write_packets_mask_T_347; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_6 = write_packets_mask_22_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_348 = write_packets_vaddr_offset_1[4:3] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_350 = _write_packets_mask_T_349 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_351 = _write_packets_mask_T_348 & _write_packets_mask_T_350; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_1 = _write_packets_mask_T_351; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_7 = write_packets_mask_23_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_352 = write_packets_vaddr_offset_1 < 5'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_354 = _write_packets_mask_T_353 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_355 = _write_packets_mask_T_352 & _write_packets_mask_T_354; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_1 = _write_packets_mask_T_355; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_8 = write_packets_mask_24_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_356 = write_packets_vaddr_offset_1 < 5'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_358 = _write_packets_mask_T_357 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_359 = _write_packets_mask_T_356 & _write_packets_mask_T_358; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_1 = _write_packets_mask_T_359; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_9 = write_packets_mask_25_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_360 = write_packets_vaddr_offset_1 < 5'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_362 = _write_packets_mask_T_361 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_363 = _write_packets_mask_T_360 & _write_packets_mask_T_362; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_1 = _write_packets_mask_T_363; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_10 = write_packets_mask_26_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_364 = write_packets_vaddr_offset_1[4:2] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_366 = _write_packets_mask_T_365 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_367 = _write_packets_mask_T_364 & _write_packets_mask_T_366; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_1 = _write_packets_mask_T_367; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_11 = write_packets_mask_27_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_368 = write_packets_vaddr_offset_1 < 5'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_370 = _write_packets_mask_T_369 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_371 = _write_packets_mask_T_368 & _write_packets_mask_T_370; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_1 = _write_packets_mask_T_371; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_12 = write_packets_mask_28_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_372 = write_packets_vaddr_offset_1[4:1] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_374 = _write_packets_mask_T_373 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_375 = _write_packets_mask_T_372 & _write_packets_mask_T_374; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_1 = _write_packets_mask_T_375; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_13 = write_packets_mask_29_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_376 = write_packets_vaddr_offset_1 != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_378 = _write_packets_mask_T_377 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_379 = _write_packets_mask_T_376 & _write_packets_mask_T_378; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_1 = _write_packets_mask_T_379; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_14 = write_packets_mask_30_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_382 = |(_write_packets_mask_T_381[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_383 = _write_packets_mask_T_382; // @[DMA.scala:431:{68,75}] wire write_packets_mask_31_1 = _write_packets_mask_T_383; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_15 = write_packets_mask_31_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_386 = _write_packets_mask_T_385 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_387 = _write_packets_mask_T_386; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_390 = _write_packets_mask_T_389 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_391 = _write_packets_mask_T_390; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_394 = _write_packets_mask_T_393 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_395 = _write_packets_mask_T_394; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_398 = _write_packets_mask_T_397 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_399 = _write_packets_mask_T_398; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_402 = _write_packets_mask_T_401 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_403 = _write_packets_mask_T_402; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_406 = _write_packets_mask_T_405 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_407 = _write_packets_mask_T_406; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_410 = _write_packets_mask_T_409 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_411 = _write_packets_mask_T_410; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_414 = _write_packets_mask_T_413 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_415 = _write_packets_mask_T_414; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_418 = _write_packets_mask_T_417 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_419 = _write_packets_mask_T_418; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_422 = _write_packets_mask_T_421 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_423 = _write_packets_mask_T_422; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_426 = _write_packets_mask_T_425 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_427 = _write_packets_mask_T_426; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_430 = _write_packets_mask_T_429 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_431 = _write_packets_mask_T_430; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_434 = _write_packets_mask_T_433 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_435 = _write_packets_mask_T_434; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_438 = _write_packets_mask_T_437 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_439 = _write_packets_mask_T_438; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_442 = _write_packets_mask_T_441 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_443 = _write_packets_mask_T_442; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_446 = _write_packets_mask_T_445 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_447 = _write_packets_mask_T_446; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_450 = _write_packets_mask_T_449 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_451 = _write_packets_mask_T_450; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_454 = _write_packets_mask_T_453 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_455 = _write_packets_mask_T_454; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_458 = _write_packets_mask_T_457 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_459 = _write_packets_mask_T_458; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_462 = _write_packets_mask_T_461 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_463 = _write_packets_mask_T_462; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_466 = _write_packets_mask_T_465 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_467 = _write_packets_mask_T_466; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_470 = _write_packets_mask_T_469 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_471 = _write_packets_mask_T_470; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_474 = _write_packets_mask_T_473 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_475 = _write_packets_mask_T_474; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_478 = _write_packets_mask_T_477 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_479 = _write_packets_mask_T_478; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_482 = _write_packets_mask_T_481 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_483 = _write_packets_mask_T_482; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_486 = _write_packets_mask_T_485 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_487 = _write_packets_mask_T_486; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_490 = _write_packets_mask_T_489 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_491 = _write_packets_mask_T_490; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_494 = _write_packets_mask_T_493 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_495 = _write_packets_mask_T_494; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_498 = _write_packets_mask_T_497 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_499 = _write_packets_mask_T_498; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_502 = _write_packets_mask_T_501 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_503 = _write_packets_mask_T_502; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_506 = _write_packets_mask_T_505 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_507 = _write_packets_mask_T_506; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_510 = |(_write_packets_mask_T_509[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_511 = _write_packets_mask_T_510; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_5 = _write_packets_bytes_written_T_4 > 8'h20; // @[DMA.scala:434:{26,39}] wire [6:0] _GEN_5 = {2'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :434:50] wire [6:0] _write_packets_bytes_written_T_6 = 7'h20 - _GEN_5; // @[DMA.scala:434:50] wire [5:0] _write_packets_bytes_written_T_7 = _write_packets_bytes_written_T_6[5:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_1 = _write_packets_bytes_written_T_5 ? {1'h0, _write_packets_bytes_written_T_7} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_1_bytes_written = write_packets_bytes_written_1; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_9_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_45; // @[DMA.scala:442:47] wire write_packets_1_mask_0_0; // @[DMA.scala:437:24] wire write_packets_1_mask_0_1; // @[DMA.scala:437:24] wire write_packets_1_mask_0_2; // @[DMA.scala:437:24] wire write_packets_1_mask_0_3; // @[DMA.scala:437:24] wire write_packets_1_mask_0_4; // @[DMA.scala:437:24] wire write_packets_1_mask_0_5; // @[DMA.scala:437:24] wire write_packets_1_mask_0_6; // @[DMA.scala:437:24] wire write_packets_1_mask_0_7; // @[DMA.scala:437:24] wire write_packets_1_mask_0_8; // @[DMA.scala:437:24] wire write_packets_1_mask_0_9; // @[DMA.scala:437:24] wire write_packets_1_mask_0_10; // @[DMA.scala:437:24] wire write_packets_1_mask_0_11; // @[DMA.scala:437:24] wire write_packets_1_mask_0_12; // @[DMA.scala:437:24] wire write_packets_1_mask_0_13; // @[DMA.scala:437:24] wire write_packets_1_mask_0_14; // @[DMA.scala:437:24] wire write_packets_1_mask_0_15; // @[DMA.scala:437:24] wire write_packets_1_mask_1_0; // @[DMA.scala:437:24] wire write_packets_1_mask_1_1; // @[DMA.scala:437:24] wire write_packets_1_mask_1_2; // @[DMA.scala:437:24] wire write_packets_1_mask_1_3; // @[DMA.scala:437:24] wire write_packets_1_mask_1_4; // @[DMA.scala:437:24] wire write_packets_1_mask_1_5; // @[DMA.scala:437:24] wire write_packets_1_mask_1_6; // @[DMA.scala:437:24] wire write_packets_1_mask_1_7; // @[DMA.scala:437:24] wire write_packets_1_mask_1_8; // @[DMA.scala:437:24] wire write_packets_1_mask_1_9; // @[DMA.scala:437:24] wire write_packets_1_mask_1_10; // @[DMA.scala:437:24] wire write_packets_1_mask_1_11; // @[DMA.scala:437:24] wire write_packets_1_mask_1_12; // @[DMA.scala:437:24] wire write_packets_1_mask_1_13; // @[DMA.scala:437:24] wire write_packets_1_mask_1_14; // @[DMA.scala:437:24] wire write_packets_1_mask_1_15; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_1_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_9_0_0 = _write_packets_WIRE_5_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_1 = _write_packets_WIRE_5_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_2 = _write_packets_WIRE_5_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_3 = _write_packets_WIRE_5_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_4 = _write_packets_WIRE_5_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_5 = _write_packets_WIRE_5_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_6 = _write_packets_WIRE_5_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_7 = _write_packets_WIRE_5_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_8 = _write_packets_WIRE_5_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_9 = _write_packets_WIRE_5_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_10 = _write_packets_WIRE_5_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_11 = _write_packets_WIRE_5_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_12 = _write_packets_WIRE_5_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_13 = _write_packets_WIRE_5_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_14 = _write_packets_WIRE_5_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_15 = _write_packets_WIRE_5_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_0 = _write_packets_WIRE_6_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_1 = _write_packets_WIRE_6_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_2 = _write_packets_WIRE_6_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_3 = _write_packets_WIRE_6_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_4 = _write_packets_WIRE_6_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_5 = _write_packets_WIRE_6_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_6 = _write_packets_WIRE_6_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_7 = _write_packets_WIRE_6_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_8 = _write_packets_WIRE_6_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_9 = _write_packets_WIRE_6_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_10 = _write_packets_WIRE_6_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_11 = _write_packets_WIRE_6_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_12 = _write_packets_WIRE_6_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_13 = _write_packets_WIRE_6_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_14 = _write_packets_WIRE_6_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_15 = _write_packets_WIRE_6_15; // @[DMA.scala:440:{29,70}] assign write_packets_1_mask_0_0 = _write_packets_WIRE_9_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_1 = _write_packets_WIRE_9_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_2 = _write_packets_WIRE_9_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_3 = _write_packets_WIRE_9_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_4 = _write_packets_WIRE_9_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_5 = _write_packets_WIRE_9_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_6 = _write_packets_WIRE_9_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_7 = _write_packets_WIRE_9_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_8 = _write_packets_WIRE_9_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_9 = _write_packets_WIRE_9_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_10 = _write_packets_WIRE_9_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_11 = _write_packets_WIRE_9_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_12 = _write_packets_WIRE_9_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_13 = _write_packets_WIRE_9_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_14 = _write_packets_WIRE_9_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_15 = _write_packets_WIRE_9_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_0 = _write_packets_WIRE_9_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_1 = _write_packets_WIRE_9_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_2 = _write_packets_WIRE_9_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_3 = _write_packets_WIRE_9_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_4 = _write_packets_WIRE_9_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_5 = _write_packets_WIRE_9_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_6 = _write_packets_WIRE_9_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_7 = _write_packets_WIRE_9_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_8 = _write_packets_WIRE_9_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_9 = _write_packets_WIRE_9_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_10 = _write_packets_WIRE_9_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_11 = _write_packets_WIRE_9_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_12 = _write_packets_WIRE_9_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_13 = _write_packets_WIRE_9_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_14 = _write_packets_WIRE_9_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_15 = _write_packets_WIRE_9_1_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_15 = write_packets_mask_0_1 & write_packets_mask_1_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_16 = _write_packets_packet_is_full_T_15 & write_packets_mask_2_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_17 = _write_packets_packet_is_full_T_16 & write_packets_mask_3_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_18 = _write_packets_packet_is_full_T_17 & write_packets_mask_4_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_19 = _write_packets_packet_is_full_T_18 & write_packets_mask_5_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_20 = _write_packets_packet_is_full_T_19 & write_packets_mask_6_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_21 = _write_packets_packet_is_full_T_20 & write_packets_mask_7_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_22 = _write_packets_packet_is_full_T_21 & write_packets_mask_8_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_23 = _write_packets_packet_is_full_T_22 & write_packets_mask_9_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_24 = _write_packets_packet_is_full_T_23 & write_packets_mask_10_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_25 = _write_packets_packet_is_full_T_24 & write_packets_mask_11_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_26 = _write_packets_packet_is_full_T_25 & write_packets_mask_12_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_27 = _write_packets_packet_is_full_T_26 & write_packets_mask_13_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_28 = _write_packets_packet_is_full_T_27 & write_packets_mask_14_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_29 = _write_packets_packet_is_full_T_28 & write_packets_mask_15_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_30 = _write_packets_packet_is_full_T_29 & write_packets_mask_16_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_31 = _write_packets_packet_is_full_T_30 & write_packets_mask_17_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_32 = _write_packets_packet_is_full_T_31 & write_packets_mask_18_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_33 = _write_packets_packet_is_full_T_32 & write_packets_mask_19_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_34 = _write_packets_packet_is_full_T_33 & write_packets_mask_20_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_35 = _write_packets_packet_is_full_T_34 & write_packets_mask_21_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_36 = _write_packets_packet_is_full_T_35 & write_packets_mask_22_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_37 = _write_packets_packet_is_full_T_36 & write_packets_mask_23_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_38 = _write_packets_packet_is_full_T_37 & write_packets_mask_24_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_39 = _write_packets_packet_is_full_T_38 & write_packets_mask_25_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_40 = _write_packets_packet_is_full_T_39 & write_packets_mask_26_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_41 = _write_packets_packet_is_full_T_40 & write_packets_mask_27_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_42 = _write_packets_packet_is_full_T_41 & write_packets_mask_28_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_43 = _write_packets_packet_is_full_T_42 & write_packets_mask_29_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_44 = _write_packets_packet_is_full_T_43 & write_packets_mask_30_1; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_45 = _write_packets_packet_is_full_T_44 & write_packets_mask_31_1; // @[DMA.scala:431:103, :442:47] assign write_packets_1_is_full = _write_packets_packet_is_full_T_45; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_21 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_22 = _write_packets_left_shift_T_21; // @[DMA.scala:449:{62,78}] wire [5:0] _write_packets_left_shift_T_23 = {1'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :450:24] wire [4:0] _write_packets_left_shift_T_24 = _write_packets_left_shift_T_23[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_4 = _write_packets_left_shift_T_22 ? _write_packets_left_shift_T_24 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_35 = _write_packets_right_shift_T_34 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_36 = _write_packets_right_shift_T_35; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_38 = 9'h10 - {1'h0, _write_packets_right_shift_T_37}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_39 = _write_packets_right_shift_T_38[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_4 = _write_packets_right_shift_T_36 ? _write_packets_right_shift_T_39 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_4 = _write_packets_too_late_T_4 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_5 = write_packets_too_early_4 | write_packets_too_late_4; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_6 = {4'h0, write_packets_left_shift_4} + {1'h0, write_packets_right_shift_4}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_8 = _write_packets_packet_bytes_written_per_beat_0_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_9 = _write_packets_packet_bytes_written_per_beat_0_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_27 = _write_packets_left_shift_T_25; // @[DMA.scala:449:{43,62}] wire [5:0] _write_packets_left_shift_T_28 = _write_packets_left_shift_T_23 - 6'h10; // @[DMA.scala:450:24] wire [4:0] _write_packets_left_shift_T_29 = _write_packets_left_shift_T_28[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_5 = _write_packets_left_shift_T_27 ? _write_packets_left_shift_T_29 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_41 = |(_write_packets_right_shift_T_40[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_43 = _write_packets_right_shift_T_42 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_44 = _write_packets_right_shift_T_41 & _write_packets_right_shift_T_43; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_46 = 9'h20 - {1'h0, _write_packets_right_shift_T_45}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_47 = _write_packets_right_shift_T_46[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_5 = _write_packets_right_shift_T_44 ? _write_packets_right_shift_T_47 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_5 = _write_packets_too_late_T_5 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_5 = write_packets_too_late_5; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_6 = {4'h0, write_packets_left_shift_5} + {1'h0, write_packets_right_shift_5}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_8 = _write_packets_packet_bytes_written_per_beat_1_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_9 = _write_packets_packet_bytes_written_per_beat_1_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_33 = _GEN_5 - 7'h20; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_34 = _write_packets_left_shift_T_33[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_49 = |(_write_packets_right_shift_T_48[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_51 = _write_packets_right_shift_T_50 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_52 = _write_packets_right_shift_T_49 & _write_packets_right_shift_T_51; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_54 = 9'h30 - {1'h0, _write_packets_right_shift_T_53}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_55 = _write_packets_right_shift_T_54[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_6 = _write_packets_right_shift_T_52 ? _write_packets_right_shift_T_55 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_6 = _write_packets_too_late_T_6 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_5 = write_packets_too_late_6; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_6 = {1'h0, write_packets_right_shift_6}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_8 = _write_packets_packet_bytes_written_per_beat_2_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_9 = _write_packets_packet_bytes_written_per_beat_2_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_38 = _GEN_5 - 7'h30; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_39 = _write_packets_left_shift_T_38[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_57 = _write_packets_right_shift_T_56 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_59 = _write_packets_right_shift_T_58 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_60 = _write_packets_right_shift_T_57 & _write_packets_right_shift_T_59; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_62 = 9'h40 - {1'h0, _write_packets_right_shift_T_61}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_63 = _write_packets_right_shift_T_62[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_7 = _write_packets_right_shift_T_60 ? _write_packets_right_shift_T_63 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_7 = _write_packets_too_late_T_7 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_5 = write_packets_too_late_7; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_6 = {1'h0, write_packets_right_shift_7}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_8 = _write_packets_packet_bytes_written_per_beat_3_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_9 = _write_packets_packet_bytes_written_per_beat_3_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [32:0] _write_packets_vaddr_aligned_to_size_T_2 = req_vaddr[38:6]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_2 = {_write_packets_vaddr_aligned_to_size_T_2, 6'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_2_vaddr = write_packets_vaddr_aligned_to_size_2; // @[DMA.scala:428:61, :437:24] wire [5:0] write_packets_vaddr_offset_2 = req_vaddr[5:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_512 = write_packets_vaddr_offset_2 == 6'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_6 = {2'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :431:90] wire [7:0] _GEN_7 = _GEN_6 + _GEN_0; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_513; // @[DMA.scala:431:90] assign _write_packets_mask_T_513 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_517; // @[DMA.scala:431:90] assign _write_packets_mask_T_517 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_521; // @[DMA.scala:431:90] assign _write_packets_mask_T_521 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_525; // @[DMA.scala:431:90] assign _write_packets_mask_T_525 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_529; // @[DMA.scala:431:90] assign _write_packets_mask_T_529 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_533; // @[DMA.scala:431:90] assign _write_packets_mask_T_533 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_537; // @[DMA.scala:431:90] assign _write_packets_mask_T_537 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_541; // @[DMA.scala:431:90] assign _write_packets_mask_T_541 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_545; // @[DMA.scala:431:90] assign _write_packets_mask_T_545 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_549; // @[DMA.scala:431:90] assign _write_packets_mask_T_549 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_553; // @[DMA.scala:431:90] assign _write_packets_mask_T_553 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_557; // @[DMA.scala:431:90] assign _write_packets_mask_T_557 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_561; // @[DMA.scala:431:90] assign _write_packets_mask_T_561 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_565; // @[DMA.scala:431:90] assign _write_packets_mask_T_565 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_569; // @[DMA.scala:431:90] assign _write_packets_mask_T_569 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_573; // @[DMA.scala:431:90] assign _write_packets_mask_T_573 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_577; // @[DMA.scala:431:90] assign _write_packets_mask_T_577 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_581; // @[DMA.scala:431:90] assign _write_packets_mask_T_581 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_585; // @[DMA.scala:431:90] assign _write_packets_mask_T_585 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_589; // @[DMA.scala:431:90] assign _write_packets_mask_T_589 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_593; // @[DMA.scala:431:90] assign _write_packets_mask_T_593 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_597; // @[DMA.scala:431:90] assign _write_packets_mask_T_597 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_601; // @[DMA.scala:431:90] assign _write_packets_mask_T_601 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_605; // @[DMA.scala:431:90] assign _write_packets_mask_T_605 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_609; // @[DMA.scala:431:90] assign _write_packets_mask_T_609 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_613; // @[DMA.scala:431:90] assign _write_packets_mask_T_613 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_617; // @[DMA.scala:431:90] assign _write_packets_mask_T_617 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_621; // @[DMA.scala:431:90] assign _write_packets_mask_T_621 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_625; // @[DMA.scala:431:90] assign _write_packets_mask_T_625 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_629; // @[DMA.scala:431:90] assign _write_packets_mask_T_629 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_633; // @[DMA.scala:431:90] assign _write_packets_mask_T_633 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_637; // @[DMA.scala:431:90] assign _write_packets_mask_T_637 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_641; // @[DMA.scala:431:90] assign _write_packets_mask_T_641 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_645; // @[DMA.scala:431:90] assign _write_packets_mask_T_645 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_649; // @[DMA.scala:431:90] assign _write_packets_mask_T_649 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_653; // @[DMA.scala:431:90] assign _write_packets_mask_T_653 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_657; // @[DMA.scala:431:90] assign _write_packets_mask_T_657 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_661; // @[DMA.scala:431:90] assign _write_packets_mask_T_661 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_665; // @[DMA.scala:431:90] assign _write_packets_mask_T_665 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_669; // @[DMA.scala:431:90] assign _write_packets_mask_T_669 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_673; // @[DMA.scala:431:90] assign _write_packets_mask_T_673 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_677; // @[DMA.scala:431:90] assign _write_packets_mask_T_677 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_681; // @[DMA.scala:431:90] assign _write_packets_mask_T_681 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_685; // @[DMA.scala:431:90] assign _write_packets_mask_T_685 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_689; // @[DMA.scala:431:90] assign _write_packets_mask_T_689 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_693; // @[DMA.scala:431:90] assign _write_packets_mask_T_693 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_697; // @[DMA.scala:431:90] assign _write_packets_mask_T_697 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_701; // @[DMA.scala:431:90] assign _write_packets_mask_T_701 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_705; // @[DMA.scala:431:90] assign _write_packets_mask_T_705 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_709; // @[DMA.scala:431:90] assign _write_packets_mask_T_709 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_713; // @[DMA.scala:431:90] assign _write_packets_mask_T_713 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_717; // @[DMA.scala:431:90] assign _write_packets_mask_T_717 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_721; // @[DMA.scala:431:90] assign _write_packets_mask_T_721 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_725; // @[DMA.scala:431:90] assign _write_packets_mask_T_725 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_729; // @[DMA.scala:431:90] assign _write_packets_mask_T_729 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_733; // @[DMA.scala:431:90] assign _write_packets_mask_T_733 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_737; // @[DMA.scala:431:90] assign _write_packets_mask_T_737 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_741; // @[DMA.scala:431:90] assign _write_packets_mask_T_741 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_745; // @[DMA.scala:431:90] assign _write_packets_mask_T_745 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_749; // @[DMA.scala:431:90] assign _write_packets_mask_T_749 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_753; // @[DMA.scala:431:90] assign _write_packets_mask_T_753 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_757; // @[DMA.scala:431:90] assign _write_packets_mask_T_757 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_761; // @[DMA.scala:431:90] assign _write_packets_mask_T_761 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_765; // @[DMA.scala:431:90] assign _write_packets_mask_T_765 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_8; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_8 = _GEN_7; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_64; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_64 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_66; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_66 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_69; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_69 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_8; // @[DMA.scala:458:37] assign _write_packets_too_late_T_8 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_72; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_72 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_74; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_74 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_77; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_77 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_9; // @[DMA.scala:458:37] assign _write_packets_too_late_T_9 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_80; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_80 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_82; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_82 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_85; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_85 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_10; // @[DMA.scala:458:37] assign _write_packets_too_late_T_10 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_88; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_88 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_90; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_90 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_93; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_93 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_11; // @[DMA.scala:458:37] assign _write_packets_too_late_T_11 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_514 = |_write_packets_mask_T_513; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_515 = _write_packets_mask_T_512 & _write_packets_mask_T_514; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_2 = _write_packets_mask_T_515; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_0 = write_packets_mask_0_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_516 = write_packets_vaddr_offset_2 < 6'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_518 = |(_write_packets_mask_T_517[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_519 = _write_packets_mask_T_516 & _write_packets_mask_T_518; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_2 = _write_packets_mask_T_519; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_1 = write_packets_mask_1_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_520 = write_packets_vaddr_offset_2 < 6'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_522 = _write_packets_mask_T_521 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_523 = _write_packets_mask_T_520 & _write_packets_mask_T_522; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_2 = _write_packets_mask_T_523; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_2 = write_packets_mask_2_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_524 = write_packets_vaddr_offset_2 < 6'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_526 = |(_write_packets_mask_T_525[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_527 = _write_packets_mask_T_524 & _write_packets_mask_T_526; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_2 = _write_packets_mask_T_527; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_3 = write_packets_mask_3_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_528 = write_packets_vaddr_offset_2 < 6'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_530 = _write_packets_mask_T_529 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_531 = _write_packets_mask_T_528 & _write_packets_mask_T_530; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_2 = _write_packets_mask_T_531; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_4 = write_packets_mask_4_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_532 = write_packets_vaddr_offset_2 < 6'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_534 = _write_packets_mask_T_533 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_535 = _write_packets_mask_T_532 & _write_packets_mask_T_534; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_2 = _write_packets_mask_T_535; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_5 = write_packets_mask_5_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_536 = write_packets_vaddr_offset_2 < 6'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_538 = _write_packets_mask_T_537 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_539 = _write_packets_mask_T_536 & _write_packets_mask_T_538; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_2 = _write_packets_mask_T_539; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_6 = write_packets_mask_6_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_540 = write_packets_vaddr_offset_2 < 6'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_542 = |(_write_packets_mask_T_541[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_543 = _write_packets_mask_T_540 & _write_packets_mask_T_542; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_2 = _write_packets_mask_T_543; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_7 = write_packets_mask_7_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_544 = write_packets_vaddr_offset_2 < 6'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_546 = _write_packets_mask_T_545 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_547 = _write_packets_mask_T_544 & _write_packets_mask_T_546; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_2 = _write_packets_mask_T_547; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_8 = write_packets_mask_8_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_548 = write_packets_vaddr_offset_2 < 6'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_550 = _write_packets_mask_T_549 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_551 = _write_packets_mask_T_548 & _write_packets_mask_T_550; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_2 = _write_packets_mask_T_551; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_9 = write_packets_mask_9_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_552 = write_packets_vaddr_offset_2 < 6'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_554 = _write_packets_mask_T_553 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_555 = _write_packets_mask_T_552 & _write_packets_mask_T_554; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_2 = _write_packets_mask_T_555; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_10 = write_packets_mask_10_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_556 = write_packets_vaddr_offset_2 < 6'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_558 = _write_packets_mask_T_557 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_559 = _write_packets_mask_T_556 & _write_packets_mask_T_558; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_2 = _write_packets_mask_T_559; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_11 = write_packets_mask_11_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_560 = write_packets_vaddr_offset_2 < 6'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_562 = _write_packets_mask_T_561 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_563 = _write_packets_mask_T_560 & _write_packets_mask_T_562; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_2 = _write_packets_mask_T_563; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_12 = write_packets_mask_12_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_564 = write_packets_vaddr_offset_2 < 6'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_566 = _write_packets_mask_T_565 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_567 = _write_packets_mask_T_564 & _write_packets_mask_T_566; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_2 = _write_packets_mask_T_567; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_13 = write_packets_mask_13_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_568 = write_packets_vaddr_offset_2 < 6'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_570 = _write_packets_mask_T_569 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_571 = _write_packets_mask_T_568 & _write_packets_mask_T_570; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_2 = _write_packets_mask_T_571; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_14 = write_packets_mask_14_2; // @[DMA.scala:431:103, :440:70] wire _GEN_8 = write_packets_vaddr_offset_2 < 6'h10; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_572; // @[DMA.scala:431:52] assign _write_packets_mask_T_572 = _GEN_8; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_41; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_41 = _GEN_8; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_574 = |(_write_packets_mask_T_573[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_575 = _write_packets_mask_T_572 & _write_packets_mask_T_574; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_2 = _write_packets_mask_T_575; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_15 = write_packets_mask_15_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_576 = write_packets_vaddr_offset_2 < 6'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_578 = _write_packets_mask_T_577 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_579 = _write_packets_mask_T_576 & _write_packets_mask_T_578; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_2 = _write_packets_mask_T_579; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_0 = write_packets_mask_16_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_580 = write_packets_vaddr_offset_2 < 6'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_582 = _write_packets_mask_T_581 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_583 = _write_packets_mask_T_580 & _write_packets_mask_T_582; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_2 = _write_packets_mask_T_583; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_1 = write_packets_mask_17_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_584 = write_packets_vaddr_offset_2 < 6'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_586 = _write_packets_mask_T_585 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_587 = _write_packets_mask_T_584 & _write_packets_mask_T_586; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_2 = _write_packets_mask_T_587; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_2 = write_packets_mask_18_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_588 = write_packets_vaddr_offset_2 < 6'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_590 = _write_packets_mask_T_589 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_591 = _write_packets_mask_T_588 & _write_packets_mask_T_590; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_2 = _write_packets_mask_T_591; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_3 = write_packets_mask_19_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_592 = write_packets_vaddr_offset_2 < 6'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_594 = _write_packets_mask_T_593 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_595 = _write_packets_mask_T_592 & _write_packets_mask_T_594; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_2 = _write_packets_mask_T_595; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_4 = write_packets_mask_20_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_596 = write_packets_vaddr_offset_2 < 6'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_598 = _write_packets_mask_T_597 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_599 = _write_packets_mask_T_596 & _write_packets_mask_T_598; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_2 = _write_packets_mask_T_599; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_5 = write_packets_mask_21_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_600 = write_packets_vaddr_offset_2 < 6'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_602 = _write_packets_mask_T_601 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_603 = _write_packets_mask_T_600 & _write_packets_mask_T_602; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_2 = _write_packets_mask_T_603; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_6 = write_packets_mask_22_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_604 = write_packets_vaddr_offset_2 < 6'h18; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_606 = _write_packets_mask_T_605 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_607 = _write_packets_mask_T_604 & _write_packets_mask_T_606; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_2 = _write_packets_mask_T_607; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_7 = write_packets_mask_23_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_608 = write_packets_vaddr_offset_2 < 6'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_610 = _write_packets_mask_T_609 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_611 = _write_packets_mask_T_608 & _write_packets_mask_T_610; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_2 = _write_packets_mask_T_611; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_8 = write_packets_mask_24_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_612 = write_packets_vaddr_offset_2 < 6'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_614 = _write_packets_mask_T_613 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_615 = _write_packets_mask_T_612 & _write_packets_mask_T_614; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_2 = _write_packets_mask_T_615; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_9 = write_packets_mask_25_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_616 = write_packets_vaddr_offset_2 < 6'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_618 = _write_packets_mask_T_617 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_619 = _write_packets_mask_T_616 & _write_packets_mask_T_618; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_2 = _write_packets_mask_T_619; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_10 = write_packets_mask_26_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_620 = write_packets_vaddr_offset_2 < 6'h1C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_622 = _write_packets_mask_T_621 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_623 = _write_packets_mask_T_620 & _write_packets_mask_T_622; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_2 = _write_packets_mask_T_623; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_11 = write_packets_mask_27_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_624 = write_packets_vaddr_offset_2 < 6'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_626 = _write_packets_mask_T_625 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_627 = _write_packets_mask_T_624 & _write_packets_mask_T_626; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_2 = _write_packets_mask_T_627; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_12 = write_packets_mask_28_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_628 = write_packets_vaddr_offset_2 < 6'h1E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_630 = _write_packets_mask_T_629 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_631 = _write_packets_mask_T_628 & _write_packets_mask_T_630; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_2 = _write_packets_mask_T_631; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_13 = write_packets_mask_29_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_632 = write_packets_vaddr_offset_2 < 6'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_634 = _write_packets_mask_T_633 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_635 = _write_packets_mask_T_632 & _write_packets_mask_T_634; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_2 = _write_packets_mask_T_635; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_14 = write_packets_mask_30_2; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_9 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_50 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_636 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_638 = |(_write_packets_mask_T_637[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_639 = _write_packets_mask_T_636 & _write_packets_mask_T_638; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_31_2 = _write_packets_mask_T_639; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_15 = write_packets_mask_31_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_640 = write_packets_vaddr_offset_2 < 6'h21; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_642 = _write_packets_mask_T_641 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_643 = _write_packets_mask_T_640 & _write_packets_mask_T_642; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_32_2 = _write_packets_mask_T_643; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_0 = write_packets_mask_32_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_644 = write_packets_vaddr_offset_2 < 6'h22; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_646 = _write_packets_mask_T_645 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_647 = _write_packets_mask_T_644 & _write_packets_mask_T_646; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_33_2 = _write_packets_mask_T_647; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_1 = write_packets_mask_33_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_648 = write_packets_vaddr_offset_2 < 6'h23; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_650 = _write_packets_mask_T_649 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_651 = _write_packets_mask_T_648 & _write_packets_mask_T_650; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_34_2 = _write_packets_mask_T_651; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_2 = write_packets_mask_34_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_652 = write_packets_vaddr_offset_2 < 6'h24; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_654 = _write_packets_mask_T_653 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_655 = _write_packets_mask_T_652 & _write_packets_mask_T_654; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_35_2 = _write_packets_mask_T_655; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_3 = write_packets_mask_35_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_656 = write_packets_vaddr_offset_2 < 6'h25; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_658 = _write_packets_mask_T_657 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_659 = _write_packets_mask_T_656 & _write_packets_mask_T_658; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_36_2 = _write_packets_mask_T_659; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_4 = write_packets_mask_36_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_660 = write_packets_vaddr_offset_2 < 6'h26; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_662 = _write_packets_mask_T_661 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_663 = _write_packets_mask_T_660 & _write_packets_mask_T_662; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_37_2 = _write_packets_mask_T_663; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_5 = write_packets_mask_37_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_664 = write_packets_vaddr_offset_2 < 6'h27; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_666 = _write_packets_mask_T_665 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_667 = _write_packets_mask_T_664 & _write_packets_mask_T_666; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_38_2 = _write_packets_mask_T_667; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_6 = write_packets_mask_38_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_668 = write_packets_vaddr_offset_2 < 6'h28; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_670 = _write_packets_mask_T_669 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_671 = _write_packets_mask_T_668 & _write_packets_mask_T_670; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_39_2 = _write_packets_mask_T_671; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_7 = write_packets_mask_39_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_672 = write_packets_vaddr_offset_2 < 6'h29; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_674 = _write_packets_mask_T_673 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_675 = _write_packets_mask_T_672 & _write_packets_mask_T_674; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_40_2 = _write_packets_mask_T_675; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_8 = write_packets_mask_40_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_676 = write_packets_vaddr_offset_2 < 6'h2A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_678 = _write_packets_mask_T_677 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_679 = _write_packets_mask_T_676 & _write_packets_mask_T_678; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_41_2 = _write_packets_mask_T_679; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_9 = write_packets_mask_41_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_680 = write_packets_vaddr_offset_2 < 6'h2B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_682 = _write_packets_mask_T_681 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_683 = _write_packets_mask_T_680 & _write_packets_mask_T_682; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_42_2 = _write_packets_mask_T_683; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_10 = write_packets_mask_42_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_684 = write_packets_vaddr_offset_2 < 6'h2C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_686 = _write_packets_mask_T_685 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_687 = _write_packets_mask_T_684 & _write_packets_mask_T_686; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_43_2 = _write_packets_mask_T_687; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_11 = write_packets_mask_43_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_688 = write_packets_vaddr_offset_2 < 6'h2D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_690 = _write_packets_mask_T_689 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_691 = _write_packets_mask_T_688 & _write_packets_mask_T_690; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_44_2 = _write_packets_mask_T_691; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_12 = write_packets_mask_44_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_692 = write_packets_vaddr_offset_2 < 6'h2E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_694 = _write_packets_mask_T_693 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_695 = _write_packets_mask_T_692 & _write_packets_mask_T_694; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_45_2 = _write_packets_mask_T_695; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_13 = write_packets_mask_45_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_696 = write_packets_vaddr_offset_2 < 6'h2F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_698 = _write_packets_mask_T_697 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_699 = _write_packets_mask_T_696 & _write_packets_mask_T_698; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_46_2 = _write_packets_mask_T_699; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_14 = write_packets_mask_46_2; // @[DMA.scala:431:103, :440:70] wire _GEN_9 = write_packets_vaddr_offset_2[5:4] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_700; // @[DMA.scala:431:52] assign _write_packets_mask_T_700 = _GEN_9; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_51; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_51 = _GEN_9; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_702 = _write_packets_mask_T_701 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_703 = _write_packets_mask_T_700 & _write_packets_mask_T_702; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_47_2 = _write_packets_mask_T_703; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_15 = write_packets_mask_47_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_704 = write_packets_vaddr_offset_2 < 6'h31; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_706 = _write_packets_mask_T_705 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_707 = _write_packets_mask_T_704 & _write_packets_mask_T_706; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_48_2 = _write_packets_mask_T_707; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_0 = write_packets_mask_48_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_708 = write_packets_vaddr_offset_2 < 6'h32; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_710 = _write_packets_mask_T_709 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_711 = _write_packets_mask_T_708 & _write_packets_mask_T_710; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_49_2 = _write_packets_mask_T_711; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_1 = write_packets_mask_49_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_712 = write_packets_vaddr_offset_2 < 6'h33; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_714 = _write_packets_mask_T_713 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_715 = _write_packets_mask_T_712 & _write_packets_mask_T_714; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_50_2 = _write_packets_mask_T_715; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_2 = write_packets_mask_50_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_716 = write_packets_vaddr_offset_2 < 6'h34; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_718 = _write_packets_mask_T_717 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_719 = _write_packets_mask_T_716 & _write_packets_mask_T_718; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_51_2 = _write_packets_mask_T_719; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_3 = write_packets_mask_51_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_720 = write_packets_vaddr_offset_2 < 6'h35; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_722 = _write_packets_mask_T_721 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_723 = _write_packets_mask_T_720 & _write_packets_mask_T_722; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_52_2 = _write_packets_mask_T_723; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_4 = write_packets_mask_52_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_724 = write_packets_vaddr_offset_2 < 6'h36; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_726 = _write_packets_mask_T_725 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_727 = _write_packets_mask_T_724 & _write_packets_mask_T_726; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_53_2 = _write_packets_mask_T_727; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_5 = write_packets_mask_53_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_728 = write_packets_vaddr_offset_2 < 6'h37; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_730 = _write_packets_mask_T_729 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_731 = _write_packets_mask_T_728 & _write_packets_mask_T_730; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_54_2 = _write_packets_mask_T_731; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_6 = write_packets_mask_54_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_732 = write_packets_vaddr_offset_2[5:3] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_734 = _write_packets_mask_T_733 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_735 = _write_packets_mask_T_732 & _write_packets_mask_T_734; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_55_2 = _write_packets_mask_T_735; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_7 = write_packets_mask_55_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_736 = write_packets_vaddr_offset_2 < 6'h39; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_738 = _write_packets_mask_T_737 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_739 = _write_packets_mask_T_736 & _write_packets_mask_T_738; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_56_2 = _write_packets_mask_T_739; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_8 = write_packets_mask_56_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_740 = write_packets_vaddr_offset_2 < 6'h3A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_742 = _write_packets_mask_T_741 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_743 = _write_packets_mask_T_740 & _write_packets_mask_T_742; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_57_2 = _write_packets_mask_T_743; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_9 = write_packets_mask_57_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_744 = write_packets_vaddr_offset_2 < 6'h3B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_746 = _write_packets_mask_T_745 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_747 = _write_packets_mask_T_744 & _write_packets_mask_T_746; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_58_2 = _write_packets_mask_T_747; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_10 = write_packets_mask_58_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_748 = write_packets_vaddr_offset_2[5:2] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_750 = _write_packets_mask_T_749 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_751 = _write_packets_mask_T_748 & _write_packets_mask_T_750; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_59_2 = _write_packets_mask_T_751; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_11 = write_packets_mask_59_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_752 = write_packets_vaddr_offset_2 < 6'h3D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_754 = _write_packets_mask_T_753 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_755 = _write_packets_mask_T_752 & _write_packets_mask_T_754; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_60_2 = _write_packets_mask_T_755; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_12 = write_packets_mask_60_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_756 = write_packets_vaddr_offset_2[5:1] != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_758 = _write_packets_mask_T_757 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_759 = _write_packets_mask_T_756 & _write_packets_mask_T_758; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_61_2 = _write_packets_mask_T_759; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_13 = write_packets_mask_61_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_760 = write_packets_vaddr_offset_2 != 6'h3F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_762 = _write_packets_mask_T_761 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_763 = _write_packets_mask_T_760 & _write_packets_mask_T_762; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_62_2 = _write_packets_mask_T_763; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_14 = write_packets_mask_62_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_766 = |(_write_packets_mask_T_765[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_767 = _write_packets_mask_T_766; // @[DMA.scala:431:{68,75}] wire write_packets_mask_63_2 = _write_packets_mask_T_767; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_15 = write_packets_mask_63_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_bytes_written_T_9 = _write_packets_bytes_written_T_8 > 8'h40; // @[DMA.scala:434:{26,39}] wire [7:0] _write_packets_bytes_written_T_10 = 8'h40 - _GEN_6; // @[DMA.scala:431:90, :434:50] wire [6:0] _write_packets_bytes_written_T_11 = _write_packets_bytes_written_T_10[6:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_2 = _write_packets_bytes_written_T_9 ? _write_packets_bytes_written_T_11 : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_2_bytes_written = write_packets_bytes_written_2; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_14_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_108; // @[DMA.scala:442:47] wire write_packets_2_mask_0_0; // @[DMA.scala:437:24] wire write_packets_2_mask_0_1; // @[DMA.scala:437:24] wire write_packets_2_mask_0_2; // @[DMA.scala:437:24] wire write_packets_2_mask_0_3; // @[DMA.scala:437:24] wire write_packets_2_mask_0_4; // @[DMA.scala:437:24] wire write_packets_2_mask_0_5; // @[DMA.scala:437:24] wire write_packets_2_mask_0_6; // @[DMA.scala:437:24] wire write_packets_2_mask_0_7; // @[DMA.scala:437:24] wire write_packets_2_mask_0_8; // @[DMA.scala:437:24] wire write_packets_2_mask_0_9; // @[DMA.scala:437:24] wire write_packets_2_mask_0_10; // @[DMA.scala:437:24] wire write_packets_2_mask_0_11; // @[DMA.scala:437:24] wire write_packets_2_mask_0_12; // @[DMA.scala:437:24] wire write_packets_2_mask_0_13; // @[DMA.scala:437:24] wire write_packets_2_mask_0_14; // @[DMA.scala:437:24] wire write_packets_2_mask_0_15; // @[DMA.scala:437:24] wire write_packets_2_mask_1_0; // @[DMA.scala:437:24] wire write_packets_2_mask_1_1; // @[DMA.scala:437:24] wire write_packets_2_mask_1_2; // @[DMA.scala:437:24] wire write_packets_2_mask_1_3; // @[DMA.scala:437:24] wire write_packets_2_mask_1_4; // @[DMA.scala:437:24] wire write_packets_2_mask_1_5; // @[DMA.scala:437:24] wire write_packets_2_mask_1_6; // @[DMA.scala:437:24] wire write_packets_2_mask_1_7; // @[DMA.scala:437:24] wire write_packets_2_mask_1_8; // @[DMA.scala:437:24] wire write_packets_2_mask_1_9; // @[DMA.scala:437:24] wire write_packets_2_mask_1_10; // @[DMA.scala:437:24] wire write_packets_2_mask_1_11; // @[DMA.scala:437:24] wire write_packets_2_mask_1_12; // @[DMA.scala:437:24] wire write_packets_2_mask_1_13; // @[DMA.scala:437:24] wire write_packets_2_mask_1_14; // @[DMA.scala:437:24] wire write_packets_2_mask_1_15; // @[DMA.scala:437:24] wire write_packets_2_mask_2_0; // @[DMA.scala:437:24] wire write_packets_2_mask_2_1; // @[DMA.scala:437:24] wire write_packets_2_mask_2_2; // @[DMA.scala:437:24] wire write_packets_2_mask_2_3; // @[DMA.scala:437:24] wire write_packets_2_mask_2_4; // @[DMA.scala:437:24] wire write_packets_2_mask_2_5; // @[DMA.scala:437:24] wire write_packets_2_mask_2_6; // @[DMA.scala:437:24] wire write_packets_2_mask_2_7; // @[DMA.scala:437:24] wire write_packets_2_mask_2_8; // @[DMA.scala:437:24] wire write_packets_2_mask_2_9; // @[DMA.scala:437:24] wire write_packets_2_mask_2_10; // @[DMA.scala:437:24] wire write_packets_2_mask_2_11; // @[DMA.scala:437:24] wire write_packets_2_mask_2_12; // @[DMA.scala:437:24] wire write_packets_2_mask_2_13; // @[DMA.scala:437:24] wire write_packets_2_mask_2_14; // @[DMA.scala:437:24] wire write_packets_2_mask_2_15; // @[DMA.scala:437:24] wire write_packets_2_mask_3_0; // @[DMA.scala:437:24] wire write_packets_2_mask_3_1; // @[DMA.scala:437:24] wire write_packets_2_mask_3_2; // @[DMA.scala:437:24] wire write_packets_2_mask_3_3; // @[DMA.scala:437:24] wire write_packets_2_mask_3_4; // @[DMA.scala:437:24] wire write_packets_2_mask_3_5; // @[DMA.scala:437:24] wire write_packets_2_mask_3_6; // @[DMA.scala:437:24] wire write_packets_2_mask_3_7; // @[DMA.scala:437:24] wire write_packets_2_mask_3_8; // @[DMA.scala:437:24] wire write_packets_2_mask_3_9; // @[DMA.scala:437:24] wire write_packets_2_mask_3_10; // @[DMA.scala:437:24] wire write_packets_2_mask_3_11; // @[DMA.scala:437:24] wire write_packets_2_mask_3_12; // @[DMA.scala:437:24] wire write_packets_2_mask_3_13; // @[DMA.scala:437:24] wire write_packets_2_mask_3_14; // @[DMA.scala:437:24] wire write_packets_2_mask_3_15; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_2_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_14_0_0 = _write_packets_WIRE_10_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_1 = _write_packets_WIRE_10_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_2 = _write_packets_WIRE_10_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_3 = _write_packets_WIRE_10_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_4 = _write_packets_WIRE_10_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_5 = _write_packets_WIRE_10_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_6 = _write_packets_WIRE_10_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_7 = _write_packets_WIRE_10_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_8 = _write_packets_WIRE_10_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_9 = _write_packets_WIRE_10_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_10 = _write_packets_WIRE_10_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_11 = _write_packets_WIRE_10_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_12 = _write_packets_WIRE_10_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_13 = _write_packets_WIRE_10_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_14 = _write_packets_WIRE_10_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_15 = _write_packets_WIRE_10_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_0 = _write_packets_WIRE_11_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_1 = _write_packets_WIRE_11_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_2 = _write_packets_WIRE_11_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_3 = _write_packets_WIRE_11_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_4 = _write_packets_WIRE_11_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_5 = _write_packets_WIRE_11_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_6 = _write_packets_WIRE_11_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_7 = _write_packets_WIRE_11_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_8 = _write_packets_WIRE_11_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_9 = _write_packets_WIRE_11_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_10 = _write_packets_WIRE_11_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_11 = _write_packets_WIRE_11_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_12 = _write_packets_WIRE_11_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_13 = _write_packets_WIRE_11_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_14 = _write_packets_WIRE_11_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_15 = _write_packets_WIRE_11_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_0 = _write_packets_WIRE_12_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_1 = _write_packets_WIRE_12_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_2 = _write_packets_WIRE_12_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_3 = _write_packets_WIRE_12_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_4 = _write_packets_WIRE_12_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_5 = _write_packets_WIRE_12_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_6 = _write_packets_WIRE_12_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_7 = _write_packets_WIRE_12_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_8 = _write_packets_WIRE_12_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_9 = _write_packets_WIRE_12_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_10 = _write_packets_WIRE_12_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_11 = _write_packets_WIRE_12_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_12 = _write_packets_WIRE_12_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_13 = _write_packets_WIRE_12_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_14 = _write_packets_WIRE_12_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_15 = _write_packets_WIRE_12_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_0 = _write_packets_WIRE_13_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_1 = _write_packets_WIRE_13_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_2 = _write_packets_WIRE_13_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_3 = _write_packets_WIRE_13_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_4 = _write_packets_WIRE_13_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_5 = _write_packets_WIRE_13_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_6 = _write_packets_WIRE_13_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_7 = _write_packets_WIRE_13_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_8 = _write_packets_WIRE_13_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_9 = _write_packets_WIRE_13_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_10 = _write_packets_WIRE_13_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_11 = _write_packets_WIRE_13_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_12 = _write_packets_WIRE_13_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_13 = _write_packets_WIRE_13_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_14 = _write_packets_WIRE_13_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_15 = _write_packets_WIRE_13_15; // @[DMA.scala:440:{29,70}] assign write_packets_2_mask_0_0 = _write_packets_WIRE_14_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_1 = _write_packets_WIRE_14_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_2 = _write_packets_WIRE_14_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_3 = _write_packets_WIRE_14_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_4 = _write_packets_WIRE_14_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_5 = _write_packets_WIRE_14_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_6 = _write_packets_WIRE_14_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_7 = _write_packets_WIRE_14_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_8 = _write_packets_WIRE_14_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_9 = _write_packets_WIRE_14_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_10 = _write_packets_WIRE_14_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_11 = _write_packets_WIRE_14_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_12 = _write_packets_WIRE_14_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_13 = _write_packets_WIRE_14_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_14 = _write_packets_WIRE_14_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_15 = _write_packets_WIRE_14_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_0 = _write_packets_WIRE_14_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_1 = _write_packets_WIRE_14_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_2 = _write_packets_WIRE_14_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_3 = _write_packets_WIRE_14_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_4 = _write_packets_WIRE_14_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_5 = _write_packets_WIRE_14_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_6 = _write_packets_WIRE_14_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_7 = _write_packets_WIRE_14_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_8 = _write_packets_WIRE_14_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_9 = _write_packets_WIRE_14_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_10 = _write_packets_WIRE_14_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_11 = _write_packets_WIRE_14_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_12 = _write_packets_WIRE_14_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_13 = _write_packets_WIRE_14_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_14 = _write_packets_WIRE_14_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_15 = _write_packets_WIRE_14_1_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_0 = _write_packets_WIRE_14_2_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_1 = _write_packets_WIRE_14_2_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_2 = _write_packets_WIRE_14_2_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_3 = _write_packets_WIRE_14_2_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_4 = _write_packets_WIRE_14_2_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_5 = _write_packets_WIRE_14_2_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_6 = _write_packets_WIRE_14_2_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_7 = _write_packets_WIRE_14_2_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_8 = _write_packets_WIRE_14_2_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_9 = _write_packets_WIRE_14_2_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_10 = _write_packets_WIRE_14_2_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_11 = _write_packets_WIRE_14_2_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_12 = _write_packets_WIRE_14_2_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_13 = _write_packets_WIRE_14_2_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_14 = _write_packets_WIRE_14_2_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_15 = _write_packets_WIRE_14_2_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_0 = _write_packets_WIRE_14_3_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_1 = _write_packets_WIRE_14_3_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_2 = _write_packets_WIRE_14_3_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_3 = _write_packets_WIRE_14_3_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_4 = _write_packets_WIRE_14_3_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_5 = _write_packets_WIRE_14_3_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_6 = _write_packets_WIRE_14_3_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_7 = _write_packets_WIRE_14_3_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_8 = _write_packets_WIRE_14_3_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_9 = _write_packets_WIRE_14_3_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_10 = _write_packets_WIRE_14_3_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_11 = _write_packets_WIRE_14_3_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_12 = _write_packets_WIRE_14_3_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_13 = _write_packets_WIRE_14_3_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_14 = _write_packets_WIRE_14_3_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_15 = _write_packets_WIRE_14_3_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_46 = write_packets_mask_0_2 & write_packets_mask_1_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_47 = _write_packets_packet_is_full_T_46 & write_packets_mask_2_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_48 = _write_packets_packet_is_full_T_47 & write_packets_mask_3_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_49 = _write_packets_packet_is_full_T_48 & write_packets_mask_4_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_50 = _write_packets_packet_is_full_T_49 & write_packets_mask_5_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_51 = _write_packets_packet_is_full_T_50 & write_packets_mask_6_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_52 = _write_packets_packet_is_full_T_51 & write_packets_mask_7_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_53 = _write_packets_packet_is_full_T_52 & write_packets_mask_8_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_54 = _write_packets_packet_is_full_T_53 & write_packets_mask_9_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_55 = _write_packets_packet_is_full_T_54 & write_packets_mask_10_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_56 = _write_packets_packet_is_full_T_55 & write_packets_mask_11_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_57 = _write_packets_packet_is_full_T_56 & write_packets_mask_12_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_58 = _write_packets_packet_is_full_T_57 & write_packets_mask_13_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_59 = _write_packets_packet_is_full_T_58 & write_packets_mask_14_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_60 = _write_packets_packet_is_full_T_59 & write_packets_mask_15_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_61 = _write_packets_packet_is_full_T_60 & write_packets_mask_16_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_62 = _write_packets_packet_is_full_T_61 & write_packets_mask_17_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_63 = _write_packets_packet_is_full_T_62 & write_packets_mask_18_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_64 = _write_packets_packet_is_full_T_63 & write_packets_mask_19_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_65 = _write_packets_packet_is_full_T_64 & write_packets_mask_20_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_66 = _write_packets_packet_is_full_T_65 & write_packets_mask_21_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_67 = _write_packets_packet_is_full_T_66 & write_packets_mask_22_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_68 = _write_packets_packet_is_full_T_67 & write_packets_mask_23_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_69 = _write_packets_packet_is_full_T_68 & write_packets_mask_24_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_70 = _write_packets_packet_is_full_T_69 & write_packets_mask_25_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_71 = _write_packets_packet_is_full_T_70 & write_packets_mask_26_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_72 = _write_packets_packet_is_full_T_71 & write_packets_mask_27_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_73 = _write_packets_packet_is_full_T_72 & write_packets_mask_28_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_74 = _write_packets_packet_is_full_T_73 & write_packets_mask_29_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_75 = _write_packets_packet_is_full_T_74 & write_packets_mask_30_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_76 = _write_packets_packet_is_full_T_75 & write_packets_mask_31_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_77 = _write_packets_packet_is_full_T_76 & write_packets_mask_32_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_78 = _write_packets_packet_is_full_T_77 & write_packets_mask_33_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_79 = _write_packets_packet_is_full_T_78 & write_packets_mask_34_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_80 = _write_packets_packet_is_full_T_79 & write_packets_mask_35_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_81 = _write_packets_packet_is_full_T_80 & write_packets_mask_36_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_82 = _write_packets_packet_is_full_T_81 & write_packets_mask_37_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_83 = _write_packets_packet_is_full_T_82 & write_packets_mask_38_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_84 = _write_packets_packet_is_full_T_83 & write_packets_mask_39_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_85 = _write_packets_packet_is_full_T_84 & write_packets_mask_40_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_86 = _write_packets_packet_is_full_T_85 & write_packets_mask_41_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_87 = _write_packets_packet_is_full_T_86 & write_packets_mask_42_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_88 = _write_packets_packet_is_full_T_87 & write_packets_mask_43_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_89 = _write_packets_packet_is_full_T_88 & write_packets_mask_44_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_90 = _write_packets_packet_is_full_T_89 & write_packets_mask_45_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_91 = _write_packets_packet_is_full_T_90 & write_packets_mask_46_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_92 = _write_packets_packet_is_full_T_91 & write_packets_mask_47_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_93 = _write_packets_packet_is_full_T_92 & write_packets_mask_48_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_94 = _write_packets_packet_is_full_T_93 & write_packets_mask_49_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_95 = _write_packets_packet_is_full_T_94 & write_packets_mask_50_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_96 = _write_packets_packet_is_full_T_95 & write_packets_mask_51_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_97 = _write_packets_packet_is_full_T_96 & write_packets_mask_52_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_98 = _write_packets_packet_is_full_T_97 & write_packets_mask_53_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_99 = _write_packets_packet_is_full_T_98 & write_packets_mask_54_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_100 = _write_packets_packet_is_full_T_99 & write_packets_mask_55_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_101 = _write_packets_packet_is_full_T_100 & write_packets_mask_56_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_102 = _write_packets_packet_is_full_T_101 & write_packets_mask_57_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_103 = _write_packets_packet_is_full_T_102 & write_packets_mask_58_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_104 = _write_packets_packet_is_full_T_103 & write_packets_mask_59_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_105 = _write_packets_packet_is_full_T_104 & write_packets_mask_60_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_106 = _write_packets_packet_is_full_T_105 & write_packets_mask_61_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_107 = _write_packets_packet_is_full_T_106 & write_packets_mask_62_2; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_108 = _write_packets_packet_is_full_T_107 & write_packets_mask_63_2; // @[DMA.scala:431:103, :442:47] assign write_packets_2_is_full = _write_packets_packet_is_full_T_108; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_42 = _write_packets_left_shift_T_41; // @[DMA.scala:449:{62,78}] wire [6:0] _write_packets_left_shift_T_43 = {1'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :450:24] wire [5:0] _write_packets_left_shift_T_44 = _write_packets_left_shift_T_43[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_8 = _write_packets_left_shift_T_42 ? _write_packets_left_shift_T_44 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_67 = _write_packets_right_shift_T_66 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_68 = _write_packets_right_shift_T_67; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_70 = 9'h10 - {1'h0, _write_packets_right_shift_T_69}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_71 = _write_packets_right_shift_T_70[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_8 = _write_packets_right_shift_T_68 ? _write_packets_right_shift_T_71 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_early_8 = |(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :457:38] wire write_packets_too_late_8 = _write_packets_too_late_T_8 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_10 = write_packets_too_early_8 | write_packets_too_late_8; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_11 = {3'h0, write_packets_left_shift_8} + {1'h0, write_packets_right_shift_8}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_13 = _write_packets_packet_bytes_written_per_beat_0_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_14 = _write_packets_packet_bytes_written_per_beat_0_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_45 = |(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :449:43, :457:38] wire _write_packets_left_shift_T_46 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_47 = _write_packets_left_shift_T_45 & _write_packets_left_shift_T_46; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_48 = _write_packets_left_shift_T_43 - 7'h10; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_49 = _write_packets_left_shift_T_48[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_9 = _write_packets_left_shift_T_47 ? _write_packets_left_shift_T_49 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_73 = |(_write_packets_right_shift_T_72[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_75 = _write_packets_right_shift_T_74 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_76 = _write_packets_right_shift_T_73 & _write_packets_right_shift_T_75; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_78 = 9'h20 - {1'h0, _write_packets_right_shift_T_77}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_79 = _write_packets_right_shift_T_78[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_9 = _write_packets_right_shift_T_76 ? _write_packets_right_shift_T_79 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_9 = _write_packets_too_late_T_9 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_10 = write_packets_too_early_9 | write_packets_too_late_9; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_11 = {3'h0, write_packets_left_shift_9} + {1'h0, write_packets_right_shift_9}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_13 = _write_packets_packet_bytes_written_per_beat_1_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_14 = _write_packets_packet_bytes_written_per_beat_1_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_52 = _write_packets_left_shift_T_50 & _write_packets_left_shift_T_51; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_53 = _write_packets_left_shift_T_43 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_54 = _write_packets_left_shift_T_53[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_10 = _write_packets_left_shift_T_52 ? _write_packets_left_shift_T_54 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_81 = |(_write_packets_right_shift_T_80[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_83 = _write_packets_right_shift_T_82 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_84 = _write_packets_right_shift_T_81 & _write_packets_right_shift_T_83; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_86 = 9'h30 - {1'h0, _write_packets_right_shift_T_85}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_87 = _write_packets_right_shift_T_86[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_10 = _write_packets_right_shift_T_84 ? _write_packets_right_shift_T_87 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire _GEN_10 = write_packets_vaddr_offset_2 > 6'h2F; // @[DMA.scala:429:42, :457:38] wire write_packets_too_early_10; // @[DMA.scala:457:38] assign write_packets_too_early_10 = _GEN_10; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_55; // @[DMA.scala:449:43] assign _write_packets_left_shift_T_55 = _GEN_10; // @[DMA.scala:449:43, :457:38] wire write_packets_too_late_10 = _write_packets_too_late_T_10 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_10 = write_packets_too_early_10 | write_packets_too_late_10; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_11 = {3'h0, write_packets_left_shift_10} + {1'h0, write_packets_right_shift_10}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_13 = _write_packets_packet_bytes_written_per_beat_2_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_14 = _write_packets_packet_bytes_written_per_beat_2_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_57 = _write_packets_left_shift_T_55; // @[DMA.scala:449:{43,62}] wire [6:0] _write_packets_left_shift_T_58 = _write_packets_left_shift_T_43 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_59 = _write_packets_left_shift_T_58[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_11 = _write_packets_left_shift_T_57 ? _write_packets_left_shift_T_59 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_89 = _write_packets_right_shift_T_88 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_91 = _write_packets_right_shift_T_90 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_92 = _write_packets_right_shift_T_89 & _write_packets_right_shift_T_91; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_94 = 9'h40 - {1'h0, _write_packets_right_shift_T_93}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_95 = _write_packets_right_shift_T_94[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_11 = _write_packets_right_shift_T_92 ? _write_packets_right_shift_T_95 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_11 = _write_packets_too_late_T_11 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_10 = write_packets_too_late_11; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_11 = {3'h0, write_packets_left_shift_11} + {1'h0, write_packets_right_shift_11}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_13 = _write_packets_packet_bytes_written_per_beat_3_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_14 = _write_packets_packet_bytes_written_per_beat_3_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _best_write_packet_T = write_packets_1_bytes_written > write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:27] wire [6:0] _best_write_packet_T_1_size = _best_write_packet_T ? 7'h20 : 7'h10; // @[DMA.scala:466:{10,27}] wire [2:0] _best_write_packet_T_1_lg_size = {2'h2, _best_write_packet_T}; // @[DMA.scala:466:{10,27}] wire _best_write_packet_T_1_mask_0_0 = _best_write_packet_T ? write_packets_1_mask_0_0 : write_packets_0_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_1 = _best_write_packet_T ? write_packets_1_mask_0_1 : write_packets_0_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_2 = _best_write_packet_T ? write_packets_1_mask_0_2 : write_packets_0_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_3 = _best_write_packet_T ? write_packets_1_mask_0_3 : write_packets_0_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_4 = _best_write_packet_T ? write_packets_1_mask_0_4 : write_packets_0_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_5 = _best_write_packet_T ? write_packets_1_mask_0_5 : write_packets_0_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_6 = _best_write_packet_T ? write_packets_1_mask_0_6 : write_packets_0_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_7 = _best_write_packet_T ? write_packets_1_mask_0_7 : write_packets_0_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_8 = _best_write_packet_T ? write_packets_1_mask_0_8 : write_packets_0_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_9 = _best_write_packet_T ? write_packets_1_mask_0_9 : write_packets_0_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_10 = _best_write_packet_T ? write_packets_1_mask_0_10 : write_packets_0_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_11 = _best_write_packet_T ? write_packets_1_mask_0_11 : write_packets_0_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_12 = _best_write_packet_T ? write_packets_1_mask_0_12 : write_packets_0_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_13 = _best_write_packet_T ? write_packets_1_mask_0_13 : write_packets_0_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_14 = _best_write_packet_T ? write_packets_1_mask_0_14 : write_packets_0_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_15 = _best_write_packet_T ? write_packets_1_mask_0_15 : write_packets_0_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_0 = _best_write_packet_T & write_packets_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_1 = _best_write_packet_T & write_packets_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_2 = _best_write_packet_T & write_packets_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_3 = _best_write_packet_T & write_packets_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_4 = _best_write_packet_T & write_packets_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_5 = _best_write_packet_T & write_packets_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_6 = _best_write_packet_T & write_packets_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_7 = _best_write_packet_T & write_packets_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_8 = _best_write_packet_T & write_packets_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_9 = _best_write_packet_T & write_packets_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_10 = _best_write_packet_T & write_packets_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_11 = _best_write_packet_T & write_packets_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_12 = _best_write_packet_T & write_packets_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_13 = _best_write_packet_T & write_packets_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_14 = _best_write_packet_T & write_packets_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_15 = _best_write_packet_T & write_packets_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] _best_write_packet_T_1_vaddr = _best_write_packet_T ? write_packets_1_vaddr : write_packets_0_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_is_full = _best_write_packet_T ? write_packets_1_is_full : write_packets_0_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] _best_write_packet_T_1_bytes_written = _best_write_packet_T ? write_packets_1_bytes_written : write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_0 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_0 : write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_1 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_1 : write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_2 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_2 : write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_3 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_3 : write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_2 = write_packets_2_bytes_written > _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_size = _best_write_packet_T_2 ? 7'h40 : _best_write_packet_T_1_size; // @[DMA.scala:466:{10,27}] wire [2:0] best_write_packet_lg_size = _best_write_packet_T_2 ? 3'h6 : _best_write_packet_T_1_lg_size; // @[DMA.scala:466:{10,27}] wire best_write_packet_mask_0_0 = _best_write_packet_T_2 ? write_packets_2_mask_0_0 : _best_write_packet_T_1_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_1 = _best_write_packet_T_2 ? write_packets_2_mask_0_1 : _best_write_packet_T_1_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_2 = _best_write_packet_T_2 ? write_packets_2_mask_0_2 : _best_write_packet_T_1_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_3 = _best_write_packet_T_2 ? write_packets_2_mask_0_3 : _best_write_packet_T_1_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_4 = _best_write_packet_T_2 ? write_packets_2_mask_0_4 : _best_write_packet_T_1_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_5 = _best_write_packet_T_2 ? write_packets_2_mask_0_5 : _best_write_packet_T_1_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_6 = _best_write_packet_T_2 ? write_packets_2_mask_0_6 : _best_write_packet_T_1_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_7 = _best_write_packet_T_2 ? write_packets_2_mask_0_7 : _best_write_packet_T_1_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_8 = _best_write_packet_T_2 ? write_packets_2_mask_0_8 : _best_write_packet_T_1_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_9 = _best_write_packet_T_2 ? write_packets_2_mask_0_9 : _best_write_packet_T_1_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_10 = _best_write_packet_T_2 ? write_packets_2_mask_0_10 : _best_write_packet_T_1_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_11 = _best_write_packet_T_2 ? write_packets_2_mask_0_11 : _best_write_packet_T_1_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_12 = _best_write_packet_T_2 ? write_packets_2_mask_0_12 : _best_write_packet_T_1_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_13 = _best_write_packet_T_2 ? write_packets_2_mask_0_13 : _best_write_packet_T_1_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_14 = _best_write_packet_T_2 ? write_packets_2_mask_0_14 : _best_write_packet_T_1_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_15 = _best_write_packet_T_2 ? write_packets_2_mask_0_15 : _best_write_packet_T_1_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_0 = _best_write_packet_T_2 ? write_packets_2_mask_1_0 : _best_write_packet_T_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_1 = _best_write_packet_T_2 ? write_packets_2_mask_1_1 : _best_write_packet_T_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_2 = _best_write_packet_T_2 ? write_packets_2_mask_1_2 : _best_write_packet_T_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_3 = _best_write_packet_T_2 ? write_packets_2_mask_1_3 : _best_write_packet_T_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_4 = _best_write_packet_T_2 ? write_packets_2_mask_1_4 : _best_write_packet_T_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_5 = _best_write_packet_T_2 ? write_packets_2_mask_1_5 : _best_write_packet_T_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_6 = _best_write_packet_T_2 ? write_packets_2_mask_1_6 : _best_write_packet_T_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_7 = _best_write_packet_T_2 ? write_packets_2_mask_1_7 : _best_write_packet_T_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_8 = _best_write_packet_T_2 ? write_packets_2_mask_1_8 : _best_write_packet_T_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_9 = _best_write_packet_T_2 ? write_packets_2_mask_1_9 : _best_write_packet_T_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_10 = _best_write_packet_T_2 ? write_packets_2_mask_1_10 : _best_write_packet_T_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_11 = _best_write_packet_T_2 ? write_packets_2_mask_1_11 : _best_write_packet_T_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_12 = _best_write_packet_T_2 ? write_packets_2_mask_1_12 : _best_write_packet_T_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_13 = _best_write_packet_T_2 ? write_packets_2_mask_1_13 : _best_write_packet_T_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_14 = _best_write_packet_T_2 ? write_packets_2_mask_1_14 : _best_write_packet_T_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_15 = _best_write_packet_T_2 ? write_packets_2_mask_1_15 : _best_write_packet_T_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_0 = _best_write_packet_T_2 & write_packets_2_mask_2_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_1 = _best_write_packet_T_2 & write_packets_2_mask_2_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_2 = _best_write_packet_T_2 & write_packets_2_mask_2_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_3 = _best_write_packet_T_2 & write_packets_2_mask_2_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_4 = _best_write_packet_T_2 & write_packets_2_mask_2_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_5 = _best_write_packet_T_2 & write_packets_2_mask_2_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_6 = _best_write_packet_T_2 & write_packets_2_mask_2_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_7 = _best_write_packet_T_2 & write_packets_2_mask_2_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_8 = _best_write_packet_T_2 & write_packets_2_mask_2_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_9 = _best_write_packet_T_2 & write_packets_2_mask_2_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_10 = _best_write_packet_T_2 & write_packets_2_mask_2_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_11 = _best_write_packet_T_2 & write_packets_2_mask_2_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_12 = _best_write_packet_T_2 & write_packets_2_mask_2_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_13 = _best_write_packet_T_2 & write_packets_2_mask_2_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_14 = _best_write_packet_T_2 & write_packets_2_mask_2_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_15 = _best_write_packet_T_2 & write_packets_2_mask_2_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_0 = _best_write_packet_T_2 & write_packets_2_mask_3_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_1 = _best_write_packet_T_2 & write_packets_2_mask_3_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_2 = _best_write_packet_T_2 & write_packets_2_mask_3_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_3 = _best_write_packet_T_2 & write_packets_2_mask_3_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_4 = _best_write_packet_T_2 & write_packets_2_mask_3_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_5 = _best_write_packet_T_2 & write_packets_2_mask_3_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_6 = _best_write_packet_T_2 & write_packets_2_mask_3_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_7 = _best_write_packet_T_2 & write_packets_2_mask_3_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_8 = _best_write_packet_T_2 & write_packets_2_mask_3_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_9 = _best_write_packet_T_2 & write_packets_2_mask_3_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_10 = _best_write_packet_T_2 & write_packets_2_mask_3_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_11 = _best_write_packet_T_2 & write_packets_2_mask_3_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_12 = _best_write_packet_T_2 & write_packets_2_mask_3_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_13 = _best_write_packet_T_2 & write_packets_2_mask_3_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_14 = _best_write_packet_T_2 & write_packets_2_mask_3_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_15 = _best_write_packet_T_2 & write_packets_2_mask_3_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] best_write_packet_vaddr = _best_write_packet_T_2 ? write_packets_2_vaddr : _best_write_packet_T_1_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_is_full = _best_write_packet_T_2 ? write_packets_2_is_full : _best_write_packet_T_1_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_bytes_written = _best_write_packet_T_2 ? write_packets_2_bytes_written : _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_0 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_0 : _best_write_packet_T_1_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_1 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_1 : _best_write_packet_T_1_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_2 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_2 : _best_write_packet_T_1_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_3 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_3 : _best_write_packet_T_1_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _T_7 = state == 2'h1; // @[DMA.scala:380:24, :468:63] wire _write_packet_T; // @[DMA.scala:468:63] assign _write_packet_T = _T_7; // @[DMA.scala:468:63] wire _beatsSent_T; // @[DMA.scala:477:31] assign _beatsSent_T = _T_7; // @[DMA.scala:468:63, :477:31] wire _putFull_T; // @[DMA.scala:486:48] assign _putFull_T = _T_7; // @[DMA.scala:468:63, :486:48] wire _putPartial_T; // @[DMA.scala:493:48] assign _putPartial_T = _T_7; // @[DMA.scala:468:63, :493:48] wire _xactBusy_fire_T_1; // @[DMA.scala:507:51] assign _xactBusy_fire_T_1 = _T_7; // @[DMA.scala:468:63, :507:51] wire _untranslated_a_valid_T; // @[DMA.scala:508:36] assign _untranslated_a_valid_T = _T_7; // @[DMA.scala:468:63, :508:36] reg [6:0] write_packet_buf_size; // @[Util.scala:90:24] reg [2:0] write_packet_buf_lg_size; // @[Util.scala:90:24] reg write_packet_buf_mask_0_0; // @[Util.scala:90:24] reg write_packet_buf_mask_0_1; // @[Util.scala:90:24] reg write_packet_buf_mask_0_2; // @[Util.scala:90:24] reg write_packet_buf_mask_0_3; // @[Util.scala:90:24] reg write_packet_buf_mask_0_4; // @[Util.scala:90:24] reg write_packet_buf_mask_0_5; // @[Util.scala:90:24] reg write_packet_buf_mask_0_6; // @[Util.scala:90:24] reg write_packet_buf_mask_0_7; // @[Util.scala:90:24] reg write_packet_buf_mask_0_8; // @[Util.scala:90:24] reg write_packet_buf_mask_0_9; // @[Util.scala:90:24] reg write_packet_buf_mask_0_10; // @[Util.scala:90:24] reg write_packet_buf_mask_0_11; // @[Util.scala:90:24] reg write_packet_buf_mask_0_12; // @[Util.scala:90:24] reg write_packet_buf_mask_0_13; // @[Util.scala:90:24] reg write_packet_buf_mask_0_14; // @[Util.scala:90:24] reg write_packet_buf_mask_0_15; // @[Util.scala:90:24] reg write_packet_buf_mask_1_0; // @[Util.scala:90:24] reg write_packet_buf_mask_1_1; // @[Util.scala:90:24] reg write_packet_buf_mask_1_2; // @[Util.scala:90:24] reg write_packet_buf_mask_1_3; // @[Util.scala:90:24] reg write_packet_buf_mask_1_4; // @[Util.scala:90:24] reg write_packet_buf_mask_1_5; // @[Util.scala:90:24] reg write_packet_buf_mask_1_6; // @[Util.scala:90:24] reg write_packet_buf_mask_1_7; // @[Util.scala:90:24] reg write_packet_buf_mask_1_8; // @[Util.scala:90:24] reg write_packet_buf_mask_1_9; // @[Util.scala:90:24] reg write_packet_buf_mask_1_10; // @[Util.scala:90:24] reg write_packet_buf_mask_1_11; // @[Util.scala:90:24] reg write_packet_buf_mask_1_12; // @[Util.scala:90:24] reg write_packet_buf_mask_1_13; // @[Util.scala:90:24] reg write_packet_buf_mask_1_14; // @[Util.scala:90:24] reg write_packet_buf_mask_1_15; // @[Util.scala:90:24] reg write_packet_buf_mask_2_0; // @[Util.scala:90:24] reg write_packet_buf_mask_2_1; // @[Util.scala:90:24] reg write_packet_buf_mask_2_2; // @[Util.scala:90:24] reg write_packet_buf_mask_2_3; // @[Util.scala:90:24] reg write_packet_buf_mask_2_4; // @[Util.scala:90:24] reg write_packet_buf_mask_2_5; // @[Util.scala:90:24] reg write_packet_buf_mask_2_6; // @[Util.scala:90:24] reg write_packet_buf_mask_2_7; // @[Util.scala:90:24] reg write_packet_buf_mask_2_8; // @[Util.scala:90:24] reg write_packet_buf_mask_2_9; // @[Util.scala:90:24] reg write_packet_buf_mask_2_10; // @[Util.scala:90:24] reg write_packet_buf_mask_2_11; // @[Util.scala:90:24] reg write_packet_buf_mask_2_12; // @[Util.scala:90:24] reg write_packet_buf_mask_2_13; // @[Util.scala:90:24] reg write_packet_buf_mask_2_14; // @[Util.scala:90:24] reg write_packet_buf_mask_2_15; // @[Util.scala:90:24] reg write_packet_buf_mask_3_0; // @[Util.scala:90:24] reg write_packet_buf_mask_3_1; // @[Util.scala:90:24] reg write_packet_buf_mask_3_2; // @[Util.scala:90:24] reg write_packet_buf_mask_3_3; // @[Util.scala:90:24] reg write_packet_buf_mask_3_4; // @[Util.scala:90:24] reg write_packet_buf_mask_3_5; // @[Util.scala:90:24] reg write_packet_buf_mask_3_6; // @[Util.scala:90:24] reg write_packet_buf_mask_3_7; // @[Util.scala:90:24] reg write_packet_buf_mask_3_8; // @[Util.scala:90:24] reg write_packet_buf_mask_3_9; // @[Util.scala:90:24] reg write_packet_buf_mask_3_10; // @[Util.scala:90:24] reg write_packet_buf_mask_3_11; // @[Util.scala:90:24] reg write_packet_buf_mask_3_12; // @[Util.scala:90:24] reg write_packet_buf_mask_3_13; // @[Util.scala:90:24] reg write_packet_buf_mask_3_14; // @[Util.scala:90:24] reg write_packet_buf_mask_3_15; // @[Util.scala:90:24] reg [38:0] write_packet_buf_vaddr; // @[Util.scala:90:24] reg write_packet_buf_is_full; // @[Util.scala:90:24] reg [6:0] write_packet_buf_bytes_written; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24] wire [6:0] write_packet_size = _write_packet_T ? best_write_packet_size : write_packet_buf_size; // @[Util.scala:90:24, :91:8] wire [2:0] write_packet_lg_size = _write_packet_T ? best_write_packet_lg_size : write_packet_buf_lg_size; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_0 = _write_packet_T ? best_write_packet_mask_0_0 : write_packet_buf_mask_0_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_1 = _write_packet_T ? best_write_packet_mask_0_1 : write_packet_buf_mask_0_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_2 = _write_packet_T ? best_write_packet_mask_0_2 : write_packet_buf_mask_0_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_3 = _write_packet_T ? best_write_packet_mask_0_3 : write_packet_buf_mask_0_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_4 = _write_packet_T ? best_write_packet_mask_0_4 : write_packet_buf_mask_0_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_5 = _write_packet_T ? best_write_packet_mask_0_5 : write_packet_buf_mask_0_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_6 = _write_packet_T ? best_write_packet_mask_0_6 : write_packet_buf_mask_0_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_7 = _write_packet_T ? best_write_packet_mask_0_7 : write_packet_buf_mask_0_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_8 = _write_packet_T ? best_write_packet_mask_0_8 : write_packet_buf_mask_0_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_9 = _write_packet_T ? best_write_packet_mask_0_9 : write_packet_buf_mask_0_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_10 = _write_packet_T ? best_write_packet_mask_0_10 : write_packet_buf_mask_0_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_11 = _write_packet_T ? best_write_packet_mask_0_11 : write_packet_buf_mask_0_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_12 = _write_packet_T ? best_write_packet_mask_0_12 : write_packet_buf_mask_0_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_13 = _write_packet_T ? best_write_packet_mask_0_13 : write_packet_buf_mask_0_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_14 = _write_packet_T ? best_write_packet_mask_0_14 : write_packet_buf_mask_0_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_15 = _write_packet_T ? best_write_packet_mask_0_15 : write_packet_buf_mask_0_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_0 = _write_packet_T ? best_write_packet_mask_1_0 : write_packet_buf_mask_1_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_1 = _write_packet_T ? best_write_packet_mask_1_1 : write_packet_buf_mask_1_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_2 = _write_packet_T ? best_write_packet_mask_1_2 : write_packet_buf_mask_1_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_3 = _write_packet_T ? best_write_packet_mask_1_3 : write_packet_buf_mask_1_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_4 = _write_packet_T ? best_write_packet_mask_1_4 : write_packet_buf_mask_1_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_5 = _write_packet_T ? best_write_packet_mask_1_5 : write_packet_buf_mask_1_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_6 = _write_packet_T ? best_write_packet_mask_1_6 : write_packet_buf_mask_1_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_7 = _write_packet_T ? best_write_packet_mask_1_7 : write_packet_buf_mask_1_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_8 = _write_packet_T ? best_write_packet_mask_1_8 : write_packet_buf_mask_1_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_9 = _write_packet_T ? best_write_packet_mask_1_9 : write_packet_buf_mask_1_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_10 = _write_packet_T ? best_write_packet_mask_1_10 : write_packet_buf_mask_1_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_11 = _write_packet_T ? best_write_packet_mask_1_11 : write_packet_buf_mask_1_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_12 = _write_packet_T ? best_write_packet_mask_1_12 : write_packet_buf_mask_1_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_13 = _write_packet_T ? best_write_packet_mask_1_13 : write_packet_buf_mask_1_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_14 = _write_packet_T ? best_write_packet_mask_1_14 : write_packet_buf_mask_1_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_15 = _write_packet_T ? best_write_packet_mask_1_15 : write_packet_buf_mask_1_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_0 = _write_packet_T ? best_write_packet_mask_2_0 : write_packet_buf_mask_2_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_1 = _write_packet_T ? best_write_packet_mask_2_1 : write_packet_buf_mask_2_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_2 = _write_packet_T ? best_write_packet_mask_2_2 : write_packet_buf_mask_2_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_3 = _write_packet_T ? best_write_packet_mask_2_3 : write_packet_buf_mask_2_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_4 = _write_packet_T ? best_write_packet_mask_2_4 : write_packet_buf_mask_2_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_5 = _write_packet_T ? best_write_packet_mask_2_5 : write_packet_buf_mask_2_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_6 = _write_packet_T ? best_write_packet_mask_2_6 : write_packet_buf_mask_2_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_7 = _write_packet_T ? best_write_packet_mask_2_7 : write_packet_buf_mask_2_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_8 = _write_packet_T ? best_write_packet_mask_2_8 : write_packet_buf_mask_2_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_9 = _write_packet_T ? best_write_packet_mask_2_9 : write_packet_buf_mask_2_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_10 = _write_packet_T ? best_write_packet_mask_2_10 : write_packet_buf_mask_2_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_11 = _write_packet_T ? best_write_packet_mask_2_11 : write_packet_buf_mask_2_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_12 = _write_packet_T ? best_write_packet_mask_2_12 : write_packet_buf_mask_2_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_13 = _write_packet_T ? best_write_packet_mask_2_13 : write_packet_buf_mask_2_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_14 = _write_packet_T ? best_write_packet_mask_2_14 : write_packet_buf_mask_2_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_15 = _write_packet_T ? best_write_packet_mask_2_15 : write_packet_buf_mask_2_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_0 = _write_packet_T ? best_write_packet_mask_3_0 : write_packet_buf_mask_3_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_1 = _write_packet_T ? best_write_packet_mask_3_1 : write_packet_buf_mask_3_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_2 = _write_packet_T ? best_write_packet_mask_3_2 : write_packet_buf_mask_3_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_3 = _write_packet_T ? best_write_packet_mask_3_3 : write_packet_buf_mask_3_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_4 = _write_packet_T ? best_write_packet_mask_3_4 : write_packet_buf_mask_3_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_5 = _write_packet_T ? best_write_packet_mask_3_5 : write_packet_buf_mask_3_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_6 = _write_packet_T ? best_write_packet_mask_3_6 : write_packet_buf_mask_3_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_7 = _write_packet_T ? best_write_packet_mask_3_7 : write_packet_buf_mask_3_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_8 = _write_packet_T ? best_write_packet_mask_3_8 : write_packet_buf_mask_3_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_9 = _write_packet_T ? best_write_packet_mask_3_9 : write_packet_buf_mask_3_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_10 = _write_packet_T ? best_write_packet_mask_3_10 : write_packet_buf_mask_3_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_11 = _write_packet_T ? best_write_packet_mask_3_11 : write_packet_buf_mask_3_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_12 = _write_packet_T ? best_write_packet_mask_3_12 : write_packet_buf_mask_3_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_13 = _write_packet_T ? best_write_packet_mask_3_13 : write_packet_buf_mask_3_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_14 = _write_packet_T ? best_write_packet_mask_3_14 : write_packet_buf_mask_3_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_15 = _write_packet_T ? best_write_packet_mask_3_15 : write_packet_buf_mask_3_15; // @[Util.scala:90:24, :91:8] wire [38:0] write_packet_vaddr = _write_packet_T ? best_write_packet_vaddr : write_packet_buf_vaddr; // @[Util.scala:90:24, :91:8] wire write_packet_is_full = _write_packet_T ? best_write_packet_is_full : write_packet_buf_is_full; // @[Util.scala:90:24, :91:8] wire [6:0] write_packet_bytes_written = _write_packet_T ? best_write_packet_bytes_written : write_packet_buf_bytes_written; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_0 = _write_packet_T ? best_write_packet_bytes_written_per_beat_0 : write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_1 = _write_packet_T ? best_write_packet_bytes_written_per_beat_1 : write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_2 = _write_packet_T ? best_write_packet_bytes_written_per_beat_2 : write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_3 = _write_packet_T ? best_write_packet_bytes_written_per_beat_3 : write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24, :91:8] wire [38:0] untranslated_a_bits_vaddr = write_packet_vaddr; // @[Util.scala:91:8] wire _write_beats_T = write_packet_size < 7'h10; // @[Util.scala:91:8] wire [6:0] _write_beats_T_1 = write_packet_size / 7'h10; // @[Util.scala:91:8] wire [6:0] write_beats = _write_beats_T ? 7'h1 : _write_beats_T_1; // @[DMA.scala:418:{44,50,75}] reg [5:0] beatsLeft; // @[DMA.scala:476:24] wire [7:0] _GEN_11 = {1'h0, write_beats}; // @[DMA.scala:418:44, :477:73] wire [7:0] _beatsSent_T_1 = _GEN_11 - {2'h0, beatsLeft}; // @[DMA.scala:476:24, :477:73] wire [6:0] _beatsSent_T_2 = _beatsSent_T_1[6:0]; // @[DMA.scala:477:73] wire [6:0] beatsSent = _beatsSent_T ? 7'h0 : _beatsSent_T_2; // @[DMA.scala:477:{24,31,73}] wire [1:0] _write_mask_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [1:0] _bytes_written_this_beat_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [3:0] _GEN_12 = {{write_packet_mask_3_0}, {write_packet_mask_2_0}, {write_packet_mask_1_0}, {write_packet_mask_0_0}}; // @[Mux.scala:50:70] wire [3:0] _GEN_13 = {{write_packet_mask_3_1}, {write_packet_mask_2_1}, {write_packet_mask_1_1}, {write_packet_mask_0_1}}; // @[Mux.scala:50:70] wire [3:0] _GEN_14 = {{write_packet_mask_3_2}, {write_packet_mask_2_2}, {write_packet_mask_1_2}, {write_packet_mask_0_2}}; // @[Mux.scala:50:70] wire [3:0] _GEN_15 = {{write_packet_mask_3_3}, {write_packet_mask_2_3}, {write_packet_mask_1_3}, {write_packet_mask_0_3}}; // @[Mux.scala:50:70] wire [3:0] _GEN_16 = {{write_packet_mask_3_4}, {write_packet_mask_2_4}, {write_packet_mask_1_4}, {write_packet_mask_0_4}}; // @[Mux.scala:50:70] wire [3:0] _GEN_17 = {{write_packet_mask_3_5}, {write_packet_mask_2_5}, {write_packet_mask_1_5}, {write_packet_mask_0_5}}; // @[Mux.scala:50:70] wire [3:0] _GEN_18 = {{write_packet_mask_3_6}, {write_packet_mask_2_6}, {write_packet_mask_1_6}, {write_packet_mask_0_6}}; // @[Mux.scala:50:70] wire [3:0] _GEN_19 = {{write_packet_mask_3_7}, {write_packet_mask_2_7}, {write_packet_mask_1_7}, {write_packet_mask_0_7}}; // @[Mux.scala:50:70] wire [3:0] _GEN_20 = {{write_packet_mask_3_8}, {write_packet_mask_2_8}, {write_packet_mask_1_8}, {write_packet_mask_0_8}}; // @[Mux.scala:50:70] wire [3:0] _GEN_21 = {{write_packet_mask_3_9}, {write_packet_mask_2_9}, {write_packet_mask_1_9}, {write_packet_mask_0_9}}; // @[Mux.scala:50:70] wire [3:0] _GEN_22 = {{write_packet_mask_3_10}, {write_packet_mask_2_10}, {write_packet_mask_1_10}, {write_packet_mask_0_10}}; // @[Mux.scala:50:70] wire [3:0] _GEN_23 = {{write_packet_mask_3_11}, {write_packet_mask_2_11}, {write_packet_mask_1_11}, {write_packet_mask_0_11}}; // @[Mux.scala:50:70] wire [3:0] _GEN_24 = {{write_packet_mask_3_12}, {write_packet_mask_2_12}, {write_packet_mask_1_12}, {write_packet_mask_0_12}}; // @[Mux.scala:50:70] wire [3:0] _GEN_25 = {{write_packet_mask_3_13}, {write_packet_mask_2_13}, {write_packet_mask_1_13}, {write_packet_mask_0_13}}; // @[Mux.scala:50:70] wire [3:0] _GEN_26 = {{write_packet_mask_3_14}, {write_packet_mask_2_14}, {write_packet_mask_1_14}, {write_packet_mask_0_14}}; // @[Mux.scala:50:70] wire [3:0] _GEN_27 = {{write_packet_mask_3_15}, {write_packet_mask_2_15}, {write_packet_mask_1_15}, {write_packet_mask_0_15}}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T = {3'h7, ~_GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_1 = _GEN_25[_write_mask_T] ? 4'hD : _write_shift_T; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_2 = _GEN_24[_write_mask_T] ? 4'hC : _write_shift_T_1; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_3 = _GEN_23[_write_mask_T] ? 4'hB : _write_shift_T_2; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_4 = _GEN_22[_write_mask_T] ? 4'hA : _write_shift_T_3; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_5 = _GEN_21[_write_mask_T] ? 4'h9 : _write_shift_T_4; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_6 = _GEN_20[_write_mask_T] ? 4'h8 : _write_shift_T_5; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_7 = _GEN_19[_write_mask_T] ? 4'h7 : _write_shift_T_6; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_8 = _GEN_18[_write_mask_T] ? 4'h6 : _write_shift_T_7; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_9 = _GEN_17[_write_mask_T] ? 4'h5 : _write_shift_T_8; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_10 = _GEN_16[_write_mask_T] ? 4'h4 : _write_shift_T_9; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_11 = _GEN_15[_write_mask_T] ? 4'h3 : _write_shift_T_10; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_12 = _GEN_14[_write_mask_T] ? 4'h2 : _write_shift_T_11; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_13 = _GEN_13[_write_mask_T] ? 4'h1 : _write_shift_T_12; // @[Mux.scala:50:70] wire [3:0] write_shift = _GEN_12[_write_mask_T] ? 4'h0 : _write_shift_T_13; // @[Mux.scala:50:70] reg [3:0] putFull_buf; // @[Util.scala:90:24] wire [3:0] _putFull_T_1 = _putFull_T ? xactId : putFull_buf; // @[OneHot.scala:32:10] wire [3:0] putFull_source = _putFull_T_1; // @[Edges.scala:480:17] wire [10:0] _GEN_28 = {1'h0, bytesSent, 3'h0}; // @[DMA.scala:389:24, :489:34] wire [10:0] _putFull_T_2; // @[DMA.scala:489:34] assign _putFull_T_2 = _GEN_28; // @[DMA.scala:489:34] wire [10:0] _putPartial_T_2; // @[DMA.scala:496:35] assign _putPartial_T_2 = _GEN_28; // @[DMA.scala:489:34, :496:35] wire [511:0] _putFull_T_3 = data >> _putFull_T_2; // @[DMA.scala:387:19, :489:{20,34}] wire _GEN_29 = write_packet_lg_size != 3'h7; // @[Parameters.scala:92:38] wire _putFull_legal_T_11; // @[Parameters.scala:92:38] assign _putFull_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putPartial_legal_T_11; // @[Parameters.scala:92:38] assign _putPartial_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putFull_legal_T_12 = _putFull_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putFull_legal_T_13 = _putFull_legal_T_12; // @[Parameters.scala:684:29] wire _putFull_legal_T_61 = _putFull_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putFull_legal_T_70 = _putFull_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putFull_legal = _putFull_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _putFull_a_mask_T; // @[Misc.scala:222:10] wire [3:0] putFull_size; // @[Edges.scala:480:17] wire [15:0] putFull_mask; // @[Edges.scala:480:17] wire [127:0] putFull_data; // @[Edges.scala:480:17] wire [3:0] _GEN_30 = {1'h0, write_packet_lg_size}; // @[Edges.scala:483:15] assign putFull_size = _GEN_30; // @[Edges.scala:480:17, :483:15] wire [3:0] _putFull_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _putFull_a_mask_sizeOH_T = _GEN_30; // @[Misc.scala:202:34] wire [3:0] putPartial_size; // @[Edges.scala:500:17] assign putPartial_size = _GEN_30; // @[Edges.scala:483:15, :500:17] wire [1:0] putFull_a_mask_sizeOH_shiftAmount = _putFull_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _putFull_a_mask_sizeOH_T_1 = 4'h1 << putFull_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _putFull_a_mask_sizeOH_T_2 = _putFull_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] putFull_a_mask_sizeOH = {_putFull_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire putFull_a_mask_sub_sub_sub_sub_0_1 = write_packet_lg_size[2]; // @[Misc.scala:206:21] wire putFull_a_mask_sub_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21, :215:29] wire putFull_a_mask_sub_sub_sub_size = putFull_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_sub_acc_T = putFull_a_mask_sub_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire putFull_a_mask_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_2_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_3_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_size = putFull_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_acc_T = putFull_a_mask_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_1_1 = putFull_a_mask_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_2_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_3_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_4_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_5_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_6_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_7_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_size = putFull_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_acc_T = putFull_a_mask_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_0_1 = putFull_a_mask_sub_sub_0_1 | _putFull_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_acc_1 = putFull_a_mask_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_2 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_3 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_4 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_5 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_6 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_7 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_8 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_9 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_10 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_11 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_12 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_13 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_14 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_15 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_size = putFull_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_acc_T = putFull_a_mask_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_acc = putFull_a_mask_sub_0_1 | _putFull_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire [1:0] putFull_a_mask_lo_lo_lo = {putFull_a_mask_acc_1, putFull_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_lo_hi = {putFull_a_mask_acc_3, putFull_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_lo = {putFull_a_mask_lo_lo_hi, putFull_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_lo_hi_lo = {putFull_a_mask_acc_5, putFull_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_hi_hi = {putFull_a_mask_acc_7, putFull_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_hi = {putFull_a_mask_lo_hi_hi, putFull_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_lo = {putFull_a_mask_lo_hi, putFull_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_lo_lo = {putFull_a_mask_acc_9, putFull_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_lo_hi = {putFull_a_mask_acc_11, putFull_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_lo = {putFull_a_mask_hi_lo_hi, putFull_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_hi_lo = {putFull_a_mask_acc_13, putFull_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_hi_hi = {putFull_a_mask_acc_15, putFull_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_hi = {putFull_a_mask_hi_hi_hi, putFull_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_hi = {putFull_a_mask_hi_hi, putFull_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _putFull_a_mask_T = {putFull_a_mask_hi, putFull_a_mask_lo}; // @[Misc.scala:222:10] assign putFull_mask = _putFull_a_mask_T; // @[Misc.scala:222:10] assign putFull_data = _putFull_T_3[127:0]; // @[Edges.scala:480:17, :489:15] reg [3:0] putPartial_buf; // @[Util.scala:90:24] wire [3:0] _putPartial_T_1 = _putPartial_T ? xactId : putPartial_buf; // @[OneHot.scala:32:10] wire [3:0] putPartial_source = _putPartial_T_1; // @[Edges.scala:500:17] wire [511:0] _putPartial_T_3 = data >> _putPartial_T_2; // @[DMA.scala:387:19, :496:{21,35}] wire [7:0] _putPartial_T_4 = {1'h0, write_shift, 3'h0}; // @[Mux.scala:50:70] wire [766:0] _putPartial_T_5 = {255'h0, _putPartial_T_3} << _putPartial_T_4; // @[DMA.scala:496:{21,43,59}] wire [1:0] putPartial_lo_lo_lo = {_GEN_13[_write_mask_T], _GEN_12[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_lo_hi = {_GEN_15[_write_mask_T], _GEN_14[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_lo = {putPartial_lo_lo_hi, putPartial_lo_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_lo_hi_lo = {_GEN_17[_write_mask_T], _GEN_16[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_hi_hi = {_GEN_19[_write_mask_T], _GEN_18[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_hi = {putPartial_lo_hi_hi, putPartial_lo_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_lo = {putPartial_lo_hi, putPartial_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_lo_lo = {_GEN_21[_write_mask_T], _GEN_20[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_lo_hi = {_GEN_23[_write_mask_T], _GEN_22[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_lo = {putPartial_hi_lo_hi, putPartial_hi_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_hi_lo = {_GEN_25[_write_mask_T], _GEN_24[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_hi_hi = {_GEN_27[_write_mask_T], _GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_hi = {putPartial_hi_hi_hi, putPartial_hi_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_hi = {putPartial_hi_hi, putPartial_hi_lo}; // @[DMA.scala:497:25] wire [15:0] _putPartial_T_6 = {putPartial_hi, putPartial_lo}; // @[DMA.scala:497:25] wire [15:0] putPartial_mask = _putPartial_T_6; // @[Edges.scala:500:17] wire _putPartial_legal_T_12 = _putPartial_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putPartial_legal_T_13 = _putPartial_legal_T_12; // @[Parameters.scala:684:29] wire _putPartial_legal_T_61 = _putPartial_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putPartial_legal_T_70 = _putPartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putPartial_legal = _putPartial_legal_T_70; // @[Parameters.scala:686:26] wire [127:0] putPartial_data; // @[Edges.scala:500:17] assign putPartial_data = _putPartial_T_5[127:0]; // @[Edges.scala:500:17, :509:15] wire _untranslated_a_valid_T_5; // @[DMA.scala:508:90] wire [2:0] _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:509:36] wire [3:0] _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:509:36] wire [3:0] _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:509:36] wire [15:0] _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:509:36] wire [127:0] _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:509:36] wire [2:0] untranslated_a_bits_tl_a_opcode; // @[DMA.scala:506:30] wire [3:0] untranslated_a_bits_tl_a_size; // @[DMA.scala:506:30] wire [3:0] untranslated_a_bits_tl_a_source; // @[DMA.scala:506:30] wire [15:0] untranslated_a_bits_tl_a_mask; // @[DMA.scala:506:30] wire [127:0] untranslated_a_bits_tl_a_data; // @[DMA.scala:506:30] wire untranslated_a_ready; // @[DMA.scala:506:30] wire untranslated_a_valid; // @[DMA.scala:506:30] wire _xactBusy_fire_T = untranslated_a_ready & untranslated_a_valid; // @[Decoupled.scala:51:35] assign _xactBusy_fire_T_2 = _xactBusy_fire_T & _xactBusy_fire_T_1; // @[Decoupled.scala:51:35] assign xactBusy_fire = _xactBusy_fire_T_2; // @[DMA.scala:396:33, :507:42] wire _untranslated_a_valid_T_1 = state == 2'h2; // @[DMA.scala:380:24, :508:69] wire _untranslated_a_valid_T_2 = _untranslated_a_valid_T | _untranslated_a_valid_T_1; // @[DMA.scala:508:{36,60,69}] wire _untranslated_a_valid_T_3 = &xactBusy; // @[DMA.scala:392:27, :508:103] wire _untranslated_a_valid_T_4 = ~_untranslated_a_valid_T_3; // @[DMA.scala:508:{93,103}] assign _untranslated_a_valid_T_5 = _untranslated_a_valid_T_2 & _untranslated_a_valid_T_4; // @[DMA.scala:508:{60,90,93}] assign untranslated_a_valid = _untranslated_a_valid_T_5; // @[DMA.scala:506:30, :508:90] assign _untranslated_a_bits_tl_a_T_opcode = {2'h0, ~write_packet_is_full}; // @[Util.scala:91:8] assign _untranslated_a_bits_tl_a_T_size = write_packet_is_full ? putFull_size : putPartial_size; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_source = write_packet_is_full ? putFull_source : putPartial_source; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_mask = write_packet_is_full ? putFull_mask : putPartial_mask; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_data = write_packet_is_full ? putFull_data : putPartial_data; // @[Edges.scala:480:17, :500:17] assign untranslated_a_bits_tl_a_opcode = _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_size = _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_source = _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_mask = _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_data = _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:506:30, :509:36] wire _retry_a_valid_T; // @[DMA.scala:543:47] wire [2:0] retry_a_bits_tl_a_opcode; // @[DMA.scala:514:23] wire [2:0] retry_a_bits_tl_a_param; // @[DMA.scala:514:23] wire [3:0] retry_a_bits_tl_a_size; // @[DMA.scala:514:23] wire [3:0] retry_a_bits_tl_a_source; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_tl_a_address; // @[DMA.scala:514:23] wire [15:0] retry_a_bits_tl_a_mask; // @[DMA.scala:514:23] wire [127:0] retry_a_bits_tl_a_data; // @[DMA.scala:514:23] wire retry_a_bits_tl_a_corrupt; // @[DMA.scala:514:23] wire retry_a_bits_status_debug; // @[DMA.scala:514:23] wire retry_a_bits_status_cease; // @[DMA.scala:514:23] wire retry_a_bits_status_wfi; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_status_isa; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_dprv; // @[DMA.scala:514:23] wire retry_a_bits_status_dv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_prv; // @[DMA.scala:514:23] wire retry_a_bits_status_v; // @[DMA.scala:514:23] wire retry_a_bits_status_sd; // @[DMA.scala:514:23] wire [22:0] retry_a_bits_status_zero2; // @[DMA.scala:514:23] wire retry_a_bits_status_mpv; // @[DMA.scala:514:23] wire retry_a_bits_status_gva; // @[DMA.scala:514:23] wire retry_a_bits_status_mbe; // @[DMA.scala:514:23] wire retry_a_bits_status_sbe; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_sxl; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_uxl; // @[DMA.scala:514:23] wire retry_a_bits_status_sd_rv32; // @[DMA.scala:514:23] wire [7:0] retry_a_bits_status_zero1; // @[DMA.scala:514:23] wire retry_a_bits_status_tsr; // @[DMA.scala:514:23] wire retry_a_bits_status_tw; // @[DMA.scala:514:23] wire retry_a_bits_status_tvm; // @[DMA.scala:514:23] wire retry_a_bits_status_mxr; // @[DMA.scala:514:23] wire retry_a_bits_status_sum; // @[DMA.scala:514:23] wire retry_a_bits_status_mprv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_xs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_fs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_mpp; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_vs; // @[DMA.scala:514:23] wire retry_a_bits_status_spp; // @[DMA.scala:514:23] wire retry_a_bits_status_mpie; // @[DMA.scala:514:23] wire retry_a_bits_status_ube; // @[DMA.scala:514:23] wire retry_a_bits_status_spie; // @[DMA.scala:514:23] wire retry_a_bits_status_upie; // @[DMA.scala:514:23] wire retry_a_bits_status_mie; // @[DMA.scala:514:23] wire retry_a_bits_status_hie; // @[DMA.scala:514:23] wire retry_a_bits_status_sie; // @[DMA.scala:514:23] wire retry_a_bits_status_uie; // @[DMA.scala:514:23] wire [38:0] retry_a_bits_vaddr; // @[DMA.scala:514:23] wire retry_a_ready; // @[DMA.scala:514:23] wire retry_a_valid; // @[DMA.scala:514:23] assign _io_tlb_req_valid_T = _translate_q_io_enq_ready & _tlb_q_io_deq_valid; // @[Decoupled.scala:51:35] assign io_tlb_req_valid_0 = _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] assign io_tlb_req_bits_tlb_req_vaddr_0 = {1'h0, _tlb_q_io_deq_bits_vaddr}; // @[DMA.scala:360:9, :523:23, :528:35] wire _translate_q_io_deq_ready_T = nodeOut_a_ready | io_tlb_resp_miss_0; // @[DMA.scala:360:9, :541:44] assign _retry_a_valid_T = _translate_q_io_deq_valid & io_tlb_resp_miss_0; // @[DMA.scala:360:9, :534:29, :543:47] assign retry_a_valid = _retry_a_valid_T; // @[DMA.scala:514:23, :543:47] wire _nodeOut_a_valid_T = ~io_tlb_resp_miss_0; // @[DMA.scala:360:9, :547:47] assign _nodeOut_a_valid_T_1 = _translate_q_io_deq_valid & _nodeOut_a_valid_T; // @[DMA.scala:534:29, :547:{44,47}] assign nodeOut_a_valid = _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] reg nodeOut_a_bits_address_REG; // @[DMA.scala:549:66] reg [31:0] nodeOut_a_bits_address_buf; // @[Util.scala:90:24] assign _nodeOut_a_bits_address_T = nodeOut_a_bits_address_REG ? io_tlb_resp_paddr_0 : nodeOut_a_bits_address_buf; // @[Util.scala:90:24, :91:8] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign _nodeOut_d_ready_T = |xactBusy; // @[DMA.scala:392:27, :403:25, :551:28] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[DMA.scala:551:28] wire [7:0] _beatsLeft_T = _GEN_11 - 8'h1; // @[DMA.scala:477:73, :555:34] wire [6:0] _beatsLeft_T_1 = _beatsLeft_T[6:0]; // @[DMA.scala:555:34] wire [40:0] _next_vaddr_T = {1'h0, req_vaddr} + {34'h0, write_packet_bytes_written}; // @[Util.scala:91:8] wire [39:0] next_vaddr = _next_vaddr_T[39:0]; // @[DMA.scala:557:36] wire [3:0][4:0] _GEN_31 = {{write_packet_bytes_written_per_beat_3}, {write_packet_bytes_written_per_beat_2}, {write_packet_bytes_written_per_beat_1}, {write_packet_bytes_written_per_beat_0}}; // @[Util.scala:91:8] wire [7:0] _GEN_32 = _GEN + {3'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:390:29, :560:32] wire [7:0] _bytesSent_T; // @[DMA.scala:560:32] assign _bytesSent_T = _GEN_32; // @[DMA.scala:560:32] wire [7:0] _bytesSent_T_2; // @[DMA.scala:573:32] assign _bytesSent_T_2 = _GEN_32; // @[DMA.scala:560:32, :573:32] wire [6:0] _bytesSent_T_1 = _bytesSent_T[6:0]; // @[DMA.scala:560:32] wire _T_8 = write_beats == 7'h1; // @[DMA.scala:418:44, :562:27] wire [6:0] _GEN_33 = {2'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:560:32, :563:41] wire _T_9 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41] wire [6:0] _beatsLeft_T_2 = {1'h0, beatsLeft} - 7'h1; // @[DMA.scala:476:24, :572:32] wire [5:0] _beatsLeft_T_3 = _beatsLeft_T_2[5:0]; // @[DMA.scala:572:32] wire [6:0] _bytesSent_T_3 = _bytesSent_T_2[6:0]; // @[DMA.scala:573:32] wire _T_15 = beatsLeft == 6'h1; // @[DMA.scala:476:24, :577:25] wire _T_16 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41, :578:41] assign state_machine_ready_for_req = _xactBusy_fire_T ? (_T_7 ? _T_8 & _T_9 | _state_machine_ready_for_req_T : _untranslated_a_valid_T_1 & _T_15 & _T_16 | _state_machine_ready_for_req_T) : _state_machine_ready_for_req_T; // @[Decoupled.scala:51:35] wire _T_17 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_33; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_35; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_37; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_39; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_41; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_43; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_45; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_47; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_49; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_51; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_53; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_55; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_57; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_59; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_61; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_65; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_67; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_69; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_71; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_73; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_75; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_77; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_79; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_81; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_83; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_85; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_87; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_89; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_91; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_93; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_95; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_97; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_99; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_101; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_103; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_105; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_107; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_109; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_111; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_113; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_115; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_117; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_119; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_121; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_123; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_125; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_127; // @[DMA.scala:593:43] wire [7:0] pooled_v1_0; // @[DMA.scala:593:43] wire [7:0] pooled_v1_1; // @[DMA.scala:593:43] wire [7:0] pooled_v1_2; // @[DMA.scala:593:43] wire [7:0] pooled_v1_3; // @[DMA.scala:593:43] wire [7:0] pooled_v1_4; // @[DMA.scala:593:43] wire [7:0] pooled_v1_5; // @[DMA.scala:593:43] wire [7:0] pooled_v1_6; // @[DMA.scala:593:43] wire [7:0] pooled_v1_7; // @[DMA.scala:593:43] wire [7:0] pooled_v1_8; // @[DMA.scala:593:43] wire [7:0] pooled_v1_9; // @[DMA.scala:593:43] wire [7:0] pooled_v1_10; // @[DMA.scala:593:43] wire [7:0] pooled_v1_11; // @[DMA.scala:593:43] wire [7:0] pooled_v1_12; // @[DMA.scala:593:43] wire [7:0] pooled_v1_13; // @[DMA.scala:593:43] wire [7:0] pooled_v1_14; // @[DMA.scala:593:43] wire [7:0] pooled_v1_15; // @[DMA.scala:593:43] wire [7:0] pooled_v1_16; // @[DMA.scala:593:43] wire [7:0] pooled_v1_17; // @[DMA.scala:593:43] wire [7:0] pooled_v1_18; // @[DMA.scala:593:43] wire [7:0] pooled_v1_19; // @[DMA.scala:593:43] wire [7:0] pooled_v1_20; // @[DMA.scala:593:43] wire [7:0] pooled_v1_21; // @[DMA.scala:593:43] wire [7:0] pooled_v1_22; // @[DMA.scala:593:43] wire [7:0] pooled_v1_23; // @[DMA.scala:593:43] wire [7:0] pooled_v1_24; // @[DMA.scala:593:43] wire [7:0] pooled_v1_25; // @[DMA.scala:593:43] wire [7:0] pooled_v1_26; // @[DMA.scala:593:43] wire [7:0] pooled_v1_27; // @[DMA.scala:593:43] wire [7:0] pooled_v1_28; // @[DMA.scala:593:43] wire [7:0] pooled_v1_29; // @[DMA.scala:593:43] wire [7:0] pooled_v1_30; // @[DMA.scala:593:43] wire [7:0] pooled_v1_31; // @[DMA.scala:593:43] wire [7:0] pooled_v1_32; // @[DMA.scala:593:43] wire [7:0] pooled_v1_33; // @[DMA.scala:593:43] wire [7:0] pooled_v1_34; // @[DMA.scala:593:43] wire [7:0] pooled_v1_35; // @[DMA.scala:593:43] wire [7:0] pooled_v1_36; // @[DMA.scala:593:43] wire [7:0] pooled_v1_37; // @[DMA.scala:593:43] wire [7:0] pooled_v1_38; // @[DMA.scala:593:43] wire [7:0] pooled_v1_39; // @[DMA.scala:593:43] wire [7:0] pooled_v1_40; // @[DMA.scala:593:43] wire [7:0] pooled_v1_41; // @[DMA.scala:593:43] wire [7:0] pooled_v1_42; // @[DMA.scala:593:43] wire [7:0] pooled_v1_43; // @[DMA.scala:593:43] wire [7:0] pooled_v1_44; // @[DMA.scala:593:43] wire [7:0] pooled_v1_45; // @[DMA.scala:593:43] wire [7:0] pooled_v1_46; // @[DMA.scala:593:43] wire [7:0] pooled_v1_47; // @[DMA.scala:593:43] wire [7:0] pooled_v1_48; // @[DMA.scala:593:43] wire [7:0] pooled_v1_49; // @[DMA.scala:593:43] wire [7:0] pooled_v1_50; // @[DMA.scala:593:43] wire [7:0] pooled_v1_51; // @[DMA.scala:593:43] wire [7:0] pooled_v1_52; // @[DMA.scala:593:43] wire [7:0] pooled_v1_53; // @[DMA.scala:593:43] wire [7:0] pooled_v1_54; // @[DMA.scala:593:43] wire [7:0] pooled_v1_55; // @[DMA.scala:593:43] wire [7:0] pooled_v1_56; // @[DMA.scala:593:43] wire [7:0] pooled_v1_57; // @[DMA.scala:593:43] wire [7:0] pooled_v1_58; // @[DMA.scala:593:43] wire [7:0] pooled_v1_59; // @[DMA.scala:593:43] wire [7:0] pooled_v1_60; // @[DMA.scala:593:43] wire [7:0] pooled_v1_61; // @[DMA.scala:593:43] wire [7:0] pooled_v1_62; // @[DMA.scala:593:43] wire [7:0] pooled_v1_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T = _pooled_v1_WIRE[7:0]; // @[DMA.scala:593:43] assign _pooled_v1_T_1 = _pooled_v1_T; // @[DMA.scala:593:43] assign pooled_v1_0 = _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_2 = _pooled_v1_WIRE[15:8]; // @[DMA.scala:593:43] assign _pooled_v1_T_3 = _pooled_v1_T_2; // @[DMA.scala:593:43] assign pooled_v1_1 = _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_4 = _pooled_v1_WIRE[23:16]; // @[DMA.scala:593:43] assign _pooled_v1_T_5 = _pooled_v1_T_4; // @[DMA.scala:593:43] assign pooled_v1_2 = _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_6 = _pooled_v1_WIRE[31:24]; // @[DMA.scala:593:43] assign _pooled_v1_T_7 = _pooled_v1_T_6; // @[DMA.scala:593:43] assign pooled_v1_3 = _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_8 = _pooled_v1_WIRE[39:32]; // @[DMA.scala:593:43] assign _pooled_v1_T_9 = _pooled_v1_T_8; // @[DMA.scala:593:43] assign pooled_v1_4 = _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_10 = _pooled_v1_WIRE[47:40]; // @[DMA.scala:593:43] assign _pooled_v1_T_11 = _pooled_v1_T_10; // @[DMA.scala:593:43] assign pooled_v1_5 = _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_12 = _pooled_v1_WIRE[55:48]; // @[DMA.scala:593:43] assign _pooled_v1_T_13 = _pooled_v1_T_12; // @[DMA.scala:593:43] assign pooled_v1_6 = _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_14 = _pooled_v1_WIRE[63:56]; // @[DMA.scala:593:43] assign _pooled_v1_T_15 = _pooled_v1_T_14; // @[DMA.scala:593:43] assign pooled_v1_7 = _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_16 = _pooled_v1_WIRE[71:64]; // @[DMA.scala:593:43] assign _pooled_v1_T_17 = _pooled_v1_T_16; // @[DMA.scala:593:43] assign pooled_v1_8 = _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_18 = _pooled_v1_WIRE[79:72]; // @[DMA.scala:593:43] assign _pooled_v1_T_19 = _pooled_v1_T_18; // @[DMA.scala:593:43] assign pooled_v1_9 = _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_20 = _pooled_v1_WIRE[87:80]; // @[DMA.scala:593:43] assign _pooled_v1_T_21 = _pooled_v1_T_20; // @[DMA.scala:593:43] assign pooled_v1_10 = _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_22 = _pooled_v1_WIRE[95:88]; // @[DMA.scala:593:43] assign _pooled_v1_T_23 = _pooled_v1_T_22; // @[DMA.scala:593:43] assign pooled_v1_11 = _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_24 = _pooled_v1_WIRE[103:96]; // @[DMA.scala:593:43] assign _pooled_v1_T_25 = _pooled_v1_T_24; // @[DMA.scala:593:43] assign pooled_v1_12 = _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_26 = _pooled_v1_WIRE[111:104]; // @[DMA.scala:593:43] assign _pooled_v1_T_27 = _pooled_v1_T_26; // @[DMA.scala:593:43] assign pooled_v1_13 = _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_28 = _pooled_v1_WIRE[119:112]; // @[DMA.scala:593:43] assign _pooled_v1_T_29 = _pooled_v1_T_28; // @[DMA.scala:593:43] assign pooled_v1_14 = _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_30 = _pooled_v1_WIRE[127:120]; // @[DMA.scala:593:43] assign _pooled_v1_T_31 = _pooled_v1_T_30; // @[DMA.scala:593:43] assign pooled_v1_15 = _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_32 = _pooled_v1_WIRE[135:128]; // @[DMA.scala:593:43] assign _pooled_v1_T_33 = _pooled_v1_T_32; // @[DMA.scala:593:43] assign pooled_v1_16 = _pooled_v1_T_33; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_34 = _pooled_v1_WIRE[143:136]; // @[DMA.scala:593:43] assign _pooled_v1_T_35 = _pooled_v1_T_34; // @[DMA.scala:593:43] assign pooled_v1_17 = _pooled_v1_T_35; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_36 = _pooled_v1_WIRE[151:144]; // @[DMA.scala:593:43] assign _pooled_v1_T_37 = _pooled_v1_T_36; // @[DMA.scala:593:43] assign pooled_v1_18 = _pooled_v1_T_37; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_38 = _pooled_v1_WIRE[159:152]; // @[DMA.scala:593:43] assign _pooled_v1_T_39 = _pooled_v1_T_38; // @[DMA.scala:593:43] assign pooled_v1_19 = _pooled_v1_T_39; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_40 = _pooled_v1_WIRE[167:160]; // @[DMA.scala:593:43] assign _pooled_v1_T_41 = _pooled_v1_T_40; // @[DMA.scala:593:43] assign pooled_v1_20 = _pooled_v1_T_41; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_42 = _pooled_v1_WIRE[175:168]; // @[DMA.scala:593:43] assign _pooled_v1_T_43 = _pooled_v1_T_42; // @[DMA.scala:593:43] assign pooled_v1_21 = _pooled_v1_T_43; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_44 = _pooled_v1_WIRE[183:176]; // @[DMA.scala:593:43] assign _pooled_v1_T_45 = _pooled_v1_T_44; // @[DMA.scala:593:43] assign pooled_v1_22 = _pooled_v1_T_45; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_46 = _pooled_v1_WIRE[191:184]; // @[DMA.scala:593:43] assign _pooled_v1_T_47 = _pooled_v1_T_46; // @[DMA.scala:593:43] assign pooled_v1_23 = _pooled_v1_T_47; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_48 = _pooled_v1_WIRE[199:192]; // @[DMA.scala:593:43] assign _pooled_v1_T_49 = _pooled_v1_T_48; // @[DMA.scala:593:43] assign pooled_v1_24 = _pooled_v1_T_49; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_50 = _pooled_v1_WIRE[207:200]; // @[DMA.scala:593:43] assign _pooled_v1_T_51 = _pooled_v1_T_50; // @[DMA.scala:593:43] assign pooled_v1_25 = _pooled_v1_T_51; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_52 = _pooled_v1_WIRE[215:208]; // @[DMA.scala:593:43] assign _pooled_v1_T_53 = _pooled_v1_T_52; // @[DMA.scala:593:43] assign pooled_v1_26 = _pooled_v1_T_53; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_54 = _pooled_v1_WIRE[223:216]; // @[DMA.scala:593:43] assign _pooled_v1_T_55 = _pooled_v1_T_54; // @[DMA.scala:593:43] assign pooled_v1_27 = _pooled_v1_T_55; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_56 = _pooled_v1_WIRE[231:224]; // @[DMA.scala:593:43] assign _pooled_v1_T_57 = _pooled_v1_T_56; // @[DMA.scala:593:43] assign pooled_v1_28 = _pooled_v1_T_57; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_58 = _pooled_v1_WIRE[239:232]; // @[DMA.scala:593:43] assign _pooled_v1_T_59 = _pooled_v1_T_58; // @[DMA.scala:593:43] assign pooled_v1_29 = _pooled_v1_T_59; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_60 = _pooled_v1_WIRE[247:240]; // @[DMA.scala:593:43] assign _pooled_v1_T_61 = _pooled_v1_T_60; // @[DMA.scala:593:43] assign pooled_v1_30 = _pooled_v1_T_61; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_62 = _pooled_v1_WIRE[255:248]; // @[DMA.scala:593:43] assign _pooled_v1_T_63 = _pooled_v1_T_62; // @[DMA.scala:593:43] assign pooled_v1_31 = _pooled_v1_T_63; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_64 = _pooled_v1_WIRE[263:256]; // @[DMA.scala:593:43] assign _pooled_v1_T_65 = _pooled_v1_T_64; // @[DMA.scala:593:43] assign pooled_v1_32 = _pooled_v1_T_65; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_66 = _pooled_v1_WIRE[271:264]; // @[DMA.scala:593:43] assign _pooled_v1_T_67 = _pooled_v1_T_66; // @[DMA.scala:593:43] assign pooled_v1_33 = _pooled_v1_T_67; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_68 = _pooled_v1_WIRE[279:272]; // @[DMA.scala:593:43] assign _pooled_v1_T_69 = _pooled_v1_T_68; // @[DMA.scala:593:43] assign pooled_v1_34 = _pooled_v1_T_69; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_70 = _pooled_v1_WIRE[287:280]; // @[DMA.scala:593:43] assign _pooled_v1_T_71 = _pooled_v1_T_70; // @[DMA.scala:593:43] assign pooled_v1_35 = _pooled_v1_T_71; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_72 = _pooled_v1_WIRE[295:288]; // @[DMA.scala:593:43] assign _pooled_v1_T_73 = _pooled_v1_T_72; // @[DMA.scala:593:43] assign pooled_v1_36 = _pooled_v1_T_73; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_74 = _pooled_v1_WIRE[303:296]; // @[DMA.scala:593:43] assign _pooled_v1_T_75 = _pooled_v1_T_74; // @[DMA.scala:593:43] assign pooled_v1_37 = _pooled_v1_T_75; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_76 = _pooled_v1_WIRE[311:304]; // @[DMA.scala:593:43] assign _pooled_v1_T_77 = _pooled_v1_T_76; // @[DMA.scala:593:43] assign pooled_v1_38 = _pooled_v1_T_77; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_78 = _pooled_v1_WIRE[319:312]; // @[DMA.scala:593:43] assign _pooled_v1_T_79 = _pooled_v1_T_78; // @[DMA.scala:593:43] assign pooled_v1_39 = _pooled_v1_T_79; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_80 = _pooled_v1_WIRE[327:320]; // @[DMA.scala:593:43] assign _pooled_v1_T_81 = _pooled_v1_T_80; // @[DMA.scala:593:43] assign pooled_v1_40 = _pooled_v1_T_81; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_82 = _pooled_v1_WIRE[335:328]; // @[DMA.scala:593:43] assign _pooled_v1_T_83 = _pooled_v1_T_82; // @[DMA.scala:593:43] assign pooled_v1_41 = _pooled_v1_T_83; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_84 = _pooled_v1_WIRE[343:336]; // @[DMA.scala:593:43] assign _pooled_v1_T_85 = _pooled_v1_T_84; // @[DMA.scala:593:43] assign pooled_v1_42 = _pooled_v1_T_85; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_86 = _pooled_v1_WIRE[351:344]; // @[DMA.scala:593:43] assign _pooled_v1_T_87 = _pooled_v1_T_86; // @[DMA.scala:593:43] assign pooled_v1_43 = _pooled_v1_T_87; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_88 = _pooled_v1_WIRE[359:352]; // @[DMA.scala:593:43] assign _pooled_v1_T_89 = _pooled_v1_T_88; // @[DMA.scala:593:43] assign pooled_v1_44 = _pooled_v1_T_89; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_90 = _pooled_v1_WIRE[367:360]; // @[DMA.scala:593:43] assign _pooled_v1_T_91 = _pooled_v1_T_90; // @[DMA.scala:593:43] assign pooled_v1_45 = _pooled_v1_T_91; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_92 = _pooled_v1_WIRE[375:368]; // @[DMA.scala:593:43] assign _pooled_v1_T_93 = _pooled_v1_T_92; // @[DMA.scala:593:43] assign pooled_v1_46 = _pooled_v1_T_93; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_94 = _pooled_v1_WIRE[383:376]; // @[DMA.scala:593:43] assign _pooled_v1_T_95 = _pooled_v1_T_94; // @[DMA.scala:593:43] assign pooled_v1_47 = _pooled_v1_T_95; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_96 = _pooled_v1_WIRE[391:384]; // @[DMA.scala:593:43] assign _pooled_v1_T_97 = _pooled_v1_T_96; // @[DMA.scala:593:43] assign pooled_v1_48 = _pooled_v1_T_97; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_98 = _pooled_v1_WIRE[399:392]; // @[DMA.scala:593:43] assign _pooled_v1_T_99 = _pooled_v1_T_98; // @[DMA.scala:593:43] assign pooled_v1_49 = _pooled_v1_T_99; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_100 = _pooled_v1_WIRE[407:400]; // @[DMA.scala:593:43] assign _pooled_v1_T_101 = _pooled_v1_T_100; // @[DMA.scala:593:43] assign pooled_v1_50 = _pooled_v1_T_101; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_102 = _pooled_v1_WIRE[415:408]; // @[DMA.scala:593:43] assign _pooled_v1_T_103 = _pooled_v1_T_102; // @[DMA.scala:593:43] assign pooled_v1_51 = _pooled_v1_T_103; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_104 = _pooled_v1_WIRE[423:416]; // @[DMA.scala:593:43] assign _pooled_v1_T_105 = _pooled_v1_T_104; // @[DMA.scala:593:43] assign pooled_v1_52 = _pooled_v1_T_105; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_106 = _pooled_v1_WIRE[431:424]; // @[DMA.scala:593:43] assign _pooled_v1_T_107 = _pooled_v1_T_106; // @[DMA.scala:593:43] assign pooled_v1_53 = _pooled_v1_T_107; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_108 = _pooled_v1_WIRE[439:432]; // @[DMA.scala:593:43] assign _pooled_v1_T_109 = _pooled_v1_T_108; // @[DMA.scala:593:43] assign pooled_v1_54 = _pooled_v1_T_109; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_110 = _pooled_v1_WIRE[447:440]; // @[DMA.scala:593:43] assign _pooled_v1_T_111 = _pooled_v1_T_110; // @[DMA.scala:593:43] assign pooled_v1_55 = _pooled_v1_T_111; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_112 = _pooled_v1_WIRE[455:448]; // @[DMA.scala:593:43] assign _pooled_v1_T_113 = _pooled_v1_T_112; // @[DMA.scala:593:43] assign pooled_v1_56 = _pooled_v1_T_113; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_114 = _pooled_v1_WIRE[463:456]; // @[DMA.scala:593:43] assign _pooled_v1_T_115 = _pooled_v1_T_114; // @[DMA.scala:593:43] assign pooled_v1_57 = _pooled_v1_T_115; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_116 = _pooled_v1_WIRE[471:464]; // @[DMA.scala:593:43] assign _pooled_v1_T_117 = _pooled_v1_T_116; // @[DMA.scala:593:43] assign pooled_v1_58 = _pooled_v1_T_117; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_118 = _pooled_v1_WIRE[479:472]; // @[DMA.scala:593:43] assign _pooled_v1_T_119 = _pooled_v1_T_118; // @[DMA.scala:593:43] assign pooled_v1_59 = _pooled_v1_T_119; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_120 = _pooled_v1_WIRE[487:480]; // @[DMA.scala:593:43] assign _pooled_v1_T_121 = _pooled_v1_T_120; // @[DMA.scala:593:43] assign pooled_v1_60 = _pooled_v1_T_121; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_122 = _pooled_v1_WIRE[495:488]; // @[DMA.scala:593:43] assign _pooled_v1_T_123 = _pooled_v1_T_122; // @[DMA.scala:593:43] assign pooled_v1_61 = _pooled_v1_T_123; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_124 = _pooled_v1_WIRE[503:496]; // @[DMA.scala:593:43] assign _pooled_v1_T_125 = _pooled_v1_T_124; // @[DMA.scala:593:43] assign pooled_v1_62 = _pooled_v1_T_125; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_126 = _pooled_v1_WIRE[511:504]; // @[DMA.scala:593:43] assign _pooled_v1_T_127 = _pooled_v1_T_126; // @[DMA.scala:593:43] assign pooled_v1_63 = _pooled_v1_T_127; // @[DMA.scala:593:43] wire [7:0] _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_31; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_33; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_35; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_16 = pooled_v2_16; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_37; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_17 = pooled_v2_17; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_39; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_18 = pooled_v2_18; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_41; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_19 = pooled_v2_19; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_43; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_20 = pooled_v2_20; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_45; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_21 = pooled_v2_21; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_47; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_22 = pooled_v2_22; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_49; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_23 = pooled_v2_23; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_51; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_24 = pooled_v2_24; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_53; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_25 = pooled_v2_25; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_55; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_26 = pooled_v2_26; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_57; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_27 = pooled_v2_27; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_59; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_28 = pooled_v2_28; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_61; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_29 = pooled_v2_29; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_63; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_30 = pooled_v2_30; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_65; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_31 = pooled_v2_31; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_67; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_32 = pooled_v2_32; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_69; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_33 = pooled_v2_33; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_71; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_34 = pooled_v2_34; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_73; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_35 = pooled_v2_35; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_75; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_36 = pooled_v2_36; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_77; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_37 = pooled_v2_37; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_79; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_38 = pooled_v2_38; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_81; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_39 = pooled_v2_39; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_83; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_40 = pooled_v2_40; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_85; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_41 = pooled_v2_41; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_87; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_42 = pooled_v2_42; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_89; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_43 = pooled_v2_43; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_91; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_44 = pooled_v2_44; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_93; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_45 = pooled_v2_45; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_95; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_46 = pooled_v2_46; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_97; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_47 = pooled_v2_47; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_99; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_48 = pooled_v2_48; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_101; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_49 = pooled_v2_49; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_103; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_50 = pooled_v2_50; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_105; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_51 = pooled_v2_51; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_107; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_52 = pooled_v2_52; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_109; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_53 = pooled_v2_53; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_111; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_54 = pooled_v2_54; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_113; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_55 = pooled_v2_55; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_115; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_56 = pooled_v2_56; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_117; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_57 = pooled_v2_57; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_119; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_58 = pooled_v2_58; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_121; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_59 = pooled_v2_59; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_123; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_60 = pooled_v2_60; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_125; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_61 = pooled_v2_61; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T_127; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_62 = pooled_v2_62; // @[DMA.scala:594:44, :596:16] wire [7:0] pooled_v2_0; // @[DMA.scala:594:44] wire [7:0] pooled_v2_1; // @[DMA.scala:594:44] wire [7:0] pooled_v2_2; // @[DMA.scala:594:44] wire [7:0] pooled_v2_3; // @[DMA.scala:594:44] wire [7:0] pooled_v2_4; // @[DMA.scala:594:44] wire [7:0] pooled_v2_5; // @[DMA.scala:594:44] wire [7:0] pooled_v2_6; // @[DMA.scala:594:44] wire [7:0] pooled_v2_7; // @[DMA.scala:594:44] wire [7:0] pooled_v2_8; // @[DMA.scala:594:44] wire [7:0] pooled_v2_9; // @[DMA.scala:594:44] wire [7:0] pooled_v2_10; // @[DMA.scala:594:44] wire [7:0] pooled_v2_11; // @[DMA.scala:594:44] wire [7:0] pooled_v2_12; // @[DMA.scala:594:44] wire [7:0] pooled_v2_13; // @[DMA.scala:594:44] wire [7:0] pooled_v2_14; // @[DMA.scala:594:44] wire [7:0] pooled_v2_15; // @[DMA.scala:594:44] wire [7:0] pooled_v2_63; // @[DMA.scala:594:44] wire [7:0] _pooled_WIRE_63 = pooled_v2_63; // @[DMA.scala:594:44, :596:16] wire [7:0] _pooled_v2_T = _pooled_v2_WIRE[7:0]; // @[DMA.scala:594:44] assign _pooled_v2_T_1 = _pooled_v2_T; // @[DMA.scala:594:44] assign pooled_v2_0 = _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_2 = _pooled_v2_WIRE[15:8]; // @[DMA.scala:594:44] assign _pooled_v2_T_3 = _pooled_v2_T_2; // @[DMA.scala:594:44] assign pooled_v2_1 = _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_4 = _pooled_v2_WIRE[23:16]; // @[DMA.scala:594:44] assign _pooled_v2_T_5 = _pooled_v2_T_4; // @[DMA.scala:594:44] assign pooled_v2_2 = _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_6 = _pooled_v2_WIRE[31:24]; // @[DMA.scala:594:44] assign _pooled_v2_T_7 = _pooled_v2_T_6; // @[DMA.scala:594:44] assign pooled_v2_3 = _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_8 = _pooled_v2_WIRE[39:32]; // @[DMA.scala:594:44] assign _pooled_v2_T_9 = _pooled_v2_T_8; // @[DMA.scala:594:44] assign pooled_v2_4 = _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_10 = _pooled_v2_WIRE[47:40]; // @[DMA.scala:594:44] assign _pooled_v2_T_11 = _pooled_v2_T_10; // @[DMA.scala:594:44] assign pooled_v2_5 = _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_12 = _pooled_v2_WIRE[55:48]; // @[DMA.scala:594:44] assign _pooled_v2_T_13 = _pooled_v2_T_12; // @[DMA.scala:594:44] assign pooled_v2_6 = _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_14 = _pooled_v2_WIRE[63:56]; // @[DMA.scala:594:44] assign _pooled_v2_T_15 = _pooled_v2_T_14; // @[DMA.scala:594:44] assign pooled_v2_7 = _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_16 = _pooled_v2_WIRE[71:64]; // @[DMA.scala:594:44] assign _pooled_v2_T_17 = _pooled_v2_T_16; // @[DMA.scala:594:44] assign pooled_v2_8 = _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_18 = _pooled_v2_WIRE[79:72]; // @[DMA.scala:594:44] assign _pooled_v2_T_19 = _pooled_v2_T_18; // @[DMA.scala:594:44] assign pooled_v2_9 = _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_20 = _pooled_v2_WIRE[87:80]; // @[DMA.scala:594:44] assign _pooled_v2_T_21 = _pooled_v2_T_20; // @[DMA.scala:594:44] assign pooled_v2_10 = _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_22 = _pooled_v2_WIRE[95:88]; // @[DMA.scala:594:44] assign _pooled_v2_T_23 = _pooled_v2_T_22; // @[DMA.scala:594:44] assign pooled_v2_11 = _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_24 = _pooled_v2_WIRE[103:96]; // @[DMA.scala:594:44] assign _pooled_v2_T_25 = _pooled_v2_T_24; // @[DMA.scala:594:44] assign pooled_v2_12 = _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_26 = _pooled_v2_WIRE[111:104]; // @[DMA.scala:594:44] assign _pooled_v2_T_27 = _pooled_v2_T_26; // @[DMA.scala:594:44] assign pooled_v2_13 = _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_28 = _pooled_v2_WIRE[119:112]; // @[DMA.scala:594:44] assign _pooled_v2_T_29 = _pooled_v2_T_28; // @[DMA.scala:594:44] assign pooled_v2_14 = _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_30 = _pooled_v2_WIRE[127:120]; // @[DMA.scala:594:44] assign _pooled_v2_T_31 = _pooled_v2_T_30; // @[DMA.scala:594:44] assign pooled_v2_15 = _pooled_v2_T_31; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_32 = _pooled_v2_WIRE[135:128]; // @[DMA.scala:594:44] assign _pooled_v2_T_33 = _pooled_v2_T_32; // @[DMA.scala:594:44] assign pooled_v2_16 = _pooled_v2_T_33; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_34 = _pooled_v2_WIRE[143:136]; // @[DMA.scala:594:44] assign _pooled_v2_T_35 = _pooled_v2_T_34; // @[DMA.scala:594:44] assign pooled_v2_17 = _pooled_v2_T_35; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_36 = _pooled_v2_WIRE[151:144]; // @[DMA.scala:594:44] assign _pooled_v2_T_37 = _pooled_v2_T_36; // @[DMA.scala:594:44] assign pooled_v2_18 = _pooled_v2_T_37; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_38 = _pooled_v2_WIRE[159:152]; // @[DMA.scala:594:44] assign _pooled_v2_T_39 = _pooled_v2_T_38; // @[DMA.scala:594:44] assign pooled_v2_19 = _pooled_v2_T_39; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_40 = _pooled_v2_WIRE[167:160]; // @[DMA.scala:594:44] assign _pooled_v2_T_41 = _pooled_v2_T_40; // @[DMA.scala:594:44] assign pooled_v2_20 = _pooled_v2_T_41; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_42 = _pooled_v2_WIRE[175:168]; // @[DMA.scala:594:44] assign _pooled_v2_T_43 = _pooled_v2_T_42; // @[DMA.scala:594:44] assign pooled_v2_21 = _pooled_v2_T_43; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_44 = _pooled_v2_WIRE[183:176]; // @[DMA.scala:594:44] assign _pooled_v2_T_45 = _pooled_v2_T_44; // @[DMA.scala:594:44] assign pooled_v2_22 = _pooled_v2_T_45; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_46 = _pooled_v2_WIRE[191:184]; // @[DMA.scala:594:44] assign _pooled_v2_T_47 = _pooled_v2_T_46; // @[DMA.scala:594:44] assign pooled_v2_23 = _pooled_v2_T_47; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_48 = _pooled_v2_WIRE[199:192]; // @[DMA.scala:594:44] assign _pooled_v2_T_49 = _pooled_v2_T_48; // @[DMA.scala:594:44] assign pooled_v2_24 = _pooled_v2_T_49; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_50 = _pooled_v2_WIRE[207:200]; // @[DMA.scala:594:44] assign _pooled_v2_T_51 = _pooled_v2_T_50; // @[DMA.scala:594:44] assign pooled_v2_25 = _pooled_v2_T_51; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_52 = _pooled_v2_WIRE[215:208]; // @[DMA.scala:594:44] assign _pooled_v2_T_53 = _pooled_v2_T_52; // @[DMA.scala:594:44] assign pooled_v2_26 = _pooled_v2_T_53; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_54 = _pooled_v2_WIRE[223:216]; // @[DMA.scala:594:44] assign _pooled_v2_T_55 = _pooled_v2_T_54; // @[DMA.scala:594:44] assign pooled_v2_27 = _pooled_v2_T_55; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_56 = _pooled_v2_WIRE[231:224]; // @[DMA.scala:594:44] assign _pooled_v2_T_57 = _pooled_v2_T_56; // @[DMA.scala:594:44] assign pooled_v2_28 = _pooled_v2_T_57; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_58 = _pooled_v2_WIRE[239:232]; // @[DMA.scala:594:44] assign _pooled_v2_T_59 = _pooled_v2_T_58; // @[DMA.scala:594:44] assign pooled_v2_29 = _pooled_v2_T_59; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_60 = _pooled_v2_WIRE[247:240]; // @[DMA.scala:594:44] assign _pooled_v2_T_61 = _pooled_v2_T_60; // @[DMA.scala:594:44] assign pooled_v2_30 = _pooled_v2_T_61; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_62 = _pooled_v2_WIRE[255:248]; // @[DMA.scala:594:44] assign _pooled_v2_T_63 = _pooled_v2_T_62; // @[DMA.scala:594:44] assign pooled_v2_31 = _pooled_v2_T_63; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_64 = _pooled_v2_WIRE[263:256]; // @[DMA.scala:594:44] assign _pooled_v2_T_65 = _pooled_v2_T_64; // @[DMA.scala:594:44] assign pooled_v2_32 = _pooled_v2_T_65; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_66 = _pooled_v2_WIRE[271:264]; // @[DMA.scala:594:44] assign _pooled_v2_T_67 = _pooled_v2_T_66; // @[DMA.scala:594:44] assign pooled_v2_33 = _pooled_v2_T_67; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_68 = _pooled_v2_WIRE[279:272]; // @[DMA.scala:594:44] assign _pooled_v2_T_69 = _pooled_v2_T_68; // @[DMA.scala:594:44] assign pooled_v2_34 = _pooled_v2_T_69; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_70 = _pooled_v2_WIRE[287:280]; // @[DMA.scala:594:44] assign _pooled_v2_T_71 = _pooled_v2_T_70; // @[DMA.scala:594:44] assign pooled_v2_35 = _pooled_v2_T_71; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_72 = _pooled_v2_WIRE[295:288]; // @[DMA.scala:594:44] assign _pooled_v2_T_73 = _pooled_v2_T_72; // @[DMA.scala:594:44] assign pooled_v2_36 = _pooled_v2_T_73; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_74 = _pooled_v2_WIRE[303:296]; // @[DMA.scala:594:44] assign _pooled_v2_T_75 = _pooled_v2_T_74; // @[DMA.scala:594:44] assign pooled_v2_37 = _pooled_v2_T_75; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_76 = _pooled_v2_WIRE[311:304]; // @[DMA.scala:594:44] assign _pooled_v2_T_77 = _pooled_v2_T_76; // @[DMA.scala:594:44] assign pooled_v2_38 = _pooled_v2_T_77; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_78 = _pooled_v2_WIRE[319:312]; // @[DMA.scala:594:44] assign _pooled_v2_T_79 = _pooled_v2_T_78; // @[DMA.scala:594:44] assign pooled_v2_39 = _pooled_v2_T_79; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_80 = _pooled_v2_WIRE[327:320]; // @[DMA.scala:594:44] assign _pooled_v2_T_81 = _pooled_v2_T_80; // @[DMA.scala:594:44] assign pooled_v2_40 = _pooled_v2_T_81; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_82 = _pooled_v2_WIRE[335:328]; // @[DMA.scala:594:44] assign _pooled_v2_T_83 = _pooled_v2_T_82; // @[DMA.scala:594:44] assign pooled_v2_41 = _pooled_v2_T_83; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_84 = _pooled_v2_WIRE[343:336]; // @[DMA.scala:594:44] assign _pooled_v2_T_85 = _pooled_v2_T_84; // @[DMA.scala:594:44] assign pooled_v2_42 = _pooled_v2_T_85; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_86 = _pooled_v2_WIRE[351:344]; // @[DMA.scala:594:44] assign _pooled_v2_T_87 = _pooled_v2_T_86; // @[DMA.scala:594:44] assign pooled_v2_43 = _pooled_v2_T_87; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_88 = _pooled_v2_WIRE[359:352]; // @[DMA.scala:594:44] assign _pooled_v2_T_89 = _pooled_v2_T_88; // @[DMA.scala:594:44] assign pooled_v2_44 = _pooled_v2_T_89; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_90 = _pooled_v2_WIRE[367:360]; // @[DMA.scala:594:44] assign _pooled_v2_T_91 = _pooled_v2_T_90; // @[DMA.scala:594:44] assign pooled_v2_45 = _pooled_v2_T_91; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_92 = _pooled_v2_WIRE[375:368]; // @[DMA.scala:594:44] assign _pooled_v2_T_93 = _pooled_v2_T_92; // @[DMA.scala:594:44] assign pooled_v2_46 = _pooled_v2_T_93; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_94 = _pooled_v2_WIRE[383:376]; // @[DMA.scala:594:44] assign _pooled_v2_T_95 = _pooled_v2_T_94; // @[DMA.scala:594:44] assign pooled_v2_47 = _pooled_v2_T_95; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_96 = _pooled_v2_WIRE[391:384]; // @[DMA.scala:594:44] assign _pooled_v2_T_97 = _pooled_v2_T_96; // @[DMA.scala:594:44] assign pooled_v2_48 = _pooled_v2_T_97; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_98 = _pooled_v2_WIRE[399:392]; // @[DMA.scala:594:44] assign _pooled_v2_T_99 = _pooled_v2_T_98; // @[DMA.scala:594:44] assign pooled_v2_49 = _pooled_v2_T_99; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_100 = _pooled_v2_WIRE[407:400]; // @[DMA.scala:594:44] assign _pooled_v2_T_101 = _pooled_v2_T_100; // @[DMA.scala:594:44] assign pooled_v2_50 = _pooled_v2_T_101; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_102 = _pooled_v2_WIRE[415:408]; // @[DMA.scala:594:44] assign _pooled_v2_T_103 = _pooled_v2_T_102; // @[DMA.scala:594:44] assign pooled_v2_51 = _pooled_v2_T_103; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_104 = _pooled_v2_WIRE[423:416]; // @[DMA.scala:594:44] assign _pooled_v2_T_105 = _pooled_v2_T_104; // @[DMA.scala:594:44] assign pooled_v2_52 = _pooled_v2_T_105; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_106 = _pooled_v2_WIRE[431:424]; // @[DMA.scala:594:44] assign _pooled_v2_T_107 = _pooled_v2_T_106; // @[DMA.scala:594:44] assign pooled_v2_53 = _pooled_v2_T_107; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_108 = _pooled_v2_WIRE[439:432]; // @[DMA.scala:594:44] assign _pooled_v2_T_109 = _pooled_v2_T_108; // @[DMA.scala:594:44] assign pooled_v2_54 = _pooled_v2_T_109; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_110 = _pooled_v2_WIRE[447:440]; // @[DMA.scala:594:44] assign _pooled_v2_T_111 = _pooled_v2_T_110; // @[DMA.scala:594:44] assign pooled_v2_55 = _pooled_v2_T_111; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_112 = _pooled_v2_WIRE[455:448]; // @[DMA.scala:594:44] assign _pooled_v2_T_113 = _pooled_v2_T_112; // @[DMA.scala:594:44] assign pooled_v2_56 = _pooled_v2_T_113; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_114 = _pooled_v2_WIRE[463:456]; // @[DMA.scala:594:44] assign _pooled_v2_T_115 = _pooled_v2_T_114; // @[DMA.scala:594:44] assign pooled_v2_57 = _pooled_v2_T_115; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_116 = _pooled_v2_WIRE[471:464]; // @[DMA.scala:594:44] assign _pooled_v2_T_117 = _pooled_v2_T_116; // @[DMA.scala:594:44] assign pooled_v2_58 = _pooled_v2_T_117; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_118 = _pooled_v2_WIRE[479:472]; // @[DMA.scala:594:44] assign _pooled_v2_T_119 = _pooled_v2_T_118; // @[DMA.scala:594:44] assign pooled_v2_59 = _pooled_v2_T_119; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_120 = _pooled_v2_WIRE[487:480]; // @[DMA.scala:594:44] assign _pooled_v2_T_121 = _pooled_v2_T_120; // @[DMA.scala:594:44] assign pooled_v2_60 = _pooled_v2_T_121; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_122 = _pooled_v2_WIRE[495:488]; // @[DMA.scala:594:44] assign _pooled_v2_T_123 = _pooled_v2_T_122; // @[DMA.scala:594:44] assign pooled_v2_61 = _pooled_v2_T_123; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_124 = _pooled_v2_WIRE[503:496]; // @[DMA.scala:594:44] assign _pooled_v2_T_125 = _pooled_v2_T_124; // @[DMA.scala:594:44] assign pooled_v2_62 = _pooled_v2_T_125; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_126 = _pooled_v2_WIRE[511:504]; // @[DMA.scala:594:44] assign _pooled_v2_T_127 = _pooled_v2_T_126; // @[DMA.scala:594:44] assign pooled_v2_63 = _pooled_v2_T_127; // @[DMA.scala:594:44] wire _pooled_T = $signed(pooled_v1_0) > $signed(pooled_v2_0); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_1 = _pooled_T ? pooled_v1_0 : pooled_v2_0; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_0 = _pooled_T_1; // @[Util.scala:105:8] wire _pooled_T_2 = $signed(pooled_v1_1) > $signed(pooled_v2_1); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_3 = _pooled_T_2 ? pooled_v1_1 : pooled_v2_1; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_1 = _pooled_T_3; // @[Util.scala:105:8] wire _pooled_T_4 = $signed(pooled_v1_2) > $signed(pooled_v2_2); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_5 = _pooled_T_4 ? pooled_v1_2 : pooled_v2_2; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_2 = _pooled_T_5; // @[Util.scala:105:8] wire _pooled_T_6 = $signed(pooled_v1_3) > $signed(pooled_v2_3); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_7 = _pooled_T_6 ? pooled_v1_3 : pooled_v2_3; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_3 = _pooled_T_7; // @[Util.scala:105:8] wire _pooled_T_8 = $signed(pooled_v1_4) > $signed(pooled_v2_4); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_9 = _pooled_T_8 ? pooled_v1_4 : pooled_v2_4; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_4 = _pooled_T_9; // @[Util.scala:105:8] wire _pooled_T_10 = $signed(pooled_v1_5) > $signed(pooled_v2_5); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_11 = _pooled_T_10 ? pooled_v1_5 : pooled_v2_5; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_5 = _pooled_T_11; // @[Util.scala:105:8] wire _pooled_T_12 = $signed(pooled_v1_6) > $signed(pooled_v2_6); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_13 = _pooled_T_12 ? pooled_v1_6 : pooled_v2_6; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_6 = _pooled_T_13; // @[Util.scala:105:8] wire _pooled_T_14 = $signed(pooled_v1_7) > $signed(pooled_v2_7); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_15 = _pooled_T_14 ? pooled_v1_7 : pooled_v2_7; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_7 = _pooled_T_15; // @[Util.scala:105:8] wire _pooled_T_16 = $signed(pooled_v1_8) > $signed(pooled_v2_8); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_17 = _pooled_T_16 ? pooled_v1_8 : pooled_v2_8; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_8 = _pooled_T_17; // @[Util.scala:105:8] wire _pooled_T_18 = $signed(pooled_v1_9) > $signed(pooled_v2_9); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_19 = _pooled_T_18 ? pooled_v1_9 : pooled_v2_9; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_9 = _pooled_T_19; // @[Util.scala:105:8] wire _pooled_T_20 = $signed(pooled_v1_10) > $signed(pooled_v2_10); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_21 = _pooled_T_20 ? pooled_v1_10 : pooled_v2_10; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_10 = _pooled_T_21; // @[Util.scala:105:8] wire _pooled_T_22 = $signed(pooled_v1_11) > $signed(pooled_v2_11); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_23 = _pooled_T_22 ? pooled_v1_11 : pooled_v2_11; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_11 = _pooled_T_23; // @[Util.scala:105:8] wire _pooled_T_24 = $signed(pooled_v1_12) > $signed(pooled_v2_12); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_25 = _pooled_T_24 ? pooled_v1_12 : pooled_v2_12; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_12 = _pooled_T_25; // @[Util.scala:105:8] wire _pooled_T_26 = $signed(pooled_v1_13) > $signed(pooled_v2_13); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_27 = _pooled_T_26 ? pooled_v1_13 : pooled_v2_13; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_13 = _pooled_T_27; // @[Util.scala:105:8] wire _pooled_T_28 = $signed(pooled_v1_14) > $signed(pooled_v2_14); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_29 = _pooled_T_28 ? pooled_v1_14 : pooled_v2_14; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_14 = _pooled_T_29; // @[Util.scala:105:8] wire _pooled_T_30 = $signed(pooled_v1_15) > $signed(pooled_v2_15); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_31 = _pooled_T_30 ? pooled_v1_15 : pooled_v2_15; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_15 = _pooled_T_31; // @[Util.scala:105:8] wire [7:0] _pooled_T_32 = _pooled_WIRE_0; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_33 = _pooled_WIRE_1; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_34 = _pooled_WIRE_2; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_35 = _pooled_WIRE_3; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_36 = _pooled_WIRE_4; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_37 = _pooled_WIRE_5; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_38 = _pooled_WIRE_6; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_39 = _pooled_WIRE_7; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_40 = _pooled_WIRE_8; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_41 = _pooled_WIRE_9; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_42 = _pooled_WIRE_10; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_43 = _pooled_WIRE_11; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_44 = _pooled_WIRE_12; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_45 = _pooled_WIRE_13; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_46 = _pooled_WIRE_14; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_47 = _pooled_WIRE_15; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_48 = _pooled_WIRE_16; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_49 = _pooled_WIRE_17; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_50 = _pooled_WIRE_18; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_51 = _pooled_WIRE_19; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_52 = _pooled_WIRE_20; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_53 = _pooled_WIRE_21; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_54 = _pooled_WIRE_22; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_55 = _pooled_WIRE_23; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_56 = _pooled_WIRE_24; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_57 = _pooled_WIRE_25; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_58 = _pooled_WIRE_26; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_59 = _pooled_WIRE_27; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_60 = _pooled_WIRE_28; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_61 = _pooled_WIRE_29; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_62 = _pooled_WIRE_30; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_63 = _pooled_WIRE_31; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_64 = _pooled_WIRE_32; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_65 = _pooled_WIRE_33; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_66 = _pooled_WIRE_34; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_67 = _pooled_WIRE_35; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_68 = _pooled_WIRE_36; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_69 = _pooled_WIRE_37; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_70 = _pooled_WIRE_38; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_71 = _pooled_WIRE_39; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_72 = _pooled_WIRE_40; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_73 = _pooled_WIRE_41; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_74 = _pooled_WIRE_42; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_75 = _pooled_WIRE_43; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_76 = _pooled_WIRE_44; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_77 = _pooled_WIRE_45; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_78 = _pooled_WIRE_46; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_79 = _pooled_WIRE_47; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_80 = _pooled_WIRE_48; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_81 = _pooled_WIRE_49; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_82 = _pooled_WIRE_50; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_83 = _pooled_WIRE_51; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_84 = _pooled_WIRE_52; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_85 = _pooled_WIRE_53; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_86 = _pooled_WIRE_54; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_87 = _pooled_WIRE_55; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_88 = _pooled_WIRE_56; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_89 = _pooled_WIRE_57; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_90 = _pooled_WIRE_58; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_91 = _pooled_WIRE_59; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_92 = _pooled_WIRE_60; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_93 = _pooled_WIRE_61; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_94 = _pooled_WIRE_62; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_95 = _pooled_WIRE_63; // @[DMA.scala:596:{16,97}] wire [15:0] pooled_lo_lo_lo_lo_lo = {_pooled_T_33, _pooled_T_32}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_lo_hi = {_pooled_T_35, _pooled_T_34}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_lo_lo = {pooled_lo_lo_lo_lo_hi, pooled_lo_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_hi_lo = {_pooled_T_37, _pooled_T_36}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_lo_hi_hi = {_pooled_T_39, _pooled_T_38}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_lo_hi = {pooled_lo_lo_lo_hi_hi, pooled_lo_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_lo_lo = {pooled_lo_lo_lo_hi, pooled_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_lo_lo = {_pooled_T_41, _pooled_T_40}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_lo_hi = {_pooled_T_43, _pooled_T_42}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_hi_lo = {pooled_lo_lo_hi_lo_hi, pooled_lo_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_hi_lo = {_pooled_T_45, _pooled_T_44}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi_hi_hi = {_pooled_T_47, _pooled_T_46}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo_hi_hi = {pooled_lo_lo_hi_hi_hi, pooled_lo_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_lo_hi = {pooled_lo_lo_hi_hi, pooled_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_lo_lo = {pooled_lo_lo_hi, pooled_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_lo_lo = {_pooled_T_49, _pooled_T_48}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_lo_hi = {_pooled_T_51, _pooled_T_50}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_lo_lo = {pooled_lo_hi_lo_lo_hi, pooled_lo_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_hi_lo = {_pooled_T_53, _pooled_T_52}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo_hi_hi = {_pooled_T_55, _pooled_T_54}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_lo_hi = {pooled_lo_hi_lo_hi_hi, pooled_lo_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_hi_lo = {pooled_lo_hi_lo_hi, pooled_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_lo_lo = {_pooled_T_57, _pooled_T_56}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_lo_hi = {_pooled_T_59, _pooled_T_58}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_hi_lo = {pooled_lo_hi_hi_lo_hi, pooled_lo_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_hi_lo = {_pooled_T_61, _pooled_T_60}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi_hi_hi = {_pooled_T_63, _pooled_T_62}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi_hi_hi = {pooled_lo_hi_hi_hi_hi, pooled_lo_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo_hi_hi = {pooled_lo_hi_hi_hi, pooled_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_lo_hi = {pooled_lo_hi_hi, pooled_lo_hi_lo}; // @[DMA.scala:596:97] wire [255:0] pooled_lo = {pooled_lo_hi, pooled_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_lo_lo = {_pooled_T_65, _pooled_T_64}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_lo_hi = {_pooled_T_67, _pooled_T_66}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_lo_lo = {pooled_hi_lo_lo_lo_hi, pooled_hi_lo_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_hi_lo = {_pooled_T_69, _pooled_T_68}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo_hi_hi = {_pooled_T_71, _pooled_T_70}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_lo_hi = {pooled_hi_lo_lo_hi_hi, pooled_hi_lo_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_lo_lo = {pooled_hi_lo_lo_hi, pooled_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_lo_lo = {_pooled_T_73, _pooled_T_72}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_lo_hi = {_pooled_T_75, _pooled_T_74}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_hi_lo = {pooled_hi_lo_hi_lo_hi, pooled_hi_lo_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_hi_lo = {_pooled_T_77, _pooled_T_76}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi_hi_hi = {_pooled_T_79, _pooled_T_78}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo_hi_hi = {pooled_hi_lo_hi_hi_hi, pooled_hi_lo_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_lo_hi = {pooled_hi_lo_hi_hi, pooled_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_hi_lo = {pooled_hi_lo_hi, pooled_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_lo_lo = {_pooled_T_81, _pooled_T_80}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_lo_hi = {_pooled_T_83, _pooled_T_82}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_lo_lo = {pooled_hi_hi_lo_lo_hi, pooled_hi_hi_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_hi_lo = {_pooled_T_85, _pooled_T_84}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo_hi_hi = {_pooled_T_87, _pooled_T_86}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_lo_hi = {pooled_hi_hi_lo_hi_hi, pooled_hi_hi_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_hi_lo = {pooled_hi_hi_lo_hi, pooled_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_lo_lo = {_pooled_T_89, _pooled_T_88}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_lo_hi = {_pooled_T_91, _pooled_T_90}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_hi_lo = {pooled_hi_hi_hi_lo_hi, pooled_hi_hi_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_hi_lo = {_pooled_T_93, _pooled_T_92}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi_hi_hi = {_pooled_T_95, _pooled_T_94}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi_hi_hi = {pooled_hi_hi_hi_hi_hi, pooled_hi_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi_hi_hi = {pooled_hi_hi_hi_hi, pooled_hi_hi_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled_hi_hi = {pooled_hi_hi_hi, pooled_hi_hi_lo}; // @[DMA.scala:596:97] wire [255:0] pooled_hi = {pooled_hi_hi, pooled_hi_lo}; // @[DMA.scala:596:97] wire [511:0] pooled = {pooled_hi, pooled_lo}; // @[DMA.scala:596:97] wire [12:0] _req_len_T = {1'h0, io_req_bits_block_0, 4'h0}; // @[DMA.scala:360:9, :600:36] wire [13:0] _req_len_T_1 = {1'h0, _req_len_T} + {7'h0, io_req_bits_len_0}; // @[DMA.scala:360:9, :600:{36,58}] wire [12:0] _req_len_T_2 = _req_len_T_1[12:0]; // @[DMA.scala:600:58] wire [511:0] _data_single_block_T = io_req_bits_pool_en_0 ? pooled : io_req_bits_data_0; // @[DMA.scala:360:9, :596:97, :602:31] wire [1:0] _state_T = {1'h0, io_req_bits_store_en_0}; // @[DMA.scala:360:9, :607:19]

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied

module IssueSlot( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]

Generate the Verilog code corresponding to this FIRRTL code module TageBranchPredictorBank_3 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire f3_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} node _T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node lo = cat(_T_1, _T) node hi = cat(_T_3, _T_2) node _T_4 = cat(hi, lo) node lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _T_5 = cat(hi_1, lo_1) node lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _T_6 = cat(hi_2, lo_2) node lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _T_7 = cat(hi_3, lo_3) node _T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node lo_4 = cat(_T_9, _T_8) node hi_4 = cat(_T_11, _T_10) node _T_12 = cat(hi_4, lo_4) node lo_5 = cat(_T_5, _T_4) node hi_hi = cat(_T_12, _T_7) node hi_5 = cat(hi_hi, _T_6) node _T_13 = cat(hi_5, lo_5) inst tt_0_1 of TageTable_18 connect tt_0_1.clock, clock connect tt_0_1.reset, reset reg t_io_f1_req_valid_REG : UInt<1>, clock connect t_io_f1_req_valid_REG, io.f0_valid connect tt_0_1.io.f1_req_valid, t_io_f1_req_valid_REG reg t_io_f1_req_pc_REG : UInt, clock connect t_io_f1_req_pc_REG, io.f0_pc connect tt_0_1.io.f1_req_pc, t_io_f1_req_pc_REG connect tt_0_1.io.f1_req_ghist, io.f1_ghist inst tt_1_1 of TageTable_19 connect tt_1_1.clock, clock connect tt_1_1.reset, reset reg t_io_f1_req_valid_REG_1 : UInt<1>, clock connect t_io_f1_req_valid_REG_1, io.f0_valid connect tt_1_1.io.f1_req_valid, t_io_f1_req_valid_REG_1 reg t_io_f1_req_pc_REG_1 : UInt, clock connect t_io_f1_req_pc_REG_1, io.f0_pc connect tt_1_1.io.f1_req_pc, t_io_f1_req_pc_REG_1 connect tt_1_1.io.f1_req_ghist, io.f1_ghist inst tt_2_1 of TageTable_20 connect tt_2_1.clock, clock connect tt_2_1.reset, reset reg t_io_f1_req_valid_REG_2 : UInt<1>, clock connect t_io_f1_req_valid_REG_2, io.f0_valid connect tt_2_1.io.f1_req_valid, t_io_f1_req_valid_REG_2 reg t_io_f1_req_pc_REG_2 : UInt, clock connect t_io_f1_req_pc_REG_2, io.f0_pc connect tt_2_1.io.f1_req_pc, t_io_f1_req_pc_REG_2 connect tt_2_1.io.f1_req_ghist, io.f1_ghist inst tt_3_1 of TageTable_21 connect tt_3_1.clock, clock connect tt_3_1.reset, reset reg t_io_f1_req_valid_REG_3 : UInt<1>, clock connect t_io_f1_req_valid_REG_3, io.f0_valid connect tt_3_1.io.f1_req_valid, t_io_f1_req_valid_REG_3 reg t_io_f1_req_pc_REG_3 : UInt, clock connect t_io_f1_req_pc_REG_3, io.f0_pc connect tt_3_1.io.f1_req_pc, t_io_f1_req_pc_REG_3 connect tt_3_1.io.f1_req_ghist, io.f1_ghist inst tt_4_1 of TageTable_22 connect tt_4_1.clock, clock connect tt_4_1.reset, reset reg t_io_f1_req_valid_REG_4 : UInt<1>, clock connect t_io_f1_req_valid_REG_4, io.f0_valid connect tt_4_1.io.f1_req_valid, t_io_f1_req_valid_REG_4 reg t_io_f1_req_pc_REG_4 : UInt, clock connect t_io_f1_req_pc_REG_4, io.f0_pc connect tt_4_1.io.f1_req_pc, t_io_f1_req_pc_REG_4 connect tt_4_1.io.f1_req_ghist, io.f1_ghist inst tt_5_1 of TageTable_23 connect tt_5_1.clock, clock connect tt_5_1.reset, reset reg t_io_f1_req_valid_REG_5 : UInt<1>, clock connect t_io_f1_req_valid_REG_5, io.f0_valid connect tt_5_1.io.f1_req_valid, t_io_f1_req_valid_REG_5 reg t_io_f1_req_pc_REG_5 : UInt, clock connect t_io_f1_req_pc_REG_5, io.f0_pc connect tt_5_1.io.f1_req_pc, t_io_f1_req_pc_REG_5 connect tt_5_1.io.f1_req_ghist, io.f1_ghist wire f3_resps : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4][6] connect f3_resps[0], tt_0_1.io.f3_resp connect f3_resps[1], tt_1_1.io.f3_resp connect f3_resps[2], tt_2_1.io.f3_resp connect f3_resps[3], tt_3_1.io.f3_resp connect f3_resps[4], tt_4_1.io.f3_resp connect f3_resps[5], tt_5_1.io.f3_resp wire s1_update_meta : { provider : { valid : UInt<1>, bits : UInt<3>}[4], alt_differs : UInt<1>[4], provider_u : UInt<2>[4], provider_ctr : UInt<3>[4], allocate : { valid : UInt<1>, bits : UInt<3>}[4]} wire _s1_update_meta_WIRE : UInt<56> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 2, 0) connect s1_update_meta.allocate[0].bits, _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 3) connect s1_update_meta.allocate[0].valid, _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 6, 4) connect s1_update_meta.allocate[1].bits, _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 7) connect s1_update_meta.allocate[1].valid, _s1_update_meta_T_3 node _s1_update_meta_T_4 = bits(_s1_update_meta_WIRE, 10, 8) connect s1_update_meta.allocate[2].bits, _s1_update_meta_T_4 node _s1_update_meta_T_5 = bits(_s1_update_meta_WIRE, 11, 11) connect s1_update_meta.allocate[2].valid, _s1_update_meta_T_5 node _s1_update_meta_T_6 = bits(_s1_update_meta_WIRE, 14, 12) connect s1_update_meta.allocate[3].bits, _s1_update_meta_T_6 node _s1_update_meta_T_7 = bits(_s1_update_meta_WIRE, 15, 15) connect s1_update_meta.allocate[3].valid, _s1_update_meta_T_7 node _s1_update_meta_T_8 = bits(_s1_update_meta_WIRE, 18, 16) connect s1_update_meta.provider_ctr[0], _s1_update_meta_T_8 node _s1_update_meta_T_9 = bits(_s1_update_meta_WIRE, 21, 19) connect s1_update_meta.provider_ctr[1], _s1_update_meta_T_9 node _s1_update_meta_T_10 = bits(_s1_update_meta_WIRE, 24, 22) connect s1_update_meta.provider_ctr[2], _s1_update_meta_T_10 node _s1_update_meta_T_11 = bits(_s1_update_meta_WIRE, 27, 25) connect s1_update_meta.provider_ctr[3], _s1_update_meta_T_11 node _s1_update_meta_T_12 = bits(_s1_update_meta_WIRE, 29, 28) connect s1_update_meta.provider_u[0], _s1_update_meta_T_12 node _s1_update_meta_T_13 = bits(_s1_update_meta_WIRE, 31, 30) connect s1_update_meta.provider_u[1], _s1_update_meta_T_13 node _s1_update_meta_T_14 = bits(_s1_update_meta_WIRE, 33, 32) connect s1_update_meta.provider_u[2], _s1_update_meta_T_14 node _s1_update_meta_T_15 = bits(_s1_update_meta_WIRE, 35, 34) connect s1_update_meta.provider_u[3], _s1_update_meta_T_15 node _s1_update_meta_T_16 = bits(_s1_update_meta_WIRE, 36, 36) connect s1_update_meta.alt_differs[0], _s1_update_meta_T_16 node _s1_update_meta_T_17 = bits(_s1_update_meta_WIRE, 37, 37) connect s1_update_meta.alt_differs[1], _s1_update_meta_T_17 node _s1_update_meta_T_18 = bits(_s1_update_meta_WIRE, 38, 38) connect s1_update_meta.alt_differs[2], _s1_update_meta_T_18 node _s1_update_meta_T_19 = bits(_s1_update_meta_WIRE, 39, 39) connect s1_update_meta.alt_differs[3], _s1_update_meta_T_19 node _s1_update_meta_T_20 = bits(_s1_update_meta_WIRE, 42, 40) connect s1_update_meta.provider[0].bits, _s1_update_meta_T_20 node _s1_update_meta_T_21 = bits(_s1_update_meta_WIRE, 43, 43) connect s1_update_meta.provider[0].valid, _s1_update_meta_T_21 node _s1_update_meta_T_22 = bits(_s1_update_meta_WIRE, 46, 44) connect s1_update_meta.provider[1].bits, _s1_update_meta_T_22 node _s1_update_meta_T_23 = bits(_s1_update_meta_WIRE, 47, 47) connect s1_update_meta.provider[1].valid, _s1_update_meta_T_23 node _s1_update_meta_T_24 = bits(_s1_update_meta_WIRE, 50, 48) connect s1_update_meta.provider[2].bits, _s1_update_meta_T_24 node _s1_update_meta_T_25 = bits(_s1_update_meta_WIRE, 51, 51) connect s1_update_meta.provider[2].valid, _s1_update_meta_T_25 node _s1_update_meta_T_26 = bits(_s1_update_meta_WIRE, 54, 52) connect s1_update_meta.provider[3].bits, _s1_update_meta_T_26 node _s1_update_meta_T_27 = bits(_s1_update_meta_WIRE, 55, 55) connect s1_update_meta.provider[3].valid, _s1_update_meta_T_27 node _s1_update_mispredict_mask_T = dshl(UInt<1>(0h1), s1_update.bits.cfi_idx.bits) node _s1_update_mispredict_mask_T_1 = mux(s1_update.bits.cfi_mispredicted, UInt<4>(0hf), UInt<4>(0h0)) node s1_update_mispredict_mask = and(_s1_update_mispredict_mask_T, _s1_update_mispredict_mask_T_1) wire _s1_update_mask_WIRE : UInt<1>[4][6] connect _s1_update_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_mask : UInt<1>[4][6] connect s1_update_mask, _s1_update_mask_WIRE wire _s1_update_u_mask_WIRE : UInt<1>[4][6] connect _s1_update_u_mask_WIRE[0][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[0][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[1][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[2][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[3][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[4][3], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][0], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][1], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][2], UInt<1>(0h0) connect _s1_update_u_mask_WIRE[5][3], UInt<1>(0h0) wire s1_update_u_mask : UInt<1>[4][6] connect s1_update_u_mask, _s1_update_u_mask_WIRE wire s1_update_taken : UInt<1>[4][6] wire s1_update_old_ctr : UInt<3>[4][6] wire s1_update_alloc : UInt<1>[4][6] wire s1_update_u : UInt<2>[4][6] invalidate s1_update_taken[0][0] invalidate s1_update_taken[0][1] invalidate s1_update_taken[0][2] invalidate s1_update_taken[0][3] invalidate s1_update_taken[1][0] invalidate s1_update_taken[1][1] invalidate s1_update_taken[1][2] invalidate s1_update_taken[1][3] invalidate s1_update_taken[2][0] invalidate s1_update_taken[2][1] invalidate s1_update_taken[2][2] invalidate s1_update_taken[2][3] invalidate s1_update_taken[3][0] invalidate s1_update_taken[3][1] invalidate s1_update_taken[3][2] invalidate s1_update_taken[3][3] invalidate s1_update_taken[4][0] invalidate s1_update_taken[4][1] invalidate s1_update_taken[4][2] invalidate s1_update_taken[4][3] invalidate s1_update_taken[5][0] invalidate s1_update_taken[5][1] invalidate s1_update_taken[5][2] invalidate s1_update_taken[5][3] invalidate s1_update_old_ctr[0][0] invalidate s1_update_old_ctr[0][1] invalidate s1_update_old_ctr[0][2] invalidate s1_update_old_ctr[0][3] invalidate s1_update_old_ctr[1][0] invalidate s1_update_old_ctr[1][1] invalidate s1_update_old_ctr[1][2] invalidate s1_update_old_ctr[1][3] invalidate s1_update_old_ctr[2][0] invalidate s1_update_old_ctr[2][1] invalidate s1_update_old_ctr[2][2] invalidate s1_update_old_ctr[2][3] invalidate s1_update_old_ctr[3][0] invalidate s1_update_old_ctr[3][1] invalidate s1_update_old_ctr[3][2] invalidate s1_update_old_ctr[3][3] invalidate s1_update_old_ctr[4][0] invalidate s1_update_old_ctr[4][1] invalidate s1_update_old_ctr[4][2] invalidate s1_update_old_ctr[4][3] invalidate s1_update_old_ctr[5][0] invalidate s1_update_old_ctr[5][1] invalidate s1_update_old_ctr[5][2] invalidate s1_update_old_ctr[5][3] invalidate s1_update_alloc[0][0] invalidate s1_update_alloc[0][1] invalidate s1_update_alloc[0][2] invalidate s1_update_alloc[0][3] invalidate s1_update_alloc[1][0] invalidate s1_update_alloc[1][1] invalidate s1_update_alloc[1][2] invalidate s1_update_alloc[1][3] invalidate s1_update_alloc[2][0] invalidate s1_update_alloc[2][1] invalidate s1_update_alloc[2][2] invalidate s1_update_alloc[2][3] invalidate s1_update_alloc[3][0] invalidate s1_update_alloc[3][1] invalidate s1_update_alloc[3][2] invalidate s1_update_alloc[3][3] invalidate s1_update_alloc[4][0] invalidate s1_update_alloc[4][1] invalidate s1_update_alloc[4][2] invalidate s1_update_alloc[4][3] invalidate s1_update_alloc[5][0] invalidate s1_update_alloc[5][1] invalidate s1_update_alloc[5][2] invalidate s1_update_alloc[5][3] invalidate s1_update_u[0][0] invalidate s1_update_u[0][1] invalidate s1_update_u[0][2] invalidate s1_update_u[0][3] invalidate s1_update_u[1][0] invalidate s1_update_u[1][1] invalidate s1_update_u[1][2] invalidate s1_update_u[1][3] invalidate s1_update_u[2][0] invalidate s1_update_u[2][1] invalidate s1_update_u[2][2] invalidate s1_update_u[2][3] invalidate s1_update_u[3][0] invalidate s1_update_u[3][1] invalidate s1_update_u[3][2] invalidate s1_update_u[3][3] invalidate s1_update_u[4][0] invalidate s1_update_u[4][1] invalidate s1_update_u[4][2] invalidate s1_update_u[4][3] invalidate s1_update_u[5][0] invalidate s1_update_u[5][1] invalidate s1_update_u[5][2] invalidate s1_update_u[5][3] wire final_altpred : UInt<1> connect final_altpred, io.resp_in[0].f3[0].taken connect io.resp.f3[0].taken, io.resp_in[0].f3[0].taken when f3_resps[0][0].valid : node _io_resp_f3_0_taken_T = eq(f3_resps[0][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_1 = eq(f3_resps[0][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_2 = or(_io_resp_f3_0_taken_T, _io_resp_f3_0_taken_T_1) node _io_resp_f3_0_taken_T_3 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_4 = mux(_io_resp_f3_0_taken_T_2, io.resp_in[0].f3[0].taken, _io_resp_f3_0_taken_T_3) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_4 connect final_altpred, io.resp_in[0].f3[0].taken node _T_14 = or(UInt<1>(0h0), f3_resps[0][0].valid) node _T_15 = mux(f3_resps[0][0].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_16 = bits(f3_resps[0][0].bits.ctr, 2, 2) node _T_17 = mux(f3_resps[0][0].valid, _T_16, io.resp_in[0].f3[0].taken) when f3_resps[1][0].valid : node _io_resp_f3_0_taken_T_5 = eq(f3_resps[1][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_6 = eq(f3_resps[1][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_7 = or(_io_resp_f3_0_taken_T_5, _io_resp_f3_0_taken_T_6) node _io_resp_f3_0_taken_T_8 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_9 = mux(_io_resp_f3_0_taken_T_7, _T_17, _io_resp_f3_0_taken_T_8) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_9 connect final_altpred, _T_17 node _T_18 = or(_T_14, f3_resps[1][0].valid) node _T_19 = mux(f3_resps[1][0].valid, UInt<1>(0h1), _T_15) node _T_20 = bits(f3_resps[1][0].bits.ctr, 2, 2) node _T_21 = mux(f3_resps[1][0].valid, _T_20, _T_17) when f3_resps[2][0].valid : node _io_resp_f3_0_taken_T_10 = eq(f3_resps[2][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_11 = eq(f3_resps[2][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_12 = or(_io_resp_f3_0_taken_T_10, _io_resp_f3_0_taken_T_11) node _io_resp_f3_0_taken_T_13 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_14 = mux(_io_resp_f3_0_taken_T_12, _T_21, _io_resp_f3_0_taken_T_13) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_14 connect final_altpred, _T_21 node _T_22 = or(_T_18, f3_resps[2][0].valid) node _T_23 = mux(f3_resps[2][0].valid, UInt<2>(0h2), _T_19) node _T_24 = bits(f3_resps[2][0].bits.ctr, 2, 2) node _T_25 = mux(f3_resps[2][0].valid, _T_24, _T_21) when f3_resps[3][0].valid : node _io_resp_f3_0_taken_T_15 = eq(f3_resps[3][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_16 = eq(f3_resps[3][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_17 = or(_io_resp_f3_0_taken_T_15, _io_resp_f3_0_taken_T_16) node _io_resp_f3_0_taken_T_18 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_19 = mux(_io_resp_f3_0_taken_T_17, _T_25, _io_resp_f3_0_taken_T_18) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_19 connect final_altpred, _T_25 node _T_26 = or(_T_22, f3_resps[3][0].valid) node _T_27 = mux(f3_resps[3][0].valid, UInt<2>(0h3), _T_23) node _T_28 = bits(f3_resps[3][0].bits.ctr, 2, 2) node _T_29 = mux(f3_resps[3][0].valid, _T_28, _T_25) when f3_resps[4][0].valid : node _io_resp_f3_0_taken_T_20 = eq(f3_resps[4][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_21 = eq(f3_resps[4][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_22 = or(_io_resp_f3_0_taken_T_20, _io_resp_f3_0_taken_T_21) node _io_resp_f3_0_taken_T_23 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_24 = mux(_io_resp_f3_0_taken_T_22, _T_29, _io_resp_f3_0_taken_T_23) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_24 connect final_altpred, _T_29 node _T_30 = or(_T_26, f3_resps[4][0].valid) node _T_31 = mux(f3_resps[4][0].valid, UInt<3>(0h4), _T_27) node _T_32 = bits(f3_resps[4][0].bits.ctr, 2, 2) node _T_33 = mux(f3_resps[4][0].valid, _T_32, _T_29) when f3_resps[5][0].valid : node _io_resp_f3_0_taken_T_25 = eq(f3_resps[5][0].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_0_taken_T_26 = eq(f3_resps[5][0].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_0_taken_T_27 = or(_io_resp_f3_0_taken_T_25, _io_resp_f3_0_taken_T_26) node _io_resp_f3_0_taken_T_28 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _io_resp_f3_0_taken_T_29 = mux(_io_resp_f3_0_taken_T_27, _T_33, _io_resp_f3_0_taken_T_28) connect io.resp.f3[0].taken, _io_resp_f3_0_taken_T_29 connect final_altpred, _T_33 node _T_34 = or(_T_30, f3_resps[5][0].valid) node _T_35 = mux(f3_resps[5][0].valid, UInt<3>(0h5), _T_31) node _T_36 = bits(f3_resps[5][0].bits.ctr, 2, 2) node _T_37 = mux(f3_resps[5][0].valid, _T_36, _T_33) connect f3_meta.provider[0].valid, _T_34 connect f3_meta.provider[0].bits, _T_35 node _f3_meta_alt_differs_0_T = neq(final_altpred, io.resp.f3[0].taken) connect f3_meta.alt_differs[0], _f3_meta_alt_differs_0_T connect f3_meta.provider_u[0], f3_resps[_T_35][0].bits.u connect f3_meta.provider_ctr[0], f3_resps[_T_35][0].bits.ctr node _allocatable_slots_T = eq(f3_resps[0][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_1 = eq(f3_resps[0][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_2 = and(_allocatable_slots_T, _allocatable_slots_T_1) node _allocatable_slots_T_3 = eq(f3_resps[1][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_4 = eq(f3_resps[1][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_5 = and(_allocatable_slots_T_3, _allocatable_slots_T_4) node _allocatable_slots_T_6 = eq(f3_resps[2][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_7 = eq(f3_resps[2][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_8 = and(_allocatable_slots_T_6, _allocatable_slots_T_7) node _allocatable_slots_T_9 = eq(f3_resps[3][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_10 = eq(f3_resps[3][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_11 = and(_allocatable_slots_T_9, _allocatable_slots_T_10) node _allocatable_slots_T_12 = eq(f3_resps[4][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_13 = eq(f3_resps[4][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_14 = and(_allocatable_slots_T_12, _allocatable_slots_T_13) node _allocatable_slots_T_15 = eq(f3_resps[5][0].valid, UInt<1>(0h0)) node _allocatable_slots_T_16 = eq(f3_resps[5][0].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_17 = and(_allocatable_slots_T_15, _allocatable_slots_T_16) wire _allocatable_slots_WIRE : UInt<1>[6] connect _allocatable_slots_WIRE[0], _allocatable_slots_T_2 connect _allocatable_slots_WIRE[1], _allocatable_slots_T_5 connect _allocatable_slots_WIRE[2], _allocatable_slots_T_8 connect _allocatable_slots_WIRE[3], _allocatable_slots_T_11 connect _allocatable_slots_WIRE[4], _allocatable_slots_T_14 connect _allocatable_slots_WIRE[5], _allocatable_slots_T_17 node allocatable_slots_lo_hi = cat(_allocatable_slots_WIRE[2], _allocatable_slots_WIRE[1]) node allocatable_slots_lo = cat(allocatable_slots_lo_hi, _allocatable_slots_WIRE[0]) node allocatable_slots_hi_hi = cat(_allocatable_slots_WIRE[5], _allocatable_slots_WIRE[4]) node allocatable_slots_hi = cat(allocatable_slots_hi_hi, _allocatable_slots_WIRE[3]) node _allocatable_slots_T_18 = cat(allocatable_slots_hi, allocatable_slots_lo) node _allocatable_slots_T_19 = dshl(UInt<1>(0h1), _T_35) node _allocatable_slots_T_20 = dshr(_allocatable_slots_T_19, UInt<1>(0h0)) node _allocatable_slots_T_21 = dshr(_allocatable_slots_T_19, UInt<1>(0h1)) node _allocatable_slots_T_22 = dshr(_allocatable_slots_T_19, UInt<2>(0h2)) node _allocatable_slots_T_23 = dshr(_allocatable_slots_T_19, UInt<2>(0h3)) node _allocatable_slots_T_24 = dshr(_allocatable_slots_T_19, UInt<3>(0h4)) node _allocatable_slots_T_25 = dshr(_allocatable_slots_T_19, UInt<3>(0h5)) node _allocatable_slots_T_26 = dshr(_allocatable_slots_T_19, UInt<3>(0h6)) node _allocatable_slots_T_27 = dshr(_allocatable_slots_T_19, UInt<3>(0h7)) node _allocatable_slots_T_28 = or(_allocatable_slots_T_20, _allocatable_slots_T_21) node _allocatable_slots_T_29 = or(_allocatable_slots_T_28, _allocatable_slots_T_22) node _allocatable_slots_T_30 = or(_allocatable_slots_T_29, _allocatable_slots_T_23) node _allocatable_slots_T_31 = or(_allocatable_slots_T_30, _allocatable_slots_T_24) node _allocatable_slots_T_32 = or(_allocatable_slots_T_31, _allocatable_slots_T_25) node _allocatable_slots_T_33 = or(_allocatable_slots_T_32, _allocatable_slots_T_26) node _allocatable_slots_T_34 = or(_allocatable_slots_T_33, _allocatable_slots_T_27) node _allocatable_slots_T_35 = mux(_T_34, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_36 = and(_allocatable_slots_T_34, _allocatable_slots_T_35) node _allocatable_slots_T_37 = not(_allocatable_slots_T_36) node allocatable_slots = and(_allocatable_slots_T_18, _allocatable_slots_T_37) inst alloc_lfsr_prng of MaxPeriodFibonacciLFSR_21 connect alloc_lfsr_prng.clock, clock connect alloc_lfsr_prng.reset, reset connect alloc_lfsr_prng.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng.io.seed.bits[0] invalidate alloc_lfsr_prng.io.seed.bits[1] invalidate alloc_lfsr_prng.io.seed.bits[2] invalidate alloc_lfsr_prng.io.seed.bits[3] invalidate alloc_lfsr_prng.io.seed.bits[4] invalidate alloc_lfsr_prng.io.seed.bits[5] connect alloc_lfsr_prng.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi = cat(alloc_lfsr_prng.io.out[2], alloc_lfsr_prng.io.out[1]) node alloc_lfsr_lo = cat(alloc_lfsr_lo_hi, alloc_lfsr_prng.io.out[0]) node alloc_lfsr_hi_hi = cat(alloc_lfsr_prng.io.out[5], alloc_lfsr_prng.io.out[4]) node alloc_lfsr_hi = cat(alloc_lfsr_hi_hi, alloc_lfsr_prng.io.out[3]) node alloc_lfsr = cat(alloc_lfsr_hi, alloc_lfsr_lo) node _first_entry_T = bits(allocatable_slots, 0, 0) node _first_entry_T_1 = bits(allocatable_slots, 1, 1) node _first_entry_T_2 = bits(allocatable_slots, 2, 2) node _first_entry_T_3 = bits(allocatable_slots, 3, 3) node _first_entry_T_4 = bits(allocatable_slots, 4, 4) node _first_entry_T_5 = bits(allocatable_slots, 5, 5) node _first_entry_T_6 = bits(allocatable_slots, 6, 6) node _first_entry_T_7 = bits(allocatable_slots, 7, 7) node _first_entry_T_8 = mux(_first_entry_T_6, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_9 = mux(_first_entry_T_5, UInt<3>(0h5), _first_entry_T_8) node _first_entry_T_10 = mux(_first_entry_T_4, UInt<3>(0h4), _first_entry_T_9) node _first_entry_T_11 = mux(_first_entry_T_3, UInt<2>(0h3), _first_entry_T_10) node _first_entry_T_12 = mux(_first_entry_T_2, UInt<2>(0h2), _first_entry_T_11) node _first_entry_T_13 = mux(_first_entry_T_1, UInt<1>(0h1), _first_entry_T_12) node first_entry = mux(_first_entry_T, UInt<1>(0h0), _first_entry_T_13) node _masked_entry_T = and(allocatable_slots, alloc_lfsr) node _masked_entry_T_1 = bits(_masked_entry_T, 0, 0) node _masked_entry_T_2 = bits(_masked_entry_T, 1, 1) node _masked_entry_T_3 = bits(_masked_entry_T, 2, 2) node _masked_entry_T_4 = bits(_masked_entry_T, 3, 3) node _masked_entry_T_5 = bits(_masked_entry_T, 4, 4) node _masked_entry_T_6 = bits(_masked_entry_T, 5, 5) node _masked_entry_T_7 = bits(_masked_entry_T, 6, 6) node _masked_entry_T_8 = bits(_masked_entry_T, 7, 7) node _masked_entry_T_9 = mux(_masked_entry_T_7, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_10 = mux(_masked_entry_T_6, UInt<3>(0h5), _masked_entry_T_9) node _masked_entry_T_11 = mux(_masked_entry_T_5, UInt<3>(0h4), _masked_entry_T_10) node _masked_entry_T_12 = mux(_masked_entry_T_4, UInt<2>(0h3), _masked_entry_T_11) node _masked_entry_T_13 = mux(_masked_entry_T_3, UInt<2>(0h2), _masked_entry_T_12) node _masked_entry_T_14 = mux(_masked_entry_T_2, UInt<1>(0h1), _masked_entry_T_13) node masked_entry = mux(_masked_entry_T_1, UInt<1>(0h0), _masked_entry_T_14) node _alloc_entry_T = dshr(allocatable_slots, masked_entry) node _alloc_entry_T_1 = bits(_alloc_entry_T, 0, 0) node alloc_entry = mux(_alloc_entry_T_1, masked_entry, first_entry) node _f3_meta_allocate_0_valid_T = neq(allocatable_slots, UInt<1>(0h0)) connect f3_meta.allocate[0].valid, _f3_meta_allocate_0_valid_T connect f3_meta.allocate[0].bits, alloc_entry node _update_was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _update_was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T) node update_was_taken = and(_update_was_taken_T_1, s1_update.bits.cfi_taken) node _T_38 = bits(s1_update.bits.br_mask, 0, 0) node _T_39 = and(_T_38, s1_update.valid) node _T_40 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_41 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = and(_T_39, _T_43) when _T_44 : when s1_update_meta.provider[0].valid : connect s1_update_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[0].bits][0], UInt<1>(0h1) node _new_u_T = bits(s1_update_mispredict_mask, 0, 0) node _new_u_T_1 = eq(s1_update_meta.alt_differs[0], UInt<1>(0h0)) node _new_u_T_2 = eq(s1_update_meta.provider_u[0], UInt<1>(0h0)) node _new_u_T_3 = sub(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_4 = tail(_new_u_T_3, 1) node _new_u_T_5 = mux(_new_u_T_2, UInt<1>(0h0), _new_u_T_4) node _new_u_T_6 = eq(s1_update_meta.provider_u[0], UInt<2>(0h3)) node _new_u_T_7 = add(s1_update_meta.provider_u[0], UInt<1>(0h1)) node _new_u_T_8 = tail(_new_u_T_7, 1) node _new_u_T_9 = mux(_new_u_T_6, UInt<2>(0h3), _new_u_T_8) node _new_u_T_10 = mux(_new_u_T, _new_u_T_5, _new_u_T_9) node new_u = mux(_new_u_T_1, s1_update_meta.provider_u[0], _new_u_T_10) connect s1_update_u[s1_update_meta.provider[0].bits][0], new_u connect s1_update_taken[s1_update_meta.provider[0].bits][0], update_was_taken connect s1_update_old_ctr[s1_update_meta.provider[0].bits][0], s1_update_meta.provider_ctr[0] connect s1_update_alloc[s1_update_meta.provider[0].bits][0], UInt<1>(0h0) wire final_altpred_1 : UInt<1> connect final_altpred_1, io.resp_in[0].f3[1].taken connect io.resp.f3[1].taken, io.resp_in[0].f3[1].taken when f3_resps[0][1].valid : node _io_resp_f3_1_taken_T = eq(f3_resps[0][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_1 = eq(f3_resps[0][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_2 = or(_io_resp_f3_1_taken_T, _io_resp_f3_1_taken_T_1) node _io_resp_f3_1_taken_T_3 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_4 = mux(_io_resp_f3_1_taken_T_2, io.resp_in[0].f3[1].taken, _io_resp_f3_1_taken_T_3) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_4 connect final_altpred_1, io.resp_in[0].f3[1].taken node _T_45 = or(UInt<1>(0h0), f3_resps[0][1].valid) node _T_46 = mux(f3_resps[0][1].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = bits(f3_resps[0][1].bits.ctr, 2, 2) node _T_48 = mux(f3_resps[0][1].valid, _T_47, io.resp_in[0].f3[1].taken) when f3_resps[1][1].valid : node _io_resp_f3_1_taken_T_5 = eq(f3_resps[1][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_6 = eq(f3_resps[1][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_7 = or(_io_resp_f3_1_taken_T_5, _io_resp_f3_1_taken_T_6) node _io_resp_f3_1_taken_T_8 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_9 = mux(_io_resp_f3_1_taken_T_7, _T_48, _io_resp_f3_1_taken_T_8) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_9 connect final_altpred_1, _T_48 node _T_49 = or(_T_45, f3_resps[1][1].valid) node _T_50 = mux(f3_resps[1][1].valid, UInt<1>(0h1), _T_46) node _T_51 = bits(f3_resps[1][1].bits.ctr, 2, 2) node _T_52 = mux(f3_resps[1][1].valid, _T_51, _T_48) when f3_resps[2][1].valid : node _io_resp_f3_1_taken_T_10 = eq(f3_resps[2][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_11 = eq(f3_resps[2][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_12 = or(_io_resp_f3_1_taken_T_10, _io_resp_f3_1_taken_T_11) node _io_resp_f3_1_taken_T_13 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_14 = mux(_io_resp_f3_1_taken_T_12, _T_52, _io_resp_f3_1_taken_T_13) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_14 connect final_altpred_1, _T_52 node _T_53 = or(_T_49, f3_resps[2][1].valid) node _T_54 = mux(f3_resps[2][1].valid, UInt<2>(0h2), _T_50) node _T_55 = bits(f3_resps[2][1].bits.ctr, 2, 2) node _T_56 = mux(f3_resps[2][1].valid, _T_55, _T_52) when f3_resps[3][1].valid : node _io_resp_f3_1_taken_T_15 = eq(f3_resps[3][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_16 = eq(f3_resps[3][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_17 = or(_io_resp_f3_1_taken_T_15, _io_resp_f3_1_taken_T_16) node _io_resp_f3_1_taken_T_18 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_19 = mux(_io_resp_f3_1_taken_T_17, _T_56, _io_resp_f3_1_taken_T_18) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_19 connect final_altpred_1, _T_56 node _T_57 = or(_T_53, f3_resps[3][1].valid) node _T_58 = mux(f3_resps[3][1].valid, UInt<2>(0h3), _T_54) node _T_59 = bits(f3_resps[3][1].bits.ctr, 2, 2) node _T_60 = mux(f3_resps[3][1].valid, _T_59, _T_56) when f3_resps[4][1].valid : node _io_resp_f3_1_taken_T_20 = eq(f3_resps[4][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_21 = eq(f3_resps[4][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_22 = or(_io_resp_f3_1_taken_T_20, _io_resp_f3_1_taken_T_21) node _io_resp_f3_1_taken_T_23 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_24 = mux(_io_resp_f3_1_taken_T_22, _T_60, _io_resp_f3_1_taken_T_23) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_24 connect final_altpred_1, _T_60 node _T_61 = or(_T_57, f3_resps[4][1].valid) node _T_62 = mux(f3_resps[4][1].valid, UInt<3>(0h4), _T_58) node _T_63 = bits(f3_resps[4][1].bits.ctr, 2, 2) node _T_64 = mux(f3_resps[4][1].valid, _T_63, _T_60) when f3_resps[5][1].valid : node _io_resp_f3_1_taken_T_25 = eq(f3_resps[5][1].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_1_taken_T_26 = eq(f3_resps[5][1].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_1_taken_T_27 = or(_io_resp_f3_1_taken_T_25, _io_resp_f3_1_taken_T_26) node _io_resp_f3_1_taken_T_28 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _io_resp_f3_1_taken_T_29 = mux(_io_resp_f3_1_taken_T_27, _T_64, _io_resp_f3_1_taken_T_28) connect io.resp.f3[1].taken, _io_resp_f3_1_taken_T_29 connect final_altpred_1, _T_64 node _T_65 = or(_T_61, f3_resps[5][1].valid) node _T_66 = mux(f3_resps[5][1].valid, UInt<3>(0h5), _T_62) node _T_67 = bits(f3_resps[5][1].bits.ctr, 2, 2) node _T_68 = mux(f3_resps[5][1].valid, _T_67, _T_64) connect f3_meta.provider[1].valid, _T_65 connect f3_meta.provider[1].bits, _T_66 node _f3_meta_alt_differs_1_T = neq(final_altpred_1, io.resp.f3[1].taken) connect f3_meta.alt_differs[1], _f3_meta_alt_differs_1_T connect f3_meta.provider_u[1], f3_resps[_T_66][1].bits.u connect f3_meta.provider_ctr[1], f3_resps[_T_66][1].bits.ctr node _allocatable_slots_T_38 = eq(f3_resps[0][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_39 = eq(f3_resps[0][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_40 = and(_allocatable_slots_T_38, _allocatable_slots_T_39) node _allocatable_slots_T_41 = eq(f3_resps[1][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_42 = eq(f3_resps[1][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_43 = and(_allocatable_slots_T_41, _allocatable_slots_T_42) node _allocatable_slots_T_44 = eq(f3_resps[2][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_45 = eq(f3_resps[2][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_46 = and(_allocatable_slots_T_44, _allocatable_slots_T_45) node _allocatable_slots_T_47 = eq(f3_resps[3][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_48 = eq(f3_resps[3][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_49 = and(_allocatable_slots_T_47, _allocatable_slots_T_48) node _allocatable_slots_T_50 = eq(f3_resps[4][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_51 = eq(f3_resps[4][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_52 = and(_allocatable_slots_T_50, _allocatable_slots_T_51) node _allocatable_slots_T_53 = eq(f3_resps[5][1].valid, UInt<1>(0h0)) node _allocatable_slots_T_54 = eq(f3_resps[5][1].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_55 = and(_allocatable_slots_T_53, _allocatable_slots_T_54) wire _allocatable_slots_WIRE_1 : UInt<1>[6] connect _allocatable_slots_WIRE_1[0], _allocatable_slots_T_40 connect _allocatable_slots_WIRE_1[1], _allocatable_slots_T_43 connect _allocatable_slots_WIRE_1[2], _allocatable_slots_T_46 connect _allocatable_slots_WIRE_1[3], _allocatable_slots_T_49 connect _allocatable_slots_WIRE_1[4], _allocatable_slots_T_52 connect _allocatable_slots_WIRE_1[5], _allocatable_slots_T_55 node allocatable_slots_lo_hi_1 = cat(_allocatable_slots_WIRE_1[2], _allocatable_slots_WIRE_1[1]) node allocatable_slots_lo_1 = cat(allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1[0]) node allocatable_slots_hi_hi_1 = cat(_allocatable_slots_WIRE_1[5], _allocatable_slots_WIRE_1[4]) node allocatable_slots_hi_1 = cat(allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1[3]) node _allocatable_slots_T_56 = cat(allocatable_slots_hi_1, allocatable_slots_lo_1) node _allocatable_slots_T_57 = dshl(UInt<1>(0h1), _T_66) node _allocatable_slots_T_58 = dshr(_allocatable_slots_T_57, UInt<1>(0h0)) node _allocatable_slots_T_59 = dshr(_allocatable_slots_T_57, UInt<1>(0h1)) node _allocatable_slots_T_60 = dshr(_allocatable_slots_T_57, UInt<2>(0h2)) node _allocatable_slots_T_61 = dshr(_allocatable_slots_T_57, UInt<2>(0h3)) node _allocatable_slots_T_62 = dshr(_allocatable_slots_T_57, UInt<3>(0h4)) node _allocatable_slots_T_63 = dshr(_allocatable_slots_T_57, UInt<3>(0h5)) node _allocatable_slots_T_64 = dshr(_allocatable_slots_T_57, UInt<3>(0h6)) node _allocatable_slots_T_65 = dshr(_allocatable_slots_T_57, UInt<3>(0h7)) node _allocatable_slots_T_66 = or(_allocatable_slots_T_58, _allocatable_slots_T_59) node _allocatable_slots_T_67 = or(_allocatable_slots_T_66, _allocatable_slots_T_60) node _allocatable_slots_T_68 = or(_allocatable_slots_T_67, _allocatable_slots_T_61) node _allocatable_slots_T_69 = or(_allocatable_slots_T_68, _allocatable_slots_T_62) node _allocatable_slots_T_70 = or(_allocatable_slots_T_69, _allocatable_slots_T_63) node _allocatable_slots_T_71 = or(_allocatable_slots_T_70, _allocatable_slots_T_64) node _allocatable_slots_T_72 = or(_allocatable_slots_T_71, _allocatable_slots_T_65) node _allocatable_slots_T_73 = mux(_T_65, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_74 = and(_allocatable_slots_T_72, _allocatable_slots_T_73) node _allocatable_slots_T_75 = not(_allocatable_slots_T_74) node allocatable_slots_1 = and(_allocatable_slots_T_56, _allocatable_slots_T_75) inst alloc_lfsr_prng_1 of MaxPeriodFibonacciLFSR_22 connect alloc_lfsr_prng_1.clock, clock connect alloc_lfsr_prng_1.reset, reset connect alloc_lfsr_prng_1.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_1.io.seed.bits[0] invalidate alloc_lfsr_prng_1.io.seed.bits[1] invalidate alloc_lfsr_prng_1.io.seed.bits[2] invalidate alloc_lfsr_prng_1.io.seed.bits[3] invalidate alloc_lfsr_prng_1.io.seed.bits[4] invalidate alloc_lfsr_prng_1.io.seed.bits[5] connect alloc_lfsr_prng_1.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_1 = cat(alloc_lfsr_prng_1.io.out[2], alloc_lfsr_prng_1.io.out[1]) node alloc_lfsr_lo_1 = cat(alloc_lfsr_lo_hi_1, alloc_lfsr_prng_1.io.out[0]) node alloc_lfsr_hi_hi_1 = cat(alloc_lfsr_prng_1.io.out[5], alloc_lfsr_prng_1.io.out[4]) node alloc_lfsr_hi_1 = cat(alloc_lfsr_hi_hi_1, alloc_lfsr_prng_1.io.out[3]) node alloc_lfsr_1 = cat(alloc_lfsr_hi_1, alloc_lfsr_lo_1) node _first_entry_T_14 = bits(allocatable_slots_1, 0, 0) node _first_entry_T_15 = bits(allocatable_slots_1, 1, 1) node _first_entry_T_16 = bits(allocatable_slots_1, 2, 2) node _first_entry_T_17 = bits(allocatable_slots_1, 3, 3) node _first_entry_T_18 = bits(allocatable_slots_1, 4, 4) node _first_entry_T_19 = bits(allocatable_slots_1, 5, 5) node _first_entry_T_20 = bits(allocatable_slots_1, 6, 6) node _first_entry_T_21 = bits(allocatable_slots_1, 7, 7) node _first_entry_T_22 = mux(_first_entry_T_20, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_23 = mux(_first_entry_T_19, UInt<3>(0h5), _first_entry_T_22) node _first_entry_T_24 = mux(_first_entry_T_18, UInt<3>(0h4), _first_entry_T_23) node _first_entry_T_25 = mux(_first_entry_T_17, UInt<2>(0h3), _first_entry_T_24) node _first_entry_T_26 = mux(_first_entry_T_16, UInt<2>(0h2), _first_entry_T_25) node _first_entry_T_27 = mux(_first_entry_T_15, UInt<1>(0h1), _first_entry_T_26) node first_entry_1 = mux(_first_entry_T_14, UInt<1>(0h0), _first_entry_T_27) node _masked_entry_T_15 = and(allocatable_slots_1, alloc_lfsr_1) node _masked_entry_T_16 = bits(_masked_entry_T_15, 0, 0) node _masked_entry_T_17 = bits(_masked_entry_T_15, 1, 1) node _masked_entry_T_18 = bits(_masked_entry_T_15, 2, 2) node _masked_entry_T_19 = bits(_masked_entry_T_15, 3, 3) node _masked_entry_T_20 = bits(_masked_entry_T_15, 4, 4) node _masked_entry_T_21 = bits(_masked_entry_T_15, 5, 5) node _masked_entry_T_22 = bits(_masked_entry_T_15, 6, 6) node _masked_entry_T_23 = bits(_masked_entry_T_15, 7, 7) node _masked_entry_T_24 = mux(_masked_entry_T_22, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_25 = mux(_masked_entry_T_21, UInt<3>(0h5), _masked_entry_T_24) node _masked_entry_T_26 = mux(_masked_entry_T_20, UInt<3>(0h4), _masked_entry_T_25) node _masked_entry_T_27 = mux(_masked_entry_T_19, UInt<2>(0h3), _masked_entry_T_26) node _masked_entry_T_28 = mux(_masked_entry_T_18, UInt<2>(0h2), _masked_entry_T_27) node _masked_entry_T_29 = mux(_masked_entry_T_17, UInt<1>(0h1), _masked_entry_T_28) node masked_entry_1 = mux(_masked_entry_T_16, UInt<1>(0h0), _masked_entry_T_29) node _alloc_entry_T_2 = dshr(allocatable_slots_1, masked_entry_1) node _alloc_entry_T_3 = bits(_alloc_entry_T_2, 0, 0) node alloc_entry_1 = mux(_alloc_entry_T_3, masked_entry_1, first_entry_1) node _f3_meta_allocate_1_valid_T = neq(allocatable_slots_1, UInt<1>(0h0)) connect f3_meta.allocate[1].valid, _f3_meta_allocate_1_valid_T connect f3_meta.allocate[1].bits, alloc_entry_1 node _update_was_taken_T_2 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _update_was_taken_T_3 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_2) node update_was_taken_1 = and(_update_was_taken_T_3, s1_update.bits.cfi_taken) node _T_69 = bits(s1_update.bits.br_mask, 1, 1) node _T_70 = and(_T_69, s1_update.valid) node _T_71 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_72 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_73 = or(_T_71, _T_72) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = and(_T_70, _T_74) when _T_75 : when s1_update_meta.provider[1].valid : connect s1_update_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[1].bits][1], UInt<1>(0h1) node _new_u_T_11 = bits(s1_update_mispredict_mask, 1, 1) node _new_u_T_12 = eq(s1_update_meta.alt_differs[1], UInt<1>(0h0)) node _new_u_T_13 = eq(s1_update_meta.provider_u[1], UInt<1>(0h0)) node _new_u_T_14 = sub(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_15 = tail(_new_u_T_14, 1) node _new_u_T_16 = mux(_new_u_T_13, UInt<1>(0h0), _new_u_T_15) node _new_u_T_17 = eq(s1_update_meta.provider_u[1], UInt<2>(0h3)) node _new_u_T_18 = add(s1_update_meta.provider_u[1], UInt<1>(0h1)) node _new_u_T_19 = tail(_new_u_T_18, 1) node _new_u_T_20 = mux(_new_u_T_17, UInt<2>(0h3), _new_u_T_19) node _new_u_T_21 = mux(_new_u_T_11, _new_u_T_16, _new_u_T_20) node new_u_1 = mux(_new_u_T_12, s1_update_meta.provider_u[1], _new_u_T_21) connect s1_update_u[s1_update_meta.provider[1].bits][1], new_u_1 connect s1_update_taken[s1_update_meta.provider[1].bits][1], update_was_taken_1 connect s1_update_old_ctr[s1_update_meta.provider[1].bits][1], s1_update_meta.provider_ctr[1] connect s1_update_alloc[s1_update_meta.provider[1].bits][1], UInt<1>(0h0) wire final_altpred_2 : UInt<1> connect final_altpred_2, io.resp_in[0].f3[2].taken connect io.resp.f3[2].taken, io.resp_in[0].f3[2].taken when f3_resps[0][2].valid : node _io_resp_f3_2_taken_T = eq(f3_resps[0][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_1 = eq(f3_resps[0][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_2 = or(_io_resp_f3_2_taken_T, _io_resp_f3_2_taken_T_1) node _io_resp_f3_2_taken_T_3 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_4 = mux(_io_resp_f3_2_taken_T_2, io.resp_in[0].f3[2].taken, _io_resp_f3_2_taken_T_3) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_4 connect final_altpred_2, io.resp_in[0].f3[2].taken node _T_76 = or(UInt<1>(0h0), f3_resps[0][2].valid) node _T_77 = mux(f3_resps[0][2].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_78 = bits(f3_resps[0][2].bits.ctr, 2, 2) node _T_79 = mux(f3_resps[0][2].valid, _T_78, io.resp_in[0].f3[2].taken) when f3_resps[1][2].valid : node _io_resp_f3_2_taken_T_5 = eq(f3_resps[1][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_6 = eq(f3_resps[1][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_7 = or(_io_resp_f3_2_taken_T_5, _io_resp_f3_2_taken_T_6) node _io_resp_f3_2_taken_T_8 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_9 = mux(_io_resp_f3_2_taken_T_7, _T_79, _io_resp_f3_2_taken_T_8) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_9 connect final_altpred_2, _T_79 node _T_80 = or(_T_76, f3_resps[1][2].valid) node _T_81 = mux(f3_resps[1][2].valid, UInt<1>(0h1), _T_77) node _T_82 = bits(f3_resps[1][2].bits.ctr, 2, 2) node _T_83 = mux(f3_resps[1][2].valid, _T_82, _T_79) when f3_resps[2][2].valid : node _io_resp_f3_2_taken_T_10 = eq(f3_resps[2][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_11 = eq(f3_resps[2][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_12 = or(_io_resp_f3_2_taken_T_10, _io_resp_f3_2_taken_T_11) node _io_resp_f3_2_taken_T_13 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_14 = mux(_io_resp_f3_2_taken_T_12, _T_83, _io_resp_f3_2_taken_T_13) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_14 connect final_altpred_2, _T_83 node _T_84 = or(_T_80, f3_resps[2][2].valid) node _T_85 = mux(f3_resps[2][2].valid, UInt<2>(0h2), _T_81) node _T_86 = bits(f3_resps[2][2].bits.ctr, 2, 2) node _T_87 = mux(f3_resps[2][2].valid, _T_86, _T_83) when f3_resps[3][2].valid : node _io_resp_f3_2_taken_T_15 = eq(f3_resps[3][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_16 = eq(f3_resps[3][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_17 = or(_io_resp_f3_2_taken_T_15, _io_resp_f3_2_taken_T_16) node _io_resp_f3_2_taken_T_18 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_19 = mux(_io_resp_f3_2_taken_T_17, _T_87, _io_resp_f3_2_taken_T_18) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_19 connect final_altpred_2, _T_87 node _T_88 = or(_T_84, f3_resps[3][2].valid) node _T_89 = mux(f3_resps[3][2].valid, UInt<2>(0h3), _T_85) node _T_90 = bits(f3_resps[3][2].bits.ctr, 2, 2) node _T_91 = mux(f3_resps[3][2].valid, _T_90, _T_87) when f3_resps[4][2].valid : node _io_resp_f3_2_taken_T_20 = eq(f3_resps[4][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_21 = eq(f3_resps[4][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_22 = or(_io_resp_f3_2_taken_T_20, _io_resp_f3_2_taken_T_21) node _io_resp_f3_2_taken_T_23 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_24 = mux(_io_resp_f3_2_taken_T_22, _T_91, _io_resp_f3_2_taken_T_23) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_24 connect final_altpred_2, _T_91 node _T_92 = or(_T_88, f3_resps[4][2].valid) node _T_93 = mux(f3_resps[4][2].valid, UInt<3>(0h4), _T_89) node _T_94 = bits(f3_resps[4][2].bits.ctr, 2, 2) node _T_95 = mux(f3_resps[4][2].valid, _T_94, _T_91) when f3_resps[5][2].valid : node _io_resp_f3_2_taken_T_25 = eq(f3_resps[5][2].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_2_taken_T_26 = eq(f3_resps[5][2].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_2_taken_T_27 = or(_io_resp_f3_2_taken_T_25, _io_resp_f3_2_taken_T_26) node _io_resp_f3_2_taken_T_28 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _io_resp_f3_2_taken_T_29 = mux(_io_resp_f3_2_taken_T_27, _T_95, _io_resp_f3_2_taken_T_28) connect io.resp.f3[2].taken, _io_resp_f3_2_taken_T_29 connect final_altpred_2, _T_95 node _T_96 = or(_T_92, f3_resps[5][2].valid) node _T_97 = mux(f3_resps[5][2].valid, UInt<3>(0h5), _T_93) node _T_98 = bits(f3_resps[5][2].bits.ctr, 2, 2) node _T_99 = mux(f3_resps[5][2].valid, _T_98, _T_95) connect f3_meta.provider[2].valid, _T_96 connect f3_meta.provider[2].bits, _T_97 node _f3_meta_alt_differs_2_T = neq(final_altpred_2, io.resp.f3[2].taken) connect f3_meta.alt_differs[2], _f3_meta_alt_differs_2_T connect f3_meta.provider_u[2], f3_resps[_T_97][2].bits.u connect f3_meta.provider_ctr[2], f3_resps[_T_97][2].bits.ctr node _allocatable_slots_T_76 = eq(f3_resps[0][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_77 = eq(f3_resps[0][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_78 = and(_allocatable_slots_T_76, _allocatable_slots_T_77) node _allocatable_slots_T_79 = eq(f3_resps[1][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_80 = eq(f3_resps[1][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_81 = and(_allocatable_slots_T_79, _allocatable_slots_T_80) node _allocatable_slots_T_82 = eq(f3_resps[2][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_83 = eq(f3_resps[2][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_84 = and(_allocatable_slots_T_82, _allocatable_slots_T_83) node _allocatable_slots_T_85 = eq(f3_resps[3][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_86 = eq(f3_resps[3][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_87 = and(_allocatable_slots_T_85, _allocatable_slots_T_86) node _allocatable_slots_T_88 = eq(f3_resps[4][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_89 = eq(f3_resps[4][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_90 = and(_allocatable_slots_T_88, _allocatable_slots_T_89) node _allocatable_slots_T_91 = eq(f3_resps[5][2].valid, UInt<1>(0h0)) node _allocatable_slots_T_92 = eq(f3_resps[5][2].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_93 = and(_allocatable_slots_T_91, _allocatable_slots_T_92) wire _allocatable_slots_WIRE_2 : UInt<1>[6] connect _allocatable_slots_WIRE_2[0], _allocatable_slots_T_78 connect _allocatable_slots_WIRE_2[1], _allocatable_slots_T_81 connect _allocatable_slots_WIRE_2[2], _allocatable_slots_T_84 connect _allocatable_slots_WIRE_2[3], _allocatable_slots_T_87 connect _allocatable_slots_WIRE_2[4], _allocatable_slots_T_90 connect _allocatable_slots_WIRE_2[5], _allocatable_slots_T_93 node allocatable_slots_lo_hi_2 = cat(_allocatable_slots_WIRE_2[2], _allocatable_slots_WIRE_2[1]) node allocatable_slots_lo_2 = cat(allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2[0]) node allocatable_slots_hi_hi_2 = cat(_allocatable_slots_WIRE_2[5], _allocatable_slots_WIRE_2[4]) node allocatable_slots_hi_2 = cat(allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2[3]) node _allocatable_slots_T_94 = cat(allocatable_slots_hi_2, allocatable_slots_lo_2) node _allocatable_slots_T_95 = dshl(UInt<1>(0h1), _T_97) node _allocatable_slots_T_96 = dshr(_allocatable_slots_T_95, UInt<1>(0h0)) node _allocatable_slots_T_97 = dshr(_allocatable_slots_T_95, UInt<1>(0h1)) node _allocatable_slots_T_98 = dshr(_allocatable_slots_T_95, UInt<2>(0h2)) node _allocatable_slots_T_99 = dshr(_allocatable_slots_T_95, UInt<2>(0h3)) node _allocatable_slots_T_100 = dshr(_allocatable_slots_T_95, UInt<3>(0h4)) node _allocatable_slots_T_101 = dshr(_allocatable_slots_T_95, UInt<3>(0h5)) node _allocatable_slots_T_102 = dshr(_allocatable_slots_T_95, UInt<3>(0h6)) node _allocatable_slots_T_103 = dshr(_allocatable_slots_T_95, UInt<3>(0h7)) node _allocatable_slots_T_104 = or(_allocatable_slots_T_96, _allocatable_slots_T_97) node _allocatable_slots_T_105 = or(_allocatable_slots_T_104, _allocatable_slots_T_98) node _allocatable_slots_T_106 = or(_allocatable_slots_T_105, _allocatable_slots_T_99) node _allocatable_slots_T_107 = or(_allocatable_slots_T_106, _allocatable_slots_T_100) node _allocatable_slots_T_108 = or(_allocatable_slots_T_107, _allocatable_slots_T_101) node _allocatable_slots_T_109 = or(_allocatable_slots_T_108, _allocatable_slots_T_102) node _allocatable_slots_T_110 = or(_allocatable_slots_T_109, _allocatable_slots_T_103) node _allocatable_slots_T_111 = mux(_T_96, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_112 = and(_allocatable_slots_T_110, _allocatable_slots_T_111) node _allocatable_slots_T_113 = not(_allocatable_slots_T_112) node allocatable_slots_2 = and(_allocatable_slots_T_94, _allocatable_slots_T_113) inst alloc_lfsr_prng_2 of MaxPeriodFibonacciLFSR_23 connect alloc_lfsr_prng_2.clock, clock connect alloc_lfsr_prng_2.reset, reset connect alloc_lfsr_prng_2.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_2.io.seed.bits[0] invalidate alloc_lfsr_prng_2.io.seed.bits[1] invalidate alloc_lfsr_prng_2.io.seed.bits[2] invalidate alloc_lfsr_prng_2.io.seed.bits[3] invalidate alloc_lfsr_prng_2.io.seed.bits[4] invalidate alloc_lfsr_prng_2.io.seed.bits[5] connect alloc_lfsr_prng_2.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_2 = cat(alloc_lfsr_prng_2.io.out[2], alloc_lfsr_prng_2.io.out[1]) node alloc_lfsr_lo_2 = cat(alloc_lfsr_lo_hi_2, alloc_lfsr_prng_2.io.out[0]) node alloc_lfsr_hi_hi_2 = cat(alloc_lfsr_prng_2.io.out[5], alloc_lfsr_prng_2.io.out[4]) node alloc_lfsr_hi_2 = cat(alloc_lfsr_hi_hi_2, alloc_lfsr_prng_2.io.out[3]) node alloc_lfsr_2 = cat(alloc_lfsr_hi_2, alloc_lfsr_lo_2) node _first_entry_T_28 = bits(allocatable_slots_2, 0, 0) node _first_entry_T_29 = bits(allocatable_slots_2, 1, 1) node _first_entry_T_30 = bits(allocatable_slots_2, 2, 2) node _first_entry_T_31 = bits(allocatable_slots_2, 3, 3) node _first_entry_T_32 = bits(allocatable_slots_2, 4, 4) node _first_entry_T_33 = bits(allocatable_slots_2, 5, 5) node _first_entry_T_34 = bits(allocatable_slots_2, 6, 6) node _first_entry_T_35 = bits(allocatable_slots_2, 7, 7) node _first_entry_T_36 = mux(_first_entry_T_34, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_37 = mux(_first_entry_T_33, UInt<3>(0h5), _first_entry_T_36) node _first_entry_T_38 = mux(_first_entry_T_32, UInt<3>(0h4), _first_entry_T_37) node _first_entry_T_39 = mux(_first_entry_T_31, UInt<2>(0h3), _first_entry_T_38) node _first_entry_T_40 = mux(_first_entry_T_30, UInt<2>(0h2), _first_entry_T_39) node _first_entry_T_41 = mux(_first_entry_T_29, UInt<1>(0h1), _first_entry_T_40) node first_entry_2 = mux(_first_entry_T_28, UInt<1>(0h0), _first_entry_T_41) node _masked_entry_T_30 = and(allocatable_slots_2, alloc_lfsr_2) node _masked_entry_T_31 = bits(_masked_entry_T_30, 0, 0) node _masked_entry_T_32 = bits(_masked_entry_T_30, 1, 1) node _masked_entry_T_33 = bits(_masked_entry_T_30, 2, 2) node _masked_entry_T_34 = bits(_masked_entry_T_30, 3, 3) node _masked_entry_T_35 = bits(_masked_entry_T_30, 4, 4) node _masked_entry_T_36 = bits(_masked_entry_T_30, 5, 5) node _masked_entry_T_37 = bits(_masked_entry_T_30, 6, 6) node _masked_entry_T_38 = bits(_masked_entry_T_30, 7, 7) node _masked_entry_T_39 = mux(_masked_entry_T_37, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_40 = mux(_masked_entry_T_36, UInt<3>(0h5), _masked_entry_T_39) node _masked_entry_T_41 = mux(_masked_entry_T_35, UInt<3>(0h4), _masked_entry_T_40) node _masked_entry_T_42 = mux(_masked_entry_T_34, UInt<2>(0h3), _masked_entry_T_41) node _masked_entry_T_43 = mux(_masked_entry_T_33, UInt<2>(0h2), _masked_entry_T_42) node _masked_entry_T_44 = mux(_masked_entry_T_32, UInt<1>(0h1), _masked_entry_T_43) node masked_entry_2 = mux(_masked_entry_T_31, UInt<1>(0h0), _masked_entry_T_44) node _alloc_entry_T_4 = dshr(allocatable_slots_2, masked_entry_2) node _alloc_entry_T_5 = bits(_alloc_entry_T_4, 0, 0) node alloc_entry_2 = mux(_alloc_entry_T_5, masked_entry_2, first_entry_2) node _f3_meta_allocate_2_valid_T = neq(allocatable_slots_2, UInt<1>(0h0)) connect f3_meta.allocate[2].valid, _f3_meta_allocate_2_valid_T connect f3_meta.allocate[2].bits, alloc_entry_2 node _update_was_taken_T_4 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _update_was_taken_T_5 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_4) node update_was_taken_2 = and(_update_was_taken_T_5, s1_update.bits.cfi_taken) node _T_100 = bits(s1_update.bits.br_mask, 2, 2) node _T_101 = and(_T_100, s1_update.valid) node _T_102 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_103 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = and(_T_101, _T_105) when _T_106 : when s1_update_meta.provider[2].valid : connect s1_update_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[2].bits][2], UInt<1>(0h1) node _new_u_T_22 = bits(s1_update_mispredict_mask, 2, 2) node _new_u_T_23 = eq(s1_update_meta.alt_differs[2], UInt<1>(0h0)) node _new_u_T_24 = eq(s1_update_meta.provider_u[2], UInt<1>(0h0)) node _new_u_T_25 = sub(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_26 = tail(_new_u_T_25, 1) node _new_u_T_27 = mux(_new_u_T_24, UInt<1>(0h0), _new_u_T_26) node _new_u_T_28 = eq(s1_update_meta.provider_u[2], UInt<2>(0h3)) node _new_u_T_29 = add(s1_update_meta.provider_u[2], UInt<1>(0h1)) node _new_u_T_30 = tail(_new_u_T_29, 1) node _new_u_T_31 = mux(_new_u_T_28, UInt<2>(0h3), _new_u_T_30) node _new_u_T_32 = mux(_new_u_T_22, _new_u_T_27, _new_u_T_31) node new_u_2 = mux(_new_u_T_23, s1_update_meta.provider_u[2], _new_u_T_32) connect s1_update_u[s1_update_meta.provider[2].bits][2], new_u_2 connect s1_update_taken[s1_update_meta.provider[2].bits][2], update_was_taken_2 connect s1_update_old_ctr[s1_update_meta.provider[2].bits][2], s1_update_meta.provider_ctr[2] connect s1_update_alloc[s1_update_meta.provider[2].bits][2], UInt<1>(0h0) wire final_altpred_3 : UInt<1> connect final_altpred_3, io.resp_in[0].f3[3].taken connect io.resp.f3[3].taken, io.resp_in[0].f3[3].taken when f3_resps[0][3].valid : node _io_resp_f3_3_taken_T = eq(f3_resps[0][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_1 = eq(f3_resps[0][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_2 = or(_io_resp_f3_3_taken_T, _io_resp_f3_3_taken_T_1) node _io_resp_f3_3_taken_T_3 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_4 = mux(_io_resp_f3_3_taken_T_2, io.resp_in[0].f3[3].taken, _io_resp_f3_3_taken_T_3) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_4 connect final_altpred_3, io.resp_in[0].f3[3].taken node _T_107 = or(UInt<1>(0h0), f3_resps[0][3].valid) node _T_108 = mux(f3_resps[0][3].valid, UInt<1>(0h0), UInt<1>(0h0)) node _T_109 = bits(f3_resps[0][3].bits.ctr, 2, 2) node _T_110 = mux(f3_resps[0][3].valid, _T_109, io.resp_in[0].f3[3].taken) when f3_resps[1][3].valid : node _io_resp_f3_3_taken_T_5 = eq(f3_resps[1][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_6 = eq(f3_resps[1][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_7 = or(_io_resp_f3_3_taken_T_5, _io_resp_f3_3_taken_T_6) node _io_resp_f3_3_taken_T_8 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_9 = mux(_io_resp_f3_3_taken_T_7, _T_110, _io_resp_f3_3_taken_T_8) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_9 connect final_altpred_3, _T_110 node _T_111 = or(_T_107, f3_resps[1][3].valid) node _T_112 = mux(f3_resps[1][3].valid, UInt<1>(0h1), _T_108) node _T_113 = bits(f3_resps[1][3].bits.ctr, 2, 2) node _T_114 = mux(f3_resps[1][3].valid, _T_113, _T_110) when f3_resps[2][3].valid : node _io_resp_f3_3_taken_T_10 = eq(f3_resps[2][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_11 = eq(f3_resps[2][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_12 = or(_io_resp_f3_3_taken_T_10, _io_resp_f3_3_taken_T_11) node _io_resp_f3_3_taken_T_13 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_14 = mux(_io_resp_f3_3_taken_T_12, _T_114, _io_resp_f3_3_taken_T_13) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_14 connect final_altpred_3, _T_114 node _T_115 = or(_T_111, f3_resps[2][3].valid) node _T_116 = mux(f3_resps[2][3].valid, UInt<2>(0h2), _T_112) node _T_117 = bits(f3_resps[2][3].bits.ctr, 2, 2) node _T_118 = mux(f3_resps[2][3].valid, _T_117, _T_114) when f3_resps[3][3].valid : node _io_resp_f3_3_taken_T_15 = eq(f3_resps[3][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_16 = eq(f3_resps[3][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_17 = or(_io_resp_f3_3_taken_T_15, _io_resp_f3_3_taken_T_16) node _io_resp_f3_3_taken_T_18 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_19 = mux(_io_resp_f3_3_taken_T_17, _T_118, _io_resp_f3_3_taken_T_18) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_19 connect final_altpred_3, _T_118 node _T_119 = or(_T_115, f3_resps[3][3].valid) node _T_120 = mux(f3_resps[3][3].valid, UInt<2>(0h3), _T_116) node _T_121 = bits(f3_resps[3][3].bits.ctr, 2, 2) node _T_122 = mux(f3_resps[3][3].valid, _T_121, _T_118) when f3_resps[4][3].valid : node _io_resp_f3_3_taken_T_20 = eq(f3_resps[4][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_21 = eq(f3_resps[4][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_22 = or(_io_resp_f3_3_taken_T_20, _io_resp_f3_3_taken_T_21) node _io_resp_f3_3_taken_T_23 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_24 = mux(_io_resp_f3_3_taken_T_22, _T_122, _io_resp_f3_3_taken_T_23) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_24 connect final_altpred_3, _T_122 node _T_123 = or(_T_119, f3_resps[4][3].valid) node _T_124 = mux(f3_resps[4][3].valid, UInt<3>(0h4), _T_120) node _T_125 = bits(f3_resps[4][3].bits.ctr, 2, 2) node _T_126 = mux(f3_resps[4][3].valid, _T_125, _T_122) when f3_resps[5][3].valid : node _io_resp_f3_3_taken_T_25 = eq(f3_resps[5][3].bits.ctr, UInt<2>(0h3)) node _io_resp_f3_3_taken_T_26 = eq(f3_resps[5][3].bits.ctr, UInt<3>(0h4)) node _io_resp_f3_3_taken_T_27 = or(_io_resp_f3_3_taken_T_25, _io_resp_f3_3_taken_T_26) node _io_resp_f3_3_taken_T_28 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _io_resp_f3_3_taken_T_29 = mux(_io_resp_f3_3_taken_T_27, _T_126, _io_resp_f3_3_taken_T_28) connect io.resp.f3[3].taken, _io_resp_f3_3_taken_T_29 connect final_altpred_3, _T_126 node _T_127 = or(_T_123, f3_resps[5][3].valid) node _T_128 = mux(f3_resps[5][3].valid, UInt<3>(0h5), _T_124) node _T_129 = bits(f3_resps[5][3].bits.ctr, 2, 2) node _T_130 = mux(f3_resps[5][3].valid, _T_129, _T_126) connect f3_meta.provider[3].valid, _T_127 connect f3_meta.provider[3].bits, _T_128 node _f3_meta_alt_differs_3_T = neq(final_altpred_3, io.resp.f3[3].taken) connect f3_meta.alt_differs[3], _f3_meta_alt_differs_3_T connect f3_meta.provider_u[3], f3_resps[_T_128][3].bits.u connect f3_meta.provider_ctr[3], f3_resps[_T_128][3].bits.ctr node _allocatable_slots_T_114 = eq(f3_resps[0][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_115 = eq(f3_resps[0][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_116 = and(_allocatable_slots_T_114, _allocatable_slots_T_115) node _allocatable_slots_T_117 = eq(f3_resps[1][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_118 = eq(f3_resps[1][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_119 = and(_allocatable_slots_T_117, _allocatable_slots_T_118) node _allocatable_slots_T_120 = eq(f3_resps[2][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_121 = eq(f3_resps[2][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_122 = and(_allocatable_slots_T_120, _allocatable_slots_T_121) node _allocatable_slots_T_123 = eq(f3_resps[3][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_124 = eq(f3_resps[3][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_125 = and(_allocatable_slots_T_123, _allocatable_slots_T_124) node _allocatable_slots_T_126 = eq(f3_resps[4][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_127 = eq(f3_resps[4][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_128 = and(_allocatable_slots_T_126, _allocatable_slots_T_127) node _allocatable_slots_T_129 = eq(f3_resps[5][3].valid, UInt<1>(0h0)) node _allocatable_slots_T_130 = eq(f3_resps[5][3].bits.u, UInt<1>(0h0)) node _allocatable_slots_T_131 = and(_allocatable_slots_T_129, _allocatable_slots_T_130) wire _allocatable_slots_WIRE_3 : UInt<1>[6] connect _allocatable_slots_WIRE_3[0], _allocatable_slots_T_116 connect _allocatable_slots_WIRE_3[1], _allocatable_slots_T_119 connect _allocatable_slots_WIRE_3[2], _allocatable_slots_T_122 connect _allocatable_slots_WIRE_3[3], _allocatable_slots_T_125 connect _allocatable_slots_WIRE_3[4], _allocatable_slots_T_128 connect _allocatable_slots_WIRE_3[5], _allocatable_slots_T_131 node allocatable_slots_lo_hi_3 = cat(_allocatable_slots_WIRE_3[2], _allocatable_slots_WIRE_3[1]) node allocatable_slots_lo_3 = cat(allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3[0]) node allocatable_slots_hi_hi_3 = cat(_allocatable_slots_WIRE_3[5], _allocatable_slots_WIRE_3[4]) node allocatable_slots_hi_3 = cat(allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3[3]) node _allocatable_slots_T_132 = cat(allocatable_slots_hi_3, allocatable_slots_lo_3) node _allocatable_slots_T_133 = dshl(UInt<1>(0h1), _T_128) node _allocatable_slots_T_134 = dshr(_allocatable_slots_T_133, UInt<1>(0h0)) node _allocatable_slots_T_135 = dshr(_allocatable_slots_T_133, UInt<1>(0h1)) node _allocatable_slots_T_136 = dshr(_allocatable_slots_T_133, UInt<2>(0h2)) node _allocatable_slots_T_137 = dshr(_allocatable_slots_T_133, UInt<2>(0h3)) node _allocatable_slots_T_138 = dshr(_allocatable_slots_T_133, UInt<3>(0h4)) node _allocatable_slots_T_139 = dshr(_allocatable_slots_T_133, UInt<3>(0h5)) node _allocatable_slots_T_140 = dshr(_allocatable_slots_T_133, UInt<3>(0h6)) node _allocatable_slots_T_141 = dshr(_allocatable_slots_T_133, UInt<3>(0h7)) node _allocatable_slots_T_142 = or(_allocatable_slots_T_134, _allocatable_slots_T_135) node _allocatable_slots_T_143 = or(_allocatable_slots_T_142, _allocatable_slots_T_136) node _allocatable_slots_T_144 = or(_allocatable_slots_T_143, _allocatable_slots_T_137) node _allocatable_slots_T_145 = or(_allocatable_slots_T_144, _allocatable_slots_T_138) node _allocatable_slots_T_146 = or(_allocatable_slots_T_145, _allocatable_slots_T_139) node _allocatable_slots_T_147 = or(_allocatable_slots_T_146, _allocatable_slots_T_140) node _allocatable_slots_T_148 = or(_allocatable_slots_T_147, _allocatable_slots_T_141) node _allocatable_slots_T_149 = mux(_T_127, UInt<6>(0h3f), UInt<6>(0h0)) node _allocatable_slots_T_150 = and(_allocatable_slots_T_148, _allocatable_slots_T_149) node _allocatable_slots_T_151 = not(_allocatable_slots_T_150) node allocatable_slots_3 = and(_allocatable_slots_T_132, _allocatable_slots_T_151) inst alloc_lfsr_prng_3 of MaxPeriodFibonacciLFSR_24 connect alloc_lfsr_prng_3.clock, clock connect alloc_lfsr_prng_3.reset, reset connect alloc_lfsr_prng_3.io.seed.valid, UInt<1>(0h0) invalidate alloc_lfsr_prng_3.io.seed.bits[0] invalidate alloc_lfsr_prng_3.io.seed.bits[1] invalidate alloc_lfsr_prng_3.io.seed.bits[2] invalidate alloc_lfsr_prng_3.io.seed.bits[3] invalidate alloc_lfsr_prng_3.io.seed.bits[4] invalidate alloc_lfsr_prng_3.io.seed.bits[5] connect alloc_lfsr_prng_3.io.increment, UInt<1>(0h1) node alloc_lfsr_lo_hi_3 = cat(alloc_lfsr_prng_3.io.out[2], alloc_lfsr_prng_3.io.out[1]) node alloc_lfsr_lo_3 = cat(alloc_lfsr_lo_hi_3, alloc_lfsr_prng_3.io.out[0]) node alloc_lfsr_hi_hi_3 = cat(alloc_lfsr_prng_3.io.out[5], alloc_lfsr_prng_3.io.out[4]) node alloc_lfsr_hi_3 = cat(alloc_lfsr_hi_hi_3, alloc_lfsr_prng_3.io.out[3]) node alloc_lfsr_3 = cat(alloc_lfsr_hi_3, alloc_lfsr_lo_3) node _first_entry_T_42 = bits(allocatable_slots_3, 0, 0) node _first_entry_T_43 = bits(allocatable_slots_3, 1, 1) node _first_entry_T_44 = bits(allocatable_slots_3, 2, 2) node _first_entry_T_45 = bits(allocatable_slots_3, 3, 3) node _first_entry_T_46 = bits(allocatable_slots_3, 4, 4) node _first_entry_T_47 = bits(allocatable_slots_3, 5, 5) node _first_entry_T_48 = bits(allocatable_slots_3, 6, 6) node _first_entry_T_49 = bits(allocatable_slots_3, 7, 7) node _first_entry_T_50 = mux(_first_entry_T_48, UInt<3>(0h6), UInt<3>(0h7)) node _first_entry_T_51 = mux(_first_entry_T_47, UInt<3>(0h5), _first_entry_T_50) node _first_entry_T_52 = mux(_first_entry_T_46, UInt<3>(0h4), _first_entry_T_51) node _first_entry_T_53 = mux(_first_entry_T_45, UInt<2>(0h3), _first_entry_T_52) node _first_entry_T_54 = mux(_first_entry_T_44, UInt<2>(0h2), _first_entry_T_53) node _first_entry_T_55 = mux(_first_entry_T_43, UInt<1>(0h1), _first_entry_T_54) node first_entry_3 = mux(_first_entry_T_42, UInt<1>(0h0), _first_entry_T_55) node _masked_entry_T_45 = and(allocatable_slots_3, alloc_lfsr_3) node _masked_entry_T_46 = bits(_masked_entry_T_45, 0, 0) node _masked_entry_T_47 = bits(_masked_entry_T_45, 1, 1) node _masked_entry_T_48 = bits(_masked_entry_T_45, 2, 2) node _masked_entry_T_49 = bits(_masked_entry_T_45, 3, 3) node _masked_entry_T_50 = bits(_masked_entry_T_45, 4, 4) node _masked_entry_T_51 = bits(_masked_entry_T_45, 5, 5) node _masked_entry_T_52 = bits(_masked_entry_T_45, 6, 6) node _masked_entry_T_53 = bits(_masked_entry_T_45, 7, 7) node _masked_entry_T_54 = mux(_masked_entry_T_52, UInt<3>(0h6), UInt<3>(0h7)) node _masked_entry_T_55 = mux(_masked_entry_T_51, UInt<3>(0h5), _masked_entry_T_54) node _masked_entry_T_56 = mux(_masked_entry_T_50, UInt<3>(0h4), _masked_entry_T_55) node _masked_entry_T_57 = mux(_masked_entry_T_49, UInt<2>(0h3), _masked_entry_T_56) node _masked_entry_T_58 = mux(_masked_entry_T_48, UInt<2>(0h2), _masked_entry_T_57) node _masked_entry_T_59 = mux(_masked_entry_T_47, UInt<1>(0h1), _masked_entry_T_58) node masked_entry_3 = mux(_masked_entry_T_46, UInt<1>(0h0), _masked_entry_T_59) node _alloc_entry_T_6 = dshr(allocatable_slots_3, masked_entry_3) node _alloc_entry_T_7 = bits(_alloc_entry_T_6, 0, 0) node alloc_entry_3 = mux(_alloc_entry_T_7, masked_entry_3, first_entry_3) node _f3_meta_allocate_3_valid_T = neq(allocatable_slots_3, UInt<1>(0h0)) connect f3_meta.allocate[3].valid, _f3_meta_allocate_3_valid_T connect f3_meta.allocate[3].bits, alloc_entry_3 node _update_was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _update_was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _update_was_taken_T_6) node update_was_taken_3 = and(_update_was_taken_T_7, s1_update.bits.cfi_taken) node _T_131 = bits(s1_update.bits.br_mask, 3, 3) node _T_132 = and(_T_131, s1_update.valid) node _T_133 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_134 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = and(_T_132, _T_136) when _T_137 : when s1_update_meta.provider[3].valid : connect s1_update_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.provider[3].bits][3], UInt<1>(0h1) node _new_u_T_33 = bits(s1_update_mispredict_mask, 3, 3) node _new_u_T_34 = eq(s1_update_meta.alt_differs[3], UInt<1>(0h0)) node _new_u_T_35 = eq(s1_update_meta.provider_u[3], UInt<1>(0h0)) node _new_u_T_36 = sub(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_37 = tail(_new_u_T_36, 1) node _new_u_T_38 = mux(_new_u_T_35, UInt<1>(0h0), _new_u_T_37) node _new_u_T_39 = eq(s1_update_meta.provider_u[3], UInt<2>(0h3)) node _new_u_T_40 = add(s1_update_meta.provider_u[3], UInt<1>(0h1)) node _new_u_T_41 = tail(_new_u_T_40, 1) node _new_u_T_42 = mux(_new_u_T_39, UInt<2>(0h3), _new_u_T_41) node _new_u_T_43 = mux(_new_u_T_33, _new_u_T_38, _new_u_T_42) node new_u_3 = mux(_new_u_T_34, s1_update_meta.provider_u[3], _new_u_T_43) connect s1_update_u[s1_update_meta.provider[3].bits][3], new_u_3 connect s1_update_taken[s1_update_meta.provider[3].bits][3], update_was_taken_3 connect s1_update_old_ctr[s1_update_meta.provider[3].bits][3], s1_update_meta.provider_ctr[3] connect s1_update_alloc[s1_update_meta.provider[3].bits][3], UInt<1>(0h0) node _T_138 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_139 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_140 = or(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = and(s1_update.valid, _T_141) node _T_143 = and(_T_142, s1_update.bits.cfi_mispredicted) node _T_144 = and(_T_143, s1_update.bits.cfi_idx.valid) when _T_144 : when s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].valid : connect s1_update_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_taken[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], s1_update.bits.cfi_taken connect s1_update_alloc[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u_mask[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[s1_update_meta.allocate[s1_update.bits.cfi_idx.bits].bits][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) else : node _decr_mask_T = dshl(UInt<1>(0h1), s1_update_meta.provider[s1_update.bits.cfi_idx.bits].bits) node _decr_mask_T_1 = dshr(_decr_mask_T, UInt<1>(0h0)) node _decr_mask_T_2 = dshr(_decr_mask_T, UInt<1>(0h1)) node _decr_mask_T_3 = dshr(_decr_mask_T, UInt<2>(0h2)) node _decr_mask_T_4 = dshr(_decr_mask_T, UInt<2>(0h3)) node _decr_mask_T_5 = dshr(_decr_mask_T, UInt<3>(0h4)) node _decr_mask_T_6 = dshr(_decr_mask_T, UInt<3>(0h5)) node _decr_mask_T_7 = dshr(_decr_mask_T, UInt<3>(0h6)) node _decr_mask_T_8 = dshr(_decr_mask_T, UInt<3>(0h7)) node _decr_mask_T_9 = or(_decr_mask_T_1, _decr_mask_T_2) node _decr_mask_T_10 = or(_decr_mask_T_9, _decr_mask_T_3) node _decr_mask_T_11 = or(_decr_mask_T_10, _decr_mask_T_4) node _decr_mask_T_12 = or(_decr_mask_T_11, _decr_mask_T_5) node _decr_mask_T_13 = or(_decr_mask_T_12, _decr_mask_T_6) node _decr_mask_T_14 = or(_decr_mask_T_13, _decr_mask_T_7) node _decr_mask_T_15 = or(_decr_mask_T_14, _decr_mask_T_8) node _decr_mask_T_16 = not(_decr_mask_T_15) node decr_mask = mux(s1_update_meta.provider[s1_update.bits.cfi_idx.bits].valid, _decr_mask_T_16, UInt<1>(0h0)) node _T_145 = bits(decr_mask, 0, 0) when _T_145 : connect s1_update_u_mask[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[0][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_146 = bits(decr_mask, 1, 1) when _T_146 : connect s1_update_u_mask[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[1][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_147 = bits(decr_mask, 2, 2) when _T_147 : connect s1_update_u_mask[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[2][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_148 = bits(decr_mask, 3, 3) when _T_148 : connect s1_update_u_mask[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[3][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_149 = bits(decr_mask, 4, 4) when _T_149 : connect s1_update_u_mask[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[4][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) node _T_150 = bits(decr_mask, 5, 5) when _T_150 : connect s1_update_u_mask[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h1) connect s1_update_u[5][s1_update.bits.cfi_idx.bits], UInt<1>(0h0) reg tt_0_1_io_update_mask_0_REG : UInt<1>, clock connect tt_0_1_io_update_mask_0_REG, s1_update_mask[0][0] connect tt_0_1.io.update_mask[0], tt_0_1_io_update_mask_0_REG reg tt_0_1_io_update_taken_0_REG : UInt<1>, clock connect tt_0_1_io_update_taken_0_REG, s1_update_taken[0][0] connect tt_0_1.io.update_taken[0], tt_0_1_io_update_taken_0_REG reg tt_0_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_0_REG, s1_update_alloc[0][0] connect tt_0_1.io.update_alloc[0], tt_0_1_io_update_alloc_0_REG reg tt_0_1_io_update_old_ctr_0_REG : UInt, clock connect tt_0_1_io_update_old_ctr_0_REG, s1_update_old_ctr[0][0] connect tt_0_1.io.update_old_ctr[0], tt_0_1_io_update_old_ctr_0_REG reg tt_0_1_io_update_u_mask_0_REG : UInt, clock connect tt_0_1_io_update_u_mask_0_REG, s1_update_u_mask[0][0] connect tt_0_1.io.update_u_mask[0], tt_0_1_io_update_u_mask_0_REG reg tt_0_1_io_update_u_0_REG : UInt, clock connect tt_0_1_io_update_u_0_REG, s1_update_u[0][0] connect tt_0_1.io.update_u[0], tt_0_1_io_update_u_0_REG reg tt_0_1_io_update_mask_1_REG : UInt<1>, clock connect tt_0_1_io_update_mask_1_REG, s1_update_mask[0][1] connect tt_0_1.io.update_mask[1], tt_0_1_io_update_mask_1_REG reg tt_0_1_io_update_taken_1_REG : UInt<1>, clock connect tt_0_1_io_update_taken_1_REG, s1_update_taken[0][1] connect tt_0_1.io.update_taken[1], tt_0_1_io_update_taken_1_REG reg tt_0_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_1_REG, s1_update_alloc[0][1] connect tt_0_1.io.update_alloc[1], tt_0_1_io_update_alloc_1_REG reg tt_0_1_io_update_old_ctr_1_REG : UInt, clock connect tt_0_1_io_update_old_ctr_1_REG, s1_update_old_ctr[0][1] connect tt_0_1.io.update_old_ctr[1], tt_0_1_io_update_old_ctr_1_REG reg tt_0_1_io_update_u_mask_1_REG : UInt, clock connect tt_0_1_io_update_u_mask_1_REG, s1_update_u_mask[0][1] connect tt_0_1.io.update_u_mask[1], tt_0_1_io_update_u_mask_1_REG reg tt_0_1_io_update_u_1_REG : UInt, clock connect tt_0_1_io_update_u_1_REG, s1_update_u[0][1] connect tt_0_1.io.update_u[1], tt_0_1_io_update_u_1_REG reg tt_0_1_io_update_mask_2_REG : UInt<1>, clock connect tt_0_1_io_update_mask_2_REG, s1_update_mask[0][2] connect tt_0_1.io.update_mask[2], tt_0_1_io_update_mask_2_REG reg tt_0_1_io_update_taken_2_REG : UInt<1>, clock connect tt_0_1_io_update_taken_2_REG, s1_update_taken[0][2] connect tt_0_1.io.update_taken[2], tt_0_1_io_update_taken_2_REG reg tt_0_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_2_REG, s1_update_alloc[0][2] connect tt_0_1.io.update_alloc[2], tt_0_1_io_update_alloc_2_REG reg tt_0_1_io_update_old_ctr_2_REG : UInt, clock connect tt_0_1_io_update_old_ctr_2_REG, s1_update_old_ctr[0][2] connect tt_0_1.io.update_old_ctr[2], tt_0_1_io_update_old_ctr_2_REG reg tt_0_1_io_update_u_mask_2_REG : UInt, clock connect tt_0_1_io_update_u_mask_2_REG, s1_update_u_mask[0][2] connect tt_0_1.io.update_u_mask[2], tt_0_1_io_update_u_mask_2_REG reg tt_0_1_io_update_u_2_REG : UInt, clock connect tt_0_1_io_update_u_2_REG, s1_update_u[0][2] connect tt_0_1.io.update_u[2], tt_0_1_io_update_u_2_REG reg tt_0_1_io_update_mask_3_REG : UInt<1>, clock connect tt_0_1_io_update_mask_3_REG, s1_update_mask[0][3] connect tt_0_1.io.update_mask[3], tt_0_1_io_update_mask_3_REG reg tt_0_1_io_update_taken_3_REG : UInt<1>, clock connect tt_0_1_io_update_taken_3_REG, s1_update_taken[0][3] connect tt_0_1.io.update_taken[3], tt_0_1_io_update_taken_3_REG reg tt_0_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_0_1_io_update_alloc_3_REG, s1_update_alloc[0][3] connect tt_0_1.io.update_alloc[3], tt_0_1_io_update_alloc_3_REG reg tt_0_1_io_update_old_ctr_3_REG : UInt, clock connect tt_0_1_io_update_old_ctr_3_REG, s1_update_old_ctr[0][3] connect tt_0_1.io.update_old_ctr[3], tt_0_1_io_update_old_ctr_3_REG reg tt_0_1_io_update_u_mask_3_REG : UInt, clock connect tt_0_1_io_update_u_mask_3_REG, s1_update_u_mask[0][3] connect tt_0_1.io.update_u_mask[3], tt_0_1_io_update_u_mask_3_REG reg tt_0_1_io_update_u_3_REG : UInt, clock connect tt_0_1_io_update_u_3_REG, s1_update_u[0][3] connect tt_0_1.io.update_u[3], tt_0_1_io_update_u_3_REG reg tt_0_1_io_update_pc_REG : UInt, clock connect tt_0_1_io_update_pc_REG, s1_update.bits.pc connect tt_0_1.io.update_pc, tt_0_1_io_update_pc_REG reg tt_0_1_io_update_hist_REG : UInt, clock connect tt_0_1_io_update_hist_REG, s1_update.bits.ghist connect tt_0_1.io.update_hist, tt_0_1_io_update_hist_REG reg tt_1_1_io_update_mask_0_REG : UInt<1>, clock connect tt_1_1_io_update_mask_0_REG, s1_update_mask[1][0] connect tt_1_1.io.update_mask[0], tt_1_1_io_update_mask_0_REG reg tt_1_1_io_update_taken_0_REG : UInt<1>, clock connect tt_1_1_io_update_taken_0_REG, s1_update_taken[1][0] connect tt_1_1.io.update_taken[0], tt_1_1_io_update_taken_0_REG reg tt_1_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_0_REG, s1_update_alloc[1][0] connect tt_1_1.io.update_alloc[0], tt_1_1_io_update_alloc_0_REG reg tt_1_1_io_update_old_ctr_0_REG : UInt, clock connect tt_1_1_io_update_old_ctr_0_REG, s1_update_old_ctr[1][0] connect tt_1_1.io.update_old_ctr[0], tt_1_1_io_update_old_ctr_0_REG reg tt_1_1_io_update_u_mask_0_REG : UInt, clock connect tt_1_1_io_update_u_mask_0_REG, s1_update_u_mask[1][0] connect tt_1_1.io.update_u_mask[0], tt_1_1_io_update_u_mask_0_REG reg tt_1_1_io_update_u_0_REG : UInt, clock connect tt_1_1_io_update_u_0_REG, s1_update_u[1][0] connect tt_1_1.io.update_u[0], tt_1_1_io_update_u_0_REG reg tt_1_1_io_update_mask_1_REG : UInt<1>, clock connect tt_1_1_io_update_mask_1_REG, s1_update_mask[1][1] connect tt_1_1.io.update_mask[1], tt_1_1_io_update_mask_1_REG reg tt_1_1_io_update_taken_1_REG : UInt<1>, clock connect tt_1_1_io_update_taken_1_REG, s1_update_taken[1][1] connect tt_1_1.io.update_taken[1], tt_1_1_io_update_taken_1_REG reg tt_1_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_1_REG, s1_update_alloc[1][1] connect tt_1_1.io.update_alloc[1], tt_1_1_io_update_alloc_1_REG reg tt_1_1_io_update_old_ctr_1_REG : UInt, clock connect tt_1_1_io_update_old_ctr_1_REG, s1_update_old_ctr[1][1] connect tt_1_1.io.update_old_ctr[1], tt_1_1_io_update_old_ctr_1_REG reg tt_1_1_io_update_u_mask_1_REG : UInt, clock connect tt_1_1_io_update_u_mask_1_REG, s1_update_u_mask[1][1] connect tt_1_1.io.update_u_mask[1], tt_1_1_io_update_u_mask_1_REG reg tt_1_1_io_update_u_1_REG : UInt, clock connect tt_1_1_io_update_u_1_REG, s1_update_u[1][1] connect tt_1_1.io.update_u[1], tt_1_1_io_update_u_1_REG reg tt_1_1_io_update_mask_2_REG : UInt<1>, clock connect tt_1_1_io_update_mask_2_REG, s1_update_mask[1][2] connect tt_1_1.io.update_mask[2], tt_1_1_io_update_mask_2_REG reg tt_1_1_io_update_taken_2_REG : UInt<1>, clock connect tt_1_1_io_update_taken_2_REG, s1_update_taken[1][2] connect tt_1_1.io.update_taken[2], tt_1_1_io_update_taken_2_REG reg tt_1_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_2_REG, s1_update_alloc[1][2] connect tt_1_1.io.update_alloc[2], tt_1_1_io_update_alloc_2_REG reg tt_1_1_io_update_old_ctr_2_REG : UInt, clock connect tt_1_1_io_update_old_ctr_2_REG, s1_update_old_ctr[1][2] connect tt_1_1.io.update_old_ctr[2], tt_1_1_io_update_old_ctr_2_REG reg tt_1_1_io_update_u_mask_2_REG : UInt, clock connect tt_1_1_io_update_u_mask_2_REG, s1_update_u_mask[1][2] connect tt_1_1.io.update_u_mask[2], tt_1_1_io_update_u_mask_2_REG reg tt_1_1_io_update_u_2_REG : UInt, clock connect tt_1_1_io_update_u_2_REG, s1_update_u[1][2] connect tt_1_1.io.update_u[2], tt_1_1_io_update_u_2_REG reg tt_1_1_io_update_mask_3_REG : UInt<1>, clock connect tt_1_1_io_update_mask_3_REG, s1_update_mask[1][3] connect tt_1_1.io.update_mask[3], tt_1_1_io_update_mask_3_REG reg tt_1_1_io_update_taken_3_REG : UInt<1>, clock connect tt_1_1_io_update_taken_3_REG, s1_update_taken[1][3] connect tt_1_1.io.update_taken[3], tt_1_1_io_update_taken_3_REG reg tt_1_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_1_1_io_update_alloc_3_REG, s1_update_alloc[1][3] connect tt_1_1.io.update_alloc[3], tt_1_1_io_update_alloc_3_REG reg tt_1_1_io_update_old_ctr_3_REG : UInt, clock connect tt_1_1_io_update_old_ctr_3_REG, s1_update_old_ctr[1][3] connect tt_1_1.io.update_old_ctr[3], tt_1_1_io_update_old_ctr_3_REG reg tt_1_1_io_update_u_mask_3_REG : UInt, clock connect tt_1_1_io_update_u_mask_3_REG, s1_update_u_mask[1][3] connect tt_1_1.io.update_u_mask[3], tt_1_1_io_update_u_mask_3_REG reg tt_1_1_io_update_u_3_REG : UInt, clock connect tt_1_1_io_update_u_3_REG, s1_update_u[1][3] connect tt_1_1.io.update_u[3], tt_1_1_io_update_u_3_REG reg tt_1_1_io_update_pc_REG : UInt, clock connect tt_1_1_io_update_pc_REG, s1_update.bits.pc connect tt_1_1.io.update_pc, tt_1_1_io_update_pc_REG reg tt_1_1_io_update_hist_REG : UInt, clock connect tt_1_1_io_update_hist_REG, s1_update.bits.ghist connect tt_1_1.io.update_hist, tt_1_1_io_update_hist_REG reg tt_2_1_io_update_mask_0_REG : UInt<1>, clock connect tt_2_1_io_update_mask_0_REG, s1_update_mask[2][0] connect tt_2_1.io.update_mask[0], tt_2_1_io_update_mask_0_REG reg tt_2_1_io_update_taken_0_REG : UInt<1>, clock connect tt_2_1_io_update_taken_0_REG, s1_update_taken[2][0] connect tt_2_1.io.update_taken[0], tt_2_1_io_update_taken_0_REG reg tt_2_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_0_REG, s1_update_alloc[2][0] connect tt_2_1.io.update_alloc[0], tt_2_1_io_update_alloc_0_REG reg tt_2_1_io_update_old_ctr_0_REG : UInt, clock connect tt_2_1_io_update_old_ctr_0_REG, s1_update_old_ctr[2][0] connect tt_2_1.io.update_old_ctr[0], tt_2_1_io_update_old_ctr_0_REG reg tt_2_1_io_update_u_mask_0_REG : UInt, clock connect tt_2_1_io_update_u_mask_0_REG, s1_update_u_mask[2][0] connect tt_2_1.io.update_u_mask[0], tt_2_1_io_update_u_mask_0_REG reg tt_2_1_io_update_u_0_REG : UInt, clock connect tt_2_1_io_update_u_0_REG, s1_update_u[2][0] connect tt_2_1.io.update_u[0], tt_2_1_io_update_u_0_REG reg tt_2_1_io_update_mask_1_REG : UInt<1>, clock connect tt_2_1_io_update_mask_1_REG, s1_update_mask[2][1] connect tt_2_1.io.update_mask[1], tt_2_1_io_update_mask_1_REG reg tt_2_1_io_update_taken_1_REG : UInt<1>, clock connect tt_2_1_io_update_taken_1_REG, s1_update_taken[2][1] connect tt_2_1.io.update_taken[1], tt_2_1_io_update_taken_1_REG reg tt_2_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_1_REG, s1_update_alloc[2][1] connect tt_2_1.io.update_alloc[1], tt_2_1_io_update_alloc_1_REG reg tt_2_1_io_update_old_ctr_1_REG : UInt, clock connect tt_2_1_io_update_old_ctr_1_REG, s1_update_old_ctr[2][1] connect tt_2_1.io.update_old_ctr[1], tt_2_1_io_update_old_ctr_1_REG reg tt_2_1_io_update_u_mask_1_REG : UInt, clock connect tt_2_1_io_update_u_mask_1_REG, s1_update_u_mask[2][1] connect tt_2_1.io.update_u_mask[1], tt_2_1_io_update_u_mask_1_REG reg tt_2_1_io_update_u_1_REG : UInt, clock connect tt_2_1_io_update_u_1_REG, s1_update_u[2][1] connect tt_2_1.io.update_u[1], tt_2_1_io_update_u_1_REG reg tt_2_1_io_update_mask_2_REG : UInt<1>, clock connect tt_2_1_io_update_mask_2_REG, s1_update_mask[2][2] connect tt_2_1.io.update_mask[2], tt_2_1_io_update_mask_2_REG reg tt_2_1_io_update_taken_2_REG : UInt<1>, clock connect tt_2_1_io_update_taken_2_REG, s1_update_taken[2][2] connect tt_2_1.io.update_taken[2], tt_2_1_io_update_taken_2_REG reg tt_2_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_2_REG, s1_update_alloc[2][2] connect tt_2_1.io.update_alloc[2], tt_2_1_io_update_alloc_2_REG reg tt_2_1_io_update_old_ctr_2_REG : UInt, clock connect tt_2_1_io_update_old_ctr_2_REG, s1_update_old_ctr[2][2] connect tt_2_1.io.update_old_ctr[2], tt_2_1_io_update_old_ctr_2_REG reg tt_2_1_io_update_u_mask_2_REG : UInt, clock connect tt_2_1_io_update_u_mask_2_REG, s1_update_u_mask[2][2] connect tt_2_1.io.update_u_mask[2], tt_2_1_io_update_u_mask_2_REG reg tt_2_1_io_update_u_2_REG : UInt, clock connect tt_2_1_io_update_u_2_REG, s1_update_u[2][2] connect tt_2_1.io.update_u[2], tt_2_1_io_update_u_2_REG reg tt_2_1_io_update_mask_3_REG : UInt<1>, clock connect tt_2_1_io_update_mask_3_REG, s1_update_mask[2][3] connect tt_2_1.io.update_mask[3], tt_2_1_io_update_mask_3_REG reg tt_2_1_io_update_taken_3_REG : UInt<1>, clock connect tt_2_1_io_update_taken_3_REG, s1_update_taken[2][3] connect tt_2_1.io.update_taken[3], tt_2_1_io_update_taken_3_REG reg tt_2_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_2_1_io_update_alloc_3_REG, s1_update_alloc[2][3] connect tt_2_1.io.update_alloc[3], tt_2_1_io_update_alloc_3_REG reg tt_2_1_io_update_old_ctr_3_REG : UInt, clock connect tt_2_1_io_update_old_ctr_3_REG, s1_update_old_ctr[2][3] connect tt_2_1.io.update_old_ctr[3], tt_2_1_io_update_old_ctr_3_REG reg tt_2_1_io_update_u_mask_3_REG : UInt, clock connect tt_2_1_io_update_u_mask_3_REG, s1_update_u_mask[2][3] connect tt_2_1.io.update_u_mask[3], tt_2_1_io_update_u_mask_3_REG reg tt_2_1_io_update_u_3_REG : UInt, clock connect tt_2_1_io_update_u_3_REG, s1_update_u[2][3] connect tt_2_1.io.update_u[3], tt_2_1_io_update_u_3_REG reg tt_2_1_io_update_pc_REG : UInt, clock connect tt_2_1_io_update_pc_REG, s1_update.bits.pc connect tt_2_1.io.update_pc, tt_2_1_io_update_pc_REG reg tt_2_1_io_update_hist_REG : UInt, clock connect tt_2_1_io_update_hist_REG, s1_update.bits.ghist connect tt_2_1.io.update_hist, tt_2_1_io_update_hist_REG reg tt_3_1_io_update_mask_0_REG : UInt<1>, clock connect tt_3_1_io_update_mask_0_REG, s1_update_mask[3][0] connect tt_3_1.io.update_mask[0], tt_3_1_io_update_mask_0_REG reg tt_3_1_io_update_taken_0_REG : UInt<1>, clock connect tt_3_1_io_update_taken_0_REG, s1_update_taken[3][0] connect tt_3_1.io.update_taken[0], tt_3_1_io_update_taken_0_REG reg tt_3_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_0_REG, s1_update_alloc[3][0] connect tt_3_1.io.update_alloc[0], tt_3_1_io_update_alloc_0_REG reg tt_3_1_io_update_old_ctr_0_REG : UInt, clock connect tt_3_1_io_update_old_ctr_0_REG, s1_update_old_ctr[3][0] connect tt_3_1.io.update_old_ctr[0], tt_3_1_io_update_old_ctr_0_REG reg tt_3_1_io_update_u_mask_0_REG : UInt, clock connect tt_3_1_io_update_u_mask_0_REG, s1_update_u_mask[3][0] connect tt_3_1.io.update_u_mask[0], tt_3_1_io_update_u_mask_0_REG reg tt_3_1_io_update_u_0_REG : UInt, clock connect tt_3_1_io_update_u_0_REG, s1_update_u[3][0] connect tt_3_1.io.update_u[0], tt_3_1_io_update_u_0_REG reg tt_3_1_io_update_mask_1_REG : UInt<1>, clock connect tt_3_1_io_update_mask_1_REG, s1_update_mask[3][1] connect tt_3_1.io.update_mask[1], tt_3_1_io_update_mask_1_REG reg tt_3_1_io_update_taken_1_REG : UInt<1>, clock connect tt_3_1_io_update_taken_1_REG, s1_update_taken[3][1] connect tt_3_1.io.update_taken[1], tt_3_1_io_update_taken_1_REG reg tt_3_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_1_REG, s1_update_alloc[3][1] connect tt_3_1.io.update_alloc[1], tt_3_1_io_update_alloc_1_REG reg tt_3_1_io_update_old_ctr_1_REG : UInt, clock connect tt_3_1_io_update_old_ctr_1_REG, s1_update_old_ctr[3][1] connect tt_3_1.io.update_old_ctr[1], tt_3_1_io_update_old_ctr_1_REG reg tt_3_1_io_update_u_mask_1_REG : UInt, clock connect tt_3_1_io_update_u_mask_1_REG, s1_update_u_mask[3][1] connect tt_3_1.io.update_u_mask[1], tt_3_1_io_update_u_mask_1_REG reg tt_3_1_io_update_u_1_REG : UInt, clock connect tt_3_1_io_update_u_1_REG, s1_update_u[3][1] connect tt_3_1.io.update_u[1], tt_3_1_io_update_u_1_REG reg tt_3_1_io_update_mask_2_REG : UInt<1>, clock connect tt_3_1_io_update_mask_2_REG, s1_update_mask[3][2] connect tt_3_1.io.update_mask[2], tt_3_1_io_update_mask_2_REG reg tt_3_1_io_update_taken_2_REG : UInt<1>, clock connect tt_3_1_io_update_taken_2_REG, s1_update_taken[3][2] connect tt_3_1.io.update_taken[2], tt_3_1_io_update_taken_2_REG reg tt_3_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_2_REG, s1_update_alloc[3][2] connect tt_3_1.io.update_alloc[2], tt_3_1_io_update_alloc_2_REG reg tt_3_1_io_update_old_ctr_2_REG : UInt, clock connect tt_3_1_io_update_old_ctr_2_REG, s1_update_old_ctr[3][2] connect tt_3_1.io.update_old_ctr[2], tt_3_1_io_update_old_ctr_2_REG reg tt_3_1_io_update_u_mask_2_REG : UInt, clock connect tt_3_1_io_update_u_mask_2_REG, s1_update_u_mask[3][2] connect tt_3_1.io.update_u_mask[2], tt_3_1_io_update_u_mask_2_REG reg tt_3_1_io_update_u_2_REG : UInt, clock connect tt_3_1_io_update_u_2_REG, s1_update_u[3][2] connect tt_3_1.io.update_u[2], tt_3_1_io_update_u_2_REG reg tt_3_1_io_update_mask_3_REG : UInt<1>, clock connect tt_3_1_io_update_mask_3_REG, s1_update_mask[3][3] connect tt_3_1.io.update_mask[3], tt_3_1_io_update_mask_3_REG reg tt_3_1_io_update_taken_3_REG : UInt<1>, clock connect tt_3_1_io_update_taken_3_REG, s1_update_taken[3][3] connect tt_3_1.io.update_taken[3], tt_3_1_io_update_taken_3_REG reg tt_3_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_3_1_io_update_alloc_3_REG, s1_update_alloc[3][3] connect tt_3_1.io.update_alloc[3], tt_3_1_io_update_alloc_3_REG reg tt_3_1_io_update_old_ctr_3_REG : UInt, clock connect tt_3_1_io_update_old_ctr_3_REG, s1_update_old_ctr[3][3] connect tt_3_1.io.update_old_ctr[3], tt_3_1_io_update_old_ctr_3_REG reg tt_3_1_io_update_u_mask_3_REG : UInt, clock connect tt_3_1_io_update_u_mask_3_REG, s1_update_u_mask[3][3] connect tt_3_1.io.update_u_mask[3], tt_3_1_io_update_u_mask_3_REG reg tt_3_1_io_update_u_3_REG : UInt, clock connect tt_3_1_io_update_u_3_REG, s1_update_u[3][3] connect tt_3_1.io.update_u[3], tt_3_1_io_update_u_3_REG reg tt_3_1_io_update_pc_REG : UInt, clock connect tt_3_1_io_update_pc_REG, s1_update.bits.pc connect tt_3_1.io.update_pc, tt_3_1_io_update_pc_REG reg tt_3_1_io_update_hist_REG : UInt, clock connect tt_3_1_io_update_hist_REG, s1_update.bits.ghist connect tt_3_1.io.update_hist, tt_3_1_io_update_hist_REG reg tt_4_1_io_update_mask_0_REG : UInt<1>, clock connect tt_4_1_io_update_mask_0_REG, s1_update_mask[4][0] connect tt_4_1.io.update_mask[0], tt_4_1_io_update_mask_0_REG reg tt_4_1_io_update_taken_0_REG : UInt<1>, clock connect tt_4_1_io_update_taken_0_REG, s1_update_taken[4][0] connect tt_4_1.io.update_taken[0], tt_4_1_io_update_taken_0_REG reg tt_4_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_0_REG, s1_update_alloc[4][0] connect tt_4_1.io.update_alloc[0], tt_4_1_io_update_alloc_0_REG reg tt_4_1_io_update_old_ctr_0_REG : UInt, clock connect tt_4_1_io_update_old_ctr_0_REG, s1_update_old_ctr[4][0] connect tt_4_1.io.update_old_ctr[0], tt_4_1_io_update_old_ctr_0_REG reg tt_4_1_io_update_u_mask_0_REG : UInt, clock connect tt_4_1_io_update_u_mask_0_REG, s1_update_u_mask[4][0] connect tt_4_1.io.update_u_mask[0], tt_4_1_io_update_u_mask_0_REG reg tt_4_1_io_update_u_0_REG : UInt, clock connect tt_4_1_io_update_u_0_REG, s1_update_u[4][0] connect tt_4_1.io.update_u[0], tt_4_1_io_update_u_0_REG reg tt_4_1_io_update_mask_1_REG : UInt<1>, clock connect tt_4_1_io_update_mask_1_REG, s1_update_mask[4][1] connect tt_4_1.io.update_mask[1], tt_4_1_io_update_mask_1_REG reg tt_4_1_io_update_taken_1_REG : UInt<1>, clock connect tt_4_1_io_update_taken_1_REG, s1_update_taken[4][1] connect tt_4_1.io.update_taken[1], tt_4_1_io_update_taken_1_REG reg tt_4_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_1_REG, s1_update_alloc[4][1] connect tt_4_1.io.update_alloc[1], tt_4_1_io_update_alloc_1_REG reg tt_4_1_io_update_old_ctr_1_REG : UInt, clock connect tt_4_1_io_update_old_ctr_1_REG, s1_update_old_ctr[4][1] connect tt_4_1.io.update_old_ctr[1], tt_4_1_io_update_old_ctr_1_REG reg tt_4_1_io_update_u_mask_1_REG : UInt, clock connect tt_4_1_io_update_u_mask_1_REG, s1_update_u_mask[4][1] connect tt_4_1.io.update_u_mask[1], tt_4_1_io_update_u_mask_1_REG reg tt_4_1_io_update_u_1_REG : UInt, clock connect tt_4_1_io_update_u_1_REG, s1_update_u[4][1] connect tt_4_1.io.update_u[1], tt_4_1_io_update_u_1_REG reg tt_4_1_io_update_mask_2_REG : UInt<1>, clock connect tt_4_1_io_update_mask_2_REG, s1_update_mask[4][2] connect tt_4_1.io.update_mask[2], tt_4_1_io_update_mask_2_REG reg tt_4_1_io_update_taken_2_REG : UInt<1>, clock connect tt_4_1_io_update_taken_2_REG, s1_update_taken[4][2] connect tt_4_1.io.update_taken[2], tt_4_1_io_update_taken_2_REG reg tt_4_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_2_REG, s1_update_alloc[4][2] connect tt_4_1.io.update_alloc[2], tt_4_1_io_update_alloc_2_REG reg tt_4_1_io_update_old_ctr_2_REG : UInt, clock connect tt_4_1_io_update_old_ctr_2_REG, s1_update_old_ctr[4][2] connect tt_4_1.io.update_old_ctr[2], tt_4_1_io_update_old_ctr_2_REG reg tt_4_1_io_update_u_mask_2_REG : UInt, clock connect tt_4_1_io_update_u_mask_2_REG, s1_update_u_mask[4][2] connect tt_4_1.io.update_u_mask[2], tt_4_1_io_update_u_mask_2_REG reg tt_4_1_io_update_u_2_REG : UInt, clock connect tt_4_1_io_update_u_2_REG, s1_update_u[4][2] connect tt_4_1.io.update_u[2], tt_4_1_io_update_u_2_REG reg tt_4_1_io_update_mask_3_REG : UInt<1>, clock connect tt_4_1_io_update_mask_3_REG, s1_update_mask[4][3] connect tt_4_1.io.update_mask[3], tt_4_1_io_update_mask_3_REG reg tt_4_1_io_update_taken_3_REG : UInt<1>, clock connect tt_4_1_io_update_taken_3_REG, s1_update_taken[4][3] connect tt_4_1.io.update_taken[3], tt_4_1_io_update_taken_3_REG reg tt_4_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_4_1_io_update_alloc_3_REG, s1_update_alloc[4][3] connect tt_4_1.io.update_alloc[3], tt_4_1_io_update_alloc_3_REG reg tt_4_1_io_update_old_ctr_3_REG : UInt, clock connect tt_4_1_io_update_old_ctr_3_REG, s1_update_old_ctr[4][3] connect tt_4_1.io.update_old_ctr[3], tt_4_1_io_update_old_ctr_3_REG reg tt_4_1_io_update_u_mask_3_REG : UInt, clock connect tt_4_1_io_update_u_mask_3_REG, s1_update_u_mask[4][3] connect tt_4_1.io.update_u_mask[3], tt_4_1_io_update_u_mask_3_REG reg tt_4_1_io_update_u_3_REG : UInt, clock connect tt_4_1_io_update_u_3_REG, s1_update_u[4][3] connect tt_4_1.io.update_u[3], tt_4_1_io_update_u_3_REG reg tt_4_1_io_update_pc_REG : UInt, clock connect tt_4_1_io_update_pc_REG, s1_update.bits.pc connect tt_4_1.io.update_pc, tt_4_1_io_update_pc_REG reg tt_4_1_io_update_hist_REG : UInt, clock connect tt_4_1_io_update_hist_REG, s1_update.bits.ghist connect tt_4_1.io.update_hist, tt_4_1_io_update_hist_REG reg tt_5_1_io_update_mask_0_REG : UInt<1>, clock connect tt_5_1_io_update_mask_0_REG, s1_update_mask[5][0] connect tt_5_1.io.update_mask[0], tt_5_1_io_update_mask_0_REG reg tt_5_1_io_update_taken_0_REG : UInt<1>, clock connect tt_5_1_io_update_taken_0_REG, s1_update_taken[5][0] connect tt_5_1.io.update_taken[0], tt_5_1_io_update_taken_0_REG reg tt_5_1_io_update_alloc_0_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_0_REG, s1_update_alloc[5][0] connect tt_5_1.io.update_alloc[0], tt_5_1_io_update_alloc_0_REG reg tt_5_1_io_update_old_ctr_0_REG : UInt, clock connect tt_5_1_io_update_old_ctr_0_REG, s1_update_old_ctr[5][0] connect tt_5_1.io.update_old_ctr[0], tt_5_1_io_update_old_ctr_0_REG reg tt_5_1_io_update_u_mask_0_REG : UInt, clock connect tt_5_1_io_update_u_mask_0_REG, s1_update_u_mask[5][0] connect tt_5_1.io.update_u_mask[0], tt_5_1_io_update_u_mask_0_REG reg tt_5_1_io_update_u_0_REG : UInt, clock connect tt_5_1_io_update_u_0_REG, s1_update_u[5][0] connect tt_5_1.io.update_u[0], tt_5_1_io_update_u_0_REG reg tt_5_1_io_update_mask_1_REG : UInt<1>, clock connect tt_5_1_io_update_mask_1_REG, s1_update_mask[5][1] connect tt_5_1.io.update_mask[1], tt_5_1_io_update_mask_1_REG reg tt_5_1_io_update_taken_1_REG : UInt<1>, clock connect tt_5_1_io_update_taken_1_REG, s1_update_taken[5][1] connect tt_5_1.io.update_taken[1], tt_5_1_io_update_taken_1_REG reg tt_5_1_io_update_alloc_1_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_1_REG, s1_update_alloc[5][1] connect tt_5_1.io.update_alloc[1], tt_5_1_io_update_alloc_1_REG reg tt_5_1_io_update_old_ctr_1_REG : UInt, clock connect tt_5_1_io_update_old_ctr_1_REG, s1_update_old_ctr[5][1] connect tt_5_1.io.update_old_ctr[1], tt_5_1_io_update_old_ctr_1_REG reg tt_5_1_io_update_u_mask_1_REG : UInt, clock connect tt_5_1_io_update_u_mask_1_REG, s1_update_u_mask[5][1] connect tt_5_1.io.update_u_mask[1], tt_5_1_io_update_u_mask_1_REG reg tt_5_1_io_update_u_1_REG : UInt, clock connect tt_5_1_io_update_u_1_REG, s1_update_u[5][1] connect tt_5_1.io.update_u[1], tt_5_1_io_update_u_1_REG reg tt_5_1_io_update_mask_2_REG : UInt<1>, clock connect tt_5_1_io_update_mask_2_REG, s1_update_mask[5][2] connect tt_5_1.io.update_mask[2], tt_5_1_io_update_mask_2_REG reg tt_5_1_io_update_taken_2_REG : UInt<1>, clock connect tt_5_1_io_update_taken_2_REG, s1_update_taken[5][2] connect tt_5_1.io.update_taken[2], tt_5_1_io_update_taken_2_REG reg tt_5_1_io_update_alloc_2_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_2_REG, s1_update_alloc[5][2] connect tt_5_1.io.update_alloc[2], tt_5_1_io_update_alloc_2_REG reg tt_5_1_io_update_old_ctr_2_REG : UInt, clock connect tt_5_1_io_update_old_ctr_2_REG, s1_update_old_ctr[5][2] connect tt_5_1.io.update_old_ctr[2], tt_5_1_io_update_old_ctr_2_REG reg tt_5_1_io_update_u_mask_2_REG : UInt, clock connect tt_5_1_io_update_u_mask_2_REG, s1_update_u_mask[5][2] connect tt_5_1.io.update_u_mask[2], tt_5_1_io_update_u_mask_2_REG reg tt_5_1_io_update_u_2_REG : UInt, clock connect tt_5_1_io_update_u_2_REG, s1_update_u[5][2] connect tt_5_1.io.update_u[2], tt_5_1_io_update_u_2_REG reg tt_5_1_io_update_mask_3_REG : UInt<1>, clock connect tt_5_1_io_update_mask_3_REG, s1_update_mask[5][3] connect tt_5_1.io.update_mask[3], tt_5_1_io_update_mask_3_REG reg tt_5_1_io_update_taken_3_REG : UInt<1>, clock connect tt_5_1_io_update_taken_3_REG, s1_update_taken[5][3] connect tt_5_1.io.update_taken[3], tt_5_1_io_update_taken_3_REG reg tt_5_1_io_update_alloc_3_REG : UInt<1>, clock connect tt_5_1_io_update_alloc_3_REG, s1_update_alloc[5][3] connect tt_5_1.io.update_alloc[3], tt_5_1_io_update_alloc_3_REG reg tt_5_1_io_update_old_ctr_3_REG : UInt, clock connect tt_5_1_io_update_old_ctr_3_REG, s1_update_old_ctr[5][3] connect tt_5_1.io.update_old_ctr[3], tt_5_1_io_update_old_ctr_3_REG reg tt_5_1_io_update_u_mask_3_REG : UInt, clock connect tt_5_1_io_update_u_mask_3_REG, s1_update_u_mask[5][3] connect tt_5_1.io.update_u_mask[3], tt_5_1_io_update_u_mask_3_REG reg tt_5_1_io_update_u_3_REG : UInt, clock connect tt_5_1_io_update_u_3_REG, s1_update_u[5][3] connect tt_5_1.io.update_u[3], tt_5_1_io_update_u_3_REG reg tt_5_1_io_update_pc_REG : UInt, clock connect tt_5_1_io_update_pc_REG, s1_update.bits.pc connect tt_5_1.io.update_pc, tt_5_1_io_update_pc_REG reg tt_5_1_io_update_hist_REG : UInt, clock connect tt_5_1_io_update_hist_REG, s1_update.bits.ghist connect tt_5_1.io.update_hist, tt_5_1_io_update_hist_REG node _io_f3_meta_T = cat(f3_meta.allocate[0].valid, f3_meta.allocate[0].bits) node _io_f3_meta_T_1 = cat(f3_meta.allocate[1].valid, f3_meta.allocate[1].bits) node _io_f3_meta_T_2 = cat(f3_meta.allocate[2].valid, f3_meta.allocate[2].bits) node _io_f3_meta_T_3 = cat(f3_meta.allocate[3].valid, f3_meta.allocate[3].bits) node io_f3_meta_lo = cat(_io_f3_meta_T_1, _io_f3_meta_T) node io_f3_meta_hi = cat(_io_f3_meta_T_3, _io_f3_meta_T_2) node _io_f3_meta_T_4 = cat(io_f3_meta_hi, io_f3_meta_lo) node io_f3_meta_lo_1 = cat(f3_meta.provider_ctr[1], f3_meta.provider_ctr[0]) node io_f3_meta_hi_1 = cat(f3_meta.provider_ctr[3], f3_meta.provider_ctr[2]) node _io_f3_meta_T_5 = cat(io_f3_meta_hi_1, io_f3_meta_lo_1) node io_f3_meta_lo_2 = cat(f3_meta.provider_u[1], f3_meta.provider_u[0]) node io_f3_meta_hi_2 = cat(f3_meta.provider_u[3], f3_meta.provider_u[2]) node _io_f3_meta_T_6 = cat(io_f3_meta_hi_2, io_f3_meta_lo_2) node io_f3_meta_lo_3 = cat(f3_meta.alt_differs[1], f3_meta.alt_differs[0]) node io_f3_meta_hi_3 = cat(f3_meta.alt_differs[3], f3_meta.alt_differs[2]) node _io_f3_meta_T_7 = cat(io_f3_meta_hi_3, io_f3_meta_lo_3) node _io_f3_meta_T_8 = cat(f3_meta.provider[0].valid, f3_meta.provider[0].bits) node _io_f3_meta_T_9 = cat(f3_meta.provider[1].valid, f3_meta.provider[1].bits) node _io_f3_meta_T_10 = cat(f3_meta.provider[2].valid, f3_meta.provider[2].bits) node _io_f3_meta_T_11 = cat(f3_meta.provider[3].valid, f3_meta.provider[3].bits) node io_f3_meta_lo_4 = cat(_io_f3_meta_T_9, _io_f3_meta_T_8) node io_f3_meta_hi_4 = cat(_io_f3_meta_T_11, _io_f3_meta_T_10) node _io_f3_meta_T_12 = cat(io_f3_meta_hi_4, io_f3_meta_lo_4) node io_f3_meta_lo_5 = cat(_io_f3_meta_T_5, _io_f3_meta_T_4) node io_f3_meta_hi_hi = cat(_io_f3_meta_T_12, _io_f3_meta_T_7) node io_f3_meta_hi_5 = cat(io_f3_meta_hi_hi, _io_f3_meta_T_6) node _io_f3_meta_T_13 = cat(io_f3_meta_hi_5, io_f3_meta_lo_5) connect io.f3_meta, _io_f3_meta_T_13

module TageBranchPredictorBank_3( // @[tage.scala:198:7] input clock, // @[tage.scala:198:7] input reset, // @[tage.scala:198:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [2:0] s1_update_meta_provider_ctr_3; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_2; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_1; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_ctr_0; // @[tage.scala:236:52] wire _alloc_lfsr_prng_3_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_3_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_2_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_1_io_out_5; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _alloc_lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire io_f0_valid_0 = io_f0_valid; // @[tage.scala:198:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[tage.scala:198:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[tage.scala:198:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[tage.scala:198:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[tage.scala:198:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[tage.scala:198:7] wire io_f3_fire_0 = io_f3_fire; // @[tage.scala:198:7] wire io_update_valid_0 = io_update_valid; // @[tage.scala:198:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[tage.scala:198:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[tage.scala:198:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[tage.scala:198:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[tage.scala:198:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[tage.scala:198:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[tage.scala:198:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[tage.scala:198:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[tage.scala:198:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[tage.scala:198:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[tage.scala:198:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[tage.scala:198:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[tage.scala:198:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[tage.scala:198:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[tage.scala:198:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[tage.scala:198:7] wire io_f1_lhist = 1'h0; // @[tage.scala:198:7] wire _s1_update_mask_WIRE_0_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_0_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_1_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_2_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_3_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_4_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_0 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_1 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_2 = 1'h0; // @[tage.scala:240:48] wire _s1_update_mask_WIRE_5_3 = 1'h0; // @[tage.scala:240:48] wire _s1_update_u_mask_WIRE_0_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_0_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_1_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_2_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_3_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_4_3 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_0 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_1 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_2 = 1'h0; // @[tage.scala:241:50] wire _s1_update_u_mask_WIRE_5_3 = 1'h0; // @[tage.scala:241:50] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[tage.scala:198:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[tage.scala:198:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] wire io_resp_f3_0_taken_0; // @[tage.scala:198:7] wire io_resp_f3_1_taken_0; // @[tage.scala:198:7] wire io_resp_f3_2_taken_0; // @[tage.scala:198:7] wire io_resp_f3_3_taken_0; // @[tage.scala:198:7] wire [119:0] io_f3_meta_0; // @[tage.scala:198:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire _f3_meta_alt_differs_0_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_1_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_2_T; // @[tage.scala:275:48] wire _f3_meta_alt_differs_3_T; // @[tage.scala:275:48] wire _f3_meta_allocate_0_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry; // @[tage.scala:289:26] wire _f3_meta_allocate_1_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_1; // @[tage.scala:289:26] wire _f3_meta_allocate_2_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_2; // @[tage.scala:289:26] wire _f3_meta_allocate_3_valid_T; // @[tage.scala:293:52] wire [2:0] alloc_entry_3; // @[tage.scala:289:26] wire f3_meta_provider_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_0_bits; // @[tage.scala:212:21] wire f3_meta_provider_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_1_bits; // @[tage.scala:212:21] wire f3_meta_provider_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_2_bits; // @[tage.scala:212:21] wire f3_meta_provider_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_3_bits; // @[tage.scala:212:21] wire f3_meta_alt_differs_0; // @[tage.scala:212:21] wire f3_meta_alt_differs_1; // @[tage.scala:212:21] wire f3_meta_alt_differs_2; // @[tage.scala:212:21] wire f3_meta_alt_differs_3; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_0; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_1; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_2; // @[tage.scala:212:21] wire [1:0] f3_meta_provider_u_3; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_0; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_1; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_2; // @[tage.scala:212:21] wire [2:0] f3_meta_provider_ctr_3; // @[tage.scala:212:21] wire f3_meta_allocate_0_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_0_bits; // @[tage.scala:212:21] wire f3_meta_allocate_1_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_1_bits; // @[tage.scala:212:21] wire f3_meta_allocate_2_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_2_bits; // @[tage.scala:212:21] wire f3_meta_allocate_3_valid; // @[tage.scala:212:21] wire [2:0] f3_meta_allocate_3_bits; // @[tage.scala:212:21] wire [3:0] _io_f3_meta_T = {f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_1 = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_2 = {f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_3 = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo = {f3_meta_allocate_1_valid, f3_meta_allocate_1_bits, f3_meta_allocate_0_valid, f3_meta_allocate_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi = {f3_meta_allocate_3_valid, f3_meta_allocate_3_bits, f3_meta_allocate_2_valid, f3_meta_allocate_2_bits}; // @[tage.scala:212:21, :213:33] wire [5:0] _GEN = {f3_meta_provider_ctr_1, f3_meta_provider_ctr_0}; // @[tage.scala:212:21, :213:33] wire [5:0] lo_1; // @[tage.scala:213:33] assign lo_1 = _GEN; // @[tage.scala:213:33] wire [5:0] io_f3_meta_lo_1; // @[tage.scala:359:25] assign io_f3_meta_lo_1 = _GEN; // @[tage.scala:213:33, :359:25] wire [5:0] _GEN_0 = {f3_meta_provider_ctr_3, f3_meta_provider_ctr_2}; // @[tage.scala:212:21, :213:33] wire [5:0] hi_1; // @[tage.scala:213:33] assign hi_1 = _GEN_0; // @[tage.scala:213:33] wire [5:0] io_f3_meta_hi_1; // @[tage.scala:359:25] assign io_f3_meta_hi_1 = _GEN_0; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_1 = {f3_meta_provider_u_1, f3_meta_provider_u_0}; // @[tage.scala:212:21, :213:33] wire [3:0] lo_2; // @[tage.scala:213:33] assign lo_2 = _GEN_1; // @[tage.scala:213:33] wire [3:0] io_f3_meta_lo_2; // @[tage.scala:359:25] assign io_f3_meta_lo_2 = _GEN_1; // @[tage.scala:213:33, :359:25] wire [3:0] _GEN_2 = {f3_meta_provider_u_3, f3_meta_provider_u_2}; // @[tage.scala:212:21, :213:33] wire [3:0] hi_2; // @[tage.scala:213:33] assign hi_2 = _GEN_2; // @[tage.scala:213:33] wire [3:0] io_f3_meta_hi_2; // @[tage.scala:359:25] assign io_f3_meta_hi_2 = _GEN_2; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_3 = {f3_meta_alt_differs_1, f3_meta_alt_differs_0}; // @[tage.scala:212:21, :213:33] wire [1:0] lo_3; // @[tage.scala:213:33] assign lo_3 = _GEN_3; // @[tage.scala:213:33] wire [1:0] io_f3_meta_lo_3; // @[tage.scala:359:25] assign io_f3_meta_lo_3 = _GEN_3; // @[tage.scala:213:33, :359:25] wire [1:0] _GEN_4 = {f3_meta_alt_differs_3, f3_meta_alt_differs_2}; // @[tage.scala:212:21, :213:33] wire [1:0] hi_3; // @[tage.scala:213:33] assign hi_3 = _GEN_4; // @[tage.scala:213:33] wire [1:0] io_f3_meta_hi_3; // @[tage.scala:359:25] assign io_f3_meta_hi_3 = _GEN_4; // @[tage.scala:213:33, :359:25] wire [3:0] _io_f3_meta_T_8 = {f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_9 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_10 = {f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [3:0] _io_f3_meta_T_11 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits}; // @[tage.scala:212:21, :213:33, :359:25] wire [7:0] lo_4 = {f3_meta_provider_1_valid, f3_meta_provider_1_bits, f3_meta_provider_0_valid, f3_meta_provider_0_bits}; // @[tage.scala:212:21, :213:33] wire [7:0] hi_4 = {f3_meta_provider_3_valid, f3_meta_provider_3_bits, f3_meta_provider_2_valid, f3_meta_provider_2_bits}; // @[tage.scala:212:21, :213:33] wire [27:0] lo_5 = {hi_1, lo_1, hi, lo}; // @[tage.scala:213:33] wire [19:0] hi_hi = {hi_4, lo_4, hi_3, lo_3}; // @[tage.scala:213:33] wire [27:0] hi_5 = {hi_hi, hi_2, lo_2}; // @[tage.scala:213:33] reg t_io_f1_req_valid_REG; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_1; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_1; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_2; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_2; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_3; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_3; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_4; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_4; // @[tage.scala:226:35] reg t_io_f1_req_valid_REG_5; // @[tage.scala:225:35] reg [39:0] t_io_f1_req_pc_REG_5; // @[tage.scala:226:35] wire [2:0] f3_resps_0_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_0_bits_u; // @[tage.scala:234:25] wire f3_resps_0_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_1_bits_u; // @[tage.scala:234:25] wire f3_resps_0_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_2_bits_u; // @[tage.scala:234:25] wire f3_resps_0_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_0_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_0_3_bits_u; // @[tage.scala:234:25] wire f3_resps_0_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_0_bits_u; // @[tage.scala:234:25] wire f3_resps_1_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_1_bits_u; // @[tage.scala:234:25] wire f3_resps_1_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_2_bits_u; // @[tage.scala:234:25] wire f3_resps_1_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_1_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_1_3_bits_u; // @[tage.scala:234:25] wire f3_resps_1_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_0_bits_u; // @[tage.scala:234:25] wire f3_resps_2_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_1_bits_u; // @[tage.scala:234:25] wire f3_resps_2_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_2_bits_u; // @[tage.scala:234:25] wire f3_resps_2_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_2_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_2_3_bits_u; // @[tage.scala:234:25] wire f3_resps_2_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_0_bits_u; // @[tage.scala:234:25] wire f3_resps_3_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_1_bits_u; // @[tage.scala:234:25] wire f3_resps_3_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_2_bits_u; // @[tage.scala:234:25] wire f3_resps_3_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_3_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_3_3_bits_u; // @[tage.scala:234:25] wire f3_resps_3_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_0_bits_u; // @[tage.scala:234:25] wire f3_resps_4_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_1_bits_u; // @[tage.scala:234:25] wire f3_resps_4_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_2_bits_u; // @[tage.scala:234:25] wire f3_resps_4_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_4_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_4_3_bits_u; // @[tage.scala:234:25] wire f3_resps_4_3_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_0_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_0_bits_u; // @[tage.scala:234:25] wire f3_resps_5_0_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_1_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_1_bits_u; // @[tage.scala:234:25] wire f3_resps_5_1_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_2_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_2_bits_u; // @[tage.scala:234:25] wire f3_resps_5_2_valid; // @[tage.scala:234:25] wire [2:0] f3_resps_5_3_bits_ctr; // @[tage.scala:234:25] wire [1:0] f3_resps_5_3_bits_u; // @[tage.scala:234:25] wire f3_resps_5_3_valid; // @[tage.scala:234:25] wire _s1_update_meta_T_21; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_20; // @[tage.scala:236:52] wire _s1_update_meta_T_23; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_22; // @[tage.scala:236:52] wire _s1_update_meta_T_25; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_24; // @[tage.scala:236:52] wire _s1_update_meta_T_27; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_26; // @[tage.scala:236:52] wire _s1_update_meta_T_16; // @[tage.scala:236:52] wire _s1_update_meta_T_17; // @[tage.scala:236:52] wire _s1_update_meta_T_18; // @[tage.scala:236:52] wire _s1_update_meta_T_19; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_12; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_13; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_14; // @[tage.scala:236:52] wire [1:0] _s1_update_meta_T_15; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_8; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_9; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_0 = s1_update_meta_provider_ctr_0; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_10; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_1 = s1_update_meta_provider_ctr_1; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T_11; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_2 = s1_update_meta_provider_ctr_2; // @[tage.scala:236:52, :244:31] wire _s1_update_meta_T_1; // @[tage.scala:236:52] wire [2:0] s1_update_old_ctr_0_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_1_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_2_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_3_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_4_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] s1_update_old_ctr_5_3 = s1_update_meta_provider_ctr_3; // @[tage.scala:236:52, :244:31] wire [2:0] _s1_update_meta_T; // @[tage.scala:236:52] wire _s1_update_meta_T_3; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_2; // @[tage.scala:236:52] wire _s1_update_meta_T_5; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_4; // @[tage.scala:236:52] wire _s1_update_meta_T_7; // @[tage.scala:236:52] wire [2:0] _s1_update_meta_T_6; // @[tage.scala:236:52] wire s1_update_meta_provider_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_0_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_1_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_2_bits; // @[tage.scala:236:52] wire s1_update_meta_provider_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_provider_3_bits; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_0; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_1; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_2; // @[tage.scala:236:52] wire s1_update_meta_alt_differs_3; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_0; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_1; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_2; // @[tage.scala:236:52] wire [1:0] s1_update_meta_provider_u_3; // @[tage.scala:236:52] wire s1_update_meta_allocate_0_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_0_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_1_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_1_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_2_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_2_bits; // @[tage.scala:236:52] wire s1_update_meta_allocate_3_valid; // @[tage.scala:236:52] wire [2:0] s1_update_meta_allocate_3_bits; // @[tage.scala:236:52] wire [55:0] _s1_update_meta_WIRE = s1_update_bits_meta[55:0]; // @[tage.scala:236:52] assign _s1_update_meta_T = _s1_update_meta_WIRE[2:0]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_bits = _s1_update_meta_T; // @[tage.scala:236:52] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3]; // @[tage.scala:236:52] assign s1_update_meta_allocate_0_valid = _s1_update_meta_T_1; // @[tage.scala:236:52] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[6:4]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_bits = _s1_update_meta_T_2; // @[tage.scala:236:52] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7]; // @[tage.scala:236:52] assign s1_update_meta_allocate_1_valid = _s1_update_meta_T_3; // @[tage.scala:236:52] assign _s1_update_meta_T_4 = _s1_update_meta_WIRE[10:8]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_bits = _s1_update_meta_T_4; // @[tage.scala:236:52] assign _s1_update_meta_T_5 = _s1_update_meta_WIRE[11]; // @[tage.scala:236:52] assign s1_update_meta_allocate_2_valid = _s1_update_meta_T_5; // @[tage.scala:236:52] assign _s1_update_meta_T_6 = _s1_update_meta_WIRE[14:12]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_bits = _s1_update_meta_T_6; // @[tage.scala:236:52] assign _s1_update_meta_T_7 = _s1_update_meta_WIRE[15]; // @[tage.scala:236:52] assign s1_update_meta_allocate_3_valid = _s1_update_meta_T_7; // @[tage.scala:236:52] assign _s1_update_meta_T_8 = _s1_update_meta_WIRE[18:16]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_0 = _s1_update_meta_T_8; // @[tage.scala:236:52] assign _s1_update_meta_T_9 = _s1_update_meta_WIRE[21:19]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_1 = _s1_update_meta_T_9; // @[tage.scala:236:52] assign _s1_update_meta_T_10 = _s1_update_meta_WIRE[24:22]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_2 = _s1_update_meta_T_10; // @[tage.scala:236:52] assign _s1_update_meta_T_11 = _s1_update_meta_WIRE[27:25]; // @[tage.scala:236:52] assign s1_update_meta_provider_ctr_3 = _s1_update_meta_T_11; // @[tage.scala:236:52] assign _s1_update_meta_T_12 = _s1_update_meta_WIRE[29:28]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_0 = _s1_update_meta_T_12; // @[tage.scala:236:52] assign _s1_update_meta_T_13 = _s1_update_meta_WIRE[31:30]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_1 = _s1_update_meta_T_13; // @[tage.scala:236:52] assign _s1_update_meta_T_14 = _s1_update_meta_WIRE[33:32]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_2 = _s1_update_meta_T_14; // @[tage.scala:236:52] assign _s1_update_meta_T_15 = _s1_update_meta_WIRE[35:34]; // @[tage.scala:236:52] assign s1_update_meta_provider_u_3 = _s1_update_meta_T_15; // @[tage.scala:236:52] assign _s1_update_meta_T_16 = _s1_update_meta_WIRE[36]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_0 = _s1_update_meta_T_16; // @[tage.scala:236:52] assign _s1_update_meta_T_17 = _s1_update_meta_WIRE[37]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_1 = _s1_update_meta_T_17; // @[tage.scala:236:52] assign _s1_update_meta_T_18 = _s1_update_meta_WIRE[38]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_2 = _s1_update_meta_T_18; // @[tage.scala:236:52] assign _s1_update_meta_T_19 = _s1_update_meta_WIRE[39]; // @[tage.scala:236:52] assign s1_update_meta_alt_differs_3 = _s1_update_meta_T_19; // @[tage.scala:236:52] assign _s1_update_meta_T_20 = _s1_update_meta_WIRE[42:40]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_bits = _s1_update_meta_T_20; // @[tage.scala:236:52] assign _s1_update_meta_T_21 = _s1_update_meta_WIRE[43]; // @[tage.scala:236:52] assign s1_update_meta_provider_0_valid = _s1_update_meta_T_21; // @[tage.scala:236:52] assign _s1_update_meta_T_22 = _s1_update_meta_WIRE[46:44]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_bits = _s1_update_meta_T_22; // @[tage.scala:236:52] assign _s1_update_meta_T_23 = _s1_update_meta_WIRE[47]; // @[tage.scala:236:52] assign s1_update_meta_provider_1_valid = _s1_update_meta_T_23; // @[tage.scala:236:52] assign _s1_update_meta_T_24 = _s1_update_meta_WIRE[50:48]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_bits = _s1_update_meta_T_24; // @[tage.scala:236:52] assign _s1_update_meta_T_25 = _s1_update_meta_WIRE[51]; // @[tage.scala:236:52] assign s1_update_meta_provider_2_valid = _s1_update_meta_T_25; // @[tage.scala:236:52] assign _s1_update_meta_T_26 = _s1_update_meta_WIRE[54:52]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_bits = _s1_update_meta_T_26; // @[tage.scala:236:52] assign _s1_update_meta_T_27 = _s1_update_meta_WIRE[55]; // @[tage.scala:236:52] assign s1_update_meta_provider_3_valid = _s1_update_meta_T_27; // @[tage.scala:236:52] wire [3:0] _s1_update_mispredict_mask_T = 4'h1 << s1_update_bits_cfi_idx_bits; // @[OneHot.scala:58:35] wire [3:0] _s1_update_mispredict_mask_T_1 = {4{s1_update_bits_cfi_mispredicted}}; // @[tage.scala:238:9] wire [3:0] s1_update_mispredict_mask = _s1_update_mispredict_mask_T & _s1_update_mispredict_mask_T_1; // @[OneHot.scala:58:35] wire s1_update_mask_0_0; // @[tage.scala:240:33] wire s1_update_mask_0_1; // @[tage.scala:240:33] wire s1_update_mask_0_2; // @[tage.scala:240:33] wire s1_update_mask_0_3; // @[tage.scala:240:33] wire s1_update_mask_1_0; // @[tage.scala:240:33] wire s1_update_mask_1_1; // @[tage.scala:240:33] wire s1_update_mask_1_2; // @[tage.scala:240:33] wire s1_update_mask_1_3; // @[tage.scala:240:33] wire s1_update_mask_2_0; // @[tage.scala:240:33] wire s1_update_mask_2_1; // @[tage.scala:240:33] wire s1_update_mask_2_2; // @[tage.scala:240:33] wire s1_update_mask_2_3; // @[tage.scala:240:33] wire s1_update_mask_3_0; // @[tage.scala:240:33] wire s1_update_mask_3_1; // @[tage.scala:240:33] wire s1_update_mask_3_2; // @[tage.scala:240:33] wire s1_update_mask_3_3; // @[tage.scala:240:33] wire s1_update_mask_4_0; // @[tage.scala:240:33] wire s1_update_mask_4_1; // @[tage.scala:240:33] wire s1_update_mask_4_2; // @[tage.scala:240:33] wire s1_update_mask_4_3; // @[tage.scala:240:33] wire s1_update_mask_5_0; // @[tage.scala:240:33] wire s1_update_mask_5_1; // @[tage.scala:240:33] wire s1_update_mask_5_2; // @[tage.scala:240:33] wire s1_update_mask_5_3; // @[tage.scala:240:33] wire s1_update_u_mask_0_0; // @[tage.scala:241:35] wire s1_update_u_mask_0_1; // @[tage.scala:241:35] wire s1_update_u_mask_0_2; // @[tage.scala:241:35] wire s1_update_u_mask_0_3; // @[tage.scala:241:35] wire s1_update_u_mask_1_0; // @[tage.scala:241:35] wire s1_update_u_mask_1_1; // @[tage.scala:241:35] wire s1_update_u_mask_1_2; // @[tage.scala:241:35] wire s1_update_u_mask_1_3; // @[tage.scala:241:35] wire s1_update_u_mask_2_0; // @[tage.scala:241:35] wire s1_update_u_mask_2_1; // @[tage.scala:241:35] wire s1_update_u_mask_2_2; // @[tage.scala:241:35] wire s1_update_u_mask_2_3; // @[tage.scala:241:35] wire s1_update_u_mask_3_0; // @[tage.scala:241:35] wire s1_update_u_mask_3_1; // @[tage.scala:241:35] wire s1_update_u_mask_3_2; // @[tage.scala:241:35] wire s1_update_u_mask_3_3; // @[tage.scala:241:35] wire s1_update_u_mask_4_0; // @[tage.scala:241:35] wire s1_update_u_mask_4_1; // @[tage.scala:241:35] wire s1_update_u_mask_4_2; // @[tage.scala:241:35] wire s1_update_u_mask_4_3; // @[tage.scala:241:35] wire s1_update_u_mask_5_0; // @[tage.scala:241:35] wire s1_update_u_mask_5_1; // @[tage.scala:241:35] wire s1_update_u_mask_5_2; // @[tage.scala:241:35] wire s1_update_u_mask_5_3; // @[tage.scala:241:35] wire s1_update_taken_0_0; // @[tage.scala:243:31] wire s1_update_taken_0_1; // @[tage.scala:243:31] wire s1_update_taken_0_2; // @[tage.scala:243:31] wire s1_update_taken_0_3; // @[tage.scala:243:31] wire s1_update_taken_1_0; // @[tage.scala:243:31] wire s1_update_taken_1_1; // @[tage.scala:243:31] wire s1_update_taken_1_2; // @[tage.scala:243:31] wire s1_update_taken_1_3; // @[tage.scala:243:31] wire s1_update_taken_2_0; // @[tage.scala:243:31] wire s1_update_taken_2_1; // @[tage.scala:243:31] wire s1_update_taken_2_2; // @[tage.scala:243:31] wire s1_update_taken_2_3; // @[tage.scala:243:31] wire s1_update_taken_3_0; // @[tage.scala:243:31] wire s1_update_taken_3_1; // @[tage.scala:243:31] wire s1_update_taken_3_2; // @[tage.scala:243:31] wire s1_update_taken_3_3; // @[tage.scala:243:31] wire s1_update_taken_4_0; // @[tage.scala:243:31] wire s1_update_taken_4_1; // @[tage.scala:243:31] wire s1_update_taken_4_2; // @[tage.scala:243:31] wire s1_update_taken_4_3; // @[tage.scala:243:31] wire s1_update_taken_5_0; // @[tage.scala:243:31] wire s1_update_taken_5_1; // @[tage.scala:243:31] wire s1_update_taken_5_2; // @[tage.scala:243:31] wire s1_update_taken_5_3; // @[tage.scala:243:31] wire s1_update_alloc_0_0; // @[tage.scala:245:31] wire s1_update_alloc_0_1; // @[tage.scala:245:31] wire s1_update_alloc_0_2; // @[tage.scala:245:31] wire s1_update_alloc_0_3; // @[tage.scala:245:31] wire s1_update_alloc_1_0; // @[tage.scala:245:31] wire s1_update_alloc_1_1; // @[tage.scala:245:31] wire s1_update_alloc_1_2; // @[tage.scala:245:31] wire s1_update_alloc_1_3; // @[tage.scala:245:31] wire s1_update_alloc_2_0; // @[tage.scala:245:31] wire s1_update_alloc_2_1; // @[tage.scala:245:31] wire s1_update_alloc_2_2; // @[tage.scala:245:31] wire s1_update_alloc_2_3; // @[tage.scala:245:31] wire s1_update_alloc_3_0; // @[tage.scala:245:31] wire s1_update_alloc_3_1; // @[tage.scala:245:31] wire s1_update_alloc_3_2; // @[tage.scala:245:31] wire s1_update_alloc_3_3; // @[tage.scala:245:31] wire s1_update_alloc_4_0; // @[tage.scala:245:31] wire s1_update_alloc_4_1; // @[tage.scala:245:31] wire s1_update_alloc_4_2; // @[tage.scala:245:31] wire s1_update_alloc_4_3; // @[tage.scala:245:31] wire s1_update_alloc_5_0; // @[tage.scala:245:31] wire s1_update_alloc_5_1; // @[tage.scala:245:31] wire s1_update_alloc_5_2; // @[tage.scala:245:31] wire s1_update_alloc_5_3; // @[tage.scala:245:31] wire [1:0] s1_update_u_0_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_0_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_1_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_2_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_3_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_4_3; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_0; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_1; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_2; // @[tage.scala:246:31] wire [1:0] s1_update_u_5_3; // @[tage.scala:246:31] wire final_altpred; // @[tage.scala:256:33] wire _io_resp_f3_0_taken_T = f3_resps_0_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_1 = f3_resps_0_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_2 = _io_resp_f3_0_taken_T | _io_resp_f3_0_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_3 = f3_resps_0_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_4 = _io_resp_f3_0_taken_T_2 ? io_resp_in_0_f3_0_taken_0 : _io_resp_f3_0_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_17 = f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_5 = f3_resps_1_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_6 = f3_resps_1_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_7 = _io_resp_f3_0_taken_T_5 | _io_resp_f3_0_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_8 = f3_resps_1_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_9 = _io_resp_f3_0_taken_T_7 ? _T_17 : _io_resp_f3_0_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_21 = f3_resps_1_0_valid ? f3_resps_1_0_bits_ctr[2] : _T_17; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_10 = f3_resps_2_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_11 = f3_resps_2_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_12 = _io_resp_f3_0_taken_T_10 | _io_resp_f3_0_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_13 = f3_resps_2_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_14 = _io_resp_f3_0_taken_T_12 ? _T_21 : _io_resp_f3_0_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_25 = f3_resps_2_0_valid ? f3_resps_2_0_bits_ctr[2] : _T_21; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_15 = f3_resps_3_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_16 = f3_resps_3_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_17 = _io_resp_f3_0_taken_T_15 | _io_resp_f3_0_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_18 = f3_resps_3_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_19 = _io_resp_f3_0_taken_T_17 ? _T_25 : _io_resp_f3_0_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_29 = f3_resps_3_0_valid ? f3_resps_3_0_bits_ctr[2] : _T_25; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_20 = f3_resps_4_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_21 = f3_resps_4_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_22 = _io_resp_f3_0_taken_T_20 | _io_resp_f3_0_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_23 = f3_resps_4_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_24 = _io_resp_f3_0_taken_T_22 ? _T_29 : _io_resp_f3_0_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_33 = f3_resps_4_0_valid ? f3_resps_4_0_bits_ctr[2] : _T_29; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_0_taken_T_25 = f3_resps_5_0_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_0_taken_T_26 = f3_resps_5_0_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_0_taken_T_27 = _io_resp_f3_0_taken_T_25 | _io_resp_f3_0_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_0_taken_T_28 = f3_resps_5_0_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_0_taken_T_29 = _io_resp_f3_0_taken_T_27 ? _T_33 : _io_resp_f3_0_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_0_taken_0 = f3_resps_5_0_valid ? _io_resp_f3_0_taken_T_29 : f3_resps_4_0_valid ? _io_resp_f3_0_taken_T_24 : f3_resps_3_0_valid ? _io_resp_f3_0_taken_T_19 : f3_resps_2_0_valid ? _io_resp_f3_0_taken_T_14 : f3_resps_1_0_valid ? _io_resp_f3_0_taken_T_9 : f3_resps_0_0_valid ? _io_resp_f3_0_taken_T_4 : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred = f3_resps_5_0_valid ? _T_33 : f3_resps_4_0_valid ? _T_29 : f3_resps_3_0_valid ? _T_25 : f3_resps_2_0_valid ? _T_21 : f3_resps_1_0_valid & f3_resps_0_0_valid ? f3_resps_0_0_bits_ctr[2] : io_resp_in_0_f3_0_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_0_valid = f3_resps_0_0_valid | f3_resps_1_0_valid | f3_resps_2_0_valid | f3_resps_3_0_valid | f3_resps_4_0_valid | f3_resps_5_0_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_0_bits = f3_resps_5_0_valid ? 3'h5 : f3_resps_4_0_valid ? 3'h4 : {1'h0, f3_resps_3_0_valid ? 2'h3 : f3_resps_2_0_valid ? 2'h2 : {1'h0, f3_resps_1_0_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_0_T = final_altpred != io_resp_f3_0_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_0 = _f3_meta_alt_differs_0_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_5 = {{f3_resps_0_0_bits_ctr}, {f3_resps_0_0_bits_ctr}, {f3_resps_5_0_bits_ctr}, {f3_resps_4_0_bits_ctr}, {f3_resps_3_0_bits_ctr}, {f3_resps_2_0_bits_ctr}, {f3_resps_1_0_bits_ctr}, {f3_resps_0_0_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_0 = _GEN_5[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_6 = {{f3_resps_0_0_bits_u}, {f3_resps_0_0_bits_u}, {f3_resps_5_0_bits_u}, {f3_resps_4_0_bits_u}, {f3_resps_3_0_bits_u}, {f3_resps_2_0_bits_u}, {f3_resps_1_0_bits_u}, {f3_resps_0_0_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_0 = _GEN_6[f3_meta_provider_0_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T = ~f3_resps_0_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_1 = f3_resps_0_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_2 = _allocatable_slots_T & _allocatable_slots_T_1; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_0 = _allocatable_slots_T_2; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_3 = ~f3_resps_1_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_4 = f3_resps_1_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_5 = _allocatable_slots_T_3 & _allocatable_slots_T_4; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1 = _allocatable_slots_T_5; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_6 = ~f3_resps_2_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_7 = f3_resps_2_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_8 = _allocatable_slots_T_6 & _allocatable_slots_T_7; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2 = _allocatable_slots_T_8; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_9 = ~f3_resps_3_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_10 = f3_resps_3_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_11 = _allocatable_slots_T_9 & _allocatable_slots_T_10; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3 = _allocatable_slots_T_11; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_12 = ~f3_resps_4_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_13 = f3_resps_4_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_14 = _allocatable_slots_T_12 & _allocatable_slots_T_13; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_4 = _allocatable_slots_T_14; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_15 = ~f3_resps_5_0_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_16 = f3_resps_5_0_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_17 = _allocatable_slots_T_15 & _allocatable_slots_T_16; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_5 = _allocatable_slots_T_17; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi = {_allocatable_slots_WIRE_2, _allocatable_slots_WIRE_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo = {allocatable_slots_lo_hi, _allocatable_slots_WIRE_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi = {_allocatable_slots_WIRE_5, _allocatable_slots_WIRE_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi = {allocatable_slots_hi_hi, _allocatable_slots_WIRE_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_18 = {allocatable_slots_hi, allocatable_slots_lo}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_19 = 8'h1 << f3_meta_provider_0_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_20 = _allocatable_slots_T_19; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_21 = {1'h0, _allocatable_slots_T_19[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_22 = {2'h0, _allocatable_slots_T_19[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_23 = {3'h0, _allocatable_slots_T_19[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_24 = {4'h0, _allocatable_slots_T_19[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_25 = {5'h0, _allocatable_slots_T_19[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_26 = {6'h0, _allocatable_slots_T_19[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_27 = {7'h0, _allocatable_slots_T_19[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_28 = _allocatable_slots_T_20 | _allocatable_slots_T_21; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_29 = _allocatable_slots_T_28 | _allocatable_slots_T_22; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_30 = _allocatable_slots_T_29 | _allocatable_slots_T_23; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_31 = _allocatable_slots_T_30 | _allocatable_slots_T_24; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_32 = _allocatable_slots_T_31 | _allocatable_slots_T_25; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_33 = _allocatable_slots_T_32 | _allocatable_slots_T_26; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_34 = _allocatable_slots_T_33 | _allocatable_slots_T_27; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_35 = {6{f3_meta_provider_0_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_36 = {2'h0, _allocatable_slots_T_34[5:0] & _allocatable_slots_T_35}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_37 = ~_allocatable_slots_T_36; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots = {2'h0, _allocatable_slots_T_37[5:0] & _allocatable_slots_T_18}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi = {_alloc_lfsr_prng_io_out_2, _alloc_lfsr_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo = {alloc_lfsr_lo_hi, _alloc_lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi = {_alloc_lfsr_prng_io_out_5, _alloc_lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi = {alloc_lfsr_hi_hi, _alloc_lfsr_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr = {alloc_lfsr_hi, alloc_lfsr_lo}; // @[PRNG.scala:95:17] wire _first_entry_T = allocatable_slots[0]; // @[OneHot.scala:48:45] wire _first_entry_T_1 = allocatable_slots[1]; // @[OneHot.scala:48:45] wire _first_entry_T_2 = allocatable_slots[2]; // @[OneHot.scala:48:45] wire _first_entry_T_3 = allocatable_slots[3]; // @[OneHot.scala:48:45] wire _first_entry_T_4 = allocatable_slots[4]; // @[OneHot.scala:48:45] wire _first_entry_T_5 = allocatable_slots[5]; // @[OneHot.scala:48:45] wire _first_entry_T_6 = allocatable_slots[6]; // @[OneHot.scala:48:45] wire _first_entry_T_7 = allocatable_slots[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_8 = {2'h3, ~_first_entry_T_6}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_9 = _first_entry_T_5 ? 3'h5 : _first_entry_T_8; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_10 = _first_entry_T_4 ? 3'h4 : _first_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_11 = _first_entry_T_3 ? 3'h3 : _first_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_12 = _first_entry_T_2 ? 3'h2 : _first_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_13 = _first_entry_T_1 ? 3'h1 : _first_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] first_entry = _first_entry_T ? 3'h0 : _first_entry_T_13; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T = {2'h0, allocatable_slots[5:0] & alloc_lfsr}; // @[PRNG.scala:95:17] wire _masked_entry_T_1 = _masked_entry_T[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_2 = _masked_entry_T[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_3 = _masked_entry_T[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_4 = _masked_entry_T[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_5 = _masked_entry_T[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_6 = _masked_entry_T[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_7 = _masked_entry_T[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_8 = _masked_entry_T[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_9 = {2'h3, ~_masked_entry_T_7}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_10 = _masked_entry_T_6 ? 3'h5 : _masked_entry_T_9; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_11 = _masked_entry_T_5 ? 3'h4 : _masked_entry_T_10; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_12 = _masked_entry_T_4 ? 3'h3 : _masked_entry_T_11; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_13 = _masked_entry_T_3 ? 3'h2 : _masked_entry_T_12; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_14 = _masked_entry_T_2 ? 3'h1 : _masked_entry_T_13; // @[OneHot.scala:48:45] wire [2:0] masked_entry = _masked_entry_T_1 ? 3'h0 : _masked_entry_T_14; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T = allocatable_slots >> masked_entry; // @[Mux.scala:50:70] wire _alloc_entry_T_1 = _alloc_entry_T[0]; // @[tage.scala:289:44] assign alloc_entry = _alloc_entry_T_1 ? masked_entry : first_entry; // @[Mux.scala:50:70] assign f3_meta_allocate_0_bits = alloc_entry; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_0_valid_T = |allocatable_slots; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_0_valid = _f3_meta_allocate_0_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[tage.scala:297:58] wire _update_was_taken_T_1 = s1_update_bits_cfi_idx_valid & _update_was_taken_T; // @[tage.scala:296:58, :297:58] wire update_was_taken = _update_was_taken_T_1 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire [4:0] _GEN_7 = {s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30] wire _T_44 = s1_update_bits_br_mask[0] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_8 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_9 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_10 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_11 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_12 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_13 = _T_44 & s1_update_meta_provider_0_valid & s1_update_meta_provider_0_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T = s1_update_mispredict_mask[0]; // @[tage.scala:237:73, :308:52] wire _new_u_T_1 = ~s1_update_meta_alt_differs_0; // @[tage.scala:217:9, :236:52] wire _new_u_T_2 = s1_update_meta_provider_u_0 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_14 = {1'h0, s1_update_meta_provider_u_0}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_3 = _GEN_14 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_4 = _new_u_T_3[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_5 = _new_u_T_2 ? 2'h0 : _new_u_T_4; // @[tage.scala:218:{24,27,43}] wire _new_u_T_6 = &s1_update_meta_provider_u_0; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_7 = _GEN_14 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_8 = _new_u_T_7[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_9 = _new_u_T_6 ? 2'h3 : _new_u_T_8; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_10 = _new_u_T ? _new_u_T_5 : _new_u_T_9; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u = _new_u_T_1 ? s1_update_meta_provider_u_0 : _new_u_T_10; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_1; // @[tage.scala:256:33] wire _io_resp_f3_1_taken_T = f3_resps_0_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_1 = f3_resps_0_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_2 = _io_resp_f3_1_taken_T | _io_resp_f3_1_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_3 = f3_resps_0_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_4 = _io_resp_f3_1_taken_T_2 ? io_resp_in_0_f3_1_taken_0 : _io_resp_f3_1_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_48 = f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_5 = f3_resps_1_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_6 = f3_resps_1_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_7 = _io_resp_f3_1_taken_T_5 | _io_resp_f3_1_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_8 = f3_resps_1_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_9 = _io_resp_f3_1_taken_T_7 ? _T_48 : _io_resp_f3_1_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_52 = f3_resps_1_1_valid ? f3_resps_1_1_bits_ctr[2] : _T_48; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_10 = f3_resps_2_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_11 = f3_resps_2_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_12 = _io_resp_f3_1_taken_T_10 | _io_resp_f3_1_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_13 = f3_resps_2_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_14 = _io_resp_f3_1_taken_T_12 ? _T_52 : _io_resp_f3_1_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_56 = f3_resps_2_1_valid ? f3_resps_2_1_bits_ctr[2] : _T_52; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_15 = f3_resps_3_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_16 = f3_resps_3_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_17 = _io_resp_f3_1_taken_T_15 | _io_resp_f3_1_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_18 = f3_resps_3_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_19 = _io_resp_f3_1_taken_T_17 ? _T_56 : _io_resp_f3_1_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_60 = f3_resps_3_1_valid ? f3_resps_3_1_bits_ctr[2] : _T_56; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_20 = f3_resps_4_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_21 = f3_resps_4_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_22 = _io_resp_f3_1_taken_T_20 | _io_resp_f3_1_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_23 = f3_resps_4_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_24 = _io_resp_f3_1_taken_T_22 ? _T_60 : _io_resp_f3_1_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_64 = f3_resps_4_1_valid ? f3_resps_4_1_bits_ctr[2] : _T_60; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_1_taken_T_25 = f3_resps_5_1_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_1_taken_T_26 = f3_resps_5_1_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_1_taken_T_27 = _io_resp_f3_1_taken_T_25 | _io_resp_f3_1_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_1_taken_T_28 = f3_resps_5_1_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_1_taken_T_29 = _io_resp_f3_1_taken_T_27 ? _T_64 : _io_resp_f3_1_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_1_taken_0 = f3_resps_5_1_valid ? _io_resp_f3_1_taken_T_29 : f3_resps_4_1_valid ? _io_resp_f3_1_taken_T_24 : f3_resps_3_1_valid ? _io_resp_f3_1_taken_T_19 : f3_resps_2_1_valid ? _io_resp_f3_1_taken_T_14 : f3_resps_1_1_valid ? _io_resp_f3_1_taken_T_9 : f3_resps_0_1_valid ? _io_resp_f3_1_taken_T_4 : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_1 = f3_resps_5_1_valid ? _T_64 : f3_resps_4_1_valid ? _T_60 : f3_resps_3_1_valid ? _T_56 : f3_resps_2_1_valid ? _T_52 : f3_resps_1_1_valid & f3_resps_0_1_valid ? f3_resps_0_1_bits_ctr[2] : io_resp_in_0_f3_1_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_1_valid = f3_resps_0_1_valid | f3_resps_1_1_valid | f3_resps_2_1_valid | f3_resps_3_1_valid | f3_resps_4_1_valid | f3_resps_5_1_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_1_bits = f3_resps_5_1_valid ? 3'h5 : f3_resps_4_1_valid ? 3'h4 : {1'h0, f3_resps_3_1_valid ? 2'h3 : f3_resps_2_1_valid ? 2'h2 : {1'h0, f3_resps_1_1_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_1_T = final_altpred_1 != io_resp_f3_1_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_1 = _f3_meta_alt_differs_1_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_15 = {{f3_resps_0_1_bits_ctr}, {f3_resps_0_1_bits_ctr}, {f3_resps_5_1_bits_ctr}, {f3_resps_4_1_bits_ctr}, {f3_resps_3_1_bits_ctr}, {f3_resps_2_1_bits_ctr}, {f3_resps_1_1_bits_ctr}, {f3_resps_0_1_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_1 = _GEN_15[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_16 = {{f3_resps_0_1_bits_u}, {f3_resps_0_1_bits_u}, {f3_resps_5_1_bits_u}, {f3_resps_4_1_bits_u}, {f3_resps_3_1_bits_u}, {f3_resps_2_1_bits_u}, {f3_resps_1_1_bits_u}, {f3_resps_0_1_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_1 = _GEN_16[f3_meta_provider_1_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_38 = ~f3_resps_0_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_39 = f3_resps_0_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_40 = _allocatable_slots_T_38 & _allocatable_slots_T_39; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_0 = _allocatable_slots_T_40; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_41 = ~f3_resps_1_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_42 = f3_resps_1_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_43 = _allocatable_slots_T_41 & _allocatable_slots_T_42; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_1 = _allocatable_slots_T_43; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_44 = ~f3_resps_2_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_45 = f3_resps_2_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_46 = _allocatable_slots_T_44 & _allocatable_slots_T_45; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_2 = _allocatable_slots_T_46; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_47 = ~f3_resps_3_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_48 = f3_resps_3_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_49 = _allocatable_slots_T_47 & _allocatable_slots_T_48; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_3 = _allocatable_slots_T_49; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_50 = ~f3_resps_4_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_51 = f3_resps_4_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_52 = _allocatable_slots_T_50 & _allocatable_slots_T_51; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_4 = _allocatable_slots_T_52; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_53 = ~f3_resps_5_1_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_54 = f3_resps_5_1_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_55 = _allocatable_slots_T_53 & _allocatable_slots_T_54; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_1_5 = _allocatable_slots_T_55; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_1 = {_allocatable_slots_WIRE_1_2, _allocatable_slots_WIRE_1_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_1 = {allocatable_slots_lo_hi_1, _allocatable_slots_WIRE_1_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_1 = {_allocatable_slots_WIRE_1_5, _allocatable_slots_WIRE_1_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_1 = {allocatable_slots_hi_hi_1, _allocatable_slots_WIRE_1_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_56 = {allocatable_slots_hi_1, allocatable_slots_lo_1}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_57 = 8'h1 << f3_meta_provider_1_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_58 = _allocatable_slots_T_57; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_59 = {1'h0, _allocatable_slots_T_57[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_60 = {2'h0, _allocatable_slots_T_57[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_61 = {3'h0, _allocatable_slots_T_57[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_62 = {4'h0, _allocatable_slots_T_57[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_63 = {5'h0, _allocatable_slots_T_57[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_64 = {6'h0, _allocatable_slots_T_57[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_65 = {7'h0, _allocatable_slots_T_57[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_66 = _allocatable_slots_T_58 | _allocatable_slots_T_59; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_67 = _allocatable_slots_T_66 | _allocatable_slots_T_60; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_68 = _allocatable_slots_T_67 | _allocatable_slots_T_61; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_69 = _allocatable_slots_T_68 | _allocatable_slots_T_62; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_70 = _allocatable_slots_T_69 | _allocatable_slots_T_63; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_71 = _allocatable_slots_T_70 | _allocatable_slots_T_64; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_72 = _allocatable_slots_T_71 | _allocatable_slots_T_65; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_73 = {6{f3_meta_provider_1_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_74 = {2'h0, _allocatable_slots_T_72[5:0] & _allocatable_slots_T_73}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_75 = ~_allocatable_slots_T_74; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_1 = {2'h0, _allocatable_slots_T_75[5:0] & _allocatable_slots_T_56}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_1 = {_alloc_lfsr_prng_1_io_out_2, _alloc_lfsr_prng_1_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_1 = {alloc_lfsr_lo_hi_1, _alloc_lfsr_prng_1_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_1 = {_alloc_lfsr_prng_1_io_out_5, _alloc_lfsr_prng_1_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_1 = {alloc_lfsr_hi_hi_1, _alloc_lfsr_prng_1_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_1 = {alloc_lfsr_hi_1, alloc_lfsr_lo_1}; // @[PRNG.scala:95:17] wire _first_entry_T_14 = allocatable_slots_1[0]; // @[OneHot.scala:48:45] wire _first_entry_T_15 = allocatable_slots_1[1]; // @[OneHot.scala:48:45] wire _first_entry_T_16 = allocatable_slots_1[2]; // @[OneHot.scala:48:45] wire _first_entry_T_17 = allocatable_slots_1[3]; // @[OneHot.scala:48:45] wire _first_entry_T_18 = allocatable_slots_1[4]; // @[OneHot.scala:48:45] wire _first_entry_T_19 = allocatable_slots_1[5]; // @[OneHot.scala:48:45] wire _first_entry_T_20 = allocatable_slots_1[6]; // @[OneHot.scala:48:45] wire _first_entry_T_21 = allocatable_slots_1[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_22 = {2'h3, ~_first_entry_T_20}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_23 = _first_entry_T_19 ? 3'h5 : _first_entry_T_22; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_24 = _first_entry_T_18 ? 3'h4 : _first_entry_T_23; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_25 = _first_entry_T_17 ? 3'h3 : _first_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_26 = _first_entry_T_16 ? 3'h2 : _first_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_27 = _first_entry_T_15 ? 3'h1 : _first_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] first_entry_1 = _first_entry_T_14 ? 3'h0 : _first_entry_T_27; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_15 = {2'h0, allocatable_slots_1[5:0] & alloc_lfsr_1}; // @[PRNG.scala:95:17] wire _masked_entry_T_16 = _masked_entry_T_15[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_17 = _masked_entry_T_15[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_18 = _masked_entry_T_15[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_19 = _masked_entry_T_15[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_20 = _masked_entry_T_15[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_21 = _masked_entry_T_15[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_22 = _masked_entry_T_15[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_23 = _masked_entry_T_15[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_24 = {2'h3, ~_masked_entry_T_22}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_25 = _masked_entry_T_21 ? 3'h5 : _masked_entry_T_24; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_26 = _masked_entry_T_20 ? 3'h4 : _masked_entry_T_25; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_27 = _masked_entry_T_19 ? 3'h3 : _masked_entry_T_26; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_28 = _masked_entry_T_18 ? 3'h2 : _masked_entry_T_27; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_29 = _masked_entry_T_17 ? 3'h1 : _masked_entry_T_28; // @[OneHot.scala:48:45] wire [2:0] masked_entry_1 = _masked_entry_T_16 ? 3'h0 : _masked_entry_T_29; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_2 = allocatable_slots_1 >> masked_entry_1; // @[Mux.scala:50:70] wire _alloc_entry_T_3 = _alloc_entry_T_2[0]; // @[tage.scala:289:44] assign alloc_entry_1 = _alloc_entry_T_3 ? masked_entry_1 : first_entry_1; // @[Mux.scala:50:70] assign f3_meta_allocate_1_bits = alloc_entry_1; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_1_valid_T = |allocatable_slots_1; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_1_valid = _f3_meta_allocate_1_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_2 = s1_update_bits_cfi_idx_bits == 2'h1; // @[tage.scala:297:58] wire _update_was_taken_T_3 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_2; // @[tage.scala:296:58, :297:58] wire update_was_taken_1 = _update_was_taken_T_3 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_75 = s1_update_bits_br_mask[1] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_17 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_18 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_19 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_20 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_21 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_22 = _T_75 & s1_update_meta_provider_1_valid & s1_update_meta_provider_1_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_11 = s1_update_mispredict_mask[1]; // @[tage.scala:237:73, :308:52] wire _new_u_T_12 = ~s1_update_meta_alt_differs_1; // @[tage.scala:217:9, :236:52] wire _new_u_T_13 = s1_update_meta_provider_u_1 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_23 = {1'h0, s1_update_meta_provider_u_1}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_14 = _GEN_23 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_15 = _new_u_T_14[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_16 = _new_u_T_13 ? 2'h0 : _new_u_T_15; // @[tage.scala:218:{24,27,43}] wire _new_u_T_17 = &s1_update_meta_provider_u_1; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_18 = _GEN_23 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_19 = _new_u_T_18[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_20 = _new_u_T_17 ? 2'h3 : _new_u_T_19; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_21 = _new_u_T_11 ? _new_u_T_16 : _new_u_T_20; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_1 = _new_u_T_12 ? s1_update_meta_provider_u_1 : _new_u_T_21; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_2; // @[tage.scala:256:33] wire _io_resp_f3_2_taken_T = f3_resps_0_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_1 = f3_resps_0_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_2 = _io_resp_f3_2_taken_T | _io_resp_f3_2_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_3 = f3_resps_0_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_4 = _io_resp_f3_2_taken_T_2 ? io_resp_in_0_f3_2_taken_0 : _io_resp_f3_2_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_79 = f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_5 = f3_resps_1_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_6 = f3_resps_1_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_7 = _io_resp_f3_2_taken_T_5 | _io_resp_f3_2_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_8 = f3_resps_1_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_9 = _io_resp_f3_2_taken_T_7 ? _T_79 : _io_resp_f3_2_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_83 = f3_resps_1_2_valid ? f3_resps_1_2_bits_ctr[2] : _T_79; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_10 = f3_resps_2_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_11 = f3_resps_2_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_12 = _io_resp_f3_2_taken_T_10 | _io_resp_f3_2_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_13 = f3_resps_2_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_14 = _io_resp_f3_2_taken_T_12 ? _T_83 : _io_resp_f3_2_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_87 = f3_resps_2_2_valid ? f3_resps_2_2_bits_ctr[2] : _T_83; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_15 = f3_resps_3_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_16 = f3_resps_3_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_17 = _io_resp_f3_2_taken_T_15 | _io_resp_f3_2_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_18 = f3_resps_3_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_19 = _io_resp_f3_2_taken_T_17 ? _T_87 : _io_resp_f3_2_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_91 = f3_resps_3_2_valid ? f3_resps_3_2_bits_ctr[2] : _T_87; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_20 = f3_resps_4_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_21 = f3_resps_4_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_22 = _io_resp_f3_2_taken_T_20 | _io_resp_f3_2_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_23 = f3_resps_4_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_24 = _io_resp_f3_2_taken_T_22 ? _T_91 : _io_resp_f3_2_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_95 = f3_resps_4_2_valid ? f3_resps_4_2_bits_ctr[2] : _T_91; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_2_taken_T_25 = f3_resps_5_2_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_2_taken_T_26 = f3_resps_5_2_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_2_taken_T_27 = _io_resp_f3_2_taken_T_25 | _io_resp_f3_2_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_2_taken_T_28 = f3_resps_5_2_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_2_taken_T_29 = _io_resp_f3_2_taken_T_27 ? _T_95 : _io_resp_f3_2_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_2_taken_0 = f3_resps_5_2_valid ? _io_resp_f3_2_taken_T_29 : f3_resps_4_2_valid ? _io_resp_f3_2_taken_T_24 : f3_resps_3_2_valid ? _io_resp_f3_2_taken_T_19 : f3_resps_2_2_valid ? _io_resp_f3_2_taken_T_14 : f3_resps_1_2_valid ? _io_resp_f3_2_taken_T_9 : f3_resps_0_2_valid ? _io_resp_f3_2_taken_T_4 : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_2 = f3_resps_5_2_valid ? _T_95 : f3_resps_4_2_valid ? _T_91 : f3_resps_3_2_valid ? _T_87 : f3_resps_2_2_valid ? _T_83 : f3_resps_1_2_valid & f3_resps_0_2_valid ? f3_resps_0_2_bits_ctr[2] : io_resp_in_0_f3_2_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_2_valid = f3_resps_0_2_valid | f3_resps_1_2_valid | f3_resps_2_2_valid | f3_resps_3_2_valid | f3_resps_4_2_valid | f3_resps_5_2_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_2_bits = f3_resps_5_2_valid ? 3'h5 : f3_resps_4_2_valid ? 3'h4 : {1'h0, f3_resps_3_2_valid ? 2'h3 : f3_resps_2_2_valid ? 2'h2 : {1'h0, f3_resps_1_2_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_2_T = final_altpred_2 != io_resp_f3_2_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_2 = _f3_meta_alt_differs_2_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_24 = {{f3_resps_0_2_bits_ctr}, {f3_resps_0_2_bits_ctr}, {f3_resps_5_2_bits_ctr}, {f3_resps_4_2_bits_ctr}, {f3_resps_3_2_bits_ctr}, {f3_resps_2_2_bits_ctr}, {f3_resps_1_2_bits_ctr}, {f3_resps_0_2_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_2 = _GEN_24[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_25 = {{f3_resps_0_2_bits_u}, {f3_resps_0_2_bits_u}, {f3_resps_5_2_bits_u}, {f3_resps_4_2_bits_u}, {f3_resps_3_2_bits_u}, {f3_resps_2_2_bits_u}, {f3_resps_1_2_bits_u}, {f3_resps_0_2_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_2 = _GEN_25[f3_meta_provider_2_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_76 = ~f3_resps_0_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_77 = f3_resps_0_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_78 = _allocatable_slots_T_76 & _allocatable_slots_T_77; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_0 = _allocatable_slots_T_78; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_79 = ~f3_resps_1_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_80 = f3_resps_1_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_81 = _allocatable_slots_T_79 & _allocatable_slots_T_80; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_1 = _allocatable_slots_T_81; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_82 = ~f3_resps_2_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_83 = f3_resps_2_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_84 = _allocatable_slots_T_82 & _allocatable_slots_T_83; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_2 = _allocatable_slots_T_84; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_85 = ~f3_resps_3_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_86 = f3_resps_3_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_87 = _allocatable_slots_T_85 & _allocatable_slots_T_86; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_3 = _allocatable_slots_T_87; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_88 = ~f3_resps_4_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_89 = f3_resps_4_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_90 = _allocatable_slots_T_88 & _allocatable_slots_T_89; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_4 = _allocatable_slots_T_90; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_91 = ~f3_resps_5_2_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_92 = f3_resps_5_2_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_93 = _allocatable_slots_T_91 & _allocatable_slots_T_92; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_2_5 = _allocatable_slots_T_93; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_2 = {_allocatable_slots_WIRE_2_2, _allocatable_slots_WIRE_2_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_2 = {allocatable_slots_lo_hi_2, _allocatable_slots_WIRE_2_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_2 = {_allocatable_slots_WIRE_2_5, _allocatable_slots_WIRE_2_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_2 = {allocatable_slots_hi_hi_2, _allocatable_slots_WIRE_2_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_94 = {allocatable_slots_hi_2, allocatable_slots_lo_2}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_95 = 8'h1 << f3_meta_provider_2_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_96 = _allocatable_slots_T_95; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_97 = {1'h0, _allocatable_slots_T_95[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_98 = {2'h0, _allocatable_slots_T_95[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_99 = {3'h0, _allocatable_slots_T_95[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_100 = {4'h0, _allocatable_slots_T_95[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_101 = {5'h0, _allocatable_slots_T_95[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_102 = {6'h0, _allocatable_slots_T_95[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_103 = {7'h0, _allocatable_slots_T_95[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_104 = _allocatable_slots_T_96 | _allocatable_slots_T_97; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_105 = _allocatable_slots_T_104 | _allocatable_slots_T_98; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_106 = _allocatable_slots_T_105 | _allocatable_slots_T_99; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_107 = _allocatable_slots_T_106 | _allocatable_slots_T_100; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_108 = _allocatable_slots_T_107 | _allocatable_slots_T_101; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_109 = _allocatable_slots_T_108 | _allocatable_slots_T_102; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_110 = _allocatable_slots_T_109 | _allocatable_slots_T_103; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_111 = {6{f3_meta_provider_2_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_112 = {2'h0, _allocatable_slots_T_110[5:0] & _allocatable_slots_T_111}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_113 = ~_allocatable_slots_T_112; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_2 = {2'h0, _allocatable_slots_T_113[5:0] & _allocatable_slots_T_94}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_2 = {_alloc_lfsr_prng_2_io_out_2, _alloc_lfsr_prng_2_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_2 = {alloc_lfsr_lo_hi_2, _alloc_lfsr_prng_2_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_2 = {_alloc_lfsr_prng_2_io_out_5, _alloc_lfsr_prng_2_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_2 = {alloc_lfsr_hi_hi_2, _alloc_lfsr_prng_2_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_2 = {alloc_lfsr_hi_2, alloc_lfsr_lo_2}; // @[PRNG.scala:95:17] wire _first_entry_T_28 = allocatable_slots_2[0]; // @[OneHot.scala:48:45] wire _first_entry_T_29 = allocatable_slots_2[1]; // @[OneHot.scala:48:45] wire _first_entry_T_30 = allocatable_slots_2[2]; // @[OneHot.scala:48:45] wire _first_entry_T_31 = allocatable_slots_2[3]; // @[OneHot.scala:48:45] wire _first_entry_T_32 = allocatable_slots_2[4]; // @[OneHot.scala:48:45] wire _first_entry_T_33 = allocatable_slots_2[5]; // @[OneHot.scala:48:45] wire _first_entry_T_34 = allocatable_slots_2[6]; // @[OneHot.scala:48:45] wire _first_entry_T_35 = allocatable_slots_2[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_36 = {2'h3, ~_first_entry_T_34}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_37 = _first_entry_T_33 ? 3'h5 : _first_entry_T_36; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_38 = _first_entry_T_32 ? 3'h4 : _first_entry_T_37; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_39 = _first_entry_T_31 ? 3'h3 : _first_entry_T_38; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_40 = _first_entry_T_30 ? 3'h2 : _first_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_41 = _first_entry_T_29 ? 3'h1 : _first_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] first_entry_2 = _first_entry_T_28 ? 3'h0 : _first_entry_T_41; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_30 = {2'h0, allocatable_slots_2[5:0] & alloc_lfsr_2}; // @[PRNG.scala:95:17] wire _masked_entry_T_31 = _masked_entry_T_30[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_32 = _masked_entry_T_30[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_33 = _masked_entry_T_30[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_34 = _masked_entry_T_30[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_35 = _masked_entry_T_30[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_36 = _masked_entry_T_30[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_37 = _masked_entry_T_30[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_38 = _masked_entry_T_30[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_39 = {2'h3, ~_masked_entry_T_37}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_40 = _masked_entry_T_36 ? 3'h5 : _masked_entry_T_39; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_41 = _masked_entry_T_35 ? 3'h4 : _masked_entry_T_40; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_42 = _masked_entry_T_34 ? 3'h3 : _masked_entry_T_41; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_43 = _masked_entry_T_33 ? 3'h2 : _masked_entry_T_42; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_44 = _masked_entry_T_32 ? 3'h1 : _masked_entry_T_43; // @[OneHot.scala:48:45] wire [2:0] masked_entry_2 = _masked_entry_T_31 ? 3'h0 : _masked_entry_T_44; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_4 = allocatable_slots_2 >> masked_entry_2; // @[Mux.scala:50:70] wire _alloc_entry_T_5 = _alloc_entry_T_4[0]; // @[tage.scala:289:44] assign alloc_entry_2 = _alloc_entry_T_5 ? masked_entry_2 : first_entry_2; // @[Mux.scala:50:70] assign f3_meta_allocate_2_bits = alloc_entry_2; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_2_valid_T = |allocatable_slots_2; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_2_valid = _f3_meta_allocate_2_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_4 = s1_update_bits_cfi_idx_bits == 2'h2; // @[tage.scala:297:58] wire _update_was_taken_T_5 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_4; // @[tage.scala:296:58, :297:58] wire update_was_taken_2 = _update_was_taken_T_5 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_106 = s1_update_bits_br_mask[2] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_26 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_27 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_28 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_29 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_30 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_31 = _T_106 & s1_update_meta_provider_2_valid & s1_update_meta_provider_2_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_22 = s1_update_mispredict_mask[2]; // @[tage.scala:237:73, :308:52] wire _new_u_T_23 = ~s1_update_meta_alt_differs_2; // @[tage.scala:217:9, :236:52] wire _new_u_T_24 = s1_update_meta_provider_u_2 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_32 = {1'h0, s1_update_meta_provider_u_2}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_25 = _GEN_32 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_26 = _new_u_T_25[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_27 = _new_u_T_24 ? 2'h0 : _new_u_T_26; // @[tage.scala:218:{24,27,43}] wire _new_u_T_28 = &s1_update_meta_provider_u_2; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_29 = _GEN_32 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_30 = _new_u_T_29[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_31 = _new_u_T_28 ? 2'h3 : _new_u_T_30; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_32 = _new_u_T_22 ? _new_u_T_27 : _new_u_T_31; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_2 = _new_u_T_23 ? s1_update_meta_provider_u_2 : _new_u_T_32; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire final_altpred_3; // @[tage.scala:256:33] wire _io_resp_f3_3_taken_T = f3_resps_0_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_1 = f3_resps_0_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_2 = _io_resp_f3_3_taken_T | _io_resp_f3_3_taken_T_1; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_3 = f3_resps_0_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_4 = _io_resp_f3_3_taken_T_2 ? io_resp_in_0_f3_3_taken_0 : _io_resp_f3_3_taken_T_3; // @[tage.scala:198:7, :265:{35,48,76}] wire _T_110 = f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_5 = f3_resps_1_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_6 = f3_resps_1_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_7 = _io_resp_f3_3_taken_T_5 | _io_resp_f3_3_taken_T_6; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_8 = f3_resps_1_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_9 = _io_resp_f3_3_taken_T_7 ? _T_110 : _io_resp_f3_3_taken_T_8; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_114 = f3_resps_1_3_valid ? f3_resps_1_3_bits_ctr[2] : _T_110; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_10 = f3_resps_2_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_11 = f3_resps_2_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_12 = _io_resp_f3_3_taken_T_10 | _io_resp_f3_3_taken_T_11; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_13 = f3_resps_2_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_14 = _io_resp_f3_3_taken_T_12 ? _T_114 : _io_resp_f3_3_taken_T_13; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_118 = f3_resps_2_3_valid ? f3_resps_2_3_bits_ctr[2] : _T_114; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_15 = f3_resps_3_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_16 = f3_resps_3_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_17 = _io_resp_f3_3_taken_T_15 | _io_resp_f3_3_taken_T_16; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_18 = f3_resps_3_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_19 = _io_resp_f3_3_taken_T_17 ? _T_118 : _io_resp_f3_3_taken_T_18; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_122 = f3_resps_3_3_valid ? f3_resps_3_3_bits_ctr[2] : _T_118; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_20 = f3_resps_4_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_21 = f3_resps_4_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_22 = _io_resp_f3_3_taken_T_20 | _io_resp_f3_3_taken_T_21; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_23 = f3_resps_4_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_24 = _io_resp_f3_3_taken_T_22 ? _T_122 : _io_resp_f3_3_taken_T_23; // @[tage.scala:265:{35,48,76}, :271:21] wire _T_126 = f3_resps_4_3_valid ? f3_resps_4_3_bits_ctr[2] : _T_122; // @[tage.scala:234:25, :271:{21,50}] wire _io_resp_f3_3_taken_T_25 = f3_resps_5_3_bits_ctr == 3'h3; // @[tage.scala:234:25, :265:40] wire _io_resp_f3_3_taken_T_26 = f3_resps_5_3_bits_ctr == 3'h4; // @[tage.scala:234:25, :265:55] wire _io_resp_f3_3_taken_T_27 = _io_resp_f3_3_taken_T_25 | _io_resp_f3_3_taken_T_26; // @[tage.scala:265:{40,48,55}] wire _io_resp_f3_3_taken_T_28 = f3_resps_5_3_bits_ctr[2]; // @[tage.scala:234:25, :265:76] wire _io_resp_f3_3_taken_T_29 = _io_resp_f3_3_taken_T_27 ? _T_126 : _io_resp_f3_3_taken_T_28; // @[tage.scala:265:{35,48,76}, :271:21] assign io_resp_f3_3_taken_0 = f3_resps_5_3_valid ? _io_resp_f3_3_taken_T_29 : f3_resps_4_3_valid ? _io_resp_f3_3_taken_T_24 : f3_resps_3_3_valid ? _io_resp_f3_3_taken_T_19 : f3_resps_2_3_valid ? _io_resp_f3_3_taken_T_14 : f3_resps_1_3_valid ? _io_resp_f3_3_taken_T_9 : f3_resps_0_3_valid ? _io_resp_f3_3_taken_T_4 : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :259:25, :264:18, :265:{29,35}] assign final_altpred_3 = f3_resps_5_3_valid ? _T_126 : f3_resps_4_3_valid ? _T_122 : f3_resps_3_3_valid ? _T_118 : f3_resps_2_3_valid ? _T_114 : f3_resps_1_3_valid & f3_resps_0_3_valid ? f3_resps_0_3_bits_ctr[2] : io_resp_in_0_f3_3_taken_0; // @[tage.scala:198:7, :234:25, :256:33, :264:18, :266:29, :271:{21,50}] assign f3_meta_provider_3_valid = f3_resps_0_3_valid | f3_resps_1_3_valid | f3_resps_2_3_valid | f3_resps_3_3_valid | f3_resps_4_3_valid | f3_resps_5_3_valid; // @[tage.scala:212:21, :234:25, :269:27] assign f3_meta_provider_3_bits = f3_resps_5_3_valid ? 3'h5 : f3_resps_4_3_valid ? 3'h4 : {1'h0, f3_resps_3_3_valid ? 2'h3 : f3_resps_2_3_valid ? 2'h2 : {1'h0, f3_resps_1_3_valid}}; // @[tage.scala:212:21, :234:25, :270:21] assign _f3_meta_alt_differs_3_T = final_altpred_3 != io_resp_f3_3_taken_0; // @[tage.scala:198:7, :256:33, :275:48] assign f3_meta_alt_differs_3 = _f3_meta_alt_differs_3_T; // @[tage.scala:212:21, :275:48] wire [7:0][2:0] _GEN_33 = {{f3_resps_0_3_bits_ctr}, {f3_resps_0_3_bits_ctr}, {f3_resps_5_3_bits_ctr}, {f3_resps_4_3_bits_ctr}, {f3_resps_3_3_bits_ctr}, {f3_resps_2_3_bits_ctr}, {f3_resps_1_3_bits_ctr}, {f3_resps_0_3_bits_ctr}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_ctr_3 = _GEN_33[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire [7:0][1:0] _GEN_34 = {{f3_resps_0_3_bits_u}, {f3_resps_0_3_bits_u}, {f3_resps_5_3_bits_u}, {f3_resps_4_3_bits_u}, {f3_resps_3_3_bits_u}, {f3_resps_2_3_bits_u}, {f3_resps_1_3_bits_u}, {f3_resps_0_3_bits_u}}; // @[tage.scala:234:25, :276:31] assign f3_meta_provider_u_3 = _GEN_34[f3_meta_provider_3_bits]; // @[tage.scala:212:21, :276:31] wire _allocatable_slots_T_114 = ~f3_resps_0_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_115 = f3_resps_0_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_116 = _allocatable_slots_T_114 & _allocatable_slots_T_115; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_0 = _allocatable_slots_T_116; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_117 = ~f3_resps_1_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_118 = f3_resps_1_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_119 = _allocatable_slots_T_117 & _allocatable_slots_T_118; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_1 = _allocatable_slots_T_119; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_120 = ~f3_resps_2_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_121 = f3_resps_2_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_122 = _allocatable_slots_T_120 & _allocatable_slots_T_121; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_2 = _allocatable_slots_T_122; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_123 = ~f3_resps_3_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_124 = f3_resps_3_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_125 = _allocatable_slots_T_123 & _allocatable_slots_T_124; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_3 = _allocatable_slots_T_125; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_126 = ~f3_resps_4_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_127 = f3_resps_4_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_128 = _allocatable_slots_T_126 & _allocatable_slots_T_127; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_4 = _allocatable_slots_T_128; // @[tage.scala:282:{14,45}] wire _allocatable_slots_T_129 = ~f3_resps_5_3_valid; // @[tage.scala:234:25, :282:33] wire _allocatable_slots_T_130 = f3_resps_5_3_bits_u == 2'h0; // @[tage.scala:234:25, :282:60] wire _allocatable_slots_T_131 = _allocatable_slots_T_129 & _allocatable_slots_T_130; // @[tage.scala:282:{33,45,60}] wire _allocatable_slots_WIRE_3_5 = _allocatable_slots_T_131; // @[tage.scala:282:{14,45}] wire [1:0] allocatable_slots_lo_hi_3 = {_allocatable_slots_WIRE_3_2, _allocatable_slots_WIRE_3_1}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_lo_3 = {allocatable_slots_lo_hi_3, _allocatable_slots_WIRE_3_0}; // @[tage.scala:282:{14,70}] wire [1:0] allocatable_slots_hi_hi_3 = {_allocatable_slots_WIRE_3_5, _allocatable_slots_WIRE_3_4}; // @[tage.scala:282:{14,70}] wire [2:0] allocatable_slots_hi_3 = {allocatable_slots_hi_hi_3, _allocatable_slots_WIRE_3_3}; // @[tage.scala:282:{14,70}] wire [5:0] _allocatable_slots_T_132 = {allocatable_slots_hi_3, allocatable_slots_lo_3}; // @[tage.scala:282:70] wire [7:0] _allocatable_slots_T_133 = 8'h1 << f3_meta_provider_3_bits; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_134 = _allocatable_slots_T_133; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_135 = {1'h0, _allocatable_slots_T_133[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_136 = {2'h0, _allocatable_slots_T_133[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_137 = {3'h0, _allocatable_slots_T_133[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_138 = {4'h0, _allocatable_slots_T_133[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_139 = {5'h0, _allocatable_slots_T_133[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_140 = {6'h0, _allocatable_slots_T_133[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_141 = {7'h0, _allocatable_slots_T_133[7]}; // @[OneHot.scala:58:35] wire [7:0] _allocatable_slots_T_142 = _allocatable_slots_T_134 | _allocatable_slots_T_135; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_143 = _allocatable_slots_T_142 | _allocatable_slots_T_136; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_144 = _allocatable_slots_T_143 | _allocatable_slots_T_137; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_145 = _allocatable_slots_T_144 | _allocatable_slots_T_138; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_146 = _allocatable_slots_T_145 | _allocatable_slots_T_139; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_147 = _allocatable_slots_T_146 | _allocatable_slots_T_140; // @[util.scala:373:{29,45}] wire [7:0] _allocatable_slots_T_148 = _allocatable_slots_T_147 | _allocatable_slots_T_141; // @[util.scala:373:{29,45}] wire [5:0] _allocatable_slots_T_149 = {6{f3_meta_provider_3_valid}}; // @[tage.scala:212:21, :283:45] wire [7:0] _allocatable_slots_T_150 = {2'h0, _allocatable_slots_T_148[5:0] & _allocatable_slots_T_149}; // @[util.scala:373:45] wire [7:0] _allocatable_slots_T_151 = ~_allocatable_slots_T_150; // @[tage.scala:283:{7,39}] wire [7:0] allocatable_slots_3 = {2'h0, _allocatable_slots_T_151[5:0] & _allocatable_slots_T_132}; // @[tage.scala:282:{70,77}, :283:7] wire [1:0] alloc_lfsr_lo_hi_3 = {_alloc_lfsr_prng_3_io_out_2, _alloc_lfsr_prng_3_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_lo_3 = {alloc_lfsr_lo_hi_3, _alloc_lfsr_prng_3_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] alloc_lfsr_hi_hi_3 = {_alloc_lfsr_prng_3_io_out_5, _alloc_lfsr_prng_3_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [2:0] alloc_lfsr_hi_3 = {alloc_lfsr_hi_hi_3, _alloc_lfsr_prng_3_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [5:0] alloc_lfsr_3 = {alloc_lfsr_hi_3, alloc_lfsr_lo_3}; // @[PRNG.scala:95:17] wire _first_entry_T_42 = allocatable_slots_3[0]; // @[OneHot.scala:48:45] wire _first_entry_T_43 = allocatable_slots_3[1]; // @[OneHot.scala:48:45] wire _first_entry_T_44 = allocatable_slots_3[2]; // @[OneHot.scala:48:45] wire _first_entry_T_45 = allocatable_slots_3[3]; // @[OneHot.scala:48:45] wire _first_entry_T_46 = allocatable_slots_3[4]; // @[OneHot.scala:48:45] wire _first_entry_T_47 = allocatable_slots_3[5]; // @[OneHot.scala:48:45] wire _first_entry_T_48 = allocatable_slots_3[6]; // @[OneHot.scala:48:45] wire _first_entry_T_49 = allocatable_slots_3[7]; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_50 = {2'h3, ~_first_entry_T_48}; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_51 = _first_entry_T_47 ? 3'h5 : _first_entry_T_50; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_52 = _first_entry_T_46 ? 3'h4 : _first_entry_T_51; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_53 = _first_entry_T_45 ? 3'h3 : _first_entry_T_52; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_54 = _first_entry_T_44 ? 3'h2 : _first_entry_T_53; // @[OneHot.scala:48:45] wire [2:0] _first_entry_T_55 = _first_entry_T_43 ? 3'h1 : _first_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] first_entry_3 = _first_entry_T_42 ? 3'h0 : _first_entry_T_55; // @[OneHot.scala:48:45] wire [7:0] _masked_entry_T_45 = {2'h0, allocatable_slots_3[5:0] & alloc_lfsr_3}; // @[PRNG.scala:95:17] wire _masked_entry_T_46 = _masked_entry_T_45[0]; // @[OneHot.scala:48:45] wire _masked_entry_T_47 = _masked_entry_T_45[1]; // @[OneHot.scala:48:45] wire _masked_entry_T_48 = _masked_entry_T_45[2]; // @[OneHot.scala:48:45] wire _masked_entry_T_49 = _masked_entry_T_45[3]; // @[OneHot.scala:48:45] wire _masked_entry_T_50 = _masked_entry_T_45[4]; // @[OneHot.scala:48:45] wire _masked_entry_T_51 = _masked_entry_T_45[5]; // @[OneHot.scala:48:45] wire _masked_entry_T_52 = _masked_entry_T_45[6]; // @[OneHot.scala:48:45] wire _masked_entry_T_53 = _masked_entry_T_45[7]; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_54 = {2'h3, ~_masked_entry_T_52}; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_55 = _masked_entry_T_51 ? 3'h5 : _masked_entry_T_54; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_56 = _masked_entry_T_50 ? 3'h4 : _masked_entry_T_55; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_57 = _masked_entry_T_49 ? 3'h3 : _masked_entry_T_56; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_58 = _masked_entry_T_48 ? 3'h2 : _masked_entry_T_57; // @[OneHot.scala:48:45] wire [2:0] _masked_entry_T_59 = _masked_entry_T_47 ? 3'h1 : _masked_entry_T_58; // @[OneHot.scala:48:45] wire [2:0] masked_entry_3 = _masked_entry_T_46 ? 3'h0 : _masked_entry_T_59; // @[OneHot.scala:48:45] wire [7:0] _alloc_entry_T_6 = allocatable_slots_3 >> masked_entry_3; // @[Mux.scala:50:70] wire _alloc_entry_T_7 = _alloc_entry_T_6[0]; // @[tage.scala:289:44] assign alloc_entry_3 = _alloc_entry_T_7 ? masked_entry_3 : first_entry_3; // @[Mux.scala:50:70] assign f3_meta_allocate_3_bits = alloc_entry_3; // @[tage.scala:212:21, :289:26] assign _f3_meta_allocate_3_valid_T = |allocatable_slots_3; // @[tage.scala:282:77, :293:52] assign f3_meta_allocate_3_valid = _f3_meta_allocate_3_valid_T; // @[tage.scala:212:21, :293:52] wire _update_was_taken_T_6 = &s1_update_bits_cfi_idx_bits; // @[tage.scala:297:58] wire _update_was_taken_T_7 = s1_update_bits_cfi_idx_valid & _update_was_taken_T_6; // @[tage.scala:296:58, :297:58] wire update_was_taken_3 = _update_was_taken_T_7 & s1_update_bits_cfi_taken; // @[tage.scala:296:58, :297:67] wire _T_137 = s1_update_bits_br_mask[3] & s1_update_valid & _GEN_7 == 5'h0; // @[OneHot.scala:58:35] wire _GEN_35 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h0; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_36 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h1; // @[tage.scala:218:43, :236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_37 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h2; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_38 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h3; // @[tage.scala:236:52, :240:33, :265:40, :299:{37,56,92}, :300:47, :303:37] wire _GEN_39 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h4; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _GEN_40 = _T_137 & s1_update_meta_provider_3_valid & s1_update_meta_provider_3_bits == 3'h5; // @[tage.scala:236:52, :240:33, :299:{37,56,92}, :300:47, :303:37] wire _new_u_T_33 = s1_update_mispredict_mask[3]; // @[tage.scala:237:73, :308:52] wire _new_u_T_34 = ~s1_update_meta_alt_differs_3; // @[tage.scala:217:9, :236:52] wire _new_u_T_35 = s1_update_meta_provider_u_3 == 2'h0; // @[tage.scala:218:27, :236:52] wire [2:0] _GEN_41 = {1'h0, s1_update_meta_provider_u_3}; // @[tage.scala:218:43, :236:52] wire [2:0] _new_u_T_36 = _GEN_41 - 3'h1; // @[tage.scala:218:43] wire [1:0] _new_u_T_37 = _new_u_T_36[1:0]; // @[tage.scala:218:43] wire [1:0] _new_u_T_38 = _new_u_T_35 ? 2'h0 : _new_u_T_37; // @[tage.scala:218:{24,27,43}] wire _new_u_T_39 = &s1_update_meta_provider_u_3; // @[tage.scala:219:27, :236:52] wire [2:0] _new_u_T_40 = _GEN_41 + 3'h1; // @[tage.scala:218:43, :219:43] wire [1:0] _new_u_T_41 = _new_u_T_40[1:0]; // @[tage.scala:219:43] wire [1:0] _new_u_T_42 = _new_u_T_39 ? 2'h3 : _new_u_T_41; // @[tage.scala:219:{24,27,43}] wire [1:0] _new_u_T_43 = _new_u_T_33 ? _new_u_T_38 : _new_u_T_42; // @[tage.scala:218:{8,24}, :219:24, :308:52] wire [1:0] new_u_3 = _new_u_T_34 ? s1_update_meta_provider_u_3 : _new_u_T_43; // @[tage.scala:217:{8,9}, :218:8, :236:52] wire _T_144 = s1_update_valid & _GEN_7 == 5'h0 & s1_update_bits_cfi_mispredicted & s1_update_bits_cfi_idx_valid; // @[OneHot.scala:58:35] wire [3:0] _GEN_42 = {{s1_update_meta_allocate_3_valid}, {s1_update_meta_allocate_2_valid}, {s1_update_meta_allocate_1_valid}, {s1_update_meta_allocate_0_valid}}; // @[tage.scala:236:52, :320:27] wire _GEN_43 = _GEN_42[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire [3:0][2:0] _GEN_44 = {{s1_update_meta_allocate_3_bits}, {s1_update_meta_allocate_2_bits}, {s1_update_meta_allocate_1_bits}, {s1_update_meta_allocate_0_bits}}; // @[tage.scala:236:52, :320:27] wire [2:0] _GEN_45 = _GEN_44[s1_update_bits_cfi_idx_bits]; // @[tage.scala:320:27] wire _GEN_46 = _GEN_45 == 3'h0; // @[tage.scala:320:27, :321:43] wire _GEN_47 = _T_144 & _GEN_43 & _GEN_46; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_0_0 = _GEN_47 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_0 = s1_update_alloc_0_0 | _GEN_8; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_1 = _GEN_47 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_1 = s1_update_alloc_0_1 | _GEN_17; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_2 = _GEN_47 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_2 = s1_update_alloc_0_2 | _GEN_26; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_0_3 = _GEN_47 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_0_3 = s1_update_alloc_0_3 | _GEN_35; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_48 = _GEN_45 == 3'h1; // @[tage.scala:218:43, :320:27, :321:43] wire _GEN_49 = _T_144 & _GEN_43 & _GEN_48; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_1_0 = _GEN_49 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_0 = s1_update_alloc_1_0 | _GEN_9; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_1 = _GEN_49 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_1 = s1_update_alloc_1_1 | _GEN_18; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_2 = _GEN_49 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_2 = s1_update_alloc_1_2 | _GEN_27; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_1_3 = _GEN_49 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_1_3 = s1_update_alloc_1_3 | _GEN_36; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_50 = _GEN_45 == 3'h2; // @[tage.scala:320:27, :321:43] wire _GEN_51 = _T_144 & _GEN_43 & _GEN_50; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_2_0 = _GEN_51 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_0 = s1_update_alloc_2_0 | _GEN_10; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_1 = _GEN_51 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_1 = s1_update_alloc_2_1 | _GEN_19; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_2 = _GEN_51 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_2 = s1_update_alloc_2_2 | _GEN_28; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_2_3 = _GEN_51 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_2_3 = s1_update_alloc_2_3 | _GEN_37; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_52 = _GEN_45 == 3'h3; // @[tage.scala:265:40, :320:27, :321:43] wire _GEN_53 = _T_144 & _GEN_43 & _GEN_52; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_3_0 = _GEN_53 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_0 = s1_update_alloc_3_0 | _GEN_11; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_1 = _GEN_53 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_1 = s1_update_alloc_3_1 | _GEN_20; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_2 = _GEN_53 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_2 = s1_update_alloc_3_2 | _GEN_29; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_3_3 = _GEN_53 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_3_3 = s1_update_alloc_3_3 | _GEN_38; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_54 = _GEN_45 == 3'h4; // @[tage.scala:320:27, :321:43] wire _GEN_55 = _T_144 & _GEN_43 & _GEN_54; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_4_0 = _GEN_55 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_0 = s1_update_alloc_4_0 | _GEN_12; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_1 = _GEN_55 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_1 = s1_update_alloc_4_1 | _GEN_21; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_2 = _GEN_55 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_2 = s1_update_alloc_4_2 | _GEN_30; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_4_3 = _GEN_55 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_4_3 = s1_update_alloc_4_3 | _GEN_39; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_56 = _GEN_45 == 3'h5; // @[tage.scala:320:27, :321:43] wire _GEN_57 = _T_144 & _GEN_43 & _GEN_56; // @[tage.scala:299:92, :317:{25,60,95,128}, :320:27, :321:43] assign s1_update_alloc_5_0 = _GEN_57 & _update_was_taken_T; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_0 = s1_update_alloc_5_0 | _GEN_13; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_1 = _GEN_57 & _update_was_taken_T_2; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_1 = s1_update_alloc_5_1 | _GEN_22; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_2 = _GEN_57 & _update_was_taken_T_4; // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_2 = s1_update_alloc_5_2 | _GEN_31; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] assign s1_update_alloc_5_3 = _GEN_57 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:245:31, :297:58, :299:92, :317:128, :320:27, :321:43] assign s1_update_mask_5_3 = s1_update_alloc_5_3 | _GEN_40; // @[tage.scala:240:33, :245:31, :299:92, :300:47, :303:37, :317:128, :320:27, :321:43] wire _GEN_58 = _GEN_46 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_0 = _T_144 & _GEN_43 & _GEN_58 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_59 = _GEN_46 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_1 = _T_144 & _GEN_43 & _GEN_59 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_60 = _GEN_46 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_2 = _T_144 & _GEN_43 & _GEN_60 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_61 = _GEN_46 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_0_3 = _T_144 & _GEN_43 & _GEN_61 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_62 = _GEN_48 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_0 = _T_144 & _GEN_43 & _GEN_62 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_63 = _GEN_48 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_1 = _T_144 & _GEN_43 & _GEN_63 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_64 = _GEN_48 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_2 = _T_144 & _GEN_43 & _GEN_64 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_65 = _GEN_48 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_1_3 = _T_144 & _GEN_43 & _GEN_65 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_66 = _GEN_50 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_0 = _T_144 & _GEN_43 & _GEN_66 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_67 = _GEN_50 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_1 = _T_144 & _GEN_43 & _GEN_67 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_68 = _GEN_50 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_2 = _T_144 & _GEN_43 & _GEN_68 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_69 = _GEN_50 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_2_3 = _T_144 & _GEN_43 & _GEN_69 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_70 = _GEN_52 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_0 = _T_144 & _GEN_43 & _GEN_70 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_71 = _GEN_52 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_1 = _T_144 & _GEN_43 & _GEN_71 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_72 = _GEN_52 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_2 = _T_144 & _GEN_43 & _GEN_72 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_73 = _GEN_52 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_3_3 = _T_144 & _GEN_43 & _GEN_73 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_74 = _GEN_54 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_0 = _T_144 & _GEN_43 & _GEN_74 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_75 = _GEN_54 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_1 = _T_144 & _GEN_43 & _GEN_75 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_76 = _GEN_54 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_2 = _T_144 & _GEN_43 & _GEN_76 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_77 = _GEN_54 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_4_3 = _T_144 & _GEN_43 & _GEN_77 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_78 = _GEN_56 & _update_was_taken_T; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_0 = _T_144 & _GEN_43 & _GEN_78 ? s1_update_bits_cfi_taken : update_was_taken; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_79 = _GEN_56 & _update_was_taken_T_2; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_1 = _T_144 & _GEN_43 & _GEN_79 ? s1_update_bits_cfi_taken : update_was_taken_1; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_80 = _GEN_56 & _update_was_taken_T_4; // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_2 = _T_144 & _GEN_43 & _GEN_80 ? s1_update_bits_cfi_taken : update_was_taken_2; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire _GEN_81 = _GEN_56 & (&s1_update_bits_cfi_idx_bits); // @[tage.scala:297:58, :299:92, :321:43, :322:43] assign s1_update_taken_5_3 = _T_144 & _GEN_43 & _GEN_81 ? s1_update_bits_cfi_taken : update_was_taken_3; // @[tage.scala:243:31, :297:67, :299:92, :317:{25,60,95,128}, :320:27, :322:43] wire [3:0] _GEN_82 = {{s1_update_meta_provider_3_valid}, {s1_update_meta_provider_2_valid}, {s1_update_meta_provider_1_valid}, {s1_update_meta_provider_0_valid}}; // @[OneHot.scala:58:35] wire [3:0][2:0] _GEN_83 = {{s1_update_meta_provider_3_bits}, {s1_update_meta_provider_2_bits}, {s1_update_meta_provider_1_bits}, {s1_update_meta_provider_0_bits}}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T = 8'h1 << _GEN_83[s1_update_bits_cfi_idx_bits]; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_1 = _decr_mask_T; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_2 = {1'h0, _decr_mask_T[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_3 = {2'h0, _decr_mask_T[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_4 = {3'h0, _decr_mask_T[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_5 = {4'h0, _decr_mask_T[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_6 = {5'h0, _decr_mask_T[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_7 = {6'h0, _decr_mask_T[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_8 = {7'h0, _decr_mask_T[7]}; // @[OneHot.scala:58:35] wire [7:0] _decr_mask_T_9 = _decr_mask_T_1 | _decr_mask_T_2; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_10 = _decr_mask_T_9 | _decr_mask_T_3; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_11 = _decr_mask_T_10 | _decr_mask_T_4; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_12 = _decr_mask_T_11 | _decr_mask_T_5; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_13 = _decr_mask_T_12 | _decr_mask_T_6; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_14 = _decr_mask_T_13 | _decr_mask_T_7; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_15 = _decr_mask_T_14 | _decr_mask_T_8; // @[util.scala:373:{29,45}] wire [7:0] _decr_mask_T_16 = ~_decr_mask_T_15; // @[util.scala:373:45] wire [7:0] decr_mask = _GEN_82[s1_update_bits_cfi_idx_bits] ? _decr_mask_T_16 : 8'h0; // @[OneHot.scala:58:35] assign s1_update_u_mask_0_0 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T | _GEN_8 : decr_mask[0] & _update_was_taken_T | _GEN_8) : _GEN_8; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_1 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_2 | _GEN_17 : decr_mask[0] & _update_was_taken_T_2 | _GEN_17) : _GEN_17; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_2 = _T_144 ? (_GEN_43 ? _GEN_46 & _update_was_taken_T_4 | _GEN_26 : decr_mask[0] & _update_was_taken_T_4 | _GEN_26) : _GEN_26; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_0_3 = _T_144 ? (_GEN_43 ? _GEN_46 & (&s1_update_bits_cfi_idx_bits) | _GEN_35 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits) | _GEN_35) : _GEN_35; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_0_0 = _T_144 & (_GEN_43 ? _GEN_58 : decr_mask[0] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_1 = _T_144 & (_GEN_43 ? _GEN_59 : decr_mask[0] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_2 = _T_144 & (_GEN_43 ? _GEN_60 : decr_mask[0] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_0_3 = _T_144 & (_GEN_43 ? _GEN_61 : decr_mask[0] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_1_0 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T | _GEN_9 : decr_mask[1] & _update_was_taken_T | _GEN_9) : _GEN_9; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_1 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_2 | _GEN_18 : decr_mask[1] & _update_was_taken_T_2 | _GEN_18) : _GEN_18; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_2 = _T_144 ? (_GEN_43 ? _GEN_48 & _update_was_taken_T_4 | _GEN_27 : decr_mask[1] & _update_was_taken_T_4 | _GEN_27) : _GEN_27; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_1_3 = _T_144 ? (_GEN_43 ? _GEN_48 & (&s1_update_bits_cfi_idx_bits) | _GEN_36 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits) | _GEN_36) : _GEN_36; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_1_0 = _T_144 & (_GEN_43 ? _GEN_62 : decr_mask[1] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_1 = _T_144 & (_GEN_43 ? _GEN_63 : decr_mask[1] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_2 = _T_144 & (_GEN_43 ? _GEN_64 : decr_mask[1] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_1_3 = _T_144 & (_GEN_43 ? _GEN_65 : decr_mask[1] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_2_0 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T | _GEN_10 : decr_mask[2] & _update_was_taken_T | _GEN_10) : _GEN_10; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_1 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_2 | _GEN_19 : decr_mask[2] & _update_was_taken_T_2 | _GEN_19) : _GEN_19; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_2 = _T_144 ? (_GEN_43 ? _GEN_50 & _update_was_taken_T_4 | _GEN_28 : decr_mask[2] & _update_was_taken_T_4 | _GEN_28) : _GEN_28; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_2_3 = _T_144 ? (_GEN_43 ? _GEN_50 & (&s1_update_bits_cfi_idx_bits) | _GEN_37 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits) | _GEN_37) : _GEN_37; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_2_0 = _T_144 & (_GEN_43 ? _GEN_66 : decr_mask[2] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_1 = _T_144 & (_GEN_43 ? _GEN_67 : decr_mask[2] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_2 = _T_144 & (_GEN_43 ? _GEN_68 : decr_mask[2] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_2_3 = _T_144 & (_GEN_43 ? _GEN_69 : decr_mask[2] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_3_0 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T | _GEN_11 : decr_mask[3] & _update_was_taken_T | _GEN_11) : _GEN_11; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_1 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_2 | _GEN_20 : decr_mask[3] & _update_was_taken_T_2 | _GEN_20) : _GEN_20; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_2 = _T_144 ? (_GEN_43 ? _GEN_52 & _update_was_taken_T_4 | _GEN_29 : decr_mask[3] & _update_was_taken_T_4 | _GEN_29) : _GEN_29; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_3_3 = _T_144 ? (_GEN_43 ? _GEN_52 & (&s1_update_bits_cfi_idx_bits) | _GEN_38 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits) | _GEN_38) : _GEN_38; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_3_0 = _T_144 & (_GEN_43 ? _GEN_70 : decr_mask[3] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_1 = _T_144 & (_GEN_43 ? _GEN_71 : decr_mask[3] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_2 = _T_144 & (_GEN_43 ? _GEN_72 : decr_mask[3] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_3_3 = _T_144 & (_GEN_43 ? _GEN_73 : decr_mask[3] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_4_0 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T | _GEN_12 : decr_mask[4] & _update_was_taken_T | _GEN_12) : _GEN_12; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_1 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_2 | _GEN_21 : decr_mask[4] & _update_was_taken_T_2 | _GEN_21) : _GEN_21; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_2 = _T_144 ? (_GEN_43 ? _GEN_54 & _update_was_taken_T_4 | _GEN_30 : decr_mask[4] & _update_was_taken_T_4 | _GEN_30) : _GEN_30; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_4_3 = _T_144 ? (_GEN_43 ? _GEN_54 & (&s1_update_bits_cfi_idx_bits) | _GEN_39 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits) | _GEN_39) : _GEN_39; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_4_0 = _T_144 & (_GEN_43 ? _GEN_74 : decr_mask[4] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_1 = _T_144 & (_GEN_43 ? _GEN_75 : decr_mask[4] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_2 = _T_144 & (_GEN_43 ? _GEN_76 : decr_mask[4] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_4_3 = _T_144 & (_GEN_43 ? _GEN_77 : decr_mask[4] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_mask_5_0 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T | _GEN_13 : decr_mask[5] & _update_was_taken_T | _GEN_13) : _GEN_13; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_1 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_2 | _GEN_22 : decr_mask[5] & _update_was_taken_T_2 | _GEN_22) : _GEN_22; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_2 = _T_144 ? (_GEN_43 ? _GEN_56 & _update_was_taken_T_4 | _GEN_31 : decr_mask[5] & _update_was_taken_T_4 | _GEN_31) : _GEN_31; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_mask_5_3 = _T_144 ? (_GEN_43 ? _GEN_56 & (&s1_update_bits_cfi_idx_bits) | _GEN_40 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits) | _GEN_40) : _GEN_40; // @[tage.scala:240:33, :241:35, :297:58, :299:92, :300:47, :303:37, :317:{25,60,95,128}, :320:27, :321:43, :325:44, :330:26, :333:{24,29}, :334:36] assign s1_update_u_5_0 = _T_144 & (_GEN_43 ? _GEN_78 : decr_mask[5] & _update_was_taken_T) ? 2'h0 : new_u; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_1 = _T_144 & (_GEN_43 ? _GEN_79 : decr_mask[5] & _update_was_taken_T_2) ? 2'h0 : new_u_1; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_2 = _T_144 & (_GEN_43 ? _GEN_80 : decr_mask[5] & _update_was_taken_T_4) ? 2'h0 : new_u_2; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] assign s1_update_u_5_3 = _T_144 & (_GEN_43 ? _GEN_81 : decr_mask[5] & (&s1_update_bits_cfi_idx_bits)) ? 2'h0 : new_u_3; // @[tage.scala:217:8, :246:31, :297:58, :299:92, :317:{25,60,95,128}, :320:27, :322:43, :326:44, :330:26, :333:{24,29}, :335:36] reg tt_0_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_0_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_0_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_0_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_0_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_0_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_0_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_0_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_0_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_1_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_1_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_1_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_1_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_1_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_1_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_1_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_1_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_1_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_2_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_2_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_2_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_2_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_2_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_2_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_2_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_2_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_2_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_3_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_3_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_3_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_3_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_3_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_3_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_3_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_3_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_3_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_4_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_4_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_4_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_4_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_4_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_4_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_4_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_4_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_4_1_io_update_hist_REG; // @[tage.scala:354:41] reg tt_5_1_io_update_mask_0_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_0_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_0_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_0_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_0_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_0_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_1_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_1_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_1_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_1_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_1_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_1_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_2_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_2_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_2_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_2_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_2_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_2_REG; // @[tage.scala:351:47] reg tt_5_1_io_update_mask_3_REG; // @[tage.scala:345:48] reg tt_5_1_io_update_taken_3_REG; // @[tage.scala:346:48] reg tt_5_1_io_update_alloc_3_REG; // @[tage.scala:347:48] reg [2:0] tt_5_1_io_update_old_ctr_3_REG; // @[tage.scala:348:48] reg tt_5_1_io_update_u_mask_3_REG; // @[tage.scala:350:47] reg [1:0] tt_5_1_io_update_u_3_REG; // @[tage.scala:351:47] reg [39:0] tt_5_1_io_update_pc_REG; // @[tage.scala:353:41] reg [63:0] tt_5_1_io_update_hist_REG; // @[tage.scala:354:41] wire [7:0] io_f3_meta_lo = {_io_f3_meta_T_1, _io_f3_meta_T}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi = {_io_f3_meta_T_3, _io_f3_meta_T_2}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_4 = {io_f3_meta_hi, io_f3_meta_lo}; // @[tage.scala:359:25] wire [11:0] _io_f3_meta_T_5 = {io_f3_meta_hi_1, io_f3_meta_lo_1}; // @[tage.scala:359:25] wire [7:0] _io_f3_meta_T_6 = {io_f3_meta_hi_2, io_f3_meta_lo_2}; // @[tage.scala:359:25] wire [3:0] _io_f3_meta_T_7 = {io_f3_meta_hi_3, io_f3_meta_lo_3}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_lo_4 = {_io_f3_meta_T_9, _io_f3_meta_T_8}; // @[tage.scala:359:25] wire [7:0] io_f3_meta_hi_4 = {_io_f3_meta_T_11, _io_f3_meta_T_10}; // @[tage.scala:359:25] wire [15:0] _io_f3_meta_T_12 = {io_f3_meta_hi_4, io_f3_meta_lo_4}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_lo_5 = {_io_f3_meta_T_5, _io_f3_meta_T_4}; // @[tage.scala:359:25] wire [19:0] io_f3_meta_hi_hi = {_io_f3_meta_T_12, _io_f3_meta_T_7}; // @[tage.scala:359:25] wire [27:0] io_f3_meta_hi_5 = {io_f3_meta_hi_hi, _io_f3_meta_T_6}; // @[tage.scala:359:25] wire [55:0] _io_f3_meta_T_13 = {io_f3_meta_hi_5, io_f3_meta_lo_5}; // @[tage.scala:359:25] assign io_f3_meta_0 = {64'h0, _io_f3_meta_T_13}; // @[tage.scala:198:7, :359:{14,25}] always @(posedge clock) begin // @[tage.scala:198:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[tage.scala:198:7] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[tage.scala:198:7] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[tage.scala:198:7] s1_update_valid <= io_update_valid_0; // @[tage.scala:198:7] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[tage.scala:198:7] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[tage.scala:198:7] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[tage.scala:198:7] s1_update_bits_pc <= io_update_bits_pc_0; // @[tage.scala:198:7] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[tage.scala:198:7] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[tage.scala:198:7] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[tage.scala:198:7] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[tage.scala:198:7] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[tage.scala:198:7] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[tage.scala:198:7] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[tage.scala:198:7] s1_update_bits_target <= io_update_bits_target_0; // @[tage.scala:198:7] s1_update_bits_meta <= io_update_bits_meta_0; // @[tage.scala:198:7] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[tage.scala:198:7] t_io_f1_req_valid_REG <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_1 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_1 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_2 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_2 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_3 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_3 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_4 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_4 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] t_io_f1_req_valid_REG_5 <= io_f0_valid_0; // @[tage.scala:198:7, :225:35] t_io_f1_req_pc_REG_5 <= io_f0_pc_0; // @[tage.scala:198:7, :226:35] tt_0_1_io_update_mask_0_REG <= s1_update_mask_0_0; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_0_REG <= s1_update_taken_0_0; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_0_REG <= s1_update_alloc_0_0; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_0_0; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_0_REG <= s1_update_u_mask_0_0; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_0_REG <= s1_update_u_0_0; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_1_REG <= s1_update_mask_0_1; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_1_REG <= s1_update_taken_0_1; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_1_REG <= s1_update_alloc_0_1; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_0_1; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_1_REG <= s1_update_u_mask_0_1; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_1_REG <= s1_update_u_0_1; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_2_REG <= s1_update_mask_0_2; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_2_REG <= s1_update_taken_0_2; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_2_REG <= s1_update_alloc_0_2; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_0_2; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_2_REG <= s1_update_u_mask_0_2; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_2_REG <= s1_update_u_0_2; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_mask_3_REG <= s1_update_mask_0_3; // @[tage.scala:240:33, :345:48] tt_0_1_io_update_taken_3_REG <= s1_update_taken_0_3; // @[tage.scala:243:31, :346:48] tt_0_1_io_update_alloc_3_REG <= s1_update_alloc_0_3; // @[tage.scala:245:31, :347:48] tt_0_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_0_3; // @[tage.scala:244:31, :348:48] tt_0_1_io_update_u_mask_3_REG <= s1_update_u_mask_0_3; // @[tage.scala:241:35, :350:47] tt_0_1_io_update_u_3_REG <= s1_update_u_0_3; // @[tage.scala:246:31, :351:47] tt_0_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_0_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_1_1_io_update_mask_0_REG <= s1_update_mask_1_0; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_0_REG <= s1_update_taken_1_0; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_0_REG <= s1_update_alloc_1_0; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_1_0; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_0_REG <= s1_update_u_mask_1_0; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_0_REG <= s1_update_u_1_0; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_1_REG <= s1_update_mask_1_1; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_1_REG <= s1_update_taken_1_1; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_1_REG <= s1_update_alloc_1_1; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_1_1; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_1_REG <= s1_update_u_mask_1_1; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_1_REG <= s1_update_u_1_1; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_2_REG <= s1_update_mask_1_2; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_2_REG <= s1_update_taken_1_2; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_2_REG <= s1_update_alloc_1_2; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_1_2; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_2_REG <= s1_update_u_mask_1_2; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_2_REG <= s1_update_u_1_2; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_mask_3_REG <= s1_update_mask_1_3; // @[tage.scala:240:33, :345:48] tt_1_1_io_update_taken_3_REG <= s1_update_taken_1_3; // @[tage.scala:243:31, :346:48] tt_1_1_io_update_alloc_3_REG <= s1_update_alloc_1_3; // @[tage.scala:245:31, :347:48] tt_1_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_1_3; // @[tage.scala:244:31, :348:48] tt_1_1_io_update_u_mask_3_REG <= s1_update_u_mask_1_3; // @[tage.scala:241:35, :350:47] tt_1_1_io_update_u_3_REG <= s1_update_u_1_3; // @[tage.scala:246:31, :351:47] tt_1_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_1_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_2_1_io_update_mask_0_REG <= s1_update_mask_2_0; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_0_REG <= s1_update_taken_2_0; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_0_REG <= s1_update_alloc_2_0; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_2_0; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_0_REG <= s1_update_u_mask_2_0; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_0_REG <= s1_update_u_2_0; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_1_REG <= s1_update_mask_2_1; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_1_REG <= s1_update_taken_2_1; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_1_REG <= s1_update_alloc_2_1; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_2_1; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_1_REG <= s1_update_u_mask_2_1; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_1_REG <= s1_update_u_2_1; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_2_REG <= s1_update_mask_2_2; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_2_REG <= s1_update_taken_2_2; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_2_REG <= s1_update_alloc_2_2; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_2_2; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_2_REG <= s1_update_u_mask_2_2; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_2_REG <= s1_update_u_2_2; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_mask_3_REG <= s1_update_mask_2_3; // @[tage.scala:240:33, :345:48] tt_2_1_io_update_taken_3_REG <= s1_update_taken_2_3; // @[tage.scala:243:31, :346:48] tt_2_1_io_update_alloc_3_REG <= s1_update_alloc_2_3; // @[tage.scala:245:31, :347:48] tt_2_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_2_3; // @[tage.scala:244:31, :348:48] tt_2_1_io_update_u_mask_3_REG <= s1_update_u_mask_2_3; // @[tage.scala:241:35, :350:47] tt_2_1_io_update_u_3_REG <= s1_update_u_2_3; // @[tage.scala:246:31, :351:47] tt_2_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_2_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_3_1_io_update_mask_0_REG <= s1_update_mask_3_0; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_0_REG <= s1_update_taken_3_0; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_0_REG <= s1_update_alloc_3_0; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_3_0; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_0_REG <= s1_update_u_mask_3_0; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_0_REG <= s1_update_u_3_0; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_1_REG <= s1_update_mask_3_1; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_1_REG <= s1_update_taken_3_1; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_1_REG <= s1_update_alloc_3_1; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_3_1; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_1_REG <= s1_update_u_mask_3_1; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_1_REG <= s1_update_u_3_1; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_2_REG <= s1_update_mask_3_2; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_2_REG <= s1_update_taken_3_2; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_2_REG <= s1_update_alloc_3_2; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_3_2; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_2_REG <= s1_update_u_mask_3_2; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_2_REG <= s1_update_u_3_2; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_mask_3_REG <= s1_update_mask_3_3; // @[tage.scala:240:33, :345:48] tt_3_1_io_update_taken_3_REG <= s1_update_taken_3_3; // @[tage.scala:243:31, :346:48] tt_3_1_io_update_alloc_3_REG <= s1_update_alloc_3_3; // @[tage.scala:245:31, :347:48] tt_3_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_3_3; // @[tage.scala:244:31, :348:48] tt_3_1_io_update_u_mask_3_REG <= s1_update_u_mask_3_3; // @[tage.scala:241:35, :350:47] tt_3_1_io_update_u_3_REG <= s1_update_u_3_3; // @[tage.scala:246:31, :351:47] tt_3_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_3_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_4_1_io_update_mask_0_REG <= s1_update_mask_4_0; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_0_REG <= s1_update_taken_4_0; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_0_REG <= s1_update_alloc_4_0; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_4_0; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_0_REG <= s1_update_u_mask_4_0; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_0_REG <= s1_update_u_4_0; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_1_REG <= s1_update_mask_4_1; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_1_REG <= s1_update_taken_4_1; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_1_REG <= s1_update_alloc_4_1; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_4_1; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_1_REG <= s1_update_u_mask_4_1; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_1_REG <= s1_update_u_4_1; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_2_REG <= s1_update_mask_4_2; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_2_REG <= s1_update_taken_4_2; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_2_REG <= s1_update_alloc_4_2; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_4_2; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_2_REG <= s1_update_u_mask_4_2; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_2_REG <= s1_update_u_4_2; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_mask_3_REG <= s1_update_mask_4_3; // @[tage.scala:240:33, :345:48] tt_4_1_io_update_taken_3_REG <= s1_update_taken_4_3; // @[tage.scala:243:31, :346:48] tt_4_1_io_update_alloc_3_REG <= s1_update_alloc_4_3; // @[tage.scala:245:31, :347:48] tt_4_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_4_3; // @[tage.scala:244:31, :348:48] tt_4_1_io_update_u_mask_3_REG <= s1_update_u_mask_4_3; // @[tage.scala:241:35, :350:47] tt_4_1_io_update_u_3_REG <= s1_update_u_4_3; // @[tage.scala:246:31, :351:47] tt_4_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_4_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] tt_5_1_io_update_mask_0_REG <= s1_update_mask_5_0; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_0_REG <= s1_update_taken_5_0; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_0_REG <= s1_update_alloc_5_0; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_0_REG <= s1_update_old_ctr_5_0; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_0_REG <= s1_update_u_mask_5_0; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_0_REG <= s1_update_u_5_0; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_1_REG <= s1_update_mask_5_1; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_1_REG <= s1_update_taken_5_1; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_1_REG <= s1_update_alloc_5_1; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_1_REG <= s1_update_old_ctr_5_1; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_1_REG <= s1_update_u_mask_5_1; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_1_REG <= s1_update_u_5_1; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_2_REG <= s1_update_mask_5_2; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_2_REG <= s1_update_taken_5_2; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_2_REG <= s1_update_alloc_5_2; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_2_REG <= s1_update_old_ctr_5_2; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_2_REG <= s1_update_u_mask_5_2; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_2_REG <= s1_update_u_5_2; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_mask_3_REG <= s1_update_mask_5_3; // @[tage.scala:240:33, :345:48] tt_5_1_io_update_taken_3_REG <= s1_update_taken_5_3; // @[tage.scala:243:31, :346:48] tt_5_1_io_update_alloc_3_REG <= s1_update_alloc_5_3; // @[tage.scala:245:31, :347:48] tt_5_1_io_update_old_ctr_3_REG <= s1_update_old_ctr_5_3; // @[tage.scala:244:31, :348:48] tt_5_1_io_update_u_mask_3_REG <= s1_update_u_mask_5_3; // @[tage.scala:241:35, :350:47] tt_5_1_io_update_u_3_REG <= s1_update_u_5_3; // @[tage.scala:246:31, :351:47] tt_5_1_io_update_pc_REG <= s1_update_bits_pc; // @[tage.scala:353:41] tt_5_1_io_update_hist_REG <= s1_update_bits_ghist; // @[tage.scala:354:41] always @(posedge) TageTable_18 tt_0_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_0_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_0_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_0_0_bits_u), .io_f3_resp_1_valid (f3_resps_0_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_0_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_0_1_bits_u), .io_f3_resp_2_valid (f3_resps_0_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_0_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_0_2_bits_u), .io_f3_resp_3_valid (f3_resps_0_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_0_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_0_3_bits_u), .io_update_mask_0 (tt_0_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_0_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_0_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_0_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_0_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_0_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_0_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_0_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_0_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_0_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_0_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_0_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_0_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_0_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_0_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_0_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_0_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_0_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_0_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_0_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_0_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_0_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_0_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_0_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_0_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_0_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_19 tt_1_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_1), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_1), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_1_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_1_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_1_0_bits_u), .io_f3_resp_1_valid (f3_resps_1_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_1_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_1_1_bits_u), .io_f3_resp_2_valid (f3_resps_1_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_1_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_1_2_bits_u), .io_f3_resp_3_valid (f3_resps_1_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_1_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_1_3_bits_u), .io_update_mask_0 (tt_1_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_1_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_1_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_1_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_1_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_1_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_1_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_1_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_1_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_1_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_1_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_1_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_1_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_1_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_1_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_1_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_1_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_1_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_1_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_1_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_1_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_1_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_1_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_1_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_1_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_1_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_20 tt_2_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_2), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_2), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_2_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_2_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_2_0_bits_u), .io_f3_resp_1_valid (f3_resps_2_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_2_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_2_1_bits_u), .io_f3_resp_2_valid (f3_resps_2_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_2_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_2_2_bits_u), .io_f3_resp_3_valid (f3_resps_2_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_2_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_2_3_bits_u), .io_update_mask_0 (tt_2_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_2_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_2_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_2_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_2_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_2_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_2_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_2_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_2_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_2_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_2_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_2_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_2_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_2_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_2_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_2_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_2_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_2_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_2_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_2_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_2_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_2_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_2_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_2_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_2_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_2_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_21 tt_3_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_3), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_3), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_3_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_3_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_3_0_bits_u), .io_f3_resp_1_valid (f3_resps_3_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_3_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_3_1_bits_u), .io_f3_resp_2_valid (f3_resps_3_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_3_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_3_2_bits_u), .io_f3_resp_3_valid (f3_resps_3_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_3_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_3_3_bits_u), .io_update_mask_0 (tt_3_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_3_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_3_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_3_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_3_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_3_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_3_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_3_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_3_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_3_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_3_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_3_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_3_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_3_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_3_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_3_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_3_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_3_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_3_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_3_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_3_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_3_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_3_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_3_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_3_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_3_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_22 tt_4_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_4), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_4), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_4_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_4_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_4_0_bits_u), .io_f3_resp_1_valid (f3_resps_4_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_4_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_4_1_bits_u), .io_f3_resp_2_valid (f3_resps_4_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_4_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_4_2_bits_u), .io_f3_resp_3_valid (f3_resps_4_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_4_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_4_3_bits_u), .io_update_mask_0 (tt_4_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_4_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_4_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_4_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_4_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_4_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_4_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_4_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_4_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_4_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_4_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_4_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_4_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_4_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_4_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_4_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_4_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_4_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_4_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_4_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_4_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_4_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_4_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_4_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_4_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_4_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] TageTable_23 tt_5_1 ( // @[tage.scala:224:21] .clock (clock), .reset (reset), .io_f1_req_valid (t_io_f1_req_valid_REG_5), // @[tage.scala:225:35] .io_f1_req_pc (t_io_f1_req_pc_REG_5), // @[tage.scala:226:35] .io_f1_req_ghist (io_f1_ghist_0), // @[tage.scala:198:7] .io_f3_resp_0_valid (f3_resps_5_0_valid), .io_f3_resp_0_bits_ctr (f3_resps_5_0_bits_ctr), .io_f3_resp_0_bits_u (f3_resps_5_0_bits_u), .io_f3_resp_1_valid (f3_resps_5_1_valid), .io_f3_resp_1_bits_ctr (f3_resps_5_1_bits_ctr), .io_f3_resp_1_bits_u (f3_resps_5_1_bits_u), .io_f3_resp_2_valid (f3_resps_5_2_valid), .io_f3_resp_2_bits_ctr (f3_resps_5_2_bits_ctr), .io_f3_resp_2_bits_u (f3_resps_5_2_bits_u), .io_f3_resp_3_valid (f3_resps_5_3_valid), .io_f3_resp_3_bits_ctr (f3_resps_5_3_bits_ctr), .io_f3_resp_3_bits_u (f3_resps_5_3_bits_u), .io_update_mask_0 (tt_5_1_io_update_mask_0_REG), // @[tage.scala:345:48] .io_update_mask_1 (tt_5_1_io_update_mask_1_REG), // @[tage.scala:345:48] .io_update_mask_2 (tt_5_1_io_update_mask_2_REG), // @[tage.scala:345:48] .io_update_mask_3 (tt_5_1_io_update_mask_3_REG), // @[tage.scala:345:48] .io_update_taken_0 (tt_5_1_io_update_taken_0_REG), // @[tage.scala:346:48] .io_update_taken_1 (tt_5_1_io_update_taken_1_REG), // @[tage.scala:346:48] .io_update_taken_2 (tt_5_1_io_update_taken_2_REG), // @[tage.scala:346:48] .io_update_taken_3 (tt_5_1_io_update_taken_3_REG), // @[tage.scala:346:48] .io_update_alloc_0 (tt_5_1_io_update_alloc_0_REG), // @[tage.scala:347:48] .io_update_alloc_1 (tt_5_1_io_update_alloc_1_REG), // @[tage.scala:347:48] .io_update_alloc_2 (tt_5_1_io_update_alloc_2_REG), // @[tage.scala:347:48] .io_update_alloc_3 (tt_5_1_io_update_alloc_3_REG), // @[tage.scala:347:48] .io_update_old_ctr_0 (tt_5_1_io_update_old_ctr_0_REG), // @[tage.scala:348:48] .io_update_old_ctr_1 (tt_5_1_io_update_old_ctr_1_REG), // @[tage.scala:348:48] .io_update_old_ctr_2 (tt_5_1_io_update_old_ctr_2_REG), // @[tage.scala:348:48] .io_update_old_ctr_3 (tt_5_1_io_update_old_ctr_3_REG), // @[tage.scala:348:48] .io_update_pc (tt_5_1_io_update_pc_REG), // @[tage.scala:353:41] .io_update_hist (tt_5_1_io_update_hist_REG), // @[tage.scala:354:41] .io_update_u_mask_0 (tt_5_1_io_update_u_mask_0_REG), // @[tage.scala:350:47] .io_update_u_mask_1 (tt_5_1_io_update_u_mask_1_REG), // @[tage.scala:350:47] .io_update_u_mask_2 (tt_5_1_io_update_u_mask_2_REG), // @[tage.scala:350:47] .io_update_u_mask_3 (tt_5_1_io_update_u_mask_3_REG), // @[tage.scala:350:47] .io_update_u_0 (tt_5_1_io_update_u_0_REG), // @[tage.scala:351:47] .io_update_u_1 (tt_5_1_io_update_u_1_REG), // @[tage.scala:351:47] .io_update_u_2 (tt_5_1_io_update_u_2_REG), // @[tage.scala:351:47] .io_update_u_3 (tt_5_1_io_update_u_3_REG) // @[tage.scala:351:47] ); // @[tage.scala:224:21] MaxPeriodFibonacciLFSR_21 alloc_lfsr_prng ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_io_out_0), .io_out_1 (_alloc_lfsr_prng_io_out_1), .io_out_2 (_alloc_lfsr_prng_io_out_2), .io_out_3 (_alloc_lfsr_prng_io_out_3), .io_out_4 (_alloc_lfsr_prng_io_out_4), .io_out_5 (_alloc_lfsr_prng_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_22 alloc_lfsr_prng_1 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_1_io_out_0), .io_out_1 (_alloc_lfsr_prng_1_io_out_1), .io_out_2 (_alloc_lfsr_prng_1_io_out_2), .io_out_3 (_alloc_lfsr_prng_1_io_out_3), .io_out_4 (_alloc_lfsr_prng_1_io_out_4), .io_out_5 (_alloc_lfsr_prng_1_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_23 alloc_lfsr_prng_2 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_2_io_out_0), .io_out_1 (_alloc_lfsr_prng_2_io_out_1), .io_out_2 (_alloc_lfsr_prng_2_io_out_2), .io_out_3 (_alloc_lfsr_prng_2_io_out_3), .io_out_4 (_alloc_lfsr_prng_2_io_out_4), .io_out_5 (_alloc_lfsr_prng_2_io_out_5) ); // @[PRNG.scala:91:22] MaxPeriodFibonacciLFSR_24 alloc_lfsr_prng_3 ( // @[PRNG.scala:91:22] .clock (clock), .reset (reset), .io_out_0 (_alloc_lfsr_prng_3_io_out_0), .io_out_1 (_alloc_lfsr_prng_3_io_out_1), .io_out_2 (_alloc_lfsr_prng_3_io_out_2), .io_out_3 (_alloc_lfsr_prng_3_io_out_3), .io_out_4 (_alloc_lfsr_prng_3_io_out_4), .io_out_5 (_alloc_lfsr_prng_3_io_out_5) ); // @[PRNG.scala:91:22] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[tage.scala:198:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[tage.scala:198:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[tage.scala:198:7] assign io_f3_meta = io_f3_meta_0; // @[tage.scala:198:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache : input clock : Clock input reset : Reset output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} inst ctrls of InclusiveCacheControl connect ctrls.clock, clock connect ctrls.reset, reset wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_37 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler connect inclusive_cache_bank_sched.clock, clock connect inclusive_cache_bank_sched.reset, reset connect inclusive_cache_bank_sched.io.in, nodeIn connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready connect inclusive_cache_bank_sched.io.out.d, nodeOut.d connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready connect inclusive_cache_bank_sched.io.out.b, nodeOut.b connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready invalidate inclusive_cache_bank_sched.io.ways[0] invalidate inclusive_cache_bank_sched.io.ways[1] invalidate inclusive_cache_bank_sched.io.ways[2] invalidate inclusive_cache_bank_sched.io.ways[3] invalidate inclusive_cache_bank_sched.io.ways[4] invalidate inclusive_cache_bank_sched.io.ways[5] invalidate inclusive_cache_bank_sched.io.ways[6] invalidate inclusive_cache_bank_sched.io.ways[7] invalidate inclusive_cache_bank_sched.io.ways[8] invalidate inclusive_cache_bank_sched.io.divs[0] invalidate inclusive_cache_bank_sched.io.divs[1] invalidate inclusive_cache_bank_sched.io.divs[2] invalidate inclusive_cache_bank_sched.io.divs[3] invalidate inclusive_cache_bank_sched.io.divs[4] invalidate inclusive_cache_bank_sched.io.divs[5] invalidate inclusive_cache_bank_sched.io.divs[6] invalidate inclusive_cache_bank_sched.io.divs[7] invalidate inclusive_cache_bank_sched.io.divs[8] connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T) node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2) node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0)) connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T) node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2) node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0)) connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T) node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2) node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0))) node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0)) connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T connect ctrls.io.flush_req.ready, UInt<1>(0h0) connect ctrls.io.flush_resp, UInt<1>(0h0) connect ctrls.io.flush_match, UInt<1>(0h0) node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000)) node _contained_T_1 = cvt(_contained_T) node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h10000000))) node _contained_T_3 = asSInt(_contained_T_2) node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0))) node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000)) node _contained_T_6 = cvt(_contained_T_5) node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h10000))) node _contained_T_8 = asSInt(_contained_T_7) node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0))) node contained = or(_contained_T_4, _contained_T_9) when contained : connect ctrls.io.flush_match, UInt<1>(0h1) node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid) connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits node _T = and(contained, inclusive_cache_bank_sched.io.req.ready) when _T : connect ctrls.io.flush_req.ready, UInt<1>(0h1) when inclusive_cache_bank_sched.io.resp.valid : connect ctrls.io.flush_resp, UInt<1>(0h1) connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1)

module InclusiveCache( // @[InclusiveCache.scala:108:9] input clock, // @[InclusiveCache.scala:108:9] input reset, // @[InclusiveCache.scala:108:9] output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_a_bits_address; // @[InclusiveCache.scala:137:29] wire [31:0] _inclusive_cache_bank_sched_io_out_c_bits_address; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29] wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29] wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43] wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43] wire auto_ctrls_ctrl_in_a_valid_0 = auto_ctrls_ctrl_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_opcode_0 = auto_ctrls_ctrl_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_a_bits_param_0 = auto_ctrls_ctrl_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_a_bits_size_0 = auto_ctrls_ctrl_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [12:0] auto_ctrls_ctrl_in_a_bits_source_0 = auto_ctrls_ctrl_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [25:0] auto_ctrls_ctrl_in_a_bits_address_0 = auto_ctrls_ctrl_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [7:0] auto_ctrls_ctrl_in_a_bits_mask_0 = auto_ctrls_ctrl_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_a_bits_data_0 = auto_ctrls_ctrl_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_a_bits_corrupt_0 = auto_ctrls_ctrl_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_ready_0 = auto_ctrls_ctrl_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[InclusiveCache.scala:108:9] wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[InclusiveCache.scala:108:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[InclusiveCache.scala:108:9] wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[InclusiveCache.scala:108:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[InclusiveCache.scala:108:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[InclusiveCache.scala:108:9] wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[InclusiveCache.scala:108:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[InclusiveCache.scala:108:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[InclusiveCache.scala:108:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[InclusiveCache.scala:108:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[InclusiveCache.scala:108:9] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [63:0] auto_out_b_bits_data = 64'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [63:0] nodeOut_b_bits_data = 64'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [7:0] auto_out_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [7:0] nodeOut_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] auto_out_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [31:0] nodeOut_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [3:0] auto_out_b_bits_source = 4'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [3:0] nodeOut_b_bits_source = 4'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] auto_out_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire [2:0] nodeOut_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29] wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_b_ready = 1'h1; // @[Nodes.scala:27:25] wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_b_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_a_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeIn_b_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire nodeOut_c_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25] wire [127:0] auto_in_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [127:0] nodeIn_b_bits_data = 128'h0; // @[Nodes.scala:27:25] wire [15:0] auto_in_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [15:0] nodeIn_b_bits_mask = 16'hFFFF; // @[Nodes.scala:27:25] wire [7:0] auto_in_b_bits_source = 8'hA0; // @[Nodes.scala:27:25] wire [7:0] nodeIn_b_bits_source = 8'hA0; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25] wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_valid = 1'h0; // @[Nodes.scala:27:25] wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_valid = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_ctrls_ctrl_in_d_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] auto_out_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire [1:0] nodeOut_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[InclusiveCache.scala:108:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[InclusiveCache.scala:108:9] wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[InclusiveCache.scala:108:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [12:0] auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] wire auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] wire auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [1:0] auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] wire [7:0] auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] wire [127:0] auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] wire [7:0] auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] wire [3:0] auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] wire [31:0] auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] wire [63:0] auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] wire auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] wire auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] wire [2:0] auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] wire auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[InclusiveCache.scala:108:9] wire [31:0] _nodeOut_a_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_a_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_a_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeIn_b_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeIn_b_bits_address_mux_matches_T_1 = {1'h0, _nodeIn_b_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeIn_b_bits_address = _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14] wire [31:0] _nodeOut_c_bits_address_mux_matches_T; // @[Parameters.scala:137:31] wire [32:0] _nodeOut_c_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_c_bits_address_mux_matches_T}; // @[Nodes.scala:27:25] assign nodeOut_c_bits_address = _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14] wire [63:0] _contained_T = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_1 = {1'h0, _contained_T}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_2 = _contained_T_1 & 65'h1FFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_3 = _contained_T_2; // @[Parameters.scala:137:46] wire _contained_T_4 = _contained_T_3 == 65'h0; // @[Parameters.scala:137:{46,59}] wire [63:0] _contained_T_5 = {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [64:0] _contained_T_6 = {1'h0, _contained_T_5}; // @[Nodes.scala:27:25] wire [64:0] _contained_T_7 = _contained_T_6 & 65'h1FFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [64:0] _contained_T_8 = _contained_T_7; // @[Parameters.scala:137:46] wire _contained_T_9 = _contained_T_8 == 65'h0; // @[Parameters.scala:137:{46,59}] wire contained = _contained_T_4 | _contained_T_9; // @[Parameters.scala:137:59] wire _inclusive_cache_bank_sched_io_req_valid_T = contained & _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43, :169:67, :172:41] InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready_0), .auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready_0), // @[InclusiveCache.scala:108:9] .auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid_0), .auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size_0), .auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source_0), .auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data_0), .io_flush_match (contained), // @[InclusiveCache.scala:169:67] .io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25] .io_flush_req_valid (_ctrls_io_flush_req_valid), .io_flush_req_bits (_ctrls_io_flush_req_bits), .io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29] ); // @[InclusiveCache.scala:103:43] TLMonitor_37 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), .io_in_b_bits_param (nodeIn_b_bits_param), .io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), .io_in_c_ready (nodeIn_c_ready), .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), .io_in_d_bits_opcode (nodeIn_d_bits_opcode), .io_in_d_bits_param (nodeIn_d_bits_param), .io_in_d_bits_size (nodeIn_d_bits_size), .io_in_d_bits_source (nodeIn_d_bits_source), .io_in_d_bits_sink (nodeIn_d_bits_sink), .io_in_d_bits_denied (nodeIn_d_bits_denied), .io_in_d_bits_data (nodeIn_d_bits_data), .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_out_a_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_out_a_valid (nodeOut_a_valid), .io_out_a_bits_opcode (nodeOut_a_bits_opcode), .io_out_a_bits_param (nodeOut_a_bits_param), .io_out_a_bits_size (nodeOut_a_bits_size), .io_out_a_bits_source (nodeOut_a_bits_source), .io_out_a_bits_address (_inclusive_cache_bank_sched_io_out_a_bits_address), .io_out_a_bits_mask (nodeOut_a_bits_mask), .io_out_a_bits_data (nodeOut_a_bits_data), .io_out_a_bits_corrupt (nodeOut_a_bits_corrupt), .io_out_c_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_out_c_valid (nodeOut_c_valid), .io_out_c_bits_opcode (nodeOut_c_bits_opcode), .io_out_c_bits_param (nodeOut_c_bits_param), .io_out_c_bits_size (nodeOut_c_bits_size), .io_out_c_bits_source (nodeOut_c_bits_source), .io_out_c_bits_address (_inclusive_cache_bank_sched_io_out_c_bits_address), .io_out_c_bits_data (nodeOut_c_bits_data), .io_out_c_bits_corrupt (nodeOut_c_bits_corrupt), .io_out_d_ready (nodeOut_d_ready), .io_out_d_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_out_d_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_out_d_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_out_d_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_out_d_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_out_d_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_out_d_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_out_d_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_out_d_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_out_e_valid (nodeOut_e_valid), .io_out_e_bits_sink (nodeOut_e_bits_sink), .io_req_ready (_inclusive_cache_bank_sched_io_req_ready), .io_req_valid (_inclusive_cache_bank_sched_io_req_valid_T), // @[InclusiveCache.scala:172:41] .io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31] .io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid) ); // @[InclusiveCache.scala:137:29] assign _nodeOut_a_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_a_bits_address_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:248:14] assign _nodeIn_b_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:137:31] assign _nodeIn_b_bits_address_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:248:14] assign _nodeOut_c_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:137:31] assign _nodeOut_c_bits_address_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:248:14] assign auto_ctrls_ctrl_in_a_ready = auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_valid = auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_opcode = auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_size = auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_source = auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_ctrls_ctrl_in_d_bits_data = auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[InclusiveCache.scala:108:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<13>(0h1000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = or(_T_144, _T_149) node _T_151 = and(_T_139, _T_150) node _T_152 = or(UInt<1>(0h0), _T_151) node _T_153 = and(_T_138, _T_152) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_153, UInt<1>(0h1), "") : assert_2 node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = or(_T_165, _T_170) node _T_172 = and(_T_160, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = and(UInt<1>(0h0), _T_173) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_174, UInt<1>(0h1), "") : assert_3 node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(source_ok, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_181 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_181, UInt<1>(0h1), "") : assert_5 node _T_185 = asUInt(reset) node _T_186 = eq(_T_185, UInt<1>(0h0)) when _T_186 : node _T_187 = eq(is_aligned, UInt<1>(0h0)) when _T_187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_188 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_188, UInt<1>(0h1), "") : assert_7 node _T_192 = not(io.in.a.bits.mask) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_193, UInt<1>(0h1), "") : assert_8 node _T_197 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_197, UInt<1>(0h1), "") : assert_9 node _T_201 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_201 : node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_206 = shr(io.in.a.bits.source, 2) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = leq(UInt<1>(0h0), uncommonBits_8) node _T_209 = and(_T_207, _T_208) node _T_210 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_211 = and(_T_209, _T_210) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_212 = shr(io.in.a.bits.source, 2) node _T_213 = eq(_T_212, UInt<1>(0h1)) node _T_214 = leq(UInt<1>(0h0), uncommonBits_9) node _T_215 = and(_T_213, _T_214) node _T_216 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_217 = and(_T_215, _T_216) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_218 = shr(io.in.a.bits.source, 2) node _T_219 = eq(_T_218, UInt<2>(0h2)) node _T_220 = leq(UInt<1>(0h0), uncommonBits_10) node _T_221 = and(_T_219, _T_220) node _T_222 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_223 = and(_T_221, _T_222) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<2>(0h3)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_11) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_231 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_233 = or(_T_205, _T_211) node _T_234 = or(_T_233, _T_217) node _T_235 = or(_T_234, _T_223) node _T_236 = or(_T_235, _T_229) node _T_237 = or(_T_236, _T_230) node _T_238 = or(_T_237, _T_231) node _T_239 = or(_T_238, _T_232) node _T_240 = and(_T_204, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_243 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_244 = cvt(_T_243) node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000))) node _T_246 = asSInt(_T_245) node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0))) node _T_248 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_249 = cvt(_T_248) node _T_250 = and(_T_249, asSInt(UInt<13>(0h1000))) node _T_251 = asSInt(_T_250) node _T_252 = eq(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = or(_T_247, _T_252) node _T_254 = and(_T_242, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = and(_T_241, _T_255) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_256, UInt<1>(0h1), "") : assert_10 node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_262 = and(_T_260, _T_261) node _T_263 = or(UInt<1>(0h0), _T_262) node _T_264 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<13>(0h1000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = or(_T_268, _T_273) node _T_275 = and(_T_263, _T_274) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = and(UInt<1>(0h0), _T_276) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_277, UInt<1>(0h1), "") : assert_11 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(source_ok, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_284 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_284, UInt<1>(0h1), "") : assert_13 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(is_aligned, UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_291 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(_T_291, UInt<1>(0h0)) when _T_294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_291, UInt<1>(0h1), "") : assert_15 node _T_295 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_295, UInt<1>(0h1), "") : assert_16 node _T_299 = not(io.in.a.bits.mask) node _T_300 = eq(_T_299, UInt<1>(0h0)) node _T_301 = asUInt(reset) node _T_302 = eq(_T_301, UInt<1>(0h0)) when _T_302 : node _T_303 = eq(_T_300, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_300, UInt<1>(0h1), "") : assert_17 node _T_304 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_T_304, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_304, UInt<1>(0h1), "") : assert_18 node _T_308 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_308 : node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<1>(0h0)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_12) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h1)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_13) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<2>(0h2)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_14) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h3)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_15) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_339 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_340 = or(_T_312, _T_318) node _T_341 = or(_T_340, _T_324) node _T_342 = or(_T_341, _T_330) node _T_343 = or(_T_342, _T_336) node _T_344 = or(_T_343, _T_337) node _T_345 = or(_T_344, _T_338) node _T_346 = or(_T_345, _T_339) node _T_347 = and(_T_311, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = asUInt(reset) node _T_350 = eq(_T_349, UInt<1>(0h0)) when _T_350 : node _T_351 = eq(_T_348, UInt<1>(0h0)) when _T_351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_348, UInt<1>(0h1), "") : assert_19 node _T_352 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_353 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_354 = and(_T_352, _T_353) node _T_355 = or(UInt<1>(0h0), _T_354) node _T_356 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_357 = cvt(_T_356) node _T_358 = and(_T_357, asSInt(UInt<13>(0h1000))) node _T_359 = asSInt(_T_358) node _T_360 = eq(_T_359, asSInt(UInt<1>(0h0))) node _T_361 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_362 = cvt(_T_361) node _T_363 = and(_T_362, asSInt(UInt<13>(0h1000))) node _T_364 = asSInt(_T_363) node _T_365 = eq(_T_364, asSInt(UInt<1>(0h0))) node _T_366 = or(_T_360, _T_365) node _T_367 = and(_T_355, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(source_ok, UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_395 = shr(io.in.a.bits.source, 2) node _T_396 = eq(_T_395, UInt<1>(0h0)) node _T_397 = leq(UInt<1>(0h0), uncommonBits_16) node _T_398 = and(_T_396, _T_397) node _T_399 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_400 = and(_T_398, _T_399) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_401 = shr(io.in.a.bits.source, 2) node _T_402 = eq(_T_401, UInt<1>(0h1)) node _T_403 = leq(UInt<1>(0h0), uncommonBits_17) node _T_404 = and(_T_402, _T_403) node _T_405 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_406 = and(_T_404, _T_405) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_407 = shr(io.in.a.bits.source, 2) node _T_408 = eq(_T_407, UInt<2>(0h2)) node _T_409 = leq(UInt<1>(0h0), uncommonBits_18) node _T_410 = and(_T_408, _T_409) node _T_411 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_413 = shr(io.in.a.bits.source, 2) node _T_414 = eq(_T_413, UInt<2>(0h3)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_19) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_418 = and(_T_416, _T_417) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_422 = or(_T_394, _T_400) node _T_423 = or(_T_422, _T_406) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_424, _T_418) node _T_426 = or(_T_425, _T_419) node _T_427 = or(_T_426, _T_420) node _T_428 = or(_T_427, _T_421) node _T_429 = and(_T_393, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_433 = and(_T_431, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<13>(0h1000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = or(_T_439, _T_444) node _T_446 = and(_T_434, _T_445) node _T_447 = or(UInt<1>(0h0), _T_446) node _T_448 = and(_T_430, _T_447) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_448, UInt<1>(0h1), "") : assert_26 node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(source_ok, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(is_aligned, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_458 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_458, UInt<1>(0h1), "") : assert_29 node _T_462 = eq(io.in.a.bits.mask, mask) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_462, UInt<1>(0h1), "") : assert_30 node _T_466 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_466 : node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_471 = shr(io.in.a.bits.source, 2) node _T_472 = eq(_T_471, UInt<1>(0h0)) node _T_473 = leq(UInt<1>(0h0), uncommonBits_20) node _T_474 = and(_T_472, _T_473) node _T_475 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_476 = and(_T_474, _T_475) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_477 = shr(io.in.a.bits.source, 2) node _T_478 = eq(_T_477, UInt<1>(0h1)) node _T_479 = leq(UInt<1>(0h0), uncommonBits_21) node _T_480 = and(_T_478, _T_479) node _T_481 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_482 = and(_T_480, _T_481) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_483 = shr(io.in.a.bits.source, 2) node _T_484 = eq(_T_483, UInt<2>(0h2)) node _T_485 = leq(UInt<1>(0h0), uncommonBits_22) node _T_486 = and(_T_484, _T_485) node _T_487 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_488 = and(_T_486, _T_487) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_489 = shr(io.in.a.bits.source, 2) node _T_490 = eq(_T_489, UInt<2>(0h3)) node _T_491 = leq(UInt<1>(0h0), uncommonBits_23) node _T_492 = and(_T_490, _T_491) node _T_493 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_497 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_498 = or(_T_470, _T_476) node _T_499 = or(_T_498, _T_482) node _T_500 = or(_T_499, _T_488) node _T_501 = or(_T_500, _T_494) node _T_502 = or(_T_501, _T_495) node _T_503 = or(_T_502, _T_496) node _T_504 = or(_T_503, _T_497) node _T_505 = and(_T_469, _T_504) node _T_506 = or(UInt<1>(0h0), _T_505) node _T_507 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_508 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_509 = and(_T_507, _T_508) node _T_510 = or(UInt<1>(0h0), _T_509) node _T_511 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<13>(0h1000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = or(_T_515, _T_520) node _T_522 = and(_T_510, _T_521) node _T_523 = or(UInt<1>(0h0), _T_522) node _T_524 = and(_T_506, _T_523) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_524, UInt<1>(0h1), "") : assert_31 node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(source_ok, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(is_aligned, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_534 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_534, UInt<1>(0h1), "") : assert_34 node _T_538 = not(mask) node _T_539 = and(io.in.a.bits.mask, _T_538) node _T_540 = eq(_T_539, UInt<1>(0h0)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_540, UInt<1>(0h1), "") : assert_35 node _T_544 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_544 : node _T_545 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_546 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_547 = and(_T_545, _T_546) node _T_548 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_549 = shr(io.in.a.bits.source, 2) node _T_550 = eq(_T_549, UInt<1>(0h0)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_24) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_554 = and(_T_552, _T_553) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_555 = shr(io.in.a.bits.source, 2) node _T_556 = eq(_T_555, UInt<1>(0h1)) node _T_557 = leq(UInt<1>(0h0), uncommonBits_25) node _T_558 = and(_T_556, _T_557) node _T_559 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_560 = and(_T_558, _T_559) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_561 = shr(io.in.a.bits.source, 2) node _T_562 = eq(_T_561, UInt<2>(0h2)) node _T_563 = leq(UInt<1>(0h0), uncommonBits_26) node _T_564 = and(_T_562, _T_563) node _T_565 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_566 = and(_T_564, _T_565) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_567 = shr(io.in.a.bits.source, 2) node _T_568 = eq(_T_567, UInt<2>(0h3)) node _T_569 = leq(UInt<1>(0h0), uncommonBits_27) node _T_570 = and(_T_568, _T_569) node _T_571 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_572 = and(_T_570, _T_571) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_576 = or(_T_548, _T_554) node _T_577 = or(_T_576, _T_560) node _T_578 = or(_T_577, _T_566) node _T_579 = or(_T_578, _T_572) node _T_580 = or(_T_579, _T_573) node _T_581 = or(_T_580, _T_574) node _T_582 = or(_T_581, _T_575) node _T_583 = and(_T_547, _T_582) node _T_584 = or(UInt<1>(0h0), _T_583) node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_586 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = or(UInt<1>(0h0), _T_587) node _T_589 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = or(_T_593, _T_598) node _T_600 = and(_T_588, _T_599) node _T_601 = or(UInt<1>(0h0), _T_600) node _T_602 = and(_T_584, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_602, UInt<1>(0h1), "") : assert_36 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_612 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_612, UInt<1>(0h1), "") : assert_39 node _T_616 = eq(io.in.a.bits.mask, mask) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_616, UInt<1>(0h1), "") : assert_40 node _T_620 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_620 : node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_625 = shr(io.in.a.bits.source, 2) node _T_626 = eq(_T_625, UInt<1>(0h0)) node _T_627 = leq(UInt<1>(0h0), uncommonBits_28) node _T_628 = and(_T_626, _T_627) node _T_629 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_630 = and(_T_628, _T_629) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_631 = shr(io.in.a.bits.source, 2) node _T_632 = eq(_T_631, UInt<1>(0h1)) node _T_633 = leq(UInt<1>(0h0), uncommonBits_29) node _T_634 = and(_T_632, _T_633) node _T_635 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_636 = and(_T_634, _T_635) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_637 = shr(io.in.a.bits.source, 2) node _T_638 = eq(_T_637, UInt<2>(0h2)) node _T_639 = leq(UInt<1>(0h0), uncommonBits_30) node _T_640 = and(_T_638, _T_639) node _T_641 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_642 = and(_T_640, _T_641) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_643 = shr(io.in.a.bits.source, 2) node _T_644 = eq(_T_643, UInt<2>(0h3)) node _T_645 = leq(UInt<1>(0h0), uncommonBits_31) node _T_646 = and(_T_644, _T_645) node _T_647 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_652 = or(_T_624, _T_630) node _T_653 = or(_T_652, _T_636) node _T_654 = or(_T_653, _T_642) node _T_655 = or(_T_654, _T_648) node _T_656 = or(_T_655, _T_649) node _T_657 = or(_T_656, _T_650) node _T_658 = or(_T_657, _T_651) node _T_659 = and(_T_623, _T_658) node _T_660 = or(UInt<1>(0h0), _T_659) node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_662 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _T_664 = or(UInt<1>(0h0), _T_663) node _T_665 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<13>(0h1000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = or(_T_669, _T_674) node _T_676 = and(_T_664, _T_675) node _T_677 = or(UInt<1>(0h0), _T_676) node _T_678 = and(_T_660, _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_678, UInt<1>(0h1), "") : assert_41 node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(source_ok, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_685 = asUInt(reset) node _T_686 = eq(_T_685, UInt<1>(0h0)) when _T_686 : node _T_687 = eq(is_aligned, UInt<1>(0h0)) when _T_687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_688 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_688, UInt<1>(0h1), "") : assert_44 node _T_692 = eq(io.in.a.bits.mask, mask) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_692, UInt<1>(0h1), "") : assert_45 node _T_696 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_696 : node _T_697 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_698 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_699 = and(_T_697, _T_698) node _T_700 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<1>(0h0)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_32) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<1>(0h1)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_33) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_713 = shr(io.in.a.bits.source, 2) node _T_714 = eq(_T_713, UInt<2>(0h2)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_34) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<2>(0h3)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_35) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_726 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_727 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_728 = or(_T_700, _T_706) node _T_729 = or(_T_728, _T_712) node _T_730 = or(_T_729, _T_718) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = or(_T_732, _T_726) node _T_734 = or(_T_733, _T_727) node _T_735 = and(_T_699, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_738 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<13>(0h1000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = or(_T_742, _T_747) node _T_749 = and(_T_737, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = and(_T_736, _T_750) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_751, UInt<1>(0h1), "") : assert_46 node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(source_ok, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_758 = asUInt(reset) node _T_759 = eq(_T_758, UInt<1>(0h0)) when _T_759 : node _T_760 = eq(is_aligned, UInt<1>(0h0)) when _T_760 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_761 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_761, UInt<1>(0h1), "") : assert_49 node _T_765 = eq(io.in.a.bits.mask, mask) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_765, UInt<1>(0h1), "") : assert_50 node _T_769 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_769, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_773 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_773, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_777 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_777 : node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(source_ok_1, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_781 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_781, UInt<1>(0h1), "") : assert_54 node _T_785 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_785, UInt<1>(0h1), "") : assert_55 node _T_789 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_789, UInt<1>(0h1), "") : assert_56 node _T_793 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_793, UInt<1>(0h1), "") : assert_57 node _T_797 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_797 : node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(source_ok_1, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(sink_ok, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_804 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_804, UInt<1>(0h1), "") : assert_60 node _T_808 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_809 = asUInt(reset) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(_T_808, UInt<1>(0h0)) when _T_811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_808, UInt<1>(0h1), "") : assert_61 node _T_812 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(_T_812, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_812, UInt<1>(0h1), "") : assert_62 node _T_816 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_816, UInt<1>(0h1), "") : assert_63 node _T_820 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_821 = or(UInt<1>(0h0), _T_820) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_821, UInt<1>(0h1), "") : assert_64 node _T_825 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_825 : node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(source_ok_1, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(sink_ok, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_832 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_832, UInt<1>(0h1), "") : assert_67 node _T_836 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_836, UInt<1>(0h1), "") : assert_68 node _T_840 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(_T_840, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_840, UInt<1>(0h1), "") : assert_69 node _T_844 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_845 = or(_T_844, io.in.d.bits.corrupt) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_845, UInt<1>(0h1), "") : assert_70 node _T_849 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_850, UInt<1>(0h1), "") : assert_71 node _T_854 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_854 : node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok_1, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_858 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_858, UInt<1>(0h1), "") : assert_73 node _T_862 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_863 = asUInt(reset) node _T_864 = eq(_T_863, UInt<1>(0h0)) when _T_864 : node _T_865 = eq(_T_862, UInt<1>(0h0)) when _T_865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_862, UInt<1>(0h1), "") : assert_74 node _T_866 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_867, UInt<1>(0h1), "") : assert_75 node _T_871 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_871 : node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok_1, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_875 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_876 = asUInt(reset) node _T_877 = eq(_T_876, UInt<1>(0h0)) when _T_877 : node _T_878 = eq(_T_875, UInt<1>(0h0)) when _T_878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_875, UInt<1>(0h1), "") : assert_77 node _T_879 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_880 = or(_T_879, io.in.d.bits.corrupt) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_880, UInt<1>(0h1), "") : assert_78 node _T_884 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_885, UInt<1>(0h1), "") : assert_79 node _T_889 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_889 : node _T_890 = asUInt(reset) node _T_891 = eq(_T_890, UInt<1>(0h0)) when _T_891 : node _T_892 = eq(source_ok_1, UInt<1>(0h0)) when _T_892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(_T_893, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_893, UInt<1>(0h1), "") : assert_81 node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(_T_897, UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_897, UInt<1>(0h1), "") : assert_82 node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_902 = or(UInt<1>(0h0), _T_901) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_902, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_906 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_906, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_910 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_910, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_914 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_914, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_918 = eq(a_first, UInt<1>(0h0)) node _T_919 = and(io.in.a.valid, _T_918) when _T_919 : node _T_920 = eq(io.in.a.bits.opcode, opcode) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_920, UInt<1>(0h1), "") : assert_87 node _T_924 = eq(io.in.a.bits.param, param) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_924, UInt<1>(0h1), "") : assert_88 node _T_928 = eq(io.in.a.bits.size, size) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_928, UInt<1>(0h1), "") : assert_89 node _T_932 = eq(io.in.a.bits.source, source) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_932, UInt<1>(0h1), "") : assert_90 node _T_936 = eq(io.in.a.bits.address, address) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_936, UInt<1>(0h1), "") : assert_91 node _T_940 = and(io.in.a.ready, io.in.a.valid) node _T_941 = and(_T_940, a_first) when _T_941 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_942 = eq(d_first, UInt<1>(0h0)) node _T_943 = and(io.in.d.valid, _T_942) when _T_943 : node _T_944 = eq(io.in.d.bits.opcode, opcode_1) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_944, UInt<1>(0h1), "") : assert_92 node _T_948 = eq(io.in.d.bits.param, param_1) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_948, UInt<1>(0h1), "") : assert_93 node _T_952 = eq(io.in.d.bits.size, size_1) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_952, UInt<1>(0h1), "") : assert_94 node _T_956 = eq(io.in.d.bits.source, source_1) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_956, UInt<1>(0h1), "") : assert_95 node _T_960 = eq(io.in.d.bits.sink, sink) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_960, UInt<1>(0h1), "") : assert_96 node _T_964 = eq(io.in.d.bits.denied, denied) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_964, UInt<1>(0h1), "") : assert_97 node _T_968 = and(io.in.d.ready, io.in.d.valid) node _T_969 = and(_T_968, d_first) when _T_969 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_970 = and(io.in.a.valid, a_first_1) node _T_971 = and(_T_970, UInt<1>(0h1)) when _T_971 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_972 = and(io.in.a.ready, io.in.a.valid) node _T_973 = and(_T_972, a_first_1) node _T_974 = and(_T_973, UInt<1>(0h1)) when _T_974 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_975 = dshr(inflight, io.in.a.bits.source) node _T_976 = bits(_T_975, 0, 0) node _T_977 = eq(_T_976, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_977, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_981 = and(io.in.d.valid, d_first_1) node _T_982 = and(_T_981, UInt<1>(0h1)) node _T_983 = eq(d_release_ack, UInt<1>(0h0)) node _T_984 = and(_T_982, _T_983) when _T_984 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_985 = and(io.in.d.ready, io.in.d.valid) node _T_986 = and(_T_985, d_first_1) node _T_987 = and(_T_986, UInt<1>(0h1)) node _T_988 = eq(d_release_ack, UInt<1>(0h0)) node _T_989 = and(_T_987, _T_988) when _T_989 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_990 = and(io.in.d.valid, d_first_1) node _T_991 = and(_T_990, UInt<1>(0h1)) node _T_992 = eq(d_release_ack, UInt<1>(0h0)) node _T_993 = and(_T_991, _T_992) when _T_993 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_994 = dshr(inflight, io.in.d.bits.source) node _T_995 = bits(_T_994, 0, 0) node _T_996 = or(_T_995, same_cycle_resp) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_996, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1000 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1001 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1002 = or(_T_1000, _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_100 node _T_1006 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_101 else : node _T_1010 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1011 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1012 = or(_T_1010, _T_1011) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_102 node _T_1016 = eq(io.in.d.bits.size, a_size_lookup) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_103 node _T_1020 = and(io.in.d.valid, d_first_1) node _T_1021 = and(_T_1020, a_first_1) node _T_1022 = and(_T_1021, io.in.a.valid) node _T_1023 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1024 = and(_T_1022, _T_1023) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.a.ready) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_104 node _T_1032 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1033 = orr(a_set_wo_ready) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) node _T_1035 = or(_T_1032, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_8 node _T_1039 = orr(inflight) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1042 = or(_T_1040, _T_1041) node _T_1043 = lt(watchdog, plusarg_reader.out) node _T_1044 = or(_T_1042, _T_1043) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1048 = and(io.in.a.ready, io.in.a.valid) node _T_1049 = and(io.in.d.ready, io.in.d.valid) node _T_1050 = or(_T_1048, _T_1049) when _T_1050 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1051 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1052 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1053 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = and(_T_1051, _T_1054) when _T_1055 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1056 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1057 = and(_T_1056, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1058 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1059 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = and(_T_1057, _T_1060) when _T_1061 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1062 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1063 = bits(_T_1062, 0, 0) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1068 = and(io.in.d.valid, d_first_2) node _T_1069 = and(_T_1068, UInt<1>(0h1)) node _T_1070 = and(_T_1069, d_release_ack_1) when _T_1070 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1071 = and(io.in.d.ready, io.in.d.valid) node _T_1072 = and(_T_1071, d_first_2) node _T_1073 = and(_T_1072, UInt<1>(0h1)) node _T_1074 = and(_T_1073, d_release_ack_1) when _T_1074 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1075 = and(io.in.d.valid, d_first_2) node _T_1076 = and(_T_1075, UInt<1>(0h1)) node _T_1077 = and(_T_1076, d_release_ack_1) when _T_1077 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1078 = dshr(inflight_1, io.in.d.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = or(_T_1079, same_cycle_resp_1) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1084 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_109 else : node _T_1088 = eq(io.in.d.bits.size, c_size_lookup) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_110 node _T_1092 = and(io.in.d.valid, d_first_2) node _T_1093 = and(_T_1092, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1094 = and(_T_1093, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1095 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = and(_T_1096, d_release_ack_1) node _T_1098 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1099 = and(_T_1097, _T_1098) when _T_1099 : node _T_1100 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1101 = or(_T_1100, _WIRE_23.ready) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_111 node _T_1105 = orr(c_set_wo_ready) when _T_1105 : node _T_1106 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_9 node _T_1110 = orr(inflight_1) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1113 = or(_T_1111, _T_1112) node _T_1114 = lt(watchdog_1, plusarg_reader_1.out) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1119 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1120 = and(io.in.d.ready, io.in.d.valid) node _T_1121 = or(_T_1119, _T_1120) when _T_1121 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1048 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1048; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1048; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1121 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1121; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1121; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_974 = _T_1048 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_974 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_974 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_974 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_974 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_974 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1020 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1020 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_989 = _T_1121 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_989 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_989 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_989 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1092 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1092 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1074 = _T_1121 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1074 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1074 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1074 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_175 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_175( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ITLB : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_28 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s2 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_2 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_29 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_30 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_31 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_32 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_33 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_34 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_35 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_36 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_37 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_38 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_39 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_40 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_41 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gf_inst_array, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)

module ITLB( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output io_ptw_req_bits_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_kill // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_cacheable; // @[TLB.scala:422:19] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] reg [1:0] waddr; // @[TLB.scala:355:34] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_need_gpa; // @[TLB.scala:361:23] wire _vm_enabled_T_1 = io_ptw_ptbr_mode[3] & ~(io_req_bits_prv[1]); // @[TLB.scala:372:27, :374:41, :399:45] wire io_ptw_req_valid_0 = state == 2'h1; // @[package.scala:16:47] wire ignore_13 = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire [27:0] mpu_ppn = io_ptw_resp_valid ? {8'h0, io_ptw_resp_bits_pte_ppn[19:0]} : _vm_enabled_T_1 ? {8'h0, _mpu_ppn_barrier_io_y_ppn[19:18], (ignore_13 ? io_req_bits_vaddr[29:21] : 9'h0) | _mpu_ppn_barrier_io_y_ppn[17:9], (special_entry_level[1] ? 9'h0 : io_req_bits_vaddr[20:12]) | _mpu_ppn_barrier_io_y_ppn[8:0]} : io_req_bits_vaddr[39:12]; // @[package.scala:267:25] wire [2:0] mpu_priv = io_ptw_resp_valid ? 3'h1 : {io_ptw_status_debug, io_req_bits_prv}; // @[TLB.scala:415:{27,103}] wire deny_access_to_debug = ~(mpu_priv[2]) & mpu_ppn == 28'h0; // @[TLB.scala:412:20, :415:27, :428:{39,50}] wire prot_x = _pma_io_resp_x & ~deny_access_to_debug & _pmp_io_x; // @[TLB.scala:416:19, :422:19, :428:50, :429:33, :434:{30,55}] wire [24:0] _hitsVec_T = sectored_entries_0_0_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_6 = sectored_entries_0_1_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_12 = sectored_entries_0_2_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_18 = sectored_entries_0_3_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_24 = sectored_entries_0_4_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_30 = sectored_entries_0_5_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_36 = sectored_entries_0_6_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [24:0] _hitsVec_T_42 = sectored_entries_0_7_tag_vpn[26:2] ^ io_req_bits_vaddr[38:14]; // @[TLB.scala:174:61, :335:30, :339:29] wire [17:0] _hitsVec_T_58 = superpage_entries_0_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_1 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_73 = superpage_entries_1_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_4 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_88 = superpage_entries_2_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_7 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [17:0] _hitsVec_T_103 = superpage_entries_3_tag_vpn[26:9] ^ io_req_bits_vaddr[38:21]; // @[TLB.scala:183:52, :335:30, :341:30] wire ignore_10 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire [3:0] _GEN = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_0 = _vm_enabled_T_1 & _GEN[io_req_bits_vaddr[13:12]] & _hitsVec_T == 25'h0 & ~sectored_entries_0_0_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_0 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_1 = _vm_enabled_T_1 & _GEN_0[io_req_bits_vaddr[13:12]] & _hitsVec_T_6 == 25'h0 & ~sectored_entries_0_1_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_1 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_2 = _vm_enabled_T_1 & _GEN_1[io_req_bits_vaddr[13:12]] & _hitsVec_T_12 == 25'h0 & ~sectored_entries_0_2_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_2 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_3 = _vm_enabled_T_1 & _GEN_2[io_req_bits_vaddr[13:12]] & _hitsVec_T_18 == 25'h0 & ~sectored_entries_0_3_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_3 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_4 = _vm_enabled_T_1 & _GEN_3[io_req_bits_vaddr[13:12]] & _hitsVec_T_24 == 25'h0 & ~sectored_entries_0_4_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_4 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_5 = _vm_enabled_T_1 & _GEN_4[io_req_bits_vaddr[13:12]] & _hitsVec_T_30 == 25'h0 & ~sectored_entries_0_5_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_5 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_6 = _vm_enabled_T_1 & _GEN_5[io_req_bits_vaddr[13:12]] & _hitsVec_T_36 == 25'h0 & ~sectored_entries_0_6_tag_v; // @[package.scala:163:13] wire [3:0] _GEN_6 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire hitsVec_7 = _vm_enabled_T_1 & _GEN_6[io_req_bits_vaddr[13:12]] & _hitsVec_T_42 == 25'h0 & ~sectored_entries_0_7_tag_v; // @[package.scala:163:13] wire hitsVec_8 = _vm_enabled_T_1 & superpage_entries_0_valid_0 & ~superpage_entries_0_tag_v & _hitsVec_T_58[17:9] == 9'h0 & (ignore_1 | _hitsVec_T_58[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_9 = _vm_enabled_T_1 & superpage_entries_1_valid_0 & ~superpage_entries_1_tag_v & _hitsVec_T_73[17:9] == 9'h0 & (ignore_4 | _hitsVec_T_73[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_10 = _vm_enabled_T_1 & superpage_entries_2_valid_0 & ~superpage_entries_2_tag_v & _hitsVec_T_88[17:9] == 9'h0 & (ignore_7 | _hitsVec_T_88[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire hitsVec_11 = _vm_enabled_T_1 & superpage_entries_3_valid_0 & ~superpage_entries_3_tag_v & _hitsVec_T_103[17:9] == 9'h0 & (ignore_10 | _hitsVec_T_103[8:0] == 9'h0); // @[TLB.scala:178:{33,43}, :182:28, :183:{29,40,52,58,79}, :341:30, :399:45, :440:44] wire [26:0] _hitsVec_T_118 = special_entry_tag_vpn ^ io_req_bits_vaddr[38:12]; // @[TLB.scala:183:52, :335:30, :346:56] wire hitsVec_12 = _vm_enabled_T_1 & special_entry_valid_0 & _hitsVec_T_118[26:18] == 9'h0 & (ignore_13 | _hitsVec_T_118[17:9] == 9'h0) & (~(special_entry_level[1]) | _hitsVec_T_118[8:0] == 9'h0); // @[TLB.scala:183:{29,40,52,58,79}, :197:28, :346:56, :399:45, :440:44] wire [12:0] real_hits = {hitsVec_12, hitsVec_11, hitsVec_10, hitsVec_9, hitsVec_8, hitsVec_7, hitsVec_6, hitsVec_5, hitsVec_4, hitsVec_3, hitsVec_2, hitsVec_1, hitsVec_0}; // @[package.scala:45:27] wire [13:0] hits = {~_vm_enabled_T_1, hitsVec_12, hitsVec_11, hitsVec_10, hitsVec_9, hitsVec_8, hitsVec_7, hitsVec_6, hitsVec_5, hitsVec_4, hitsVec_3, hitsVec_2, hitsVec_1, hitsVec_0}; // @[TLB.scala:174:95, :178:33, :183:29, :188:18, :399:45, :440:44, :442:{17,18}] wire [3:0][41:0] _GEN_7 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_7[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_8 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_8[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_9 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_9[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_10 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_10[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_11 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_11[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_12 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_12[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_13 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_13[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire [3:0][41:0] _GEN_14 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_14[io_req_bits_vaddr[13:12]]; // @[package.scala:163:13] wire bad_va = _vm_enabled_T_1 & ~(io_req_bits_vaddr[39:38] == 2'h0 | (&(io_req_bits_vaddr[39:38]))); // @[TLB.scala:320:14, :399:45, :559:43, :560:{37,51,59,86}, :568:34] wire tlb_miss = _vm_enabled_T_1 & ~bad_va & real_hits == 13'h0; // @[package.scala:45:27] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire multipleHits_rightOne_1 = hitsVec_1 | hitsVec_2; // @[Misc.scala:183:16] wire multipleHits_leftOne_2 = hitsVec_0 | multipleHits_rightOne_1; // @[Misc.scala:183:16] wire multipleHits_rightOne_3 = hitsVec_4 | hitsVec_5; // @[Misc.scala:183:16] wire multipleHits_rightOne_4 = hitsVec_3 | multipleHits_rightOne_3; // @[Misc.scala:183:16] wire multipleHits_rightOne_6 = hitsVec_7 | hitsVec_8; // @[Misc.scala:183:16] wire multipleHits_leftOne_8 = hitsVec_6 | multipleHits_rightOne_6; // @[Misc.scala:183:16] wire multipleHits_leftOne_10 = hitsVec_9 | hitsVec_10; // @[Misc.scala:183:16] wire multipleHits_rightOne_9 = hitsVec_11 | hitsVec_12; // @[Misc.scala:183:16] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire multipleHits = hitsVec_1 & hitsVec_2 | hitsVec_0 & multipleHits_rightOne_1 | hitsVec_4 & hitsVec_5 | hitsVec_3 & multipleHits_rightOne_3 | multipleHits_leftOne_2 & multipleHits_rightOne_4 | hitsVec_7 & hitsVec_8 | hitsVec_6 & multipleHits_rightOne_6 | hitsVec_9 & hitsVec_10 | hitsVec_11 & hitsVec_12 | multipleHits_leftOne_10 & multipleHits_rightOne_9 | multipleHits_leftOne_8 & multipleHits_rightOne_10 | (multipleHits_leftOne_2 | multipleHits_rightOne_4) & (multipleHits_leftOne_8 | multipleHits_rightOne_10); // @[Misc.scala:183:{16,37,49,61}]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_4 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_4( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - 12'h2B; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_116 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_137 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_116( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_137 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 : input clock : Clock input reset : Reset output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clientNodeOut.d.bits.corrupt invalidate clientNodeOut.d.bits.data invalidate clientNodeOut.d.bits.denied invalidate clientNodeOut.d.bits.sink invalidate clientNodeOut.d.bits.source invalidate clientNodeOut.d.bits.size invalidate clientNodeOut.d.bits.param invalidate clientNodeOut.d.bits.opcode invalidate clientNodeOut.d.valid invalidate clientNodeOut.d.ready invalidate clientNodeOut.a.bits.corrupt invalidate clientNodeOut.a.bits.data invalidate clientNodeOut.a.bits.mask invalidate clientNodeOut.a.bits.address invalidate clientNodeOut.a.bits.source invalidate clientNodeOut.a.bits.size invalidate clientNodeOut.a.bits.param invalidate clientNodeOut.a.bits.opcode invalidate clientNodeOut.a.valid invalidate clientNodeOut.a.ready connect auto.client_out, clientNodeOut wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect manager_tl.e.bits.sink, UInt<8>(0h0) connect manager_tl.e.valid, UInt<1>(0h0) connect manager_tl.e.ready, UInt<1>(0h0) connect manager_tl.d.bits.corrupt, UInt<1>(0h0) connect manager_tl.d.bits.data, UInt<64>(0h0) connect manager_tl.d.bits.denied, UInt<1>(0h0) connect manager_tl.d.bits.sink, UInt<8>(0h0) connect manager_tl.d.bits.source, UInt<8>(0h0) connect manager_tl.d.bits.size, UInt<8>(0h0) connect manager_tl.d.bits.param, UInt<2>(0h0) connect manager_tl.d.bits.opcode, UInt<3>(0h0) connect manager_tl.d.valid, UInt<1>(0h0) connect manager_tl.d.ready, UInt<1>(0h0) connect manager_tl.c.bits.corrupt, UInt<1>(0h0) connect manager_tl.c.bits.data, UInt<64>(0h0) connect manager_tl.c.bits.address, UInt<64>(0h0) connect manager_tl.c.bits.source, UInt<8>(0h0) connect manager_tl.c.bits.size, UInt<8>(0h0) connect manager_tl.c.bits.param, UInt<3>(0h0) connect manager_tl.c.bits.opcode, UInt<3>(0h0) connect manager_tl.c.valid, UInt<1>(0h0) connect manager_tl.c.ready, UInt<1>(0h0) connect manager_tl.b.bits.corrupt, UInt<1>(0h0) connect manager_tl.b.bits.data, UInt<64>(0h0) connect manager_tl.b.bits.mask, UInt<8>(0h0) connect manager_tl.b.bits.address, UInt<64>(0h0) connect manager_tl.b.bits.source, UInt<8>(0h0) connect manager_tl.b.bits.size, UInt<8>(0h0) connect manager_tl.b.bits.param, UInt<2>(0h0) connect manager_tl.b.bits.opcode, UInt<3>(0h0) connect manager_tl.b.valid, UInt<1>(0h0) connect manager_tl.b.ready, UInt<1>(0h0) connect manager_tl.a.bits.corrupt, UInt<1>(0h0) connect manager_tl.a.bits.data, UInt<64>(0h0) connect manager_tl.a.bits.mask, UInt<8>(0h0) connect manager_tl.a.bits.address, UInt<64>(0h0) connect manager_tl.a.bits.source, UInt<8>(0h0) connect manager_tl.a.bits.size, UInt<8>(0h0) connect manager_tl.a.bits.param, UInt<3>(0h0) connect manager_tl.a.bits.opcode, UInt<3>(0h0) connect manager_tl.a.valid, UInt<1>(0h0) connect manager_tl.a.ready, UInt<1>(0h0) inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_1_2.clock, clock connect out_channels_1_2.reset, reset wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE.bits.data, UInt<64>(0h0) connect _out_channels_WIRE.bits.mask, UInt<8>(0h0) connect _out_channels_WIRE.bits.address, UInt<32>(0h0) connect _out_channels_WIRE.bits.source, UInt<4>(0h0) connect _out_channels_WIRE.bits.size, UInt<4>(0h0) connect _out_channels_WIRE.bits.param, UInt<2>(0h0) connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_3_1.bits, _out_channels_WIRE.bits connect out_channels_3_1.valid, _out_channels_WIRE.valid connect out_channels_3_1.ready, _out_channels_WIRE.ready inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_3_2.clock, clock connect out_channels_3_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_1_2.io.protocol, clientNodeOut.d inst ser_1 of GenericSerializer_TLBeatw67_f32 connect ser_1.clock, clock connect ser_1.reset, reset connect ser_1.io.in, out_channels_1_2.io.beat connect io.ser[1].out.bits, ser_1.io.out.bits connect io.ser[1].out.valid, ser_1.io.out.valid connect ser_1.io.out.ready, io.ser[1].out.ready connect out_channels_3_2.io.protocol, out_channels_3_1 inst ser_3 of GenericSerializer_TLBeatw87_f32 connect ser_3.clock, clock connect ser_3.reset, reset connect ser_3.io.in, out_channels_3_2.io.beat connect io.ser[3].out.bits, ser_3.io.out.bits connect io.ser[3].out.valid, ser_3.io.out.valid connect ser_3.io.out.ready, io.ser[3].out.ready node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _in_channels_WIRE.bits.sink, UInt<1>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect in_channels_0_1.bits, _in_channels_WIRE.bits connect in_channels_0_1.valid, _in_channels_WIRE.valid connect in_channels_0_1.ready, _in_channels_WIRE.ready inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE_1.valid, UInt<1>(0h0) connect _in_channels_WIRE_1.ready, UInt<1>(0h0) wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_2_1.bits, _in_channels_WIRE_1.bits connect in_channels_2_1.valid, _in_channels_WIRE_1.valid connect in_channels_2_1.ready, _in_channels_WIRE_1.ready inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready inst des_0 of GenericDeserializer_TLBeatw10_f32 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready inst des_2 of GenericDeserializer_TLBeatw88_f32 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready inst des_3 of GenericDeserializer_TLBeatw87_f32 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_1 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3

module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_1_out_ready, // @[TLSerdes.scala:40:16] output io_ser_1_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_3_out_ready, // @[TLSerdes.scala:40:16] output io_ser_3_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] output io_debug_ser_busy, // @[TLSerdes.scala:40:16] output io_debug_des_busy // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28] wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_2_2_io_protocol_bits_size; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_2_2_io_protocol_bits_source; // @[TLSerdes.scala:80:28] wire [63:0] _in_channels_2_2_io_protocol_bits_address; // @[TLSerdes.scala:80:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_0_2_io_protocol_bits_sink; // @[TLSerdes.scala:78:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_3_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_3_io_busy; // @[TLSerdes.scala:69:23] wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_1_io_busy; // @[TLSerdes.scala:69:23] wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50] wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50] wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50] wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50] wire auto_client_out_a_ready_0 = auto_client_out_a_ready; // @[TLSerdes.scala:39:9] wire auto_client_out_d_valid_0 = auto_client_out_d_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_d_bits_opcode_0 = auto_client_out_d_bits_opcode; // @[TLSerdes.scala:39:9] wire [1:0] auto_client_out_d_bits_param_0 = auto_client_out_d_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_size_0 = auto_client_out_d_bits_size; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_source_0 = auto_client_out_d_bits_source; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_sink_0 = auto_client_out_d_bits_sink; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_denied_0 = auto_client_out_d_bits_denied; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_d_bits_data_0 = auto_client_out_d_bits_data; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_corrupt_0 = auto_client_out_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_out_ready_0 = io_ser_1_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_out_ready_0 = io_ser_3_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire [1:0] _out_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] out_channels_3_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [7:0] manager_tl_a_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_mask = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_e_bits_sink = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] _out_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] out_channels_3_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [2:0] manager_tl_a_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_a_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] _out_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] out_channels_3_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _in_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _in_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [3:0] _out_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] out_channels_3_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] out_channels_3_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _in_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _in_channels_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [63:0] manager_tl_a_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_a_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] _out_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] out_channels_3_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _in_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [31:0] io_ser_0_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] out_channels_3_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _in_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire manager_tl_a_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_b_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_d_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_valid = 1'h0; // @[TLSerdes.scala:47:72] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire out_channels_3_1_valid = 1'h0; // @[Bundles.scala:264:61] wire out_channels_3_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _in_channels_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire in_channels_0_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _in_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_channels_2_1_ready = 1'h0; // @[Bundles.scala:265:61] wire io_ser_0_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_2_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_4_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire out_channels_3_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire clientNodeOut_a_ready = auto_client_out_a_ready_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] clientNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] clientNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] clientNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire clientNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire clientNodeOut_d_ready; // @[MixedNode.scala:542:17] wire clientNodeOut_d_valid = auto_client_out_d_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] clientNodeOut_d_bits_opcode = auto_client_out_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] clientNodeOut_d_bits_param = auto_client_out_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_size = auto_client_out_d_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_source = auto_client_out_d_bits_source_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_sink = auto_client_out_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_denied = auto_client_out_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] clientNodeOut_d_bits_data = auto_client_out_d_bits_data_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_corrupt = auto_client_out_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire _io_debug_ser_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire [2:0] auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] wire auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] wire io_debug_des_busy_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_valid_0 = clientNodeOut_a_valid; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode_0 = clientNodeOut_a_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param_0 = clientNodeOut_a_bits_param; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size_0 = clientNodeOut_a_bits_size; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source_0 = clientNodeOut_a_bits_source; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address_0 = clientNodeOut_a_bits_address; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask_0 = clientNodeOut_a_bits_mask; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data_0 = clientNodeOut_a_bits_data; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt_0 = clientNodeOut_a_bits_corrupt; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready_0 = clientNodeOut_d_ready; // @[TLSerdes.scala:39:9] wire [2:0] manager_tl_b_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_b_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_source; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_address; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_mask; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_b_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_b_valid; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_d_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_d_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_source; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_sink; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_denied; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_d_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_d_valid; // @[TLSerdes.scala:47:72] assign _io_debug_ser_busy_T = _ser_1_io_busy | _ser_3_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy_0 = _io_debug_ser_busy_T; // @[TLSerdes.scala:39:9] wire in_channels_0_1_bits_sink; // @[Bundles.scala:267:61] wire in_channels_0_1_valid; // @[Bundles.scala:267:61] wire [2:0] in_channels_2_1_bits_opcode; // @[Bundles.scala:265:61] wire [2:0] in_channels_2_1_bits_param; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_size; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_source; // @[Bundles.scala:265:61] wire [31:0] in_channels_2_1_bits_address; // @[Bundles.scala:265:61] wire [63:0] in_channels_2_1_bits_data; // @[Bundles.scala:265:61] wire in_channels_2_1_bits_corrupt; // @[Bundles.scala:265:61] wire in_channels_2_1_valid; // @[Bundles.scala:265:61] assign in_channels_0_1_bits_sink = _in_channels_0_2_io_protocol_bits_sink[0]; // @[TLSerdes.scala:78:28, :85:9] assign in_channels_2_1_bits_size = _in_channels_2_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_source = _in_channels_2_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_address = _in_channels_2_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:80:28, :85:9] assign clientNodeOut_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:82:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy_0 = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_d_ready), .io_protocol_valid (clientNodeOut_d_valid), // @[MixedNode.scala:542:17] .io_protocol_bits_opcode (clientNodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_protocol_bits_param (clientNodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_protocol_bits_size ({4'h0, clientNodeOut_d_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({4'h0, clientNodeOut_d_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_sink ({7'h0, clientNodeOut_d_bits_sink}), // @[TLSerdes.scala:68:21] .io_protocol_bits_denied (clientNodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_protocol_bits_data (clientNodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_protocol_bits_corrupt (clientNodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_1_2_io_beat_valid), .io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_1_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail) ); // @[TLSerdes.scala:60:50] TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_3_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_3_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail) ); // @[TLSerdes.scala:62:50] GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_1_io_in_ready), .io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50] .io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50] .io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50] .io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50] .io_out_ready (io_ser_1_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_1_out_valid_0), .io_out_bits_flit (io_ser_1_out_bits_flit_0), .io_busy (_ser_1_io_busy) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_3_io_in_ready), .io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50] .io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50] .io_out_ready (io_ser_3_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_3_out_valid_0), .io_out_bits_flit (io_ser_3_out_bits_flit_0), .io_busy (_ser_3_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_0_1_valid), .io_protocol_bits_sink (_in_channels_0_2_io_protocol_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_d_valid), .io_protocol_bits_opcode (manager_tl_d_bits_opcode), .io_protocol_bits_param (manager_tl_d_bits_param), .io_protocol_bits_size (manager_tl_d_bits_size), .io_protocol_bits_source (manager_tl_d_bits_source), .io_protocol_bits_sink (manager_tl_d_bits_sink), .io_protocol_bits_denied (manager_tl_d_bits_denied), .io_protocol_bits_data (manager_tl_d_bits_data), .io_protocol_bits_corrupt (manager_tl_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_2_1_valid), .io_protocol_bits_opcode (in_channels_2_1_bits_opcode), .io_protocol_bits_param (in_channels_2_1_bits_param), .io_protocol_bits_size (_in_channels_2_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_2_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_2_2_io_protocol_bits_address), .io_protocol_bits_data (in_channels_2_1_bits_data), .io_protocol_bits_corrupt (in_channels_2_1_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_b_valid), .io_protocol_bits_opcode (manager_tl_b_bits_opcode), .io_protocol_bits_param (manager_tl_b_bits_param), .io_protocol_bits_size (manager_tl_b_bits_size), .io_protocol_bits_source (manager_tl_b_bits_source), .io_protocol_bits_address (manager_tl_b_bits_address), .io_protocol_bits_mask (manager_tl_b_bits_mask), .io_protocol_bits_data (manager_tl_b_bits_data), .io_protocol_bits_corrupt (manager_tl_b_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_a_ready), // @[MixedNode.scala:542:17] .io_protocol_valid (clientNodeOut_a_valid), .io_protocol_bits_opcode (clientNodeOut_a_bits_opcode), .io_protocol_bits_param (clientNodeOut_a_bits_param), .io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address), .io_protocol_bits_mask (clientNodeOut_a_bits_mask), .io_protocol_bits_data (clientNodeOut_a_bits_data), .io_protocol_bits_corrupt (clientNodeOut_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_1 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_client_out_a_valid = auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode = auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param = auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size = auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source = auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address = auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask = auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data = auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt = auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready = auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_valid = io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_bits_flit = io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_valid = io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_bits_flit = io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_debug_ser_busy = io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] assign io_debug_des_busy = io_debug_des_busy_0; // @[TLSerdes.scala:39:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_13( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_127 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_137 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_127( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_137 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_51 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg

module AsyncResetRegVec_w1_i0_51( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module Tile_215 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_471 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_215( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_471 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_7 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T

module AsyncResetSynchronizerShiftReg_w4_d3_i0_7( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_97 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_98 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_99 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_100 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_167 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_423 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_167( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_423 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_68 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_68 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_68 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_100 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFN_e8_s24_68( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_68 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_68 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_100 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Tile_228 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_484 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_228( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_484 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_20 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_20( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_91 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_92 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_sbus_to_bus_named_cbus : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst widget of TLWidthWidget16 connect widget.clock, clock connect widget.reset, reset wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn connect widget.auto.anon_out.d, bus_xingIn.d connect bus_xingIn.a.bits, widget.auto.anon_out.a.bits connect bus_xingIn.a.valid, widget.auto.anon_out.a.valid connect widget.auto.anon_out.a.ready, bus_xingIn.a.ready connect auto.bus_xing_out, bus_xingOut connect widget.auto.anon_in, auto.widget_anon_in extmodule plusarg_reader_8 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_9 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLInterconnectCoupler_sbus_to_bus_named_cbus( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [15:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_ready_0 = auto_bus_xing_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_valid_0 = auto_bus_xing_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_d_bits_opcode_0 = auto_bus_xing_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_bus_xing_out_d_bits_param_0 = auto_bus_xing_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_d_bits_size_0 = auto_bus_xing_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_d_bits_source_0 = auto_bus_xing_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_sink_0 = auto_bus_xing_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_denied_0 = auto_bus_xing_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_d_bits_data_0 = auto_bus_xing_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_bits_corrupt_0 = auto_bus_xing_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire bus_xingOut_a_ready = auto_bus_xing_out_a_ready_0; // @[MixedNode.scala:542:17] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingOut_d_valid = auto_bus_xing_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] bus_xingOut_d_bits_opcode = auto_bus_xing_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] bus_xingOut_d_bits_param = auto_bus_xing_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] bus_xingOut_d_bits_size = auto_bus_xing_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [7:0] bus_xingOut_d_bits_source = auto_bus_xing_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_sink = auto_bus_xing_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_denied = auto_bus_xing_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [63:0] bus_xingOut_d_bits_data = auto_bus_xing_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire bus_xingOut_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [127:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [3:0] auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [28:0] auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_valid_0 = bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_opcode_0 = bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] bus_xingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_param_0 = bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] bus_xingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_size_0 = bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_source_0 = bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] bus_xingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_address_0 = bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] bus_xingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_mask_0 = bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] bus_xingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_data_0 = bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_a_bits_corrupt_0 = bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire bus_xingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_bus_xing_out_d_ready_0 = bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [7:0] bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] TLWidthWidget16 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_param (auto_widget_anon_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_source (auto_widget_anon_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_mask (auto_widget_anon_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_ready (auto_widget_anon_in_d_ready_0), // @[LazyModuleImp.scala:138:7] .auto_anon_in_d_valid (auto_widget_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param_0), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_widget_anon_in_d_bits_source_0), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink_0), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied_0), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data_0), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt_0), .auto_anon_out_a_ready (bus_xingIn_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (bus_xingIn_a_valid), .auto_anon_out_a_bits_opcode (bus_xingIn_a_bits_opcode), .auto_anon_out_a_bits_param (bus_xingIn_a_bits_param), .auto_anon_out_a_bits_size (bus_xingIn_a_bits_size), .auto_anon_out_a_bits_source (bus_xingIn_a_bits_source), .auto_anon_out_a_bits_address (bus_xingIn_a_bits_address), .auto_anon_out_a_bits_mask (bus_xingIn_a_bits_mask), .auto_anon_out_a_bits_data (bus_xingIn_a_bits_data), .auto_anon_out_a_bits_corrupt (bus_xingIn_a_bits_corrupt), .auto_anon_out_d_ready (bus_xingIn_d_ready), .auto_anon_out_d_valid (bus_xingIn_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (bus_xingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (bus_xingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (bus_xingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (bus_xingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (bus_xingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (bus_xingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (bus_xingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (bus_xingIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[WidthWidget.scala:230:28] assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_param = auto_widget_anon_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_sink = auto_widget_anon_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_valid = auto_bus_xing_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_opcode = auto_bus_xing_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_param = auto_bus_xing_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_size = auto_bus_xing_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_source = auto_bus_xing_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_address = auto_bus_xing_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_mask = auto_bus_xing_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_data = auto_bus_xing_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_a_bits_corrupt = auto_bus_xing_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_bus_xing_out_d_ready = auto_bus_xing_out_d_ready_0; // @[LazyModuleImp.scala:138:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_54 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_54( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_55 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg

module AsyncResetRegVec_w1_i0_55( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module Core : input clock : Clock input reset : Reset output io : { imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip dcpath : { halt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} inst c of CtlPath connect c.clock, clock connect c.reset, reset inst d of DatPath connect d.clock, clock connect d.reset, reset connect d.io.ctl, c.io.ctl connect c.io.dat, d.io.dat connect c.io.imem.resp, io.imem.resp connect io.imem.req.bits, c.io.imem.req.bits connect io.imem.req.valid, c.io.imem.req.valid connect c.io.imem.req.ready, io.imem.req.ready connect d.io.imem.resp, io.imem.resp connect io.imem.req.bits, d.io.imem.req.bits connect io.imem.req.valid, d.io.imem.req.valid connect d.io.imem.req.ready, io.imem.req.ready connect c.io.dmem.resp, io.dmem.resp connect io.dmem.req.bits, c.io.dmem.req.bits connect io.dmem.req.valid, c.io.dmem.req.valid connect c.io.dmem.req.ready, io.dmem.req.ready connect d.io.dmem.resp, io.dmem.resp connect io.dmem.req.bits, d.io.dmem.req.bits connect io.dmem.req.valid, d.io.dmem.req.valid connect d.io.dmem.req.ready, io.dmem.req.ready connect io.dmem.req.valid, c.io.dmem.req.valid connect io.dmem.req.bits.typ, c.io.dmem.req.bits.typ connect io.dmem.req.bits.fcn, c.io.dmem.req.bits.fcn connect d.io.ddpath, io.ddpath connect c.io.dcpath, io.dcpath connect d.io.interrupt.meip, io.interrupt.meip connect d.io.interrupt.msip, io.interrupt.msip connect d.io.interrupt.mtip, io.interrupt.mtip connect d.io.interrupt.debug, io.interrupt.debug connect d.io.hartid, io.hartid connect d.io.reset_vector, io.reset_vector

module Core( // @[core.scala:36:7] input clock, // @[core.scala:36:7] input reset, // @[core.scala:36:7] input io_imem_req_ready, // @[core.scala:38:14] output io_imem_req_valid, // @[core.scala:38:14] output [31:0] io_imem_req_bits_addr, // @[core.scala:38:14] input io_imem_resp_valid, // @[core.scala:38:14] input [31:0] io_imem_resp_bits_data, // @[core.scala:38:14] input io_dmem_req_ready, // @[core.scala:38:14] output io_dmem_req_valid, // @[core.scala:38:14] output [31:0] io_dmem_req_bits_addr, // @[core.scala:38:14] output [31:0] io_dmem_req_bits_data, // @[core.scala:38:14] output io_dmem_req_bits_fcn, // @[core.scala:38:14] output [2:0] io_dmem_req_bits_typ, // @[core.scala:38:14] input io_dmem_resp_valid, // @[core.scala:38:14] input [31:0] io_dmem_resp_bits_data, // @[core.scala:38:14] input io_interrupt_debug, // @[core.scala:38:14] input io_interrupt_mtip, // @[core.scala:38:14] input io_interrupt_msip, // @[core.scala:38:14] input io_interrupt_meip, // @[core.scala:38:14] input io_hartid // @[core.scala:38:14] ); wire _d_io_dat_if_valid_resp; // @[core.scala:40:18] wire [31:0] _d_io_dat_inst; // @[core.scala:40:18] wire _d_io_dat_br_eq; // @[core.scala:40:18] wire _d_io_dat_br_lt; // @[core.scala:40:18] wire _d_io_dat_br_ltu; // @[core.scala:40:18] wire _d_io_dat_inst_misaligned; // @[core.scala:40:18] wire _d_io_dat_data_misaligned; // @[core.scala:40:18] wire _d_io_dat_mem_store; // @[core.scala:40:18] wire _d_io_dat_csr_eret; // @[core.scala:40:18] wire _d_io_dat_csr_interrupt; // @[core.scala:40:18] wire _c_io_ctl_stall; // @[core.scala:39:18] wire _c_io_ctl_if_kill; // @[core.scala:39:18] wire [2:0] _c_io_ctl_pc_sel; // @[core.scala:39:18] wire [1:0] _c_io_ctl_op1_sel; // @[core.scala:39:18] wire [2:0] _c_io_ctl_op2_sel; // @[core.scala:39:18] wire [4:0] _c_io_ctl_alu_fun; // @[core.scala:39:18] wire [1:0] _c_io_ctl_wb_sel; // @[core.scala:39:18] wire _c_io_ctl_rf_wen; // @[core.scala:39:18] wire [2:0] _c_io_ctl_csr_cmd; // @[core.scala:39:18] wire _c_io_ctl_mem_val; // @[core.scala:39:18] wire [1:0] _c_io_ctl_mem_fcn; // @[core.scala:39:18] wire [2:0] _c_io_ctl_mem_typ; // @[core.scala:39:18] wire _c_io_ctl_exception; // @[core.scala:39:18] wire [31:0] _c_io_ctl_exception_cause; // @[core.scala:39:18] wire [2:0] _c_io_ctl_pc_sel_no_xept; // @[core.scala:39:18] wire io_imem_req_ready_0 = io_imem_req_ready; // @[core.scala:36:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[core.scala:36:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[core.scala:36:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[core.scala:36:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[core.scala:36:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[core.scala:36:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[core.scala:36:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[core.scala:36:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[core.scala:36:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[core.scala:36:7] wire io_hartid_0 = io_hartid; // @[core.scala:36:7] wire [31:0] io_reset_vector = 32'h10000; // @[core.scala:36:7, :38:14, :40:18] wire [4:0] io_ddpath_addr = 5'h0; // @[core.scala:36:7, :38:14, :40:18] wire [2:0] io_imem_req_bits_typ = 3'h7; // @[core.scala:36:7, :38:14, :40:18] wire io_imem_req_bits_fcn = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_ddpath_validreq = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_ddpath_resetpc = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire io_dcpath_halt = 1'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_imem_req_bits_data = 32'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_ddpath_wdata = 32'h0; // @[core.scala:36:7, :38:14, :39:18, :40:18] wire [31:0] io_imem_req_bits_addr_0; // @[core.scala:36:7] wire io_imem_req_valid_0; // @[core.scala:36:7] wire [31:0] io_dmem_req_bits_addr_0; // @[core.scala:36:7] wire [31:0] io_dmem_req_bits_data_0; // @[core.scala:36:7] wire io_dmem_req_bits_fcn_0; // @[core.scala:36:7] wire [2:0] io_dmem_req_bits_typ_0; // @[core.scala:36:7] wire io_dmem_req_valid_0; // @[core.scala:36:7] wire [31:0] io_ddpath_rdata; // @[core.scala:36:7] CtlPath c ( // @[core.scala:39:18] .clock (clock), .reset (reset), .io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:36:7] .io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:36:7] .io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:36:7] .io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:36:7] .io_dmem_req_valid (io_dmem_req_valid_0), .io_dmem_req_bits_fcn (io_dmem_req_bits_fcn_0), .io_dmem_req_bits_typ (io_dmem_req_bits_typ_0), .io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:36:7] .io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:36:7] .io_dat_if_valid_resp (_d_io_dat_if_valid_resp), // @[core.scala:40:18] .io_dat_inst (_d_io_dat_inst), // @[core.scala:40:18] .io_dat_br_eq (_d_io_dat_br_eq), // @[core.scala:40:18] .io_dat_br_lt (_d_io_dat_br_lt), // @[core.scala:40:18] .io_dat_br_ltu (_d_io_dat_br_ltu), // @[core.scala:40:18] .io_dat_inst_misaligned (_d_io_dat_inst_misaligned), // @[core.scala:40:18] .io_dat_data_misaligned (_d_io_dat_data_misaligned), // @[core.scala:40:18] .io_dat_mem_store (_d_io_dat_mem_store), // @[core.scala:40:18] .io_dat_csr_eret (_d_io_dat_csr_eret), // @[core.scala:40:18] .io_dat_csr_interrupt (_d_io_dat_csr_interrupt), // @[core.scala:40:18] .io_ctl_stall (_c_io_ctl_stall), .io_ctl_if_kill (_c_io_ctl_if_kill), .io_ctl_pc_sel (_c_io_ctl_pc_sel), .io_ctl_op1_sel (_c_io_ctl_op1_sel), .io_ctl_op2_sel (_c_io_ctl_op2_sel), .io_ctl_alu_fun (_c_io_ctl_alu_fun), .io_ctl_wb_sel (_c_io_ctl_wb_sel), .io_ctl_rf_wen (_c_io_ctl_rf_wen), .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), .io_ctl_mem_val (_c_io_ctl_mem_val), .io_ctl_mem_fcn (_c_io_ctl_mem_fcn), .io_ctl_mem_typ (_c_io_ctl_mem_typ), .io_ctl_exception (_c_io_ctl_exception), .io_ctl_exception_cause (_c_io_ctl_exception_cause), .io_ctl_pc_sel_no_xept (_c_io_ctl_pc_sel_no_xept) ); // @[core.scala:39:18] DatPath d ( // @[core.scala:40:18] .clock (clock), .reset (reset), .io_ddpath_rdata (io_ddpath_rdata), .io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:36:7] .io_imem_req_valid (io_imem_req_valid_0), .io_imem_req_bits_addr (io_imem_req_bits_addr_0), .io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:36:7] .io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:36:7] .io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:36:7] .io_dmem_req_bits_addr (io_dmem_req_bits_addr_0), .io_dmem_req_bits_data (io_dmem_req_bits_data_0), .io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:36:7] .io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:36:7] .io_ctl_stall (_c_io_ctl_stall), // @[core.scala:39:18] .io_ctl_if_kill (_c_io_ctl_if_kill), // @[core.scala:39:18] .io_ctl_pc_sel (_c_io_ctl_pc_sel), // @[core.scala:39:18] .io_ctl_op1_sel (_c_io_ctl_op1_sel), // @[core.scala:39:18] .io_ctl_op2_sel (_c_io_ctl_op2_sel), // @[core.scala:39:18] .io_ctl_alu_fun (_c_io_ctl_alu_fun), // @[core.scala:39:18] .io_ctl_wb_sel (_c_io_ctl_wb_sel), // @[core.scala:39:18] .io_ctl_rf_wen (_c_io_ctl_rf_wen), // @[core.scala:39:18] .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), // @[core.scala:39:18] .io_ctl_mem_val (_c_io_ctl_mem_val), // @[core.scala:39:18] .io_ctl_mem_fcn (_c_io_ctl_mem_fcn), // @[core.scala:39:18] .io_ctl_mem_typ (_c_io_ctl_mem_typ), // @[core.scala:39:18] .io_ctl_exception (_c_io_ctl_exception), // @[core.scala:39:18] .io_ctl_exception_cause (_c_io_ctl_exception_cause), // @[core.scala:39:18] .io_ctl_pc_sel_no_xept (_c_io_ctl_pc_sel_no_xept), // @[core.scala:39:18] .io_dat_if_valid_resp (_d_io_dat_if_valid_resp), .io_dat_inst (_d_io_dat_inst), .io_dat_br_eq (_d_io_dat_br_eq), .io_dat_br_lt (_d_io_dat_br_lt), .io_dat_br_ltu (_d_io_dat_br_ltu), .io_dat_inst_misaligned (_d_io_dat_inst_misaligned), .io_dat_data_misaligned (_d_io_dat_data_misaligned), .io_dat_mem_store (_d_io_dat_mem_store), .io_dat_csr_eret (_d_io_dat_csr_eret), .io_dat_csr_interrupt (_d_io_dat_csr_interrupt), .io_interrupt_debug (io_interrupt_debug_0), // @[core.scala:36:7] .io_interrupt_mtip (io_interrupt_mtip_0), // @[core.scala:36:7] .io_interrupt_msip (io_interrupt_msip_0), // @[core.scala:36:7] .io_interrupt_meip (io_interrupt_meip_0), // @[core.scala:36:7] .io_hartid (io_hartid_0) // @[core.scala:36:7] ); // @[core.scala:40:18] assign io_imem_req_valid = io_imem_req_valid_0; // @[core.scala:36:7] assign io_imem_req_bits_addr = io_imem_req_bits_addr_0; // @[core.scala:36:7] assign io_dmem_req_valid = io_dmem_req_valid_0; // @[core.scala:36:7] assign io_dmem_req_bits_addr = io_dmem_req_bits_addr_0; // @[core.scala:36:7] assign io_dmem_req_bits_data = io_dmem_req_bits_data_0; // @[core.scala:36:7] assign io_dmem_req_bits_fcn = io_dmem_req_bits_fcn_0; // @[core.scala:36:7] assign io_dmem_req_bits_typ = io_dmem_req_bits_typ_0; // @[core.scala:36:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_67 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_67( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerControlRemapper_4 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<18>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn

module ReRoCCManagerControlRemapper_4( // @[Control.scala:30:9] input clock, // @[Control.scala:30:9] input reset, // @[Control.scala:30:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [17:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Control.scala:30:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Control.scala:30:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Control.scala:30:9] wire [17:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Control.scala:30:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Control.scala:30:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Control.scala:30:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Control.scala:30:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Control.scala:30:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Control.scala:30:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Control.scala:30:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Control.scala:30:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Control.scala:30:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Control.scala:30:9] wire auto_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire auto_out_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeIn_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_sink = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_denied = 1'h0; // @[Nodes.scala:27:25] wire nodeOut_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Nodes.scala:27:25] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Control.scala:30:9] wire [17:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Control.scala:30:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Control.scala:30:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Control.scala:30:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Control.scala:30:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_a_ready_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_in_d_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_in_d_bits_source_0; // @[Control.scala:30:9] wire [63:0] auto_in_d_bits_data_0; // @[Control.scala:30:9] wire auto_in_d_valid_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_param_0; // @[Control.scala:30:9] wire [2:0] auto_out_a_bits_size_0; // @[Control.scala:30:9] wire [6:0] auto_out_a_bits_source_0; // @[Control.scala:30:9] wire [11:0] auto_out_a_bits_address_0; // @[Control.scala:30:9] wire [7:0] auto_out_a_bits_mask_0; // @[Control.scala:30:9] wire [63:0] auto_out_a_bits_data_0; // @[Control.scala:30:9] wire auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] wire auto_out_a_valid_0; // @[Control.scala:30:9] wire auto_out_d_ready_0; // @[Control.scala:30:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Control.scala:30:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Control.scala:30:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Control.scala:30:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Control.scala:30:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Control.scala:30:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Control.scala:30:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Control.scala:30:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Control.scala:30:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Control.scala:30:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Control.scala:30:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Control.scala:30:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Control.scala:30:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Control.scala:30:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Control.scala:30:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Control.scala:30:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address[11:0]; // @[Control.scala:32:11] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[Control.scala:30:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Control.scala:30:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Control.scala:30:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Control.scala:30:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Control.scala:30:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Control.scala:30:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Control.scala:30:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Control.scala:30:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Control.scala:30:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Control.scala:30:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Control.scala:30:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Control.scala:30:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Control.scala:30:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Control.scala:30:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Control.scala:30:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_338( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_52 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_52 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_131 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulRecFN_52( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_52 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_131 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_507 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_251 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_507( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_251 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = and(_T_16, _T_24) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_25, UInt<1>(0h1), "") : assert_1 node _T_29 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_29 : node _T_30 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_31 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_32 = and(_T_30, _T_31) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_33 = shr(io.in.a.bits.source, 2) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = leq(UInt<1>(0h0), uncommonBits_1) node _T_36 = and(_T_34, _T_35) node _T_37 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_40 = or(_T_38, _T_39) node _T_41 = and(_T_32, _T_40) node _T_42 = or(UInt<1>(0h0), _T_41) node _T_43 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_44 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<14>(0h2000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<13>(0h1000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<18>(0h2f000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<27>(0h4000000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_48, _T_53) node _T_85 = or(_T_84, _T_58) node _T_86 = or(_T_85, _T_63) node _T_87 = or(_T_86, _T_68) node _T_88 = or(_T_87, _T_73) node _T_89 = or(_T_88, _T_78) node _T_90 = or(_T_89, _T_83) node _T_91 = and(_T_43, _T_90) node _T_92 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_95 = cvt(_T_94) node _T_96 = and(_T_95, asSInt(UInt<17>(0h10000))) node _T_97 = asSInt(_T_96) node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0))) node _T_99 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_100 = cvt(_T_99) node _T_101 = and(_T_100, asSInt(UInt<29>(0h10000000))) node _T_102 = asSInt(_T_101) node _T_103 = eq(_T_102, asSInt(UInt<1>(0h0))) node _T_104 = or(_T_98, _T_103) node _T_105 = and(_T_93, _T_104) node _T_106 = or(UInt<1>(0h0), _T_91) node _T_107 = or(_T_106, _T_105) node _T_108 = and(_T_42, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_108, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_2) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_117 connect _WIRE[1], _T_118 node _T_119 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_120 = mux(_WIRE[0], _T_119, UInt<1>(0h0)) node _T_121 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_122 = or(_T_120, _T_121) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_122 node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_125 = and(_T_123, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<14>(0h2000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<18>(0h2f000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<27>(0h4000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<29>(0h10000000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_131, _T_136) node _T_178 = or(_T_177, _T_141) node _T_179 = or(_T_178, _T_146) node _T_180 = or(_T_179, _T_151) node _T_181 = or(_T_180, _T_156) node _T_182 = or(_T_181, _T_161) node _T_183 = or(_T_182, _T_166) node _T_184 = or(_T_183, _T_171) node _T_185 = or(_T_184, _T_176) node _T_186 = and(_T_126, _T_185) node _T_187 = or(UInt<1>(0h0), _T_186) node _T_188 = and(_WIRE_1, _T_187) node _T_189 = asUInt(reset) node _T_190 = eq(_T_189, UInt<1>(0h0)) when _T_190 : node _T_191 = eq(_T_188, UInt<1>(0h0)) when _T_191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_188, UInt<1>(0h1), "") : assert_3 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(source_ok, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_195 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(_T_195, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_195, UInt<1>(0h1), "") : assert_5 node _T_199 = asUInt(reset) node _T_200 = eq(_T_199, UInt<1>(0h0)) when _T_200 : node _T_201 = eq(is_aligned, UInt<1>(0h0)) when _T_201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_202 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_202, UInt<1>(0h1), "") : assert_7 node _T_206 = not(io.in.a.bits.mask) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(_T_207, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_207, UInt<1>(0h1), "") : assert_8 node _T_211 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_211, UInt<1>(0h1), "") : assert_9 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_219 = shr(io.in.a.bits.source, 2) node _T_220 = eq(_T_219, UInt<1>(0h0)) node _T_221 = leq(UInt<1>(0h0), uncommonBits_3) node _T_222 = and(_T_220, _T_221) node _T_223 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_226 = or(_T_224, _T_225) node _T_227 = and(_T_218, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_230 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<14>(0h2000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<17>(0h10000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<18>(0h2f000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<13>(0h1000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<27>(0h4000000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<13>(0h1000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_234, _T_239) node _T_271 = or(_T_270, _T_244) node _T_272 = or(_T_271, _T_249) node _T_273 = or(_T_272, _T_254) node _T_274 = or(_T_273, _T_259) node _T_275 = or(_T_274, _T_264) node _T_276 = or(_T_275, _T_269) node _T_277 = and(_T_229, _T_276) node _T_278 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_279 = or(UInt<1>(0h0), _T_278) node _T_280 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_281 = cvt(_T_280) node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000))) node _T_283 = asSInt(_T_282) node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_286 = cvt(_T_285) node _T_287 = and(_T_286, asSInt(UInt<29>(0h10000000))) node _T_288 = asSInt(_T_287) node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) node _T_290 = or(_T_284, _T_289) node _T_291 = and(_T_279, _T_290) node _T_292 = or(UInt<1>(0h0), _T_277) node _T_293 = or(_T_292, _T_291) node _T_294 = and(_T_228, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_294, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_298 = shr(io.in.a.bits.source, 2) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = leq(UInt<1>(0h0), uncommonBits_4) node _T_301 = and(_T_299, _T_300) node _T_302 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<2>(0h3)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_303 connect _WIRE_2[1], _T_304 node _T_305 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_306 = mux(_WIRE_2[0], _T_305, UInt<1>(0h0)) node _T_307 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_308 = or(_T_306, _T_307) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<17>(0h10000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<27>(0h4000000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<13>(0h1000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_317, _T_322) node _T_364 = or(_T_363, _T_327) node _T_365 = or(_T_364, _T_332) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_342) node _T_368 = or(_T_367, _T_347) node _T_369 = or(_T_368, _T_352) node _T_370 = or(_T_369, _T_357) node _T_371 = or(_T_370, _T_362) node _T_372 = and(_T_312, _T_371) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = and(_WIRE_3, _T_373) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_374, UInt<1>(0h1), "") : assert_11 node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(source_ok, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_381 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_381, UInt<1>(0h1), "") : assert_13 node _T_385 = asUInt(reset) node _T_386 = eq(_T_385, UInt<1>(0h0)) when _T_386 : node _T_387 = eq(is_aligned, UInt<1>(0h0)) when _T_387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_388 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_388, UInt<1>(0h1), "") : assert_15 node _T_392 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_392, UInt<1>(0h1), "") : assert_16 node _T_396 = not(io.in.a.bits.mask) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_397, UInt<1>(0h1), "") : assert_17 node _T_401 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_401, UInt<1>(0h1), "") : assert_18 node _T_405 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_405 : node _T_406 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_407 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_408 = and(_T_406, _T_407) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_5) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_414 = and(_T_412, _T_413) node _T_415 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_416 = or(_T_414, _T_415) node _T_417 = and(_T_408, _T_416) node _T_418 = or(UInt<1>(0h0), _T_417) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_418, UInt<1>(0h1), "") : assert_19 node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_423 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_424 = and(_T_422, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = and(_T_425, _T_430) node _T_432 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_433 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_434 = and(_T_432, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<14>(0h2000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<17>(0h10000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<27>(0h4000000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<29>(0h10000000))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_440, _T_445) node _T_482 = or(_T_481, _T_450) node _T_483 = or(_T_482, _T_455) node _T_484 = or(_T_483, _T_460) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_470) node _T_487 = or(_T_486, _T_475) node _T_488 = or(_T_487, _T_480) node _T_489 = and(_T_435, _T_488) node _T_490 = or(UInt<1>(0h0), _T_431) node _T_491 = or(_T_490, _T_489) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_491, UInt<1>(0h1), "") : assert_20 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(source_ok, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(is_aligned, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_501 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_501, UInt<1>(0h1), "") : assert_23 node _T_505 = eq(io.in.a.bits.mask, mask) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_505, UInt<1>(0h1), "") : assert_24 node _T_509 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_509, UInt<1>(0h1), "") : assert_25 node _T_513 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_513 : node _T_514 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_515 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_517 = shr(io.in.a.bits.source, 2) node _T_518 = eq(_T_517, UInt<1>(0h0)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_6) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_524 = or(_T_522, _T_523) node _T_525 = and(_T_516, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_528 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_529 = and(_T_527, _T_528) node _T_530 = or(UInt<1>(0h0), _T_529) node _T_531 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = and(_T_530, _T_535) node _T_537 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_538 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_539 = and(_T_537, _T_538) node _T_540 = or(UInt<1>(0h0), _T_539) node _T_541 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<14>(0h2000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_547 = cvt(_T_546) node _T_548 = and(_T_547, asSInt(UInt<18>(0h2f000))) node _T_549 = asSInt(_T_548) node _T_550 = eq(_T_549, asSInt(UInt<1>(0h0))) node _T_551 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_557 = cvt(_T_556) node _T_558 = and(_T_557, asSInt(UInt<13>(0h1000))) node _T_559 = asSInt(_T_558) node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0))) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<27>(0h4000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<13>(0h1000))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<29>(0h10000000))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = or(_T_545, _T_550) node _T_582 = or(_T_581, _T_555) node _T_583 = or(_T_582, _T_560) node _T_584 = or(_T_583, _T_565) node _T_585 = or(_T_584, _T_570) node _T_586 = or(_T_585, _T_575) node _T_587 = or(_T_586, _T_580) node _T_588 = and(_T_540, _T_587) node _T_589 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_590 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_591 = cvt(_T_590) node _T_592 = and(_T_591, asSInt(UInt<17>(0h10000))) node _T_593 = asSInt(_T_592) node _T_594 = eq(_T_593, asSInt(UInt<1>(0h0))) node _T_595 = and(_T_589, _T_594) node _T_596 = or(UInt<1>(0h0), _T_536) node _T_597 = or(_T_596, _T_588) node _T_598 = or(_T_597, _T_595) node _T_599 = and(_T_526, _T_598) node _T_600 = asUInt(reset) node _T_601 = eq(_T_600, UInt<1>(0h0)) when _T_601 : node _T_602 = eq(_T_599, UInt<1>(0h0)) when _T_602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_599, UInt<1>(0h1), "") : assert_26 node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(source_ok, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(is_aligned, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_609 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_609, UInt<1>(0h1), "") : assert_29 node _T_613 = eq(io.in.a.bits.mask, mask) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_613, UInt<1>(0h1), "") : assert_30 node _T_617 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_617 : node _T_618 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_619 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h0)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_7) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_626 = and(_T_624, _T_625) node _T_627 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_628 = or(_T_626, _T_627) node _T_629 = and(_T_620, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_703, UInt<1>(0h1), "") : assert_31 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_713, UInt<1>(0h1), "") : assert_34 node _T_717 = not(mask) node _T_718 = and(io.in.a.bits.mask, _T_717) node _T_719 = eq(_T_718, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_719, UInt<1>(0h1), "") : assert_35 node _T_723 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_723 : node _T_724 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_725 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<1>(0h0)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_8) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_732 = and(_T_730, _T_731) node _T_733 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_734 = or(_T_732, _T_733) node _T_735 = and(_T_726, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<14>(0h2000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<18>(0h2f000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<17>(0h10000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<13>(0h1000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<27>(0h4000000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<13>(0h1000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<29>(0h10000000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = or(_T_745, _T_750) node _T_787 = or(_T_786, _T_755) node _T_788 = or(_T_787, _T_760) node _T_789 = or(_T_788, _T_765) node _T_790 = or(_T_789, _T_770) node _T_791 = or(_T_790, _T_775) node _T_792 = or(_T_791, _T_780) node _T_793 = or(_T_792, _T_785) node _T_794 = and(_T_740, _T_793) node _T_795 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_796 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = and(_T_795, _T_800) node _T_802 = or(UInt<1>(0h0), _T_794) node _T_803 = or(_T_802, _T_801) node _T_804 = and(_T_736, _T_803) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_804, UInt<1>(0h1), "") : assert_36 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(source_ok, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(is_aligned, UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_814 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_814, UInt<1>(0h1), "") : assert_39 node _T_818 = eq(io.in.a.bits.mask, mask) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_818, UInt<1>(0h1), "") : assert_40 node _T_822 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_822 : node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h0)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_9) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_833 = or(_T_831, _T_832) node _T_834 = and(_T_825, _T_833) node _T_835 = or(UInt<1>(0h0), _T_834) node _T_836 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_837 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _T_839 = or(UInt<1>(0h0), _T_838) node _T_840 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_841 = cvt(_T_840) node _T_842 = and(_T_841, asSInt(UInt<14>(0h2000))) node _T_843 = asSInt(_T_842) node _T_844 = eq(_T_843, asSInt(UInt<1>(0h0))) node _T_845 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<18>(0h2f000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_856 = cvt(_T_855) node _T_857 = and(_T_856, asSInt(UInt<17>(0h10000))) node _T_858 = asSInt(_T_857) node _T_859 = eq(_T_858, asSInt(UInt<1>(0h0))) node _T_860 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<13>(0h1000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<17>(0h10000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_871 = cvt(_T_870) node _T_872 = and(_T_871, asSInt(UInt<27>(0h4000000))) node _T_873 = asSInt(_T_872) node _T_874 = eq(_T_873, asSInt(UInt<1>(0h0))) node _T_875 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_876 = cvt(_T_875) node _T_877 = and(_T_876, asSInt(UInt<13>(0h1000))) node _T_878 = asSInt(_T_877) node _T_879 = eq(_T_878, asSInt(UInt<1>(0h0))) node _T_880 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_881 = cvt(_T_880) node _T_882 = and(_T_881, asSInt(UInt<29>(0h10000000))) node _T_883 = asSInt(_T_882) node _T_884 = eq(_T_883, asSInt(UInt<1>(0h0))) node _T_885 = or(_T_844, _T_849) node _T_886 = or(_T_885, _T_854) node _T_887 = or(_T_886, _T_859) node _T_888 = or(_T_887, _T_864) node _T_889 = or(_T_888, _T_869) node _T_890 = or(_T_889, _T_874) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_884) node _T_893 = and(_T_839, _T_892) node _T_894 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_895 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_896 = cvt(_T_895) node _T_897 = and(_T_896, asSInt(UInt<17>(0h10000))) node _T_898 = asSInt(_T_897) node _T_899 = eq(_T_898, asSInt(UInt<1>(0h0))) node _T_900 = and(_T_894, _T_899) node _T_901 = or(UInt<1>(0h0), _T_893) node _T_902 = or(_T_901, _T_900) node _T_903 = and(_T_835, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_903, UInt<1>(0h1), "") : assert_41 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_913 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_913, UInt<1>(0h1), "") : assert_44 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_917, UInt<1>(0h1), "") : assert_45 node _T_921 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_925 = shr(io.in.a.bits.source, 2) node _T_926 = eq(_T_925, UInt<1>(0h0)) node _T_927 = leq(UInt<1>(0h0), uncommonBits_10) node _T_928 = and(_T_926, _T_927) node _T_929 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_930 = and(_T_928, _T_929) node _T_931 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_932 = or(_T_930, _T_931) node _T_933 = and(_T_924, _T_932) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_936 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_937 = and(_T_935, _T_936) node _T_938 = or(UInt<1>(0h0), _T_937) node _T_939 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_940 = cvt(_T_939) node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000))) node _T_942 = asSInt(_T_941) node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0))) node _T_944 = and(_T_938, _T_943) node _T_945 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_947 = cvt(_T_946) node _T_948 = and(_T_947, asSInt(UInt<14>(0h2000))) node _T_949 = asSInt(_T_948) node _T_950 = eq(_T_949, asSInt(UInt<1>(0h0))) node _T_951 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_952 = cvt(_T_951) node _T_953 = and(_T_952, asSInt(UInt<17>(0h10000))) node _T_954 = asSInt(_T_953) node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0))) node _T_956 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_957 = cvt(_T_956) node _T_958 = and(_T_957, asSInt(UInt<18>(0h2f000))) node _T_959 = asSInt(_T_958) node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0))) node _T_961 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_962 = cvt(_T_961) node _T_963 = and(_T_962, asSInt(UInt<17>(0h10000))) node _T_964 = asSInt(_T_963) node _T_965 = eq(_T_964, asSInt(UInt<1>(0h0))) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_972 = cvt(_T_971) node _T_973 = and(_T_972, asSInt(UInt<27>(0h4000000))) node _T_974 = asSInt(_T_973) node _T_975 = eq(_T_974, asSInt(UInt<1>(0h0))) node _T_976 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_977 = cvt(_T_976) node _T_978 = and(_T_977, asSInt(UInt<13>(0h1000))) node _T_979 = asSInt(_T_978) node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0))) node _T_981 = or(_T_950, _T_955) node _T_982 = or(_T_981, _T_960) node _T_983 = or(_T_982, _T_965) node _T_984 = or(_T_983, _T_970) node _T_985 = or(_T_984, _T_975) node _T_986 = or(_T_985, _T_980) node _T_987 = and(_T_945, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h10000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_944) node _T_1005 = or(_T_1004, _T_987) node _T_1006 = or(_T_1005, _T_1003) node _T_1007 = and(_T_934, _T_1006) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_46 node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(is_aligned, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1017 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_49 node _T_1021 = eq(io.in.a.bits.mask, mask) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_50 node _T_1025 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1029 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.d.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h0)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = eq(io.in.d.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_12 connect _source_ok_WIRE_1[1], _source_ok_T_13 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1033 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1033 : node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(source_ok_1, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1037 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_54 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_55 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_56 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_57 node _T_1053 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(source_ok_1, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(sink_ok, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1060 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_60 node _T_1064 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_61 node _T_1068 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_62 node _T_1072 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_63 node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1077 = or(UInt<1>(0h1), _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_64 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(source_ok_1, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_67 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_68 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_69 node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1101 = or(_T_1100, io.in.d.bits.corrupt) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_70 node _T_1105 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1106 = or(UInt<1>(0h1), _T_1105) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_71 node _T_1110 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1110 : node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(source_ok_1, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1114 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_73 node _T_1118 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_74 node _T_1122 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1123 = or(UInt<1>(0h1), _T_1122) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_75 node _T_1127 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1127 : node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(source_ok_1, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1131 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_77 node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1136 = or(_T_1135, io.in.d.bits.corrupt) node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(_T_1136, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1136, UInt<1>(0h1), "") : assert_78 node _T_1140 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1141 = or(UInt<1>(0h1), _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_79 node _T_1145 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1145 : node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(source_ok_1, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1149 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_81 node _T_1153 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_82 node _T_1157 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1158 = or(UInt<1>(0h1), _T_1157) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1162 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1166 = shr(io.in.b.bits.source, 2) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) node _T_1168 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1169 = and(_T_1167, _T_1168) node _T_1170 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1174 = cvt(_T_1173) node _T_1175 = and(_T_1174, asSInt(UInt<1>(0h0))) node _T_1176 = asSInt(_T_1175) node _T_1177 = eq(_T_1176, asSInt(UInt<1>(0h0))) node _T_1178 = or(_T_1172, _T_1177) node _T_1179 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) node _T_1181 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1182 = cvt(_T_1181) node _T_1183 = and(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = asSInt(_T_1183) node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = or(_T_1180, _T_1185) node _T_1187 = and(_T_1178, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 node _legal_source_T_7 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_8 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_9 = or(_legal_source_T_7, _legal_source_T_8) wire _legal_source_WIRE_1 : UInt<2> connect _legal_source_WIRE_1, _legal_source_T_9 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1191 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1191 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1192 = shr(io.in.b.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = eq(io.in.b.bits.source, UInt<2>(0h3)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1197 connect _WIRE_4[1], _T_1198 node _T_1199 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1200 = mux(_WIRE_4[0], _T_1199, UInt<1>(0h0)) node _T_1201 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1202 = or(_T_1200, _T_1201) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1202 node _T_1203 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1204 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = or(UInt<1>(0h0), _T_1205) node _T_1207 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1208 = cvt(_T_1207) node _T_1209 = and(_T_1208, asSInt(UInt<14>(0h2000))) node _T_1210 = asSInt(_T_1209) node _T_1211 = eq(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<13>(0h1000))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1218 = cvt(_T_1217) node _T_1219 = and(_T_1218, asSInt(UInt<17>(0h10000))) node _T_1220 = asSInt(_T_1219) node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0))) node _T_1222 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<18>(0h2f000))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1228 = cvt(_T_1227) node _T_1229 = and(_T_1228, asSInt(UInt<17>(0h10000))) node _T_1230 = asSInt(_T_1229) node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0))) node _T_1232 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1233 = cvt(_T_1232) node _T_1234 = and(_T_1233, asSInt(UInt<13>(0h1000))) node _T_1235 = asSInt(_T_1234) node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1238 = cvt(_T_1237) node _T_1239 = and(_T_1238, asSInt(UInt<17>(0h10000))) node _T_1240 = asSInt(_T_1239) node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0))) node _T_1242 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<27>(0h4000000))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1248 = cvt(_T_1247) node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000))) node _T_1250 = asSInt(_T_1249) node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0))) node _T_1252 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1253 = cvt(_T_1252) node _T_1254 = and(_T_1253, asSInt(UInt<29>(0h10000000))) node _T_1255 = asSInt(_T_1254) node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = or(_T_1211, _T_1216) node _T_1258 = or(_T_1257, _T_1221) node _T_1259 = or(_T_1258, _T_1226) node _T_1260 = or(_T_1259, _T_1231) node _T_1261 = or(_T_1260, _T_1236) node _T_1262 = or(_T_1261, _T_1241) node _T_1263 = or(_T_1262, _T_1246) node _T_1264 = or(_T_1263, _T_1251) node _T_1265 = or(_T_1264, _T_1256) node _T_1266 = and(_T_1206, _T_1265) node _T_1267 = or(UInt<1>(0h0), _T_1266) node _T_1268 = and(_WIRE_5, _T_1267) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_86 node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(address_ok, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(legal_source, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1281 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_90 node _T_1285 = eq(io.in.b.bits.mask, mask_1) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_91 node _T_1289 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_92 node _T_1293 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1293 : node _T_1294 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1295 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1296 = and(_T_1294, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1299 = cvt(_T_1298) node _T_1300 = and(_T_1299, asSInt(UInt<14>(0h2000))) node _T_1301 = asSInt(_T_1300) node _T_1302 = eq(_T_1301, asSInt(UInt<1>(0h0))) node _T_1303 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1304 = cvt(_T_1303) node _T_1305 = and(_T_1304, asSInt(UInt<13>(0h1000))) node _T_1306 = asSInt(_T_1305) node _T_1307 = eq(_T_1306, asSInt(UInt<1>(0h0))) node _T_1308 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1309 = cvt(_T_1308) node _T_1310 = and(_T_1309, asSInt(UInt<17>(0h10000))) node _T_1311 = asSInt(_T_1310) node _T_1312 = eq(_T_1311, asSInt(UInt<1>(0h0))) node _T_1313 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1314 = cvt(_T_1313) node _T_1315 = and(_T_1314, asSInt(UInt<18>(0h2f000))) node _T_1316 = asSInt(_T_1315) node _T_1317 = eq(_T_1316, asSInt(UInt<1>(0h0))) node _T_1318 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1319 = cvt(_T_1318) node _T_1320 = and(_T_1319, asSInt(UInt<17>(0h10000))) node _T_1321 = asSInt(_T_1320) node _T_1322 = eq(_T_1321, asSInt(UInt<1>(0h0))) node _T_1323 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1324 = cvt(_T_1323) node _T_1325 = and(_T_1324, asSInt(UInt<13>(0h1000))) node _T_1326 = asSInt(_T_1325) node _T_1327 = eq(_T_1326, asSInt(UInt<1>(0h0))) node _T_1328 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1329 = cvt(_T_1328) node _T_1330 = and(_T_1329, asSInt(UInt<17>(0h10000))) node _T_1331 = asSInt(_T_1330) node _T_1332 = eq(_T_1331, asSInt(UInt<1>(0h0))) node _T_1333 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1334 = cvt(_T_1333) node _T_1335 = and(_T_1334, asSInt(UInt<27>(0h4000000))) node _T_1336 = asSInt(_T_1335) node _T_1337 = eq(_T_1336, asSInt(UInt<1>(0h0))) node _T_1338 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1339 = cvt(_T_1338) node _T_1340 = and(_T_1339, asSInt(UInt<13>(0h1000))) node _T_1341 = asSInt(_T_1340) node _T_1342 = eq(_T_1341, asSInt(UInt<1>(0h0))) node _T_1343 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<29>(0h10000000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = or(_T_1302, _T_1307) node _T_1349 = or(_T_1348, _T_1312) node _T_1350 = or(_T_1349, _T_1317) node _T_1351 = or(_T_1350, _T_1322) node _T_1352 = or(_T_1351, _T_1327) node _T_1353 = or(_T_1352, _T_1332) node _T_1354 = or(_T_1353, _T_1337) node _T_1355 = or(_T_1354, _T_1342) node _T_1356 = or(_T_1355, _T_1347) node _T_1357 = and(_T_1297, _T_1356) node _T_1358 = or(UInt<1>(0h0), _T_1357) node _T_1359 = and(UInt<1>(0h0), _T_1358) node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(_T_1359, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1359, UInt<1>(0h1), "") : assert_93 node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(address_ok, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(legal_source, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1372 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_97 node _T_1376 = eq(io.in.b.bits.mask, mask_1) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_98 node _T_1380 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_99 node _T_1384 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1384 : node _T_1385 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1386 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1390 = cvt(_T_1389) node _T_1391 = and(_T_1390, asSInt(UInt<14>(0h2000))) node _T_1392 = asSInt(_T_1391) node _T_1393 = eq(_T_1392, asSInt(UInt<1>(0h0))) node _T_1394 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1395 = cvt(_T_1394) node _T_1396 = and(_T_1395, asSInt(UInt<13>(0h1000))) node _T_1397 = asSInt(_T_1396) node _T_1398 = eq(_T_1397, asSInt(UInt<1>(0h0))) node _T_1399 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1400 = cvt(_T_1399) node _T_1401 = and(_T_1400, asSInt(UInt<17>(0h10000))) node _T_1402 = asSInt(_T_1401) node _T_1403 = eq(_T_1402, asSInt(UInt<1>(0h0))) node _T_1404 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1405 = cvt(_T_1404) node _T_1406 = and(_T_1405, asSInt(UInt<18>(0h2f000))) node _T_1407 = asSInt(_T_1406) node _T_1408 = eq(_T_1407, asSInt(UInt<1>(0h0))) node _T_1409 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1410 = cvt(_T_1409) node _T_1411 = and(_T_1410, asSInt(UInt<17>(0h10000))) node _T_1412 = asSInt(_T_1411) node _T_1413 = eq(_T_1412, asSInt(UInt<1>(0h0))) node _T_1414 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1415 = cvt(_T_1414) node _T_1416 = and(_T_1415, asSInt(UInt<13>(0h1000))) node _T_1417 = asSInt(_T_1416) node _T_1418 = eq(_T_1417, asSInt(UInt<1>(0h0))) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<27>(0h4000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<13>(0h1000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1435 = cvt(_T_1434) node _T_1436 = and(_T_1435, asSInt(UInt<29>(0h10000000))) node _T_1437 = asSInt(_T_1436) node _T_1438 = eq(_T_1437, asSInt(UInt<1>(0h0))) node _T_1439 = or(_T_1393, _T_1398) node _T_1440 = or(_T_1439, _T_1403) node _T_1441 = or(_T_1440, _T_1408) node _T_1442 = or(_T_1441, _T_1413) node _T_1443 = or(_T_1442, _T_1418) node _T_1444 = or(_T_1443, _T_1423) node _T_1445 = or(_T_1444, _T_1428) node _T_1446 = or(_T_1445, _T_1433) node _T_1447 = or(_T_1446, _T_1438) node _T_1448 = and(_T_1388, _T_1447) node _T_1449 = or(UInt<1>(0h0), _T_1448) node _T_1450 = and(UInt<1>(0h0), _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100 node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(address_ok, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(legal_source, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1463 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_104 node _T_1467 = eq(io.in.b.bits.mask, mask_1) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_105 node _T_1471 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1471 : node _T_1472 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1473 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1474 = and(_T_1472, _T_1473) node _T_1475 = or(UInt<1>(0h0), _T_1474) node _T_1476 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1477 = cvt(_T_1476) node _T_1478 = and(_T_1477, asSInt(UInt<14>(0h2000))) node _T_1479 = asSInt(_T_1478) node _T_1480 = eq(_T_1479, asSInt(UInt<1>(0h0))) node _T_1481 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1482 = cvt(_T_1481) node _T_1483 = and(_T_1482, asSInt(UInt<13>(0h1000))) node _T_1484 = asSInt(_T_1483) node _T_1485 = eq(_T_1484, asSInt(UInt<1>(0h0))) node _T_1486 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1487 = cvt(_T_1486) node _T_1488 = and(_T_1487, asSInt(UInt<17>(0h10000))) node _T_1489 = asSInt(_T_1488) node _T_1490 = eq(_T_1489, asSInt(UInt<1>(0h0))) node _T_1491 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1492 = cvt(_T_1491) node _T_1493 = and(_T_1492, asSInt(UInt<18>(0h2f000))) node _T_1494 = asSInt(_T_1493) node _T_1495 = eq(_T_1494, asSInt(UInt<1>(0h0))) node _T_1496 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1497 = cvt(_T_1496) node _T_1498 = and(_T_1497, asSInt(UInt<17>(0h10000))) node _T_1499 = asSInt(_T_1498) node _T_1500 = eq(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<13>(0h1000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<17>(0h10000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1512 = cvt(_T_1511) node _T_1513 = and(_T_1512, asSInt(UInt<27>(0h4000000))) node _T_1514 = asSInt(_T_1513) node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0))) node _T_1516 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1517 = cvt(_T_1516) node _T_1518 = and(_T_1517, asSInt(UInt<13>(0h1000))) node _T_1519 = asSInt(_T_1518) node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0))) node _T_1521 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<29>(0h10000000))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1480, _T_1485) node _T_1527 = or(_T_1526, _T_1490) node _T_1528 = or(_T_1527, _T_1495) node _T_1529 = or(_T_1528, _T_1500) node _T_1530 = or(_T_1529, _T_1505) node _T_1531 = or(_T_1530, _T_1510) node _T_1532 = or(_T_1531, _T_1515) node _T_1533 = or(_T_1532, _T_1520) node _T_1534 = or(_T_1533, _T_1525) node _T_1535 = and(_T_1475, _T_1534) node _T_1536 = or(UInt<1>(0h0), _T_1535) node _T_1537 = and(UInt<1>(0h0), _T_1536) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_106 node _T_1541 = asUInt(reset) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(address_ok, UInt<1>(0h0)) when _T_1543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(legal_source, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1550 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(_T_1550, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1550, UInt<1>(0h1), "") : assert_110 node _T_1554 = not(mask_1) node _T_1555 = and(io.in.b.bits.mask, _T_1554) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) node _T_1557 = asUInt(reset) node _T_1558 = eq(_T_1557, UInt<1>(0h0)) when _T_1558 : node _T_1559 = eq(_T_1556, UInt<1>(0h0)) when _T_1559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1556, UInt<1>(0h1), "") : assert_111 node _T_1560 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1560 : node _T_1561 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1562 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1566 = cvt(_T_1565) node _T_1567 = and(_T_1566, asSInt(UInt<14>(0h2000))) node _T_1568 = asSInt(_T_1567) node _T_1569 = eq(_T_1568, asSInt(UInt<1>(0h0))) node _T_1570 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<13>(0h1000))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h10000))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<18>(0h2f000))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1586 = cvt(_T_1585) node _T_1587 = and(_T_1586, asSInt(UInt<17>(0h10000))) node _T_1588 = asSInt(_T_1587) node _T_1589 = eq(_T_1588, asSInt(UInt<1>(0h0))) node _T_1590 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1591 = cvt(_T_1590) node _T_1592 = and(_T_1591, asSInt(UInt<13>(0h1000))) node _T_1593 = asSInt(_T_1592) node _T_1594 = eq(_T_1593, asSInt(UInt<1>(0h0))) node _T_1595 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1596 = cvt(_T_1595) node _T_1597 = and(_T_1596, asSInt(UInt<17>(0h10000))) node _T_1598 = asSInt(_T_1597) node _T_1599 = eq(_T_1598, asSInt(UInt<1>(0h0))) node _T_1600 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1601 = cvt(_T_1600) node _T_1602 = and(_T_1601, asSInt(UInt<27>(0h4000000))) node _T_1603 = asSInt(_T_1602) node _T_1604 = eq(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1606 = cvt(_T_1605) node _T_1607 = and(_T_1606, asSInt(UInt<13>(0h1000))) node _T_1608 = asSInt(_T_1607) node _T_1609 = eq(_T_1608, asSInt(UInt<1>(0h0))) node _T_1610 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1611 = cvt(_T_1610) node _T_1612 = and(_T_1611, asSInt(UInt<29>(0h10000000))) node _T_1613 = asSInt(_T_1612) node _T_1614 = eq(_T_1613, asSInt(UInt<1>(0h0))) node _T_1615 = or(_T_1569, _T_1574) node _T_1616 = or(_T_1615, _T_1579) node _T_1617 = or(_T_1616, _T_1584) node _T_1618 = or(_T_1617, _T_1589) node _T_1619 = or(_T_1618, _T_1594) node _T_1620 = or(_T_1619, _T_1599) node _T_1621 = or(_T_1620, _T_1604) node _T_1622 = or(_T_1621, _T_1609) node _T_1623 = or(_T_1622, _T_1614) node _T_1624 = and(_T_1564, _T_1623) node _T_1625 = or(UInt<1>(0h0), _T_1624) node _T_1626 = and(UInt<1>(0h0), _T_1625) node _T_1627 = asUInt(reset) node _T_1628 = eq(_T_1627, UInt<1>(0h0)) when _T_1628 : node _T_1629 = eq(_T_1626, UInt<1>(0h0)) when _T_1629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1626, UInt<1>(0h1), "") : assert_112 node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(address_ok, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(legal_source, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1639 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_116 node _T_1643 = eq(io.in.b.bits.mask, mask_1) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_117 node _T_1647 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1647 : node _T_1648 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1649 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1650 = and(_T_1648, _T_1649) node _T_1651 = or(UInt<1>(0h0), _T_1650) node _T_1652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1653 = cvt(_T_1652) node _T_1654 = and(_T_1653, asSInt(UInt<14>(0h2000))) node _T_1655 = asSInt(_T_1654) node _T_1656 = eq(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1658 = cvt(_T_1657) node _T_1659 = and(_T_1658, asSInt(UInt<13>(0h1000))) node _T_1660 = asSInt(_T_1659) node _T_1661 = eq(_T_1660, asSInt(UInt<1>(0h0))) node _T_1662 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1663 = cvt(_T_1662) node _T_1664 = and(_T_1663, asSInt(UInt<17>(0h10000))) node _T_1665 = asSInt(_T_1664) node _T_1666 = eq(_T_1665, asSInt(UInt<1>(0h0))) node _T_1667 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<18>(0h2f000))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1673 = cvt(_T_1672) node _T_1674 = and(_T_1673, asSInt(UInt<17>(0h10000))) node _T_1675 = asSInt(_T_1674) node _T_1676 = eq(_T_1675, asSInt(UInt<1>(0h0))) node _T_1677 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1678 = cvt(_T_1677) node _T_1679 = and(_T_1678, asSInt(UInt<13>(0h1000))) node _T_1680 = asSInt(_T_1679) node _T_1681 = eq(_T_1680, asSInt(UInt<1>(0h0))) node _T_1682 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1683 = cvt(_T_1682) node _T_1684 = and(_T_1683, asSInt(UInt<17>(0h10000))) node _T_1685 = asSInt(_T_1684) node _T_1686 = eq(_T_1685, asSInt(UInt<1>(0h0))) node _T_1687 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1688 = cvt(_T_1687) node _T_1689 = and(_T_1688, asSInt(UInt<27>(0h4000000))) node _T_1690 = asSInt(_T_1689) node _T_1691 = eq(_T_1690, asSInt(UInt<1>(0h0))) node _T_1692 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1693 = cvt(_T_1692) node _T_1694 = and(_T_1693, asSInt(UInt<13>(0h1000))) node _T_1695 = asSInt(_T_1694) node _T_1696 = eq(_T_1695, asSInt(UInt<1>(0h0))) node _T_1697 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1698 = cvt(_T_1697) node _T_1699 = and(_T_1698, asSInt(UInt<29>(0h10000000))) node _T_1700 = asSInt(_T_1699) node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = or(_T_1656, _T_1661) node _T_1703 = or(_T_1702, _T_1666) node _T_1704 = or(_T_1703, _T_1671) node _T_1705 = or(_T_1704, _T_1676) node _T_1706 = or(_T_1705, _T_1681) node _T_1707 = or(_T_1706, _T_1686) node _T_1708 = or(_T_1707, _T_1691) node _T_1709 = or(_T_1708, _T_1696) node _T_1710 = or(_T_1709, _T_1701) node _T_1711 = and(_T_1651, _T_1710) node _T_1712 = or(UInt<1>(0h0), _T_1711) node _T_1713 = and(UInt<1>(0h0), _T_1712) node _T_1714 = asUInt(reset) node _T_1715 = eq(_T_1714, UInt<1>(0h0)) when _T_1715 : node _T_1716 = eq(_T_1713, UInt<1>(0h0)) when _T_1716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1713, UInt<1>(0h1), "") : assert_118 node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(address_ok, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1720 = asUInt(reset) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) when _T_1721 : node _T_1722 = eq(legal_source, UInt<1>(0h0)) when _T_1722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1726 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_122 node _T_1730 = eq(io.in.b.bits.mask, mask_1) node _T_1731 = asUInt(reset) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) when _T_1732 : node _T_1733 = eq(_T_1730, UInt<1>(0h0)) when _T_1733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1730, UInt<1>(0h1), "") : assert_123 node _T_1734 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1734 : node _T_1735 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1736 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1737 = and(_T_1735, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1740 = cvt(_T_1739) node _T_1741 = and(_T_1740, asSInt(UInt<14>(0h2000))) node _T_1742 = asSInt(_T_1741) node _T_1743 = eq(_T_1742, asSInt(UInt<1>(0h0))) node _T_1744 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<13>(0h1000))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1750 = cvt(_T_1749) node _T_1751 = and(_T_1750, asSInt(UInt<17>(0h10000))) node _T_1752 = asSInt(_T_1751) node _T_1753 = eq(_T_1752, asSInt(UInt<1>(0h0))) node _T_1754 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<18>(0h2f000))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1760 = cvt(_T_1759) node _T_1761 = and(_T_1760, asSInt(UInt<17>(0h10000))) node _T_1762 = asSInt(_T_1761) node _T_1763 = eq(_T_1762, asSInt(UInt<1>(0h0))) node _T_1764 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1765 = cvt(_T_1764) node _T_1766 = and(_T_1765, asSInt(UInt<13>(0h1000))) node _T_1767 = asSInt(_T_1766) node _T_1768 = eq(_T_1767, asSInt(UInt<1>(0h0))) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h10000))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<27>(0h4000000))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1780 = cvt(_T_1779) node _T_1781 = and(_T_1780, asSInt(UInt<13>(0h1000))) node _T_1782 = asSInt(_T_1781) node _T_1783 = eq(_T_1782, asSInt(UInt<1>(0h0))) node _T_1784 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1785 = cvt(_T_1784) node _T_1786 = and(_T_1785, asSInt(UInt<29>(0h10000000))) node _T_1787 = asSInt(_T_1786) node _T_1788 = eq(_T_1787, asSInt(UInt<1>(0h0))) node _T_1789 = or(_T_1743, _T_1748) node _T_1790 = or(_T_1789, _T_1753) node _T_1791 = or(_T_1790, _T_1758) node _T_1792 = or(_T_1791, _T_1763) node _T_1793 = or(_T_1792, _T_1768) node _T_1794 = or(_T_1793, _T_1773) node _T_1795 = or(_T_1794, _T_1778) node _T_1796 = or(_T_1795, _T_1783) node _T_1797 = or(_T_1796, _T_1788) node _T_1798 = and(_T_1738, _T_1797) node _T_1799 = or(UInt<1>(0h0), _T_1798) node _T_1800 = and(UInt<1>(0h0), _T_1799) node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(_T_1800, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1800, UInt<1>(0h1), "") : assert_124 node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(address_ok, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1807 = asUInt(reset) node _T_1808 = eq(_T_1807, UInt<1>(0h0)) when _T_1808 : node _T_1809 = eq(legal_source, UInt<1>(0h0)) when _T_1809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1813 = eq(io.in.b.bits.mask, mask_1) node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(_T_1813, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1813, UInt<1>(0h1), "") : assert_128 node _T_1817 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1818 = asUInt(reset) node _T_1819 = eq(_T_1818, UInt<1>(0h0)) when _T_1819 : node _T_1820 = eq(_T_1817, UInt<1>(0h0)) when _T_1820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1817, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1821 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1822 = asUInt(reset) node _T_1823 = eq(_T_1822, UInt<1>(0h0)) when _T_1823 : node _T_1824 = eq(_T_1821, UInt<1>(0h0)) when _T_1824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1821, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_14 = shr(io.in.c.bits.source, 2) node _source_ok_T_15 = eq(_source_ok_T_14, UInt<1>(0h0)) node _source_ok_T_16 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_T_18 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_19 = and(_source_ok_T_17, _source_ok_T_18) node _source_ok_T_20 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_19 connect _source_ok_WIRE_2[1], _source_ok_T_20 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1825 = shr(io.in.c.bits.source, 2) node _T_1826 = eq(_T_1825, UInt<1>(0h0)) node _T_1827 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1828 = and(_T_1826, _T_1827) node _T_1829 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1830 = and(_T_1828, _T_1829) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) node _T_1832 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = or(_T_1831, _T_1836) node _T_1838 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1839 = eq(_T_1838, UInt<1>(0h0)) node _T_1840 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = or(_T_1839, _T_1844) node _T_1846 = and(_T_1837, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_131 node _T_1850 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1850 : node _T_1851 = asUInt(reset) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) when _T_1852 : node _T_1853 = eq(address_ok_1, UInt<1>(0h0)) when _T_1853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(source_ok_2, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1857 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_134 node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1864 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_136 node _T_1868 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_137 node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1872 : node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(address_ok_1, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_2, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1879 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_140 node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1886 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1887 = asUInt(reset) node _T_1888 = eq(_T_1887, UInt<1>(0h0)) when _T_1888 : node _T_1889 = eq(_T_1886, UInt<1>(0h0)) when _T_1889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1886, UInt<1>(0h1), "") : assert_142 node _T_1890 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1890 : node _T_1891 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1892 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1893 = and(_T_1891, _T_1892) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1894 = shr(io.in.c.bits.source, 2) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1897 = and(_T_1895, _T_1896) node _T_1898 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1899 = and(_T_1897, _T_1898) node _T_1900 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1901 = or(_T_1899, _T_1900) node _T_1902 = and(_T_1893, _T_1901) node _T_1903 = or(UInt<1>(0h0), _T_1902) node _T_1904 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1905 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1906 = cvt(_T_1905) node _T_1907 = and(_T_1906, asSInt(UInt<14>(0h2000))) node _T_1908 = asSInt(_T_1907) node _T_1909 = eq(_T_1908, asSInt(UInt<1>(0h0))) node _T_1910 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1911 = cvt(_T_1910) node _T_1912 = and(_T_1911, asSInt(UInt<13>(0h1000))) node _T_1913 = asSInt(_T_1912) node _T_1914 = eq(_T_1913, asSInt(UInt<1>(0h0))) node _T_1915 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1916 = cvt(_T_1915) node _T_1917 = and(_T_1916, asSInt(UInt<17>(0h10000))) node _T_1918 = asSInt(_T_1917) node _T_1919 = eq(_T_1918, asSInt(UInt<1>(0h0))) node _T_1920 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1921 = cvt(_T_1920) node _T_1922 = and(_T_1921, asSInt(UInt<18>(0h2f000))) node _T_1923 = asSInt(_T_1922) node _T_1924 = eq(_T_1923, asSInt(UInt<1>(0h0))) node _T_1925 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1926 = cvt(_T_1925) node _T_1927 = and(_T_1926, asSInt(UInt<17>(0h10000))) node _T_1928 = asSInt(_T_1927) node _T_1929 = eq(_T_1928, asSInt(UInt<1>(0h0))) node _T_1930 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1931 = cvt(_T_1930) node _T_1932 = and(_T_1931, asSInt(UInt<13>(0h1000))) node _T_1933 = asSInt(_T_1932) node _T_1934 = eq(_T_1933, asSInt(UInt<1>(0h0))) node _T_1935 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1936 = cvt(_T_1935) node _T_1937 = and(_T_1936, asSInt(UInt<27>(0h4000000))) node _T_1938 = asSInt(_T_1937) node _T_1939 = eq(_T_1938, asSInt(UInt<1>(0h0))) node _T_1940 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1941 = cvt(_T_1940) node _T_1942 = and(_T_1941, asSInt(UInt<13>(0h1000))) node _T_1943 = asSInt(_T_1942) node _T_1944 = eq(_T_1943, asSInt(UInt<1>(0h0))) node _T_1945 = or(_T_1909, _T_1914) node _T_1946 = or(_T_1945, _T_1919) node _T_1947 = or(_T_1946, _T_1924) node _T_1948 = or(_T_1947, _T_1929) node _T_1949 = or(_T_1948, _T_1934) node _T_1950 = or(_T_1949, _T_1939) node _T_1951 = or(_T_1950, _T_1944) node _T_1952 = and(_T_1904, _T_1951) node _T_1953 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1954 = or(UInt<1>(0h0), _T_1953) node _T_1955 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1956 = cvt(_T_1955) node _T_1957 = and(_T_1956, asSInt(UInt<17>(0h10000))) node _T_1958 = asSInt(_T_1957) node _T_1959 = eq(_T_1958, asSInt(UInt<1>(0h0))) node _T_1960 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1961 = cvt(_T_1960) node _T_1962 = and(_T_1961, asSInt(UInt<29>(0h10000000))) node _T_1963 = asSInt(_T_1962) node _T_1964 = eq(_T_1963, asSInt(UInt<1>(0h0))) node _T_1965 = or(_T_1959, _T_1964) node _T_1966 = and(_T_1954, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1952) node _T_1968 = or(_T_1967, _T_1966) node _T_1969 = and(_T_1903, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_1973 = shr(io.in.c.bits.source, 2) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) node _T_1975 = leq(UInt<1>(0h0), uncommonBits_15) node _T_1976 = and(_T_1974, _T_1975) node _T_1977 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_1978 = and(_T_1976, _T_1977) node _T_1979 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1978 connect _WIRE_6[1], _T_1979 node _T_1980 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1981 = mux(_WIRE_6[0], _T_1980, UInt<1>(0h0)) node _T_1982 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1983 = or(_T_1981, _T_1982) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1983 node _T_1984 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1985 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1986 = and(_T_1984, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1989 = cvt(_T_1988) node _T_1990 = and(_T_1989, asSInt(UInt<14>(0h2000))) node _T_1991 = asSInt(_T_1990) node _T_1992 = eq(_T_1991, asSInt(UInt<1>(0h0))) node _T_1993 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1994 = cvt(_T_1993) node _T_1995 = and(_T_1994, asSInt(UInt<13>(0h1000))) node _T_1996 = asSInt(_T_1995) node _T_1997 = eq(_T_1996, asSInt(UInt<1>(0h0))) node _T_1998 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1999 = cvt(_T_1998) node _T_2000 = and(_T_1999, asSInt(UInt<17>(0h10000))) node _T_2001 = asSInt(_T_2000) node _T_2002 = eq(_T_2001, asSInt(UInt<1>(0h0))) node _T_2003 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2004 = cvt(_T_2003) node _T_2005 = and(_T_2004, asSInt(UInt<18>(0h2f000))) node _T_2006 = asSInt(_T_2005) node _T_2007 = eq(_T_2006, asSInt(UInt<1>(0h0))) node _T_2008 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2009 = cvt(_T_2008) node _T_2010 = and(_T_2009, asSInt(UInt<17>(0h10000))) node _T_2011 = asSInt(_T_2010) node _T_2012 = eq(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2014 = cvt(_T_2013) node _T_2015 = and(_T_2014, asSInt(UInt<13>(0h1000))) node _T_2016 = asSInt(_T_2015) node _T_2017 = eq(_T_2016, asSInt(UInt<1>(0h0))) node _T_2018 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2019 = cvt(_T_2018) node _T_2020 = and(_T_2019, asSInt(UInt<17>(0h10000))) node _T_2021 = asSInt(_T_2020) node _T_2022 = eq(_T_2021, asSInt(UInt<1>(0h0))) node _T_2023 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<27>(0h4000000))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2029 = cvt(_T_2028) node _T_2030 = and(_T_2029, asSInt(UInt<13>(0h1000))) node _T_2031 = asSInt(_T_2030) node _T_2032 = eq(_T_2031, asSInt(UInt<1>(0h0))) node _T_2033 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2034 = cvt(_T_2033) node _T_2035 = and(_T_2034, asSInt(UInt<29>(0h10000000))) node _T_2036 = asSInt(_T_2035) node _T_2037 = eq(_T_2036, asSInt(UInt<1>(0h0))) node _T_2038 = or(_T_1992, _T_1997) node _T_2039 = or(_T_2038, _T_2002) node _T_2040 = or(_T_2039, _T_2007) node _T_2041 = or(_T_2040, _T_2012) node _T_2042 = or(_T_2041, _T_2017) node _T_2043 = or(_T_2042, _T_2022) node _T_2044 = or(_T_2043, _T_2027) node _T_2045 = or(_T_2044, _T_2032) node _T_2046 = or(_T_2045, _T_2037) node _T_2047 = and(_T_1987, _T_2046) node _T_2048 = or(UInt<1>(0h0), _T_2047) node _T_2049 = and(_WIRE_7, _T_2048) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_144 node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(source_ok_2, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2056 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_146 node _T_2060 = asUInt(reset) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) when _T_2061 : node _T_2062 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2063 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2064 = asUInt(reset) node _T_2065 = eq(_T_2064, UInt<1>(0h0)) when _T_2065 : node _T_2066 = eq(_T_2063, UInt<1>(0h0)) when _T_2066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2063, UInt<1>(0h1), "") : assert_148 node _T_2067 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(_T_2067, UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2067, UInt<1>(0h1), "") : assert_149 node _T_2071 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2071 : node _T_2072 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2073 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2074 = and(_T_2072, _T_2073) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2075 = shr(io.in.c.bits.source, 2) node _T_2076 = eq(_T_2075, UInt<1>(0h0)) node _T_2077 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2078 = and(_T_2076, _T_2077) node _T_2079 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2082 = or(_T_2080, _T_2081) node _T_2083 = and(_T_2074, _T_2082) node _T_2084 = or(UInt<1>(0h0), _T_2083) node _T_2085 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<14>(0h2000))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2092 = cvt(_T_2091) node _T_2093 = and(_T_2092, asSInt(UInt<13>(0h1000))) node _T_2094 = asSInt(_T_2093) node _T_2095 = eq(_T_2094, asSInt(UInt<1>(0h0))) node _T_2096 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2097 = cvt(_T_2096) node _T_2098 = and(_T_2097, asSInt(UInt<17>(0h10000))) node _T_2099 = asSInt(_T_2098) node _T_2100 = eq(_T_2099, asSInt(UInt<1>(0h0))) node _T_2101 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2102 = cvt(_T_2101) node _T_2103 = and(_T_2102, asSInt(UInt<18>(0h2f000))) node _T_2104 = asSInt(_T_2103) node _T_2105 = eq(_T_2104, asSInt(UInt<1>(0h0))) node _T_2106 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2107 = cvt(_T_2106) node _T_2108 = and(_T_2107, asSInt(UInt<17>(0h10000))) node _T_2109 = asSInt(_T_2108) node _T_2110 = eq(_T_2109, asSInt(UInt<1>(0h0))) node _T_2111 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2112 = cvt(_T_2111) node _T_2113 = and(_T_2112, asSInt(UInt<13>(0h1000))) node _T_2114 = asSInt(_T_2113) node _T_2115 = eq(_T_2114, asSInt(UInt<1>(0h0))) node _T_2116 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2117 = cvt(_T_2116) node _T_2118 = and(_T_2117, asSInt(UInt<27>(0h4000000))) node _T_2119 = asSInt(_T_2118) node _T_2120 = eq(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2122 = cvt(_T_2121) node _T_2123 = and(_T_2122, asSInt(UInt<13>(0h1000))) node _T_2124 = asSInt(_T_2123) node _T_2125 = eq(_T_2124, asSInt(UInt<1>(0h0))) node _T_2126 = or(_T_2090, _T_2095) node _T_2127 = or(_T_2126, _T_2100) node _T_2128 = or(_T_2127, _T_2105) node _T_2129 = or(_T_2128, _T_2110) node _T_2130 = or(_T_2129, _T_2115) node _T_2131 = or(_T_2130, _T_2120) node _T_2132 = or(_T_2131, _T_2125) node _T_2133 = and(_T_2085, _T_2132) node _T_2134 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2135 = or(UInt<1>(0h0), _T_2134) node _T_2136 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2137 = cvt(_T_2136) node _T_2138 = and(_T_2137, asSInt(UInt<17>(0h10000))) node _T_2139 = asSInt(_T_2138) node _T_2140 = eq(_T_2139, asSInt(UInt<1>(0h0))) node _T_2141 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2142 = cvt(_T_2141) node _T_2143 = and(_T_2142, asSInt(UInt<29>(0h10000000))) node _T_2144 = asSInt(_T_2143) node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0))) node _T_2146 = or(_T_2140, _T_2145) node _T_2147 = and(_T_2135, _T_2146) node _T_2148 = or(UInt<1>(0h0), _T_2133) node _T_2149 = or(_T_2148, _T_2147) node _T_2150 = and(_T_2084, _T_2149) node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(_T_2150, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2150, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2154 = shr(io.in.c.bits.source, 2) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2157 = and(_T_2155, _T_2156) node _T_2158 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2159 = and(_T_2157, _T_2158) node _T_2160 = eq(io.in.c.bits.source, UInt<2>(0h3)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2159 connect _WIRE_8[1], _T_2160 node _T_2161 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2162 = mux(_WIRE_8[0], _T_2161, UInt<1>(0h0)) node _T_2163 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2164 = or(_T_2162, _T_2163) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2164 node _T_2165 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2166 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2167 = and(_T_2165, _T_2166) node _T_2168 = or(UInt<1>(0h0), _T_2167) node _T_2169 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2170 = cvt(_T_2169) node _T_2171 = and(_T_2170, asSInt(UInt<14>(0h2000))) node _T_2172 = asSInt(_T_2171) node _T_2173 = eq(_T_2172, asSInt(UInt<1>(0h0))) node _T_2174 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<13>(0h1000))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2180 = cvt(_T_2179) node _T_2181 = and(_T_2180, asSInt(UInt<17>(0h10000))) node _T_2182 = asSInt(_T_2181) node _T_2183 = eq(_T_2182, asSInt(UInt<1>(0h0))) node _T_2184 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2185 = cvt(_T_2184) node _T_2186 = and(_T_2185, asSInt(UInt<18>(0h2f000))) node _T_2187 = asSInt(_T_2186) node _T_2188 = eq(_T_2187, asSInt(UInt<1>(0h0))) node _T_2189 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2190 = cvt(_T_2189) node _T_2191 = and(_T_2190, asSInt(UInt<17>(0h10000))) node _T_2192 = asSInt(_T_2191) node _T_2193 = eq(_T_2192, asSInt(UInt<1>(0h0))) node _T_2194 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2195 = cvt(_T_2194) node _T_2196 = and(_T_2195, asSInt(UInt<13>(0h1000))) node _T_2197 = asSInt(_T_2196) node _T_2198 = eq(_T_2197, asSInt(UInt<1>(0h0))) node _T_2199 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2200 = cvt(_T_2199) node _T_2201 = and(_T_2200, asSInt(UInt<17>(0h10000))) node _T_2202 = asSInt(_T_2201) node _T_2203 = eq(_T_2202, asSInt(UInt<1>(0h0))) node _T_2204 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2205 = cvt(_T_2204) node _T_2206 = and(_T_2205, asSInt(UInt<27>(0h4000000))) node _T_2207 = asSInt(_T_2206) node _T_2208 = eq(_T_2207, asSInt(UInt<1>(0h0))) node _T_2209 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2210 = cvt(_T_2209) node _T_2211 = and(_T_2210, asSInt(UInt<13>(0h1000))) node _T_2212 = asSInt(_T_2211) node _T_2213 = eq(_T_2212, asSInt(UInt<1>(0h0))) node _T_2214 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2215 = cvt(_T_2214) node _T_2216 = and(_T_2215, asSInt(UInt<29>(0h10000000))) node _T_2217 = asSInt(_T_2216) node _T_2218 = eq(_T_2217, asSInt(UInt<1>(0h0))) node _T_2219 = or(_T_2173, _T_2178) node _T_2220 = or(_T_2219, _T_2183) node _T_2221 = or(_T_2220, _T_2188) node _T_2222 = or(_T_2221, _T_2193) node _T_2223 = or(_T_2222, _T_2198) node _T_2224 = or(_T_2223, _T_2203) node _T_2225 = or(_T_2224, _T_2208) node _T_2226 = or(_T_2225, _T_2213) node _T_2227 = or(_T_2226, _T_2218) node _T_2228 = and(_T_2168, _T_2227) node _T_2229 = or(UInt<1>(0h0), _T_2228) node _T_2230 = and(_WIRE_9, _T_2229) node _T_2231 = asUInt(reset) node _T_2232 = eq(_T_2231, UInt<1>(0h0)) when _T_2232 : node _T_2233 = eq(_T_2230, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2230, UInt<1>(0h1), "") : assert_151 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(source_ok_2, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2237 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_153 node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2244 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(_T_2244, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2244, UInt<1>(0h1), "") : assert_155 node _T_2248 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2248 : node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(address_ok_1, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(source_ok_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2255 = asUInt(reset) node _T_2256 = eq(_T_2255, UInt<1>(0h0)) when _T_2256 : node _T_2257 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2258 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_159 node _T_2262 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_160 node _T_2266 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2266 : node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(address_ok_1, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(source_ok_2, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2273 = asUInt(reset) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2276 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_164 node _T_2280 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2280 : node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(address_ok_1, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : node _T_2286 = eq(source_ok_2, UInt<1>(0h0)) when _T_2286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2290 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_168 node _T_2294 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2301 = eq(a_first, UInt<1>(0h0)) node _T_2302 = and(io.in.a.valid, _T_2301) when _T_2302 : node _T_2303 = eq(io.in.a.bits.opcode, opcode) node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : node _T_2306 = eq(_T_2303, UInt<1>(0h0)) when _T_2306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2303, UInt<1>(0h1), "") : assert_171 node _T_2307 = eq(io.in.a.bits.param, param) node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : node _T_2310 = eq(_T_2307, UInt<1>(0h0)) when _T_2310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2307, UInt<1>(0h1), "") : assert_172 node _T_2311 = eq(io.in.a.bits.size, size) node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : node _T_2314 = eq(_T_2311, UInt<1>(0h0)) when _T_2314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2311, UInt<1>(0h1), "") : assert_173 node _T_2315 = eq(io.in.a.bits.source, source) node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : node _T_2318 = eq(_T_2315, UInt<1>(0h0)) when _T_2318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2315, UInt<1>(0h1), "") : assert_174 node _T_2319 = eq(io.in.a.bits.address, address) node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : node _T_2322 = eq(_T_2319, UInt<1>(0h0)) when _T_2322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2319, UInt<1>(0h1), "") : assert_175 node _T_2323 = and(io.in.a.ready, io.in.a.valid) node _T_2324 = and(_T_2323, a_first) when _T_2324 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2325 = eq(d_first, UInt<1>(0h0)) node _T_2326 = and(io.in.d.valid, _T_2325) when _T_2326 : node _T_2327 = eq(io.in.d.bits.opcode, opcode_1) node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : node _T_2330 = eq(_T_2327, UInt<1>(0h0)) when _T_2330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2327, UInt<1>(0h1), "") : assert_176 node _T_2331 = eq(io.in.d.bits.param, param_1) node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(_T_2331, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2331, UInt<1>(0h1), "") : assert_177 node _T_2335 = eq(io.in.d.bits.size, size_1) node _T_2336 = asUInt(reset) node _T_2337 = eq(_T_2336, UInt<1>(0h0)) when _T_2337 : node _T_2338 = eq(_T_2335, UInt<1>(0h0)) when _T_2338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2335, UInt<1>(0h1), "") : assert_178 node _T_2339 = eq(io.in.d.bits.source, source_1) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_179 node _T_2343 = eq(io.in.d.bits.sink, sink) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_180 node _T_2347 = eq(io.in.d.bits.denied, denied) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_181 node _T_2351 = and(io.in.d.ready, io.in.d.valid) node _T_2352 = and(_T_2351, d_first) when _T_2352 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2353 = eq(b_first, UInt<1>(0h0)) node _T_2354 = and(io.in.b.valid, _T_2353) when _T_2354 : node _T_2355 = eq(io.in.b.bits.opcode, opcode_2) node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(_T_2355, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2355, UInt<1>(0h1), "") : assert_182 node _T_2359 = eq(io.in.b.bits.param, param_2) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(_T_2359, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2359, UInt<1>(0h1), "") : assert_183 node _T_2363 = eq(io.in.b.bits.size, size_2) node _T_2364 = asUInt(reset) node _T_2365 = eq(_T_2364, UInt<1>(0h0)) when _T_2365 : node _T_2366 = eq(_T_2363, UInt<1>(0h0)) when _T_2366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2363, UInt<1>(0h1), "") : assert_184 node _T_2367 = eq(io.in.b.bits.source, source_2) node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(_T_2367, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2367, UInt<1>(0h1), "") : assert_185 node _T_2371 = eq(io.in.b.bits.address, address_1) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_186 node _T_2375 = and(io.in.b.ready, io.in.b.valid) node _T_2376 = and(_T_2375, b_first) when _T_2376 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2377 = eq(c_first, UInt<1>(0h0)) node _T_2378 = and(io.in.c.valid, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.c.bits.opcode, opcode_3) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_187 node _T_2383 = eq(io.in.c.bits.param, param_3) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_188 node _T_2387 = eq(io.in.c.bits.size, size_3) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_189 node _T_2391 = eq(io.in.c.bits.source, source_3) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_190 node _T_2395 = eq(io.in.c.bits.address, address_2) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_191 node _T_2399 = and(io.in.c.ready, io.in.c.valid) node _T_2400 = and(_T_2399, c_first) when _T_2400 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2401 = and(io.in.a.valid, a_first_1) node _T_2402 = and(_T_2401, UInt<1>(0h1)) when _T_2402 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2403 = and(io.in.a.ready, io.in.a.valid) node _T_2404 = and(_T_2403, a_first_1) node _T_2405 = and(_T_2404, UInt<1>(0h1)) when _T_2405 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2406 = dshr(inflight, io.in.a.bits.source) node _T_2407 = bits(_T_2406, 0, 0) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) node _T_2409 = asUInt(reset) node _T_2410 = eq(_T_2409, UInt<1>(0h0)) when _T_2410 : node _T_2411 = eq(_T_2408, UInt<1>(0h0)) when _T_2411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2408, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2412 = and(io.in.d.valid, d_first_1) node _T_2413 = and(_T_2412, UInt<1>(0h1)) node _T_2414 = eq(d_release_ack, UInt<1>(0h0)) node _T_2415 = and(_T_2413, _T_2414) when _T_2415 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2416 = and(io.in.d.ready, io.in.d.valid) node _T_2417 = and(_T_2416, d_first_1) node _T_2418 = and(_T_2417, UInt<1>(0h1)) node _T_2419 = eq(d_release_ack, UInt<1>(0h0)) node _T_2420 = and(_T_2418, _T_2419) when _T_2420 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2421 = and(io.in.d.valid, d_first_1) node _T_2422 = and(_T_2421, UInt<1>(0h1)) node _T_2423 = eq(d_release_ack, UInt<1>(0h0)) node _T_2424 = and(_T_2422, _T_2423) when _T_2424 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2425 = dshr(inflight, io.in.d.bits.source) node _T_2426 = bits(_T_2425, 0, 0) node _T_2427 = or(_T_2426, same_cycle_resp) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2431 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2432 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2433 = or(_T_2431, _T_2432) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_194 node _T_2437 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2438 = asUInt(reset) node _T_2439 = eq(_T_2438, UInt<1>(0h0)) when _T_2439 : node _T_2440 = eq(_T_2437, UInt<1>(0h0)) when _T_2440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2437, UInt<1>(0h1), "") : assert_195 else : node _T_2441 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2442 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2443 = or(_T_2441, _T_2442) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_196 node _T_2447 = eq(io.in.d.bits.size, a_size_lookup) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_197 node _T_2451 = and(io.in.d.valid, d_first_1) node _T_2452 = and(_T_2451, a_first_1) node _T_2453 = and(_T_2452, io.in.a.valid) node _T_2454 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2455 = and(_T_2453, _T_2454) node _T_2456 = eq(d_release_ack, UInt<1>(0h0)) node _T_2457 = and(_T_2455, _T_2456) when _T_2457 : node _T_2458 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2459 = or(_T_2458, io.in.a.ready) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_198 node _T_2463 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2464 = orr(a_set_wo_ready) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) node _T_2466 = or(_T_2463, _T_2465) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_2470 = orr(inflight) node _T_2471 = eq(_T_2470, UInt<1>(0h0)) node _T_2472 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2473 = or(_T_2471, _T_2472) node _T_2474 = lt(watchdog, plusarg_reader.out) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = asUInt(reset) node _T_2477 = eq(_T_2476, UInt<1>(0h0)) when _T_2477 : node _T_2478 = eq(_T_2475, UInt<1>(0h0)) when _T_2478 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2475, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2479 = and(io.in.a.ready, io.in.a.valid) node _T_2480 = and(io.in.d.ready, io.in.d.valid) node _T_2481 = or(_T_2479, _T_2480) when _T_2481 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2482 = and(io.in.c.valid, c_first_1) node _T_2483 = bits(io.in.c.bits.opcode, 2, 2) node _T_2484 = bits(io.in.c.bits.opcode, 1, 1) node _T_2485 = and(_T_2483, _T_2484) node _T_2486 = and(_T_2482, _T_2485) when _T_2486 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2487 = and(io.in.c.ready, io.in.c.valid) node _T_2488 = and(_T_2487, c_first_1) node _T_2489 = bits(io.in.c.bits.opcode, 2, 2) node _T_2490 = bits(io.in.c.bits.opcode, 1, 1) node _T_2491 = and(_T_2489, _T_2490) node _T_2492 = and(_T_2488, _T_2491) when _T_2492 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2493 = dshr(inflight_1, io.in.c.bits.source) node _T_2494 = bits(_T_2493, 0, 0) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2499 = and(io.in.d.valid, d_first_2) node _T_2500 = and(_T_2499, UInt<1>(0h1)) node _T_2501 = and(_T_2500, d_release_ack_1) when _T_2501 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2502 = and(io.in.d.ready, io.in.d.valid) node _T_2503 = and(_T_2502, d_first_2) node _T_2504 = and(_T_2503, UInt<1>(0h1)) node _T_2505 = and(_T_2504, d_release_ack_1) when _T_2505 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2506 = and(io.in.d.valid, d_first_2) node _T_2507 = and(_T_2506, UInt<1>(0h1)) node _T_2508 = and(_T_2507, d_release_ack_1) when _T_2508 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2509 = dshr(inflight_1, io.in.d.bits.source) node _T_2510 = bits(_T_2509, 0, 0) node _T_2511 = or(_T_2510, same_cycle_resp_1) node _T_2512 = asUInt(reset) node _T_2513 = eq(_T_2512, UInt<1>(0h0)) when _T_2513 : node _T_2514 = eq(_T_2511, UInt<1>(0h0)) when _T_2514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2511, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2515 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_203 else : node _T_2519 = eq(io.in.d.bits.size, c_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_204 node _T_2523 = and(io.in.d.valid, d_first_2) node _T_2524 = and(_T_2523, c_first_1) node _T_2525 = and(_T_2524, io.in.c.valid) node _T_2526 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = and(_T_2527, d_release_ack_1) node _T_2529 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2530 = and(_T_2528, _T_2529) when _T_2530 : node _T_2531 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2532 = or(_T_2531, io.in.c.ready) node _T_2533 = asUInt(reset) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) when _T_2534 : node _T_2535 = eq(_T_2532, UInt<1>(0h0)) when _T_2535 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2532, UInt<1>(0h1), "") : assert_205 node _T_2536 = orr(c_set_wo_ready) when _T_2536 : node _T_2537 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_2541 = orr(inflight_1) node _T_2542 = eq(_T_2541, UInt<1>(0h0)) node _T_2543 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2544 = or(_T_2542, _T_2543) node _T_2545 = lt(watchdog_1, plusarg_reader_1.out) node _T_2546 = or(_T_2544, _T_2545) node _T_2547 = asUInt(reset) node _T_2548 = eq(_T_2547, UInt<1>(0h0)) when _T_2548 : node _T_2549 = eq(_T_2546, UInt<1>(0h0)) when _T_2549 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2546, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2550 = and(io.in.c.ready, io.in.c.valid) node _T_2551 = and(io.in.d.ready, io.in.d.valid) node _T_2552 = or(_T_2550, _T_2551) when _T_2552 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2553 = and(io.in.d.ready, io.in.d.valid) node _T_2554 = and(_T_2553, d_first_3) node _T_2555 = bits(io.in.d.bits.opcode, 2, 2) node _T_2556 = bits(io.in.d.bits.opcode, 1, 1) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = and(_T_2555, _T_2557) node _T_2559 = and(_T_2554, _T_2558) when _T_2559 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2560 = dshr(inflight_2, io.in.d.bits.sink) node _T_2561 = bits(_T_2560, 0, 0) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = asUInt(reset) node _T_2564 = eq(_T_2563, UInt<1>(0h0)) when _T_2564 : node _T_2565 = eq(_T_2562, UInt<1>(0h0)) when _T_2565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2562, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2566 = and(io.in.e.ready, io.in.e.valid) node _T_2567 = and(_T_2566, UInt<1>(0h1)) node _T_2568 = and(_T_2567, UInt<1>(0h1)) when _T_2568 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2569 = or(d_set, inflight_2) node _T_2570 = dshr(_T_2569, io.in.e.bits.sink) node _T_2571 = bits(_T_2570, 0, 0) node _T_2572 = asUInt(reset) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) when _T_2573 : node _T_2574 = eq(_T_2571, UInt<1>(0h0)) when _T_2574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:134:48)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2571, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_7 = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _legal_source_T_7 = 1'h0; // @[Mux.scala:30:73] wire _source_ok_T_14 = 1'h0; // @[Parameters.scala:54:10] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = &io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_11 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_12 = _source_ok_T_11; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire _source_ok_T_13 = &io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_13; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_6 = &io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_4; // @[Parameters.scala:56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_8 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_9 = _legal_source_T_8; // @[Mux.scala:30:73] wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_9; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_19; // @[Parameters.scala:1138:31] wire _source_ok_T_20 = &io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_20; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17; // @[Parameters.scala:52:{29,56}] wire _T_2479 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2479; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2479; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2553 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2553; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2553; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [1:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2550 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2550; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2550; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [1:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_21 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_22 = 4'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2405 = _T_2479 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2405 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2405 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2405 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2405 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2405 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2451 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_24 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_25 = 4'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2451 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2420 = _T_2553 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2420 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2420 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2420 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_set; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [15:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [31:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [3:0] _GEN_26 = {2'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_27 = 4'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [3:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2550 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2492 ? _c_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2492 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2492 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2492 ? _c_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2492 ? _c_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2523 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2523 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_2505 = _T_2553 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2505 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2505 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2505 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [3:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2559 = _T_2553 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2559 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2568 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2568 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>}}, flip lb_resp : UInt<128>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 4) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock reg refill_ctr : UInt<2>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2) node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2) node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2) node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4) node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2) node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5) node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2) node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6) node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2) node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8) node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8) node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9) node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9) node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10) node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10) node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11) node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11) node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12) node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12) node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13) node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13) node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14) node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14) node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15) node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15) node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo) node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8) node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo) node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12) node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<4>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node word_idx = bits(rp_addr, 3, 3) node _data_word_T = cat(word_idx, UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 4) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<2>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<2>(0h3)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1

module BoomMSHR( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_valid, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [1:0] io_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_id = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h0; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:342:30] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire io_lb_write_ready = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = |state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = |state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [33:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:261:22, :262:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:262:56, :264:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :264:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [35:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :340:59] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :345:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_137 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_137( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h101c0))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<29>(0h100001c0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = and(_T_150, _T_161) node _T_163 = or(UInt<1>(0h0), _T_162) node _T_164 = and(_T_148, _T_163) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_164, UInt<1>(0h1), "") : assert_2 node _T_168 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_169 = shr(io.in.a.bits.source, 2) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = leq(UInt<1>(0h0), uncommonBits_10) node _T_172 = and(_T_170, _T_171) node _T_173 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_174 = and(_T_172, _T_173) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_175 = shr(io.in.a.bits.source, 2) node _T_176 = eq(_T_175, UInt<1>(0h1)) node _T_177 = leq(UInt<1>(0h0), uncommonBits_11) node _T_178 = and(_T_176, _T_177) node _T_179 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_180 = and(_T_178, _T_179) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<2>(0h2)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_12) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_187 = shr(io.in.a.bits.source, 2) node _T_188 = eq(_T_187, UInt<2>(0h3)) node _T_189 = leq(UInt<1>(0h0), uncommonBits_13) node _T_190 = and(_T_188, _T_189) node _T_191 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_192 = and(_T_190, _T_191) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_193 = shr(io.in.a.bits.source, 3) node _T_194 = eq(_T_193, UInt<3>(0h4)) node _T_195 = leq(UInt<1>(0h0), uncommonBits_14) node _T_196 = and(_T_194, _T_195) node _T_197 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_168 connect _WIRE[1], _T_174 connect _WIRE[2], _T_180 connect _WIRE[3], _T_186 connect _WIRE[4], _T_192 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 node _T_201 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_202 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_203 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_204 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[6], _T_201, UInt<1>(0h0)) node _T_209 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = or(_T_202, _T_203) node _T_211 = or(_T_210, _T_204) node _T_212 = or(_T_211, _T_205) node _T_213 = or(_T_212, _T_206) node _T_214 = or(_T_213, _T_207) node _T_215 = or(_T_214, _T_208) node _T_216 = or(_T_215, _T_209) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_216 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<17>(0h101c0))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<29>(0h100001c0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = and(_T_220, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_15) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_16) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_17) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_18) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_290 = shr(io.in.a.bits.source, 3) node _T_291 = eq(_T_290, UInt<3>(0h4)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_19) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_298 = or(_T_265, _T_271) node _T_299 = or(_T_298, _T_277) node _T_300 = or(_T_299, _T_283) node _T_301 = or(_T_300, _T_289) node _T_302 = or(_T_301, _T_295) node _T_303 = or(_T_302, _T_296) node _T_304 = or(_T_303, _T_297) node _T_305 = and(_T_264, _T_304) node _T_306 = or(UInt<1>(0h0), _T_305) node _T_307 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<17>(0h101c0))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<29>(0h100001c0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = and(_T_308, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = and(_T_306, _T_321) node _T_323 = asUInt(reset) node _T_324 = eq(_T_323, UInt<1>(0h0)) when _T_324 : node _T_325 = eq(_T_322, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_322, UInt<1>(0h1), "") : assert_10 node _T_326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_327 = shr(io.in.a.bits.source, 2) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = leq(UInt<1>(0h0), uncommonBits_20) node _T_330 = and(_T_328, _T_329) node _T_331 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_333 = shr(io.in.a.bits.source, 2) node _T_334 = eq(_T_333, UInt<1>(0h1)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_21) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_338 = and(_T_336, _T_337) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<2>(0h2)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_22) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<2>(0h3)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_23) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<3>(0h4)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_24) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_358 = eq(io.in.a.bits.source, UInt<6>(0h2a)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_326 connect _WIRE_2[1], _T_332 connect _WIRE_2[2], _T_338 connect _WIRE_2[3], _T_344 connect _WIRE_2[4], _T_350 connect _WIRE_2[5], _T_356 connect _WIRE_2[6], _T_357 connect _WIRE_2[7], _T_358 node _T_359 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_360 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = mux(_WIRE_2[6], _T_359, UInt<1>(0h0)) node _T_367 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = or(_T_360, _T_361) node _T_369 = or(_T_368, _T_362) node _T_370 = or(_T_369, _T_363) node _T_371 = or(_T_370, _T_364) node _T_372 = or(_T_371, _T_365) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_374 node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<17>(0h101c0))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<29>(0h100001c0))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_383, _T_388) node _T_390 = and(_T_378, _T_389) node _T_391 = or(UInt<1>(0h0), _T_390) node _T_392 = and(_WIRE_3, _T_391) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_392, UInt<1>(0h1), "") : assert_11 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(source_ok, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_399 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_399, UInt<1>(0h1), "") : assert_13 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(is_aligned, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_406 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_406, UInt<1>(0h1), "") : assert_15 node _T_410 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_410, UInt<1>(0h1), "") : assert_16 node _T_414 = not(io.in.a.bits.mask) node _T_415 = eq(_T_414, UInt<1>(0h0)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_415, UInt<1>(0h1), "") : assert_17 node _T_419 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(_T_419, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_419, UInt<1>(0h1), "") : assert_18 node _T_423 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_423 : node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_426 = and(_T_424, _T_425) node _T_427 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_25) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_433 = and(_T_431, _T_432) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_434 = shr(io.in.a.bits.source, 2) node _T_435 = eq(_T_434, UInt<1>(0h1)) node _T_436 = leq(UInt<1>(0h0), uncommonBits_26) node _T_437 = and(_T_435, _T_436) node _T_438 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_439 = and(_T_437, _T_438) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<2>(0h2)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_27) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<2>(0h3)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_28) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_452 = shr(io.in.a.bits.source, 3) node _T_453 = eq(_T_452, UInt<3>(0h4)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_29) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_460 = or(_T_427, _T_433) node _T_461 = or(_T_460, _T_439) node _T_462 = or(_T_461, _T_445) node _T_463 = or(_T_462, _T_451) node _T_464 = or(_T_463, _T_457) node _T_465 = or(_T_464, _T_458) node _T_466 = or(_T_465, _T_459) node _T_467 = and(_T_426, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_468, UInt<1>(0h1), "") : assert_19 node _T_472 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_473 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_474 = and(_T_472, _T_473) node _T_475 = or(UInt<1>(0h0), _T_474) node _T_476 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<17>(0h101c0))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_482 = cvt(_T_481) node _T_483 = and(_T_482, asSInt(UInt<29>(0h100001c0))) node _T_484 = asSInt(_T_483) node _T_485 = eq(_T_484, asSInt(UInt<1>(0h0))) node _T_486 = or(_T_480, _T_485) node _T_487 = and(_T_475, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_488, UInt<1>(0h1), "") : assert_20 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(source_ok, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_498 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_498, UInt<1>(0h1), "") : assert_23 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_502, UInt<1>(0h1), "") : assert_24 node _T_506 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_506, UInt<1>(0h1), "") : assert_25 node _T_510 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_510 : node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_512 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_515 = shr(io.in.a.bits.source, 2) node _T_516 = eq(_T_515, UInt<1>(0h0)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_30) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_521 = shr(io.in.a.bits.source, 2) node _T_522 = eq(_T_521, UInt<1>(0h1)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_31) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_526 = and(_T_524, _T_525) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_527 = shr(io.in.a.bits.source, 2) node _T_528 = eq(_T_527, UInt<2>(0h2)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_32) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_533 = shr(io.in.a.bits.source, 2) node _T_534 = eq(_T_533, UInt<2>(0h3)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_33) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_538 = and(_T_536, _T_537) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_539 = shr(io.in.a.bits.source, 3) node _T_540 = eq(_T_539, UInt<3>(0h4)) node _T_541 = leq(UInt<1>(0h0), uncommonBits_34) node _T_542 = and(_T_540, _T_541) node _T_543 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_544 = and(_T_542, _T_543) node _T_545 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_547 = or(_T_514, _T_520) node _T_548 = or(_T_547, _T_526) node _T_549 = or(_T_548, _T_532) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_544) node _T_552 = or(_T_551, _T_545) node _T_553 = or(_T_552, _T_546) node _T_554 = and(_T_513, _T_553) node _T_555 = or(UInt<1>(0h0), _T_554) node _T_556 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_557 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_561 = cvt(_T_560) node _T_562 = and(_T_561, asSInt(UInt<17>(0h101c0))) node _T_563 = asSInt(_T_562) node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0))) node _T_565 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_566 = cvt(_T_565) node _T_567 = and(_T_566, asSInt(UInt<29>(0h100001c0))) node _T_568 = asSInt(_T_567) node _T_569 = eq(_T_568, asSInt(UInt<1>(0h0))) node _T_570 = or(_T_564, _T_569) node _T_571 = and(_T_559, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = and(_T_555, _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_573, UInt<1>(0h1), "") : assert_26 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_583, UInt<1>(0h1), "") : assert_29 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_587, UInt<1>(0h1), "") : assert_30 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_35) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_620 = shr(io.in.a.bits.source, 3) node _T_621 = eq(_T_620, UInt<3>(0h4)) node _T_622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_623 = and(_T_621, _T_622) node _T_624 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_625 = and(_T_623, _T_624) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_625) node _T_633 = or(_T_632, _T_626) node _T_634 = or(_T_633, _T_627) node _T_635 = and(_T_594, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_638 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_639 = and(_T_637, _T_638) node _T_640 = or(UInt<1>(0h0), _T_639) node _T_641 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_642 = cvt(_T_641) node _T_643 = and(_T_642, asSInt(UInt<17>(0h101c0))) node _T_644 = asSInt(_T_643) node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0))) node _T_646 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<29>(0h100001c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = or(_T_645, _T_650) node _T_652 = and(_T_640, _T_651) node _T_653 = or(UInt<1>(0h0), _T_652) node _T_654 = and(_T_636, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_654, UInt<1>(0h1), "") : assert_31 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(source_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(is_aligned, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_664 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_665 = asUInt(reset) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(_T_664, UInt<1>(0h0)) when _T_667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_664, UInt<1>(0h1), "") : assert_34 node _T_668 = not(mask) node _T_669 = and(io.in.a.bits.mask, _T_668) node _T_670 = eq(_T_669, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_670, UInt<1>(0h1), "") : assert_35 node _T_674 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_674 : node _T_675 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_676 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_677 = and(_T_675, _T_676) node _T_678 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_679 = shr(io.in.a.bits.source, 2) node _T_680 = eq(_T_679, UInt<1>(0h0)) node _T_681 = leq(UInt<1>(0h0), uncommonBits_40) node _T_682 = and(_T_680, _T_681) node _T_683 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_684 = and(_T_682, _T_683) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h1)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_41) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<2>(0h2)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_42) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h3)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_43) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_703 = shr(io.in.a.bits.source, 3) node _T_704 = eq(_T_703, UInt<3>(0h4)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_44) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_711 = or(_T_678, _T_684) node _T_712 = or(_T_711, _T_690) node _T_713 = or(_T_712, _T_696) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_708) node _T_716 = or(_T_715, _T_709) node _T_717 = or(_T_716, _T_710) node _T_718 = and(_T_677, _T_717) node _T_719 = or(UInt<1>(0h0), _T_718) node _T_720 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_721 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_722 = and(_T_720, _T_721) node _T_723 = or(UInt<1>(0h0), _T_722) node _T_724 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_725 = cvt(_T_724) node _T_726 = and(_T_725, asSInt(UInt<17>(0h101c0))) node _T_727 = asSInt(_T_726) node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) node _T_729 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_730 = cvt(_T_729) node _T_731 = and(_T_730, asSInt(UInt<29>(0h100001c0))) node _T_732 = asSInt(_T_731) node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) node _T_734 = or(_T_728, _T_733) node _T_735 = and(_T_723, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = and(_T_719, _T_736) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_737, UInt<1>(0h1), "") : assert_36 node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(source_ok, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_744 = asUInt(reset) node _T_745 = eq(_T_744, UInt<1>(0h0)) when _T_745 : node _T_746 = eq(is_aligned, UInt<1>(0h0)) when _T_746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_747 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_748 = asUInt(reset) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(_T_747, UInt<1>(0h0)) when _T_750 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_747, UInt<1>(0h1), "") : assert_39 node _T_751 = eq(io.in.a.bits.mask, mask) node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(_T_751, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_751, UInt<1>(0h1), "") : assert_40 node _T_755 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_755 : node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_45) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<1>(0h1)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_46) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<2>(0h2)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_47) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<2>(0h3)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_48) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_784 = shr(io.in.a.bits.source, 3) node _T_785 = eq(_T_784, UInt<3>(0h4)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_49) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_792 = or(_T_759, _T_765) node _T_793 = or(_T_792, _T_771) node _T_794 = or(_T_793, _T_777) node _T_795 = or(_T_794, _T_783) node _T_796 = or(_T_795, _T_789) node _T_797 = or(_T_796, _T_790) node _T_798 = or(_T_797, _T_791) node _T_799 = and(_T_758, _T_798) node _T_800 = or(UInt<1>(0h0), _T_799) node _T_801 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_802 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_803 = and(_T_801, _T_802) node _T_804 = or(UInt<1>(0h0), _T_803) node _T_805 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h101c0))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<29>(0h100001c0))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = or(_T_809, _T_814) node _T_816 = and(_T_804, _T_815) node _T_817 = or(UInt<1>(0h0), _T_816) node _T_818 = and(_T_800, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(source_ok, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<1>(0h0)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_50) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<1>(0h1)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_51) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<2>(0h2)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_52) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<2>(0h3)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_53) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_865 = shr(io.in.a.bits.source, 3) node _T_866 = eq(_T_865, UInt<3>(0h4)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_54) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_870 = and(_T_868, _T_869) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_873 = or(_T_840, _T_846) node _T_874 = or(_T_873, _T_852) node _T_875 = or(_T_874, _T_858) node _T_876 = or(_T_875, _T_864) node _T_877 = or(_T_876, _T_870) node _T_878 = or(_T_877, _T_871) node _T_879 = or(_T_878, _T_872) node _T_880 = and(_T_839, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_883 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_884 = and(_T_882, _T_883) node _T_885 = or(UInt<1>(0h0), _T_884) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000080)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h101c0))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<32>(0h80000080)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<29>(0h100001c0))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = or(_T_890, _T_895) node _T_897 = and(_T_885, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = and(_T_881, _T_898) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_899, UInt<1>(0h1), "") : assert_46 node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(source_ok, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(is_aligned, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_909 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(_T_909, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_909, UInt<1>(0h1), "") : assert_49 node _T_913 = eq(io.in.a.bits.mask, mask) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_913, UInt<1>(0h1), "") : assert_50 node _T_917 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_917, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_921 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_921, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc)) node _T_925 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_925 : node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(source_ok_1, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_929 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_929, UInt<1>(0h1), "") : assert_54 node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_933, UInt<1>(0h1), "") : assert_55 node _T_937 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_937, UInt<1>(0h1), "") : assert_56 node _T_941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_941, UInt<1>(0h1), "") : assert_57 node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(sink_ok, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_952 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_952, UInt<1>(0h1), "") : assert_60 node _T_956 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_956, UInt<1>(0h1), "") : assert_61 node _T_960 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_960, UInt<1>(0h1), "") : assert_62 node _T_964 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_964, UInt<1>(0h1), "") : assert_63 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h1), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_969, UInt<1>(0h1), "") : assert_64 node _T_973 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(sink_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_980 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_980, UInt<1>(0h1), "") : assert_67 node _T_984 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_984, UInt<1>(0h1), "") : assert_68 node _T_988 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_988, UInt<1>(0h1), "") : assert_69 node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_993 = or(_T_992, io.in.d.bits.corrupt) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_993, UInt<1>(0h1), "") : assert_70 node _T_997 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_998 = or(UInt<1>(0h1), _T_997) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_998, UInt<1>(0h1), "") : assert_71 node _T_1002 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1002 : node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(source_ok_1, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1006 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_73 node _T_1010 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_74 node _T_1014 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1015 = or(UInt<1>(0h1), _T_1014) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_75 node _T_1019 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1019 : node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(source_ok_1, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1023 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_77 node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1028 = or(_T_1027, io.in.d.bits.corrupt) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_78 node _T_1032 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1033 = or(UInt<1>(0h1), _T_1032) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_79 node _T_1037 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1037 : node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(source_ok_1, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1041 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_81 node _T_1045 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_82 node _T_1049 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1050 = or(UInt<1>(0h1), _T_1049) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1054 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_84 node _T_1058 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) node _T_1060 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1061 = cvt(_T_1060) node _T_1062 = and(_T_1061, asSInt(UInt<1>(0h0))) node _T_1063 = asSInt(_T_1062) node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0))) node _T_1065 = or(_T_1059, _T_1064) node _uncommonBits_T_55 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1066 = shr(io.in.b.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) node _T_1073 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<1>(0h0))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = or(_T_1072, _T_1077) node _uncommonBits_T_56 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1079 = shr(io.in.b.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h1)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) node _T_1086 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1087 = cvt(_T_1086) node _T_1088 = and(_T_1087, asSInt(UInt<1>(0h0))) node _T_1089 = asSInt(_T_1088) node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0))) node _T_1091 = or(_T_1085, _T_1090) node _uncommonBits_T_57 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1092 = shr(io.in.b.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) node _T_1099 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1100 = cvt(_T_1099) node _T_1101 = and(_T_1100, asSInt(UInt<1>(0h0))) node _T_1102 = asSInt(_T_1101) node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0))) node _T_1104 = or(_T_1098, _T_1103) node _uncommonBits_T_58 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1105 = shr(io.in.b.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) node _T_1112 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = or(_T_1111, _T_1116) node _uncommonBits_T_59 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1118 = shr(io.in.b.bits.source, 3) node _T_1119 = eq(_T_1118, UInt<3>(0h4)) node _T_1120 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1121 = and(_T_1119, _T_1120) node _T_1122 = leq(uncommonBits_59, UInt<3>(0h7)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) node _T_1125 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<1>(0h0))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1124, _T_1129) node _T_1131 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) node _T_1133 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1134 = cvt(_T_1133) node _T_1135 = and(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = asSInt(_T_1135) node _T_1137 = eq(_T_1136, asSInt(UInt<1>(0h0))) node _T_1138 = or(_T_1132, _T_1137) node _T_1139 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) node _T_1141 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1142 = cvt(_T_1141) node _T_1143 = and(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = asSInt(_T_1143) node _T_1145 = eq(_T_1144, asSInt(UInt<1>(0h0))) node _T_1146 = or(_T_1140, _T_1145) node _T_1147 = and(_T_1065, _T_1078) node _T_1148 = and(_T_1147, _T_1091) node _T_1149 = and(_T_1148, _T_1104) node _T_1150 = and(_T_1149, _T_1117) node _T_1151 = and(_T_1150, _T_1130) node _T_1152 = and(_T_1151, _T_1138) node _T_1153 = and(_T_1152, _T_1146) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 2, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 3) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<3>(0h4)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<3>(0h7)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _legal_source_WIRE : UInt<1>[8] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_31 connect _legal_source_WIRE[7], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_41 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_42 = or(_legal_source_T_41, _legal_source_T_35) node _legal_source_T_43 = or(_legal_source_T_42, _legal_source_T_36) node _legal_source_T_44 = or(_legal_source_T_43, _legal_source_T_37) node _legal_source_T_45 = or(_legal_source_T_44, _legal_source_T_38) node _legal_source_T_46 = or(_legal_source_T_45, _legal_source_T_39) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_40) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_47 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1157 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1157 : node _T_1158 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1159 = shr(io.in.b.bits.source, 2) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) node _T_1161 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1162 = and(_T_1160, _T_1161) node _T_1163 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1164 = and(_T_1162, _T_1163) node _uncommonBits_T_61 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1165 = shr(io.in.b.bits.source, 2) node _T_1166 = eq(_T_1165, UInt<1>(0h1)) node _T_1167 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1170 = and(_T_1168, _T_1169) node _uncommonBits_T_62 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1171 = shr(io.in.b.bits.source, 2) node _T_1172 = eq(_T_1171, UInt<2>(0h2)) node _T_1173 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1176 = and(_T_1174, _T_1175) node _uncommonBits_T_63 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1177 = shr(io.in.b.bits.source, 2) node _T_1178 = eq(_T_1177, UInt<2>(0h3)) node _T_1179 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1182 = and(_T_1180, _T_1181) node _uncommonBits_T_64 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1183 = shr(io.in.b.bits.source, 3) node _T_1184 = eq(_T_1183, UInt<3>(0h4)) node _T_1185 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = leq(uncommonBits_64, UInt<3>(0h7)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1190 = eq(io.in.b.bits.source, UInt<6>(0h2a)) wire _WIRE_4 : UInt<1>[8] connect _WIRE_4[0], _T_1158 connect _WIRE_4[1], _T_1164 connect _WIRE_4[2], _T_1170 connect _WIRE_4[3], _T_1176 connect _WIRE_4[4], _T_1182 connect _WIRE_4[5], _T_1188 connect _WIRE_4[6], _T_1189 connect _WIRE_4[7], _T_1190 node _T_1191 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1192 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1193 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1194 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1195 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1196 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1197 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1198 = mux(_WIRE_4[6], _T_1191, UInt<1>(0h0)) node _T_1199 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1200 = or(_T_1192, _T_1193) node _T_1201 = or(_T_1200, _T_1194) node _T_1202 = or(_T_1201, _T_1195) node _T_1203 = or(_T_1202, _T_1196) node _T_1204 = or(_T_1203, _T_1197) node _T_1205 = or(_T_1204, _T_1198) node _T_1206 = or(_T_1205, _T_1199) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1206 node _T_1207 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1208 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = or(UInt<1>(0h0), _T_1209) node _T_1211 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1212 = cvt(_T_1211) node _T_1213 = and(_T_1212, asSInt(UInt<17>(0h101c0))) node _T_1214 = asSInt(_T_1213) node _T_1215 = eq(_T_1214, asSInt(UInt<1>(0h0))) node _T_1216 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1217 = cvt(_T_1216) node _T_1218 = and(_T_1217, asSInt(UInt<29>(0h100001c0))) node _T_1219 = asSInt(_T_1218) node _T_1220 = eq(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = or(_T_1215, _T_1220) node _T_1222 = and(_T_1210, _T_1221) node _T_1223 = or(UInt<1>(0h0), _T_1222) node _T_1224 = and(_WIRE_5, _T_1223) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_86 node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(address_ok, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(legal_source, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1237 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_90 node _T_1241 = eq(io.in.b.bits.mask, mask_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_91 node _T_1245 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_92 node _T_1249 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1249 : node _T_1250 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1251 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = or(UInt<1>(0h0), _T_1252) node _T_1254 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<17>(0h101c0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<29>(0h100001c0))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = or(_T_1258, _T_1263) node _T_1265 = and(_T_1253, _T_1264) node _T_1266 = or(UInt<1>(0h0), _T_1265) node _T_1267 = and(UInt<1>(0h0), _T_1266) node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(_T_1267, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1267, UInt<1>(0h1), "") : assert_93 node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(address_ok, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(legal_source, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1280 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_97 node _T_1284 = eq(io.in.b.bits.mask, mask_1) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_98 node _T_1288 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_99 node _T_1292 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1292 : node _T_1293 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1294 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<17>(0h101c0))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1303 = cvt(_T_1302) node _T_1304 = and(_T_1303, asSInt(UInt<29>(0h100001c0))) node _T_1305 = asSInt(_T_1304) node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0))) node _T_1307 = or(_T_1301, _T_1306) node _T_1308 = and(_T_1296, _T_1307) node _T_1309 = or(UInt<1>(0h0), _T_1308) node _T_1310 = and(UInt<1>(0h0), _T_1309) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_100 node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(address_ok, UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(legal_source, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1323 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_104 node _T_1327 = eq(io.in.b.bits.mask, mask_1) node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(_T_1327, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1327, UInt<1>(0h1), "") : assert_105 node _T_1331 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1331 : node _T_1332 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1333 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1337 = cvt(_T_1336) node _T_1338 = and(_T_1337, asSInt(UInt<17>(0h101c0))) node _T_1339 = asSInt(_T_1338) node _T_1340 = eq(_T_1339, asSInt(UInt<1>(0h0))) node _T_1341 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<29>(0h100001c0))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = or(_T_1340, _T_1345) node _T_1347 = and(_T_1335, _T_1346) node _T_1348 = or(UInt<1>(0h0), _T_1347) node _T_1349 = and(UInt<1>(0h0), _T_1348) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_106 node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(address_ok, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(legal_source, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1362 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_110 node _T_1366 = not(mask_1) node _T_1367 = and(io.in.b.bits.mask, _T_1366) node _T_1368 = eq(_T_1367, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_111 node _T_1372 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1372 : node _T_1373 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1374 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1375 = and(_T_1373, _T_1374) node _T_1376 = or(UInt<1>(0h0), _T_1375) node _T_1377 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1378 = cvt(_T_1377) node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h101c0))) node _T_1380 = asSInt(_T_1379) node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0))) node _T_1382 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1383 = cvt(_T_1382) node _T_1384 = and(_T_1383, asSInt(UInt<29>(0h100001c0))) node _T_1385 = asSInt(_T_1384) node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0))) node _T_1387 = or(_T_1381, _T_1386) node _T_1388 = and(_T_1376, _T_1387) node _T_1389 = or(UInt<1>(0h0), _T_1388) node _T_1390 = and(UInt<1>(0h0), _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(address_ok, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(legal_source, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1403 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_116 node _T_1407 = eq(io.in.b.bits.mask, mask_1) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_117 node _T_1411 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1411 : node _T_1412 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1413 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1414 = and(_T_1412, _T_1413) node _T_1415 = or(UInt<1>(0h0), _T_1414) node _T_1416 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<17>(0h101c0))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<29>(0h100001c0))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = or(_T_1420, _T_1425) node _T_1427 = and(_T_1415, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1427) node _T_1429 = and(UInt<1>(0h0), _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_118 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(address_ok, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(legal_source, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1442 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_122 node _T_1446 = eq(io.in.b.bits.mask, mask_1) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_123 node _T_1450 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1450 : node _T_1451 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1452 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = or(UInt<1>(0h0), _T_1453) node _T_1455 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _T_1456 = cvt(_T_1455) node _T_1457 = and(_T_1456, asSInt(UInt<17>(0h101c0))) node _T_1458 = asSInt(_T_1457) node _T_1459 = eq(_T_1458, asSInt(UInt<1>(0h0))) node _T_1460 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _T_1461 = cvt(_T_1460) node _T_1462 = and(_T_1461, asSInt(UInt<29>(0h100001c0))) node _T_1463 = asSInt(_T_1462) node _T_1464 = eq(_T_1463, asSInt(UInt<1>(0h0))) node _T_1465 = or(_T_1459, _T_1464) node _T_1466 = and(_T_1454, _T_1465) node _T_1467 = or(UInt<1>(0h0), _T_1466) node _T_1468 = and(UInt<1>(0h0), _T_1467) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_124 node _T_1472 = asUInt(reset) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) when _T_1473 : node _T_1474 = eq(address_ok, UInt<1>(0h0)) when _T_1474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(legal_source, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1481 = eq(io.in.b.bits.mask, mask_1) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_128 node _T_1485 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1489 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_130 node _source_ok_T_78 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_79 = shr(io.in.c.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_85 = shr(io.in.c.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_91 = shr(io.in.c.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_97 = shr(io.in.c.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 2, 0) node _source_ok_T_103 = shr(io.in.c.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_14, UInt<3>(0h7)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_110 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _source_ok_WIRE_2 : UInt<1>[8] connect _source_ok_WIRE_2[0], _source_ok_T_78 connect _source_ok_WIRE_2[1], _source_ok_T_84 connect _source_ok_WIRE_2[2], _source_ok_T_90 connect _source_ok_WIRE_2[3], _source_ok_T_96 connect _source_ok_WIRE_2[4], _source_ok_T_102 connect _source_ok_WIRE_2[5], _source_ok_T_108 connect _source_ok_WIRE_2[6], _source_ok_T_109 connect _source_ok_WIRE_2[7], _source_ok_T_110 node _source_ok_T_111 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_2[2]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_2[3]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_2[4]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_2[5]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_2[6]) node source_ok_2 = or(_source_ok_T_116, _source_ok_WIRE_2[7]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1493 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<1>(0h0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = or(_T_1494, _T_1499) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_1501 = shr(io.in.c.bits.source, 2) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) node _T_1503 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) node _T_1508 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1509 = cvt(_T_1508) node _T_1510 = and(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = asSInt(_T_1510) node _T_1512 = eq(_T_1511, asSInt(UInt<1>(0h0))) node _T_1513 = or(_T_1507, _T_1512) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_1514 = shr(io.in.c.bits.source, 2) node _T_1515 = eq(_T_1514, UInt<1>(0h1)) node _T_1516 = leq(UInt<1>(0h0), uncommonBits_66) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_1519 = and(_T_1517, _T_1518) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) node _T_1521 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1522 = cvt(_T_1521) node _T_1523 = and(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = asSInt(_T_1523) node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0))) node _T_1526 = or(_T_1520, _T_1525) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_1527 = shr(io.in.c.bits.source, 2) node _T_1528 = eq(_T_1527, UInt<2>(0h2)) node _T_1529 = leq(UInt<1>(0h0), uncommonBits_67) node _T_1530 = and(_T_1528, _T_1529) node _T_1531 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_1532 = and(_T_1530, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<1>(0h0))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = or(_T_1533, _T_1538) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_1540 = shr(io.in.c.bits.source, 2) node _T_1541 = eq(_T_1540, UInt<2>(0h3)) node _T_1542 = leq(UInt<1>(0h0), uncommonBits_68) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) node _T_1547 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0) node _T_1553 = shr(io.in.c.bits.source, 3) node _T_1554 = eq(_T_1553, UInt<3>(0h4)) node _T_1555 = leq(UInt<1>(0h0), uncommonBits_69) node _T_1556 = and(_T_1554, _T_1555) node _T_1557 = leq(uncommonBits_69, UInt<3>(0h7)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) node _T_1560 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1561 = cvt(_T_1560) node _T_1562 = and(_T_1561, asSInt(UInt<1>(0h0))) node _T_1563 = asSInt(_T_1562) node _T_1564 = eq(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = or(_T_1559, _T_1564) node _T_1566 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) node _T_1568 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1569 = cvt(_T_1568) node _T_1570 = and(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = asSInt(_T_1570) node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = or(_T_1567, _T_1572) node _T_1574 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) node _T_1576 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1577 = cvt(_T_1576) node _T_1578 = and(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = asSInt(_T_1578) node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = or(_T_1575, _T_1580) node _T_1582 = and(_T_1500, _T_1513) node _T_1583 = and(_T_1582, _T_1526) node _T_1584 = and(_T_1583, _T_1539) node _T_1585 = and(_T_1584, _T_1552) node _T_1586 = and(_T_1585, _T_1565) node _T_1587 = and(_T_1586, _T_1573) node _T_1588 = and(_T_1587, _T_1581) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_131 node _T_1592 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1592 : node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(address_ok_1, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(source_ok_2, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1599 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_134 node _T_1603 = asUInt(reset) node _T_1604 = eq(_T_1603, UInt<1>(0h0)) when _T_1604 : node _T_1605 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1606 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1607 = asUInt(reset) node _T_1608 = eq(_T_1607, UInt<1>(0h0)) when _T_1608 : node _T_1609 = eq(_T_1606, UInt<1>(0h0)) when _T_1609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1606, UInt<1>(0h1), "") : assert_136 node _T_1610 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1611 = asUInt(reset) node _T_1612 = eq(_T_1611, UInt<1>(0h0)) when _T_1612 : node _T_1613 = eq(_T_1610, UInt<1>(0h0)) when _T_1613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1610, UInt<1>(0h1), "") : assert_137 node _T_1614 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1614 : node _T_1615 = asUInt(reset) node _T_1616 = eq(_T_1615, UInt<1>(0h0)) when _T_1616 : node _T_1617 = eq(address_ok_1, UInt<1>(0h0)) when _T_1617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(source_ok_2, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1621 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(_T_1621, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1621, UInt<1>(0h1), "") : assert_140 node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1628 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1629 = asUInt(reset) node _T_1630 = eq(_T_1629, UInt<1>(0h0)) when _T_1630 : node _T_1631 = eq(_T_1628, UInt<1>(0h0)) when _T_1631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1628, UInt<1>(0h1), "") : assert_142 node _T_1632 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1632 : node _T_1633 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1634 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_1637 = shr(io.in.c.bits.source, 2) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) node _T_1639 = leq(UInt<1>(0h0), uncommonBits_70) node _T_1640 = and(_T_1638, _T_1639) node _T_1641 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_1642 = and(_T_1640, _T_1641) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_1643 = shr(io.in.c.bits.source, 2) node _T_1644 = eq(_T_1643, UInt<1>(0h1)) node _T_1645 = leq(UInt<1>(0h0), uncommonBits_71) node _T_1646 = and(_T_1644, _T_1645) node _T_1647 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_1648 = and(_T_1646, _T_1647) node _uncommonBits_T_72 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_1649 = shr(io.in.c.bits.source, 2) node _T_1650 = eq(_T_1649, UInt<2>(0h2)) node _T_1651 = leq(UInt<1>(0h0), uncommonBits_72) node _T_1652 = and(_T_1650, _T_1651) node _T_1653 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_1654 = and(_T_1652, _T_1653) node _uncommonBits_T_73 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_1655 = shr(io.in.c.bits.source, 2) node _T_1656 = eq(_T_1655, UInt<2>(0h3)) node _T_1657 = leq(UInt<1>(0h0), uncommonBits_73) node _T_1658 = and(_T_1656, _T_1657) node _T_1659 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_1660 = and(_T_1658, _T_1659) node _uncommonBits_T_74 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0) node _T_1661 = shr(io.in.c.bits.source, 3) node _T_1662 = eq(_T_1661, UInt<3>(0h4)) node _T_1663 = leq(UInt<1>(0h0), uncommonBits_74) node _T_1664 = and(_T_1662, _T_1663) node _T_1665 = leq(uncommonBits_74, UInt<3>(0h7)) node _T_1666 = and(_T_1664, _T_1665) node _T_1667 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1669 = or(_T_1636, _T_1642) node _T_1670 = or(_T_1669, _T_1648) node _T_1671 = or(_T_1670, _T_1654) node _T_1672 = or(_T_1671, _T_1660) node _T_1673 = or(_T_1672, _T_1666) node _T_1674 = or(_T_1673, _T_1667) node _T_1675 = or(_T_1674, _T_1668) node _T_1676 = and(_T_1635, _T_1675) node _T_1677 = or(UInt<1>(0h0), _T_1676) node _T_1678 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1679 = or(UInt<1>(0h0), _T_1678) node _T_1680 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<17>(0h101c0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1686 = cvt(_T_1685) node _T_1687 = and(_T_1686, asSInt(UInt<29>(0h100001c0))) node _T_1688 = asSInt(_T_1687) node _T_1689 = eq(_T_1688, asSInt(UInt<1>(0h0))) node _T_1690 = or(_T_1684, _T_1689) node _T_1691 = and(_T_1679, _T_1690) node _T_1692 = or(UInt<1>(0h0), _T_1691) node _T_1693 = and(_T_1677, _T_1692) node _T_1694 = asUInt(reset) node _T_1695 = eq(_T_1694, UInt<1>(0h0)) when _T_1695 : node _T_1696 = eq(_T_1693, UInt<1>(0h0)) when _T_1696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1693, UInt<1>(0h1), "") : assert_143 node _T_1697 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_75 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_1698 = shr(io.in.c.bits.source, 2) node _T_1699 = eq(_T_1698, UInt<1>(0h0)) node _T_1700 = leq(UInt<1>(0h0), uncommonBits_75) node _T_1701 = and(_T_1699, _T_1700) node _T_1702 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_1703 = and(_T_1701, _T_1702) node _uncommonBits_T_76 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 1, 0) node _T_1704 = shr(io.in.c.bits.source, 2) node _T_1705 = eq(_T_1704, UInt<1>(0h1)) node _T_1706 = leq(UInt<1>(0h0), uncommonBits_76) node _T_1707 = and(_T_1705, _T_1706) node _T_1708 = leq(uncommonBits_76, UInt<2>(0h3)) node _T_1709 = and(_T_1707, _T_1708) node _uncommonBits_T_77 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 1, 0) node _T_1710 = shr(io.in.c.bits.source, 2) node _T_1711 = eq(_T_1710, UInt<2>(0h2)) node _T_1712 = leq(UInt<1>(0h0), uncommonBits_77) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = leq(uncommonBits_77, UInt<2>(0h3)) node _T_1715 = and(_T_1713, _T_1714) node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_1716 = shr(io.in.c.bits.source, 2) node _T_1717 = eq(_T_1716, UInt<2>(0h3)) node _T_1718 = leq(UInt<1>(0h0), uncommonBits_78) node _T_1719 = and(_T_1717, _T_1718) node _T_1720 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_1721 = and(_T_1719, _T_1720) node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 2, 0) node _T_1722 = shr(io.in.c.bits.source, 3) node _T_1723 = eq(_T_1722, UInt<3>(0h4)) node _T_1724 = leq(UInt<1>(0h0), uncommonBits_79) node _T_1725 = and(_T_1723, _T_1724) node _T_1726 = leq(uncommonBits_79, UInt<3>(0h7)) node _T_1727 = and(_T_1725, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_6 : UInt<1>[8] connect _WIRE_6[0], _T_1697 connect _WIRE_6[1], _T_1703 connect _WIRE_6[2], _T_1709 connect _WIRE_6[3], _T_1715 connect _WIRE_6[4], _T_1721 connect _WIRE_6[5], _T_1727 connect _WIRE_6[6], _T_1728 connect _WIRE_6[7], _T_1729 node _T_1730 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1731 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1732 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1733 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1734 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1735 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1736 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1737 = mux(_WIRE_6[6], _T_1730, UInt<1>(0h0)) node _T_1738 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1739 = or(_T_1731, _T_1732) node _T_1740 = or(_T_1739, _T_1733) node _T_1741 = or(_T_1740, _T_1734) node _T_1742 = or(_T_1741, _T_1735) node _T_1743 = or(_T_1742, _T_1736) node _T_1744 = or(_T_1743, _T_1737) node _T_1745 = or(_T_1744, _T_1738) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1745 node _T_1746 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1747 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1748 = and(_T_1746, _T_1747) node _T_1749 = or(UInt<1>(0h0), _T_1748) node _T_1750 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<17>(0h101c0))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1756 = cvt(_T_1755) node _T_1757 = and(_T_1756, asSInt(UInt<29>(0h100001c0))) node _T_1758 = asSInt(_T_1757) node _T_1759 = eq(_T_1758, asSInt(UInt<1>(0h0))) node _T_1760 = or(_T_1754, _T_1759) node _T_1761 = and(_T_1749, _T_1760) node _T_1762 = or(UInt<1>(0h0), _T_1761) node _T_1763 = and(_WIRE_7, _T_1762) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_144 node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(source_ok_2, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1770 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1771 = asUInt(reset) node _T_1772 = eq(_T_1771, UInt<1>(0h0)) when _T_1772 : node _T_1773 = eq(_T_1770, UInt<1>(0h0)) when _T_1773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1770, UInt<1>(0h1), "") : assert_146 node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1777 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1778 = asUInt(reset) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) when _T_1779 : node _T_1780 = eq(_T_1777, UInt<1>(0h0)) when _T_1780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1777, UInt<1>(0h1), "") : assert_148 node _T_1781 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1782 = asUInt(reset) node _T_1783 = eq(_T_1782, UInt<1>(0h0)) when _T_1783 : node _T_1784 = eq(_T_1781, UInt<1>(0h0)) when _T_1784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1781, UInt<1>(0h1), "") : assert_149 node _T_1785 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1785 : node _T_1786 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1787 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1788 = and(_T_1786, _T_1787) node _T_1789 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0) node _T_1790 = shr(io.in.c.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<1>(0h0)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_80) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_80, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0) node _T_1796 = shr(io.in.c.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<1>(0h1)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_81) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_81, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 1, 0) node _T_1802 = shr(io.in.c.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<2>(0h2)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_82) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_82, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 1, 0) node _T_1808 = shr(io.in.c.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<2>(0h3)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_83) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_83, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 2, 0) node _T_1814 = shr(io.in.c.bits.source, 3) node _T_1815 = eq(_T_1814, UInt<3>(0h4)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_84, UInt<3>(0h7)) node _T_1819 = and(_T_1817, _T_1818) node _T_1820 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1821 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1822 = or(_T_1789, _T_1795) node _T_1823 = or(_T_1822, _T_1801) node _T_1824 = or(_T_1823, _T_1807) node _T_1825 = or(_T_1824, _T_1813) node _T_1826 = or(_T_1825, _T_1819) node _T_1827 = or(_T_1826, _T_1820) node _T_1828 = or(_T_1827, _T_1821) node _T_1829 = and(_T_1788, _T_1828) node _T_1830 = or(UInt<1>(0h0), _T_1829) node _T_1831 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1832 = or(UInt<1>(0h0), _T_1831) node _T_1833 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1834 = cvt(_T_1833) node _T_1835 = and(_T_1834, asSInt(UInt<17>(0h101c0))) node _T_1836 = asSInt(_T_1835) node _T_1837 = eq(_T_1836, asSInt(UInt<1>(0h0))) node _T_1838 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1839 = cvt(_T_1838) node _T_1840 = and(_T_1839, asSInt(UInt<29>(0h100001c0))) node _T_1841 = asSInt(_T_1840) node _T_1842 = eq(_T_1841, asSInt(UInt<1>(0h0))) node _T_1843 = or(_T_1837, _T_1842) node _T_1844 = and(_T_1832, _T_1843) node _T_1845 = or(UInt<1>(0h0), _T_1844) node _T_1846 = and(_T_1830, _T_1845) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_150 node _T_1850 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1851 = shr(io.in.c.bits.source, 2) node _T_1852 = eq(_T_1851, UInt<1>(0h0)) node _T_1853 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1854 = and(_T_1852, _T_1853) node _T_1855 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1856 = and(_T_1854, _T_1855) node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1857 = shr(io.in.c.bits.source, 2) node _T_1858 = eq(_T_1857, UInt<1>(0h1)) node _T_1859 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1860 = and(_T_1858, _T_1859) node _T_1861 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1862 = and(_T_1860, _T_1861) node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1863 = shr(io.in.c.bits.source, 2) node _T_1864 = eq(_T_1863, UInt<2>(0h2)) node _T_1865 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1866 = and(_T_1864, _T_1865) node _T_1867 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1868 = and(_T_1866, _T_1867) node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_1869 = shr(io.in.c.bits.source, 2) node _T_1870 = eq(_T_1869, UInt<2>(0h3)) node _T_1871 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1872 = and(_T_1870, _T_1871) node _T_1873 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_1874 = and(_T_1872, _T_1873) node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 2, 0) node _T_1875 = shr(io.in.c.bits.source, 3) node _T_1876 = eq(_T_1875, UInt<3>(0h4)) node _T_1877 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1878 = and(_T_1876, _T_1877) node _T_1879 = leq(uncommonBits_89, UInt<3>(0h7)) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1882 = eq(io.in.c.bits.source, UInt<6>(0h2a)) wire _WIRE_8 : UInt<1>[8] connect _WIRE_8[0], _T_1850 connect _WIRE_8[1], _T_1856 connect _WIRE_8[2], _T_1862 connect _WIRE_8[3], _T_1868 connect _WIRE_8[4], _T_1874 connect _WIRE_8[5], _T_1880 connect _WIRE_8[6], _T_1881 connect _WIRE_8[7], _T_1882 node _T_1883 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1884 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1885 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1886 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1887 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1888 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1889 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1890 = mux(_WIRE_8[6], _T_1883, UInt<1>(0h0)) node _T_1891 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1892 = or(_T_1884, _T_1885) node _T_1893 = or(_T_1892, _T_1886) node _T_1894 = or(_T_1893, _T_1887) node _T_1895 = or(_T_1894, _T_1888) node _T_1896 = or(_T_1895, _T_1889) node _T_1897 = or(_T_1896, _T_1890) node _T_1898 = or(_T_1897, _T_1891) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_1898 node _T_1899 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1900 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _T_1904 = cvt(_T_1903) node _T_1905 = and(_T_1904, asSInt(UInt<17>(0h101c0))) node _T_1906 = asSInt(_T_1905) node _T_1907 = eq(_T_1906, asSInt(UInt<1>(0h0))) node _T_1908 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<29>(0h100001c0))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = or(_T_1907, _T_1912) node _T_1914 = and(_T_1902, _T_1913) node _T_1915 = or(UInt<1>(0h0), _T_1914) node _T_1916 = and(_WIRE_9, _T_1915) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_151 node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(source_ok_2, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_1923 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(_T_1923, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1923, UInt<1>(0h1), "") : assert_153 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1930 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_155 node _T_1934 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_1941 = asUInt(reset) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) when _T_1942 : node _T_1943 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1944 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_159 node _T_1948 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_160 node _T_1952 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(address_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1956 = asUInt(reset) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) when _T_1957 : node _T_1958 = eq(source_ok_2, UInt<1>(0h0)) when _T_1958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_1959 = asUInt(reset) node _T_1960 = eq(_T_1959, UInt<1>(0h0)) when _T_1960 : node _T_1961 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1962 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1963 = asUInt(reset) node _T_1964 = eq(_T_1963, UInt<1>(0h0)) when _T_1964 : node _T_1965 = eq(_T_1962, UInt<1>(0h0)) when _T_1965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1962, UInt<1>(0h1), "") : assert_164 node _T_1966 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1966 : node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(address_ok_1, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_2, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1976 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_168 node _T_1980 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1987 = eq(a_first, UInt<1>(0h0)) node _T_1988 = and(io.in.a.valid, _T_1987) when _T_1988 : node _T_1989 = eq(io.in.a.bits.opcode, opcode) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_171 node _T_1993 = eq(io.in.a.bits.param, param) node _T_1994 = asUInt(reset) node _T_1995 = eq(_T_1994, UInt<1>(0h0)) when _T_1995 : node _T_1996 = eq(_T_1993, UInt<1>(0h0)) when _T_1996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1993, UInt<1>(0h1), "") : assert_172 node _T_1997 = eq(io.in.a.bits.size, size) node _T_1998 = asUInt(reset) node _T_1999 = eq(_T_1998, UInt<1>(0h0)) when _T_1999 : node _T_2000 = eq(_T_1997, UInt<1>(0h0)) when _T_2000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1997, UInt<1>(0h1), "") : assert_173 node _T_2001 = eq(io.in.a.bits.source, source) node _T_2002 = asUInt(reset) node _T_2003 = eq(_T_2002, UInt<1>(0h0)) when _T_2003 : node _T_2004 = eq(_T_2001, UInt<1>(0h0)) when _T_2004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2001, UInt<1>(0h1), "") : assert_174 node _T_2005 = eq(io.in.a.bits.address, address) node _T_2006 = asUInt(reset) node _T_2007 = eq(_T_2006, UInt<1>(0h0)) when _T_2007 : node _T_2008 = eq(_T_2005, UInt<1>(0h0)) when _T_2008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2005, UInt<1>(0h1), "") : assert_175 node _T_2009 = and(io.in.a.ready, io.in.a.valid) node _T_2010 = and(_T_2009, a_first) when _T_2010 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2011 = eq(d_first, UInt<1>(0h0)) node _T_2012 = and(io.in.d.valid, _T_2011) when _T_2012 : node _T_2013 = eq(io.in.d.bits.opcode, opcode_1) node _T_2014 = asUInt(reset) node _T_2015 = eq(_T_2014, UInt<1>(0h0)) when _T_2015 : node _T_2016 = eq(_T_2013, UInt<1>(0h0)) when _T_2016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2013, UInt<1>(0h1), "") : assert_176 node _T_2017 = eq(io.in.d.bits.param, param_1) node _T_2018 = asUInt(reset) node _T_2019 = eq(_T_2018, UInt<1>(0h0)) when _T_2019 : node _T_2020 = eq(_T_2017, UInt<1>(0h0)) when _T_2020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2017, UInt<1>(0h1), "") : assert_177 node _T_2021 = eq(io.in.d.bits.size, size_1) node _T_2022 = asUInt(reset) node _T_2023 = eq(_T_2022, UInt<1>(0h0)) when _T_2023 : node _T_2024 = eq(_T_2021, UInt<1>(0h0)) when _T_2024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2021, UInt<1>(0h1), "") : assert_178 node _T_2025 = eq(io.in.d.bits.source, source_1) node _T_2026 = asUInt(reset) node _T_2027 = eq(_T_2026, UInt<1>(0h0)) when _T_2027 : node _T_2028 = eq(_T_2025, UInt<1>(0h0)) when _T_2028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2025, UInt<1>(0h1), "") : assert_179 node _T_2029 = eq(io.in.d.bits.sink, sink) node _T_2030 = asUInt(reset) node _T_2031 = eq(_T_2030, UInt<1>(0h0)) when _T_2031 : node _T_2032 = eq(_T_2029, UInt<1>(0h0)) when _T_2032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2029, UInt<1>(0h1), "") : assert_180 node _T_2033 = eq(io.in.d.bits.denied, denied) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_181 node _T_2037 = and(io.in.d.ready, io.in.d.valid) node _T_2038 = and(_T_2037, d_first) when _T_2038 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2039 = eq(b_first, UInt<1>(0h0)) node _T_2040 = and(io.in.b.valid, _T_2039) when _T_2040 : node _T_2041 = eq(io.in.b.bits.opcode, opcode_2) node _T_2042 = asUInt(reset) node _T_2043 = eq(_T_2042, UInt<1>(0h0)) when _T_2043 : node _T_2044 = eq(_T_2041, UInt<1>(0h0)) when _T_2044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2041, UInt<1>(0h1), "") : assert_182 node _T_2045 = eq(io.in.b.bits.param, param_2) node _T_2046 = asUInt(reset) node _T_2047 = eq(_T_2046, UInt<1>(0h0)) when _T_2047 : node _T_2048 = eq(_T_2045, UInt<1>(0h0)) when _T_2048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2045, UInt<1>(0h1), "") : assert_183 node _T_2049 = eq(io.in.b.bits.size, size_2) node _T_2050 = asUInt(reset) node _T_2051 = eq(_T_2050, UInt<1>(0h0)) when _T_2051 : node _T_2052 = eq(_T_2049, UInt<1>(0h0)) when _T_2052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2049, UInt<1>(0h1), "") : assert_184 node _T_2053 = eq(io.in.b.bits.source, source_2) node _T_2054 = asUInt(reset) node _T_2055 = eq(_T_2054, UInt<1>(0h0)) when _T_2055 : node _T_2056 = eq(_T_2053, UInt<1>(0h0)) when _T_2056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2053, UInt<1>(0h1), "") : assert_185 node _T_2057 = eq(io.in.b.bits.address, address_1) node _T_2058 = asUInt(reset) node _T_2059 = eq(_T_2058, UInt<1>(0h0)) when _T_2059 : node _T_2060 = eq(_T_2057, UInt<1>(0h0)) when _T_2060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2057, UInt<1>(0h1), "") : assert_186 node _T_2061 = and(io.in.b.ready, io.in.b.valid) node _T_2062 = and(_T_2061, b_first) when _T_2062 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2063 = eq(c_first, UInt<1>(0h0)) node _T_2064 = and(io.in.c.valid, _T_2063) when _T_2064 : node _T_2065 = eq(io.in.c.bits.opcode, opcode_3) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_187 node _T_2069 = eq(io.in.c.bits.param, param_3) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_188 node _T_2073 = eq(io.in.c.bits.size, size_3) node _T_2074 = asUInt(reset) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) when _T_2075 : node _T_2076 = eq(_T_2073, UInt<1>(0h0)) when _T_2076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2073, UInt<1>(0h1), "") : assert_189 node _T_2077 = eq(io.in.c.bits.source, source_3) node _T_2078 = asUInt(reset) node _T_2079 = eq(_T_2078, UInt<1>(0h0)) when _T_2079 : node _T_2080 = eq(_T_2077, UInt<1>(0h0)) when _T_2080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2077, UInt<1>(0h1), "") : assert_190 node _T_2081 = eq(io.in.c.bits.address, address_2) node _T_2082 = asUInt(reset) node _T_2083 = eq(_T_2082, UInt<1>(0h0)) when _T_2083 : node _T_2084 = eq(_T_2081, UInt<1>(0h0)) when _T_2084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2081, UInt<1>(0h1), "") : assert_191 node _T_2085 = and(io.in.c.ready, io.in.c.valid) node _T_2086 = and(_T_2085, c_first) when _T_2086 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes : UInt<172>, clock, reset, UInt<172>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<43> connect a_set, UInt<43>(0h0) wire a_set_wo_ready : UInt<43> connect a_set_wo_ready, UInt<43>(0h0) wire a_opcodes_set : UInt<172> connect a_opcodes_set, UInt<172>(0h0) wire a_sizes_set : UInt<172> connect a_sizes_set, UInt<172>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2087 = and(io.in.a.valid, a_first_1) node _T_2088 = and(_T_2087, UInt<1>(0h1)) when _T_2088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2089 = and(io.in.a.ready, io.in.a.valid) node _T_2090 = and(_T_2089, a_first_1) node _T_2091 = and(_T_2090, UInt<1>(0h1)) when _T_2091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2092 = dshr(inflight, io.in.a.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<43> connect d_clr, UInt<43>(0h0) wire d_clr_wo_ready : UInt<43> connect d_clr_wo_ready, UInt<43>(0h0) wire d_opcodes_clr : UInt<172> connect d_opcodes_clr, UInt<172>(0h0) wire d_sizes_clr : UInt<172> connect d_sizes_clr, UInt<172>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2098 = and(io.in.d.valid, d_first_1) node _T_2099 = and(_T_2098, UInt<1>(0h1)) node _T_2100 = eq(d_release_ack, UInt<1>(0h0)) node _T_2101 = and(_T_2099, _T_2100) when _T_2101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2102 = and(io.in.d.ready, io.in.d.valid) node _T_2103 = and(_T_2102, d_first_1) node _T_2104 = and(_T_2103, UInt<1>(0h1)) node _T_2105 = eq(d_release_ack, UInt<1>(0h0)) node _T_2106 = and(_T_2104, _T_2105) when _T_2106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2107 = and(io.in.d.valid, d_first_1) node _T_2108 = and(_T_2107, UInt<1>(0h1)) node _T_2109 = eq(d_release_ack, UInt<1>(0h0)) node _T_2110 = and(_T_2108, _T_2109) when _T_2110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2111 = dshr(inflight, io.in.d.bits.source) node _T_2112 = bits(_T_2111, 0, 0) node _T_2113 = or(_T_2112, same_cycle_resp) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2119 = or(_T_2117, _T_2118) node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(_T_2119, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2119, UInt<1>(0h1), "") : assert_194 node _T_2123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_195 else : node _T_2127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_196 node _T_2133 = eq(io.in.d.bits.size, a_size_lookup) node _T_2134 = asUInt(reset) node _T_2135 = eq(_T_2134, UInt<1>(0h0)) when _T_2135 : node _T_2136 = eq(_T_2133, UInt<1>(0h0)) when _T_2136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2133, UInt<1>(0h1), "") : assert_197 node _T_2137 = and(io.in.d.valid, d_first_1) node _T_2138 = and(_T_2137, a_first_1) node _T_2139 = and(_T_2138, io.in.a.valid) node _T_2140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2141 = and(_T_2139, _T_2140) node _T_2142 = eq(d_release_ack, UInt<1>(0h0)) node _T_2143 = and(_T_2141, _T_2142) when _T_2143 : node _T_2144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2145 = or(_T_2144, io.in.a.ready) node _T_2146 = asUInt(reset) node _T_2147 = eq(_T_2146, UInt<1>(0h0)) when _T_2147 : node _T_2148 = eq(_T_2145, UInt<1>(0h0)) when _T_2148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2145, UInt<1>(0h1), "") : assert_198 node _T_2149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2150 = orr(a_set_wo_ready) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) node _T_2152 = or(_T_2149, _T_2151) node _T_2153 = asUInt(reset) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(_T_2152, UInt<1>(0h0)) when _T_2155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2152, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_120 node _T_2156 = orr(inflight) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2159 = or(_T_2157, _T_2158) node _T_2160 = lt(watchdog, plusarg_reader.out) node _T_2161 = or(_T_2159, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2165 = and(io.in.a.ready, io.in.a.valid) node _T_2166 = and(io.in.d.ready, io.in.d.valid) node _T_2167 = or(_T_2165, _T_2166) when _T_2167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<43>, clock, reset, UInt<43>(0h0) regreset inflight_opcodes_1 : UInt<172>, clock, reset, UInt<172>(0h0) regreset inflight_sizes_1 : UInt<172>, clock, reset, UInt<172>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<43> connect c_set, UInt<43>(0h0) wire c_set_wo_ready : UInt<43> connect c_set_wo_ready, UInt<43>(0h0) wire c_opcodes_set : UInt<172> connect c_opcodes_set, UInt<172>(0h0) wire c_sizes_set : UInt<172> connect c_sizes_set, UInt<172>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2168 = and(io.in.c.valid, c_first_1) node _T_2169 = bits(io.in.c.bits.opcode, 2, 2) node _T_2170 = bits(io.in.c.bits.opcode, 1, 1) node _T_2171 = and(_T_2169, _T_2170) node _T_2172 = and(_T_2168, _T_2171) when _T_2172 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2173 = and(io.in.c.ready, io.in.c.valid) node _T_2174 = and(_T_2173, c_first_1) node _T_2175 = bits(io.in.c.bits.opcode, 2, 2) node _T_2176 = bits(io.in.c.bits.opcode, 1, 1) node _T_2177 = and(_T_2175, _T_2176) node _T_2178 = and(_T_2174, _T_2177) when _T_2178 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2179 = dshr(inflight_1, io.in.c.bits.source) node _T_2180 = bits(_T_2179, 0, 0) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = asUInt(reset) node _T_2183 = eq(_T_2182, UInt<1>(0h0)) when _T_2183 : node _T_2184 = eq(_T_2181, UInt<1>(0h0)) when _T_2184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2181, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<43> connect d_clr_1, UInt<43>(0h0) wire d_clr_wo_ready_1 : UInt<43> connect d_clr_wo_ready_1, UInt<43>(0h0) wire d_opcodes_clr_1 : UInt<172> connect d_opcodes_clr_1, UInt<172>(0h0) wire d_sizes_clr_1 : UInt<172> connect d_sizes_clr_1, UInt<172>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2185 = and(io.in.d.valid, d_first_2) node _T_2186 = and(_T_2185, UInt<1>(0h1)) node _T_2187 = and(_T_2186, d_release_ack_1) when _T_2187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2188 = and(io.in.d.ready, io.in.d.valid) node _T_2189 = and(_T_2188, d_first_2) node _T_2190 = and(_T_2189, UInt<1>(0h1)) node _T_2191 = and(_T_2190, d_release_ack_1) when _T_2191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2192 = and(io.in.d.valid, d_first_2) node _T_2193 = and(_T_2192, UInt<1>(0h1)) node _T_2194 = and(_T_2193, d_release_ack_1) when _T_2194 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2195 = dshr(inflight_1, io.in.d.bits.source) node _T_2196 = bits(_T_2195, 0, 0) node _T_2197 = or(_T_2196, same_cycle_resp_1) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2201 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_203 else : node _T_2205 = eq(io.in.d.bits.size, c_size_lookup) node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : node _T_2208 = eq(_T_2205, UInt<1>(0h0)) when _T_2208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2205, UInt<1>(0h1), "") : assert_204 node _T_2209 = and(io.in.d.valid, d_first_2) node _T_2210 = and(_T_2209, c_first_1) node _T_2211 = and(_T_2210, io.in.c.valid) node _T_2212 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2213 = and(_T_2211, _T_2212) node _T_2214 = and(_T_2213, d_release_ack_1) node _T_2215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2216 = and(_T_2214, _T_2215) when _T_2216 : node _T_2217 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2218 = or(_T_2217, io.in.c.ready) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(_T_2218, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2218, UInt<1>(0h1), "") : assert_205 node _T_2222 = orr(c_set_wo_ready) when _T_2222 : node _T_2223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : node _T_2226 = eq(_T_2223, UInt<1>(0h0)) when _T_2226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2223, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_121 node _T_2227 = orr(inflight_1) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) node _T_2229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2230 = or(_T_2228, _T_2229) node _T_2231 = lt(watchdog_1, plusarg_reader_1.out) node _T_2232 = or(_T_2230, _T_2231) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2236 = and(io.in.c.ready, io.in.c.valid) node _T_2237 = and(io.in.d.ready, io.in.d.valid) node _T_2238 = or(_T_2236, _T_2237) when _T_2238 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<12> connect d_set, UInt<12>(0h0) node _T_2239 = and(io.in.d.ready, io.in.d.valid) node _T_2240 = and(_T_2239, d_first_3) node _T_2241 = bits(io.in.d.bits.opcode, 2, 2) node _T_2242 = bits(io.in.d.bits.opcode, 1, 1) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) node _T_2244 = and(_T_2241, _T_2243) node _T_2245 = and(_T_2240, _T_2244) when _T_2245 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2246 = dshr(inflight_2, io.in.d.bits.sink) node _T_2247 = bits(_T_2246, 0, 0) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<12> connect e_clr, UInt<12>(0h0) node _T_2252 = and(io.in.e.ready, io.in.e.valid) node _T_2253 = and(_T_2252, UInt<1>(0h1)) node _T_2254 = and(_T_2253, UInt<1>(0h1)) when _T_2254 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2255 = or(d_set, inflight_2) node _T_2256 = dshr(_T_2255, io.in.e.bits.sink) node _T_2257 = bits(_T_2256, 0, 0) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_122 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_123 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_31 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_6 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h28; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_56 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_57 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_58 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_59 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_39 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h28; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_60 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_61 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_62 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_63 = 6'h28; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_64 = 6'h28; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h5; // @[Parameters.scala:54:10] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_59 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _legal_source_T_35 = 3'h0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_64 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [1:0] uncommonBits_55 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_56 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_57 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_58 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_60 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_61 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_62 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_63 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_38 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] _legal_source_T_33 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_41 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_42 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_43 = 5'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_44 = 5'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_1 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'hA; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'hA; // @[Parameters.scala:54:10] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000080; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000080; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_78 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_79 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_103 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_104 = _source_ok_T_103 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_116 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000080; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000080; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_75 = _uncommonBits_T_75[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_76 = _uncommonBits_T_76[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_77 = _uncommonBits_T_77[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_79 = _uncommonBits_T_79[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_82 = _uncommonBits_T_82[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_83 = _uncommonBits_T_83[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_84 = _uncommonBits_T_84[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_89 = _uncommonBits_T_89[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31] wire _T_2165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2165; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2239 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2239; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2239; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [1:0] b_first_counter; // @[Edges.scala:229:27] wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2236 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2236; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2236; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [42:0] inflight; // @[Monitor.scala:614:27] reg [171:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [171:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [1:0] a_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] a_set; // @[Monitor.scala:626:34] wire [42:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [171:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [171:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [171:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [171:0] _a_opcode_lookup_T_6 = {168'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [171:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [171:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [171:0] _a_size_lookup_T_6 = {168'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [171:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[171:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2091 = _T_2165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2091 ? _a_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2091 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2091 ? _a_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2091 ? _a_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [42:0] d_clr; // @[Monitor.scala:664:34] wire [42:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [171:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [171:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2137 & ~d_release_ack ? _d_clr_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2106 = _T_2239 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2106 ? _d_clr_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2106 ? _d_opcodes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2106 ? _d_sizes_clr_T_5[171:0] : 172'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [42:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [42:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [42:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [171:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [171:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [171:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [171:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [171:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [171:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [42:0] inflight_1; // @[Monitor.scala:726:35] reg [171:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [171:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46] wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [1:0] c_first_counter_1; // @[Edges.scala:229:27] wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_2; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [42:0] c_set; // @[Monitor.scala:738:34] wire [42:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [171:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [171:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [171:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [171:0] _c_opcode_lookup_T_6 = {168'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [171:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[171:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [171:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [171:0] _c_size_lookup_T_6 = {168'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [171:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[171:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2178 = _T_2236 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2178 ? _c_set_T[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2178 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2178 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2178 ? _c_opcodes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2178 ? _c_sizes_set_T_1[171:0] : 172'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [42:0] d_clr_1; // @[Monitor.scala:774:34] wire [42:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [171:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [171:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire _T_2191 = _T_2239 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2191 ? _d_clr_T_1[42:0] : 43'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2191 ? _d_opcodes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2191 ? _d_sizes_clr_T_11[171:0] : 172'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [42:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [42:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [42:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [171:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [171:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [171:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [171:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [171:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [171:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [11:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46] wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [1:0] d_first_counter_3; // @[Edges.scala:229:27] wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28] wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_set; // @[Monitor.scala:833:25] wire _T_2245 = _T_2239 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2245 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35] wire [11:0] e_clr; // @[Monitor.scala:839:25] wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module RocketTile : input clock : Clock input reset : Reset output auto : { buffer_out_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, buffer_out_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>} inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c connect tlMasterXbar.clock, clock connect tlMasterXbar.reset, reset inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u connect tlSlaveXbar.clock, clock connect tlSlaveXbar.reset, reset inst intXbar of IntXbar_i4_o1 inst broadcast of BundleBridgeNexus_UInt1 inst broadcast_1 of BundleBridgeNexus_UInt32 inst nexus of BundleBridgeNexus_NoOutput_6 inst nexus_1 of BundleBridgeNexus_TraceAux inst broadcast_2 of BundleBridgeNexus_NoOutput_7 inst widget of TLWidthWidget8_8 connect widget.clock, clock connect widget.reset, reset inst dcache of DCache connect dcache.clock, clock connect dcache.reset, reset inst zstd_compressor of ZstdCompressor connect zstd_compressor.clock, clock connect zstd_compressor.reset, reset inst frontend of Frontend connect frontend.clock, clock connect frontend.reset, reset inst widget_1 of TLWidthWidget8_9 connect widget_1.clock, clock connect widget_1.reset, reset inst fragmenter of TLFragmenter connect fragmenter.clock, clock connect fragmenter.reset, reset inst widget_2 of TLWidthWidget8_10 connect widget_2.clock, clock connect widget_2.reset, reset inst buffer of TLBuffer_a32d64s2k3z4u connect buffer.clock, clock connect buffer.reset, reset inst buffer_1 of TLBuffer_1 connect buffer_1.clock, clock connect buffer_1.reset, reset wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOtherMastersNodeOut.d.bits.corrupt invalidate tlOtherMastersNodeOut.d.bits.data invalidate tlOtherMastersNodeOut.d.bits.denied invalidate tlOtherMastersNodeOut.d.bits.sink invalidate tlOtherMastersNodeOut.d.bits.source invalidate tlOtherMastersNodeOut.d.bits.size invalidate tlOtherMastersNodeOut.d.bits.param invalidate tlOtherMastersNodeOut.d.bits.opcode invalidate tlOtherMastersNodeOut.d.valid invalidate tlOtherMastersNodeOut.d.ready invalidate tlOtherMastersNodeOut.a.bits.corrupt invalidate tlOtherMastersNodeOut.a.bits.data invalidate tlOtherMastersNodeOut.a.bits.mask invalidate tlOtherMastersNodeOut.a.bits.address invalidate tlOtherMastersNodeOut.a.bits.source invalidate tlOtherMastersNodeOut.a.bits.size invalidate tlOtherMastersNodeOut.a.bits.param invalidate tlOtherMastersNodeOut.a.bits.opcode invalidate tlOtherMastersNodeOut.a.valid invalidate tlOtherMastersNodeOut.a.ready wire x1_tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut.d.bits.data invalidate x1_tlOtherMastersNodeOut.d.bits.denied invalidate x1_tlOtherMastersNodeOut.d.bits.sink invalidate x1_tlOtherMastersNodeOut.d.bits.source invalidate x1_tlOtherMastersNodeOut.d.bits.size invalidate x1_tlOtherMastersNodeOut.d.bits.param invalidate x1_tlOtherMastersNodeOut.d.bits.opcode invalidate x1_tlOtherMastersNodeOut.d.valid invalidate x1_tlOtherMastersNodeOut.d.ready invalidate x1_tlOtherMastersNodeOut.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut.a.bits.data invalidate x1_tlOtherMastersNodeOut.a.bits.mask invalidate x1_tlOtherMastersNodeOut.a.bits.address invalidate x1_tlOtherMastersNodeOut.a.bits.source invalidate x1_tlOtherMastersNodeOut.a.bits.size invalidate x1_tlOtherMastersNodeOut.a.bits.param invalidate x1_tlOtherMastersNodeOut.a.bits.opcode invalidate x1_tlOtherMastersNodeOut.a.valid invalidate x1_tlOtherMastersNodeOut.a.ready wire x1_tlOtherMastersNodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_1.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_1.d.bits.data invalidate x1_tlOtherMastersNodeOut_1.d.bits.denied invalidate x1_tlOtherMastersNodeOut_1.d.bits.sink invalidate x1_tlOtherMastersNodeOut_1.d.bits.source invalidate x1_tlOtherMastersNodeOut_1.d.bits.size invalidate x1_tlOtherMastersNodeOut_1.d.bits.param invalidate x1_tlOtherMastersNodeOut_1.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_1.d.valid invalidate x1_tlOtherMastersNodeOut_1.d.ready invalidate x1_tlOtherMastersNodeOut_1.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_1.a.bits.data invalidate x1_tlOtherMastersNodeOut_1.a.bits.mask invalidate x1_tlOtherMastersNodeOut_1.a.bits.address invalidate x1_tlOtherMastersNodeOut_1.a.bits.source invalidate x1_tlOtherMastersNodeOut_1.a.bits.size invalidate x1_tlOtherMastersNodeOut_1.a.bits.param invalidate x1_tlOtherMastersNodeOut_1.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_1.a.valid invalidate x1_tlOtherMastersNodeOut_1.a.ready wire x1_tlOtherMastersNodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_2.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_2.d.bits.data invalidate x1_tlOtherMastersNodeOut_2.d.bits.denied invalidate x1_tlOtherMastersNodeOut_2.d.bits.sink invalidate x1_tlOtherMastersNodeOut_2.d.bits.source invalidate x1_tlOtherMastersNodeOut_2.d.bits.size invalidate x1_tlOtherMastersNodeOut_2.d.bits.param invalidate x1_tlOtherMastersNodeOut_2.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_2.d.valid invalidate x1_tlOtherMastersNodeOut_2.d.ready invalidate x1_tlOtherMastersNodeOut_2.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_2.a.bits.data invalidate x1_tlOtherMastersNodeOut_2.a.bits.mask invalidate x1_tlOtherMastersNodeOut_2.a.bits.address invalidate x1_tlOtherMastersNodeOut_2.a.bits.source invalidate x1_tlOtherMastersNodeOut_2.a.bits.size invalidate x1_tlOtherMastersNodeOut_2.a.bits.param invalidate x1_tlOtherMastersNodeOut_2.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_2.a.valid invalidate x1_tlOtherMastersNodeOut_2.a.ready wire x1_tlOtherMastersNodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_3.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_3.d.bits.data invalidate x1_tlOtherMastersNodeOut_3.d.bits.denied invalidate x1_tlOtherMastersNodeOut_3.d.bits.sink invalidate x1_tlOtherMastersNodeOut_3.d.bits.source invalidate x1_tlOtherMastersNodeOut_3.d.bits.size invalidate x1_tlOtherMastersNodeOut_3.d.bits.param invalidate x1_tlOtherMastersNodeOut_3.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_3.d.valid invalidate x1_tlOtherMastersNodeOut_3.d.ready invalidate x1_tlOtherMastersNodeOut_3.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_3.a.bits.data invalidate x1_tlOtherMastersNodeOut_3.a.bits.mask invalidate x1_tlOtherMastersNodeOut_3.a.bits.address invalidate x1_tlOtherMastersNodeOut_3.a.bits.source invalidate x1_tlOtherMastersNodeOut_3.a.bits.size invalidate x1_tlOtherMastersNodeOut_3.a.bits.param invalidate x1_tlOtherMastersNodeOut_3.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_3.a.valid invalidate x1_tlOtherMastersNodeOut_3.a.ready wire x1_tlOtherMastersNodeOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_4.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_4.d.bits.data invalidate x1_tlOtherMastersNodeOut_4.d.bits.denied invalidate x1_tlOtherMastersNodeOut_4.d.bits.sink invalidate x1_tlOtherMastersNodeOut_4.d.bits.source invalidate x1_tlOtherMastersNodeOut_4.d.bits.size invalidate x1_tlOtherMastersNodeOut_4.d.bits.param invalidate x1_tlOtherMastersNodeOut_4.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_4.d.valid invalidate x1_tlOtherMastersNodeOut_4.d.ready invalidate x1_tlOtherMastersNodeOut_4.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_4.a.bits.data invalidate x1_tlOtherMastersNodeOut_4.a.bits.mask invalidate x1_tlOtherMastersNodeOut_4.a.bits.address invalidate x1_tlOtherMastersNodeOut_4.a.bits.source invalidate x1_tlOtherMastersNodeOut_4.a.bits.size invalidate x1_tlOtherMastersNodeOut_4.a.bits.param invalidate x1_tlOtherMastersNodeOut_4.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_4.a.valid invalidate x1_tlOtherMastersNodeOut_4.a.ready wire x1_tlOtherMastersNodeOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_5.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_5.d.bits.data invalidate x1_tlOtherMastersNodeOut_5.d.bits.denied invalidate x1_tlOtherMastersNodeOut_5.d.bits.sink invalidate x1_tlOtherMastersNodeOut_5.d.bits.source invalidate x1_tlOtherMastersNodeOut_5.d.bits.size invalidate x1_tlOtherMastersNodeOut_5.d.bits.param invalidate x1_tlOtherMastersNodeOut_5.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_5.d.valid invalidate x1_tlOtherMastersNodeOut_5.d.ready invalidate x1_tlOtherMastersNodeOut_5.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_5.a.bits.data invalidate x1_tlOtherMastersNodeOut_5.a.bits.mask invalidate x1_tlOtherMastersNodeOut_5.a.bits.address invalidate x1_tlOtherMastersNodeOut_5.a.bits.source invalidate x1_tlOtherMastersNodeOut_5.a.bits.size invalidate x1_tlOtherMastersNodeOut_5.a.bits.param invalidate x1_tlOtherMastersNodeOut_5.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_5.a.valid invalidate x1_tlOtherMastersNodeOut_5.a.ready wire x1_tlOtherMastersNodeOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_6.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_6.d.bits.data invalidate x1_tlOtherMastersNodeOut_6.d.bits.denied invalidate x1_tlOtherMastersNodeOut_6.d.bits.sink invalidate x1_tlOtherMastersNodeOut_6.d.bits.source invalidate x1_tlOtherMastersNodeOut_6.d.bits.size invalidate x1_tlOtherMastersNodeOut_6.d.bits.param invalidate x1_tlOtherMastersNodeOut_6.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_6.d.valid invalidate x1_tlOtherMastersNodeOut_6.d.ready invalidate x1_tlOtherMastersNodeOut_6.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_6.a.bits.data invalidate x1_tlOtherMastersNodeOut_6.a.bits.mask invalidate x1_tlOtherMastersNodeOut_6.a.bits.address invalidate x1_tlOtherMastersNodeOut_6.a.bits.source invalidate x1_tlOtherMastersNodeOut_6.a.bits.size invalidate x1_tlOtherMastersNodeOut_6.a.bits.param invalidate x1_tlOtherMastersNodeOut_6.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_6.a.valid invalidate x1_tlOtherMastersNodeOut_6.a.ready wire x1_tlOtherMastersNodeOut_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_7.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_7.d.bits.data invalidate x1_tlOtherMastersNodeOut_7.d.bits.denied invalidate x1_tlOtherMastersNodeOut_7.d.bits.sink invalidate x1_tlOtherMastersNodeOut_7.d.bits.source invalidate x1_tlOtherMastersNodeOut_7.d.bits.size invalidate x1_tlOtherMastersNodeOut_7.d.bits.param invalidate x1_tlOtherMastersNodeOut_7.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_7.d.valid invalidate x1_tlOtherMastersNodeOut_7.d.ready invalidate x1_tlOtherMastersNodeOut_7.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_7.a.bits.data invalidate x1_tlOtherMastersNodeOut_7.a.bits.mask invalidate x1_tlOtherMastersNodeOut_7.a.bits.address invalidate x1_tlOtherMastersNodeOut_7.a.bits.source invalidate x1_tlOtherMastersNodeOut_7.a.bits.size invalidate x1_tlOtherMastersNodeOut_7.a.bits.param invalidate x1_tlOtherMastersNodeOut_7.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_7.a.valid invalidate x1_tlOtherMastersNodeOut_7.a.ready wire x1_tlOtherMastersNodeOut_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_8.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_8.d.bits.data invalidate x1_tlOtherMastersNodeOut_8.d.bits.denied invalidate x1_tlOtherMastersNodeOut_8.d.bits.sink invalidate x1_tlOtherMastersNodeOut_8.d.bits.source invalidate x1_tlOtherMastersNodeOut_8.d.bits.size invalidate x1_tlOtherMastersNodeOut_8.d.bits.param invalidate x1_tlOtherMastersNodeOut_8.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_8.d.valid invalidate x1_tlOtherMastersNodeOut_8.d.ready invalidate x1_tlOtherMastersNodeOut_8.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_8.a.bits.data invalidate x1_tlOtherMastersNodeOut_8.a.bits.mask invalidate x1_tlOtherMastersNodeOut_8.a.bits.address invalidate x1_tlOtherMastersNodeOut_8.a.bits.source invalidate x1_tlOtherMastersNodeOut_8.a.bits.size invalidate x1_tlOtherMastersNodeOut_8.a.bits.param invalidate x1_tlOtherMastersNodeOut_8.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_8.a.valid invalidate x1_tlOtherMastersNodeOut_8.a.ready wire x1_tlOtherMastersNodeOut_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_9.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_9.d.bits.data invalidate x1_tlOtherMastersNodeOut_9.d.bits.denied invalidate x1_tlOtherMastersNodeOut_9.d.bits.sink invalidate x1_tlOtherMastersNodeOut_9.d.bits.source invalidate x1_tlOtherMastersNodeOut_9.d.bits.size invalidate x1_tlOtherMastersNodeOut_9.d.bits.param invalidate x1_tlOtherMastersNodeOut_9.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_9.d.valid invalidate x1_tlOtherMastersNodeOut_9.d.ready invalidate x1_tlOtherMastersNodeOut_9.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_9.a.bits.data invalidate x1_tlOtherMastersNodeOut_9.a.bits.mask invalidate x1_tlOtherMastersNodeOut_9.a.bits.address invalidate x1_tlOtherMastersNodeOut_9.a.bits.source invalidate x1_tlOtherMastersNodeOut_9.a.bits.size invalidate x1_tlOtherMastersNodeOut_9.a.bits.param invalidate x1_tlOtherMastersNodeOut_9.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_9.a.valid invalidate x1_tlOtherMastersNodeOut_9.a.ready wire x1_tlOtherMastersNodeOut_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_10.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_10.d.bits.data invalidate x1_tlOtherMastersNodeOut_10.d.bits.denied invalidate x1_tlOtherMastersNodeOut_10.d.bits.sink invalidate x1_tlOtherMastersNodeOut_10.d.bits.source invalidate x1_tlOtherMastersNodeOut_10.d.bits.size invalidate x1_tlOtherMastersNodeOut_10.d.bits.param invalidate x1_tlOtherMastersNodeOut_10.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_10.d.valid invalidate x1_tlOtherMastersNodeOut_10.d.ready invalidate x1_tlOtherMastersNodeOut_10.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_10.a.bits.data invalidate x1_tlOtherMastersNodeOut_10.a.bits.mask invalidate x1_tlOtherMastersNodeOut_10.a.bits.address invalidate x1_tlOtherMastersNodeOut_10.a.bits.source invalidate x1_tlOtherMastersNodeOut_10.a.bits.size invalidate x1_tlOtherMastersNodeOut_10.a.bits.param invalidate x1_tlOtherMastersNodeOut_10.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_10.a.valid invalidate x1_tlOtherMastersNodeOut_10.a.ready wire x1_tlOtherMastersNodeOut_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_11.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_11.d.bits.data invalidate x1_tlOtherMastersNodeOut_11.d.bits.denied invalidate x1_tlOtherMastersNodeOut_11.d.bits.sink invalidate x1_tlOtherMastersNodeOut_11.d.bits.source invalidate x1_tlOtherMastersNodeOut_11.d.bits.size invalidate x1_tlOtherMastersNodeOut_11.d.bits.param invalidate x1_tlOtherMastersNodeOut_11.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_11.d.valid invalidate x1_tlOtherMastersNodeOut_11.d.ready invalidate x1_tlOtherMastersNodeOut_11.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_11.a.bits.data invalidate x1_tlOtherMastersNodeOut_11.a.bits.mask invalidate x1_tlOtherMastersNodeOut_11.a.bits.address invalidate x1_tlOtherMastersNodeOut_11.a.bits.source invalidate x1_tlOtherMastersNodeOut_11.a.bits.size invalidate x1_tlOtherMastersNodeOut_11.a.bits.param invalidate x1_tlOtherMastersNodeOut_11.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_11.a.valid invalidate x1_tlOtherMastersNodeOut_11.a.ready wire x1_tlOtherMastersNodeOut_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_12.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_12.d.bits.data invalidate x1_tlOtherMastersNodeOut_12.d.bits.denied invalidate x1_tlOtherMastersNodeOut_12.d.bits.sink invalidate x1_tlOtherMastersNodeOut_12.d.bits.source invalidate x1_tlOtherMastersNodeOut_12.d.bits.size invalidate x1_tlOtherMastersNodeOut_12.d.bits.param invalidate x1_tlOtherMastersNodeOut_12.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_12.d.valid invalidate x1_tlOtherMastersNodeOut_12.d.ready invalidate x1_tlOtherMastersNodeOut_12.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_12.a.bits.data invalidate x1_tlOtherMastersNodeOut_12.a.bits.mask invalidate x1_tlOtherMastersNodeOut_12.a.bits.address invalidate x1_tlOtherMastersNodeOut_12.a.bits.source invalidate x1_tlOtherMastersNodeOut_12.a.bits.size invalidate x1_tlOtherMastersNodeOut_12.a.bits.param invalidate x1_tlOtherMastersNodeOut_12.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_12.a.valid invalidate x1_tlOtherMastersNodeOut_12.a.ready wire x1_tlOtherMastersNodeOut_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_13.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_13.d.bits.data invalidate x1_tlOtherMastersNodeOut_13.d.bits.denied invalidate x1_tlOtherMastersNodeOut_13.d.bits.sink invalidate x1_tlOtherMastersNodeOut_13.d.bits.source invalidate x1_tlOtherMastersNodeOut_13.d.bits.size invalidate x1_tlOtherMastersNodeOut_13.d.bits.param invalidate x1_tlOtherMastersNodeOut_13.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_13.d.valid invalidate x1_tlOtherMastersNodeOut_13.d.ready invalidate x1_tlOtherMastersNodeOut_13.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_13.a.bits.data invalidate x1_tlOtherMastersNodeOut_13.a.bits.mask invalidate x1_tlOtherMastersNodeOut_13.a.bits.address invalidate x1_tlOtherMastersNodeOut_13.a.bits.source invalidate x1_tlOtherMastersNodeOut_13.a.bits.size invalidate x1_tlOtherMastersNodeOut_13.a.bits.param invalidate x1_tlOtherMastersNodeOut_13.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_13.a.valid invalidate x1_tlOtherMastersNodeOut_13.a.ready wire x1_tlOtherMastersNodeOut_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_14.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_14.d.bits.data invalidate x1_tlOtherMastersNodeOut_14.d.bits.denied invalidate x1_tlOtherMastersNodeOut_14.d.bits.sink invalidate x1_tlOtherMastersNodeOut_14.d.bits.source invalidate x1_tlOtherMastersNodeOut_14.d.bits.size invalidate x1_tlOtherMastersNodeOut_14.d.bits.param invalidate x1_tlOtherMastersNodeOut_14.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_14.d.valid invalidate x1_tlOtherMastersNodeOut_14.d.ready invalidate x1_tlOtherMastersNodeOut_14.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_14.a.bits.data invalidate x1_tlOtherMastersNodeOut_14.a.bits.mask invalidate x1_tlOtherMastersNodeOut_14.a.bits.address invalidate x1_tlOtherMastersNodeOut_14.a.bits.source invalidate x1_tlOtherMastersNodeOut_14.a.bits.size invalidate x1_tlOtherMastersNodeOut_14.a.bits.param invalidate x1_tlOtherMastersNodeOut_14.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_14.a.valid invalidate x1_tlOtherMastersNodeOut_14.a.ready wire x1_tlOtherMastersNodeOut_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_15.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_15.d.bits.data invalidate x1_tlOtherMastersNodeOut_15.d.bits.denied invalidate x1_tlOtherMastersNodeOut_15.d.bits.sink invalidate x1_tlOtherMastersNodeOut_15.d.bits.source invalidate x1_tlOtherMastersNodeOut_15.d.bits.size invalidate x1_tlOtherMastersNodeOut_15.d.bits.param invalidate x1_tlOtherMastersNodeOut_15.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_15.d.valid invalidate x1_tlOtherMastersNodeOut_15.d.ready invalidate x1_tlOtherMastersNodeOut_15.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_15.a.bits.data invalidate x1_tlOtherMastersNodeOut_15.a.bits.mask invalidate x1_tlOtherMastersNodeOut_15.a.bits.address invalidate x1_tlOtherMastersNodeOut_15.a.bits.source invalidate x1_tlOtherMastersNodeOut_15.a.bits.size invalidate x1_tlOtherMastersNodeOut_15.a.bits.param invalidate x1_tlOtherMastersNodeOut_15.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_15.a.valid invalidate x1_tlOtherMastersNodeOut_15.a.ready wire x1_tlOtherMastersNodeOut_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeOut_16.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_16.d.bits.data invalidate x1_tlOtherMastersNodeOut_16.d.bits.denied invalidate x1_tlOtherMastersNodeOut_16.d.bits.sink invalidate x1_tlOtherMastersNodeOut_16.d.bits.source invalidate x1_tlOtherMastersNodeOut_16.d.bits.size invalidate x1_tlOtherMastersNodeOut_16.d.bits.param invalidate x1_tlOtherMastersNodeOut_16.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_16.d.valid invalidate x1_tlOtherMastersNodeOut_16.d.ready invalidate x1_tlOtherMastersNodeOut_16.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_16.a.bits.data invalidate x1_tlOtherMastersNodeOut_16.a.bits.mask invalidate x1_tlOtherMastersNodeOut_16.a.bits.address invalidate x1_tlOtherMastersNodeOut_16.a.bits.source invalidate x1_tlOtherMastersNodeOut_16.a.bits.size invalidate x1_tlOtherMastersNodeOut_16.a.bits.param invalidate x1_tlOtherMastersNodeOut_16.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_16.a.valid invalidate x1_tlOtherMastersNodeOut_16.a.ready wire x1_tlOtherMastersNodeOut_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_tlOtherMastersNodeOut_17.e.bits.sink invalidate x1_tlOtherMastersNodeOut_17.e.valid invalidate x1_tlOtherMastersNodeOut_17.e.ready invalidate x1_tlOtherMastersNodeOut_17.d.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.d.bits.data invalidate x1_tlOtherMastersNodeOut_17.d.bits.denied invalidate x1_tlOtherMastersNodeOut_17.d.bits.sink invalidate x1_tlOtherMastersNodeOut_17.d.bits.source invalidate x1_tlOtherMastersNodeOut_17.d.bits.size invalidate x1_tlOtherMastersNodeOut_17.d.bits.param invalidate x1_tlOtherMastersNodeOut_17.d.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.d.valid invalidate x1_tlOtherMastersNodeOut_17.d.ready invalidate x1_tlOtherMastersNodeOut_17.c.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.c.bits.data invalidate x1_tlOtherMastersNodeOut_17.c.bits.address invalidate x1_tlOtherMastersNodeOut_17.c.bits.source invalidate x1_tlOtherMastersNodeOut_17.c.bits.size invalidate x1_tlOtherMastersNodeOut_17.c.bits.param invalidate x1_tlOtherMastersNodeOut_17.c.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.c.valid invalidate x1_tlOtherMastersNodeOut_17.c.ready invalidate x1_tlOtherMastersNodeOut_17.b.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.b.bits.data invalidate x1_tlOtherMastersNodeOut_17.b.bits.mask invalidate x1_tlOtherMastersNodeOut_17.b.bits.address invalidate x1_tlOtherMastersNodeOut_17.b.bits.source invalidate x1_tlOtherMastersNodeOut_17.b.bits.size invalidate x1_tlOtherMastersNodeOut_17.b.bits.param invalidate x1_tlOtherMastersNodeOut_17.b.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.b.valid invalidate x1_tlOtherMastersNodeOut_17.b.ready invalidate x1_tlOtherMastersNodeOut_17.a.bits.corrupt invalidate x1_tlOtherMastersNodeOut_17.a.bits.data invalidate x1_tlOtherMastersNodeOut_17.a.bits.mask invalidate x1_tlOtherMastersNodeOut_17.a.bits.address invalidate x1_tlOtherMastersNodeOut_17.a.bits.source invalidate x1_tlOtherMastersNodeOut_17.a.bits.size invalidate x1_tlOtherMastersNodeOut_17.a.bits.param invalidate x1_tlOtherMastersNodeOut_17.a.bits.opcode invalidate x1_tlOtherMastersNodeOut_17.a.valid invalidate x1_tlOtherMastersNodeOut_17.a.ready wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOtherMastersNodeIn.d.bits.corrupt invalidate tlOtherMastersNodeIn.d.bits.data invalidate tlOtherMastersNodeIn.d.bits.denied invalidate tlOtherMastersNodeIn.d.bits.sink invalidate tlOtherMastersNodeIn.d.bits.source invalidate tlOtherMastersNodeIn.d.bits.size invalidate tlOtherMastersNodeIn.d.bits.param invalidate tlOtherMastersNodeIn.d.bits.opcode invalidate tlOtherMastersNodeIn.d.valid invalidate tlOtherMastersNodeIn.d.ready invalidate tlOtherMastersNodeIn.a.bits.corrupt invalidate tlOtherMastersNodeIn.a.bits.data invalidate tlOtherMastersNodeIn.a.bits.mask invalidate tlOtherMastersNodeIn.a.bits.address invalidate tlOtherMastersNodeIn.a.bits.source invalidate tlOtherMastersNodeIn.a.bits.size invalidate tlOtherMastersNodeIn.a.bits.param invalidate tlOtherMastersNodeIn.a.bits.opcode invalidate tlOtherMastersNodeIn.a.valid invalidate tlOtherMastersNodeIn.a.ready wire x1_tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn.d.bits.data invalidate x1_tlOtherMastersNodeIn.d.bits.denied invalidate x1_tlOtherMastersNodeIn.d.bits.sink invalidate x1_tlOtherMastersNodeIn.d.bits.source invalidate x1_tlOtherMastersNodeIn.d.bits.size invalidate x1_tlOtherMastersNodeIn.d.bits.param invalidate x1_tlOtherMastersNodeIn.d.bits.opcode invalidate x1_tlOtherMastersNodeIn.d.valid invalidate x1_tlOtherMastersNodeIn.d.ready invalidate x1_tlOtherMastersNodeIn.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn.a.bits.data invalidate x1_tlOtherMastersNodeIn.a.bits.mask invalidate x1_tlOtherMastersNodeIn.a.bits.address invalidate x1_tlOtherMastersNodeIn.a.bits.source invalidate x1_tlOtherMastersNodeIn.a.bits.size invalidate x1_tlOtherMastersNodeIn.a.bits.param invalidate x1_tlOtherMastersNodeIn.a.bits.opcode invalidate x1_tlOtherMastersNodeIn.a.valid invalidate x1_tlOtherMastersNodeIn.a.ready wire x1_tlOtherMastersNodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_1.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_1.d.bits.data invalidate x1_tlOtherMastersNodeIn_1.d.bits.denied invalidate x1_tlOtherMastersNodeIn_1.d.bits.sink invalidate x1_tlOtherMastersNodeIn_1.d.bits.source invalidate x1_tlOtherMastersNodeIn_1.d.bits.size invalidate x1_tlOtherMastersNodeIn_1.d.bits.param invalidate x1_tlOtherMastersNodeIn_1.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_1.d.valid invalidate x1_tlOtherMastersNodeIn_1.d.ready invalidate x1_tlOtherMastersNodeIn_1.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_1.a.bits.data invalidate x1_tlOtherMastersNodeIn_1.a.bits.mask invalidate x1_tlOtherMastersNodeIn_1.a.bits.address invalidate x1_tlOtherMastersNodeIn_1.a.bits.source invalidate x1_tlOtherMastersNodeIn_1.a.bits.size invalidate x1_tlOtherMastersNodeIn_1.a.bits.param invalidate x1_tlOtherMastersNodeIn_1.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_1.a.valid invalidate x1_tlOtherMastersNodeIn_1.a.ready wire x1_tlOtherMastersNodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_2.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_2.d.bits.data invalidate x1_tlOtherMastersNodeIn_2.d.bits.denied invalidate x1_tlOtherMastersNodeIn_2.d.bits.sink invalidate x1_tlOtherMastersNodeIn_2.d.bits.source invalidate x1_tlOtherMastersNodeIn_2.d.bits.size invalidate x1_tlOtherMastersNodeIn_2.d.bits.param invalidate x1_tlOtherMastersNodeIn_2.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_2.d.valid invalidate x1_tlOtherMastersNodeIn_2.d.ready invalidate x1_tlOtherMastersNodeIn_2.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_2.a.bits.data invalidate x1_tlOtherMastersNodeIn_2.a.bits.mask invalidate x1_tlOtherMastersNodeIn_2.a.bits.address invalidate x1_tlOtherMastersNodeIn_2.a.bits.source invalidate x1_tlOtherMastersNodeIn_2.a.bits.size invalidate x1_tlOtherMastersNodeIn_2.a.bits.param invalidate x1_tlOtherMastersNodeIn_2.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_2.a.valid invalidate x1_tlOtherMastersNodeIn_2.a.ready wire x1_tlOtherMastersNodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_3.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_3.d.bits.data invalidate x1_tlOtherMastersNodeIn_3.d.bits.denied invalidate x1_tlOtherMastersNodeIn_3.d.bits.sink invalidate x1_tlOtherMastersNodeIn_3.d.bits.source invalidate x1_tlOtherMastersNodeIn_3.d.bits.size invalidate x1_tlOtherMastersNodeIn_3.d.bits.param invalidate x1_tlOtherMastersNodeIn_3.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_3.d.valid invalidate x1_tlOtherMastersNodeIn_3.d.ready invalidate x1_tlOtherMastersNodeIn_3.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_3.a.bits.data invalidate x1_tlOtherMastersNodeIn_3.a.bits.mask invalidate x1_tlOtherMastersNodeIn_3.a.bits.address invalidate x1_tlOtherMastersNodeIn_3.a.bits.source invalidate x1_tlOtherMastersNodeIn_3.a.bits.size invalidate x1_tlOtherMastersNodeIn_3.a.bits.param invalidate x1_tlOtherMastersNodeIn_3.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_3.a.valid invalidate x1_tlOtherMastersNodeIn_3.a.ready wire x1_tlOtherMastersNodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_4.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_4.d.bits.data invalidate x1_tlOtherMastersNodeIn_4.d.bits.denied invalidate x1_tlOtherMastersNodeIn_4.d.bits.sink invalidate x1_tlOtherMastersNodeIn_4.d.bits.source invalidate x1_tlOtherMastersNodeIn_4.d.bits.size invalidate x1_tlOtherMastersNodeIn_4.d.bits.param invalidate x1_tlOtherMastersNodeIn_4.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_4.d.valid invalidate x1_tlOtherMastersNodeIn_4.d.ready invalidate x1_tlOtherMastersNodeIn_4.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_4.a.bits.data invalidate x1_tlOtherMastersNodeIn_4.a.bits.mask invalidate x1_tlOtherMastersNodeIn_4.a.bits.address invalidate x1_tlOtherMastersNodeIn_4.a.bits.source invalidate x1_tlOtherMastersNodeIn_4.a.bits.size invalidate x1_tlOtherMastersNodeIn_4.a.bits.param invalidate x1_tlOtherMastersNodeIn_4.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_4.a.valid invalidate x1_tlOtherMastersNodeIn_4.a.ready wire x1_tlOtherMastersNodeIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_5.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_5.d.bits.data invalidate x1_tlOtherMastersNodeIn_5.d.bits.denied invalidate x1_tlOtherMastersNodeIn_5.d.bits.sink invalidate x1_tlOtherMastersNodeIn_5.d.bits.source invalidate x1_tlOtherMastersNodeIn_5.d.bits.size invalidate x1_tlOtherMastersNodeIn_5.d.bits.param invalidate x1_tlOtherMastersNodeIn_5.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_5.d.valid invalidate x1_tlOtherMastersNodeIn_5.d.ready invalidate x1_tlOtherMastersNodeIn_5.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_5.a.bits.data invalidate x1_tlOtherMastersNodeIn_5.a.bits.mask invalidate x1_tlOtherMastersNodeIn_5.a.bits.address invalidate x1_tlOtherMastersNodeIn_5.a.bits.source invalidate x1_tlOtherMastersNodeIn_5.a.bits.size invalidate x1_tlOtherMastersNodeIn_5.a.bits.param invalidate x1_tlOtherMastersNodeIn_5.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_5.a.valid invalidate x1_tlOtherMastersNodeIn_5.a.ready wire x1_tlOtherMastersNodeIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_6.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_6.d.bits.data invalidate x1_tlOtherMastersNodeIn_6.d.bits.denied invalidate x1_tlOtherMastersNodeIn_6.d.bits.sink invalidate x1_tlOtherMastersNodeIn_6.d.bits.source invalidate x1_tlOtherMastersNodeIn_6.d.bits.size invalidate x1_tlOtherMastersNodeIn_6.d.bits.param invalidate x1_tlOtherMastersNodeIn_6.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_6.d.valid invalidate x1_tlOtherMastersNodeIn_6.d.ready invalidate x1_tlOtherMastersNodeIn_6.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_6.a.bits.data invalidate x1_tlOtherMastersNodeIn_6.a.bits.mask invalidate x1_tlOtherMastersNodeIn_6.a.bits.address invalidate x1_tlOtherMastersNodeIn_6.a.bits.source invalidate x1_tlOtherMastersNodeIn_6.a.bits.size invalidate x1_tlOtherMastersNodeIn_6.a.bits.param invalidate x1_tlOtherMastersNodeIn_6.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_6.a.valid invalidate x1_tlOtherMastersNodeIn_6.a.ready wire x1_tlOtherMastersNodeIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_7.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_7.d.bits.data invalidate x1_tlOtherMastersNodeIn_7.d.bits.denied invalidate x1_tlOtherMastersNodeIn_7.d.bits.sink invalidate x1_tlOtherMastersNodeIn_7.d.bits.source invalidate x1_tlOtherMastersNodeIn_7.d.bits.size invalidate x1_tlOtherMastersNodeIn_7.d.bits.param invalidate x1_tlOtherMastersNodeIn_7.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_7.d.valid invalidate x1_tlOtherMastersNodeIn_7.d.ready invalidate x1_tlOtherMastersNodeIn_7.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_7.a.bits.data invalidate x1_tlOtherMastersNodeIn_7.a.bits.mask invalidate x1_tlOtherMastersNodeIn_7.a.bits.address invalidate x1_tlOtherMastersNodeIn_7.a.bits.source invalidate x1_tlOtherMastersNodeIn_7.a.bits.size invalidate x1_tlOtherMastersNodeIn_7.a.bits.param invalidate x1_tlOtherMastersNodeIn_7.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_7.a.valid invalidate x1_tlOtherMastersNodeIn_7.a.ready wire x1_tlOtherMastersNodeIn_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_8.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_8.d.bits.data invalidate x1_tlOtherMastersNodeIn_8.d.bits.denied invalidate x1_tlOtherMastersNodeIn_8.d.bits.sink invalidate x1_tlOtherMastersNodeIn_8.d.bits.source invalidate x1_tlOtherMastersNodeIn_8.d.bits.size invalidate x1_tlOtherMastersNodeIn_8.d.bits.param invalidate x1_tlOtherMastersNodeIn_8.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_8.d.valid invalidate x1_tlOtherMastersNodeIn_8.d.ready invalidate x1_tlOtherMastersNodeIn_8.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_8.a.bits.data invalidate x1_tlOtherMastersNodeIn_8.a.bits.mask invalidate x1_tlOtherMastersNodeIn_8.a.bits.address invalidate x1_tlOtherMastersNodeIn_8.a.bits.source invalidate x1_tlOtherMastersNodeIn_8.a.bits.size invalidate x1_tlOtherMastersNodeIn_8.a.bits.param invalidate x1_tlOtherMastersNodeIn_8.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_8.a.valid invalidate x1_tlOtherMastersNodeIn_8.a.ready wire x1_tlOtherMastersNodeIn_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_9.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_9.d.bits.data invalidate x1_tlOtherMastersNodeIn_9.d.bits.denied invalidate x1_tlOtherMastersNodeIn_9.d.bits.sink invalidate x1_tlOtherMastersNodeIn_9.d.bits.source invalidate x1_tlOtherMastersNodeIn_9.d.bits.size invalidate x1_tlOtherMastersNodeIn_9.d.bits.param invalidate x1_tlOtherMastersNodeIn_9.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_9.d.valid invalidate x1_tlOtherMastersNodeIn_9.d.ready invalidate x1_tlOtherMastersNodeIn_9.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_9.a.bits.data invalidate x1_tlOtherMastersNodeIn_9.a.bits.mask invalidate x1_tlOtherMastersNodeIn_9.a.bits.address invalidate x1_tlOtherMastersNodeIn_9.a.bits.source invalidate x1_tlOtherMastersNodeIn_9.a.bits.size invalidate x1_tlOtherMastersNodeIn_9.a.bits.param invalidate x1_tlOtherMastersNodeIn_9.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_9.a.valid invalidate x1_tlOtherMastersNodeIn_9.a.ready wire x1_tlOtherMastersNodeIn_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_10.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_10.d.bits.data invalidate x1_tlOtherMastersNodeIn_10.d.bits.denied invalidate x1_tlOtherMastersNodeIn_10.d.bits.sink invalidate x1_tlOtherMastersNodeIn_10.d.bits.source invalidate x1_tlOtherMastersNodeIn_10.d.bits.size invalidate x1_tlOtherMastersNodeIn_10.d.bits.param invalidate x1_tlOtherMastersNodeIn_10.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_10.d.valid invalidate x1_tlOtherMastersNodeIn_10.d.ready invalidate x1_tlOtherMastersNodeIn_10.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_10.a.bits.data invalidate x1_tlOtherMastersNodeIn_10.a.bits.mask invalidate x1_tlOtherMastersNodeIn_10.a.bits.address invalidate x1_tlOtherMastersNodeIn_10.a.bits.source invalidate x1_tlOtherMastersNodeIn_10.a.bits.size invalidate x1_tlOtherMastersNodeIn_10.a.bits.param invalidate x1_tlOtherMastersNodeIn_10.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_10.a.valid invalidate x1_tlOtherMastersNodeIn_10.a.ready wire x1_tlOtherMastersNodeIn_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_11.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_11.d.bits.data invalidate x1_tlOtherMastersNodeIn_11.d.bits.denied invalidate x1_tlOtherMastersNodeIn_11.d.bits.sink invalidate x1_tlOtherMastersNodeIn_11.d.bits.source invalidate x1_tlOtherMastersNodeIn_11.d.bits.size invalidate x1_tlOtherMastersNodeIn_11.d.bits.param invalidate x1_tlOtherMastersNodeIn_11.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_11.d.valid invalidate x1_tlOtherMastersNodeIn_11.d.ready invalidate x1_tlOtherMastersNodeIn_11.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_11.a.bits.data invalidate x1_tlOtherMastersNodeIn_11.a.bits.mask invalidate x1_tlOtherMastersNodeIn_11.a.bits.address invalidate x1_tlOtherMastersNodeIn_11.a.bits.source invalidate x1_tlOtherMastersNodeIn_11.a.bits.size invalidate x1_tlOtherMastersNodeIn_11.a.bits.param invalidate x1_tlOtherMastersNodeIn_11.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_11.a.valid invalidate x1_tlOtherMastersNodeIn_11.a.ready wire x1_tlOtherMastersNodeIn_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_12.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_12.d.bits.data invalidate x1_tlOtherMastersNodeIn_12.d.bits.denied invalidate x1_tlOtherMastersNodeIn_12.d.bits.sink invalidate x1_tlOtherMastersNodeIn_12.d.bits.source invalidate x1_tlOtherMastersNodeIn_12.d.bits.size invalidate x1_tlOtherMastersNodeIn_12.d.bits.param invalidate x1_tlOtherMastersNodeIn_12.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_12.d.valid invalidate x1_tlOtherMastersNodeIn_12.d.ready invalidate x1_tlOtherMastersNodeIn_12.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_12.a.bits.data invalidate x1_tlOtherMastersNodeIn_12.a.bits.mask invalidate x1_tlOtherMastersNodeIn_12.a.bits.address invalidate x1_tlOtherMastersNodeIn_12.a.bits.source invalidate x1_tlOtherMastersNodeIn_12.a.bits.size invalidate x1_tlOtherMastersNodeIn_12.a.bits.param invalidate x1_tlOtherMastersNodeIn_12.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_12.a.valid invalidate x1_tlOtherMastersNodeIn_12.a.ready wire x1_tlOtherMastersNodeIn_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_13.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_13.d.bits.data invalidate x1_tlOtherMastersNodeIn_13.d.bits.denied invalidate x1_tlOtherMastersNodeIn_13.d.bits.sink invalidate x1_tlOtherMastersNodeIn_13.d.bits.source invalidate x1_tlOtherMastersNodeIn_13.d.bits.size invalidate x1_tlOtherMastersNodeIn_13.d.bits.param invalidate x1_tlOtherMastersNodeIn_13.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_13.d.valid invalidate x1_tlOtherMastersNodeIn_13.d.ready invalidate x1_tlOtherMastersNodeIn_13.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_13.a.bits.data invalidate x1_tlOtherMastersNodeIn_13.a.bits.mask invalidate x1_tlOtherMastersNodeIn_13.a.bits.address invalidate x1_tlOtherMastersNodeIn_13.a.bits.source invalidate x1_tlOtherMastersNodeIn_13.a.bits.size invalidate x1_tlOtherMastersNodeIn_13.a.bits.param invalidate x1_tlOtherMastersNodeIn_13.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_13.a.valid invalidate x1_tlOtherMastersNodeIn_13.a.ready wire x1_tlOtherMastersNodeIn_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_14.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_14.d.bits.data invalidate x1_tlOtherMastersNodeIn_14.d.bits.denied invalidate x1_tlOtherMastersNodeIn_14.d.bits.sink invalidate x1_tlOtherMastersNodeIn_14.d.bits.source invalidate x1_tlOtherMastersNodeIn_14.d.bits.size invalidate x1_tlOtherMastersNodeIn_14.d.bits.param invalidate x1_tlOtherMastersNodeIn_14.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_14.d.valid invalidate x1_tlOtherMastersNodeIn_14.d.ready invalidate x1_tlOtherMastersNodeIn_14.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_14.a.bits.data invalidate x1_tlOtherMastersNodeIn_14.a.bits.mask invalidate x1_tlOtherMastersNodeIn_14.a.bits.address invalidate x1_tlOtherMastersNodeIn_14.a.bits.source invalidate x1_tlOtherMastersNodeIn_14.a.bits.size invalidate x1_tlOtherMastersNodeIn_14.a.bits.param invalidate x1_tlOtherMastersNodeIn_14.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_14.a.valid invalidate x1_tlOtherMastersNodeIn_14.a.ready wire x1_tlOtherMastersNodeIn_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_15.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_15.d.bits.data invalidate x1_tlOtherMastersNodeIn_15.d.bits.denied invalidate x1_tlOtherMastersNodeIn_15.d.bits.sink invalidate x1_tlOtherMastersNodeIn_15.d.bits.source invalidate x1_tlOtherMastersNodeIn_15.d.bits.size invalidate x1_tlOtherMastersNodeIn_15.d.bits.param invalidate x1_tlOtherMastersNodeIn_15.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_15.d.valid invalidate x1_tlOtherMastersNodeIn_15.d.ready invalidate x1_tlOtherMastersNodeIn_15.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_15.a.bits.data invalidate x1_tlOtherMastersNodeIn_15.a.bits.mask invalidate x1_tlOtherMastersNodeIn_15.a.bits.address invalidate x1_tlOtherMastersNodeIn_15.a.bits.source invalidate x1_tlOtherMastersNodeIn_15.a.bits.size invalidate x1_tlOtherMastersNodeIn_15.a.bits.param invalidate x1_tlOtherMastersNodeIn_15.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_15.a.valid invalidate x1_tlOtherMastersNodeIn_15.a.ready wire x1_tlOtherMastersNodeIn_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_tlOtherMastersNodeIn_16.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_16.d.bits.data invalidate x1_tlOtherMastersNodeIn_16.d.bits.denied invalidate x1_tlOtherMastersNodeIn_16.d.bits.sink invalidate x1_tlOtherMastersNodeIn_16.d.bits.source invalidate x1_tlOtherMastersNodeIn_16.d.bits.size invalidate x1_tlOtherMastersNodeIn_16.d.bits.param invalidate x1_tlOtherMastersNodeIn_16.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_16.d.valid invalidate x1_tlOtherMastersNodeIn_16.d.ready invalidate x1_tlOtherMastersNodeIn_16.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_16.a.bits.data invalidate x1_tlOtherMastersNodeIn_16.a.bits.mask invalidate x1_tlOtherMastersNodeIn_16.a.bits.address invalidate x1_tlOtherMastersNodeIn_16.a.bits.source invalidate x1_tlOtherMastersNodeIn_16.a.bits.size invalidate x1_tlOtherMastersNodeIn_16.a.bits.param invalidate x1_tlOtherMastersNodeIn_16.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_16.a.valid invalidate x1_tlOtherMastersNodeIn_16.a.ready wire x1_tlOtherMastersNodeIn_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_tlOtherMastersNodeIn_17.e.bits.sink invalidate x1_tlOtherMastersNodeIn_17.e.valid invalidate x1_tlOtherMastersNodeIn_17.e.ready invalidate x1_tlOtherMastersNodeIn_17.d.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.d.bits.data invalidate x1_tlOtherMastersNodeIn_17.d.bits.denied invalidate x1_tlOtherMastersNodeIn_17.d.bits.sink invalidate x1_tlOtherMastersNodeIn_17.d.bits.source invalidate x1_tlOtherMastersNodeIn_17.d.bits.size invalidate x1_tlOtherMastersNodeIn_17.d.bits.param invalidate x1_tlOtherMastersNodeIn_17.d.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.d.valid invalidate x1_tlOtherMastersNodeIn_17.d.ready invalidate x1_tlOtherMastersNodeIn_17.c.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.c.bits.data invalidate x1_tlOtherMastersNodeIn_17.c.bits.address invalidate x1_tlOtherMastersNodeIn_17.c.bits.source invalidate x1_tlOtherMastersNodeIn_17.c.bits.size invalidate x1_tlOtherMastersNodeIn_17.c.bits.param invalidate x1_tlOtherMastersNodeIn_17.c.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.c.valid invalidate x1_tlOtherMastersNodeIn_17.c.ready invalidate x1_tlOtherMastersNodeIn_17.b.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.b.bits.data invalidate x1_tlOtherMastersNodeIn_17.b.bits.mask invalidate x1_tlOtherMastersNodeIn_17.b.bits.address invalidate x1_tlOtherMastersNodeIn_17.b.bits.source invalidate x1_tlOtherMastersNodeIn_17.b.bits.size invalidate x1_tlOtherMastersNodeIn_17.b.bits.param invalidate x1_tlOtherMastersNodeIn_17.b.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.b.valid invalidate x1_tlOtherMastersNodeIn_17.b.ready invalidate x1_tlOtherMastersNodeIn_17.a.bits.corrupt invalidate x1_tlOtherMastersNodeIn_17.a.bits.data invalidate x1_tlOtherMastersNodeIn_17.a.bits.mask invalidate x1_tlOtherMastersNodeIn_17.a.bits.address invalidate x1_tlOtherMastersNodeIn_17.a.bits.source invalidate x1_tlOtherMastersNodeIn_17.a.bits.size invalidate x1_tlOtherMastersNodeIn_17.a.bits.param invalidate x1_tlOtherMastersNodeIn_17.a.bits.opcode invalidate x1_tlOtherMastersNodeIn_17.a.valid invalidate x1_tlOtherMastersNodeIn_17.a.ready connect tlOtherMastersNodeOut, tlOtherMastersNodeIn connect x1_tlOtherMastersNodeOut, x1_tlOtherMastersNodeIn connect x1_tlOtherMastersNodeOut_1, x1_tlOtherMastersNodeIn_1 connect x1_tlOtherMastersNodeOut_2, x1_tlOtherMastersNodeIn_2 connect x1_tlOtherMastersNodeOut_3, x1_tlOtherMastersNodeIn_3 connect x1_tlOtherMastersNodeOut_4, x1_tlOtherMastersNodeIn_4 connect x1_tlOtherMastersNodeOut_5, x1_tlOtherMastersNodeIn_5 connect x1_tlOtherMastersNodeOut_6, x1_tlOtherMastersNodeIn_6 connect x1_tlOtherMastersNodeOut_7, x1_tlOtherMastersNodeIn_7 connect x1_tlOtherMastersNodeOut_8, x1_tlOtherMastersNodeIn_8 connect x1_tlOtherMastersNodeOut_9, x1_tlOtherMastersNodeIn_9 connect x1_tlOtherMastersNodeOut_10, x1_tlOtherMastersNodeIn_10 connect x1_tlOtherMastersNodeOut_11, x1_tlOtherMastersNodeIn_11 connect x1_tlOtherMastersNodeOut_12, x1_tlOtherMastersNodeIn_12 connect x1_tlOtherMastersNodeOut_13, x1_tlOtherMastersNodeIn_13 connect x1_tlOtherMastersNodeOut_14, x1_tlOtherMastersNodeIn_14 connect x1_tlOtherMastersNodeOut_15, x1_tlOtherMastersNodeIn_15 connect x1_tlOtherMastersNodeOut_16, x1_tlOtherMastersNodeIn_16 connect x1_tlOtherMastersNodeOut_17, x1_tlOtherMastersNodeIn_17 wire hartIdSinkNodeIn : UInt<1> invalidate hartIdSinkNodeIn wire hartidOut : UInt<1> invalidate hartidOut wire hartidIn : UInt<1> invalidate hartidIn connect hartidOut, hartidIn wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn wire reset_vectorOut : UInt<32> invalidate reset_vectorOut wire reset_vectorIn : UInt<32> invalidate reset_vectorIn connect reset_vectorOut, reset_vectorIn wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>} invalidate traceSourceNodeOut.time invalidate traceSourceNodeOut.insns[0].tval invalidate traceSourceNodeOut.insns[0].cause invalidate traceSourceNodeOut.insns[0].interrupt invalidate traceSourceNodeOut.insns[0].exception invalidate traceSourceNodeOut.insns[0].priv invalidate traceSourceNodeOut.insns[0].insn invalidate traceSourceNodeOut.insns[0].iaddr invalidate traceSourceNodeOut.insns[0].valid wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreSourceNodeOut.cause invalidate traceCoreSourceNodeOut.tval invalidate traceCoreSourceNodeOut.priv invalidate traceCoreSourceNodeOut.group[0].ilastsize invalidate traceCoreSourceNodeOut.group[0].itype invalidate traceCoreSourceNodeOut.group[0].iaddr invalidate traceCoreSourceNodeOut.group[0].iretire wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>} connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0) connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0) wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>} invalidate traceAuxSinkNodeIn.stall invalidate traceAuxSinkNodeIn.enable wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1] invalidate bpwatchSourceNodeOut[0].action invalidate bpwatchSourceNodeOut[0].ivalid[0] invalidate bpwatchSourceNodeOut[0].wvalid[0] invalidate bpwatchSourceNodeOut[0].rvalid[0] invalidate bpwatchSourceNodeOut[0].valid[0] wire int_localOut : UInt<1>[1] invalidate int_localOut[0] wire x1_int_localOut : UInt<1>[2] invalidate x1_int_localOut[0] invalidate x1_int_localOut[1] wire x1_int_localOut_1 : UInt<1>[1] invalidate x1_int_localOut_1[0] wire x1_int_localOut_2 : UInt<1>[1] invalidate x1_int_localOut_2[0] wire int_localIn : UInt<1>[1] invalidate int_localIn[0] wire x1_int_localIn : UInt<1>[2] invalidate x1_int_localIn[0] invalidate x1_int_localIn[1] wire x1_int_localIn_1 : UInt<1>[1] invalidate x1_int_localIn_1[0] wire x1_int_localIn_2 : UInt<1>[1] invalidate x1_int_localIn_2[0] connect int_localOut, int_localIn connect x1_int_localOut, x1_int_localIn connect x1_int_localOut_1, x1_int_localIn_1 connect x1_int_localOut_2, x1_int_localIn_2 wire intSinkNodeIn : UInt<1>[5] invalidate intSinkNodeIn[0] invalidate intSinkNodeIn[1] invalidate intSinkNodeIn[2] invalidate intSinkNodeIn[3] invalidate intSinkNodeIn[4] wire haltNodeOut : UInt<1>[1] invalidate haltNodeOut[0] wire ceaseNodeOut : UInt<1>[1] invalidate ceaseNodeOut[0] wire wfiNodeOut : UInt<1>[1] invalidate wfiNodeOut[0] connect buffer.auto.in_0, tlOtherMastersNodeOut connect buffer.auto.in_1, x1_tlOtherMastersNodeOut connect buffer.auto.in_2, x1_tlOtherMastersNodeOut_1 connect buffer.auto.in_3, x1_tlOtherMastersNodeOut_2 connect buffer.auto.in_4, x1_tlOtherMastersNodeOut_3 connect buffer.auto.in_5, x1_tlOtherMastersNodeOut_4 connect buffer.auto.in_6, x1_tlOtherMastersNodeOut_5 connect buffer.auto.in_7, x1_tlOtherMastersNodeOut_6 connect buffer.auto.in_8, x1_tlOtherMastersNodeOut_7 connect buffer.auto.in_9, x1_tlOtherMastersNodeOut_8 connect buffer.auto.in_10, x1_tlOtherMastersNodeOut_9 connect buffer.auto.in_11, x1_tlOtherMastersNodeOut_10 connect buffer.auto.in_12, x1_tlOtherMastersNodeOut_11 connect buffer.auto.in_13, x1_tlOtherMastersNodeOut_12 connect buffer.auto.in_14, x1_tlOtherMastersNodeOut_13 connect buffer.auto.in_15, x1_tlOtherMastersNodeOut_14 connect buffer.auto.in_16, x1_tlOtherMastersNodeOut_15 connect buffer.auto.in_17, x1_tlOtherMastersNodeOut_16 connect buffer.auto.in_18, x1_tlOtherMastersNodeOut_17 connect x1_tlOtherMastersNodeIn_17.e.bits, tlMasterXbar.auto.anon_out.e.bits connect x1_tlOtherMastersNodeIn_17.e.valid, tlMasterXbar.auto.anon_out.e.valid connect tlMasterXbar.auto.anon_out.e.ready, x1_tlOtherMastersNodeIn_17.e.ready connect tlMasterXbar.auto.anon_out.d, x1_tlOtherMastersNodeIn_17.d connect x1_tlOtherMastersNodeIn_17.c.bits, tlMasterXbar.auto.anon_out.c.bits connect x1_tlOtherMastersNodeIn_17.c.valid, tlMasterXbar.auto.anon_out.c.valid connect tlMasterXbar.auto.anon_out.c.ready, x1_tlOtherMastersNodeIn_17.c.ready connect tlMasterXbar.auto.anon_out.b, x1_tlOtherMastersNodeIn_17.b connect x1_tlOtherMastersNodeIn_17.a.bits, tlMasterXbar.auto.anon_out.a.bits connect x1_tlOtherMastersNodeIn_17.a.valid, tlMasterXbar.auto.anon_out.a.valid connect tlMasterXbar.auto.anon_out.a.ready, x1_tlOtherMastersNodeIn_17.a.ready connect intSinkNodeIn, intXbar.auto.anon_out connect hartIdSinkNodeIn, broadcast.auto.out connect broadcast.auto.in, hartidOut connect resetVectorSinkNodeIn, broadcast_1.auto.out_0 connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1 connect broadcast_1.auto.in, reset_vectorOut connect traceAuxSinkNodeIn, nexus_1.auto.out connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0] connect intXbar.auto.anon_in_0[0], int_localOut[0] connect intXbar.auto.anon_in_1[0], x1_int_localOut[0] connect intXbar.auto.anon_in_1[1], x1_int_localOut[1] connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0] connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0] connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out connect widget.auto.anon_in, dcache.auto.out connect zstd_compressor.auto.tl_out_0.d, tlOtherMastersNodeIn.d connect tlOtherMastersNodeIn.a.bits, zstd_compressor.auto.tl_out_0.a.bits connect tlOtherMastersNodeIn.a.valid, zstd_compressor.auto.tl_out_0.a.valid connect zstd_compressor.auto.tl_out_0.a.ready, tlOtherMastersNodeIn.a.ready connect zstd_compressor.auto.tl_out_1.d, x1_tlOtherMastersNodeIn.d connect x1_tlOtherMastersNodeIn.a.bits, zstd_compressor.auto.tl_out_1.a.bits connect x1_tlOtherMastersNodeIn.a.valid, zstd_compressor.auto.tl_out_1.a.valid connect zstd_compressor.auto.tl_out_1.a.ready, x1_tlOtherMastersNodeIn.a.ready connect zstd_compressor.auto.tl_out_2.d, x1_tlOtherMastersNodeIn_1.d connect x1_tlOtherMastersNodeIn_1.a.bits, zstd_compressor.auto.tl_out_2.a.bits connect x1_tlOtherMastersNodeIn_1.a.valid, zstd_compressor.auto.tl_out_2.a.valid connect zstd_compressor.auto.tl_out_2.a.ready, x1_tlOtherMastersNodeIn_1.a.ready connect zstd_compressor.auto.tl_out_3.d, x1_tlOtherMastersNodeIn_2.d connect x1_tlOtherMastersNodeIn_2.a.bits, zstd_compressor.auto.tl_out_3.a.bits connect x1_tlOtherMastersNodeIn_2.a.valid, zstd_compressor.auto.tl_out_3.a.valid connect zstd_compressor.auto.tl_out_3.a.ready, x1_tlOtherMastersNodeIn_2.a.ready connect zstd_compressor.auto.tl_out_4.d, x1_tlOtherMastersNodeIn_3.d connect x1_tlOtherMastersNodeIn_3.a.bits, zstd_compressor.auto.tl_out_4.a.bits connect x1_tlOtherMastersNodeIn_3.a.valid, zstd_compressor.auto.tl_out_4.a.valid connect zstd_compressor.auto.tl_out_4.a.ready, x1_tlOtherMastersNodeIn_3.a.ready connect zstd_compressor.auto.tl_out_5.d, x1_tlOtherMastersNodeIn_4.d connect x1_tlOtherMastersNodeIn_4.a.bits, zstd_compressor.auto.tl_out_5.a.bits connect x1_tlOtherMastersNodeIn_4.a.valid, zstd_compressor.auto.tl_out_5.a.valid connect zstd_compressor.auto.tl_out_5.a.ready, x1_tlOtherMastersNodeIn_4.a.ready connect zstd_compressor.auto.tl_out_6.d, x1_tlOtherMastersNodeIn_5.d connect x1_tlOtherMastersNodeIn_5.a.bits, zstd_compressor.auto.tl_out_6.a.bits connect x1_tlOtherMastersNodeIn_5.a.valid, zstd_compressor.auto.tl_out_6.a.valid connect zstd_compressor.auto.tl_out_6.a.ready, x1_tlOtherMastersNodeIn_5.a.ready connect zstd_compressor.auto.tl_out_7.d, x1_tlOtherMastersNodeIn_6.d connect x1_tlOtherMastersNodeIn_6.a.bits, zstd_compressor.auto.tl_out_7.a.bits connect x1_tlOtherMastersNodeIn_6.a.valid, zstd_compressor.auto.tl_out_7.a.valid connect zstd_compressor.auto.tl_out_7.a.ready, x1_tlOtherMastersNodeIn_6.a.ready connect zstd_compressor.auto.tl_out_8.d, x1_tlOtherMastersNodeIn_7.d connect x1_tlOtherMastersNodeIn_7.a.bits, zstd_compressor.auto.tl_out_8.a.bits connect x1_tlOtherMastersNodeIn_7.a.valid, zstd_compressor.auto.tl_out_8.a.valid connect zstd_compressor.auto.tl_out_8.a.ready, x1_tlOtherMastersNodeIn_7.a.ready connect zstd_compressor.auto.tl_out_9.d, x1_tlOtherMastersNodeIn_8.d connect x1_tlOtherMastersNodeIn_8.a.bits, zstd_compressor.auto.tl_out_9.a.bits connect x1_tlOtherMastersNodeIn_8.a.valid, zstd_compressor.auto.tl_out_9.a.valid connect zstd_compressor.auto.tl_out_9.a.ready, x1_tlOtherMastersNodeIn_8.a.ready connect zstd_compressor.auto.tl_out_10.d, x1_tlOtherMastersNodeIn_9.d connect x1_tlOtherMastersNodeIn_9.a.bits, zstd_compressor.auto.tl_out_10.a.bits connect x1_tlOtherMastersNodeIn_9.a.valid, zstd_compressor.auto.tl_out_10.a.valid connect zstd_compressor.auto.tl_out_10.a.ready, x1_tlOtherMastersNodeIn_9.a.ready connect zstd_compressor.auto.tl_out_11.d, x1_tlOtherMastersNodeIn_10.d connect x1_tlOtherMastersNodeIn_10.a.bits, zstd_compressor.auto.tl_out_11.a.bits connect x1_tlOtherMastersNodeIn_10.a.valid, zstd_compressor.auto.tl_out_11.a.valid connect zstd_compressor.auto.tl_out_11.a.ready, x1_tlOtherMastersNodeIn_10.a.ready connect zstd_compressor.auto.tl_out_12.d, x1_tlOtherMastersNodeIn_11.d connect x1_tlOtherMastersNodeIn_11.a.bits, zstd_compressor.auto.tl_out_12.a.bits connect x1_tlOtherMastersNodeIn_11.a.valid, zstd_compressor.auto.tl_out_12.a.valid connect zstd_compressor.auto.tl_out_12.a.ready, x1_tlOtherMastersNodeIn_11.a.ready connect zstd_compressor.auto.tl_out_13.d, x1_tlOtherMastersNodeIn_12.d connect x1_tlOtherMastersNodeIn_12.a.bits, zstd_compressor.auto.tl_out_13.a.bits connect x1_tlOtherMastersNodeIn_12.a.valid, zstd_compressor.auto.tl_out_13.a.valid connect zstd_compressor.auto.tl_out_13.a.ready, x1_tlOtherMastersNodeIn_12.a.ready connect zstd_compressor.auto.tl_out_14.d, x1_tlOtherMastersNodeIn_13.d connect x1_tlOtherMastersNodeIn_13.a.bits, zstd_compressor.auto.tl_out_14.a.bits connect x1_tlOtherMastersNodeIn_13.a.valid, zstd_compressor.auto.tl_out_14.a.valid connect zstd_compressor.auto.tl_out_14.a.ready, x1_tlOtherMastersNodeIn_13.a.ready connect zstd_compressor.auto.tl_out_15.d, x1_tlOtherMastersNodeIn_14.d connect x1_tlOtherMastersNodeIn_14.a.bits, zstd_compressor.auto.tl_out_15.a.bits connect x1_tlOtherMastersNodeIn_14.a.valid, zstd_compressor.auto.tl_out_15.a.valid connect zstd_compressor.auto.tl_out_15.a.ready, x1_tlOtherMastersNodeIn_14.a.ready connect zstd_compressor.auto.tl_out_16.d, x1_tlOtherMastersNodeIn_15.d connect x1_tlOtherMastersNodeIn_15.a.bits, zstd_compressor.auto.tl_out_16.a.bits connect x1_tlOtherMastersNodeIn_15.a.valid, zstd_compressor.auto.tl_out_16.a.valid connect zstd_compressor.auto.tl_out_16.a.ready, x1_tlOtherMastersNodeIn_15.a.ready connect zstd_compressor.auto.tl_out_17.d, x1_tlOtherMastersNodeIn_16.d connect x1_tlOtherMastersNodeIn_16.a.bits, zstd_compressor.auto.tl_out_17.a.bits connect x1_tlOtherMastersNodeIn_16.a.valid, zstd_compressor.auto.tl_out_17.a.valid connect zstd_compressor.auto.tl_out_17.a.ready, x1_tlOtherMastersNodeIn_16.a.ready connect widget_1.auto.anon_in, frontend.auto.icache_master_out connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out connect hartidIn, auto.hartid_in connect reset_vectorIn, auto.reset_vector_in connect auto.trace_source_out, traceSourceNodeOut connect auto.trace_core_source_out, traceCoreSourceNodeOut connect int_localIn, auto.int_local_in_0 connect x1_int_localIn, auto.int_local_in_1 connect x1_int_localIn_1, auto.int_local_in_2 connect x1_int_localIn_2, auto.int_local_in_3 connect auto.halt_out, haltNodeOut connect auto.cease_out, ceaseNodeOut connect auto.wfi_out, wfiNodeOut connect buffer.auto.out_0.d, auto.buffer_out_0.d connect auto.buffer_out_0.a.bits, buffer.auto.out_0.a.bits connect auto.buffer_out_0.a.valid, buffer.auto.out_0.a.valid connect buffer.auto.out_0.a.ready, auto.buffer_out_0.a.ready connect buffer.auto.out_1.d, auto.buffer_out_1.d connect auto.buffer_out_1.a.bits, buffer.auto.out_1.a.bits connect auto.buffer_out_1.a.valid, buffer.auto.out_1.a.valid connect buffer.auto.out_1.a.ready, auto.buffer_out_1.a.ready connect buffer.auto.out_2.d, auto.buffer_out_2.d connect auto.buffer_out_2.a.bits, buffer.auto.out_2.a.bits connect auto.buffer_out_2.a.valid, buffer.auto.out_2.a.valid connect buffer.auto.out_2.a.ready, auto.buffer_out_2.a.ready connect buffer.auto.out_3.d, auto.buffer_out_3.d connect auto.buffer_out_3.a.bits, buffer.auto.out_3.a.bits connect auto.buffer_out_3.a.valid, buffer.auto.out_3.a.valid connect buffer.auto.out_3.a.ready, auto.buffer_out_3.a.ready connect buffer.auto.out_4.d, auto.buffer_out_4.d connect auto.buffer_out_4.a.bits, buffer.auto.out_4.a.bits connect auto.buffer_out_4.a.valid, buffer.auto.out_4.a.valid connect buffer.auto.out_4.a.ready, auto.buffer_out_4.a.ready connect buffer.auto.out_5.d, auto.buffer_out_5.d connect auto.buffer_out_5.a.bits, buffer.auto.out_5.a.bits connect auto.buffer_out_5.a.valid, buffer.auto.out_5.a.valid connect buffer.auto.out_5.a.ready, auto.buffer_out_5.a.ready connect buffer.auto.out_6.d, auto.buffer_out_6.d connect auto.buffer_out_6.a.bits, buffer.auto.out_6.a.bits connect auto.buffer_out_6.a.valid, buffer.auto.out_6.a.valid connect buffer.auto.out_6.a.ready, auto.buffer_out_6.a.ready connect buffer.auto.out_7.d, auto.buffer_out_7.d connect auto.buffer_out_7.a.bits, buffer.auto.out_7.a.bits connect auto.buffer_out_7.a.valid, buffer.auto.out_7.a.valid connect buffer.auto.out_7.a.ready, auto.buffer_out_7.a.ready connect buffer.auto.out_8.d, auto.buffer_out_8.d connect auto.buffer_out_8.a.bits, buffer.auto.out_8.a.bits connect auto.buffer_out_8.a.valid, buffer.auto.out_8.a.valid connect buffer.auto.out_8.a.ready, auto.buffer_out_8.a.ready connect buffer.auto.out_9.d, auto.buffer_out_9.d connect auto.buffer_out_9.a.bits, buffer.auto.out_9.a.bits connect auto.buffer_out_9.a.valid, buffer.auto.out_9.a.valid connect buffer.auto.out_9.a.ready, auto.buffer_out_9.a.ready connect buffer.auto.out_10.d, auto.buffer_out_10.d connect auto.buffer_out_10.a.bits, buffer.auto.out_10.a.bits connect auto.buffer_out_10.a.valid, buffer.auto.out_10.a.valid connect buffer.auto.out_10.a.ready, auto.buffer_out_10.a.ready connect buffer.auto.out_11.d, auto.buffer_out_11.d connect auto.buffer_out_11.a.bits, buffer.auto.out_11.a.bits connect auto.buffer_out_11.a.valid, buffer.auto.out_11.a.valid connect buffer.auto.out_11.a.ready, auto.buffer_out_11.a.ready connect buffer.auto.out_12.d, auto.buffer_out_12.d connect auto.buffer_out_12.a.bits, buffer.auto.out_12.a.bits connect auto.buffer_out_12.a.valid, buffer.auto.out_12.a.valid connect buffer.auto.out_12.a.ready, auto.buffer_out_12.a.ready connect buffer.auto.out_13.d, auto.buffer_out_13.d connect auto.buffer_out_13.a.bits, buffer.auto.out_13.a.bits connect auto.buffer_out_13.a.valid, buffer.auto.out_13.a.valid connect buffer.auto.out_13.a.ready, auto.buffer_out_13.a.ready connect buffer.auto.out_14.d, auto.buffer_out_14.d connect auto.buffer_out_14.a.bits, buffer.auto.out_14.a.bits connect auto.buffer_out_14.a.valid, buffer.auto.out_14.a.valid connect buffer.auto.out_14.a.ready, auto.buffer_out_14.a.ready connect buffer.auto.out_15.d, auto.buffer_out_15.d connect auto.buffer_out_15.a.bits, buffer.auto.out_15.a.bits connect auto.buffer_out_15.a.valid, buffer.auto.out_15.a.valid connect buffer.auto.out_15.a.ready, auto.buffer_out_15.a.ready connect buffer.auto.out_16.d, auto.buffer_out_16.d connect auto.buffer_out_16.a.bits, buffer.auto.out_16.a.bits connect auto.buffer_out_16.a.valid, buffer.auto.out_16.a.valid connect buffer.auto.out_16.a.ready, auto.buffer_out_16.a.ready connect buffer.auto.out_17.d, auto.buffer_out_17.d connect auto.buffer_out_17.a.bits, buffer.auto.out_17.a.bits connect auto.buffer_out_17.a.valid, buffer.auto.out_17.a.valid connect buffer.auto.out_17.a.ready, auto.buffer_out_17.a.ready connect auto.buffer_out_18.e.bits, buffer.auto.out_18.e.bits connect auto.buffer_out_18.e.valid, buffer.auto.out_18.e.valid connect buffer.auto.out_18.e.ready, auto.buffer_out_18.e.ready connect buffer.auto.out_18.d, auto.buffer_out_18.d connect auto.buffer_out_18.c.bits, buffer.auto.out_18.c.bits connect auto.buffer_out_18.c.valid, buffer.auto.out_18.c.valid connect buffer.auto.out_18.c.ready, auto.buffer_out_18.c.ready connect buffer.auto.out_18.b, auto.buffer_out_18.b connect auto.buffer_out_18.a.bits, buffer.auto.out_18.a.bits connect auto.buffer_out_18.a.valid, buffer.auto.out_18.a.valid connect buffer.auto.out_18.a.ready, auto.buffer_out_18.a.ready invalidate dcache.io.tlb_port.s2_kill invalidate dcache.io.tlb_port.s1_resp.cmd invalidate dcache.io.tlb_port.s1_resp.size invalidate dcache.io.tlb_port.s1_resp.prefetchable invalidate dcache.io.tlb_port.s1_resp.must_alloc invalidate dcache.io.tlb_port.s1_resp.cacheable invalidate dcache.io.tlb_port.s1_resp.ma.inst invalidate dcache.io.tlb_port.s1_resp.ma.st invalidate dcache.io.tlb_port.s1_resp.ma.ld invalidate dcache.io.tlb_port.s1_resp.ae.inst invalidate dcache.io.tlb_port.s1_resp.ae.st invalidate dcache.io.tlb_port.s1_resp.ae.ld invalidate dcache.io.tlb_port.s1_resp.gf.inst invalidate dcache.io.tlb_port.s1_resp.gf.st invalidate dcache.io.tlb_port.s1_resp.gf.ld invalidate dcache.io.tlb_port.s1_resp.pf.inst invalidate dcache.io.tlb_port.s1_resp.pf.st invalidate dcache.io.tlb_port.s1_resp.pf.ld invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte invalidate dcache.io.tlb_port.s1_resp.gpa invalidate dcache.io.tlb_port.s1_resp.paddr invalidate dcache.io.tlb_port.s1_resp.miss invalidate dcache.io.tlb_port.req.bits.v invalidate dcache.io.tlb_port.req.bits.prv invalidate dcache.io.tlb_port.req.bits.cmd invalidate dcache.io.tlb_port.req.bits.size invalidate dcache.io.tlb_port.req.bits.passthrough invalidate dcache.io.tlb_port.req.bits.vaddr invalidate dcache.io.tlb_port.req.valid invalidate dcache.io.tlb_port.req.ready inst fpuOpt of FPU connect fpuOpt.clock, clock connect fpuOpt.reset, reset connect fpuOpt.io.cp_req.valid, UInt<1>(0h0) invalidate fpuOpt.io.cp_req.bits.in3 invalidate fpuOpt.io.cp_req.bits.in2 invalidate fpuOpt.io.cp_req.bits.in1 invalidate fpuOpt.io.cp_req.bits.fmt invalidate fpuOpt.io.cp_req.bits.typ invalidate fpuOpt.io.cp_req.bits.fmaCmd invalidate fpuOpt.io.cp_req.bits.rm invalidate fpuOpt.io.cp_req.bits.vec invalidate fpuOpt.io.cp_req.bits.wflags invalidate fpuOpt.io.cp_req.bits.sqrt invalidate fpuOpt.io.cp_req.bits.div invalidate fpuOpt.io.cp_req.bits.fma invalidate fpuOpt.io.cp_req.bits.fastpipe invalidate fpuOpt.io.cp_req.bits.toint invalidate fpuOpt.io.cp_req.bits.fromint invalidate fpuOpt.io.cp_req.bits.typeTagOut invalidate fpuOpt.io.cp_req.bits.typeTagIn invalidate fpuOpt.io.cp_req.bits.swap23 invalidate fpuOpt.io.cp_req.bits.swap12 invalidate fpuOpt.io.cp_req.bits.ren3 invalidate fpuOpt.io.cp_req.bits.ren2 invalidate fpuOpt.io.cp_req.bits.ren1 invalidate fpuOpt.io.cp_req.bits.wen invalidate fpuOpt.io.cp_req.bits.ldst connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0) inst dcacheArb of HellaCacheArbiter connect dcacheArb.clock, clock connect dcacheArb.reset, reset connect dcache.io.cpu, dcacheArb.io.mem inst ptw of PTW connect ptw.clock, clock connect ptw.reset, reset invalidate ptw.io.mem.clock_enabled invalidate ptw.io.mem.keep_clock_enabled invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad invalidate ptw.io.mem.perf.canAcceptLoadThenLoad invalidate ptw.io.mem.perf.canAcceptStoreThenRMW invalidate ptw.io.mem.perf.canAcceptStoreThenLoad invalidate ptw.io.mem.perf.blocked invalidate ptw.io.mem.perf.tlbMiss invalidate ptw.io.mem.perf.grant invalidate ptw.io.mem.perf.release invalidate ptw.io.mem.perf.acquire invalidate ptw.io.mem.store_pending invalidate ptw.io.mem.ordered invalidate ptw.io.mem.s2_gpa_is_pte invalidate ptw.io.mem.s2_gpa invalidate ptw.io.mem.s2_xcpt.ae.st invalidate ptw.io.mem.s2_xcpt.ae.ld invalidate ptw.io.mem.s2_xcpt.gf.st invalidate ptw.io.mem.s2_xcpt.gf.ld invalidate ptw.io.mem.s2_xcpt.pf.st invalidate ptw.io.mem.s2_xcpt.pf.ld invalidate ptw.io.mem.s2_xcpt.ma.st invalidate ptw.io.mem.s2_xcpt.ma.ld invalidate ptw.io.mem.replay_next invalidate ptw.io.mem.resp.bits.store_data invalidate ptw.io.mem.resp.bits.data_raw invalidate ptw.io.mem.resp.bits.data_word_bypass invalidate ptw.io.mem.resp.bits.has_data invalidate ptw.io.mem.resp.bits.replay invalidate ptw.io.mem.resp.bits.mask invalidate ptw.io.mem.resp.bits.data invalidate ptw.io.mem.resp.bits.dv invalidate ptw.io.mem.resp.bits.dprv invalidate ptw.io.mem.resp.bits.signed invalidate ptw.io.mem.resp.bits.size invalidate ptw.io.mem.resp.bits.cmd invalidate ptw.io.mem.resp.bits.tag invalidate ptw.io.mem.resp.bits.addr invalidate ptw.io.mem.resp.valid invalidate ptw.io.mem.s2_paddr invalidate ptw.io.mem.s2_uncached invalidate ptw.io.mem.s2_kill invalidate ptw.io.mem.s2_nack_cause_raw invalidate ptw.io.mem.s2_nack invalidate ptw.io.mem.s1_data.mask invalidate ptw.io.mem.s1_data.data invalidate ptw.io.mem.s1_kill invalidate ptw.io.mem.req.bits.mask invalidate ptw.io.mem.req.bits.data invalidate ptw.io.mem.req.bits.no_xcpt invalidate ptw.io.mem.req.bits.no_alloc invalidate ptw.io.mem.req.bits.no_resp invalidate ptw.io.mem.req.bits.phys invalidate ptw.io.mem.req.bits.dv invalidate ptw.io.mem.req.bits.dprv invalidate ptw.io.mem.req.bits.signed invalidate ptw.io.mem.req.bits.size invalidate ptw.io.mem.req.bits.cmd invalidate ptw.io.mem.req.bits.tag invalidate ptw.io.mem.req.bits.addr invalidate ptw.io.mem.req.valid invalidate ptw.io.mem.req.ready inst respArb of RRArbiter connect respArb.clock, clock connect respArb.reset, reset inst cmdRouter of RoccCommandRouter connect cmdRouter.clock, clock connect cmdRouter.reset, reset connect zstd_compressor.io.cmd, cmdRouter.io.out[0] inst dcIF of SimpleHellaCacheIF connect dcIF.clock, clock connect dcIF.reset, reset connect dcIF.io.requestor, zstd_compressor.io.mem inst respArb_io_in_0_q of Queue2_RoCCResponse connect respArb_io_in_0_q.clock, clock connect respArb_io_in_0_q.reset, reset connect respArb_io_in_0_q.io.enq.valid, zstd_compressor.io.resp.valid connect respArb_io_in_0_q.io.enq.bits.data, zstd_compressor.io.resp.bits.data connect respArb_io_in_0_q.io.enq.bits.rd, zstd_compressor.io.resp.bits.rd connect zstd_compressor.io.resp.ready, respArb_io_in_0_q.io.enq.ready connect respArb.io.in[0], respArb_io_in_0_q.io.deq inst core of Rocket connect core.clock, clock connect core.reset, reset invalidate core.io.reset_vector connect haltNodeOut[0], UInt<1>(0h0) connect ceaseNodeOut[0], UInt<1>(0h0) regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0) connect wfiNodeOut_0_REG, core.io.wfi connect wfiNodeOut[0], wfiNodeOut_0_REG connect core.io.interrupts.debug, intSinkNodeIn[0] connect core.io.interrupts.msip, intSinkNodeIn[1] connect core.io.interrupts.mtip, intSinkNodeIn[2] connect core.io.interrupts.meip, intSinkNodeIn[3] connect core.io.interrupts.seip, intSinkNodeIn[4] connect traceSourceNodeOut, core.io.trace connect core.io.traceStall, traceAuxSinkNodeIn.stall connect bpwatchSourceNodeOut, core.io.bpwatch connect core.io.hartid, hartIdSinkNodeIn connect frontend.io.cpu, core.io.imem connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt connect core.io.fpu.dec.div, fpuOpt.io.dec.div connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23 connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12 connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3 connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2 connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1 connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst connect fpuOpt.io.killm, core.io.fpu.killm connect fpuOpt.io.killx, core.io.fpu.killx connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy connect fpuOpt.io.valid, core.io.fpu.valid connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val connect core.io.fpu.toint_data, fpuOpt.io.toint_data connect core.io.fpu.store_data, fpuOpt.io.store_data connect fpuOpt.io.v_sew, core.io.fpu.v_sew connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data connect fpuOpt.io.inst, core.io.fpu.inst connect fpuOpt.io.time, core.io.fpu.time connect fpuOpt.io.hartid, core.io.fpu.hartid connect core.io.ptw, ptw.io.dpath connect cmdRouter.io.in, core.io.rocc.cmd connect zstd_compressor.io.exception, core.io.rocc.exception invalidate zstd_compressor.io.fpu_req.ready invalidate zstd_compressor.io.fpu_resp.valid invalidate zstd_compressor.io.fpu_resp.bits.data invalidate zstd_compressor.io.fpu_resp.bits.exc connect core.io.rocc.resp, respArb.io.out node _core_io_rocc_busy_T = or(cmdRouter.io.busy, zstd_compressor.io.busy) connect core.io.rocc.busy, _core_io_rocc_busy_T connect core.io.rocc.interrupt, zstd_compressor.io.interrupt invalidate core.io.rocc.mem.clock_enabled invalidate core.io.rocc.mem.keep_clock_enabled invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad invalidate core.io.rocc.mem.perf.blocked invalidate core.io.rocc.mem.perf.tlbMiss invalidate core.io.rocc.mem.perf.grant invalidate core.io.rocc.mem.perf.release invalidate core.io.rocc.mem.perf.acquire invalidate core.io.rocc.mem.store_pending invalidate core.io.rocc.mem.ordered invalidate core.io.rocc.mem.s2_gpa_is_pte invalidate core.io.rocc.mem.s2_gpa invalidate core.io.rocc.mem.s2_xcpt.ae.st invalidate core.io.rocc.mem.s2_xcpt.ae.ld invalidate core.io.rocc.mem.s2_xcpt.gf.st invalidate core.io.rocc.mem.s2_xcpt.gf.ld invalidate core.io.rocc.mem.s2_xcpt.pf.st invalidate core.io.rocc.mem.s2_xcpt.pf.ld invalidate core.io.rocc.mem.s2_xcpt.ma.st invalidate core.io.rocc.mem.s2_xcpt.ma.ld invalidate core.io.rocc.mem.replay_next invalidate core.io.rocc.mem.resp.bits.store_data invalidate core.io.rocc.mem.resp.bits.data_raw invalidate core.io.rocc.mem.resp.bits.data_word_bypass invalidate core.io.rocc.mem.resp.bits.has_data invalidate core.io.rocc.mem.resp.bits.replay invalidate core.io.rocc.mem.resp.bits.mask invalidate core.io.rocc.mem.resp.bits.data invalidate core.io.rocc.mem.resp.bits.dv invalidate core.io.rocc.mem.resp.bits.dprv invalidate core.io.rocc.mem.resp.bits.signed invalidate core.io.rocc.mem.resp.bits.size invalidate core.io.rocc.mem.resp.bits.cmd invalidate core.io.rocc.mem.resp.bits.tag invalidate core.io.rocc.mem.resp.bits.addr invalidate core.io.rocc.mem.resp.valid invalidate core.io.rocc.mem.s2_paddr invalidate core.io.rocc.mem.s2_uncached invalidate core.io.rocc.mem.s2_kill invalidate core.io.rocc.mem.s2_nack_cause_raw invalidate core.io.rocc.mem.s2_nack invalidate core.io.rocc.mem.s1_data.mask invalidate core.io.rocc.mem.s1_data.data invalidate core.io.rocc.mem.s1_kill invalidate core.io.rocc.mem.req.bits.mask invalidate core.io.rocc.mem.req.bits.data invalidate core.io.rocc.mem.req.bits.no_xcpt invalidate core.io.rocc.mem.req.bits.no_alloc invalidate core.io.rocc.mem.req.bits.no_resp invalidate core.io.rocc.mem.req.bits.phys invalidate core.io.rocc.mem.req.bits.dv invalidate core.io.rocc.mem.req.bits.dprv invalidate core.io.rocc.mem.req.bits.signed invalidate core.io.rocc.mem.req.bits.size invalidate core.io.rocc.mem.req.bits.cmd invalidate core.io.rocc.mem.req.bits.tag invalidate core.io.rocc.mem.req.bits.addr invalidate core.io.rocc.mem.req.valid invalidate core.io.rocc.mem.req.ready connect dcacheArb.io.requestor[0], ptw.io.mem connect dcacheArb.io.requestor[1], dcIF.io.cache connect dcacheArb.io.requestor[2], core.io.dmem connect ptw.io.requestor[0], zstd_compressor.io.ptw[0] connect ptw.io.requestor[1], zstd_compressor.io.ptw[1] connect ptw.io.requestor[2], zstd_compressor.io.ptw[2] connect ptw.io.requestor[3], zstd_compressor.io.ptw[3] connect ptw.io.requestor[4], zstd_compressor.io.ptw[4] connect ptw.io.requestor[5], zstd_compressor.io.ptw[5] connect ptw.io.requestor[6], zstd_compressor.io.ptw[6] connect ptw.io.requestor[7], zstd_compressor.io.ptw[7] connect ptw.io.requestor[8], zstd_compressor.io.ptw[8] connect ptw.io.requestor[9], zstd_compressor.io.ptw[9] connect ptw.io.requestor[10], zstd_compressor.io.ptw[10] connect ptw.io.requestor[11], zstd_compressor.io.ptw[11] connect ptw.io.requestor[12], zstd_compressor.io.ptw[12] connect ptw.io.requestor[13], zstd_compressor.io.ptw[13] connect ptw.io.requestor[14], zstd_compressor.io.ptw[14] connect ptw.io.requestor[15], zstd_compressor.io.ptw[15] connect ptw.io.requestor[16], zstd_compressor.io.ptw[16] connect ptw.io.requestor[17], zstd_compressor.io.ptw[17] connect ptw.io.requestor[18], dcache.io.ptw connect ptw.io.requestor[19], frontend.io.ptw

module RocketTile( // @[RocketTile.scala:141:7] input clock, // @[RocketTile.scala:141:7] input reset, // @[RocketTile.scala:141:7] input auto_buffer_out_18_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_18_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_18_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_18_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_18_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_18_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_18_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_18_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_18_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_18_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_18_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_18_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_18_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_18_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_18_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_18_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_18_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_18_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_18_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_18_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_18_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_17_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_17_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_17_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_17_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_17_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_17_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_17_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_17_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_17_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_17_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_17_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_17_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_16_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_16_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_16_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_16_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_16_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_16_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_16_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_16_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_16_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_16_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_16_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_16_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_15_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_15_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_15_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_15_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_15_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_15_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_15_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_15_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_15_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_15_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_15_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_15_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_14_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_14_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_14_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_14_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_14_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_14_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_14_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_14_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_14_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_14_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_14_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_14_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_13_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_13_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_13_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_13_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_13_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_13_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_13_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_13_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_13_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_13_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_13_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_13_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_12_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_12_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_12_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_12_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_12_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_12_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_12_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_12_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_12_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_12_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_12_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_12_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_11_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_11_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_11_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_11_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_11_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_11_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_11_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_11_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_11_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_11_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_11_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_11_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_10_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_10_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_10_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_10_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_10_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_10_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_10_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_10_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_10_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_10_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_10_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_10_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_9_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_9_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_9_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_9_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_9_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_9_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_9_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_9_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_9_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_9_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_9_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_9_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_8_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_8_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_8_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_8_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_8_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_8_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_8_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_8_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_8_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_8_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_8_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_8_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_buffer_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_buffer_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25] output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25] output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25] output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25] output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25] output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25] input auto_hartid_in // @[LazyModuleImp.scala:107:25] ); wire _core_io_rocc_busy_T; // @[RocketTile.scala:213:49] wire buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_2_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_2_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_2_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_2_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_2_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_2_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_2_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_2_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_2_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_2_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_3_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_3_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_3_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_3_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_3_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_3_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_3_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_3_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_3_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_3_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_4_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_4_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_4_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_4_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_4_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_4_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_4_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_4_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_4_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_4_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_5_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_5_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_5_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_5_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_5_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_5_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_5_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_5_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_5_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_5_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_6_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_6_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_6_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_6_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_6_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_6_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_6_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_6_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_6_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_6_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_7_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_7_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_7_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_7_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_7_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_7_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_7_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_7_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_7_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_7_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_8_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_8_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_8_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_8_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_8_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_8_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_8_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_8_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_9_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_9_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_9_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_9_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_9_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_9_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_9_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_9_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_10_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_10_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_10_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_10_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_10_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_10_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_10_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_10_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_10_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_10_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_11_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_11_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_11_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_11_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_11_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_11_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_11_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_11_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_11_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_11_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_12_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_12_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_12_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_12_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_12_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_12_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_12_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_12_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_12_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_12_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_13_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_13_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_13_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_13_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_13_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_13_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_13_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_13_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_13_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_13_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_14_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_14_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_14_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_14_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_14_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_14_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_14_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_14_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_14_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_14_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_15_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_15_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_15_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_15_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_15_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_15_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_15_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_15_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_15_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_15_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_16_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_16_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_16_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_16_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_16_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_16_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_16_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_16_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_16_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_16_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_17_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_d_bits_sink; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_17_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_17_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_17_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_17_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_17_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_17_a_bits_address; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_in_17_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_17_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_17_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_e_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_e_ready; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_in_18_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_d_bits_sink; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_c_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_c_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_c_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_b_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_18_b_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_b_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_b_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_b_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_b_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_18_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_18_a_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_18_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_18_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_in_18_a_bits_address; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_18_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_in_18_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_18_a_bits_opcode; // @[Buffer.scala:40:9] wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9] wire _core_io_imem_might_request; // @[RocketTile.scala:147:20] wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20] wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20] wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20] wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20] wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20] wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20] wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20] wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20] wire _core_io_imem_progress; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20] wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20] wire [7:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20] wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20] wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20] wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20] wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20] wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20] wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20] wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20] wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20] wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20] wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20] wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20] wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20] wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20] wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20] wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20] wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20] wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20] wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20] wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20] wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20] wire _core_io_fpu_hartid; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20] wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20] wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20] wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20] wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20] wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20] wire _core_io_fpu_valid; // @[RocketTile.scala:147:20] wire _core_io_fpu_killx; // @[RocketTile.scala:147:20] wire _core_io_fpu_killm; // @[RocketTile.scala:147:20] wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_valid; // @[RocketTile.scala:147:20] wire [6:0] _core_io_rocc_cmd_bits_inst_funct; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rs2; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rs1; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xd; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xs1; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_inst_xs2; // @[RocketTile.scala:147:20] wire [4:0] _core_io_rocc_cmd_bits_inst_rd; // @[RocketTile.scala:147:20] wire [6:0] _core_io_rocc_cmd_bits_inst_opcode; // @[RocketTile.scala:147:20] wire [63:0] _core_io_rocc_cmd_bits_rs1; // @[RocketTile.scala:147:20] wire [63:0] _core_io_rocc_cmd_bits_rs2; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_debug; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_cease; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_wfi; // @[RocketTile.scala:147:20] wire [31:0] _core_io_rocc_cmd_bits_status_isa; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_dprv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_dv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_prv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_v; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mpv; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_gva; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tsr; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tw; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_tvm; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mxr; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_sum; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mprv; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_fs; // @[RocketTile.scala:147:20] wire [1:0] _core_io_rocc_cmd_bits_status_mpp; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_spp; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mpie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_spie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_mie; // @[RocketTile.scala:147:20] wire _core_io_rocc_cmd_bits_status_sie; // @[RocketTile.scala:147:20] wire _core_io_rocc_resp_ready; // @[RocketTile.scala:147:20] wire _core_io_rocc_exception; // @[RocketTile.scala:147:20] wire _core_io_wfi; // @[RocketTile.scala:147:20] wire _respArb_io_in_0_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _respArb_io_in_0_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [4:0] _respArb_io_in_0_q_io_deq_bits_rd; // @[Decoupled.scala:362:21] wire [63:0] _respArb_io_in_0_q_io_deq_bits_data; // @[Decoupled.scala:362:21] wire _dcIF_io_requestor_req_ready; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_valid; // @[LazyRoCC.scala:106:24] wire [39:0] _dcIF_io_requestor_resp_bits_addr; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_requestor_resp_bits_tag; // @[LazyRoCC.scala:106:24] wire [4:0] _dcIF_io_requestor_resp_bits_cmd; // @[LazyRoCC.scala:106:24] wire [1:0] _dcIF_io_requestor_resp_bits_size; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_signed; // @[LazyRoCC.scala:106:24] wire [1:0] _dcIF_io_requestor_resp_bits_dprv; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_dv; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_requestor_resp_bits_mask; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_replay; // @[LazyRoCC.scala:106:24] wire _dcIF_io_requestor_resp_bits_has_data; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data_word_bypass; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_data_raw; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_requestor_resp_bits_store_data; // @[LazyRoCC.scala:106:24] wire _dcIF_io_cache_req_valid; // @[LazyRoCC.scala:106:24] wire [63:0] _dcIF_io_cache_s1_data_data; // @[LazyRoCC.scala:106:24] wire [7:0] _dcIF_io_cache_s1_data_mask; // @[LazyRoCC.scala:106:24] wire _cmdRouter_io_in_ready; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_valid; // @[LazyRoCC.scala:102:27] wire [6:0] _cmdRouter_io_out_0_bits_inst_funct; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rs2; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rs1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xd; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xs1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_inst_xs2; // @[LazyRoCC.scala:102:27] wire [4:0] _cmdRouter_io_out_0_bits_inst_rd; // @[LazyRoCC.scala:102:27] wire [6:0] _cmdRouter_io_out_0_bits_inst_opcode; // @[LazyRoCC.scala:102:27] wire [63:0] _cmdRouter_io_out_0_bits_rs1; // @[LazyRoCC.scala:102:27] wire [63:0] _cmdRouter_io_out_0_bits_rs2; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_debug; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_cease; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_wfi; // @[LazyRoCC.scala:102:27] wire [31:0] _cmdRouter_io_out_0_bits_status_isa; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_dprv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_dv; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_prv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_v; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sd; // @[LazyRoCC.scala:102:27] wire [22:0] _cmdRouter_io_out_0_bits_status_zero2; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mpv; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_gva; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mbe; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sbe; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_sxl; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_uxl; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sd_rv32; // @[LazyRoCC.scala:102:27] wire [7:0] _cmdRouter_io_out_0_bits_status_zero1; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tsr; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tw; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_tvm; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mxr; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sum; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mprv; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_xs; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_fs; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_mpp; // @[LazyRoCC.scala:102:27] wire [1:0] _cmdRouter_io_out_0_bits_status_vs; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_spp; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mpie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_ube; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_spie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_upie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_mie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_hie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_sie; // @[LazyRoCC.scala:102:27] wire _cmdRouter_io_out_0_bits_status_uie; // @[LazyRoCC.scala:102:27] wire _respArb_io_in_0_ready; // @[LazyRoCC.scala:101:25] wire _respArb_io_out_valid; // @[LazyRoCC.scala:101:25] wire [4:0] _respArb_io_out_bits_rd; // @[LazyRoCC.scala:101:25] wire [63:0] _respArb_io_out_bits_data; // @[LazyRoCC.scala:101:25] wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_2_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_2_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_2_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_3_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_3_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_3_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_3_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_3_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_3_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_3_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_3_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_3_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_3_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_3_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_3_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_4_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_4_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_4_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_4_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_4_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_4_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_4_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_4_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_4_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_4_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_4_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_4_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_5_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_5_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_5_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_5_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_5_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_5_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_5_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_5_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_5_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_5_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_5_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_5_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_6_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_6_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_6_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_6_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_6_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_6_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_6_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_6_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_6_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_6_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_6_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_6_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_7_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_7_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_7_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_7_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_7_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_7_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_7_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_7_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_7_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_7_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_7_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_7_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_8_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_8_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_8_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_8_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_8_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_8_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_8_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_8_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_8_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_8_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_8_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_8_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_9_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_9_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_9_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_9_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_9_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_9_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_9_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_9_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_9_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_9_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_9_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_9_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_10_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_10_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_10_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_10_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_10_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_10_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_10_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_10_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_10_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_10_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_10_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_10_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_11_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_11_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_11_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_11_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_11_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_11_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_11_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_11_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_11_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_11_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_11_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_11_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_12_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_12_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_12_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_12_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_12_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_12_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_12_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_12_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_12_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_12_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_12_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_12_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_13_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_13_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_13_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_13_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_13_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_13_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_13_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_13_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_13_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_13_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_13_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_13_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_14_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_14_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_14_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_14_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_14_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_14_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_14_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_14_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_14_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_14_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_14_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_14_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_15_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_15_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_15_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_15_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_15_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_15_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_15_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_15_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_15_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_15_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_15_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_15_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_16_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_16_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_16_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_16_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_16_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_16_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_16_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_16_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_16_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_16_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_16_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_16_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_17_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_17_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_17_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_17_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_17_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_17_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_17_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_17_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_17_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_17_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_17_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_17_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_18_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_18_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_18_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_18_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_18_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_18_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_18_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_18_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_18_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_18_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_18_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_18_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_req_ready; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_valid; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_ae_ptw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_ae_final; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pf; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gf; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_hx; // @[PTW.scala:802:19] wire [9:0] _ptw_io_requestor_19_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_19_resp_bits_pte_ppn; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_d; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_g; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_u; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_r; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_pte_v; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_resp_bits_level; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_homogeneous; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gpa_valid; // @[PTW.scala:802:19] wire [38:0] _ptw_io_requestor_19_resp_bits_gpa_bits; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_resp_bits_gpa_is_pte; // @[PTW.scala:802:19] wire [3:0] _ptw_io_requestor_19_ptbr_mode; // @[PTW.scala:802:19] wire [43:0] _ptw_io_requestor_19_ptbr_ppn; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_status_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_v; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_status_mpp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_status_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_spvp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_spv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_hstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_debug; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_cease; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_wfi; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_gstatus_isa; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_dprv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_dv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_prv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_v; // @[PTW.scala:802:19] wire [22:0] _ptw_io_requestor_19_gstatus_zero2; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mpv; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_gva; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mbe; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sbe; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_sxl; // @[PTW.scala:802:19] wire [7:0] _ptw_io_requestor_19_gstatus_zero1; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tsr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tw; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_tvm; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mxr; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sum; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mprv; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_fs; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_mpp; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_gstatus_vs; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_spp; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mpie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_ube; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_spie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_upie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_mie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_hie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_sie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_gstatus_uie; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_0_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_0_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_0_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_0_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_1_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_1_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_1_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_1_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_2_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_2_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_2_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_2_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_3_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_3_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_3_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_3_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_4_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_4_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_4_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_4_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_5_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_5_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_5_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_5_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_6_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_6_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_6_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_6_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_l; // @[PTW.scala:802:19] wire [1:0] _ptw_io_requestor_19_pmp_7_cfg_a; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_x; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_w; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_pmp_7_cfg_r; // @[PTW.scala:802:19] wire [29:0] _ptw_io_requestor_19_pmp_7_addr; // @[PTW.scala:802:19] wire [31:0] _ptw_io_requestor_19_pmp_7_mask; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_0_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_0_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_0_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_1_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_1_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_1_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_2_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_2_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_2_value; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_3_ren; // @[PTW.scala:802:19] wire _ptw_io_requestor_19_customCSRs_csrs_3_wen; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19] wire [63:0] _ptw_io_requestor_19_customCSRs_csrs_3_value; // @[PTW.scala:802:19] wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19] wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19] wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19] wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19] wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19] wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19] wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_req_ready; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_nack_cause_raw; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_uncached; // @[HellaCache.scala:292:25] wire [31:0] _dcacheArb_io_requestor_2_s2_paddr; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_2_resp_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_requestor_2_resp_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_2_resp_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_requestor_2_resp_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_dv; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_requestor_2_resp_bits_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_replay; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_resp_bits_has_data; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_raw; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_requestor_2_resp_bits_store_data; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_replay_next; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ma_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_pf_st; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_s2_xcpt_ae_st; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_requestor_2_s2_gpa; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_ordered; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_store_pending; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_acquire; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_release; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_grant; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_tlbMiss; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_blocked; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25] wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25] wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala:292:25] wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25] wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62] wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62] wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62] wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62] wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62] wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62] wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62] wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62] wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62] wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28] wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28] wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28] wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28] wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28] wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28] wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28] wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28] wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28] wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28] wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28] wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28] wire _zstd_compressor_io_cmd_ready; // @[Configs.scala:62:39] wire _zstd_compressor_io_resp_valid; // @[Configs.scala:62:39] wire [4:0] _zstd_compressor_io_resp_bits_rd; // @[Configs.scala:62:39] wire [63:0] _zstd_compressor_io_resp_bits_data; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_0_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_0_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_0_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_1_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_1_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_1_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_2_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_2_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_2_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_3_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_3_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_3_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_4_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_4_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_4_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_5_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_5_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_5_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_6_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_6_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_6_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_7_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_7_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_7_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_8_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_8_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_8_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_9_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_9_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_9_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_10_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_10_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_10_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_11_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_11_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_11_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_12_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_12_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_12_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_13_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_13_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_13_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_14_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_14_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_14_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_15_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_15_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_15_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_16_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_16_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_16_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_17_req_valid; // @[Configs.scala:62:39] wire [26:0] _zstd_compressor_io_ptw_17_req_bits_bits_addr; // @[Configs.scala:62:39] wire _zstd_compressor_io_ptw_17_req_bits_bits_need_gpa; // @[Configs.scala:62:39] wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43] wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43] wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43] wire auto_buffer_out_18_a_ready_0 = auto_buffer_out_18_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_valid_0 = auto_buffer_out_18_b_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_b_bits_opcode_0 = auto_buffer_out_18_b_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_b_bits_param_0 = auto_buffer_out_18_b_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_b_bits_size_0 = auto_buffer_out_18_b_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_b_bits_source_0 = auto_buffer_out_18_b_bits_source; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_b_bits_address_0 = auto_buffer_out_18_b_bits_address; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_18_b_bits_mask_0 = auto_buffer_out_18_b_bits_mask; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_b_bits_data_0 = auto_buffer_out_18_b_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_bits_corrupt_0 = auto_buffer_out_18_b_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_ready_0 = auto_buffer_out_18_c_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_valid_0 = auto_buffer_out_18_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_d_bits_opcode_0 = auto_buffer_out_18_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_d_bits_param_0 = auto_buffer_out_18_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_d_bits_size_0 = auto_buffer_out_18_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_d_bits_source_0 = auto_buffer_out_18_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_d_bits_sink_0 = auto_buffer_out_18_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_bits_denied_0 = auto_buffer_out_18_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_d_bits_data_0 = auto_buffer_out_18_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_bits_corrupt_0 = auto_buffer_out_18_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_e_ready_0 = auto_buffer_out_18_e_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_ready_0 = auto_buffer_out_17_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_valid_0 = auto_buffer_out_17_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_d_bits_opcode_0 = auto_buffer_out_17_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_17_d_bits_param_0 = auto_buffer_out_17_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_17_d_bits_size_0 = auto_buffer_out_17_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_17_d_bits_source_0 = auto_buffer_out_17_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_d_bits_sink_0 = auto_buffer_out_17_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_bits_denied_0 = auto_buffer_out_17_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_17_d_bits_data_0 = auto_buffer_out_17_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_bits_corrupt_0 = auto_buffer_out_17_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_ready_0 = auto_buffer_out_16_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_valid_0 = auto_buffer_out_16_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_d_bits_opcode_0 = auto_buffer_out_16_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_16_d_bits_param_0 = auto_buffer_out_16_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_16_d_bits_size_0 = auto_buffer_out_16_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_16_d_bits_source_0 = auto_buffer_out_16_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_d_bits_sink_0 = auto_buffer_out_16_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_bits_denied_0 = auto_buffer_out_16_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_16_d_bits_data_0 = auto_buffer_out_16_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_bits_corrupt_0 = auto_buffer_out_16_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_ready_0 = auto_buffer_out_15_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_valid_0 = auto_buffer_out_15_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_d_bits_opcode_0 = auto_buffer_out_15_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_15_d_bits_param_0 = auto_buffer_out_15_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_15_d_bits_size_0 = auto_buffer_out_15_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_15_d_bits_source_0 = auto_buffer_out_15_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_d_bits_sink_0 = auto_buffer_out_15_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_bits_denied_0 = auto_buffer_out_15_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_15_d_bits_data_0 = auto_buffer_out_15_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_bits_corrupt_0 = auto_buffer_out_15_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_ready_0 = auto_buffer_out_14_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_valid_0 = auto_buffer_out_14_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_d_bits_opcode_0 = auto_buffer_out_14_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_14_d_bits_param_0 = auto_buffer_out_14_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_14_d_bits_size_0 = auto_buffer_out_14_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_14_d_bits_source_0 = auto_buffer_out_14_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_d_bits_sink_0 = auto_buffer_out_14_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_bits_denied_0 = auto_buffer_out_14_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_14_d_bits_data_0 = auto_buffer_out_14_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_bits_corrupt_0 = auto_buffer_out_14_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_ready_0 = auto_buffer_out_13_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_valid_0 = auto_buffer_out_13_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_d_bits_opcode_0 = auto_buffer_out_13_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_13_d_bits_param_0 = auto_buffer_out_13_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_13_d_bits_size_0 = auto_buffer_out_13_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_13_d_bits_source_0 = auto_buffer_out_13_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_d_bits_sink_0 = auto_buffer_out_13_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_bits_denied_0 = auto_buffer_out_13_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_13_d_bits_data_0 = auto_buffer_out_13_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_bits_corrupt_0 = auto_buffer_out_13_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_ready_0 = auto_buffer_out_12_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_valid_0 = auto_buffer_out_12_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_d_bits_opcode_0 = auto_buffer_out_12_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_12_d_bits_param_0 = auto_buffer_out_12_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_12_d_bits_size_0 = auto_buffer_out_12_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_12_d_bits_source_0 = auto_buffer_out_12_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_d_bits_sink_0 = auto_buffer_out_12_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_bits_denied_0 = auto_buffer_out_12_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_12_d_bits_data_0 = auto_buffer_out_12_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_bits_corrupt_0 = auto_buffer_out_12_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_ready_0 = auto_buffer_out_11_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_valid_0 = auto_buffer_out_11_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_d_bits_opcode_0 = auto_buffer_out_11_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_11_d_bits_param_0 = auto_buffer_out_11_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_11_d_bits_size_0 = auto_buffer_out_11_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_11_d_bits_source_0 = auto_buffer_out_11_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_d_bits_sink_0 = auto_buffer_out_11_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_bits_denied_0 = auto_buffer_out_11_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_11_d_bits_data_0 = auto_buffer_out_11_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_bits_corrupt_0 = auto_buffer_out_11_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_ready_0 = auto_buffer_out_10_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_valid_0 = auto_buffer_out_10_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_d_bits_opcode_0 = auto_buffer_out_10_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_10_d_bits_param_0 = auto_buffer_out_10_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_10_d_bits_size_0 = auto_buffer_out_10_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_10_d_bits_source_0 = auto_buffer_out_10_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_d_bits_sink_0 = auto_buffer_out_10_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_bits_denied_0 = auto_buffer_out_10_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_10_d_bits_data_0 = auto_buffer_out_10_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_bits_corrupt_0 = auto_buffer_out_10_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_ready_0 = auto_buffer_out_9_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_valid_0 = auto_buffer_out_9_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_d_bits_opcode_0 = auto_buffer_out_9_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_d_bits_param_0 = auto_buffer_out_9_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_9_d_bits_size_0 = auto_buffer_out_9_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_d_bits_source_0 = auto_buffer_out_9_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_d_bits_sink_0 = auto_buffer_out_9_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_bits_denied_0 = auto_buffer_out_9_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_9_d_bits_data_0 = auto_buffer_out_9_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_bits_corrupt_0 = auto_buffer_out_9_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_ready_0 = auto_buffer_out_8_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_valid_0 = auto_buffer_out_8_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_d_bits_opcode_0 = auto_buffer_out_8_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_d_bits_param_0 = auto_buffer_out_8_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_8_d_bits_size_0 = auto_buffer_out_8_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_d_bits_source_0 = auto_buffer_out_8_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_d_bits_sink_0 = auto_buffer_out_8_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_bits_denied_0 = auto_buffer_out_8_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_8_d_bits_data_0 = auto_buffer_out_8_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_bits_corrupt_0 = auto_buffer_out_8_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_ready_0 = auto_buffer_out_7_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_valid_0 = auto_buffer_out_7_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_d_bits_opcode_0 = auto_buffer_out_7_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_7_d_bits_param_0 = auto_buffer_out_7_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_7_d_bits_size_0 = auto_buffer_out_7_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_7_d_bits_source_0 = auto_buffer_out_7_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_d_bits_sink_0 = auto_buffer_out_7_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_bits_denied_0 = auto_buffer_out_7_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_7_d_bits_data_0 = auto_buffer_out_7_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_bits_corrupt_0 = auto_buffer_out_7_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_ready_0 = auto_buffer_out_6_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_valid_0 = auto_buffer_out_6_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_d_bits_opcode_0 = auto_buffer_out_6_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_6_d_bits_param_0 = auto_buffer_out_6_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_6_d_bits_size_0 = auto_buffer_out_6_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_6_d_bits_source_0 = auto_buffer_out_6_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_d_bits_sink_0 = auto_buffer_out_6_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_bits_denied_0 = auto_buffer_out_6_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_6_d_bits_data_0 = auto_buffer_out_6_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_bits_corrupt_0 = auto_buffer_out_6_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_ready_0 = auto_buffer_out_5_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_valid_0 = auto_buffer_out_5_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_d_bits_opcode_0 = auto_buffer_out_5_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_5_d_bits_param_0 = auto_buffer_out_5_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_5_d_bits_size_0 = auto_buffer_out_5_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_5_d_bits_source_0 = auto_buffer_out_5_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_d_bits_sink_0 = auto_buffer_out_5_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_bits_denied_0 = auto_buffer_out_5_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_5_d_bits_data_0 = auto_buffer_out_5_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_bits_corrupt_0 = auto_buffer_out_5_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_ready_0 = auto_buffer_out_4_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_valid_0 = auto_buffer_out_4_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_d_bits_opcode_0 = auto_buffer_out_4_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_4_d_bits_param_0 = auto_buffer_out_4_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_4_d_bits_size_0 = auto_buffer_out_4_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_4_d_bits_source_0 = auto_buffer_out_4_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_d_bits_sink_0 = auto_buffer_out_4_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_bits_denied_0 = auto_buffer_out_4_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_4_d_bits_data_0 = auto_buffer_out_4_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_bits_corrupt_0 = auto_buffer_out_4_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_ready_0 = auto_buffer_out_3_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_valid_0 = auto_buffer_out_3_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_d_bits_opcode_0 = auto_buffer_out_3_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_3_d_bits_param_0 = auto_buffer_out_3_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_3_d_bits_size_0 = auto_buffer_out_3_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_3_d_bits_source_0 = auto_buffer_out_3_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_d_bits_sink_0 = auto_buffer_out_3_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_bits_denied_0 = auto_buffer_out_3_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_3_d_bits_data_0 = auto_buffer_out_3_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_bits_corrupt_0 = auto_buffer_out_3_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_ready_0 = auto_buffer_out_2_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_valid_0 = auto_buffer_out_2_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_d_bits_opcode_0 = auto_buffer_out_2_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_2_d_bits_param_0 = auto_buffer_out_2_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_2_d_bits_size_0 = auto_buffer_out_2_d_bits_size; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_2_d_bits_source_0 = auto_buffer_out_2_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_d_bits_sink_0 = auto_buffer_out_2_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_bits_denied_0 = auto_buffer_out_2_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_2_d_bits_data_0 = auto_buffer_out_2_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_bits_corrupt_0 = auto_buffer_out_2_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_ready_0 = auto_buffer_out_1_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_valid_0 = auto_buffer_out_1_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_d_bits_opcode_0 = auto_buffer_out_1_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_d_bits_param_0 = auto_buffer_out_1_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_1_d_bits_size_0 = auto_buffer_out_1_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_d_bits_source_0 = auto_buffer_out_1_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_d_bits_sink_0 = auto_buffer_out_1_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_bits_denied_0 = auto_buffer_out_1_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_1_d_bits_data_0 = auto_buffer_out_1_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_bits_corrupt_0 = auto_buffer_out_1_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_ready_0 = auto_buffer_out_0_a_ready; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_valid_0 = auto_buffer_out_0_d_valid; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_d_bits_opcode_0 = auto_buffer_out_0_d_bits_opcode; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_d_bits_param_0 = auto_buffer_out_0_d_bits_param; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_0_d_bits_size_0 = auto_buffer_out_0_d_bits_size; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_d_bits_source_0 = auto_buffer_out_0_d_bits_source; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_d_bits_sink_0 = auto_buffer_out_0_d_bits_sink; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_bits_denied_0 = auto_buffer_out_0_d_bits_denied; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_0_d_bits_data_0 = auto_buffer_out_0_d_bits_data; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_bits_corrupt_0 = auto_buffer_out_0_d_bits_corrupt; // @[RocketTile.scala:141:7] wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7] wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7] wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7] wire auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7] wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7] wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire buffer_auto_in_18_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_18_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_x1_nodeOut_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire buffer_x1_nodeIn_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_tlOtherMastersNodeOut_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire x1_tlOtherMastersNodeIn_17_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeIn_17_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19] wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19] wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17] wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17] wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17] wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_in_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_auto_anon_out_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonOut_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] widget_1_anonIn_a_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_out_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonIn_a_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7] wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7] wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7] wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9] wire buffer_auto_out_18_a_ready = auto_buffer_out_18_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_valid = auto_buffer_out_18_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_b_bits_opcode = auto_buffer_out_18_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_b_bits_param = auto_buffer_out_18_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_b_bits_size = auto_buffer_out_18_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_b_bits_source = auto_buffer_out_18_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_b_bits_address = auto_buffer_out_18_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_18_b_bits_mask = auto_buffer_out_18_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_b_bits_data = auto_buffer_out_18_b_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_b_bits_corrupt = auto_buffer_out_18_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_ready = auto_buffer_out_18_c_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_c_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_valid = auto_buffer_out_18_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_d_bits_opcode = auto_buffer_out_18_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_d_bits_param = auto_buffer_out_18_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_18_d_bits_size = auto_buffer_out_18_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_18_d_bits_source = auto_buffer_out_18_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_d_bits_sink = auto_buffer_out_18_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_bits_denied = auto_buffer_out_18_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_18_d_bits_data = auto_buffer_out_18_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_d_bits_corrupt = auto_buffer_out_18_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_e_ready = auto_buffer_out_18_e_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_ready = auto_buffer_out_17_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_17_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_valid = auto_buffer_out_17_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_d_bits_opcode = auto_buffer_out_17_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_17_d_bits_param = auto_buffer_out_17_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_17_d_bits_size = auto_buffer_out_17_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_17_d_bits_source = auto_buffer_out_17_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_17_d_bits_sink = auto_buffer_out_17_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_bits_denied = auto_buffer_out_17_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_17_d_bits_data = auto_buffer_out_17_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_17_d_bits_corrupt = auto_buffer_out_17_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_ready = auto_buffer_out_16_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_16_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_valid = auto_buffer_out_16_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_d_bits_opcode = auto_buffer_out_16_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_16_d_bits_param = auto_buffer_out_16_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_16_d_bits_size = auto_buffer_out_16_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_16_d_bits_source = auto_buffer_out_16_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_16_d_bits_sink = auto_buffer_out_16_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_bits_denied = auto_buffer_out_16_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_16_d_bits_data = auto_buffer_out_16_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_16_d_bits_corrupt = auto_buffer_out_16_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_ready = auto_buffer_out_15_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_15_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_valid = auto_buffer_out_15_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_d_bits_opcode = auto_buffer_out_15_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_15_d_bits_param = auto_buffer_out_15_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_15_d_bits_size = auto_buffer_out_15_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_15_d_bits_source = auto_buffer_out_15_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_15_d_bits_sink = auto_buffer_out_15_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_bits_denied = auto_buffer_out_15_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_15_d_bits_data = auto_buffer_out_15_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_15_d_bits_corrupt = auto_buffer_out_15_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_ready = auto_buffer_out_14_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_14_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_valid = auto_buffer_out_14_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_d_bits_opcode = auto_buffer_out_14_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_14_d_bits_param = auto_buffer_out_14_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_14_d_bits_size = auto_buffer_out_14_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_14_d_bits_source = auto_buffer_out_14_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_14_d_bits_sink = auto_buffer_out_14_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_bits_denied = auto_buffer_out_14_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_14_d_bits_data = auto_buffer_out_14_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_14_d_bits_corrupt = auto_buffer_out_14_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_ready = auto_buffer_out_13_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_13_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_valid = auto_buffer_out_13_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_d_bits_opcode = auto_buffer_out_13_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_13_d_bits_param = auto_buffer_out_13_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_13_d_bits_size = auto_buffer_out_13_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_13_d_bits_source = auto_buffer_out_13_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_13_d_bits_sink = auto_buffer_out_13_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_bits_denied = auto_buffer_out_13_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_13_d_bits_data = auto_buffer_out_13_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_13_d_bits_corrupt = auto_buffer_out_13_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_ready = auto_buffer_out_12_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_12_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_valid = auto_buffer_out_12_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_d_bits_opcode = auto_buffer_out_12_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_12_d_bits_param = auto_buffer_out_12_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_12_d_bits_size = auto_buffer_out_12_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_12_d_bits_source = auto_buffer_out_12_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_12_d_bits_sink = auto_buffer_out_12_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_bits_denied = auto_buffer_out_12_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_12_d_bits_data = auto_buffer_out_12_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_12_d_bits_corrupt = auto_buffer_out_12_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_ready = auto_buffer_out_11_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_11_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_valid = auto_buffer_out_11_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_d_bits_opcode = auto_buffer_out_11_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_11_d_bits_param = auto_buffer_out_11_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_11_d_bits_size = auto_buffer_out_11_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_11_d_bits_source = auto_buffer_out_11_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_11_d_bits_sink = auto_buffer_out_11_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_bits_denied = auto_buffer_out_11_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_11_d_bits_data = auto_buffer_out_11_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_11_d_bits_corrupt = auto_buffer_out_11_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_ready = auto_buffer_out_10_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_10_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_valid = auto_buffer_out_10_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_d_bits_opcode = auto_buffer_out_10_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_10_d_bits_param = auto_buffer_out_10_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_10_d_bits_size = auto_buffer_out_10_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_10_d_bits_source = auto_buffer_out_10_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_10_d_bits_sink = auto_buffer_out_10_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_bits_denied = auto_buffer_out_10_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_10_d_bits_data = auto_buffer_out_10_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_10_d_bits_corrupt = auto_buffer_out_10_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_ready = auto_buffer_out_9_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_9_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_valid = auto_buffer_out_9_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_d_bits_opcode = auto_buffer_out_9_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_d_bits_param = auto_buffer_out_9_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_9_d_bits_size = auto_buffer_out_9_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_9_d_bits_source = auto_buffer_out_9_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_9_d_bits_sink = auto_buffer_out_9_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_bits_denied = auto_buffer_out_9_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_9_d_bits_data = auto_buffer_out_9_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_9_d_bits_corrupt = auto_buffer_out_9_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_ready = auto_buffer_out_8_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_8_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_valid = auto_buffer_out_8_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_d_bits_opcode = auto_buffer_out_8_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_d_bits_param = auto_buffer_out_8_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_8_d_bits_size = auto_buffer_out_8_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_8_d_bits_source = auto_buffer_out_8_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_8_d_bits_sink = auto_buffer_out_8_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_bits_denied = auto_buffer_out_8_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_8_d_bits_data = auto_buffer_out_8_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_8_d_bits_corrupt = auto_buffer_out_8_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_ready = auto_buffer_out_7_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_7_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_valid = auto_buffer_out_7_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_d_bits_opcode = auto_buffer_out_7_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_7_d_bits_param = auto_buffer_out_7_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_7_d_bits_size = auto_buffer_out_7_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_7_d_bits_source = auto_buffer_out_7_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_7_d_bits_sink = auto_buffer_out_7_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_bits_denied = auto_buffer_out_7_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_7_d_bits_data = auto_buffer_out_7_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_7_d_bits_corrupt = auto_buffer_out_7_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_ready = auto_buffer_out_6_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_6_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_valid = auto_buffer_out_6_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_d_bits_opcode = auto_buffer_out_6_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_6_d_bits_param = auto_buffer_out_6_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_6_d_bits_size = auto_buffer_out_6_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_6_d_bits_source = auto_buffer_out_6_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_6_d_bits_sink = auto_buffer_out_6_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_bits_denied = auto_buffer_out_6_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_6_d_bits_data = auto_buffer_out_6_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_6_d_bits_corrupt = auto_buffer_out_6_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_ready = auto_buffer_out_5_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_5_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_valid = auto_buffer_out_5_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_d_bits_opcode = auto_buffer_out_5_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_5_d_bits_param = auto_buffer_out_5_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_5_d_bits_size = auto_buffer_out_5_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_5_d_bits_source = auto_buffer_out_5_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_5_d_bits_sink = auto_buffer_out_5_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_bits_denied = auto_buffer_out_5_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_5_d_bits_data = auto_buffer_out_5_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_5_d_bits_corrupt = auto_buffer_out_5_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_ready = auto_buffer_out_4_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_4_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_valid = auto_buffer_out_4_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_d_bits_opcode = auto_buffer_out_4_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_4_d_bits_param = auto_buffer_out_4_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_4_d_bits_size = auto_buffer_out_4_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_4_d_bits_source = auto_buffer_out_4_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_4_d_bits_sink = auto_buffer_out_4_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_bits_denied = auto_buffer_out_4_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_4_d_bits_data = auto_buffer_out_4_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_4_d_bits_corrupt = auto_buffer_out_4_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_ready = auto_buffer_out_3_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_3_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_valid = auto_buffer_out_3_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_d_bits_opcode = auto_buffer_out_3_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_3_d_bits_param = auto_buffer_out_3_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_3_d_bits_size = auto_buffer_out_3_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_3_d_bits_source = auto_buffer_out_3_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_3_d_bits_sink = auto_buffer_out_3_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_bits_denied = auto_buffer_out_3_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_3_d_bits_data = auto_buffer_out_3_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_3_d_bits_corrupt = auto_buffer_out_3_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_ready = auto_buffer_out_2_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_2_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_valid = auto_buffer_out_2_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_d_bits_opcode = auto_buffer_out_2_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_2_d_bits_param = auto_buffer_out_2_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_2_d_bits_size = auto_buffer_out_2_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] buffer_auto_out_2_d_bits_source = auto_buffer_out_2_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_2_d_bits_sink = auto_buffer_out_2_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_bits_denied = auto_buffer_out_2_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_2_d_bits_data = auto_buffer_out_2_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_2_d_bits_corrupt = auto_buffer_out_2_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_ready = auto_buffer_out_1_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_valid = auto_buffer_out_1_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_d_bits_opcode = auto_buffer_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_d_bits_param = auto_buffer_out_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_1_d_bits_size = auto_buffer_out_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_1_d_bits_source = auto_buffer_out_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_1_d_bits_sink = auto_buffer_out_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_bits_denied = auto_buffer_out_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_1_d_bits_data = auto_buffer_out_1_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_1_d_bits_corrupt = auto_buffer_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_ready = auto_buffer_out_0_a_ready_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9] wire buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_valid = auto_buffer_out_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_d_bits_opcode = auto_buffer_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_d_bits_param = auto_buffer_out_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] buffer_auto_out_0_d_bits_size = auto_buffer_out_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_0_d_bits_source = auto_buffer_out_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_0_d_bits_sink = auto_buffer_out_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_bits_denied = auto_buffer_out_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_0_d_bits_data = auto_buffer_out_0_d_bits_data_0; // @[Buffer.scala:40:9] wire buffer_auto_out_0_d_bits_corrupt = auto_buffer_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire wfiNodeOut_0; // @[MixedNode.scala:542:17] wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7] wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7] wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7] wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17] wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17] wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17] wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17] wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17] wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17] wire hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_18_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_b_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_c_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_c_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_18_c_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_18_c_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_18_c_bits_address_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_18_c_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_c_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_18_e_bits_sink_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_18_e_valid_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_17_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_17_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_17_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_17_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_17_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_17_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_17_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_16_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_16_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_16_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_16_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_16_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_16_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_16_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_15_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_15_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_15_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_15_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_15_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_15_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_15_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_14_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_14_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_14_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_14_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_14_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_14_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_14_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_13_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_13_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_13_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_13_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_13_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_13_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_13_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_12_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_12_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_12_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_12_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_12_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_12_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_12_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_11_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_11_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_11_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_11_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_11_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_11_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_11_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_10_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_10_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_10_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_10_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_10_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_10_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_10_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_9_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_9_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_9_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_9_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_9_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_9_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_9_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_8_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_8_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_8_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_8_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_8_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_8_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_8_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_7_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_7_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_7_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_7_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_7_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_7_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_7_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_6_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_6_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_6_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_6_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_6_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_6_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_6_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_5_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_5_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_5_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_5_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_5_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_5_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_5_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_4_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_4_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_4_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_4_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_4_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_4_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_4_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_3_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_3_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_3_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_3_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_3_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_3_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_3_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_2_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_2_a_bits_size_0; // @[RocketTile.scala:141:7] wire [4:0] auto_buffer_out_2_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_2_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_2_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_2_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_2_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7] wire [2:0] auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7] wire [3:0] auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7] wire [1:0] auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7] wire [31:0] auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7] wire [7:0] auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7] wire [63:0] auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7] wire auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7] wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] wire hartidOut; // @[MixedNode.scala:542:17] wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17] wire broadcast_nodeOut; // @[MixedNode.scala:542:17] wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9] wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17] assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17] wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17] wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire buffer_x1_nodeIn_17_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_a_ready = buffer_auto_in_18_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_a_valid = buffer_auto_in_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_a_bits_opcode = buffer_auto_in_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_a_bits_param = buffer_auto_in_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_17_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_17_a_bits_size = buffer_auto_in_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_17_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_17_a_bits_source = buffer_auto_in_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_17_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_17_a_bits_address = buffer_auto_in_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_17_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_17_a_bits_mask = buffer_auto_in_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_17_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_17_a_bits_data = buffer_auto_in_18_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_b_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_b_ready = buffer_auto_in_18_b_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_b_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_b_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_b_valid = buffer_auto_in_18_b_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_b_bits_opcode = buffer_auto_in_18_b_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_17_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_b_bits_param = buffer_auto_in_18_b_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_17_b_bits_size = buffer_auto_in_18_b_bits_size; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeIn_17_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_b_bits_source = buffer_auto_in_18_b_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeIn_17_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] x1_tlOtherMastersNodeOut_17_b_bits_address = buffer_auto_in_18_b_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_17_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] x1_tlOtherMastersNodeOut_17_b_bits_mask = buffer_auto_in_18_b_bits_mask; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_17_b_bits_data = buffer_auto_in_18_b_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_c_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_b_bits_corrupt = buffer_auto_in_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_c_ready = buffer_auto_in_18_c_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_c_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_c_valid = buffer_auto_in_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_c_bits_opcode = buffer_auto_in_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_17_c_bits_param = buffer_auto_in_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_17_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_17_c_bits_size = buffer_auto_in_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_17_c_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_17_c_bits_source = buffer_auto_in_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_17_c_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_17_c_bits_address = buffer_auto_in_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_17_c_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_17_c_bits_data = buffer_auto_in_18_c_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_d_ready = buffer_auto_in_18_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_valid = buffer_auto_in_18_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_d_bits_opcode = buffer_auto_in_18_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_17_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_d_bits_param = buffer_auto_in_18_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_17_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_17_d_bits_size = buffer_auto_in_18_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_17_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_17_d_bits_source = buffer_auto_in_18_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_17_d_bits_sink = buffer_auto_in_18_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_17_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_bits_denied = buffer_auto_in_18_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_17_d_bits_data = buffer_auto_in_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_17_e_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_17_d_bits_corrupt = buffer_auto_in_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_e_ready = buffer_auto_in_18_e_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_17_e_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_17_e_valid = buffer_auto_in_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_17_e_bits_sink; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_ready; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_17_e_bits_sink = buffer_auto_in_18_e_bits_sink; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_ready = buffer_auto_in_17_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_valid = buffer_auto_in_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_16_a_bits_opcode = buffer_auto_in_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_16_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_16_a_bits_param = buffer_auto_in_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_16_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_16_a_bits_size = buffer_auto_in_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_16_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_16_a_bits_source = buffer_auto_in_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_16_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_16_a_bits_address = buffer_auto_in_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_16_a_bits_mask = buffer_auto_in_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_16_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_16_a_bits_data = buffer_auto_in_17_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_a_bits_corrupt = buffer_auto_in_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_16_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_16_d_ready = buffer_auto_in_17_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_16_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_valid = buffer_auto_in_17_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_16_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_16_d_bits_opcode = buffer_auto_in_17_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_16_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_16_d_bits_param = buffer_auto_in_17_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_16_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_16_d_bits_size = buffer_auto_in_17_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_16_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_16_d_bits_source = buffer_auto_in_17_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_16_d_bits_sink = buffer_auto_in_17_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_16_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_bits_denied = buffer_auto_in_17_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_16_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_16_d_bits_data = buffer_auto_in_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_16_d_bits_corrupt = buffer_auto_in_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_ready = buffer_auto_in_16_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_a_valid = buffer_auto_in_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_15_a_bits_opcode = buffer_auto_in_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_15_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_15_a_bits_param = buffer_auto_in_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_15_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_15_a_bits_size = buffer_auto_in_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_15_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_15_a_bits_source = buffer_auto_in_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_15_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_15_a_bits_address = buffer_auto_in_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_15_a_bits_mask = buffer_auto_in_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_15_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_15_a_bits_data = buffer_auto_in_16_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_a_bits_corrupt = buffer_auto_in_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_15_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_15_d_ready = buffer_auto_in_16_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_15_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_valid = buffer_auto_in_16_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_15_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_15_d_bits_opcode = buffer_auto_in_16_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_15_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_15_d_bits_param = buffer_auto_in_16_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_15_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_15_d_bits_size = buffer_auto_in_16_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_15_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_15_d_bits_source = buffer_auto_in_16_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_15_d_bits_sink = buffer_auto_in_16_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_15_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_bits_denied = buffer_auto_in_16_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_15_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_15_d_bits_data = buffer_auto_in_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_15_d_bits_corrupt = buffer_auto_in_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_ready = buffer_auto_in_15_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_a_valid = buffer_auto_in_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_14_a_bits_opcode = buffer_auto_in_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_14_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_14_a_bits_param = buffer_auto_in_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_14_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_14_a_bits_size = buffer_auto_in_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_14_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_14_a_bits_source = buffer_auto_in_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_14_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_14_a_bits_address = buffer_auto_in_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_14_a_bits_mask = buffer_auto_in_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_14_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_14_a_bits_data = buffer_auto_in_15_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_a_bits_corrupt = buffer_auto_in_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_14_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_14_d_ready = buffer_auto_in_15_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_14_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_valid = buffer_auto_in_15_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_14_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_14_d_bits_opcode = buffer_auto_in_15_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_14_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_14_d_bits_param = buffer_auto_in_15_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_14_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_14_d_bits_size = buffer_auto_in_15_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_14_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_14_d_bits_source = buffer_auto_in_15_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_14_d_bits_sink = buffer_auto_in_15_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_14_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_bits_denied = buffer_auto_in_15_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_14_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_14_d_bits_data = buffer_auto_in_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_14_d_bits_corrupt = buffer_auto_in_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_ready = buffer_auto_in_14_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_a_valid = buffer_auto_in_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_13_a_bits_opcode = buffer_auto_in_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_13_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_13_a_bits_param = buffer_auto_in_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_13_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_13_a_bits_size = buffer_auto_in_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_13_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_13_a_bits_source = buffer_auto_in_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_13_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_13_a_bits_address = buffer_auto_in_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_13_a_bits_mask = buffer_auto_in_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_13_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_13_a_bits_data = buffer_auto_in_14_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_a_bits_corrupt = buffer_auto_in_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_13_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_13_d_ready = buffer_auto_in_14_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_13_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_valid = buffer_auto_in_14_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_13_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_13_d_bits_opcode = buffer_auto_in_14_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_13_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_13_d_bits_param = buffer_auto_in_14_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_13_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_13_d_bits_size = buffer_auto_in_14_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_13_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_13_d_bits_source = buffer_auto_in_14_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_13_d_bits_sink = buffer_auto_in_14_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_13_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_bits_denied = buffer_auto_in_14_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_13_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_13_d_bits_data = buffer_auto_in_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_13_d_bits_corrupt = buffer_auto_in_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_ready = buffer_auto_in_13_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_a_valid = buffer_auto_in_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_12_a_bits_opcode = buffer_auto_in_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_12_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_12_a_bits_param = buffer_auto_in_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_12_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_12_a_bits_size = buffer_auto_in_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_12_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_12_a_bits_source = buffer_auto_in_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_12_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_12_a_bits_address = buffer_auto_in_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_12_a_bits_mask = buffer_auto_in_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_12_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_12_a_bits_data = buffer_auto_in_13_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_a_bits_corrupt = buffer_auto_in_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_12_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_12_d_ready = buffer_auto_in_13_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_12_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_valid = buffer_auto_in_13_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_12_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_12_d_bits_opcode = buffer_auto_in_13_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_12_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_12_d_bits_param = buffer_auto_in_13_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_12_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_12_d_bits_size = buffer_auto_in_13_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_12_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_12_d_bits_source = buffer_auto_in_13_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_12_d_bits_sink = buffer_auto_in_13_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_12_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_bits_denied = buffer_auto_in_13_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_12_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_12_d_bits_data = buffer_auto_in_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_12_d_bits_corrupt = buffer_auto_in_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_ready = buffer_auto_in_12_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_a_valid = buffer_auto_in_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_11_a_bits_opcode = buffer_auto_in_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_11_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_11_a_bits_param = buffer_auto_in_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_11_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_11_a_bits_size = buffer_auto_in_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_11_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_11_a_bits_source = buffer_auto_in_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_11_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_11_a_bits_address = buffer_auto_in_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_11_a_bits_mask = buffer_auto_in_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_11_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_11_a_bits_data = buffer_auto_in_12_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_a_bits_corrupt = buffer_auto_in_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_11_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_11_d_ready = buffer_auto_in_12_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_11_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_valid = buffer_auto_in_12_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_11_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_11_d_bits_opcode = buffer_auto_in_12_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_11_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_11_d_bits_param = buffer_auto_in_12_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_11_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_11_d_bits_size = buffer_auto_in_12_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_11_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_11_d_bits_source = buffer_auto_in_12_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_11_d_bits_sink = buffer_auto_in_12_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_11_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_bits_denied = buffer_auto_in_12_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_11_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_11_d_bits_data = buffer_auto_in_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_11_d_bits_corrupt = buffer_auto_in_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_ready = buffer_auto_in_11_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_a_valid = buffer_auto_in_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_10_a_bits_opcode = buffer_auto_in_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_10_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_10_a_bits_param = buffer_auto_in_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_10_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_10_a_bits_size = buffer_auto_in_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_10_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_10_a_bits_source = buffer_auto_in_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_10_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_10_a_bits_address = buffer_auto_in_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_10_a_bits_mask = buffer_auto_in_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_10_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_10_a_bits_data = buffer_auto_in_11_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_a_bits_corrupt = buffer_auto_in_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_10_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_10_d_ready = buffer_auto_in_11_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_10_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_valid = buffer_auto_in_11_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_10_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_10_d_bits_opcode = buffer_auto_in_11_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_10_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_10_d_bits_param = buffer_auto_in_11_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_10_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_10_d_bits_size = buffer_auto_in_11_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_10_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_10_d_bits_source = buffer_auto_in_11_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_10_d_bits_sink = buffer_auto_in_11_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_10_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_bits_denied = buffer_auto_in_11_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_10_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_10_d_bits_data = buffer_auto_in_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_10_d_bits_corrupt = buffer_auto_in_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_ready = buffer_auto_in_10_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_a_valid = buffer_auto_in_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_9_a_bits_opcode = buffer_auto_in_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_9_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_9_a_bits_param = buffer_auto_in_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_9_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_9_a_bits_size = buffer_auto_in_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_9_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_9_a_bits_source = buffer_auto_in_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_9_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_9_a_bits_address = buffer_auto_in_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_9_a_bits_mask = buffer_auto_in_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_9_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_9_a_bits_data = buffer_auto_in_10_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_a_bits_corrupt = buffer_auto_in_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_9_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_9_d_ready = buffer_auto_in_10_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_9_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_valid = buffer_auto_in_10_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_9_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_9_d_bits_opcode = buffer_auto_in_10_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_9_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_9_d_bits_param = buffer_auto_in_10_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_9_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_9_d_bits_size = buffer_auto_in_10_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_9_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_9_d_bits_source = buffer_auto_in_10_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_9_d_bits_sink = buffer_auto_in_10_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_9_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_bits_denied = buffer_auto_in_10_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_9_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_9_d_bits_data = buffer_auto_in_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_9_d_bits_corrupt = buffer_auto_in_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_ready = buffer_auto_in_9_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_a_valid = buffer_auto_in_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_8_a_bits_opcode = buffer_auto_in_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_8_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_8_a_bits_param = buffer_auto_in_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_8_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_8_a_bits_size = buffer_auto_in_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_8_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_8_a_bits_source = buffer_auto_in_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_8_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_8_a_bits_address = buffer_auto_in_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_8_a_bits_mask = buffer_auto_in_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_8_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_8_a_bits_data = buffer_auto_in_9_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_a_bits_corrupt = buffer_auto_in_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_8_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_8_d_ready = buffer_auto_in_9_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_8_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_valid = buffer_auto_in_9_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_8_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_8_d_bits_opcode = buffer_auto_in_9_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_8_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_8_d_bits_param = buffer_auto_in_9_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_8_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_8_d_bits_size = buffer_auto_in_9_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_8_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_8_d_bits_source = buffer_auto_in_9_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_8_d_bits_sink = buffer_auto_in_9_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_8_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_bits_denied = buffer_auto_in_9_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_8_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_8_d_bits_data = buffer_auto_in_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_8_d_bits_corrupt = buffer_auto_in_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_ready = buffer_auto_in_8_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_a_valid = buffer_auto_in_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_7_a_bits_opcode = buffer_auto_in_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_7_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_7_a_bits_param = buffer_auto_in_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_7_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_7_a_bits_size = buffer_auto_in_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_7_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_7_a_bits_source = buffer_auto_in_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_7_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_7_a_bits_address = buffer_auto_in_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_7_a_bits_mask = buffer_auto_in_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_7_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_7_a_bits_data = buffer_auto_in_8_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_a_bits_corrupt = buffer_auto_in_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_7_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_7_d_ready = buffer_auto_in_8_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_7_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_valid = buffer_auto_in_8_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_7_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_7_d_bits_opcode = buffer_auto_in_8_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_7_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_7_d_bits_param = buffer_auto_in_8_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_7_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_7_d_bits_size = buffer_auto_in_8_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_7_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_7_d_bits_source = buffer_auto_in_8_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_7_d_bits_sink = buffer_auto_in_8_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_7_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_bits_denied = buffer_auto_in_8_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_7_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_7_d_bits_data = buffer_auto_in_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_7_d_bits_corrupt = buffer_auto_in_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_ready = buffer_auto_in_7_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_a_valid = buffer_auto_in_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_6_a_bits_opcode = buffer_auto_in_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_6_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_6_a_bits_param = buffer_auto_in_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_6_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_6_a_bits_size = buffer_auto_in_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_6_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_6_a_bits_source = buffer_auto_in_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_6_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_6_a_bits_address = buffer_auto_in_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_6_a_bits_mask = buffer_auto_in_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_6_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_6_a_bits_data = buffer_auto_in_7_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_a_bits_corrupt = buffer_auto_in_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_6_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_6_d_ready = buffer_auto_in_7_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_6_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_valid = buffer_auto_in_7_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_6_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_6_d_bits_opcode = buffer_auto_in_7_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_6_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_6_d_bits_param = buffer_auto_in_7_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_6_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_6_d_bits_size = buffer_auto_in_7_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_6_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_6_d_bits_source = buffer_auto_in_7_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_6_d_bits_sink = buffer_auto_in_7_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_6_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_bits_denied = buffer_auto_in_7_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_6_d_bits_data = buffer_auto_in_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_6_d_bits_corrupt = buffer_auto_in_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_ready = buffer_auto_in_6_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_a_valid = buffer_auto_in_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_5_a_bits_opcode = buffer_auto_in_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_5_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_5_a_bits_param = buffer_auto_in_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_5_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_5_a_bits_size = buffer_auto_in_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_5_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_5_a_bits_source = buffer_auto_in_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_5_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_5_a_bits_address = buffer_auto_in_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_5_a_bits_mask = buffer_auto_in_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_5_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_5_a_bits_data = buffer_auto_in_6_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_a_bits_corrupt = buffer_auto_in_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_5_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_5_d_ready = buffer_auto_in_6_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_5_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_valid = buffer_auto_in_6_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_5_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_5_d_bits_opcode = buffer_auto_in_6_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_5_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_5_d_bits_param = buffer_auto_in_6_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_5_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_5_d_bits_size = buffer_auto_in_6_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_5_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_5_d_bits_source = buffer_auto_in_6_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_5_d_bits_sink = buffer_auto_in_6_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_5_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_bits_denied = buffer_auto_in_6_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_5_d_bits_data = buffer_auto_in_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_5_d_bits_corrupt = buffer_auto_in_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_ready = buffer_auto_in_5_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_a_valid = buffer_auto_in_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_4_a_bits_opcode = buffer_auto_in_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_4_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_4_a_bits_param = buffer_auto_in_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_4_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_4_a_bits_size = buffer_auto_in_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_4_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_4_a_bits_source = buffer_auto_in_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_4_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_4_a_bits_address = buffer_auto_in_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_4_a_bits_mask = buffer_auto_in_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_4_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_4_a_bits_data = buffer_auto_in_5_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_a_bits_corrupt = buffer_auto_in_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_4_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_4_d_ready = buffer_auto_in_5_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_valid = buffer_auto_in_5_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_4_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_4_d_bits_opcode = buffer_auto_in_5_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_4_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_4_d_bits_param = buffer_auto_in_5_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_4_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_4_d_bits_size = buffer_auto_in_5_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_4_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_4_d_bits_source = buffer_auto_in_5_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_4_d_bits_sink = buffer_auto_in_5_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_4_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_bits_denied = buffer_auto_in_5_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_4_d_bits_data = buffer_auto_in_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_4_d_bits_corrupt = buffer_auto_in_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_ready = buffer_auto_in_4_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_a_valid = buffer_auto_in_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_3_a_bits_opcode = buffer_auto_in_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_3_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_3_a_bits_param = buffer_auto_in_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_3_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_3_a_bits_size = buffer_auto_in_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_3_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_3_a_bits_source = buffer_auto_in_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_3_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_3_a_bits_address = buffer_auto_in_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_3_a_bits_mask = buffer_auto_in_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_3_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_3_a_bits_data = buffer_auto_in_4_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_a_bits_corrupt = buffer_auto_in_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_3_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_3_d_ready = buffer_auto_in_4_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_valid = buffer_auto_in_4_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_3_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_3_d_bits_opcode = buffer_auto_in_4_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_3_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_3_d_bits_param = buffer_auto_in_4_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_3_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_3_d_bits_size = buffer_auto_in_4_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_3_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_3_d_bits_source = buffer_auto_in_4_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_3_d_bits_sink = buffer_auto_in_4_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_3_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_bits_denied = buffer_auto_in_4_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_3_d_bits_data = buffer_auto_in_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_3_d_bits_corrupt = buffer_auto_in_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_ready = buffer_auto_in_3_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_a_valid = buffer_auto_in_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_2_a_bits_opcode = buffer_auto_in_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_2_a_bits_param = buffer_auto_in_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_2_a_bits_size = buffer_auto_in_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_2_a_bits_source = buffer_auto_in_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_2_a_bits_address = buffer_auto_in_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_2_a_bits_mask = buffer_auto_in_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_2_a_bits_data = buffer_auto_in_3_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_a_bits_corrupt = buffer_auto_in_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_2_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_2_d_ready = buffer_auto_in_3_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_valid = buffer_auto_in_3_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_2_d_bits_opcode = buffer_auto_in_3_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_2_d_bits_param = buffer_auto_in_3_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_2_d_bits_size = buffer_auto_in_3_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_2_d_bits_source = buffer_auto_in_3_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_2_d_bits_sink = buffer_auto_in_3_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_bits_denied = buffer_auto_in_3_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_2_d_bits_data = buffer_auto_in_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_2_d_bits_corrupt = buffer_auto_in_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_ready = buffer_auto_in_2_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_a_valid = buffer_auto_in_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_1_a_bits_opcode = buffer_auto_in_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_1_a_bits_param = buffer_auto_in_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_1_a_bits_size = buffer_auto_in_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] buffer_x1_nodeIn_1_a_bits_source = buffer_auto_in_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_1_a_bits_address = buffer_auto_in_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_1_a_bits_mask = buffer_auto_in_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_1_a_bits_data = buffer_auto_in_2_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_a_bits_corrupt = buffer_auto_in_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_1_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_1_d_ready = buffer_auto_in_2_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_valid = buffer_auto_in_2_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_1_d_bits_opcode = buffer_auto_in_2_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_1_d_bits_param = buffer_auto_in_2_d_bits_param; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_1_d_bits_size = buffer_auto_in_2_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] x1_tlOtherMastersNodeOut_1_d_bits_source = buffer_auto_in_2_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_1_d_bits_sink = buffer_auto_in_2_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_bits_denied = buffer_auto_in_2_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_1_d_bits_data = buffer_auto_in_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_1_d_bits_corrupt = buffer_auto_in_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_ready = buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_a_valid = buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_a_bits_opcode = buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_x1_nodeIn_a_bits_param = buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_x1_nodeIn_a_bits_size = buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_x1_nodeIn_a_bits_source = buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_x1_nodeIn_a_bits_address = buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_x1_nodeIn_a_bits_mask = buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_x1_nodeIn_a_bits_data = buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_a_bits_corrupt = buffer_auto_in_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_x1_nodeIn_d_ready = buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_x1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_valid = buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] x1_tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] x1_tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] x1_tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_x1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] x1_tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire x1_tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_source = buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_ready = buffer_auto_out_18_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_valid_0 = buffer_auto_out_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_opcode_0 = buffer_auto_out_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_param_0 = buffer_auto_out_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_size_0 = buffer_auto_out_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_source_0 = buffer_auto_out_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_address_0 = buffer_auto_out_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_17_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_mask_0 = buffer_auto_out_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_a_bits_data_0 = buffer_auto_out_18_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_b_ready_0 = buffer_auto_out_18_b_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_valid = buffer_auto_out_18_b_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_b_bits_opcode = buffer_auto_out_18_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_b_bits_param = buffer_auto_out_18_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_b_bits_size = buffer_auto_out_18_b_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_b_bits_source = buffer_auto_out_18_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_b_bits_address = buffer_auto_out_18_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_17_b_bits_mask = buffer_auto_out_18_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_b_bits_data = buffer_auto_out_18_b_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_b_bits_corrupt = buffer_auto_out_18_b_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_c_ready = buffer_auto_out_18_c_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_c_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_valid_0 = buffer_auto_out_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_opcode_0 = buffer_auto_out_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_c_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_param_0 = buffer_auto_out_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_c_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_size_0 = buffer_auto_out_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_c_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_source_0 = buffer_auto_out_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_17_c_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_address_0 = buffer_auto_out_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_c_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_c_bits_data_0 = buffer_auto_out_18_c_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_d_ready_0 = buffer_auto_out_18_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_valid = buffer_auto_out_18_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_d_bits_opcode = buffer_auto_out_18_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_d_bits_param = buffer_auto_out_18_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_17_d_bits_size = buffer_auto_out_18_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_17_d_bits_source = buffer_auto_out_18_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_d_bits_sink = buffer_auto_out_18_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_bits_denied = buffer_auto_out_18_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_17_d_bits_data = buffer_auto_out_18_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_d_bits_corrupt = buffer_auto_out_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_e_ready = buffer_auto_out_18_e_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_17_e_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_e_valid_0 = buffer_auto_out_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_17_e_bits_sink; // @[MixedNode.scala:542:17] assign auto_buffer_out_18_e_bits_sink_0 = buffer_auto_out_18_e_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_ready = buffer_auto_out_17_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_valid_0 = buffer_auto_out_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_opcode_0 = buffer_auto_out_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_param_0 = buffer_auto_out_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_16_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_size_0 = buffer_auto_out_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_16_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_source_0 = buffer_auto_out_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_16_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_address_0 = buffer_auto_out_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_mask_0 = buffer_auto_out_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_16_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_data_0 = buffer_auto_out_17_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_a_bits_corrupt_0 = buffer_auto_out_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_17_d_ready_0 = buffer_auto_out_17_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_valid = buffer_auto_out_17_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_d_bits_opcode = buffer_auto_out_17_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_16_d_bits_param = buffer_auto_out_17_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_16_d_bits_size = buffer_auto_out_17_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_16_d_bits_source = buffer_auto_out_17_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_16_d_bits_sink = buffer_auto_out_17_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_bits_denied = buffer_auto_out_17_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_16_d_bits_data = buffer_auto_out_17_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_16_d_bits_corrupt = buffer_auto_out_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_ready = buffer_auto_out_16_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_valid_0 = buffer_auto_out_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_opcode_0 = buffer_auto_out_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_param_0 = buffer_auto_out_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_15_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_size_0 = buffer_auto_out_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_15_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_source_0 = buffer_auto_out_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_15_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_address_0 = buffer_auto_out_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_mask_0 = buffer_auto_out_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_15_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_data_0 = buffer_auto_out_16_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_a_bits_corrupt_0 = buffer_auto_out_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_16_d_ready_0 = buffer_auto_out_16_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_valid = buffer_auto_out_16_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_d_bits_opcode = buffer_auto_out_16_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_15_d_bits_param = buffer_auto_out_16_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_15_d_bits_size = buffer_auto_out_16_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_15_d_bits_source = buffer_auto_out_16_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_15_d_bits_sink = buffer_auto_out_16_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_bits_denied = buffer_auto_out_16_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_15_d_bits_data = buffer_auto_out_16_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_15_d_bits_corrupt = buffer_auto_out_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_ready = buffer_auto_out_15_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_valid_0 = buffer_auto_out_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_opcode_0 = buffer_auto_out_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_param_0 = buffer_auto_out_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_14_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_size_0 = buffer_auto_out_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_14_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_source_0 = buffer_auto_out_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_14_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_address_0 = buffer_auto_out_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_mask_0 = buffer_auto_out_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_14_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_data_0 = buffer_auto_out_15_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_a_bits_corrupt_0 = buffer_auto_out_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_15_d_ready_0 = buffer_auto_out_15_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_valid = buffer_auto_out_15_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_d_bits_opcode = buffer_auto_out_15_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_14_d_bits_param = buffer_auto_out_15_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_14_d_bits_size = buffer_auto_out_15_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_14_d_bits_source = buffer_auto_out_15_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_14_d_bits_sink = buffer_auto_out_15_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_bits_denied = buffer_auto_out_15_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_14_d_bits_data = buffer_auto_out_15_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_14_d_bits_corrupt = buffer_auto_out_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_ready = buffer_auto_out_14_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_valid_0 = buffer_auto_out_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_opcode_0 = buffer_auto_out_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_param_0 = buffer_auto_out_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_13_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_size_0 = buffer_auto_out_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_13_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_source_0 = buffer_auto_out_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_13_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_address_0 = buffer_auto_out_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_mask_0 = buffer_auto_out_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_13_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_data_0 = buffer_auto_out_14_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_a_bits_corrupt_0 = buffer_auto_out_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_14_d_ready_0 = buffer_auto_out_14_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_valid = buffer_auto_out_14_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_d_bits_opcode = buffer_auto_out_14_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_13_d_bits_param = buffer_auto_out_14_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_13_d_bits_size = buffer_auto_out_14_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_13_d_bits_source = buffer_auto_out_14_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_13_d_bits_sink = buffer_auto_out_14_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_bits_denied = buffer_auto_out_14_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_13_d_bits_data = buffer_auto_out_14_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_13_d_bits_corrupt = buffer_auto_out_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_ready = buffer_auto_out_13_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_valid_0 = buffer_auto_out_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_opcode_0 = buffer_auto_out_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_param_0 = buffer_auto_out_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_12_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_size_0 = buffer_auto_out_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_12_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_source_0 = buffer_auto_out_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_12_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_address_0 = buffer_auto_out_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_mask_0 = buffer_auto_out_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_12_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_data_0 = buffer_auto_out_13_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_a_bits_corrupt_0 = buffer_auto_out_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_13_d_ready_0 = buffer_auto_out_13_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_valid = buffer_auto_out_13_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_d_bits_opcode = buffer_auto_out_13_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_12_d_bits_param = buffer_auto_out_13_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_12_d_bits_size = buffer_auto_out_13_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_12_d_bits_source = buffer_auto_out_13_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_12_d_bits_sink = buffer_auto_out_13_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_bits_denied = buffer_auto_out_13_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_12_d_bits_data = buffer_auto_out_13_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_12_d_bits_corrupt = buffer_auto_out_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_ready = buffer_auto_out_12_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_valid_0 = buffer_auto_out_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_opcode_0 = buffer_auto_out_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_param_0 = buffer_auto_out_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_11_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_size_0 = buffer_auto_out_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_11_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_source_0 = buffer_auto_out_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_11_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_address_0 = buffer_auto_out_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_mask_0 = buffer_auto_out_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_11_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_data_0 = buffer_auto_out_12_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_a_bits_corrupt_0 = buffer_auto_out_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_12_d_ready_0 = buffer_auto_out_12_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_valid = buffer_auto_out_12_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_d_bits_opcode = buffer_auto_out_12_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_11_d_bits_param = buffer_auto_out_12_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_11_d_bits_size = buffer_auto_out_12_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_11_d_bits_source = buffer_auto_out_12_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_11_d_bits_sink = buffer_auto_out_12_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_bits_denied = buffer_auto_out_12_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_11_d_bits_data = buffer_auto_out_12_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_11_d_bits_corrupt = buffer_auto_out_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_ready = buffer_auto_out_11_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_valid_0 = buffer_auto_out_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_opcode_0 = buffer_auto_out_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_param_0 = buffer_auto_out_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_10_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_size_0 = buffer_auto_out_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_10_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_source_0 = buffer_auto_out_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_10_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_address_0 = buffer_auto_out_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_mask_0 = buffer_auto_out_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_10_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_data_0 = buffer_auto_out_11_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_a_bits_corrupt_0 = buffer_auto_out_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_11_d_ready_0 = buffer_auto_out_11_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_valid = buffer_auto_out_11_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_d_bits_opcode = buffer_auto_out_11_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_10_d_bits_param = buffer_auto_out_11_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_10_d_bits_size = buffer_auto_out_11_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_10_d_bits_source = buffer_auto_out_11_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_10_d_bits_sink = buffer_auto_out_11_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_bits_denied = buffer_auto_out_11_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_10_d_bits_data = buffer_auto_out_11_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_10_d_bits_corrupt = buffer_auto_out_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_ready = buffer_auto_out_10_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_valid_0 = buffer_auto_out_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_opcode_0 = buffer_auto_out_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_param_0 = buffer_auto_out_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_9_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_size_0 = buffer_auto_out_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_9_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_source_0 = buffer_auto_out_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_9_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_address_0 = buffer_auto_out_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_mask_0 = buffer_auto_out_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_9_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_data_0 = buffer_auto_out_10_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_a_bits_corrupt_0 = buffer_auto_out_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_10_d_ready_0 = buffer_auto_out_10_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_valid = buffer_auto_out_10_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_d_bits_opcode = buffer_auto_out_10_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_9_d_bits_param = buffer_auto_out_10_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_9_d_bits_size = buffer_auto_out_10_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_9_d_bits_source = buffer_auto_out_10_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_9_d_bits_sink = buffer_auto_out_10_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_bits_denied = buffer_auto_out_10_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_9_d_bits_data = buffer_auto_out_10_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_9_d_bits_corrupt = buffer_auto_out_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_ready = buffer_auto_out_9_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_valid_0 = buffer_auto_out_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_opcode_0 = buffer_auto_out_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_param_0 = buffer_auto_out_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_8_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_size_0 = buffer_auto_out_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_source_0 = buffer_auto_out_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_8_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_address_0 = buffer_auto_out_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_mask_0 = buffer_auto_out_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_8_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_data_0 = buffer_auto_out_9_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_a_bits_corrupt_0 = buffer_auto_out_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_9_d_ready_0 = buffer_auto_out_9_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_valid = buffer_auto_out_9_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_d_bits_opcode = buffer_auto_out_9_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_d_bits_param = buffer_auto_out_9_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_8_d_bits_size = buffer_auto_out_9_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_8_d_bits_source = buffer_auto_out_9_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_8_d_bits_sink = buffer_auto_out_9_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_bits_denied = buffer_auto_out_9_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_8_d_bits_data = buffer_auto_out_9_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_8_d_bits_corrupt = buffer_auto_out_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_ready = buffer_auto_out_8_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_valid_0 = buffer_auto_out_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_opcode_0 = buffer_auto_out_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_param_0 = buffer_auto_out_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_7_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_size_0 = buffer_auto_out_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_source_0 = buffer_auto_out_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_7_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_address_0 = buffer_auto_out_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_mask_0 = buffer_auto_out_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_7_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_data_0 = buffer_auto_out_8_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_a_bits_corrupt_0 = buffer_auto_out_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_8_d_ready_0 = buffer_auto_out_8_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_valid = buffer_auto_out_8_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_d_bits_opcode = buffer_auto_out_8_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_d_bits_param = buffer_auto_out_8_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_7_d_bits_size = buffer_auto_out_8_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_7_d_bits_source = buffer_auto_out_8_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_7_d_bits_sink = buffer_auto_out_8_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_bits_denied = buffer_auto_out_8_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_7_d_bits_data = buffer_auto_out_8_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_7_d_bits_corrupt = buffer_auto_out_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_ready = buffer_auto_out_7_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_valid_0 = buffer_auto_out_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_opcode_0 = buffer_auto_out_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_param_0 = buffer_auto_out_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_6_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_size_0 = buffer_auto_out_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_6_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_source_0 = buffer_auto_out_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_6_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_address_0 = buffer_auto_out_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_mask_0 = buffer_auto_out_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_6_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_data_0 = buffer_auto_out_7_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_a_bits_corrupt_0 = buffer_auto_out_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_7_d_ready_0 = buffer_auto_out_7_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_valid = buffer_auto_out_7_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_d_bits_opcode = buffer_auto_out_7_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_6_d_bits_param = buffer_auto_out_7_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_6_d_bits_size = buffer_auto_out_7_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_6_d_bits_source = buffer_auto_out_7_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_6_d_bits_sink = buffer_auto_out_7_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_bits_denied = buffer_auto_out_7_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_6_d_bits_data = buffer_auto_out_7_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_6_d_bits_corrupt = buffer_auto_out_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_ready = buffer_auto_out_6_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_valid_0 = buffer_auto_out_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_opcode_0 = buffer_auto_out_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_param_0 = buffer_auto_out_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_5_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_size_0 = buffer_auto_out_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_5_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_source_0 = buffer_auto_out_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_5_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_address_0 = buffer_auto_out_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_mask_0 = buffer_auto_out_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_5_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_data_0 = buffer_auto_out_6_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_a_bits_corrupt_0 = buffer_auto_out_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_6_d_ready_0 = buffer_auto_out_6_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_valid = buffer_auto_out_6_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_d_bits_opcode = buffer_auto_out_6_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_5_d_bits_param = buffer_auto_out_6_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_5_d_bits_size = buffer_auto_out_6_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_5_d_bits_source = buffer_auto_out_6_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_5_d_bits_sink = buffer_auto_out_6_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_bits_denied = buffer_auto_out_6_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_5_d_bits_data = buffer_auto_out_6_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_5_d_bits_corrupt = buffer_auto_out_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_ready = buffer_auto_out_5_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_valid_0 = buffer_auto_out_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_opcode_0 = buffer_auto_out_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_param_0 = buffer_auto_out_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_4_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_size_0 = buffer_auto_out_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_4_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_source_0 = buffer_auto_out_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_4_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_address_0 = buffer_auto_out_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_mask_0 = buffer_auto_out_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_4_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_data_0 = buffer_auto_out_5_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_a_bits_corrupt_0 = buffer_auto_out_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_5_d_ready_0 = buffer_auto_out_5_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_valid = buffer_auto_out_5_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_d_bits_opcode = buffer_auto_out_5_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_4_d_bits_param = buffer_auto_out_5_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_4_d_bits_size = buffer_auto_out_5_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_4_d_bits_source = buffer_auto_out_5_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_4_d_bits_sink = buffer_auto_out_5_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_bits_denied = buffer_auto_out_5_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_4_d_bits_data = buffer_auto_out_5_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_4_d_bits_corrupt = buffer_auto_out_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_ready = buffer_auto_out_4_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_valid_0 = buffer_auto_out_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_opcode_0 = buffer_auto_out_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_param_0 = buffer_auto_out_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_3_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_size_0 = buffer_auto_out_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_3_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_source_0 = buffer_auto_out_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_3_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_address_0 = buffer_auto_out_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_mask_0 = buffer_auto_out_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_3_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_data_0 = buffer_auto_out_4_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_a_bits_corrupt_0 = buffer_auto_out_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_4_d_ready_0 = buffer_auto_out_4_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_valid = buffer_auto_out_4_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_d_bits_opcode = buffer_auto_out_4_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_3_d_bits_param = buffer_auto_out_4_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_3_d_bits_size = buffer_auto_out_4_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_3_d_bits_source = buffer_auto_out_4_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_3_d_bits_sink = buffer_auto_out_4_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_bits_denied = buffer_auto_out_4_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_3_d_bits_data = buffer_auto_out_4_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_3_d_bits_corrupt = buffer_auto_out_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_ready = buffer_auto_out_3_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_valid_0 = buffer_auto_out_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_opcode_0 = buffer_auto_out_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_param_0 = buffer_auto_out_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_2_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_size_0 = buffer_auto_out_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_2_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_source_0 = buffer_auto_out_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_2_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_address_0 = buffer_auto_out_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_mask_0 = buffer_auto_out_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_2_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_data_0 = buffer_auto_out_3_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_a_bits_corrupt_0 = buffer_auto_out_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_3_d_ready_0 = buffer_auto_out_3_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_valid = buffer_auto_out_3_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_d_bits_opcode = buffer_auto_out_3_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_2_d_bits_param = buffer_auto_out_3_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_2_d_bits_size = buffer_auto_out_3_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_2_d_bits_source = buffer_auto_out_3_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_2_d_bits_sink = buffer_auto_out_3_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_bits_denied = buffer_auto_out_3_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_2_d_bits_data = buffer_auto_out_3_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_2_d_bits_corrupt = buffer_auto_out_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_ready = buffer_auto_out_2_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_valid_0 = buffer_auto_out_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_opcode_0 = buffer_auto_out_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_param_0 = buffer_auto_out_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_1_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_size_0 = buffer_auto_out_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_1_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_source_0 = buffer_auto_out_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_1_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_address_0 = buffer_auto_out_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_mask_0 = buffer_auto_out_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_1_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_data_0 = buffer_auto_out_2_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_a_bits_corrupt_0 = buffer_auto_out_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_2_d_ready_0 = buffer_auto_out_2_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_valid = buffer_auto_out_2_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_d_bits_opcode = buffer_auto_out_2_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_1_d_bits_param = buffer_auto_out_2_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_1_d_bits_size = buffer_auto_out_2_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] buffer_x1_nodeOut_1_d_bits_source = buffer_auto_out_2_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_1_d_bits_sink = buffer_auto_out_2_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_bits_denied = buffer_auto_out_2_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_1_d_bits_data = buffer_auto_out_2_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_1_d_bits_corrupt = buffer_auto_out_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_ready = buffer_auto_out_1_a_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_valid_0 = buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_opcode_0 = buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_param_0 = buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_size_0 = buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_source_0 = buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_address_0 = buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_mask_0 = buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_data_0 = buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_a_bits_corrupt_0 = buffer_auto_out_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_1_d_ready_0 = buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_valid = buffer_auto_out_1_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_d_bits_opcode = buffer_auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_d_bits_param = buffer_auto_out_1_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_x1_nodeOut_d_bits_size = buffer_auto_out_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_x1_nodeOut_d_bits_source = buffer_auto_out_1_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_x1_nodeOut_d_bits_sink = buffer_auto_out_1_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_bits_denied = buffer_auto_out_1_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_x1_nodeOut_d_bits_data = buffer_auto_out_1_d_bits_data; // @[Buffer.scala:40:9] wire buffer_x1_nodeOut_d_bits_corrupt = buffer_auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_ready = buffer_auto_out_0_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_valid_0 = buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_opcode_0 = buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_param_0 = buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_size_0 = buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_source_0 = buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_address_0 = buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_mask_0 = buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_data_0 = buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_a_bits_corrupt_0 = buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_buffer_out_0_d_ready_0 = buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_valid = buffer_auto_out_0_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_0_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_0_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_source = buffer_auto_out_0_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_0_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_denied = buffer_auto_out_0_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_0_d_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_0_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_0_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_0_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_a_ready = buffer_x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_1_a_valid = buffer_x1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_opcode = buffer_x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_param = buffer_x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_size = buffer_x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_source = buffer_x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_address = buffer_x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_mask = buffer_x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_data = buffer_x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_1_a_bits_corrupt = buffer_x1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_1_d_ready = buffer_x1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_d_valid = buffer_x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_opcode = buffer_x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_param = buffer_x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_size = buffer_x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_source = buffer_x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_sink = buffer_x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_denied = buffer_x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_data = buffer_x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_d_bits_corrupt = buffer_x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_a_ready = buffer_x1_nodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_2_a_valid = buffer_x1_nodeOut_1_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_opcode = buffer_x1_nodeOut_1_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_param = buffer_x1_nodeOut_1_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_size = buffer_x1_nodeOut_1_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_source = buffer_x1_nodeOut_1_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_address = buffer_x1_nodeOut_1_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_mask = buffer_x1_nodeOut_1_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_data = buffer_x1_nodeOut_1_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_2_a_bits_corrupt = buffer_x1_nodeOut_1_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_2_d_ready = buffer_x1_nodeOut_1_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_1_d_valid = buffer_x1_nodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_opcode = buffer_x1_nodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_param = buffer_x1_nodeOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_size = buffer_x1_nodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_source = buffer_x1_nodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_sink = buffer_x1_nodeOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_denied = buffer_x1_nodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_data = buffer_x1_nodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_1_d_bits_corrupt = buffer_x1_nodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_a_ready = buffer_x1_nodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_3_a_valid = buffer_x1_nodeOut_2_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_opcode = buffer_x1_nodeOut_2_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_param = buffer_x1_nodeOut_2_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_size = buffer_x1_nodeOut_2_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_source = buffer_x1_nodeOut_2_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_address = buffer_x1_nodeOut_2_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_mask = buffer_x1_nodeOut_2_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_data = buffer_x1_nodeOut_2_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_3_a_bits_corrupt = buffer_x1_nodeOut_2_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_3_d_ready = buffer_x1_nodeOut_2_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_2_d_valid = buffer_x1_nodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_opcode = buffer_x1_nodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_param = buffer_x1_nodeOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_size = buffer_x1_nodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_source = buffer_x1_nodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_sink = buffer_x1_nodeOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_denied = buffer_x1_nodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_data = buffer_x1_nodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_2_d_bits_corrupt = buffer_x1_nodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_a_ready = buffer_x1_nodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_4_a_valid = buffer_x1_nodeOut_3_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_opcode = buffer_x1_nodeOut_3_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_param = buffer_x1_nodeOut_3_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_size = buffer_x1_nodeOut_3_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_source = buffer_x1_nodeOut_3_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_address = buffer_x1_nodeOut_3_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_mask = buffer_x1_nodeOut_3_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_data = buffer_x1_nodeOut_3_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_4_a_bits_corrupt = buffer_x1_nodeOut_3_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_4_d_ready = buffer_x1_nodeOut_3_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_3_d_valid = buffer_x1_nodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_opcode = buffer_x1_nodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_param = buffer_x1_nodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_size = buffer_x1_nodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_source = buffer_x1_nodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_sink = buffer_x1_nodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_denied = buffer_x1_nodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_data = buffer_x1_nodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_3_d_bits_corrupt = buffer_x1_nodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_a_ready = buffer_x1_nodeOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_5_a_valid = buffer_x1_nodeOut_4_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_opcode = buffer_x1_nodeOut_4_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_param = buffer_x1_nodeOut_4_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_size = buffer_x1_nodeOut_4_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_source = buffer_x1_nodeOut_4_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_address = buffer_x1_nodeOut_4_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_mask = buffer_x1_nodeOut_4_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_data = buffer_x1_nodeOut_4_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_5_a_bits_corrupt = buffer_x1_nodeOut_4_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_5_d_ready = buffer_x1_nodeOut_4_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_4_d_valid = buffer_x1_nodeOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_opcode = buffer_x1_nodeOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_param = buffer_x1_nodeOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_size = buffer_x1_nodeOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_source = buffer_x1_nodeOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_sink = buffer_x1_nodeOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_denied = buffer_x1_nodeOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_data = buffer_x1_nodeOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_4_d_bits_corrupt = buffer_x1_nodeOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_a_ready = buffer_x1_nodeOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_6_a_valid = buffer_x1_nodeOut_5_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_opcode = buffer_x1_nodeOut_5_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_param = buffer_x1_nodeOut_5_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_size = buffer_x1_nodeOut_5_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_source = buffer_x1_nodeOut_5_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_address = buffer_x1_nodeOut_5_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_mask = buffer_x1_nodeOut_5_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_data = buffer_x1_nodeOut_5_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_6_a_bits_corrupt = buffer_x1_nodeOut_5_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_6_d_ready = buffer_x1_nodeOut_5_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_5_d_valid = buffer_x1_nodeOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_opcode = buffer_x1_nodeOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_param = buffer_x1_nodeOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_size = buffer_x1_nodeOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_source = buffer_x1_nodeOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_sink = buffer_x1_nodeOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_denied = buffer_x1_nodeOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_data = buffer_x1_nodeOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_5_d_bits_corrupt = buffer_x1_nodeOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_a_ready = buffer_x1_nodeOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_7_a_valid = buffer_x1_nodeOut_6_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_opcode = buffer_x1_nodeOut_6_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_param = buffer_x1_nodeOut_6_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_size = buffer_x1_nodeOut_6_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_source = buffer_x1_nodeOut_6_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_address = buffer_x1_nodeOut_6_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_mask = buffer_x1_nodeOut_6_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_data = buffer_x1_nodeOut_6_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_7_a_bits_corrupt = buffer_x1_nodeOut_6_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_7_d_ready = buffer_x1_nodeOut_6_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_6_d_valid = buffer_x1_nodeOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_opcode = buffer_x1_nodeOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_param = buffer_x1_nodeOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_size = buffer_x1_nodeOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_source = buffer_x1_nodeOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_sink = buffer_x1_nodeOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_denied = buffer_x1_nodeOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_data = buffer_x1_nodeOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_6_d_bits_corrupt = buffer_x1_nodeOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_a_ready = buffer_x1_nodeOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_8_a_valid = buffer_x1_nodeOut_7_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_opcode = buffer_x1_nodeOut_7_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_param = buffer_x1_nodeOut_7_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_size = buffer_x1_nodeOut_7_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_source = buffer_x1_nodeOut_7_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_address = buffer_x1_nodeOut_7_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_mask = buffer_x1_nodeOut_7_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_data = buffer_x1_nodeOut_7_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_8_a_bits_corrupt = buffer_x1_nodeOut_7_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_8_d_ready = buffer_x1_nodeOut_7_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_7_d_valid = buffer_x1_nodeOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_opcode = buffer_x1_nodeOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_param = buffer_x1_nodeOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_size = buffer_x1_nodeOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_source = buffer_x1_nodeOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_sink = buffer_x1_nodeOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_denied = buffer_x1_nodeOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_data = buffer_x1_nodeOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_7_d_bits_corrupt = buffer_x1_nodeOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_a_ready = buffer_x1_nodeOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_9_a_valid = buffer_x1_nodeOut_8_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_opcode = buffer_x1_nodeOut_8_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_param = buffer_x1_nodeOut_8_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_size = buffer_x1_nodeOut_8_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_source = buffer_x1_nodeOut_8_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_address = buffer_x1_nodeOut_8_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_mask = buffer_x1_nodeOut_8_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_data = buffer_x1_nodeOut_8_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_9_a_bits_corrupt = buffer_x1_nodeOut_8_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_9_d_ready = buffer_x1_nodeOut_8_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_8_d_valid = buffer_x1_nodeOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_opcode = buffer_x1_nodeOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_param = buffer_x1_nodeOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_size = buffer_x1_nodeOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_source = buffer_x1_nodeOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_sink = buffer_x1_nodeOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_denied = buffer_x1_nodeOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_data = buffer_x1_nodeOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_8_d_bits_corrupt = buffer_x1_nodeOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_a_ready = buffer_x1_nodeOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_10_a_valid = buffer_x1_nodeOut_9_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_opcode = buffer_x1_nodeOut_9_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_param = buffer_x1_nodeOut_9_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_size = buffer_x1_nodeOut_9_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_source = buffer_x1_nodeOut_9_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_address = buffer_x1_nodeOut_9_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_mask = buffer_x1_nodeOut_9_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_data = buffer_x1_nodeOut_9_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_10_a_bits_corrupt = buffer_x1_nodeOut_9_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_10_d_ready = buffer_x1_nodeOut_9_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_9_d_valid = buffer_x1_nodeOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_opcode = buffer_x1_nodeOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_param = buffer_x1_nodeOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_size = buffer_x1_nodeOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_source = buffer_x1_nodeOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_sink = buffer_x1_nodeOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_denied = buffer_x1_nodeOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_data = buffer_x1_nodeOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_9_d_bits_corrupt = buffer_x1_nodeOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_a_ready = buffer_x1_nodeOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_11_a_valid = buffer_x1_nodeOut_10_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_opcode = buffer_x1_nodeOut_10_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_param = buffer_x1_nodeOut_10_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_size = buffer_x1_nodeOut_10_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_source = buffer_x1_nodeOut_10_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_address = buffer_x1_nodeOut_10_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_mask = buffer_x1_nodeOut_10_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_data = buffer_x1_nodeOut_10_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_11_a_bits_corrupt = buffer_x1_nodeOut_10_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_11_d_ready = buffer_x1_nodeOut_10_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_10_d_valid = buffer_x1_nodeOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_opcode = buffer_x1_nodeOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_param = buffer_x1_nodeOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_size = buffer_x1_nodeOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_source = buffer_x1_nodeOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_sink = buffer_x1_nodeOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_denied = buffer_x1_nodeOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_data = buffer_x1_nodeOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_10_d_bits_corrupt = buffer_x1_nodeOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_a_ready = buffer_x1_nodeOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_12_a_valid = buffer_x1_nodeOut_11_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_opcode = buffer_x1_nodeOut_11_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_param = buffer_x1_nodeOut_11_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_size = buffer_x1_nodeOut_11_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_source = buffer_x1_nodeOut_11_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_address = buffer_x1_nodeOut_11_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_mask = buffer_x1_nodeOut_11_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_data = buffer_x1_nodeOut_11_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_12_a_bits_corrupt = buffer_x1_nodeOut_11_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_12_d_ready = buffer_x1_nodeOut_11_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_11_d_valid = buffer_x1_nodeOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_opcode = buffer_x1_nodeOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_param = buffer_x1_nodeOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_size = buffer_x1_nodeOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_source = buffer_x1_nodeOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_sink = buffer_x1_nodeOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_denied = buffer_x1_nodeOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_data = buffer_x1_nodeOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_11_d_bits_corrupt = buffer_x1_nodeOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_a_ready = buffer_x1_nodeOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_13_a_valid = buffer_x1_nodeOut_12_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_opcode = buffer_x1_nodeOut_12_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_param = buffer_x1_nodeOut_12_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_size = buffer_x1_nodeOut_12_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_source = buffer_x1_nodeOut_12_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_address = buffer_x1_nodeOut_12_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_mask = buffer_x1_nodeOut_12_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_data = buffer_x1_nodeOut_12_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_13_a_bits_corrupt = buffer_x1_nodeOut_12_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_13_d_ready = buffer_x1_nodeOut_12_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_12_d_valid = buffer_x1_nodeOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_opcode = buffer_x1_nodeOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_param = buffer_x1_nodeOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_size = buffer_x1_nodeOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_source = buffer_x1_nodeOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_sink = buffer_x1_nodeOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_denied = buffer_x1_nodeOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_data = buffer_x1_nodeOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_12_d_bits_corrupt = buffer_x1_nodeOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_a_ready = buffer_x1_nodeOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_14_a_valid = buffer_x1_nodeOut_13_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_opcode = buffer_x1_nodeOut_13_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_param = buffer_x1_nodeOut_13_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_size = buffer_x1_nodeOut_13_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_source = buffer_x1_nodeOut_13_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_address = buffer_x1_nodeOut_13_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_mask = buffer_x1_nodeOut_13_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_data = buffer_x1_nodeOut_13_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_14_a_bits_corrupt = buffer_x1_nodeOut_13_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_14_d_ready = buffer_x1_nodeOut_13_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_13_d_valid = buffer_x1_nodeOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_opcode = buffer_x1_nodeOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_param = buffer_x1_nodeOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_size = buffer_x1_nodeOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_source = buffer_x1_nodeOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_sink = buffer_x1_nodeOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_denied = buffer_x1_nodeOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_data = buffer_x1_nodeOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_13_d_bits_corrupt = buffer_x1_nodeOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_a_ready = buffer_x1_nodeOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_15_a_valid = buffer_x1_nodeOut_14_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_opcode = buffer_x1_nodeOut_14_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_param = buffer_x1_nodeOut_14_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_size = buffer_x1_nodeOut_14_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_source = buffer_x1_nodeOut_14_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_address = buffer_x1_nodeOut_14_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_mask = buffer_x1_nodeOut_14_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_data = buffer_x1_nodeOut_14_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_15_a_bits_corrupt = buffer_x1_nodeOut_14_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_15_d_ready = buffer_x1_nodeOut_14_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_14_d_valid = buffer_x1_nodeOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_opcode = buffer_x1_nodeOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_param = buffer_x1_nodeOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_size = buffer_x1_nodeOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_source = buffer_x1_nodeOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_sink = buffer_x1_nodeOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_denied = buffer_x1_nodeOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_data = buffer_x1_nodeOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_14_d_bits_corrupt = buffer_x1_nodeOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_a_ready = buffer_x1_nodeOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_16_a_valid = buffer_x1_nodeOut_15_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_opcode = buffer_x1_nodeOut_15_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_param = buffer_x1_nodeOut_15_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_size = buffer_x1_nodeOut_15_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_source = buffer_x1_nodeOut_15_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_address = buffer_x1_nodeOut_15_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_mask = buffer_x1_nodeOut_15_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_data = buffer_x1_nodeOut_15_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_16_a_bits_corrupt = buffer_x1_nodeOut_15_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_16_d_ready = buffer_x1_nodeOut_15_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_15_d_valid = buffer_x1_nodeOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_opcode = buffer_x1_nodeOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_param = buffer_x1_nodeOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_size = buffer_x1_nodeOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_source = buffer_x1_nodeOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_sink = buffer_x1_nodeOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_denied = buffer_x1_nodeOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_data = buffer_x1_nodeOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_15_d_bits_corrupt = buffer_x1_nodeOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_a_ready = buffer_x1_nodeOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_17_a_valid = buffer_x1_nodeOut_16_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_opcode = buffer_x1_nodeOut_16_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_param = buffer_x1_nodeOut_16_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_size = buffer_x1_nodeOut_16_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_source = buffer_x1_nodeOut_16_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_address = buffer_x1_nodeOut_16_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_mask = buffer_x1_nodeOut_16_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_data = buffer_x1_nodeOut_16_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_17_a_bits_corrupt = buffer_x1_nodeOut_16_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_17_d_ready = buffer_x1_nodeOut_16_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_16_d_valid = buffer_x1_nodeOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_opcode = buffer_x1_nodeOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_param = buffer_x1_nodeOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_size = buffer_x1_nodeOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_source = buffer_x1_nodeOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_sink = buffer_x1_nodeOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_denied = buffer_x1_nodeOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_data = buffer_x1_nodeOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_16_d_bits_corrupt = buffer_x1_nodeOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_a_ready = buffer_x1_nodeOut_17_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_a_valid = buffer_x1_nodeOut_17_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_opcode = buffer_x1_nodeOut_17_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_param = buffer_x1_nodeOut_17_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_size = buffer_x1_nodeOut_17_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_source = buffer_x1_nodeOut_17_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_address = buffer_x1_nodeOut_17_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_mask = buffer_x1_nodeOut_17_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_18_a_bits_data = buffer_x1_nodeOut_17_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_18_b_ready = buffer_x1_nodeOut_17_b_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_17_b_valid = buffer_x1_nodeOut_17_b_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_opcode = buffer_x1_nodeOut_17_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_param = buffer_x1_nodeOut_17_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_size = buffer_x1_nodeOut_17_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_source = buffer_x1_nodeOut_17_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_address = buffer_x1_nodeOut_17_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_mask = buffer_x1_nodeOut_17_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_data = buffer_x1_nodeOut_17_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_b_bits_corrupt = buffer_x1_nodeOut_17_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_c_ready = buffer_x1_nodeOut_17_c_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_c_valid = buffer_x1_nodeOut_17_c_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_opcode = buffer_x1_nodeOut_17_c_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_param = buffer_x1_nodeOut_17_c_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_size = buffer_x1_nodeOut_17_c_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_source = buffer_x1_nodeOut_17_c_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_address = buffer_x1_nodeOut_17_c_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_18_c_bits_data = buffer_x1_nodeOut_17_c_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_18_d_ready = buffer_x1_nodeOut_17_d_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeIn_17_d_valid = buffer_x1_nodeOut_17_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_opcode = buffer_x1_nodeOut_17_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_param = buffer_x1_nodeOut_17_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_size = buffer_x1_nodeOut_17_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_source = buffer_x1_nodeOut_17_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_sink = buffer_x1_nodeOut_17_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_denied = buffer_x1_nodeOut_17_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_data = buffer_x1_nodeOut_17_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_d_bits_corrupt = buffer_x1_nodeOut_17_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeIn_17_e_ready = buffer_x1_nodeOut_17_e_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_18_e_valid = buffer_x1_nodeOut_17_e_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_18_e_bits_sink = buffer_x1_nodeOut_17_e_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_0_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_0_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_0_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_1_a_ready = buffer_x1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_a_valid = buffer_x1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_opcode = buffer_x1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_param = buffer_x1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_size = buffer_x1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_source = buffer_x1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_address = buffer_x1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_mask = buffer_x1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_data = buffer_x1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_a_bits_corrupt = buffer_x1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_d_ready = buffer_x1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_1_d_valid = buffer_x1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_opcode = buffer_x1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_param = buffer_x1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_size = buffer_x1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_source = buffer_x1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_sink = buffer_x1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_denied = buffer_x1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_data = buffer_x1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_1_d_bits_corrupt = buffer_x1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_2_a_ready = buffer_x1_nodeIn_1_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_1_a_valid = buffer_x1_nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_opcode = buffer_x1_nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_param = buffer_x1_nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_size = buffer_x1_nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_source = buffer_x1_nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_address = buffer_x1_nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_mask = buffer_x1_nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_data = buffer_x1_nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_a_bits_corrupt = buffer_x1_nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_1_d_ready = buffer_x1_nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_2_d_valid = buffer_x1_nodeIn_1_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_opcode = buffer_x1_nodeIn_1_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_param = buffer_x1_nodeIn_1_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_size = buffer_x1_nodeIn_1_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_source = buffer_x1_nodeIn_1_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_sink = buffer_x1_nodeIn_1_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_denied = buffer_x1_nodeIn_1_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_data = buffer_x1_nodeIn_1_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_2_d_bits_corrupt = buffer_x1_nodeIn_1_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_3_a_ready = buffer_x1_nodeIn_2_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_2_a_valid = buffer_x1_nodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_opcode = buffer_x1_nodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_param = buffer_x1_nodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_size = buffer_x1_nodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_source = buffer_x1_nodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_address = buffer_x1_nodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_mask = buffer_x1_nodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_data = buffer_x1_nodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_a_bits_corrupt = buffer_x1_nodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_2_d_ready = buffer_x1_nodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_3_d_valid = buffer_x1_nodeIn_2_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_opcode = buffer_x1_nodeIn_2_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_param = buffer_x1_nodeIn_2_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_size = buffer_x1_nodeIn_2_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_source = buffer_x1_nodeIn_2_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_sink = buffer_x1_nodeIn_2_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_denied = buffer_x1_nodeIn_2_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_data = buffer_x1_nodeIn_2_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_3_d_bits_corrupt = buffer_x1_nodeIn_2_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_4_a_ready = buffer_x1_nodeIn_3_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_3_a_valid = buffer_x1_nodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_opcode = buffer_x1_nodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_param = buffer_x1_nodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_size = buffer_x1_nodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_source = buffer_x1_nodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_address = buffer_x1_nodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_mask = buffer_x1_nodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_data = buffer_x1_nodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_a_bits_corrupt = buffer_x1_nodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_3_d_ready = buffer_x1_nodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_4_d_valid = buffer_x1_nodeIn_3_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_opcode = buffer_x1_nodeIn_3_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_param = buffer_x1_nodeIn_3_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_size = buffer_x1_nodeIn_3_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_source = buffer_x1_nodeIn_3_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_sink = buffer_x1_nodeIn_3_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_denied = buffer_x1_nodeIn_3_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_data = buffer_x1_nodeIn_3_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_4_d_bits_corrupt = buffer_x1_nodeIn_3_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_5_a_ready = buffer_x1_nodeIn_4_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_4_a_valid = buffer_x1_nodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_opcode = buffer_x1_nodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_param = buffer_x1_nodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_size = buffer_x1_nodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_source = buffer_x1_nodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_address = buffer_x1_nodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_mask = buffer_x1_nodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_data = buffer_x1_nodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_a_bits_corrupt = buffer_x1_nodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_4_d_ready = buffer_x1_nodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_5_d_valid = buffer_x1_nodeIn_4_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_opcode = buffer_x1_nodeIn_4_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_param = buffer_x1_nodeIn_4_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_size = buffer_x1_nodeIn_4_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_source = buffer_x1_nodeIn_4_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_sink = buffer_x1_nodeIn_4_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_denied = buffer_x1_nodeIn_4_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_data = buffer_x1_nodeIn_4_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_5_d_bits_corrupt = buffer_x1_nodeIn_4_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_6_a_ready = buffer_x1_nodeIn_5_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_5_a_valid = buffer_x1_nodeIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_opcode = buffer_x1_nodeIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_param = buffer_x1_nodeIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_size = buffer_x1_nodeIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_source = buffer_x1_nodeIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_address = buffer_x1_nodeIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_mask = buffer_x1_nodeIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_data = buffer_x1_nodeIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_a_bits_corrupt = buffer_x1_nodeIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_5_d_ready = buffer_x1_nodeIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_6_d_valid = buffer_x1_nodeIn_5_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_opcode = buffer_x1_nodeIn_5_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_param = buffer_x1_nodeIn_5_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_size = buffer_x1_nodeIn_5_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_source = buffer_x1_nodeIn_5_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_sink = buffer_x1_nodeIn_5_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_denied = buffer_x1_nodeIn_5_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_data = buffer_x1_nodeIn_5_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_6_d_bits_corrupt = buffer_x1_nodeIn_5_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_7_a_ready = buffer_x1_nodeIn_6_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_6_a_valid = buffer_x1_nodeIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_opcode = buffer_x1_nodeIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_param = buffer_x1_nodeIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_size = buffer_x1_nodeIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_source = buffer_x1_nodeIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_address = buffer_x1_nodeIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_mask = buffer_x1_nodeIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_data = buffer_x1_nodeIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_a_bits_corrupt = buffer_x1_nodeIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_6_d_ready = buffer_x1_nodeIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_7_d_valid = buffer_x1_nodeIn_6_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_opcode = buffer_x1_nodeIn_6_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_param = buffer_x1_nodeIn_6_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_size = buffer_x1_nodeIn_6_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_source = buffer_x1_nodeIn_6_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_sink = buffer_x1_nodeIn_6_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_denied = buffer_x1_nodeIn_6_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_data = buffer_x1_nodeIn_6_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_7_d_bits_corrupt = buffer_x1_nodeIn_6_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_8_a_ready = buffer_x1_nodeIn_7_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_7_a_valid = buffer_x1_nodeIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_opcode = buffer_x1_nodeIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_param = buffer_x1_nodeIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_size = buffer_x1_nodeIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_source = buffer_x1_nodeIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_address = buffer_x1_nodeIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_mask = buffer_x1_nodeIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_data = buffer_x1_nodeIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_a_bits_corrupt = buffer_x1_nodeIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_7_d_ready = buffer_x1_nodeIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_8_d_valid = buffer_x1_nodeIn_7_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_opcode = buffer_x1_nodeIn_7_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_param = buffer_x1_nodeIn_7_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_size = buffer_x1_nodeIn_7_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_source = buffer_x1_nodeIn_7_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_sink = buffer_x1_nodeIn_7_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_denied = buffer_x1_nodeIn_7_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_data = buffer_x1_nodeIn_7_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_8_d_bits_corrupt = buffer_x1_nodeIn_7_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_9_a_ready = buffer_x1_nodeIn_8_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_8_a_valid = buffer_x1_nodeIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_opcode = buffer_x1_nodeIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_param = buffer_x1_nodeIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_size = buffer_x1_nodeIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_source = buffer_x1_nodeIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_address = buffer_x1_nodeIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_mask = buffer_x1_nodeIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_data = buffer_x1_nodeIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_a_bits_corrupt = buffer_x1_nodeIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_8_d_ready = buffer_x1_nodeIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_9_d_valid = buffer_x1_nodeIn_8_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_opcode = buffer_x1_nodeIn_8_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_param = buffer_x1_nodeIn_8_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_size = buffer_x1_nodeIn_8_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_source = buffer_x1_nodeIn_8_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_sink = buffer_x1_nodeIn_8_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_denied = buffer_x1_nodeIn_8_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_data = buffer_x1_nodeIn_8_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_9_d_bits_corrupt = buffer_x1_nodeIn_8_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_10_a_ready = buffer_x1_nodeIn_9_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_9_a_valid = buffer_x1_nodeIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_opcode = buffer_x1_nodeIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_param = buffer_x1_nodeIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_size = buffer_x1_nodeIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_source = buffer_x1_nodeIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_address = buffer_x1_nodeIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_mask = buffer_x1_nodeIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_data = buffer_x1_nodeIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_a_bits_corrupt = buffer_x1_nodeIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_9_d_ready = buffer_x1_nodeIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_10_d_valid = buffer_x1_nodeIn_9_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_opcode = buffer_x1_nodeIn_9_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_param = buffer_x1_nodeIn_9_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_size = buffer_x1_nodeIn_9_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_source = buffer_x1_nodeIn_9_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_sink = buffer_x1_nodeIn_9_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_denied = buffer_x1_nodeIn_9_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_data = buffer_x1_nodeIn_9_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_10_d_bits_corrupt = buffer_x1_nodeIn_9_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_11_a_ready = buffer_x1_nodeIn_10_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_10_a_valid = buffer_x1_nodeIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_opcode = buffer_x1_nodeIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_param = buffer_x1_nodeIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_size = buffer_x1_nodeIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_source = buffer_x1_nodeIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_address = buffer_x1_nodeIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_mask = buffer_x1_nodeIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_data = buffer_x1_nodeIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_a_bits_corrupt = buffer_x1_nodeIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_10_d_ready = buffer_x1_nodeIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_11_d_valid = buffer_x1_nodeIn_10_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_opcode = buffer_x1_nodeIn_10_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_param = buffer_x1_nodeIn_10_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_size = buffer_x1_nodeIn_10_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_source = buffer_x1_nodeIn_10_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_sink = buffer_x1_nodeIn_10_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_denied = buffer_x1_nodeIn_10_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_data = buffer_x1_nodeIn_10_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_11_d_bits_corrupt = buffer_x1_nodeIn_10_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_12_a_ready = buffer_x1_nodeIn_11_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_11_a_valid = buffer_x1_nodeIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_opcode = buffer_x1_nodeIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_param = buffer_x1_nodeIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_size = buffer_x1_nodeIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_source = buffer_x1_nodeIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_address = buffer_x1_nodeIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_mask = buffer_x1_nodeIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_data = buffer_x1_nodeIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_a_bits_corrupt = buffer_x1_nodeIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_11_d_ready = buffer_x1_nodeIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_12_d_valid = buffer_x1_nodeIn_11_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_opcode = buffer_x1_nodeIn_11_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_param = buffer_x1_nodeIn_11_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_size = buffer_x1_nodeIn_11_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_source = buffer_x1_nodeIn_11_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_sink = buffer_x1_nodeIn_11_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_denied = buffer_x1_nodeIn_11_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_data = buffer_x1_nodeIn_11_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_12_d_bits_corrupt = buffer_x1_nodeIn_11_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_13_a_ready = buffer_x1_nodeIn_12_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_12_a_valid = buffer_x1_nodeIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_opcode = buffer_x1_nodeIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_param = buffer_x1_nodeIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_size = buffer_x1_nodeIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_source = buffer_x1_nodeIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_address = buffer_x1_nodeIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_mask = buffer_x1_nodeIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_data = buffer_x1_nodeIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_a_bits_corrupt = buffer_x1_nodeIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_12_d_ready = buffer_x1_nodeIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_13_d_valid = buffer_x1_nodeIn_12_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_opcode = buffer_x1_nodeIn_12_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_param = buffer_x1_nodeIn_12_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_size = buffer_x1_nodeIn_12_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_source = buffer_x1_nodeIn_12_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_sink = buffer_x1_nodeIn_12_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_denied = buffer_x1_nodeIn_12_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_data = buffer_x1_nodeIn_12_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_13_d_bits_corrupt = buffer_x1_nodeIn_12_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_14_a_ready = buffer_x1_nodeIn_13_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_13_a_valid = buffer_x1_nodeIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_opcode = buffer_x1_nodeIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_param = buffer_x1_nodeIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_size = buffer_x1_nodeIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_source = buffer_x1_nodeIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_address = buffer_x1_nodeIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_mask = buffer_x1_nodeIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_data = buffer_x1_nodeIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_a_bits_corrupt = buffer_x1_nodeIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_13_d_ready = buffer_x1_nodeIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_14_d_valid = buffer_x1_nodeIn_13_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_opcode = buffer_x1_nodeIn_13_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_param = buffer_x1_nodeIn_13_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_size = buffer_x1_nodeIn_13_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_source = buffer_x1_nodeIn_13_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_sink = buffer_x1_nodeIn_13_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_denied = buffer_x1_nodeIn_13_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_data = buffer_x1_nodeIn_13_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_14_d_bits_corrupt = buffer_x1_nodeIn_13_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_15_a_ready = buffer_x1_nodeIn_14_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_14_a_valid = buffer_x1_nodeIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_opcode = buffer_x1_nodeIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_param = buffer_x1_nodeIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_size = buffer_x1_nodeIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_source = buffer_x1_nodeIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_address = buffer_x1_nodeIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_mask = buffer_x1_nodeIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_data = buffer_x1_nodeIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_a_bits_corrupt = buffer_x1_nodeIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_14_d_ready = buffer_x1_nodeIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_15_d_valid = buffer_x1_nodeIn_14_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_opcode = buffer_x1_nodeIn_14_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_param = buffer_x1_nodeIn_14_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_size = buffer_x1_nodeIn_14_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_source = buffer_x1_nodeIn_14_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_sink = buffer_x1_nodeIn_14_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_denied = buffer_x1_nodeIn_14_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_data = buffer_x1_nodeIn_14_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_15_d_bits_corrupt = buffer_x1_nodeIn_14_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_16_a_ready = buffer_x1_nodeIn_15_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_15_a_valid = buffer_x1_nodeIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_opcode = buffer_x1_nodeIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_param = buffer_x1_nodeIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_size = buffer_x1_nodeIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_source = buffer_x1_nodeIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_address = buffer_x1_nodeIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_mask = buffer_x1_nodeIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_data = buffer_x1_nodeIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_a_bits_corrupt = buffer_x1_nodeIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_15_d_ready = buffer_x1_nodeIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_16_d_valid = buffer_x1_nodeIn_15_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_opcode = buffer_x1_nodeIn_15_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_param = buffer_x1_nodeIn_15_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_size = buffer_x1_nodeIn_15_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_source = buffer_x1_nodeIn_15_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_sink = buffer_x1_nodeIn_15_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_denied = buffer_x1_nodeIn_15_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_data = buffer_x1_nodeIn_15_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_16_d_bits_corrupt = buffer_x1_nodeIn_15_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_17_a_ready = buffer_x1_nodeIn_16_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_16_a_valid = buffer_x1_nodeIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_opcode = buffer_x1_nodeIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_param = buffer_x1_nodeIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_size = buffer_x1_nodeIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_source = buffer_x1_nodeIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_address = buffer_x1_nodeIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_mask = buffer_x1_nodeIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_data = buffer_x1_nodeIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_a_bits_corrupt = buffer_x1_nodeIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_16_d_ready = buffer_x1_nodeIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_17_d_valid = buffer_x1_nodeIn_16_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_opcode = buffer_x1_nodeIn_16_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_param = buffer_x1_nodeIn_16_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_size = buffer_x1_nodeIn_16_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_source = buffer_x1_nodeIn_16_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_sink = buffer_x1_nodeIn_16_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_denied = buffer_x1_nodeIn_16_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_data = buffer_x1_nodeIn_16_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_17_d_bits_corrupt = buffer_x1_nodeIn_16_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_a_ready = buffer_x1_nodeIn_17_a_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_a_valid = buffer_x1_nodeIn_17_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_opcode = buffer_x1_nodeIn_17_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_param = buffer_x1_nodeIn_17_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_size = buffer_x1_nodeIn_17_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_source = buffer_x1_nodeIn_17_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_address = buffer_x1_nodeIn_17_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_mask = buffer_x1_nodeIn_17_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_a_bits_data = buffer_x1_nodeIn_17_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_b_ready = buffer_x1_nodeIn_17_b_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_18_b_valid = buffer_x1_nodeIn_17_b_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_opcode = buffer_x1_nodeIn_17_b_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_param = buffer_x1_nodeIn_17_b_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_size = buffer_x1_nodeIn_17_b_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_source = buffer_x1_nodeIn_17_b_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_address = buffer_x1_nodeIn_17_b_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_mask = buffer_x1_nodeIn_17_b_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_data = buffer_x1_nodeIn_17_b_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_18_b_bits_corrupt = buffer_x1_nodeIn_17_b_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_c_ready = buffer_x1_nodeIn_17_c_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_c_valid = buffer_x1_nodeIn_17_c_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_opcode = buffer_x1_nodeIn_17_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_param = buffer_x1_nodeIn_17_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_size = buffer_x1_nodeIn_17_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_source = buffer_x1_nodeIn_17_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_address = buffer_x1_nodeIn_17_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_c_bits_data = buffer_x1_nodeIn_17_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_d_ready = buffer_x1_nodeIn_17_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_18_d_valid = buffer_x1_nodeIn_17_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_opcode = buffer_x1_nodeIn_17_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_param = buffer_x1_nodeIn_17_d_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_size = buffer_x1_nodeIn_17_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_source = buffer_x1_nodeIn_17_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_sink = buffer_x1_nodeIn_17_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_denied = buffer_x1_nodeIn_17_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_data = buffer_x1_nodeIn_17_d_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_18_d_bits_corrupt = buffer_x1_nodeIn_17_d_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_18_e_ready = buffer_x1_nodeIn_17_e_ready; // @[Buffer.scala:40:9] assign buffer_x1_nodeOut_17_e_valid = buffer_x1_nodeIn_17_e_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_x1_nodeOut_17_e_bits_sink = buffer_x1_nodeIn_17_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_0_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_a_ready = x1_tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_valid = x1_tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_opcode = x1_tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_param = x1_tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_size = x1_tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_source = x1_tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_address = x1_tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_mask = x1_tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_data = x1_tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_a_bits_corrupt = x1_tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_1_d_ready = x1_tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_d_valid = x1_tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_d_bits_opcode = x1_tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_d_bits_param = x1_tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_d_bits_size = x1_tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_d_bits_source = x1_tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_d_bits_sink = x1_tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_d_bits_denied = x1_tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_d_bits_data = x1_tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_d_bits_corrupt = x1_tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_a_ready = x1_tlOtherMastersNodeOut_1_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_valid = x1_tlOtherMastersNodeOut_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_1_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_opcode = x1_tlOtherMastersNodeOut_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_1_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_param = x1_tlOtherMastersNodeOut_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_1_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_size = x1_tlOtherMastersNodeOut_1_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_1_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_source = x1_tlOtherMastersNodeOut_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_1_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_address = x1_tlOtherMastersNodeOut_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_1_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_mask = x1_tlOtherMastersNodeOut_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_1_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_data = x1_tlOtherMastersNodeOut_1_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_a_bits_corrupt = x1_tlOtherMastersNodeOut_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_2_d_ready = x1_tlOtherMastersNodeOut_1_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_1_d_valid = x1_tlOtherMastersNodeOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_1_d_bits_opcode = x1_tlOtherMastersNodeOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_1_d_bits_param = x1_tlOtherMastersNodeOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_1_d_bits_size = x1_tlOtherMastersNodeOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_1_d_bits_source = x1_tlOtherMastersNodeOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_1_d_bits_sink = x1_tlOtherMastersNodeOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_d_bits_denied = x1_tlOtherMastersNodeOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_1_d_bits_data = x1_tlOtherMastersNodeOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_1_d_bits_corrupt = x1_tlOtherMastersNodeOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_a_ready = x1_tlOtherMastersNodeOut_2_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_valid = x1_tlOtherMastersNodeOut_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_2_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_opcode = x1_tlOtherMastersNodeOut_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_2_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_param = x1_tlOtherMastersNodeOut_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_2_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_size = x1_tlOtherMastersNodeOut_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_2_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_source = x1_tlOtherMastersNodeOut_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_2_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_address = x1_tlOtherMastersNodeOut_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_2_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_mask = x1_tlOtherMastersNodeOut_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_2_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_data = x1_tlOtherMastersNodeOut_2_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_a_bits_corrupt = x1_tlOtherMastersNodeOut_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_3_d_ready = x1_tlOtherMastersNodeOut_2_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_2_d_valid = x1_tlOtherMastersNodeOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_2_d_bits_opcode = x1_tlOtherMastersNodeOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_2_d_bits_param = x1_tlOtherMastersNodeOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_2_d_bits_size = x1_tlOtherMastersNodeOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_2_d_bits_source = x1_tlOtherMastersNodeOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_2_d_bits_sink = x1_tlOtherMastersNodeOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_d_bits_denied = x1_tlOtherMastersNodeOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_2_d_bits_data = x1_tlOtherMastersNodeOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_2_d_bits_corrupt = x1_tlOtherMastersNodeOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_a_ready = x1_tlOtherMastersNodeOut_3_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_valid = x1_tlOtherMastersNodeOut_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_3_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_opcode = x1_tlOtherMastersNodeOut_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_3_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_param = x1_tlOtherMastersNodeOut_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_3_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_size = x1_tlOtherMastersNodeOut_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_3_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_source = x1_tlOtherMastersNodeOut_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_3_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_address = x1_tlOtherMastersNodeOut_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_3_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_mask = x1_tlOtherMastersNodeOut_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_3_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_data = x1_tlOtherMastersNodeOut_3_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_a_bits_corrupt = x1_tlOtherMastersNodeOut_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_4_d_ready = x1_tlOtherMastersNodeOut_3_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_3_d_valid = x1_tlOtherMastersNodeOut_3_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_3_d_bits_opcode = x1_tlOtherMastersNodeOut_3_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_3_d_bits_param = x1_tlOtherMastersNodeOut_3_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_3_d_bits_size = x1_tlOtherMastersNodeOut_3_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_3_d_bits_source = x1_tlOtherMastersNodeOut_3_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_3_d_bits_sink = x1_tlOtherMastersNodeOut_3_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_d_bits_denied = x1_tlOtherMastersNodeOut_3_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_3_d_bits_data = x1_tlOtherMastersNodeOut_3_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_3_d_bits_corrupt = x1_tlOtherMastersNodeOut_3_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_a_ready = x1_tlOtherMastersNodeOut_4_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_valid = x1_tlOtherMastersNodeOut_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_4_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_opcode = x1_tlOtherMastersNodeOut_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_4_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_param = x1_tlOtherMastersNodeOut_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_4_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_size = x1_tlOtherMastersNodeOut_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_4_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_source = x1_tlOtherMastersNodeOut_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_4_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_address = x1_tlOtherMastersNodeOut_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_4_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_mask = x1_tlOtherMastersNodeOut_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_4_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_data = x1_tlOtherMastersNodeOut_4_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_a_bits_corrupt = x1_tlOtherMastersNodeOut_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_5_d_ready = x1_tlOtherMastersNodeOut_4_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_4_d_valid = x1_tlOtherMastersNodeOut_4_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_4_d_bits_opcode = x1_tlOtherMastersNodeOut_4_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_4_d_bits_param = x1_tlOtherMastersNodeOut_4_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_4_d_bits_size = x1_tlOtherMastersNodeOut_4_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_4_d_bits_source = x1_tlOtherMastersNodeOut_4_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_4_d_bits_sink = x1_tlOtherMastersNodeOut_4_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_d_bits_denied = x1_tlOtherMastersNodeOut_4_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_4_d_bits_data = x1_tlOtherMastersNodeOut_4_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_4_d_bits_corrupt = x1_tlOtherMastersNodeOut_4_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_a_ready = x1_tlOtherMastersNodeOut_5_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_valid = x1_tlOtherMastersNodeOut_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_5_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_opcode = x1_tlOtherMastersNodeOut_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_5_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_param = x1_tlOtherMastersNodeOut_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_5_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_size = x1_tlOtherMastersNodeOut_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_5_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_source = x1_tlOtherMastersNodeOut_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_5_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_address = x1_tlOtherMastersNodeOut_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_5_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_mask = x1_tlOtherMastersNodeOut_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_5_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_data = x1_tlOtherMastersNodeOut_5_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_a_bits_corrupt = x1_tlOtherMastersNodeOut_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_6_d_ready = x1_tlOtherMastersNodeOut_5_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_5_d_valid = x1_tlOtherMastersNodeOut_5_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_5_d_bits_opcode = x1_tlOtherMastersNodeOut_5_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_5_d_bits_param = x1_tlOtherMastersNodeOut_5_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_5_d_bits_size = x1_tlOtherMastersNodeOut_5_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_5_d_bits_source = x1_tlOtherMastersNodeOut_5_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_5_d_bits_sink = x1_tlOtherMastersNodeOut_5_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_d_bits_denied = x1_tlOtherMastersNodeOut_5_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_5_d_bits_data = x1_tlOtherMastersNodeOut_5_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_5_d_bits_corrupt = x1_tlOtherMastersNodeOut_5_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_a_ready = x1_tlOtherMastersNodeOut_6_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_valid = x1_tlOtherMastersNodeOut_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_6_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_opcode = x1_tlOtherMastersNodeOut_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_6_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_param = x1_tlOtherMastersNodeOut_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_6_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_size = x1_tlOtherMastersNodeOut_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_6_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_source = x1_tlOtherMastersNodeOut_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_6_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_address = x1_tlOtherMastersNodeOut_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_6_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_mask = x1_tlOtherMastersNodeOut_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_6_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_data = x1_tlOtherMastersNodeOut_6_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_a_bits_corrupt = x1_tlOtherMastersNodeOut_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_7_d_ready = x1_tlOtherMastersNodeOut_6_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_6_d_valid = x1_tlOtherMastersNodeOut_6_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_6_d_bits_opcode = x1_tlOtherMastersNodeOut_6_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_6_d_bits_param = x1_tlOtherMastersNodeOut_6_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_6_d_bits_size = x1_tlOtherMastersNodeOut_6_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_6_d_bits_source = x1_tlOtherMastersNodeOut_6_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_6_d_bits_sink = x1_tlOtherMastersNodeOut_6_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_d_bits_denied = x1_tlOtherMastersNodeOut_6_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_6_d_bits_data = x1_tlOtherMastersNodeOut_6_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_6_d_bits_corrupt = x1_tlOtherMastersNodeOut_6_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_a_ready = x1_tlOtherMastersNodeOut_7_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_valid = x1_tlOtherMastersNodeOut_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_7_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_opcode = x1_tlOtherMastersNodeOut_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_7_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_param = x1_tlOtherMastersNodeOut_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_7_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_size = x1_tlOtherMastersNodeOut_7_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_7_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_source = x1_tlOtherMastersNodeOut_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_7_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_address = x1_tlOtherMastersNodeOut_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_7_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_mask = x1_tlOtherMastersNodeOut_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_7_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_data = x1_tlOtherMastersNodeOut_7_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_a_bits_corrupt = x1_tlOtherMastersNodeOut_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_8_d_ready = x1_tlOtherMastersNodeOut_7_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_7_d_valid = x1_tlOtherMastersNodeOut_7_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_7_d_bits_opcode = x1_tlOtherMastersNodeOut_7_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_7_d_bits_param = x1_tlOtherMastersNodeOut_7_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_7_d_bits_size = x1_tlOtherMastersNodeOut_7_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_7_d_bits_source = x1_tlOtherMastersNodeOut_7_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_7_d_bits_sink = x1_tlOtherMastersNodeOut_7_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_d_bits_denied = x1_tlOtherMastersNodeOut_7_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_7_d_bits_data = x1_tlOtherMastersNodeOut_7_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_7_d_bits_corrupt = x1_tlOtherMastersNodeOut_7_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_a_ready = x1_tlOtherMastersNodeOut_8_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_valid = x1_tlOtherMastersNodeOut_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_8_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_opcode = x1_tlOtherMastersNodeOut_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_8_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_param = x1_tlOtherMastersNodeOut_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_8_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_size = x1_tlOtherMastersNodeOut_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_8_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_source = x1_tlOtherMastersNodeOut_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_8_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_address = x1_tlOtherMastersNodeOut_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_8_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_mask = x1_tlOtherMastersNodeOut_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_8_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_data = x1_tlOtherMastersNodeOut_8_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_a_bits_corrupt = x1_tlOtherMastersNodeOut_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_9_d_ready = x1_tlOtherMastersNodeOut_8_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_8_d_valid = x1_tlOtherMastersNodeOut_8_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_8_d_bits_opcode = x1_tlOtherMastersNodeOut_8_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_8_d_bits_param = x1_tlOtherMastersNodeOut_8_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_8_d_bits_size = x1_tlOtherMastersNodeOut_8_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_8_d_bits_source = x1_tlOtherMastersNodeOut_8_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_8_d_bits_sink = x1_tlOtherMastersNodeOut_8_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_d_bits_denied = x1_tlOtherMastersNodeOut_8_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_8_d_bits_data = x1_tlOtherMastersNodeOut_8_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_8_d_bits_corrupt = x1_tlOtherMastersNodeOut_8_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_a_ready = x1_tlOtherMastersNodeOut_9_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_valid = x1_tlOtherMastersNodeOut_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_9_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_opcode = x1_tlOtherMastersNodeOut_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_9_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_param = x1_tlOtherMastersNodeOut_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_9_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_size = x1_tlOtherMastersNodeOut_9_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_9_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_source = x1_tlOtherMastersNodeOut_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_9_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_address = x1_tlOtherMastersNodeOut_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_9_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_mask = x1_tlOtherMastersNodeOut_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_9_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_data = x1_tlOtherMastersNodeOut_9_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_a_bits_corrupt = x1_tlOtherMastersNodeOut_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_10_d_ready = x1_tlOtherMastersNodeOut_9_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_9_d_valid = x1_tlOtherMastersNodeOut_9_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_9_d_bits_opcode = x1_tlOtherMastersNodeOut_9_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_9_d_bits_param = x1_tlOtherMastersNodeOut_9_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_9_d_bits_size = x1_tlOtherMastersNodeOut_9_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_9_d_bits_source = x1_tlOtherMastersNodeOut_9_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_9_d_bits_sink = x1_tlOtherMastersNodeOut_9_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_d_bits_denied = x1_tlOtherMastersNodeOut_9_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_9_d_bits_data = x1_tlOtherMastersNodeOut_9_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_9_d_bits_corrupt = x1_tlOtherMastersNodeOut_9_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_a_ready = x1_tlOtherMastersNodeOut_10_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_valid = x1_tlOtherMastersNodeOut_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_10_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_opcode = x1_tlOtherMastersNodeOut_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_10_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_param = x1_tlOtherMastersNodeOut_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_10_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_size = x1_tlOtherMastersNodeOut_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_10_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_source = x1_tlOtherMastersNodeOut_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_10_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_address = x1_tlOtherMastersNodeOut_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_10_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_mask = x1_tlOtherMastersNodeOut_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_10_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_data = x1_tlOtherMastersNodeOut_10_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_a_bits_corrupt = x1_tlOtherMastersNodeOut_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_11_d_ready = x1_tlOtherMastersNodeOut_10_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_10_d_valid = x1_tlOtherMastersNodeOut_10_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_10_d_bits_opcode = x1_tlOtherMastersNodeOut_10_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_10_d_bits_param = x1_tlOtherMastersNodeOut_10_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_10_d_bits_size = x1_tlOtherMastersNodeOut_10_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_10_d_bits_source = x1_tlOtherMastersNodeOut_10_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_10_d_bits_sink = x1_tlOtherMastersNodeOut_10_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_d_bits_denied = x1_tlOtherMastersNodeOut_10_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_10_d_bits_data = x1_tlOtherMastersNodeOut_10_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_10_d_bits_corrupt = x1_tlOtherMastersNodeOut_10_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_a_ready = x1_tlOtherMastersNodeOut_11_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_valid = x1_tlOtherMastersNodeOut_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_11_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_opcode = x1_tlOtherMastersNodeOut_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_11_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_param = x1_tlOtherMastersNodeOut_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_11_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_size = x1_tlOtherMastersNodeOut_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_11_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_source = x1_tlOtherMastersNodeOut_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_11_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_address = x1_tlOtherMastersNodeOut_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_11_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_mask = x1_tlOtherMastersNodeOut_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_11_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_data = x1_tlOtherMastersNodeOut_11_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_a_bits_corrupt = x1_tlOtherMastersNodeOut_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_12_d_ready = x1_tlOtherMastersNodeOut_11_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_11_d_valid = x1_tlOtherMastersNodeOut_11_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_11_d_bits_opcode = x1_tlOtherMastersNodeOut_11_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_11_d_bits_param = x1_tlOtherMastersNodeOut_11_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_11_d_bits_size = x1_tlOtherMastersNodeOut_11_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_11_d_bits_source = x1_tlOtherMastersNodeOut_11_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_11_d_bits_sink = x1_tlOtherMastersNodeOut_11_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_d_bits_denied = x1_tlOtherMastersNodeOut_11_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_11_d_bits_data = x1_tlOtherMastersNodeOut_11_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_11_d_bits_corrupt = x1_tlOtherMastersNodeOut_11_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_a_ready = x1_tlOtherMastersNodeOut_12_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_valid = x1_tlOtherMastersNodeOut_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_12_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_opcode = x1_tlOtherMastersNodeOut_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_12_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_param = x1_tlOtherMastersNodeOut_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_12_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_size = x1_tlOtherMastersNodeOut_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_12_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_source = x1_tlOtherMastersNodeOut_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_12_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_address = x1_tlOtherMastersNodeOut_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_12_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_mask = x1_tlOtherMastersNodeOut_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_12_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_data = x1_tlOtherMastersNodeOut_12_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_a_bits_corrupt = x1_tlOtherMastersNodeOut_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_13_d_ready = x1_tlOtherMastersNodeOut_12_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_12_d_valid = x1_tlOtherMastersNodeOut_12_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_12_d_bits_opcode = x1_tlOtherMastersNodeOut_12_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_12_d_bits_param = x1_tlOtherMastersNodeOut_12_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_12_d_bits_size = x1_tlOtherMastersNodeOut_12_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_12_d_bits_source = x1_tlOtherMastersNodeOut_12_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_12_d_bits_sink = x1_tlOtherMastersNodeOut_12_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_d_bits_denied = x1_tlOtherMastersNodeOut_12_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_12_d_bits_data = x1_tlOtherMastersNodeOut_12_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_12_d_bits_corrupt = x1_tlOtherMastersNodeOut_12_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_a_ready = x1_tlOtherMastersNodeOut_13_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_valid = x1_tlOtherMastersNodeOut_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_13_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_opcode = x1_tlOtherMastersNodeOut_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_13_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_param = x1_tlOtherMastersNodeOut_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_13_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_size = x1_tlOtherMastersNodeOut_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_13_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_source = x1_tlOtherMastersNodeOut_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_13_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_address = x1_tlOtherMastersNodeOut_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_13_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_mask = x1_tlOtherMastersNodeOut_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_13_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_data = x1_tlOtherMastersNodeOut_13_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_a_bits_corrupt = x1_tlOtherMastersNodeOut_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_14_d_ready = x1_tlOtherMastersNodeOut_13_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_13_d_valid = x1_tlOtherMastersNodeOut_13_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_13_d_bits_opcode = x1_tlOtherMastersNodeOut_13_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_13_d_bits_param = x1_tlOtherMastersNodeOut_13_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_13_d_bits_size = x1_tlOtherMastersNodeOut_13_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_13_d_bits_source = x1_tlOtherMastersNodeOut_13_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_13_d_bits_sink = x1_tlOtherMastersNodeOut_13_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_d_bits_denied = x1_tlOtherMastersNodeOut_13_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_13_d_bits_data = x1_tlOtherMastersNodeOut_13_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_13_d_bits_corrupt = x1_tlOtherMastersNodeOut_13_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_a_ready = x1_tlOtherMastersNodeOut_14_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_valid = x1_tlOtherMastersNodeOut_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_14_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_opcode = x1_tlOtherMastersNodeOut_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_14_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_param = x1_tlOtherMastersNodeOut_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_14_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_size = x1_tlOtherMastersNodeOut_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_14_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_source = x1_tlOtherMastersNodeOut_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_14_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_address = x1_tlOtherMastersNodeOut_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_14_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_mask = x1_tlOtherMastersNodeOut_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_14_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_data = x1_tlOtherMastersNodeOut_14_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_a_bits_corrupt = x1_tlOtherMastersNodeOut_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_15_d_ready = x1_tlOtherMastersNodeOut_14_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_14_d_valid = x1_tlOtherMastersNodeOut_14_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_14_d_bits_opcode = x1_tlOtherMastersNodeOut_14_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_14_d_bits_param = x1_tlOtherMastersNodeOut_14_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_14_d_bits_size = x1_tlOtherMastersNodeOut_14_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_14_d_bits_source = x1_tlOtherMastersNodeOut_14_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_14_d_bits_sink = x1_tlOtherMastersNodeOut_14_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_d_bits_denied = x1_tlOtherMastersNodeOut_14_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_14_d_bits_data = x1_tlOtherMastersNodeOut_14_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_14_d_bits_corrupt = x1_tlOtherMastersNodeOut_14_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_a_ready = x1_tlOtherMastersNodeOut_15_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_valid = x1_tlOtherMastersNodeOut_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_15_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_opcode = x1_tlOtherMastersNodeOut_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_15_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_param = x1_tlOtherMastersNodeOut_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_15_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_size = x1_tlOtherMastersNodeOut_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_15_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_source = x1_tlOtherMastersNodeOut_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_15_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_address = x1_tlOtherMastersNodeOut_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_15_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_mask = x1_tlOtherMastersNodeOut_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_15_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_data = x1_tlOtherMastersNodeOut_15_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_a_bits_corrupt = x1_tlOtherMastersNodeOut_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_16_d_ready = x1_tlOtherMastersNodeOut_15_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_15_d_valid = x1_tlOtherMastersNodeOut_15_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_15_d_bits_opcode = x1_tlOtherMastersNodeOut_15_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_15_d_bits_param = x1_tlOtherMastersNodeOut_15_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_15_d_bits_size = x1_tlOtherMastersNodeOut_15_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_15_d_bits_source = x1_tlOtherMastersNodeOut_15_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_15_d_bits_sink = x1_tlOtherMastersNodeOut_15_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_d_bits_denied = x1_tlOtherMastersNodeOut_15_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_15_d_bits_data = x1_tlOtherMastersNodeOut_15_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_15_d_bits_corrupt = x1_tlOtherMastersNodeOut_15_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_a_ready = x1_tlOtherMastersNodeOut_16_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_valid = x1_tlOtherMastersNodeOut_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_16_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_opcode = x1_tlOtherMastersNodeOut_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_16_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_param = x1_tlOtherMastersNodeOut_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_16_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_size = x1_tlOtherMastersNodeOut_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] x1_tlOtherMastersNodeIn_16_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_source = x1_tlOtherMastersNodeOut_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_16_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_address = x1_tlOtherMastersNodeOut_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_16_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_mask = x1_tlOtherMastersNodeOut_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_16_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_data = x1_tlOtherMastersNodeOut_16_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_a_bits_corrupt = x1_tlOtherMastersNodeOut_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_17_d_ready = x1_tlOtherMastersNodeOut_16_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_16_d_valid = x1_tlOtherMastersNodeOut_16_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_16_d_bits_opcode = x1_tlOtherMastersNodeOut_16_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_16_d_bits_param = x1_tlOtherMastersNodeOut_16_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_16_d_bits_size = x1_tlOtherMastersNodeOut_16_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [4:0] x1_tlOtherMastersNodeIn_16_d_bits_source = x1_tlOtherMastersNodeOut_16_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_16_d_bits_sink = x1_tlOtherMastersNodeOut_16_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_d_bits_denied = x1_tlOtherMastersNodeOut_16_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_16_d_bits_data = x1_tlOtherMastersNodeOut_16_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_16_d_bits_corrupt = x1_tlOtherMastersNodeOut_16_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_a_ready = x1_tlOtherMastersNodeOut_17_a_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_a_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_valid = x1_tlOtherMastersNodeOut_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_a_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_opcode = x1_tlOtherMastersNodeOut_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_a_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_param = x1_tlOtherMastersNodeOut_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_17_a_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_size = x1_tlOtherMastersNodeOut_17_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_17_a_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_source = x1_tlOtherMastersNodeOut_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_17_a_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_address = x1_tlOtherMastersNodeOut_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] x1_tlOtherMastersNodeIn_17_a_bits_mask; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_mask = x1_tlOtherMastersNodeOut_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_17_a_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_a_bits_data = x1_tlOtherMastersNodeOut_17_a_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_b_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_b_ready = x1_tlOtherMastersNodeOut_17_b_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_b_valid = x1_tlOtherMastersNodeOut_17_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_b_bits_opcode = x1_tlOtherMastersNodeOut_17_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_b_bits_param = x1_tlOtherMastersNodeOut_17_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_17_b_bits_size = x1_tlOtherMastersNodeOut_17_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_b_bits_source = x1_tlOtherMastersNodeOut_17_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] x1_tlOtherMastersNodeIn_17_b_bits_address = x1_tlOtherMastersNodeOut_17_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] x1_tlOtherMastersNodeIn_17_b_bits_mask = x1_tlOtherMastersNodeOut_17_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_17_b_bits_data = x1_tlOtherMastersNodeOut_17_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_b_bits_corrupt = x1_tlOtherMastersNodeOut_17_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_c_ready = x1_tlOtherMastersNodeOut_17_c_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_c_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_valid = x1_tlOtherMastersNodeOut_17_c_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_c_bits_opcode; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_opcode = x1_tlOtherMastersNodeOut_17_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_c_bits_param; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_param = x1_tlOtherMastersNodeOut_17_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] x1_tlOtherMastersNodeIn_17_c_bits_size; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_size = x1_tlOtherMastersNodeOut_17_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] x1_tlOtherMastersNodeIn_17_c_bits_source; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_source = x1_tlOtherMastersNodeOut_17_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] x1_tlOtherMastersNodeIn_17_c_bits_address; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_address = x1_tlOtherMastersNodeOut_17_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] x1_tlOtherMastersNodeIn_17_c_bits_data; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_c_bits_data = x1_tlOtherMastersNodeOut_17_c_bits_data; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_d_ready; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_d_ready = x1_tlOtherMastersNodeOut_17_d_ready; // @[Buffer.scala:40:9] wire x1_tlOtherMastersNodeIn_17_d_valid = x1_tlOtherMastersNodeOut_17_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_d_bits_opcode = x1_tlOtherMastersNodeOut_17_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_d_bits_param = x1_tlOtherMastersNodeOut_17_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] x1_tlOtherMastersNodeIn_17_d_bits_size = x1_tlOtherMastersNodeOut_17_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] x1_tlOtherMastersNodeIn_17_d_bits_source = x1_tlOtherMastersNodeOut_17_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] x1_tlOtherMastersNodeIn_17_d_bits_sink = x1_tlOtherMastersNodeOut_17_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_d_bits_denied = x1_tlOtherMastersNodeOut_17_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] x1_tlOtherMastersNodeIn_17_d_bits_data = x1_tlOtherMastersNodeOut_17_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_d_bits_corrupt = x1_tlOtherMastersNodeOut_17_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_e_ready = x1_tlOtherMastersNodeOut_17_e_ready; // @[MixedNode.scala:542:17, :551:17] wire x1_tlOtherMastersNodeIn_17_e_valid; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_e_valid = x1_tlOtherMastersNodeOut_17_e_valid; // @[Buffer.scala:40:9] wire [2:0] x1_tlOtherMastersNodeIn_17_e_bits_sink; // @[MixedNode.scala:551:17] assign buffer_auto_in_18_e_bits_sink = x1_tlOtherMastersNodeOut_17_e_bits_sink; // @[Buffer.scala:40:9] assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_valid = x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_opcode = x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_param = x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_size = x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_source = x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_address = x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_mask = x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_data = x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_a_bits_corrupt = x1_tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_d_ready = x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_valid = x1_tlOtherMastersNodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_opcode = x1_tlOtherMastersNodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_param = x1_tlOtherMastersNodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_size = x1_tlOtherMastersNodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_source = x1_tlOtherMastersNodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_address = x1_tlOtherMastersNodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_mask = x1_tlOtherMastersNodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_data = x1_tlOtherMastersNodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_a_bits_corrupt = x1_tlOtherMastersNodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_1_d_ready = x1_tlOtherMastersNodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_valid = x1_tlOtherMastersNodeIn_2_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_opcode = x1_tlOtherMastersNodeIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_param = x1_tlOtherMastersNodeIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_size = x1_tlOtherMastersNodeIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_source = x1_tlOtherMastersNodeIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_address = x1_tlOtherMastersNodeIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_mask = x1_tlOtherMastersNodeIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_data = x1_tlOtherMastersNodeIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_a_bits_corrupt = x1_tlOtherMastersNodeIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_2_d_ready = x1_tlOtherMastersNodeIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_valid = x1_tlOtherMastersNodeIn_3_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_opcode = x1_tlOtherMastersNodeIn_3_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_param = x1_tlOtherMastersNodeIn_3_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_size = x1_tlOtherMastersNodeIn_3_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_source = x1_tlOtherMastersNodeIn_3_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_address = x1_tlOtherMastersNodeIn_3_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_mask = x1_tlOtherMastersNodeIn_3_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_data = x1_tlOtherMastersNodeIn_3_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_a_bits_corrupt = x1_tlOtherMastersNodeIn_3_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_3_d_ready = x1_tlOtherMastersNodeIn_3_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_valid = x1_tlOtherMastersNodeIn_4_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_opcode = x1_tlOtherMastersNodeIn_4_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_param = x1_tlOtherMastersNodeIn_4_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_size = x1_tlOtherMastersNodeIn_4_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_source = x1_tlOtherMastersNodeIn_4_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_address = x1_tlOtherMastersNodeIn_4_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_mask = x1_tlOtherMastersNodeIn_4_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_data = x1_tlOtherMastersNodeIn_4_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_a_bits_corrupt = x1_tlOtherMastersNodeIn_4_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_4_d_ready = x1_tlOtherMastersNodeIn_4_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_valid = x1_tlOtherMastersNodeIn_5_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_opcode = x1_tlOtherMastersNodeIn_5_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_param = x1_tlOtherMastersNodeIn_5_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_size = x1_tlOtherMastersNodeIn_5_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_source = x1_tlOtherMastersNodeIn_5_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_address = x1_tlOtherMastersNodeIn_5_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_mask = x1_tlOtherMastersNodeIn_5_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_data = x1_tlOtherMastersNodeIn_5_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_a_bits_corrupt = x1_tlOtherMastersNodeIn_5_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_5_d_ready = x1_tlOtherMastersNodeIn_5_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_valid = x1_tlOtherMastersNodeIn_6_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_opcode = x1_tlOtherMastersNodeIn_6_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_param = x1_tlOtherMastersNodeIn_6_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_size = x1_tlOtherMastersNodeIn_6_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_source = x1_tlOtherMastersNodeIn_6_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_address = x1_tlOtherMastersNodeIn_6_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_mask = x1_tlOtherMastersNodeIn_6_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_data = x1_tlOtherMastersNodeIn_6_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_a_bits_corrupt = x1_tlOtherMastersNodeIn_6_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_6_d_ready = x1_tlOtherMastersNodeIn_6_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_valid = x1_tlOtherMastersNodeIn_7_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_opcode = x1_tlOtherMastersNodeIn_7_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_param = x1_tlOtherMastersNodeIn_7_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_size = x1_tlOtherMastersNodeIn_7_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_source = x1_tlOtherMastersNodeIn_7_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_address = x1_tlOtherMastersNodeIn_7_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_mask = x1_tlOtherMastersNodeIn_7_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_data = x1_tlOtherMastersNodeIn_7_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_a_bits_corrupt = x1_tlOtherMastersNodeIn_7_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_7_d_ready = x1_tlOtherMastersNodeIn_7_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_valid = x1_tlOtherMastersNodeIn_8_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_opcode = x1_tlOtherMastersNodeIn_8_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_param = x1_tlOtherMastersNodeIn_8_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_size = x1_tlOtherMastersNodeIn_8_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_source = x1_tlOtherMastersNodeIn_8_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_address = x1_tlOtherMastersNodeIn_8_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_mask = x1_tlOtherMastersNodeIn_8_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_data = x1_tlOtherMastersNodeIn_8_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_a_bits_corrupt = x1_tlOtherMastersNodeIn_8_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_8_d_ready = x1_tlOtherMastersNodeIn_8_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_valid = x1_tlOtherMastersNodeIn_9_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_opcode = x1_tlOtherMastersNodeIn_9_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_param = x1_tlOtherMastersNodeIn_9_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_size = x1_tlOtherMastersNodeIn_9_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_source = x1_tlOtherMastersNodeIn_9_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_address = x1_tlOtherMastersNodeIn_9_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_mask = x1_tlOtherMastersNodeIn_9_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_data = x1_tlOtherMastersNodeIn_9_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_a_bits_corrupt = x1_tlOtherMastersNodeIn_9_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_9_d_ready = x1_tlOtherMastersNodeIn_9_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_valid = x1_tlOtherMastersNodeIn_10_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_opcode = x1_tlOtherMastersNodeIn_10_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_param = x1_tlOtherMastersNodeIn_10_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_size = x1_tlOtherMastersNodeIn_10_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_source = x1_tlOtherMastersNodeIn_10_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_address = x1_tlOtherMastersNodeIn_10_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_mask = x1_tlOtherMastersNodeIn_10_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_data = x1_tlOtherMastersNodeIn_10_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_a_bits_corrupt = x1_tlOtherMastersNodeIn_10_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_10_d_ready = x1_tlOtherMastersNodeIn_10_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_valid = x1_tlOtherMastersNodeIn_11_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_opcode = x1_tlOtherMastersNodeIn_11_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_param = x1_tlOtherMastersNodeIn_11_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_size = x1_tlOtherMastersNodeIn_11_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_source = x1_tlOtherMastersNodeIn_11_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_address = x1_tlOtherMastersNodeIn_11_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_mask = x1_tlOtherMastersNodeIn_11_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_data = x1_tlOtherMastersNodeIn_11_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_a_bits_corrupt = x1_tlOtherMastersNodeIn_11_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_11_d_ready = x1_tlOtherMastersNodeIn_11_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_valid = x1_tlOtherMastersNodeIn_12_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_opcode = x1_tlOtherMastersNodeIn_12_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_param = x1_tlOtherMastersNodeIn_12_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_size = x1_tlOtherMastersNodeIn_12_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_source = x1_tlOtherMastersNodeIn_12_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_address = x1_tlOtherMastersNodeIn_12_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_mask = x1_tlOtherMastersNodeIn_12_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_data = x1_tlOtherMastersNodeIn_12_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_a_bits_corrupt = x1_tlOtherMastersNodeIn_12_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_12_d_ready = x1_tlOtherMastersNodeIn_12_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_valid = x1_tlOtherMastersNodeIn_13_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_opcode = x1_tlOtherMastersNodeIn_13_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_param = x1_tlOtherMastersNodeIn_13_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_size = x1_tlOtherMastersNodeIn_13_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_source = x1_tlOtherMastersNodeIn_13_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_address = x1_tlOtherMastersNodeIn_13_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_mask = x1_tlOtherMastersNodeIn_13_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_data = x1_tlOtherMastersNodeIn_13_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_a_bits_corrupt = x1_tlOtherMastersNodeIn_13_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_13_d_ready = x1_tlOtherMastersNodeIn_13_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_valid = x1_tlOtherMastersNodeIn_14_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_opcode = x1_tlOtherMastersNodeIn_14_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_param = x1_tlOtherMastersNodeIn_14_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_size = x1_tlOtherMastersNodeIn_14_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_source = x1_tlOtherMastersNodeIn_14_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_address = x1_tlOtherMastersNodeIn_14_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_mask = x1_tlOtherMastersNodeIn_14_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_data = x1_tlOtherMastersNodeIn_14_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_a_bits_corrupt = x1_tlOtherMastersNodeIn_14_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_14_d_ready = x1_tlOtherMastersNodeIn_14_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_valid = x1_tlOtherMastersNodeIn_15_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_opcode = x1_tlOtherMastersNodeIn_15_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_param = x1_tlOtherMastersNodeIn_15_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_size = x1_tlOtherMastersNodeIn_15_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_source = x1_tlOtherMastersNodeIn_15_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_address = x1_tlOtherMastersNodeIn_15_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_mask = x1_tlOtherMastersNodeIn_15_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_data = x1_tlOtherMastersNodeIn_15_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_a_bits_corrupt = x1_tlOtherMastersNodeIn_15_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_15_d_ready = x1_tlOtherMastersNodeIn_15_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_valid = x1_tlOtherMastersNodeIn_16_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_opcode = x1_tlOtherMastersNodeIn_16_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_param = x1_tlOtherMastersNodeIn_16_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_size = x1_tlOtherMastersNodeIn_16_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_source = x1_tlOtherMastersNodeIn_16_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_address = x1_tlOtherMastersNodeIn_16_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_mask = x1_tlOtherMastersNodeIn_16_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_data = x1_tlOtherMastersNodeIn_16_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_a_bits_corrupt = x1_tlOtherMastersNodeIn_16_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_16_d_ready = x1_tlOtherMastersNodeIn_16_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_valid = x1_tlOtherMastersNodeIn_17_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_opcode = x1_tlOtherMastersNodeIn_17_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_param = x1_tlOtherMastersNodeIn_17_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_size = x1_tlOtherMastersNodeIn_17_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_source = x1_tlOtherMastersNodeIn_17_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_address = x1_tlOtherMastersNodeIn_17_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_mask = x1_tlOtherMastersNodeIn_17_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_a_bits_data = x1_tlOtherMastersNodeIn_17_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_b_ready = x1_tlOtherMastersNodeIn_17_b_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_valid = x1_tlOtherMastersNodeIn_17_c_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_opcode = x1_tlOtherMastersNodeIn_17_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_param = x1_tlOtherMastersNodeIn_17_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_size = x1_tlOtherMastersNodeIn_17_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_source = x1_tlOtherMastersNodeIn_17_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_address = x1_tlOtherMastersNodeIn_17_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_c_bits_data = x1_tlOtherMastersNodeIn_17_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_d_ready = x1_tlOtherMastersNodeIn_17_d_ready; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_e_valid = x1_tlOtherMastersNodeIn_17_e_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_tlOtherMastersNodeOut_17_e_bits_sink = x1_tlOtherMastersNodeIn_17_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17] assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17] assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7] assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17] assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17] wire int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_1; // @[MixedNode.scala:542:17] wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17] wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17] assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17] wire intSinkNodeIn_0; // @[MixedNode.scala:551:17] wire intSinkNodeIn_1; // @[MixedNode.scala:551:17] wire intSinkNodeIn_2; // @[MixedNode.scala:551:17] wire intSinkNodeIn_3; // @[MixedNode.scala:551:17] wire intSinkNodeIn_4; // @[MixedNode.scala:551:17] assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7] reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36] always @(posedge clock) begin // @[RocketTile.scala:141:7] if (reset) // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36] else // @[RocketTile.scala:141:7] wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20] always @(posedge) TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42] .clock (clock), .reset (reset), .auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready), .auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid), .auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param), .auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size), .auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied), .auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready), .auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9] .auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid), .auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode), .auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param), .auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size), .auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source), .auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address), .auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask), .auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data), .auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt), .auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready), .auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9] .auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9] .auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid), .auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param), .auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size), .auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source), .auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied), .auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt), .auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready), .auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9] .auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9] .auto_anon_out_a_ready (x1_tlOtherMastersNodeIn_17_a_ready), // @[MixedNode.scala:551:17] .auto_anon_out_a_valid (x1_tlOtherMastersNodeIn_17_a_valid), .auto_anon_out_a_bits_opcode (x1_tlOtherMastersNodeIn_17_a_bits_opcode), .auto_anon_out_a_bits_param (x1_tlOtherMastersNodeIn_17_a_bits_param), .auto_anon_out_a_bits_size (x1_tlOtherMastersNodeIn_17_a_bits_size), .auto_anon_out_a_bits_source (x1_tlOtherMastersNodeIn_17_a_bits_source), .auto_anon_out_a_bits_address (x1_tlOtherMastersNodeIn_17_a_bits_address), .auto_anon_out_a_bits_mask (x1_tlOtherMastersNodeIn_17_a_bits_mask), .auto_anon_out_a_bits_data (x1_tlOtherMastersNodeIn_17_a_bits_data), .auto_anon_out_b_ready (x1_tlOtherMastersNodeIn_17_b_ready), .auto_anon_out_b_valid (x1_tlOtherMastersNodeIn_17_b_valid), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_opcode (x1_tlOtherMastersNodeIn_17_b_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_param (x1_tlOtherMastersNodeIn_17_b_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_size (x1_tlOtherMastersNodeIn_17_b_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_source (x1_tlOtherMastersNodeIn_17_b_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_address (x1_tlOtherMastersNodeIn_17_b_bits_address), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_mask (x1_tlOtherMastersNodeIn_17_b_bits_mask), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_data (x1_tlOtherMastersNodeIn_17_b_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_b_bits_corrupt (x1_tlOtherMastersNodeIn_17_b_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_c_ready (x1_tlOtherMastersNodeIn_17_c_ready), // @[MixedNode.scala:551:17] .auto_anon_out_c_valid (x1_tlOtherMastersNodeIn_17_c_valid), .auto_anon_out_c_bits_opcode (x1_tlOtherMastersNodeIn_17_c_bits_opcode), .auto_anon_out_c_bits_param (x1_tlOtherMastersNodeIn_17_c_bits_param), .auto_anon_out_c_bits_size (x1_tlOtherMastersNodeIn_17_c_bits_size), .auto_anon_out_c_bits_source (x1_tlOtherMastersNodeIn_17_c_bits_source), .auto_anon_out_c_bits_address (x1_tlOtherMastersNodeIn_17_c_bits_address), .auto_anon_out_c_bits_data (x1_tlOtherMastersNodeIn_17_c_bits_data), .auto_anon_out_d_ready (x1_tlOtherMastersNodeIn_17_d_ready), .auto_anon_out_d_valid (x1_tlOtherMastersNodeIn_17_d_valid), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_opcode (x1_tlOtherMastersNodeIn_17_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_param (x1_tlOtherMastersNodeIn_17_d_bits_param), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_size (x1_tlOtherMastersNodeIn_17_d_bits_size), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_source (x1_tlOtherMastersNodeIn_17_d_bits_source), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_sink (x1_tlOtherMastersNodeIn_17_d_bits_sink), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_denied (x1_tlOtherMastersNodeIn_17_d_bits_denied), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_data (x1_tlOtherMastersNodeIn_17_d_bits_data), // @[MixedNode.scala:551:17] .auto_anon_out_d_bits_corrupt (x1_tlOtherMastersNodeIn_17_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_anon_out_e_ready (x1_tlOtherMastersNodeIn_17_e_ready), // @[MixedNode.scala:551:17] .auto_anon_out_e_valid (x1_tlOtherMastersNodeIn_17_e_valid), .auto_anon_out_e_bits_sink (x1_tlOtherMastersNodeIn_17_e_bits_sink) ); // @[HierarchicalElement.scala:55:42] TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41] .clock (clock), .reset (reset) ); // @[HierarchicalElement.scala:56:41] IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37] .auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17] .auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17] .auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17] .auto_anon_out_0 (intSinkNodeIn_0), .auto_anon_out_1 (intSinkNodeIn_1), .auto_anon_out_2 (intSinkNodeIn_2), .auto_anon_out_3 (intSinkNodeIn_3), .auto_anon_out_4 (intSinkNodeIn_4) ); // @[HierarchicalElement.scala:57:37] DCache dcache ( // @[HellaCache.scala:278:43] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25] .io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25] .io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25] .io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25] .io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25] .io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[HellaCache.scala:292:25] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25] .io_ptw_req_ready (_ptw_io_requestor_18_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_18_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_18_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_18_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_18_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_18_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_18_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_18_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_18_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_18_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_18_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_18_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_18_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_18_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_18_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_18_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_18_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_18_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_18_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_18_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_18_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_18_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_18_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_18_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_18_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_18_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_18_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_18_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_18_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_18_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_18_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_18_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_18_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_18_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_18_status_v), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_18_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_18_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_18_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_18_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_18_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_18_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_18_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_18_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_18_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_18_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_18_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_18_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_18_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_18_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_18_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_18_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_18_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_18_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_18_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_18_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_18_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_18_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_18_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_18_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_18_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_18_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_18_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_18_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_18_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_18_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_18_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_18_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_18_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_18_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_18_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_18_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_18_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_18_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_18_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_18_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_18_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_18_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_18_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_18_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_18_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_18_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_18_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_18_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_18_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_18_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_18_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_18_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_18_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_18_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_18_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_18_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_18_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_18_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_18_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_18_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_18_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_18_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_18_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_18_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_18_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_18_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_18_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_18_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_18_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_18_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_18_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_18_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_18_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_18_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_18_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_18_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_18_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_18_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_18_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_18_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_18_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_18_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_18_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_18_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_18_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_18_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_18_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_18_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_18_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_18_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_18_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_18_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_18_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_18_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_18_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_18_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_18_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_18_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_18_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_18_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_18_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_18_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_18_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_18_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_18_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_18_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_18_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_18_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_18_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_18_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_18_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_18_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_18_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_18_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_18_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_18_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_18_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_18_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_18_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_18_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_18_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_18_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_18_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[HellaCache.scala:278:43] ZstdCompressor zstd_compressor ( // @[Configs.scala:62:39] .clock (clock), .reset (reset), .auto_tl_out_17_a_ready (x1_tlOtherMastersNodeIn_16_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_17_a_valid (x1_tlOtherMastersNodeIn_16_a_valid), .auto_tl_out_17_a_bits_opcode (x1_tlOtherMastersNodeIn_16_a_bits_opcode), .auto_tl_out_17_a_bits_param (x1_tlOtherMastersNodeIn_16_a_bits_param), .auto_tl_out_17_a_bits_size (x1_tlOtherMastersNodeIn_16_a_bits_size), .auto_tl_out_17_a_bits_source (x1_tlOtherMastersNodeIn_16_a_bits_source), .auto_tl_out_17_a_bits_address (x1_tlOtherMastersNodeIn_16_a_bits_address), .auto_tl_out_17_a_bits_mask (x1_tlOtherMastersNodeIn_16_a_bits_mask), .auto_tl_out_17_a_bits_data (x1_tlOtherMastersNodeIn_16_a_bits_data), .auto_tl_out_17_a_bits_corrupt (x1_tlOtherMastersNodeIn_16_a_bits_corrupt), .auto_tl_out_17_d_ready (x1_tlOtherMastersNodeIn_16_d_ready), .auto_tl_out_17_d_valid (x1_tlOtherMastersNodeIn_16_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_opcode (x1_tlOtherMastersNodeIn_16_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_param (x1_tlOtherMastersNodeIn_16_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_size (x1_tlOtherMastersNodeIn_16_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_source (x1_tlOtherMastersNodeIn_16_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_sink (x1_tlOtherMastersNodeIn_16_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_denied (x1_tlOtherMastersNodeIn_16_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_data (x1_tlOtherMastersNodeIn_16_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_17_d_bits_corrupt (x1_tlOtherMastersNodeIn_16_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_16_a_ready (x1_tlOtherMastersNodeIn_15_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_16_a_valid (x1_tlOtherMastersNodeIn_15_a_valid), .auto_tl_out_16_a_bits_opcode (x1_tlOtherMastersNodeIn_15_a_bits_opcode), .auto_tl_out_16_a_bits_param (x1_tlOtherMastersNodeIn_15_a_bits_param), .auto_tl_out_16_a_bits_size (x1_tlOtherMastersNodeIn_15_a_bits_size), .auto_tl_out_16_a_bits_source (x1_tlOtherMastersNodeIn_15_a_bits_source), .auto_tl_out_16_a_bits_address (x1_tlOtherMastersNodeIn_15_a_bits_address), .auto_tl_out_16_a_bits_mask (x1_tlOtherMastersNodeIn_15_a_bits_mask), .auto_tl_out_16_a_bits_data (x1_tlOtherMastersNodeIn_15_a_bits_data), .auto_tl_out_16_a_bits_corrupt (x1_tlOtherMastersNodeIn_15_a_bits_corrupt), .auto_tl_out_16_d_ready (x1_tlOtherMastersNodeIn_15_d_ready), .auto_tl_out_16_d_valid (x1_tlOtherMastersNodeIn_15_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_opcode (x1_tlOtherMastersNodeIn_15_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_param (x1_tlOtherMastersNodeIn_15_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_size (x1_tlOtherMastersNodeIn_15_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_source (x1_tlOtherMastersNodeIn_15_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_sink (x1_tlOtherMastersNodeIn_15_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_denied (x1_tlOtherMastersNodeIn_15_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_data (x1_tlOtherMastersNodeIn_15_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_16_d_bits_corrupt (x1_tlOtherMastersNodeIn_15_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_15_a_ready (x1_tlOtherMastersNodeIn_14_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_15_a_valid (x1_tlOtherMastersNodeIn_14_a_valid), .auto_tl_out_15_a_bits_opcode (x1_tlOtherMastersNodeIn_14_a_bits_opcode), .auto_tl_out_15_a_bits_param (x1_tlOtherMastersNodeIn_14_a_bits_param), .auto_tl_out_15_a_bits_size (x1_tlOtherMastersNodeIn_14_a_bits_size), .auto_tl_out_15_a_bits_source (x1_tlOtherMastersNodeIn_14_a_bits_source), .auto_tl_out_15_a_bits_address (x1_tlOtherMastersNodeIn_14_a_bits_address), .auto_tl_out_15_a_bits_mask (x1_tlOtherMastersNodeIn_14_a_bits_mask), .auto_tl_out_15_a_bits_data (x1_tlOtherMastersNodeIn_14_a_bits_data), .auto_tl_out_15_a_bits_corrupt (x1_tlOtherMastersNodeIn_14_a_bits_corrupt), .auto_tl_out_15_d_ready (x1_tlOtherMastersNodeIn_14_d_ready), .auto_tl_out_15_d_valid (x1_tlOtherMastersNodeIn_14_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_opcode (x1_tlOtherMastersNodeIn_14_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_param (x1_tlOtherMastersNodeIn_14_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_size (x1_tlOtherMastersNodeIn_14_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_source (x1_tlOtherMastersNodeIn_14_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_sink (x1_tlOtherMastersNodeIn_14_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_denied (x1_tlOtherMastersNodeIn_14_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_data (x1_tlOtherMastersNodeIn_14_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_15_d_bits_corrupt (x1_tlOtherMastersNodeIn_14_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_14_a_ready (x1_tlOtherMastersNodeIn_13_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_14_a_valid (x1_tlOtherMastersNodeIn_13_a_valid), .auto_tl_out_14_a_bits_opcode (x1_tlOtherMastersNodeIn_13_a_bits_opcode), .auto_tl_out_14_a_bits_param (x1_tlOtherMastersNodeIn_13_a_bits_param), .auto_tl_out_14_a_bits_size (x1_tlOtherMastersNodeIn_13_a_bits_size), .auto_tl_out_14_a_bits_source (x1_tlOtherMastersNodeIn_13_a_bits_source), .auto_tl_out_14_a_bits_address (x1_tlOtherMastersNodeIn_13_a_bits_address), .auto_tl_out_14_a_bits_mask (x1_tlOtherMastersNodeIn_13_a_bits_mask), .auto_tl_out_14_a_bits_data (x1_tlOtherMastersNodeIn_13_a_bits_data), .auto_tl_out_14_a_bits_corrupt (x1_tlOtherMastersNodeIn_13_a_bits_corrupt), .auto_tl_out_14_d_ready (x1_tlOtherMastersNodeIn_13_d_ready), .auto_tl_out_14_d_valid (x1_tlOtherMastersNodeIn_13_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_opcode (x1_tlOtherMastersNodeIn_13_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_param (x1_tlOtherMastersNodeIn_13_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_size (x1_tlOtherMastersNodeIn_13_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_source (x1_tlOtherMastersNodeIn_13_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_sink (x1_tlOtherMastersNodeIn_13_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_denied (x1_tlOtherMastersNodeIn_13_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_data (x1_tlOtherMastersNodeIn_13_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_14_d_bits_corrupt (x1_tlOtherMastersNodeIn_13_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_13_a_ready (x1_tlOtherMastersNodeIn_12_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_13_a_valid (x1_tlOtherMastersNodeIn_12_a_valid), .auto_tl_out_13_a_bits_opcode (x1_tlOtherMastersNodeIn_12_a_bits_opcode), .auto_tl_out_13_a_bits_param (x1_tlOtherMastersNodeIn_12_a_bits_param), .auto_tl_out_13_a_bits_size (x1_tlOtherMastersNodeIn_12_a_bits_size), .auto_tl_out_13_a_bits_source (x1_tlOtherMastersNodeIn_12_a_bits_source), .auto_tl_out_13_a_bits_address (x1_tlOtherMastersNodeIn_12_a_bits_address), .auto_tl_out_13_a_bits_mask (x1_tlOtherMastersNodeIn_12_a_bits_mask), .auto_tl_out_13_a_bits_data (x1_tlOtherMastersNodeIn_12_a_bits_data), .auto_tl_out_13_a_bits_corrupt (x1_tlOtherMastersNodeIn_12_a_bits_corrupt), .auto_tl_out_13_d_ready (x1_tlOtherMastersNodeIn_12_d_ready), .auto_tl_out_13_d_valid (x1_tlOtherMastersNodeIn_12_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_opcode (x1_tlOtherMastersNodeIn_12_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_param (x1_tlOtherMastersNodeIn_12_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_size (x1_tlOtherMastersNodeIn_12_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_source (x1_tlOtherMastersNodeIn_12_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_sink (x1_tlOtherMastersNodeIn_12_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_denied (x1_tlOtherMastersNodeIn_12_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_data (x1_tlOtherMastersNodeIn_12_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_13_d_bits_corrupt (x1_tlOtherMastersNodeIn_12_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_12_a_ready (x1_tlOtherMastersNodeIn_11_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_12_a_valid (x1_tlOtherMastersNodeIn_11_a_valid), .auto_tl_out_12_a_bits_opcode (x1_tlOtherMastersNodeIn_11_a_bits_opcode), .auto_tl_out_12_a_bits_param (x1_tlOtherMastersNodeIn_11_a_bits_param), .auto_tl_out_12_a_bits_size (x1_tlOtherMastersNodeIn_11_a_bits_size), .auto_tl_out_12_a_bits_source (x1_tlOtherMastersNodeIn_11_a_bits_source), .auto_tl_out_12_a_bits_address (x1_tlOtherMastersNodeIn_11_a_bits_address), .auto_tl_out_12_a_bits_mask (x1_tlOtherMastersNodeIn_11_a_bits_mask), .auto_tl_out_12_a_bits_data (x1_tlOtherMastersNodeIn_11_a_bits_data), .auto_tl_out_12_a_bits_corrupt (x1_tlOtherMastersNodeIn_11_a_bits_corrupt), .auto_tl_out_12_d_ready (x1_tlOtherMastersNodeIn_11_d_ready), .auto_tl_out_12_d_valid (x1_tlOtherMastersNodeIn_11_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_opcode (x1_tlOtherMastersNodeIn_11_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_param (x1_tlOtherMastersNodeIn_11_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_size (x1_tlOtherMastersNodeIn_11_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_source (x1_tlOtherMastersNodeIn_11_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_sink (x1_tlOtherMastersNodeIn_11_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_denied (x1_tlOtherMastersNodeIn_11_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_data (x1_tlOtherMastersNodeIn_11_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_12_d_bits_corrupt (x1_tlOtherMastersNodeIn_11_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_11_a_ready (x1_tlOtherMastersNodeIn_10_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_11_a_valid (x1_tlOtherMastersNodeIn_10_a_valid), .auto_tl_out_11_a_bits_opcode (x1_tlOtherMastersNodeIn_10_a_bits_opcode), .auto_tl_out_11_a_bits_param (x1_tlOtherMastersNodeIn_10_a_bits_param), .auto_tl_out_11_a_bits_size (x1_tlOtherMastersNodeIn_10_a_bits_size), .auto_tl_out_11_a_bits_source (x1_tlOtherMastersNodeIn_10_a_bits_source), .auto_tl_out_11_a_bits_address (x1_tlOtherMastersNodeIn_10_a_bits_address), .auto_tl_out_11_a_bits_mask (x1_tlOtherMastersNodeIn_10_a_bits_mask), .auto_tl_out_11_a_bits_data (x1_tlOtherMastersNodeIn_10_a_bits_data), .auto_tl_out_11_a_bits_corrupt (x1_tlOtherMastersNodeIn_10_a_bits_corrupt), .auto_tl_out_11_d_ready (x1_tlOtherMastersNodeIn_10_d_ready), .auto_tl_out_11_d_valid (x1_tlOtherMastersNodeIn_10_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_opcode (x1_tlOtherMastersNodeIn_10_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_param (x1_tlOtherMastersNodeIn_10_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_size (x1_tlOtherMastersNodeIn_10_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_source (x1_tlOtherMastersNodeIn_10_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_sink (x1_tlOtherMastersNodeIn_10_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_denied (x1_tlOtherMastersNodeIn_10_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_data (x1_tlOtherMastersNodeIn_10_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_11_d_bits_corrupt (x1_tlOtherMastersNodeIn_10_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_10_a_ready (x1_tlOtherMastersNodeIn_9_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_10_a_valid (x1_tlOtherMastersNodeIn_9_a_valid), .auto_tl_out_10_a_bits_opcode (x1_tlOtherMastersNodeIn_9_a_bits_opcode), .auto_tl_out_10_a_bits_param (x1_tlOtherMastersNodeIn_9_a_bits_param), .auto_tl_out_10_a_bits_size (x1_tlOtherMastersNodeIn_9_a_bits_size), .auto_tl_out_10_a_bits_source (x1_tlOtherMastersNodeIn_9_a_bits_source), .auto_tl_out_10_a_bits_address (x1_tlOtherMastersNodeIn_9_a_bits_address), .auto_tl_out_10_a_bits_mask (x1_tlOtherMastersNodeIn_9_a_bits_mask), .auto_tl_out_10_a_bits_data (x1_tlOtherMastersNodeIn_9_a_bits_data), .auto_tl_out_10_a_bits_corrupt (x1_tlOtherMastersNodeIn_9_a_bits_corrupt), .auto_tl_out_10_d_ready (x1_tlOtherMastersNodeIn_9_d_ready), .auto_tl_out_10_d_valid (x1_tlOtherMastersNodeIn_9_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_opcode (x1_tlOtherMastersNodeIn_9_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_param (x1_tlOtherMastersNodeIn_9_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_size (x1_tlOtherMastersNodeIn_9_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_source (x1_tlOtherMastersNodeIn_9_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_sink (x1_tlOtherMastersNodeIn_9_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_denied (x1_tlOtherMastersNodeIn_9_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_data (x1_tlOtherMastersNodeIn_9_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_10_d_bits_corrupt (x1_tlOtherMastersNodeIn_9_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_9_a_ready (x1_tlOtherMastersNodeIn_8_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_9_a_valid (x1_tlOtherMastersNodeIn_8_a_valid), .auto_tl_out_9_a_bits_opcode (x1_tlOtherMastersNodeIn_8_a_bits_opcode), .auto_tl_out_9_a_bits_param (x1_tlOtherMastersNodeIn_8_a_bits_param), .auto_tl_out_9_a_bits_size (x1_tlOtherMastersNodeIn_8_a_bits_size), .auto_tl_out_9_a_bits_source (x1_tlOtherMastersNodeIn_8_a_bits_source), .auto_tl_out_9_a_bits_address (x1_tlOtherMastersNodeIn_8_a_bits_address), .auto_tl_out_9_a_bits_mask (x1_tlOtherMastersNodeIn_8_a_bits_mask), .auto_tl_out_9_a_bits_data (x1_tlOtherMastersNodeIn_8_a_bits_data), .auto_tl_out_9_a_bits_corrupt (x1_tlOtherMastersNodeIn_8_a_bits_corrupt), .auto_tl_out_9_d_ready (x1_tlOtherMastersNodeIn_8_d_ready), .auto_tl_out_9_d_valid (x1_tlOtherMastersNodeIn_8_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_opcode (x1_tlOtherMastersNodeIn_8_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_param (x1_tlOtherMastersNodeIn_8_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_size (x1_tlOtherMastersNodeIn_8_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_source (x1_tlOtherMastersNodeIn_8_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_sink (x1_tlOtherMastersNodeIn_8_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_denied (x1_tlOtherMastersNodeIn_8_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_data (x1_tlOtherMastersNodeIn_8_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_9_d_bits_corrupt (x1_tlOtherMastersNodeIn_8_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_8_a_ready (x1_tlOtherMastersNodeIn_7_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_8_a_valid (x1_tlOtherMastersNodeIn_7_a_valid), .auto_tl_out_8_a_bits_opcode (x1_tlOtherMastersNodeIn_7_a_bits_opcode), .auto_tl_out_8_a_bits_param (x1_tlOtherMastersNodeIn_7_a_bits_param), .auto_tl_out_8_a_bits_size (x1_tlOtherMastersNodeIn_7_a_bits_size), .auto_tl_out_8_a_bits_source (x1_tlOtherMastersNodeIn_7_a_bits_source), .auto_tl_out_8_a_bits_address (x1_tlOtherMastersNodeIn_7_a_bits_address), .auto_tl_out_8_a_bits_mask (x1_tlOtherMastersNodeIn_7_a_bits_mask), .auto_tl_out_8_a_bits_data (x1_tlOtherMastersNodeIn_7_a_bits_data), .auto_tl_out_8_a_bits_corrupt (x1_tlOtherMastersNodeIn_7_a_bits_corrupt), .auto_tl_out_8_d_ready (x1_tlOtherMastersNodeIn_7_d_ready), .auto_tl_out_8_d_valid (x1_tlOtherMastersNodeIn_7_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_opcode (x1_tlOtherMastersNodeIn_7_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_param (x1_tlOtherMastersNodeIn_7_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_size (x1_tlOtherMastersNodeIn_7_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_source (x1_tlOtherMastersNodeIn_7_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_sink (x1_tlOtherMastersNodeIn_7_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_denied (x1_tlOtherMastersNodeIn_7_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_data (x1_tlOtherMastersNodeIn_7_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_8_d_bits_corrupt (x1_tlOtherMastersNodeIn_7_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_7_a_ready (x1_tlOtherMastersNodeIn_6_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_7_a_valid (x1_tlOtherMastersNodeIn_6_a_valid), .auto_tl_out_7_a_bits_opcode (x1_tlOtherMastersNodeIn_6_a_bits_opcode), .auto_tl_out_7_a_bits_param (x1_tlOtherMastersNodeIn_6_a_bits_param), .auto_tl_out_7_a_bits_size (x1_tlOtherMastersNodeIn_6_a_bits_size), .auto_tl_out_7_a_bits_source (x1_tlOtherMastersNodeIn_6_a_bits_source), .auto_tl_out_7_a_bits_address (x1_tlOtherMastersNodeIn_6_a_bits_address), .auto_tl_out_7_a_bits_mask (x1_tlOtherMastersNodeIn_6_a_bits_mask), .auto_tl_out_7_a_bits_data (x1_tlOtherMastersNodeIn_6_a_bits_data), .auto_tl_out_7_a_bits_corrupt (x1_tlOtherMastersNodeIn_6_a_bits_corrupt), .auto_tl_out_7_d_ready (x1_tlOtherMastersNodeIn_6_d_ready), .auto_tl_out_7_d_valid (x1_tlOtherMastersNodeIn_6_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_opcode (x1_tlOtherMastersNodeIn_6_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_param (x1_tlOtherMastersNodeIn_6_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_size (x1_tlOtherMastersNodeIn_6_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_source (x1_tlOtherMastersNodeIn_6_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_sink (x1_tlOtherMastersNodeIn_6_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_denied (x1_tlOtherMastersNodeIn_6_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_data (x1_tlOtherMastersNodeIn_6_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_7_d_bits_corrupt (x1_tlOtherMastersNodeIn_6_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_6_a_ready (x1_tlOtherMastersNodeIn_5_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_6_a_valid (x1_tlOtherMastersNodeIn_5_a_valid), .auto_tl_out_6_a_bits_opcode (x1_tlOtherMastersNodeIn_5_a_bits_opcode), .auto_tl_out_6_a_bits_param (x1_tlOtherMastersNodeIn_5_a_bits_param), .auto_tl_out_6_a_bits_size (x1_tlOtherMastersNodeIn_5_a_bits_size), .auto_tl_out_6_a_bits_source (x1_tlOtherMastersNodeIn_5_a_bits_source), .auto_tl_out_6_a_bits_address (x1_tlOtherMastersNodeIn_5_a_bits_address), .auto_tl_out_6_a_bits_mask (x1_tlOtherMastersNodeIn_5_a_bits_mask), .auto_tl_out_6_a_bits_data (x1_tlOtherMastersNodeIn_5_a_bits_data), .auto_tl_out_6_a_bits_corrupt (x1_tlOtherMastersNodeIn_5_a_bits_corrupt), .auto_tl_out_6_d_ready (x1_tlOtherMastersNodeIn_5_d_ready), .auto_tl_out_6_d_valid (x1_tlOtherMastersNodeIn_5_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_opcode (x1_tlOtherMastersNodeIn_5_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_param (x1_tlOtherMastersNodeIn_5_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_size (x1_tlOtherMastersNodeIn_5_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_source (x1_tlOtherMastersNodeIn_5_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_sink (x1_tlOtherMastersNodeIn_5_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_denied (x1_tlOtherMastersNodeIn_5_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_data (x1_tlOtherMastersNodeIn_5_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_6_d_bits_corrupt (x1_tlOtherMastersNodeIn_5_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_5_a_ready (x1_tlOtherMastersNodeIn_4_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_5_a_valid (x1_tlOtherMastersNodeIn_4_a_valid), .auto_tl_out_5_a_bits_opcode (x1_tlOtherMastersNodeIn_4_a_bits_opcode), .auto_tl_out_5_a_bits_param (x1_tlOtherMastersNodeIn_4_a_bits_param), .auto_tl_out_5_a_bits_size (x1_tlOtherMastersNodeIn_4_a_bits_size), .auto_tl_out_5_a_bits_source (x1_tlOtherMastersNodeIn_4_a_bits_source), .auto_tl_out_5_a_bits_address (x1_tlOtherMastersNodeIn_4_a_bits_address), .auto_tl_out_5_a_bits_mask (x1_tlOtherMastersNodeIn_4_a_bits_mask), .auto_tl_out_5_a_bits_data (x1_tlOtherMastersNodeIn_4_a_bits_data), .auto_tl_out_5_a_bits_corrupt (x1_tlOtherMastersNodeIn_4_a_bits_corrupt), .auto_tl_out_5_d_ready (x1_tlOtherMastersNodeIn_4_d_ready), .auto_tl_out_5_d_valid (x1_tlOtherMastersNodeIn_4_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_opcode (x1_tlOtherMastersNodeIn_4_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_param (x1_tlOtherMastersNodeIn_4_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_size (x1_tlOtherMastersNodeIn_4_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_source (x1_tlOtherMastersNodeIn_4_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_sink (x1_tlOtherMastersNodeIn_4_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_denied (x1_tlOtherMastersNodeIn_4_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_data (x1_tlOtherMastersNodeIn_4_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_5_d_bits_corrupt (x1_tlOtherMastersNodeIn_4_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_4_a_ready (x1_tlOtherMastersNodeIn_3_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_4_a_valid (x1_tlOtherMastersNodeIn_3_a_valid), .auto_tl_out_4_a_bits_opcode (x1_tlOtherMastersNodeIn_3_a_bits_opcode), .auto_tl_out_4_a_bits_param (x1_tlOtherMastersNodeIn_3_a_bits_param), .auto_tl_out_4_a_bits_size (x1_tlOtherMastersNodeIn_3_a_bits_size), .auto_tl_out_4_a_bits_source (x1_tlOtherMastersNodeIn_3_a_bits_source), .auto_tl_out_4_a_bits_address (x1_tlOtherMastersNodeIn_3_a_bits_address), .auto_tl_out_4_a_bits_mask (x1_tlOtherMastersNodeIn_3_a_bits_mask), .auto_tl_out_4_a_bits_data (x1_tlOtherMastersNodeIn_3_a_bits_data), .auto_tl_out_4_a_bits_corrupt (x1_tlOtherMastersNodeIn_3_a_bits_corrupt), .auto_tl_out_4_d_ready (x1_tlOtherMastersNodeIn_3_d_ready), .auto_tl_out_4_d_valid (x1_tlOtherMastersNodeIn_3_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_opcode (x1_tlOtherMastersNodeIn_3_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_param (x1_tlOtherMastersNodeIn_3_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_size (x1_tlOtherMastersNodeIn_3_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_source (x1_tlOtherMastersNodeIn_3_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_sink (x1_tlOtherMastersNodeIn_3_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_denied (x1_tlOtherMastersNodeIn_3_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_data (x1_tlOtherMastersNodeIn_3_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_4_d_bits_corrupt (x1_tlOtherMastersNodeIn_3_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_3_a_ready (x1_tlOtherMastersNodeIn_2_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_3_a_valid (x1_tlOtherMastersNodeIn_2_a_valid), .auto_tl_out_3_a_bits_opcode (x1_tlOtherMastersNodeIn_2_a_bits_opcode), .auto_tl_out_3_a_bits_param (x1_tlOtherMastersNodeIn_2_a_bits_param), .auto_tl_out_3_a_bits_size (x1_tlOtherMastersNodeIn_2_a_bits_size), .auto_tl_out_3_a_bits_source (x1_tlOtherMastersNodeIn_2_a_bits_source), .auto_tl_out_3_a_bits_address (x1_tlOtherMastersNodeIn_2_a_bits_address), .auto_tl_out_3_a_bits_mask (x1_tlOtherMastersNodeIn_2_a_bits_mask), .auto_tl_out_3_a_bits_data (x1_tlOtherMastersNodeIn_2_a_bits_data), .auto_tl_out_3_a_bits_corrupt (x1_tlOtherMastersNodeIn_2_a_bits_corrupt), .auto_tl_out_3_d_ready (x1_tlOtherMastersNodeIn_2_d_ready), .auto_tl_out_3_d_valid (x1_tlOtherMastersNodeIn_2_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_opcode (x1_tlOtherMastersNodeIn_2_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_param (x1_tlOtherMastersNodeIn_2_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_size (x1_tlOtherMastersNodeIn_2_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_source (x1_tlOtherMastersNodeIn_2_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_sink (x1_tlOtherMastersNodeIn_2_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_denied (x1_tlOtherMastersNodeIn_2_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_data (x1_tlOtherMastersNodeIn_2_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_3_d_bits_corrupt (x1_tlOtherMastersNodeIn_2_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_2_a_ready (x1_tlOtherMastersNodeIn_1_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_2_a_valid (x1_tlOtherMastersNodeIn_1_a_valid), .auto_tl_out_2_a_bits_opcode (x1_tlOtherMastersNodeIn_1_a_bits_opcode), .auto_tl_out_2_a_bits_param (x1_tlOtherMastersNodeIn_1_a_bits_param), .auto_tl_out_2_a_bits_size (x1_tlOtherMastersNodeIn_1_a_bits_size), .auto_tl_out_2_a_bits_source (x1_tlOtherMastersNodeIn_1_a_bits_source), .auto_tl_out_2_a_bits_address (x1_tlOtherMastersNodeIn_1_a_bits_address), .auto_tl_out_2_a_bits_mask (x1_tlOtherMastersNodeIn_1_a_bits_mask), .auto_tl_out_2_a_bits_data (x1_tlOtherMastersNodeIn_1_a_bits_data), .auto_tl_out_2_a_bits_corrupt (x1_tlOtherMastersNodeIn_1_a_bits_corrupt), .auto_tl_out_2_d_ready (x1_tlOtherMastersNodeIn_1_d_ready), .auto_tl_out_2_d_valid (x1_tlOtherMastersNodeIn_1_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_opcode (x1_tlOtherMastersNodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_param (x1_tlOtherMastersNodeIn_1_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_size (x1_tlOtherMastersNodeIn_1_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_source (x1_tlOtherMastersNodeIn_1_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_sink (x1_tlOtherMastersNodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_denied (x1_tlOtherMastersNodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_data (x1_tlOtherMastersNodeIn_1_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_2_d_bits_corrupt (x1_tlOtherMastersNodeIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_1_a_ready (x1_tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_1_a_valid (x1_tlOtherMastersNodeIn_a_valid), .auto_tl_out_1_a_bits_opcode (x1_tlOtherMastersNodeIn_a_bits_opcode), .auto_tl_out_1_a_bits_param (x1_tlOtherMastersNodeIn_a_bits_param), .auto_tl_out_1_a_bits_size (x1_tlOtherMastersNodeIn_a_bits_size), .auto_tl_out_1_a_bits_source (x1_tlOtherMastersNodeIn_a_bits_source), .auto_tl_out_1_a_bits_address (x1_tlOtherMastersNodeIn_a_bits_address), .auto_tl_out_1_a_bits_mask (x1_tlOtherMastersNodeIn_a_bits_mask), .auto_tl_out_1_a_bits_data (x1_tlOtherMastersNodeIn_a_bits_data), .auto_tl_out_1_a_bits_corrupt (x1_tlOtherMastersNodeIn_a_bits_corrupt), .auto_tl_out_1_d_ready (x1_tlOtherMastersNodeIn_d_ready), .auto_tl_out_1_d_valid (x1_tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_opcode (x1_tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_param (x1_tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_size (x1_tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_source (x1_tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_sink (x1_tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_denied (x1_tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_data (x1_tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_1_d_bits_corrupt (x1_tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_tl_out_0_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17] .auto_tl_out_0_a_valid (tlOtherMastersNodeIn_a_valid), .auto_tl_out_0_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode), .auto_tl_out_0_a_bits_param (tlOtherMastersNodeIn_a_bits_param), .auto_tl_out_0_a_bits_size (tlOtherMastersNodeIn_a_bits_size), .auto_tl_out_0_a_bits_source (tlOtherMastersNodeIn_a_bits_source), .auto_tl_out_0_a_bits_address (tlOtherMastersNodeIn_a_bits_address), .auto_tl_out_0_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask), .auto_tl_out_0_a_bits_data (tlOtherMastersNodeIn_a_bits_data), .auto_tl_out_0_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt), .auto_tl_out_0_d_ready (tlOtherMastersNodeIn_d_ready), .auto_tl_out_0_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_tl_out_0_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_cmd_ready (_zstd_compressor_io_cmd_ready), .io_cmd_valid (_cmdRouter_io_out_0_valid), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode), // @[LazyRoCC.scala:102:27] .io_cmd_bits_rs1 (_cmdRouter_io_out_0_bits_rs1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_rs2 (_cmdRouter_io_out_0_bits_rs2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_v (_cmdRouter_io_out_0_bits_status_v), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie), // @[LazyRoCC.scala:102:27] .io_cmd_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie), // @[LazyRoCC.scala:102:27] .io_resp_ready (_respArb_io_in_0_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_resp_valid (_zstd_compressor_io_resp_valid), .io_resp_bits_rd (_zstd_compressor_io_resp_bits_rd), .io_resp_bits_data (_zstd_compressor_io_resp_bits_data), .io_mem_req_ready (_dcIF_io_requestor_req_ready), // @[LazyRoCC.scala:106:24] .io_mem_resp_valid (_dcIF_io_requestor_resp_valid), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_size (_dcIF_io_requestor_resp_bits_size), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data (_dcIF_io_requestor_resp_bits_data), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw), // @[LazyRoCC.scala:106:24] .io_mem_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data), // @[LazyRoCC.scala:106:24] .io_exception (_core_io_rocc_exception), // @[RocketTile.scala:147:20] .io_ptw_0_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19] .io_ptw_0_req_valid (_zstd_compressor_io_ptw_0_req_valid), .io_ptw_0_req_bits_bits_addr (_zstd_compressor_io_ptw_0_req_bits_bits_addr), .io_ptw_0_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_0_req_bits_bits_need_gpa), .io_ptw_0_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_0_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19] .io_ptw_0_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19] .io_ptw_0_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19] .io_ptw_0_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19] .io_ptw_0_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19] .io_ptw_0_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19] .io_ptw_0_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19] .io_ptw_0_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19] .io_ptw_0_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19] .io_ptw_0_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19] .io_ptw_0_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19] .io_ptw_0_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19] .io_ptw_0_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19] .io_ptw_0_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19] .io_ptw_0_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19] .io_ptw_0_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19] .io_ptw_0_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19] .io_ptw_0_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19] .io_ptw_0_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19] .io_ptw_0_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19] .io_ptw_0_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19] .io_ptw_0_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19] .io_ptw_0_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19] .io_ptw_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19] .io_ptw_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_1_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19] .io_ptw_1_req_valid (_zstd_compressor_io_ptw_1_req_valid), .io_ptw_1_req_bits_bits_addr (_zstd_compressor_io_ptw_1_req_bits_bits_addr), .io_ptw_1_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_1_req_bits_bits_need_gpa), .io_ptw_1_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_1_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19] .io_ptw_1_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19] .io_ptw_1_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19] .io_ptw_1_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19] .io_ptw_1_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19] .io_ptw_1_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19] .io_ptw_1_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19] .io_ptw_1_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19] .io_ptw_1_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19] .io_ptw_1_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19] .io_ptw_1_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19] .io_ptw_1_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19] .io_ptw_1_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19] .io_ptw_1_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19] .io_ptw_1_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19] .io_ptw_1_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19] .io_ptw_1_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19] .io_ptw_1_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19] .io_ptw_1_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19] .io_ptw_1_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19] .io_ptw_1_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19] .io_ptw_1_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19] .io_ptw_1_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19] .io_ptw_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19] .io_ptw_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_2_req_ready (_ptw_io_requestor_2_req_ready), // @[PTW.scala:802:19] .io_ptw_2_req_valid (_zstd_compressor_io_ptw_2_req_valid), .io_ptw_2_req_bits_bits_addr (_zstd_compressor_io_ptw_2_req_bits_bits_addr), .io_ptw_2_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_2_req_bits_bits_need_gpa), .io_ptw_2_resp_valid (_ptw_io_requestor_2_resp_valid), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_2_status_debug (_ptw_io_requestor_2_status_debug), // @[PTW.scala:802:19] .io_ptw_2_status_cease (_ptw_io_requestor_2_status_cease), // @[PTW.scala:802:19] .io_ptw_2_status_wfi (_ptw_io_requestor_2_status_wfi), // @[PTW.scala:802:19] .io_ptw_2_status_isa (_ptw_io_requestor_2_status_isa), // @[PTW.scala:802:19] .io_ptw_2_status_dprv (_ptw_io_requestor_2_status_dprv), // @[PTW.scala:802:19] .io_ptw_2_status_dv (_ptw_io_requestor_2_status_dv), // @[PTW.scala:802:19] .io_ptw_2_status_prv (_ptw_io_requestor_2_status_prv), // @[PTW.scala:802:19] .io_ptw_2_status_v (_ptw_io_requestor_2_status_v), // @[PTW.scala:802:19] .io_ptw_2_status_mpv (_ptw_io_requestor_2_status_mpv), // @[PTW.scala:802:19] .io_ptw_2_status_gva (_ptw_io_requestor_2_status_gva), // @[PTW.scala:802:19] .io_ptw_2_status_tsr (_ptw_io_requestor_2_status_tsr), // @[PTW.scala:802:19] .io_ptw_2_status_tw (_ptw_io_requestor_2_status_tw), // @[PTW.scala:802:19] .io_ptw_2_status_tvm (_ptw_io_requestor_2_status_tvm), // @[PTW.scala:802:19] .io_ptw_2_status_mxr (_ptw_io_requestor_2_status_mxr), // @[PTW.scala:802:19] .io_ptw_2_status_sum (_ptw_io_requestor_2_status_sum), // @[PTW.scala:802:19] .io_ptw_2_status_mprv (_ptw_io_requestor_2_status_mprv), // @[PTW.scala:802:19] .io_ptw_2_status_fs (_ptw_io_requestor_2_status_fs), // @[PTW.scala:802:19] .io_ptw_2_status_mpp (_ptw_io_requestor_2_status_mpp), // @[PTW.scala:802:19] .io_ptw_2_status_spp (_ptw_io_requestor_2_status_spp), // @[PTW.scala:802:19] .io_ptw_2_status_mpie (_ptw_io_requestor_2_status_mpie), // @[PTW.scala:802:19] .io_ptw_2_status_spie (_ptw_io_requestor_2_status_spie), // @[PTW.scala:802:19] .io_ptw_2_status_mie (_ptw_io_requestor_2_status_mie), // @[PTW.scala:802:19] .io_ptw_2_status_sie (_ptw_io_requestor_2_status_sie), // @[PTW.scala:802:19] .io_ptw_2_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_2_hstatus_spv (_ptw_io_requestor_2_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_2_hstatus_gva (_ptw_io_requestor_2_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_2_gstatus_debug (_ptw_io_requestor_2_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_2_gstatus_cease (_ptw_io_requestor_2_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_2_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_2_gstatus_isa (_ptw_io_requestor_2_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_2_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_dv (_ptw_io_requestor_2_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_prv (_ptw_io_requestor_2_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_v (_ptw_io_requestor_2_gstatus_v), // @[PTW.scala:802:19] .io_ptw_2_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_gva (_ptw_io_requestor_2_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_2_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tw (_ptw_io_requestor_2_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_2_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sum (_ptw_io_requestor_2_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_2_gstatus_fs (_ptw_io_requestor_2_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_2_gstatus_vs (_ptw_io_requestor_2_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_2_gstatus_spp (_ptw_io_requestor_2_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_ube (_ptw_io_requestor_2_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_2_gstatus_spie (_ptw_io_requestor_2_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_upie (_ptw_io_requestor_2_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_mie (_ptw_io_requestor_2_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_hie (_ptw_io_requestor_2_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_sie (_ptw_io_requestor_2_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_2_gstatus_uie (_ptw_io_requestor_2_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_2_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_3_req_ready (_ptw_io_requestor_3_req_ready), // @[PTW.scala:802:19] .io_ptw_3_req_valid (_zstd_compressor_io_ptw_3_req_valid), .io_ptw_3_req_bits_bits_addr (_zstd_compressor_io_ptw_3_req_bits_bits_addr), .io_ptw_3_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_3_req_bits_bits_need_gpa), .io_ptw_3_resp_valid (_ptw_io_requestor_3_resp_valid), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_ae_ptw (_ptw_io_requestor_3_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_ae_final (_ptw_io_requestor_3_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pf (_ptw_io_requestor_3_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gf (_ptw_io_requestor_3_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hr (_ptw_io_requestor_3_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hw (_ptw_io_requestor_3_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_hx (_ptw_io_requestor_3_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_reserved_for_future (_ptw_io_requestor_3_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_ppn (_ptw_io_requestor_3_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_reserved_for_software (_ptw_io_requestor_3_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_d (_ptw_io_requestor_3_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_a (_ptw_io_requestor_3_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_g (_ptw_io_requestor_3_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_u (_ptw_io_requestor_3_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_x (_ptw_io_requestor_3_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_w (_ptw_io_requestor_3_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_r (_ptw_io_requestor_3_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_pte_v (_ptw_io_requestor_3_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_level (_ptw_io_requestor_3_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_homogeneous (_ptw_io_requestor_3_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_valid (_ptw_io_requestor_3_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_bits (_ptw_io_requestor_3_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_3_resp_bits_gpa_is_pte (_ptw_io_requestor_3_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_3_ptbr_mode (_ptw_io_requestor_3_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_3_ptbr_ppn (_ptw_io_requestor_3_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_3_status_debug (_ptw_io_requestor_3_status_debug), // @[PTW.scala:802:19] .io_ptw_3_status_cease (_ptw_io_requestor_3_status_cease), // @[PTW.scala:802:19] .io_ptw_3_status_wfi (_ptw_io_requestor_3_status_wfi), // @[PTW.scala:802:19] .io_ptw_3_status_isa (_ptw_io_requestor_3_status_isa), // @[PTW.scala:802:19] .io_ptw_3_status_dprv (_ptw_io_requestor_3_status_dprv), // @[PTW.scala:802:19] .io_ptw_3_status_dv (_ptw_io_requestor_3_status_dv), // @[PTW.scala:802:19] .io_ptw_3_status_prv (_ptw_io_requestor_3_status_prv), // @[PTW.scala:802:19] .io_ptw_3_status_v (_ptw_io_requestor_3_status_v), // @[PTW.scala:802:19] .io_ptw_3_status_mpv (_ptw_io_requestor_3_status_mpv), // @[PTW.scala:802:19] .io_ptw_3_status_gva (_ptw_io_requestor_3_status_gva), // @[PTW.scala:802:19] .io_ptw_3_status_tsr (_ptw_io_requestor_3_status_tsr), // @[PTW.scala:802:19] .io_ptw_3_status_tw (_ptw_io_requestor_3_status_tw), // @[PTW.scala:802:19] .io_ptw_3_status_tvm (_ptw_io_requestor_3_status_tvm), // @[PTW.scala:802:19] .io_ptw_3_status_mxr (_ptw_io_requestor_3_status_mxr), // @[PTW.scala:802:19] .io_ptw_3_status_sum (_ptw_io_requestor_3_status_sum), // @[PTW.scala:802:19] .io_ptw_3_status_mprv (_ptw_io_requestor_3_status_mprv), // @[PTW.scala:802:19] .io_ptw_3_status_fs (_ptw_io_requestor_3_status_fs), // @[PTW.scala:802:19] .io_ptw_3_status_mpp (_ptw_io_requestor_3_status_mpp), // @[PTW.scala:802:19] .io_ptw_3_status_spp (_ptw_io_requestor_3_status_spp), // @[PTW.scala:802:19] .io_ptw_3_status_mpie (_ptw_io_requestor_3_status_mpie), // @[PTW.scala:802:19] .io_ptw_3_status_spie (_ptw_io_requestor_3_status_spie), // @[PTW.scala:802:19] .io_ptw_3_status_mie (_ptw_io_requestor_3_status_mie), // @[PTW.scala:802:19] .io_ptw_3_status_sie (_ptw_io_requestor_3_status_sie), // @[PTW.scala:802:19] .io_ptw_3_hstatus_spvp (_ptw_io_requestor_3_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_3_hstatus_spv (_ptw_io_requestor_3_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_3_hstatus_gva (_ptw_io_requestor_3_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_3_gstatus_debug (_ptw_io_requestor_3_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_3_gstatus_cease (_ptw_io_requestor_3_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_3_gstatus_wfi (_ptw_io_requestor_3_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_3_gstatus_isa (_ptw_io_requestor_3_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_3_gstatus_dprv (_ptw_io_requestor_3_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_dv (_ptw_io_requestor_3_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_prv (_ptw_io_requestor_3_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_v (_ptw_io_requestor_3_gstatus_v), // @[PTW.scala:802:19] .io_ptw_3_gstatus_zero2 (_ptw_io_requestor_3_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpv (_ptw_io_requestor_3_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_gva (_ptw_io_requestor_3_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mbe (_ptw_io_requestor_3_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sbe (_ptw_io_requestor_3_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sxl (_ptw_io_requestor_3_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_3_gstatus_zero1 (_ptw_io_requestor_3_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tsr (_ptw_io_requestor_3_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tw (_ptw_io_requestor_3_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_3_gstatus_tvm (_ptw_io_requestor_3_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mxr (_ptw_io_requestor_3_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sum (_ptw_io_requestor_3_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mprv (_ptw_io_requestor_3_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_3_gstatus_fs (_ptw_io_requestor_3_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpp (_ptw_io_requestor_3_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_3_gstatus_vs (_ptw_io_requestor_3_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_3_gstatus_spp (_ptw_io_requestor_3_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mpie (_ptw_io_requestor_3_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_ube (_ptw_io_requestor_3_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_3_gstatus_spie (_ptw_io_requestor_3_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_upie (_ptw_io_requestor_3_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_mie (_ptw_io_requestor_3_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_hie (_ptw_io_requestor_3_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_sie (_ptw_io_requestor_3_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_3_gstatus_uie (_ptw_io_requestor_3_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_l (_ptw_io_requestor_3_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_a (_ptw_io_requestor_3_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_x (_ptw_io_requestor_3_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_w (_ptw_io_requestor_3_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_cfg_r (_ptw_io_requestor_3_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_addr (_ptw_io_requestor_3_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_0_mask (_ptw_io_requestor_3_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_l (_ptw_io_requestor_3_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_a (_ptw_io_requestor_3_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_x (_ptw_io_requestor_3_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_w (_ptw_io_requestor_3_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_cfg_r (_ptw_io_requestor_3_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_addr (_ptw_io_requestor_3_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_1_mask (_ptw_io_requestor_3_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_l (_ptw_io_requestor_3_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_a (_ptw_io_requestor_3_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_x (_ptw_io_requestor_3_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_w (_ptw_io_requestor_3_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_cfg_r (_ptw_io_requestor_3_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_addr (_ptw_io_requestor_3_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_2_mask (_ptw_io_requestor_3_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_l (_ptw_io_requestor_3_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_a (_ptw_io_requestor_3_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_x (_ptw_io_requestor_3_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_w (_ptw_io_requestor_3_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_cfg_r (_ptw_io_requestor_3_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_addr (_ptw_io_requestor_3_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_3_mask (_ptw_io_requestor_3_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_l (_ptw_io_requestor_3_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_a (_ptw_io_requestor_3_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_x (_ptw_io_requestor_3_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_w (_ptw_io_requestor_3_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_cfg_r (_ptw_io_requestor_3_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_addr (_ptw_io_requestor_3_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_4_mask (_ptw_io_requestor_3_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_l (_ptw_io_requestor_3_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_a (_ptw_io_requestor_3_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_x (_ptw_io_requestor_3_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_w (_ptw_io_requestor_3_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_cfg_r (_ptw_io_requestor_3_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_addr (_ptw_io_requestor_3_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_5_mask (_ptw_io_requestor_3_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_l (_ptw_io_requestor_3_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_a (_ptw_io_requestor_3_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_x (_ptw_io_requestor_3_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_w (_ptw_io_requestor_3_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_cfg_r (_ptw_io_requestor_3_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_addr (_ptw_io_requestor_3_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_6_mask (_ptw_io_requestor_3_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_l (_ptw_io_requestor_3_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_a (_ptw_io_requestor_3_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_x (_ptw_io_requestor_3_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_w (_ptw_io_requestor_3_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_cfg_r (_ptw_io_requestor_3_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_addr (_ptw_io_requestor_3_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_3_pmp_7_mask (_ptw_io_requestor_3_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_ren (_ptw_io_requestor_3_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_wen (_ptw_io_requestor_3_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_wdata (_ptw_io_requestor_3_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_0_value (_ptw_io_requestor_3_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_ren (_ptw_io_requestor_3_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_wen (_ptw_io_requestor_3_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_wdata (_ptw_io_requestor_3_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_1_value (_ptw_io_requestor_3_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_ren (_ptw_io_requestor_3_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_wen (_ptw_io_requestor_3_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_wdata (_ptw_io_requestor_3_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_2_value (_ptw_io_requestor_3_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_ren (_ptw_io_requestor_3_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_wen (_ptw_io_requestor_3_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_wdata (_ptw_io_requestor_3_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_3_customCSRs_csrs_3_value (_ptw_io_requestor_3_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_4_req_ready (_ptw_io_requestor_4_req_ready), // @[PTW.scala:802:19] .io_ptw_4_req_valid (_zstd_compressor_io_ptw_4_req_valid), .io_ptw_4_req_bits_bits_addr (_zstd_compressor_io_ptw_4_req_bits_bits_addr), .io_ptw_4_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_4_req_bits_bits_need_gpa), .io_ptw_4_resp_valid (_ptw_io_requestor_4_resp_valid), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_ae_ptw (_ptw_io_requestor_4_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_ae_final (_ptw_io_requestor_4_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pf (_ptw_io_requestor_4_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gf (_ptw_io_requestor_4_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hr (_ptw_io_requestor_4_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hw (_ptw_io_requestor_4_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_hx (_ptw_io_requestor_4_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_reserved_for_future (_ptw_io_requestor_4_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_ppn (_ptw_io_requestor_4_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_reserved_for_software (_ptw_io_requestor_4_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_d (_ptw_io_requestor_4_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_a (_ptw_io_requestor_4_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_g (_ptw_io_requestor_4_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_u (_ptw_io_requestor_4_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_x (_ptw_io_requestor_4_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_w (_ptw_io_requestor_4_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_r (_ptw_io_requestor_4_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_pte_v (_ptw_io_requestor_4_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_level (_ptw_io_requestor_4_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_homogeneous (_ptw_io_requestor_4_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_valid (_ptw_io_requestor_4_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_bits (_ptw_io_requestor_4_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_4_resp_bits_gpa_is_pte (_ptw_io_requestor_4_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_4_ptbr_mode (_ptw_io_requestor_4_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_4_ptbr_ppn (_ptw_io_requestor_4_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_4_status_debug (_ptw_io_requestor_4_status_debug), // @[PTW.scala:802:19] .io_ptw_4_status_cease (_ptw_io_requestor_4_status_cease), // @[PTW.scala:802:19] .io_ptw_4_status_wfi (_ptw_io_requestor_4_status_wfi), // @[PTW.scala:802:19] .io_ptw_4_status_isa (_ptw_io_requestor_4_status_isa), // @[PTW.scala:802:19] .io_ptw_4_status_dprv (_ptw_io_requestor_4_status_dprv), // @[PTW.scala:802:19] .io_ptw_4_status_dv (_ptw_io_requestor_4_status_dv), // @[PTW.scala:802:19] .io_ptw_4_status_prv (_ptw_io_requestor_4_status_prv), // @[PTW.scala:802:19] .io_ptw_4_status_v (_ptw_io_requestor_4_status_v), // @[PTW.scala:802:19] .io_ptw_4_status_mpv (_ptw_io_requestor_4_status_mpv), // @[PTW.scala:802:19] .io_ptw_4_status_gva (_ptw_io_requestor_4_status_gva), // @[PTW.scala:802:19] .io_ptw_4_status_tsr (_ptw_io_requestor_4_status_tsr), // @[PTW.scala:802:19] .io_ptw_4_status_tw (_ptw_io_requestor_4_status_tw), // @[PTW.scala:802:19] .io_ptw_4_status_tvm (_ptw_io_requestor_4_status_tvm), // @[PTW.scala:802:19] .io_ptw_4_status_mxr (_ptw_io_requestor_4_status_mxr), // @[PTW.scala:802:19] .io_ptw_4_status_sum (_ptw_io_requestor_4_status_sum), // @[PTW.scala:802:19] .io_ptw_4_status_mprv (_ptw_io_requestor_4_status_mprv), // @[PTW.scala:802:19] .io_ptw_4_status_fs (_ptw_io_requestor_4_status_fs), // @[PTW.scala:802:19] .io_ptw_4_status_mpp (_ptw_io_requestor_4_status_mpp), // @[PTW.scala:802:19] .io_ptw_4_status_spp (_ptw_io_requestor_4_status_spp), // @[PTW.scala:802:19] .io_ptw_4_status_mpie (_ptw_io_requestor_4_status_mpie), // @[PTW.scala:802:19] .io_ptw_4_status_spie (_ptw_io_requestor_4_status_spie), // @[PTW.scala:802:19] .io_ptw_4_status_mie (_ptw_io_requestor_4_status_mie), // @[PTW.scala:802:19] .io_ptw_4_status_sie (_ptw_io_requestor_4_status_sie), // @[PTW.scala:802:19] .io_ptw_4_hstatus_spvp (_ptw_io_requestor_4_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_4_hstatus_spv (_ptw_io_requestor_4_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_4_hstatus_gva (_ptw_io_requestor_4_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_4_gstatus_debug (_ptw_io_requestor_4_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_4_gstatus_cease (_ptw_io_requestor_4_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_4_gstatus_wfi (_ptw_io_requestor_4_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_4_gstatus_isa (_ptw_io_requestor_4_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_4_gstatus_dprv (_ptw_io_requestor_4_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_dv (_ptw_io_requestor_4_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_prv (_ptw_io_requestor_4_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_v (_ptw_io_requestor_4_gstatus_v), // @[PTW.scala:802:19] .io_ptw_4_gstatus_zero2 (_ptw_io_requestor_4_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpv (_ptw_io_requestor_4_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_gva (_ptw_io_requestor_4_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mbe (_ptw_io_requestor_4_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sbe (_ptw_io_requestor_4_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sxl (_ptw_io_requestor_4_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_4_gstatus_zero1 (_ptw_io_requestor_4_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tsr (_ptw_io_requestor_4_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tw (_ptw_io_requestor_4_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_4_gstatus_tvm (_ptw_io_requestor_4_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mxr (_ptw_io_requestor_4_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sum (_ptw_io_requestor_4_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mprv (_ptw_io_requestor_4_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_4_gstatus_fs (_ptw_io_requestor_4_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpp (_ptw_io_requestor_4_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_4_gstatus_vs (_ptw_io_requestor_4_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_4_gstatus_spp (_ptw_io_requestor_4_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mpie (_ptw_io_requestor_4_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_ube (_ptw_io_requestor_4_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_4_gstatus_spie (_ptw_io_requestor_4_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_upie (_ptw_io_requestor_4_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_mie (_ptw_io_requestor_4_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_hie (_ptw_io_requestor_4_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_sie (_ptw_io_requestor_4_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_4_gstatus_uie (_ptw_io_requestor_4_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_l (_ptw_io_requestor_4_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_a (_ptw_io_requestor_4_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_x (_ptw_io_requestor_4_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_w (_ptw_io_requestor_4_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_cfg_r (_ptw_io_requestor_4_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_addr (_ptw_io_requestor_4_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_0_mask (_ptw_io_requestor_4_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_l (_ptw_io_requestor_4_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_a (_ptw_io_requestor_4_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_x (_ptw_io_requestor_4_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_w (_ptw_io_requestor_4_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_cfg_r (_ptw_io_requestor_4_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_addr (_ptw_io_requestor_4_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_1_mask (_ptw_io_requestor_4_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_l (_ptw_io_requestor_4_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_a (_ptw_io_requestor_4_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_x (_ptw_io_requestor_4_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_w (_ptw_io_requestor_4_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_cfg_r (_ptw_io_requestor_4_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_addr (_ptw_io_requestor_4_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_2_mask (_ptw_io_requestor_4_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_l (_ptw_io_requestor_4_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_a (_ptw_io_requestor_4_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_x (_ptw_io_requestor_4_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_w (_ptw_io_requestor_4_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_cfg_r (_ptw_io_requestor_4_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_addr (_ptw_io_requestor_4_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_3_mask (_ptw_io_requestor_4_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_l (_ptw_io_requestor_4_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_a (_ptw_io_requestor_4_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_x (_ptw_io_requestor_4_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_w (_ptw_io_requestor_4_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_cfg_r (_ptw_io_requestor_4_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_addr (_ptw_io_requestor_4_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_4_mask (_ptw_io_requestor_4_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_l (_ptw_io_requestor_4_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_a (_ptw_io_requestor_4_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_x (_ptw_io_requestor_4_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_w (_ptw_io_requestor_4_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_cfg_r (_ptw_io_requestor_4_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_addr (_ptw_io_requestor_4_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_5_mask (_ptw_io_requestor_4_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_l (_ptw_io_requestor_4_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_a (_ptw_io_requestor_4_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_x (_ptw_io_requestor_4_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_w (_ptw_io_requestor_4_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_cfg_r (_ptw_io_requestor_4_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_addr (_ptw_io_requestor_4_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_6_mask (_ptw_io_requestor_4_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_l (_ptw_io_requestor_4_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_a (_ptw_io_requestor_4_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_x (_ptw_io_requestor_4_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_w (_ptw_io_requestor_4_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_cfg_r (_ptw_io_requestor_4_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_addr (_ptw_io_requestor_4_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_4_pmp_7_mask (_ptw_io_requestor_4_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_ren (_ptw_io_requestor_4_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_wen (_ptw_io_requestor_4_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_wdata (_ptw_io_requestor_4_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_0_value (_ptw_io_requestor_4_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_ren (_ptw_io_requestor_4_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_wen (_ptw_io_requestor_4_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_wdata (_ptw_io_requestor_4_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_1_value (_ptw_io_requestor_4_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_ren (_ptw_io_requestor_4_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_wen (_ptw_io_requestor_4_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_wdata (_ptw_io_requestor_4_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_2_value (_ptw_io_requestor_4_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_ren (_ptw_io_requestor_4_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_wen (_ptw_io_requestor_4_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_wdata (_ptw_io_requestor_4_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_4_customCSRs_csrs_3_value (_ptw_io_requestor_4_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_5_req_ready (_ptw_io_requestor_5_req_ready), // @[PTW.scala:802:19] .io_ptw_5_req_valid (_zstd_compressor_io_ptw_5_req_valid), .io_ptw_5_req_bits_bits_addr (_zstd_compressor_io_ptw_5_req_bits_bits_addr), .io_ptw_5_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_5_req_bits_bits_need_gpa), .io_ptw_5_resp_valid (_ptw_io_requestor_5_resp_valid), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_ae_ptw (_ptw_io_requestor_5_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_ae_final (_ptw_io_requestor_5_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pf (_ptw_io_requestor_5_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gf (_ptw_io_requestor_5_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hr (_ptw_io_requestor_5_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hw (_ptw_io_requestor_5_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_hx (_ptw_io_requestor_5_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_reserved_for_future (_ptw_io_requestor_5_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_ppn (_ptw_io_requestor_5_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_reserved_for_software (_ptw_io_requestor_5_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_d (_ptw_io_requestor_5_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_a (_ptw_io_requestor_5_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_g (_ptw_io_requestor_5_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_u (_ptw_io_requestor_5_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_x (_ptw_io_requestor_5_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_w (_ptw_io_requestor_5_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_r (_ptw_io_requestor_5_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_pte_v (_ptw_io_requestor_5_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_level (_ptw_io_requestor_5_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_homogeneous (_ptw_io_requestor_5_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_valid (_ptw_io_requestor_5_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_bits (_ptw_io_requestor_5_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_5_resp_bits_gpa_is_pte (_ptw_io_requestor_5_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_5_ptbr_mode (_ptw_io_requestor_5_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_5_ptbr_ppn (_ptw_io_requestor_5_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_5_status_debug (_ptw_io_requestor_5_status_debug), // @[PTW.scala:802:19] .io_ptw_5_status_cease (_ptw_io_requestor_5_status_cease), // @[PTW.scala:802:19] .io_ptw_5_status_wfi (_ptw_io_requestor_5_status_wfi), // @[PTW.scala:802:19] .io_ptw_5_status_isa (_ptw_io_requestor_5_status_isa), // @[PTW.scala:802:19] .io_ptw_5_status_dprv (_ptw_io_requestor_5_status_dprv), // @[PTW.scala:802:19] .io_ptw_5_status_dv (_ptw_io_requestor_5_status_dv), // @[PTW.scala:802:19] .io_ptw_5_status_prv (_ptw_io_requestor_5_status_prv), // @[PTW.scala:802:19] .io_ptw_5_status_v (_ptw_io_requestor_5_status_v), // @[PTW.scala:802:19] .io_ptw_5_status_mpv (_ptw_io_requestor_5_status_mpv), // @[PTW.scala:802:19] .io_ptw_5_status_gva (_ptw_io_requestor_5_status_gva), // @[PTW.scala:802:19] .io_ptw_5_status_tsr (_ptw_io_requestor_5_status_tsr), // @[PTW.scala:802:19] .io_ptw_5_status_tw (_ptw_io_requestor_5_status_tw), // @[PTW.scala:802:19] .io_ptw_5_status_tvm (_ptw_io_requestor_5_status_tvm), // @[PTW.scala:802:19] .io_ptw_5_status_mxr (_ptw_io_requestor_5_status_mxr), // @[PTW.scala:802:19] .io_ptw_5_status_sum (_ptw_io_requestor_5_status_sum), // @[PTW.scala:802:19] .io_ptw_5_status_mprv (_ptw_io_requestor_5_status_mprv), // @[PTW.scala:802:19] .io_ptw_5_status_fs (_ptw_io_requestor_5_status_fs), // @[PTW.scala:802:19] .io_ptw_5_status_mpp (_ptw_io_requestor_5_status_mpp), // @[PTW.scala:802:19] .io_ptw_5_status_spp (_ptw_io_requestor_5_status_spp), // @[PTW.scala:802:19] .io_ptw_5_status_mpie (_ptw_io_requestor_5_status_mpie), // @[PTW.scala:802:19] .io_ptw_5_status_spie (_ptw_io_requestor_5_status_spie), // @[PTW.scala:802:19] .io_ptw_5_status_mie (_ptw_io_requestor_5_status_mie), // @[PTW.scala:802:19] .io_ptw_5_status_sie (_ptw_io_requestor_5_status_sie), // @[PTW.scala:802:19] .io_ptw_5_hstatus_spvp (_ptw_io_requestor_5_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_5_hstatus_spv (_ptw_io_requestor_5_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_5_hstatus_gva (_ptw_io_requestor_5_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_5_gstatus_debug (_ptw_io_requestor_5_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_5_gstatus_cease (_ptw_io_requestor_5_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_5_gstatus_wfi (_ptw_io_requestor_5_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_5_gstatus_isa (_ptw_io_requestor_5_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_5_gstatus_dprv (_ptw_io_requestor_5_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_dv (_ptw_io_requestor_5_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_prv (_ptw_io_requestor_5_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_v (_ptw_io_requestor_5_gstatus_v), // @[PTW.scala:802:19] .io_ptw_5_gstatus_zero2 (_ptw_io_requestor_5_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpv (_ptw_io_requestor_5_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_gva (_ptw_io_requestor_5_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mbe (_ptw_io_requestor_5_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sbe (_ptw_io_requestor_5_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sxl (_ptw_io_requestor_5_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_5_gstatus_zero1 (_ptw_io_requestor_5_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tsr (_ptw_io_requestor_5_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tw (_ptw_io_requestor_5_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_5_gstatus_tvm (_ptw_io_requestor_5_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mxr (_ptw_io_requestor_5_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sum (_ptw_io_requestor_5_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mprv (_ptw_io_requestor_5_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_5_gstatus_fs (_ptw_io_requestor_5_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpp (_ptw_io_requestor_5_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_5_gstatus_vs (_ptw_io_requestor_5_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_5_gstatus_spp (_ptw_io_requestor_5_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mpie (_ptw_io_requestor_5_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_ube (_ptw_io_requestor_5_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_5_gstatus_spie (_ptw_io_requestor_5_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_upie (_ptw_io_requestor_5_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_mie (_ptw_io_requestor_5_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_hie (_ptw_io_requestor_5_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_sie (_ptw_io_requestor_5_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_5_gstatus_uie (_ptw_io_requestor_5_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_l (_ptw_io_requestor_5_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_a (_ptw_io_requestor_5_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_x (_ptw_io_requestor_5_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_w (_ptw_io_requestor_5_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_cfg_r (_ptw_io_requestor_5_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_addr (_ptw_io_requestor_5_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_0_mask (_ptw_io_requestor_5_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_l (_ptw_io_requestor_5_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_a (_ptw_io_requestor_5_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_x (_ptw_io_requestor_5_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_w (_ptw_io_requestor_5_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_cfg_r (_ptw_io_requestor_5_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_addr (_ptw_io_requestor_5_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_1_mask (_ptw_io_requestor_5_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_l (_ptw_io_requestor_5_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_a (_ptw_io_requestor_5_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_x (_ptw_io_requestor_5_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_w (_ptw_io_requestor_5_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_cfg_r (_ptw_io_requestor_5_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_addr (_ptw_io_requestor_5_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_2_mask (_ptw_io_requestor_5_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_l (_ptw_io_requestor_5_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_a (_ptw_io_requestor_5_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_x (_ptw_io_requestor_5_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_w (_ptw_io_requestor_5_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_cfg_r (_ptw_io_requestor_5_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_addr (_ptw_io_requestor_5_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_3_mask (_ptw_io_requestor_5_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_l (_ptw_io_requestor_5_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_a (_ptw_io_requestor_5_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_x (_ptw_io_requestor_5_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_w (_ptw_io_requestor_5_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_cfg_r (_ptw_io_requestor_5_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_addr (_ptw_io_requestor_5_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_4_mask (_ptw_io_requestor_5_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_l (_ptw_io_requestor_5_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_a (_ptw_io_requestor_5_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_x (_ptw_io_requestor_5_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_w (_ptw_io_requestor_5_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_cfg_r (_ptw_io_requestor_5_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_addr (_ptw_io_requestor_5_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_5_mask (_ptw_io_requestor_5_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_l (_ptw_io_requestor_5_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_a (_ptw_io_requestor_5_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_x (_ptw_io_requestor_5_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_w (_ptw_io_requestor_5_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_cfg_r (_ptw_io_requestor_5_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_addr (_ptw_io_requestor_5_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_6_mask (_ptw_io_requestor_5_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_l (_ptw_io_requestor_5_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_a (_ptw_io_requestor_5_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_x (_ptw_io_requestor_5_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_w (_ptw_io_requestor_5_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_cfg_r (_ptw_io_requestor_5_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_addr (_ptw_io_requestor_5_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_5_pmp_7_mask (_ptw_io_requestor_5_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_ren (_ptw_io_requestor_5_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_wen (_ptw_io_requestor_5_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_wdata (_ptw_io_requestor_5_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_0_value (_ptw_io_requestor_5_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_ren (_ptw_io_requestor_5_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_wen (_ptw_io_requestor_5_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_wdata (_ptw_io_requestor_5_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_1_value (_ptw_io_requestor_5_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_ren (_ptw_io_requestor_5_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_wen (_ptw_io_requestor_5_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_wdata (_ptw_io_requestor_5_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_2_value (_ptw_io_requestor_5_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_ren (_ptw_io_requestor_5_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_wen (_ptw_io_requestor_5_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_wdata (_ptw_io_requestor_5_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_5_customCSRs_csrs_3_value (_ptw_io_requestor_5_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_6_req_ready (_ptw_io_requestor_6_req_ready), // @[PTW.scala:802:19] .io_ptw_6_req_valid (_zstd_compressor_io_ptw_6_req_valid), .io_ptw_6_req_bits_bits_addr (_zstd_compressor_io_ptw_6_req_bits_bits_addr), .io_ptw_6_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_6_req_bits_bits_need_gpa), .io_ptw_6_resp_valid (_ptw_io_requestor_6_resp_valid), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_ae_ptw (_ptw_io_requestor_6_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_ae_final (_ptw_io_requestor_6_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pf (_ptw_io_requestor_6_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gf (_ptw_io_requestor_6_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hr (_ptw_io_requestor_6_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hw (_ptw_io_requestor_6_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_hx (_ptw_io_requestor_6_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_reserved_for_future (_ptw_io_requestor_6_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_ppn (_ptw_io_requestor_6_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_reserved_for_software (_ptw_io_requestor_6_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_d (_ptw_io_requestor_6_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_a (_ptw_io_requestor_6_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_g (_ptw_io_requestor_6_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_u (_ptw_io_requestor_6_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_x (_ptw_io_requestor_6_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_w (_ptw_io_requestor_6_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_r (_ptw_io_requestor_6_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_pte_v (_ptw_io_requestor_6_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_level (_ptw_io_requestor_6_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_homogeneous (_ptw_io_requestor_6_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_valid (_ptw_io_requestor_6_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_bits (_ptw_io_requestor_6_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_6_resp_bits_gpa_is_pte (_ptw_io_requestor_6_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_6_ptbr_mode (_ptw_io_requestor_6_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_6_ptbr_ppn (_ptw_io_requestor_6_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_6_status_debug (_ptw_io_requestor_6_status_debug), // @[PTW.scala:802:19] .io_ptw_6_status_cease (_ptw_io_requestor_6_status_cease), // @[PTW.scala:802:19] .io_ptw_6_status_wfi (_ptw_io_requestor_6_status_wfi), // @[PTW.scala:802:19] .io_ptw_6_status_isa (_ptw_io_requestor_6_status_isa), // @[PTW.scala:802:19] .io_ptw_6_status_dprv (_ptw_io_requestor_6_status_dprv), // @[PTW.scala:802:19] .io_ptw_6_status_dv (_ptw_io_requestor_6_status_dv), // @[PTW.scala:802:19] .io_ptw_6_status_prv (_ptw_io_requestor_6_status_prv), // @[PTW.scala:802:19] .io_ptw_6_status_v (_ptw_io_requestor_6_status_v), // @[PTW.scala:802:19] .io_ptw_6_status_mpv (_ptw_io_requestor_6_status_mpv), // @[PTW.scala:802:19] .io_ptw_6_status_gva (_ptw_io_requestor_6_status_gva), // @[PTW.scala:802:19] .io_ptw_6_status_tsr (_ptw_io_requestor_6_status_tsr), // @[PTW.scala:802:19] .io_ptw_6_status_tw (_ptw_io_requestor_6_status_tw), // @[PTW.scala:802:19] .io_ptw_6_status_tvm (_ptw_io_requestor_6_status_tvm), // @[PTW.scala:802:19] .io_ptw_6_status_mxr (_ptw_io_requestor_6_status_mxr), // @[PTW.scala:802:19] .io_ptw_6_status_sum (_ptw_io_requestor_6_status_sum), // @[PTW.scala:802:19] .io_ptw_6_status_mprv (_ptw_io_requestor_6_status_mprv), // @[PTW.scala:802:19] .io_ptw_6_status_fs (_ptw_io_requestor_6_status_fs), // @[PTW.scala:802:19] .io_ptw_6_status_mpp (_ptw_io_requestor_6_status_mpp), // @[PTW.scala:802:19] .io_ptw_6_status_spp (_ptw_io_requestor_6_status_spp), // @[PTW.scala:802:19] .io_ptw_6_status_mpie (_ptw_io_requestor_6_status_mpie), // @[PTW.scala:802:19] .io_ptw_6_status_spie (_ptw_io_requestor_6_status_spie), // @[PTW.scala:802:19] .io_ptw_6_status_mie (_ptw_io_requestor_6_status_mie), // @[PTW.scala:802:19] .io_ptw_6_status_sie (_ptw_io_requestor_6_status_sie), // @[PTW.scala:802:19] .io_ptw_6_hstatus_spvp (_ptw_io_requestor_6_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_6_hstatus_spv (_ptw_io_requestor_6_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_6_hstatus_gva (_ptw_io_requestor_6_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_6_gstatus_debug (_ptw_io_requestor_6_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_6_gstatus_cease (_ptw_io_requestor_6_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_6_gstatus_wfi (_ptw_io_requestor_6_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_6_gstatus_isa (_ptw_io_requestor_6_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_6_gstatus_dprv (_ptw_io_requestor_6_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_dv (_ptw_io_requestor_6_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_prv (_ptw_io_requestor_6_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_v (_ptw_io_requestor_6_gstatus_v), // @[PTW.scala:802:19] .io_ptw_6_gstatus_zero2 (_ptw_io_requestor_6_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpv (_ptw_io_requestor_6_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_gva (_ptw_io_requestor_6_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mbe (_ptw_io_requestor_6_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sbe (_ptw_io_requestor_6_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sxl (_ptw_io_requestor_6_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_6_gstatus_zero1 (_ptw_io_requestor_6_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tsr (_ptw_io_requestor_6_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tw (_ptw_io_requestor_6_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_6_gstatus_tvm (_ptw_io_requestor_6_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mxr (_ptw_io_requestor_6_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sum (_ptw_io_requestor_6_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mprv (_ptw_io_requestor_6_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_6_gstatus_fs (_ptw_io_requestor_6_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpp (_ptw_io_requestor_6_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_6_gstatus_vs (_ptw_io_requestor_6_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_6_gstatus_spp (_ptw_io_requestor_6_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mpie (_ptw_io_requestor_6_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_ube (_ptw_io_requestor_6_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_6_gstatus_spie (_ptw_io_requestor_6_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_upie (_ptw_io_requestor_6_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_mie (_ptw_io_requestor_6_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_hie (_ptw_io_requestor_6_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_sie (_ptw_io_requestor_6_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_6_gstatus_uie (_ptw_io_requestor_6_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_l (_ptw_io_requestor_6_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_a (_ptw_io_requestor_6_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_x (_ptw_io_requestor_6_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_w (_ptw_io_requestor_6_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_cfg_r (_ptw_io_requestor_6_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_addr (_ptw_io_requestor_6_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_0_mask (_ptw_io_requestor_6_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_l (_ptw_io_requestor_6_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_a (_ptw_io_requestor_6_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_x (_ptw_io_requestor_6_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_w (_ptw_io_requestor_6_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_cfg_r (_ptw_io_requestor_6_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_addr (_ptw_io_requestor_6_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_1_mask (_ptw_io_requestor_6_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_l (_ptw_io_requestor_6_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_a (_ptw_io_requestor_6_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_x (_ptw_io_requestor_6_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_w (_ptw_io_requestor_6_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_cfg_r (_ptw_io_requestor_6_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_addr (_ptw_io_requestor_6_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_2_mask (_ptw_io_requestor_6_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_l (_ptw_io_requestor_6_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_a (_ptw_io_requestor_6_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_x (_ptw_io_requestor_6_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_w (_ptw_io_requestor_6_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_cfg_r (_ptw_io_requestor_6_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_addr (_ptw_io_requestor_6_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_3_mask (_ptw_io_requestor_6_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_l (_ptw_io_requestor_6_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_a (_ptw_io_requestor_6_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_x (_ptw_io_requestor_6_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_w (_ptw_io_requestor_6_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_cfg_r (_ptw_io_requestor_6_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_addr (_ptw_io_requestor_6_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_4_mask (_ptw_io_requestor_6_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_l (_ptw_io_requestor_6_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_a (_ptw_io_requestor_6_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_x (_ptw_io_requestor_6_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_w (_ptw_io_requestor_6_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_cfg_r (_ptw_io_requestor_6_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_addr (_ptw_io_requestor_6_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_5_mask (_ptw_io_requestor_6_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_l (_ptw_io_requestor_6_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_a (_ptw_io_requestor_6_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_x (_ptw_io_requestor_6_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_w (_ptw_io_requestor_6_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_cfg_r (_ptw_io_requestor_6_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_addr (_ptw_io_requestor_6_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_6_mask (_ptw_io_requestor_6_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_l (_ptw_io_requestor_6_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_a (_ptw_io_requestor_6_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_x (_ptw_io_requestor_6_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_w (_ptw_io_requestor_6_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_cfg_r (_ptw_io_requestor_6_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_addr (_ptw_io_requestor_6_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_6_pmp_7_mask (_ptw_io_requestor_6_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_ren (_ptw_io_requestor_6_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_wen (_ptw_io_requestor_6_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_wdata (_ptw_io_requestor_6_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_0_value (_ptw_io_requestor_6_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_ren (_ptw_io_requestor_6_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_wen (_ptw_io_requestor_6_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_wdata (_ptw_io_requestor_6_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_1_value (_ptw_io_requestor_6_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_ren (_ptw_io_requestor_6_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_wen (_ptw_io_requestor_6_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_wdata (_ptw_io_requestor_6_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_2_value (_ptw_io_requestor_6_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_ren (_ptw_io_requestor_6_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_wen (_ptw_io_requestor_6_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_wdata (_ptw_io_requestor_6_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_6_customCSRs_csrs_3_value (_ptw_io_requestor_6_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_7_req_ready (_ptw_io_requestor_7_req_ready), // @[PTW.scala:802:19] .io_ptw_7_req_valid (_zstd_compressor_io_ptw_7_req_valid), .io_ptw_7_req_bits_bits_addr (_zstd_compressor_io_ptw_7_req_bits_bits_addr), .io_ptw_7_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_7_req_bits_bits_need_gpa), .io_ptw_7_resp_valid (_ptw_io_requestor_7_resp_valid), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_ae_ptw (_ptw_io_requestor_7_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_ae_final (_ptw_io_requestor_7_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pf (_ptw_io_requestor_7_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gf (_ptw_io_requestor_7_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hr (_ptw_io_requestor_7_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hw (_ptw_io_requestor_7_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_hx (_ptw_io_requestor_7_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_reserved_for_future (_ptw_io_requestor_7_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_ppn (_ptw_io_requestor_7_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_reserved_for_software (_ptw_io_requestor_7_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_d (_ptw_io_requestor_7_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_a (_ptw_io_requestor_7_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_g (_ptw_io_requestor_7_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_u (_ptw_io_requestor_7_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_x (_ptw_io_requestor_7_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_w (_ptw_io_requestor_7_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_r (_ptw_io_requestor_7_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_pte_v (_ptw_io_requestor_7_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_level (_ptw_io_requestor_7_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_homogeneous (_ptw_io_requestor_7_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_valid (_ptw_io_requestor_7_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_bits (_ptw_io_requestor_7_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_7_resp_bits_gpa_is_pte (_ptw_io_requestor_7_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_7_ptbr_mode (_ptw_io_requestor_7_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_7_ptbr_ppn (_ptw_io_requestor_7_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_7_status_debug (_ptw_io_requestor_7_status_debug), // @[PTW.scala:802:19] .io_ptw_7_status_cease (_ptw_io_requestor_7_status_cease), // @[PTW.scala:802:19] .io_ptw_7_status_wfi (_ptw_io_requestor_7_status_wfi), // @[PTW.scala:802:19] .io_ptw_7_status_isa (_ptw_io_requestor_7_status_isa), // @[PTW.scala:802:19] .io_ptw_7_status_dprv (_ptw_io_requestor_7_status_dprv), // @[PTW.scala:802:19] .io_ptw_7_status_dv (_ptw_io_requestor_7_status_dv), // @[PTW.scala:802:19] .io_ptw_7_status_prv (_ptw_io_requestor_7_status_prv), // @[PTW.scala:802:19] .io_ptw_7_status_v (_ptw_io_requestor_7_status_v), // @[PTW.scala:802:19] .io_ptw_7_status_mpv (_ptw_io_requestor_7_status_mpv), // @[PTW.scala:802:19] .io_ptw_7_status_gva (_ptw_io_requestor_7_status_gva), // @[PTW.scala:802:19] .io_ptw_7_status_tsr (_ptw_io_requestor_7_status_tsr), // @[PTW.scala:802:19] .io_ptw_7_status_tw (_ptw_io_requestor_7_status_tw), // @[PTW.scala:802:19] .io_ptw_7_status_tvm (_ptw_io_requestor_7_status_tvm), // @[PTW.scala:802:19] .io_ptw_7_status_mxr (_ptw_io_requestor_7_status_mxr), // @[PTW.scala:802:19] .io_ptw_7_status_sum (_ptw_io_requestor_7_status_sum), // @[PTW.scala:802:19] .io_ptw_7_status_mprv (_ptw_io_requestor_7_status_mprv), // @[PTW.scala:802:19] .io_ptw_7_status_fs (_ptw_io_requestor_7_status_fs), // @[PTW.scala:802:19] .io_ptw_7_status_mpp (_ptw_io_requestor_7_status_mpp), // @[PTW.scala:802:19] .io_ptw_7_status_spp (_ptw_io_requestor_7_status_spp), // @[PTW.scala:802:19] .io_ptw_7_status_mpie (_ptw_io_requestor_7_status_mpie), // @[PTW.scala:802:19] .io_ptw_7_status_spie (_ptw_io_requestor_7_status_spie), // @[PTW.scala:802:19] .io_ptw_7_status_mie (_ptw_io_requestor_7_status_mie), // @[PTW.scala:802:19] .io_ptw_7_status_sie (_ptw_io_requestor_7_status_sie), // @[PTW.scala:802:19] .io_ptw_7_hstatus_spvp (_ptw_io_requestor_7_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_7_hstatus_spv (_ptw_io_requestor_7_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_7_hstatus_gva (_ptw_io_requestor_7_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_7_gstatus_debug (_ptw_io_requestor_7_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_7_gstatus_cease (_ptw_io_requestor_7_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_7_gstatus_wfi (_ptw_io_requestor_7_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_7_gstatus_isa (_ptw_io_requestor_7_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_7_gstatus_dprv (_ptw_io_requestor_7_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_dv (_ptw_io_requestor_7_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_prv (_ptw_io_requestor_7_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_v (_ptw_io_requestor_7_gstatus_v), // @[PTW.scala:802:19] .io_ptw_7_gstatus_zero2 (_ptw_io_requestor_7_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpv (_ptw_io_requestor_7_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_gva (_ptw_io_requestor_7_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mbe (_ptw_io_requestor_7_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sbe (_ptw_io_requestor_7_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sxl (_ptw_io_requestor_7_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_7_gstatus_zero1 (_ptw_io_requestor_7_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tsr (_ptw_io_requestor_7_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tw (_ptw_io_requestor_7_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_7_gstatus_tvm (_ptw_io_requestor_7_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mxr (_ptw_io_requestor_7_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sum (_ptw_io_requestor_7_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mprv (_ptw_io_requestor_7_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_7_gstatus_fs (_ptw_io_requestor_7_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpp (_ptw_io_requestor_7_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_7_gstatus_vs (_ptw_io_requestor_7_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_7_gstatus_spp (_ptw_io_requestor_7_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mpie (_ptw_io_requestor_7_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_ube (_ptw_io_requestor_7_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_7_gstatus_spie (_ptw_io_requestor_7_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_upie (_ptw_io_requestor_7_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_mie (_ptw_io_requestor_7_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_hie (_ptw_io_requestor_7_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_sie (_ptw_io_requestor_7_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_7_gstatus_uie (_ptw_io_requestor_7_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_l (_ptw_io_requestor_7_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_a (_ptw_io_requestor_7_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_x (_ptw_io_requestor_7_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_w (_ptw_io_requestor_7_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_cfg_r (_ptw_io_requestor_7_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_addr (_ptw_io_requestor_7_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_0_mask (_ptw_io_requestor_7_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_l (_ptw_io_requestor_7_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_a (_ptw_io_requestor_7_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_x (_ptw_io_requestor_7_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_w (_ptw_io_requestor_7_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_cfg_r (_ptw_io_requestor_7_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_addr (_ptw_io_requestor_7_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_1_mask (_ptw_io_requestor_7_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_l (_ptw_io_requestor_7_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_a (_ptw_io_requestor_7_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_x (_ptw_io_requestor_7_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_w (_ptw_io_requestor_7_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_cfg_r (_ptw_io_requestor_7_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_addr (_ptw_io_requestor_7_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_2_mask (_ptw_io_requestor_7_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_l (_ptw_io_requestor_7_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_a (_ptw_io_requestor_7_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_x (_ptw_io_requestor_7_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_w (_ptw_io_requestor_7_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_cfg_r (_ptw_io_requestor_7_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_addr (_ptw_io_requestor_7_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_3_mask (_ptw_io_requestor_7_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_l (_ptw_io_requestor_7_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_a (_ptw_io_requestor_7_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_x (_ptw_io_requestor_7_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_w (_ptw_io_requestor_7_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_cfg_r (_ptw_io_requestor_7_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_addr (_ptw_io_requestor_7_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_4_mask (_ptw_io_requestor_7_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_l (_ptw_io_requestor_7_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_a (_ptw_io_requestor_7_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_x (_ptw_io_requestor_7_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_w (_ptw_io_requestor_7_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_cfg_r (_ptw_io_requestor_7_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_addr (_ptw_io_requestor_7_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_5_mask (_ptw_io_requestor_7_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_l (_ptw_io_requestor_7_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_a (_ptw_io_requestor_7_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_x (_ptw_io_requestor_7_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_w (_ptw_io_requestor_7_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_cfg_r (_ptw_io_requestor_7_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_addr (_ptw_io_requestor_7_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_6_mask (_ptw_io_requestor_7_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_l (_ptw_io_requestor_7_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_a (_ptw_io_requestor_7_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_x (_ptw_io_requestor_7_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_w (_ptw_io_requestor_7_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_cfg_r (_ptw_io_requestor_7_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_addr (_ptw_io_requestor_7_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_7_pmp_7_mask (_ptw_io_requestor_7_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_ren (_ptw_io_requestor_7_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_wen (_ptw_io_requestor_7_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_wdata (_ptw_io_requestor_7_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_0_value (_ptw_io_requestor_7_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_ren (_ptw_io_requestor_7_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_wen (_ptw_io_requestor_7_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_wdata (_ptw_io_requestor_7_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_1_value (_ptw_io_requestor_7_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_ren (_ptw_io_requestor_7_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_wen (_ptw_io_requestor_7_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_wdata (_ptw_io_requestor_7_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_2_value (_ptw_io_requestor_7_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_ren (_ptw_io_requestor_7_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_wen (_ptw_io_requestor_7_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_wdata (_ptw_io_requestor_7_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_7_customCSRs_csrs_3_value (_ptw_io_requestor_7_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_8_req_ready (_ptw_io_requestor_8_req_ready), // @[PTW.scala:802:19] .io_ptw_8_req_valid (_zstd_compressor_io_ptw_8_req_valid), .io_ptw_8_req_bits_bits_addr (_zstd_compressor_io_ptw_8_req_bits_bits_addr), .io_ptw_8_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_8_req_bits_bits_need_gpa), .io_ptw_8_resp_valid (_ptw_io_requestor_8_resp_valid), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_ae_ptw (_ptw_io_requestor_8_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_ae_final (_ptw_io_requestor_8_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pf (_ptw_io_requestor_8_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gf (_ptw_io_requestor_8_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hr (_ptw_io_requestor_8_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hw (_ptw_io_requestor_8_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_hx (_ptw_io_requestor_8_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_reserved_for_future (_ptw_io_requestor_8_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_ppn (_ptw_io_requestor_8_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_reserved_for_software (_ptw_io_requestor_8_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_d (_ptw_io_requestor_8_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_a (_ptw_io_requestor_8_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_g (_ptw_io_requestor_8_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_u (_ptw_io_requestor_8_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_x (_ptw_io_requestor_8_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_w (_ptw_io_requestor_8_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_r (_ptw_io_requestor_8_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_pte_v (_ptw_io_requestor_8_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_level (_ptw_io_requestor_8_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_homogeneous (_ptw_io_requestor_8_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_valid (_ptw_io_requestor_8_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_bits (_ptw_io_requestor_8_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_8_resp_bits_gpa_is_pte (_ptw_io_requestor_8_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_8_ptbr_mode (_ptw_io_requestor_8_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_8_ptbr_ppn (_ptw_io_requestor_8_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_8_status_debug (_ptw_io_requestor_8_status_debug), // @[PTW.scala:802:19] .io_ptw_8_status_cease (_ptw_io_requestor_8_status_cease), // @[PTW.scala:802:19] .io_ptw_8_status_wfi (_ptw_io_requestor_8_status_wfi), // @[PTW.scala:802:19] .io_ptw_8_status_isa (_ptw_io_requestor_8_status_isa), // @[PTW.scala:802:19] .io_ptw_8_status_dprv (_ptw_io_requestor_8_status_dprv), // @[PTW.scala:802:19] .io_ptw_8_status_dv (_ptw_io_requestor_8_status_dv), // @[PTW.scala:802:19] .io_ptw_8_status_prv (_ptw_io_requestor_8_status_prv), // @[PTW.scala:802:19] .io_ptw_8_status_v (_ptw_io_requestor_8_status_v), // @[PTW.scala:802:19] .io_ptw_8_status_mpv (_ptw_io_requestor_8_status_mpv), // @[PTW.scala:802:19] .io_ptw_8_status_gva (_ptw_io_requestor_8_status_gva), // @[PTW.scala:802:19] .io_ptw_8_status_tsr (_ptw_io_requestor_8_status_tsr), // @[PTW.scala:802:19] .io_ptw_8_status_tw (_ptw_io_requestor_8_status_tw), // @[PTW.scala:802:19] .io_ptw_8_status_tvm (_ptw_io_requestor_8_status_tvm), // @[PTW.scala:802:19] .io_ptw_8_status_mxr (_ptw_io_requestor_8_status_mxr), // @[PTW.scala:802:19] .io_ptw_8_status_sum (_ptw_io_requestor_8_status_sum), // @[PTW.scala:802:19] .io_ptw_8_status_mprv (_ptw_io_requestor_8_status_mprv), // @[PTW.scala:802:19] .io_ptw_8_status_fs (_ptw_io_requestor_8_status_fs), // @[PTW.scala:802:19] .io_ptw_8_status_mpp (_ptw_io_requestor_8_status_mpp), // @[PTW.scala:802:19] .io_ptw_8_status_spp (_ptw_io_requestor_8_status_spp), // @[PTW.scala:802:19] .io_ptw_8_status_mpie (_ptw_io_requestor_8_status_mpie), // @[PTW.scala:802:19] .io_ptw_8_status_spie (_ptw_io_requestor_8_status_spie), // @[PTW.scala:802:19] .io_ptw_8_status_mie (_ptw_io_requestor_8_status_mie), // @[PTW.scala:802:19] .io_ptw_8_status_sie (_ptw_io_requestor_8_status_sie), // @[PTW.scala:802:19] .io_ptw_8_hstatus_spvp (_ptw_io_requestor_8_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_8_hstatus_spv (_ptw_io_requestor_8_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_8_hstatus_gva (_ptw_io_requestor_8_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_8_gstatus_debug (_ptw_io_requestor_8_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_8_gstatus_cease (_ptw_io_requestor_8_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_8_gstatus_wfi (_ptw_io_requestor_8_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_8_gstatus_isa (_ptw_io_requestor_8_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_8_gstatus_dprv (_ptw_io_requestor_8_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_dv (_ptw_io_requestor_8_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_prv (_ptw_io_requestor_8_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_v (_ptw_io_requestor_8_gstatus_v), // @[PTW.scala:802:19] .io_ptw_8_gstatus_zero2 (_ptw_io_requestor_8_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpv (_ptw_io_requestor_8_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_gva (_ptw_io_requestor_8_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mbe (_ptw_io_requestor_8_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sbe (_ptw_io_requestor_8_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sxl (_ptw_io_requestor_8_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_8_gstatus_zero1 (_ptw_io_requestor_8_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tsr (_ptw_io_requestor_8_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tw (_ptw_io_requestor_8_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_8_gstatus_tvm (_ptw_io_requestor_8_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mxr (_ptw_io_requestor_8_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sum (_ptw_io_requestor_8_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mprv (_ptw_io_requestor_8_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_8_gstatus_fs (_ptw_io_requestor_8_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpp (_ptw_io_requestor_8_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_8_gstatus_vs (_ptw_io_requestor_8_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_8_gstatus_spp (_ptw_io_requestor_8_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mpie (_ptw_io_requestor_8_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_ube (_ptw_io_requestor_8_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_8_gstatus_spie (_ptw_io_requestor_8_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_upie (_ptw_io_requestor_8_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_mie (_ptw_io_requestor_8_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_hie (_ptw_io_requestor_8_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_sie (_ptw_io_requestor_8_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_8_gstatus_uie (_ptw_io_requestor_8_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_l (_ptw_io_requestor_8_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_a (_ptw_io_requestor_8_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_x (_ptw_io_requestor_8_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_w (_ptw_io_requestor_8_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_cfg_r (_ptw_io_requestor_8_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_addr (_ptw_io_requestor_8_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_0_mask (_ptw_io_requestor_8_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_l (_ptw_io_requestor_8_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_a (_ptw_io_requestor_8_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_x (_ptw_io_requestor_8_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_w (_ptw_io_requestor_8_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_cfg_r (_ptw_io_requestor_8_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_addr (_ptw_io_requestor_8_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_1_mask (_ptw_io_requestor_8_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_l (_ptw_io_requestor_8_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_a (_ptw_io_requestor_8_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_x (_ptw_io_requestor_8_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_w (_ptw_io_requestor_8_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_cfg_r (_ptw_io_requestor_8_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_addr (_ptw_io_requestor_8_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_2_mask (_ptw_io_requestor_8_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_l (_ptw_io_requestor_8_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_a (_ptw_io_requestor_8_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_x (_ptw_io_requestor_8_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_w (_ptw_io_requestor_8_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_cfg_r (_ptw_io_requestor_8_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_addr (_ptw_io_requestor_8_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_3_mask (_ptw_io_requestor_8_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_l (_ptw_io_requestor_8_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_a (_ptw_io_requestor_8_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_x (_ptw_io_requestor_8_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_w (_ptw_io_requestor_8_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_cfg_r (_ptw_io_requestor_8_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_addr (_ptw_io_requestor_8_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_4_mask (_ptw_io_requestor_8_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_l (_ptw_io_requestor_8_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_a (_ptw_io_requestor_8_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_x (_ptw_io_requestor_8_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_w (_ptw_io_requestor_8_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_cfg_r (_ptw_io_requestor_8_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_addr (_ptw_io_requestor_8_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_5_mask (_ptw_io_requestor_8_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_l (_ptw_io_requestor_8_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_a (_ptw_io_requestor_8_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_x (_ptw_io_requestor_8_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_w (_ptw_io_requestor_8_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_cfg_r (_ptw_io_requestor_8_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_addr (_ptw_io_requestor_8_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_6_mask (_ptw_io_requestor_8_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_l (_ptw_io_requestor_8_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_a (_ptw_io_requestor_8_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_x (_ptw_io_requestor_8_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_w (_ptw_io_requestor_8_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_cfg_r (_ptw_io_requestor_8_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_addr (_ptw_io_requestor_8_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_8_pmp_7_mask (_ptw_io_requestor_8_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_ren (_ptw_io_requestor_8_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_wen (_ptw_io_requestor_8_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_wdata (_ptw_io_requestor_8_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_0_value (_ptw_io_requestor_8_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_ren (_ptw_io_requestor_8_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_wen (_ptw_io_requestor_8_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_wdata (_ptw_io_requestor_8_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_1_value (_ptw_io_requestor_8_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_ren (_ptw_io_requestor_8_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_wen (_ptw_io_requestor_8_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_wdata (_ptw_io_requestor_8_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_2_value (_ptw_io_requestor_8_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_ren (_ptw_io_requestor_8_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_wen (_ptw_io_requestor_8_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_wdata (_ptw_io_requestor_8_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_8_customCSRs_csrs_3_value (_ptw_io_requestor_8_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_9_req_ready (_ptw_io_requestor_9_req_ready), // @[PTW.scala:802:19] .io_ptw_9_req_valid (_zstd_compressor_io_ptw_9_req_valid), .io_ptw_9_req_bits_bits_addr (_zstd_compressor_io_ptw_9_req_bits_bits_addr), .io_ptw_9_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_9_req_bits_bits_need_gpa), .io_ptw_9_resp_valid (_ptw_io_requestor_9_resp_valid), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_ae_ptw (_ptw_io_requestor_9_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_ae_final (_ptw_io_requestor_9_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pf (_ptw_io_requestor_9_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gf (_ptw_io_requestor_9_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hr (_ptw_io_requestor_9_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hw (_ptw_io_requestor_9_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_hx (_ptw_io_requestor_9_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_reserved_for_future (_ptw_io_requestor_9_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_ppn (_ptw_io_requestor_9_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_reserved_for_software (_ptw_io_requestor_9_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_d (_ptw_io_requestor_9_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_a (_ptw_io_requestor_9_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_g (_ptw_io_requestor_9_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_u (_ptw_io_requestor_9_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_x (_ptw_io_requestor_9_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_w (_ptw_io_requestor_9_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_r (_ptw_io_requestor_9_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_pte_v (_ptw_io_requestor_9_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_level (_ptw_io_requestor_9_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_homogeneous (_ptw_io_requestor_9_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_valid (_ptw_io_requestor_9_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_bits (_ptw_io_requestor_9_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_9_resp_bits_gpa_is_pte (_ptw_io_requestor_9_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_9_ptbr_mode (_ptw_io_requestor_9_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_9_ptbr_ppn (_ptw_io_requestor_9_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_9_status_debug (_ptw_io_requestor_9_status_debug), // @[PTW.scala:802:19] .io_ptw_9_status_cease (_ptw_io_requestor_9_status_cease), // @[PTW.scala:802:19] .io_ptw_9_status_wfi (_ptw_io_requestor_9_status_wfi), // @[PTW.scala:802:19] .io_ptw_9_status_isa (_ptw_io_requestor_9_status_isa), // @[PTW.scala:802:19] .io_ptw_9_status_dprv (_ptw_io_requestor_9_status_dprv), // @[PTW.scala:802:19] .io_ptw_9_status_dv (_ptw_io_requestor_9_status_dv), // @[PTW.scala:802:19] .io_ptw_9_status_prv (_ptw_io_requestor_9_status_prv), // @[PTW.scala:802:19] .io_ptw_9_status_v (_ptw_io_requestor_9_status_v), // @[PTW.scala:802:19] .io_ptw_9_status_mpv (_ptw_io_requestor_9_status_mpv), // @[PTW.scala:802:19] .io_ptw_9_status_gva (_ptw_io_requestor_9_status_gva), // @[PTW.scala:802:19] .io_ptw_9_status_tsr (_ptw_io_requestor_9_status_tsr), // @[PTW.scala:802:19] .io_ptw_9_status_tw (_ptw_io_requestor_9_status_tw), // @[PTW.scala:802:19] .io_ptw_9_status_tvm (_ptw_io_requestor_9_status_tvm), // @[PTW.scala:802:19] .io_ptw_9_status_mxr (_ptw_io_requestor_9_status_mxr), // @[PTW.scala:802:19] .io_ptw_9_status_sum (_ptw_io_requestor_9_status_sum), // @[PTW.scala:802:19] .io_ptw_9_status_mprv (_ptw_io_requestor_9_status_mprv), // @[PTW.scala:802:19] .io_ptw_9_status_fs (_ptw_io_requestor_9_status_fs), // @[PTW.scala:802:19] .io_ptw_9_status_mpp (_ptw_io_requestor_9_status_mpp), // @[PTW.scala:802:19] .io_ptw_9_status_spp (_ptw_io_requestor_9_status_spp), // @[PTW.scala:802:19] .io_ptw_9_status_mpie (_ptw_io_requestor_9_status_mpie), // @[PTW.scala:802:19] .io_ptw_9_status_spie (_ptw_io_requestor_9_status_spie), // @[PTW.scala:802:19] .io_ptw_9_status_mie (_ptw_io_requestor_9_status_mie), // @[PTW.scala:802:19] .io_ptw_9_status_sie (_ptw_io_requestor_9_status_sie), // @[PTW.scala:802:19] .io_ptw_9_hstatus_spvp (_ptw_io_requestor_9_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_9_hstatus_spv (_ptw_io_requestor_9_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_9_hstatus_gva (_ptw_io_requestor_9_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_9_gstatus_debug (_ptw_io_requestor_9_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_9_gstatus_cease (_ptw_io_requestor_9_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_9_gstatus_wfi (_ptw_io_requestor_9_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_9_gstatus_isa (_ptw_io_requestor_9_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_9_gstatus_dprv (_ptw_io_requestor_9_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_dv (_ptw_io_requestor_9_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_prv (_ptw_io_requestor_9_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_v (_ptw_io_requestor_9_gstatus_v), // @[PTW.scala:802:19] .io_ptw_9_gstatus_zero2 (_ptw_io_requestor_9_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpv (_ptw_io_requestor_9_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_gva (_ptw_io_requestor_9_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mbe (_ptw_io_requestor_9_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sbe (_ptw_io_requestor_9_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sxl (_ptw_io_requestor_9_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_9_gstatus_zero1 (_ptw_io_requestor_9_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tsr (_ptw_io_requestor_9_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tw (_ptw_io_requestor_9_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_9_gstatus_tvm (_ptw_io_requestor_9_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mxr (_ptw_io_requestor_9_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sum (_ptw_io_requestor_9_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mprv (_ptw_io_requestor_9_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_9_gstatus_fs (_ptw_io_requestor_9_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpp (_ptw_io_requestor_9_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_9_gstatus_vs (_ptw_io_requestor_9_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_9_gstatus_spp (_ptw_io_requestor_9_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mpie (_ptw_io_requestor_9_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_ube (_ptw_io_requestor_9_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_9_gstatus_spie (_ptw_io_requestor_9_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_upie (_ptw_io_requestor_9_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_mie (_ptw_io_requestor_9_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_hie (_ptw_io_requestor_9_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_sie (_ptw_io_requestor_9_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_9_gstatus_uie (_ptw_io_requestor_9_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_l (_ptw_io_requestor_9_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_a (_ptw_io_requestor_9_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_x (_ptw_io_requestor_9_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_w (_ptw_io_requestor_9_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_cfg_r (_ptw_io_requestor_9_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_addr (_ptw_io_requestor_9_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_0_mask (_ptw_io_requestor_9_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_l (_ptw_io_requestor_9_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_a (_ptw_io_requestor_9_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_x (_ptw_io_requestor_9_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_w (_ptw_io_requestor_9_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_cfg_r (_ptw_io_requestor_9_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_addr (_ptw_io_requestor_9_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_1_mask (_ptw_io_requestor_9_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_l (_ptw_io_requestor_9_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_a (_ptw_io_requestor_9_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_x (_ptw_io_requestor_9_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_w (_ptw_io_requestor_9_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_cfg_r (_ptw_io_requestor_9_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_addr (_ptw_io_requestor_9_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_2_mask (_ptw_io_requestor_9_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_l (_ptw_io_requestor_9_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_a (_ptw_io_requestor_9_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_x (_ptw_io_requestor_9_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_w (_ptw_io_requestor_9_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_cfg_r (_ptw_io_requestor_9_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_addr (_ptw_io_requestor_9_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_3_mask (_ptw_io_requestor_9_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_l (_ptw_io_requestor_9_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_a (_ptw_io_requestor_9_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_x (_ptw_io_requestor_9_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_w (_ptw_io_requestor_9_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_cfg_r (_ptw_io_requestor_9_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_addr (_ptw_io_requestor_9_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_4_mask (_ptw_io_requestor_9_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_l (_ptw_io_requestor_9_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_a (_ptw_io_requestor_9_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_x (_ptw_io_requestor_9_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_w (_ptw_io_requestor_9_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_cfg_r (_ptw_io_requestor_9_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_addr (_ptw_io_requestor_9_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_5_mask (_ptw_io_requestor_9_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_l (_ptw_io_requestor_9_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_a (_ptw_io_requestor_9_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_x (_ptw_io_requestor_9_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_w (_ptw_io_requestor_9_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_cfg_r (_ptw_io_requestor_9_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_addr (_ptw_io_requestor_9_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_6_mask (_ptw_io_requestor_9_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_l (_ptw_io_requestor_9_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_a (_ptw_io_requestor_9_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_x (_ptw_io_requestor_9_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_w (_ptw_io_requestor_9_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_cfg_r (_ptw_io_requestor_9_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_addr (_ptw_io_requestor_9_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_9_pmp_7_mask (_ptw_io_requestor_9_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_ren (_ptw_io_requestor_9_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_wen (_ptw_io_requestor_9_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_wdata (_ptw_io_requestor_9_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_0_value (_ptw_io_requestor_9_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_ren (_ptw_io_requestor_9_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_wen (_ptw_io_requestor_9_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_wdata (_ptw_io_requestor_9_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_1_value (_ptw_io_requestor_9_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_ren (_ptw_io_requestor_9_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_wen (_ptw_io_requestor_9_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_wdata (_ptw_io_requestor_9_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_2_value (_ptw_io_requestor_9_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_ren (_ptw_io_requestor_9_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_wen (_ptw_io_requestor_9_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_wdata (_ptw_io_requestor_9_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_9_customCSRs_csrs_3_value (_ptw_io_requestor_9_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_10_req_ready (_ptw_io_requestor_10_req_ready), // @[PTW.scala:802:19] .io_ptw_10_req_valid (_zstd_compressor_io_ptw_10_req_valid), .io_ptw_10_req_bits_bits_addr (_zstd_compressor_io_ptw_10_req_bits_bits_addr), .io_ptw_10_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_10_req_bits_bits_need_gpa), .io_ptw_10_resp_valid (_ptw_io_requestor_10_resp_valid), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_ae_ptw (_ptw_io_requestor_10_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_ae_final (_ptw_io_requestor_10_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pf (_ptw_io_requestor_10_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gf (_ptw_io_requestor_10_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hr (_ptw_io_requestor_10_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hw (_ptw_io_requestor_10_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_hx (_ptw_io_requestor_10_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_reserved_for_future (_ptw_io_requestor_10_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_ppn (_ptw_io_requestor_10_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_reserved_for_software (_ptw_io_requestor_10_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_d (_ptw_io_requestor_10_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_a (_ptw_io_requestor_10_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_g (_ptw_io_requestor_10_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_u (_ptw_io_requestor_10_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_x (_ptw_io_requestor_10_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_w (_ptw_io_requestor_10_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_r (_ptw_io_requestor_10_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_pte_v (_ptw_io_requestor_10_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_level (_ptw_io_requestor_10_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_homogeneous (_ptw_io_requestor_10_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_valid (_ptw_io_requestor_10_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_bits (_ptw_io_requestor_10_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_10_resp_bits_gpa_is_pte (_ptw_io_requestor_10_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_10_ptbr_mode (_ptw_io_requestor_10_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_10_ptbr_ppn (_ptw_io_requestor_10_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_10_status_debug (_ptw_io_requestor_10_status_debug), // @[PTW.scala:802:19] .io_ptw_10_status_cease (_ptw_io_requestor_10_status_cease), // @[PTW.scala:802:19] .io_ptw_10_status_wfi (_ptw_io_requestor_10_status_wfi), // @[PTW.scala:802:19] .io_ptw_10_status_isa (_ptw_io_requestor_10_status_isa), // @[PTW.scala:802:19] .io_ptw_10_status_dprv (_ptw_io_requestor_10_status_dprv), // @[PTW.scala:802:19] .io_ptw_10_status_dv (_ptw_io_requestor_10_status_dv), // @[PTW.scala:802:19] .io_ptw_10_status_prv (_ptw_io_requestor_10_status_prv), // @[PTW.scala:802:19] .io_ptw_10_status_v (_ptw_io_requestor_10_status_v), // @[PTW.scala:802:19] .io_ptw_10_status_mpv (_ptw_io_requestor_10_status_mpv), // @[PTW.scala:802:19] .io_ptw_10_status_gva (_ptw_io_requestor_10_status_gva), // @[PTW.scala:802:19] .io_ptw_10_status_tsr (_ptw_io_requestor_10_status_tsr), // @[PTW.scala:802:19] .io_ptw_10_status_tw (_ptw_io_requestor_10_status_tw), // @[PTW.scala:802:19] .io_ptw_10_status_tvm (_ptw_io_requestor_10_status_tvm), // @[PTW.scala:802:19] .io_ptw_10_status_mxr (_ptw_io_requestor_10_status_mxr), // @[PTW.scala:802:19] .io_ptw_10_status_sum (_ptw_io_requestor_10_status_sum), // @[PTW.scala:802:19] .io_ptw_10_status_mprv (_ptw_io_requestor_10_status_mprv), // @[PTW.scala:802:19] .io_ptw_10_status_fs (_ptw_io_requestor_10_status_fs), // @[PTW.scala:802:19] .io_ptw_10_status_mpp (_ptw_io_requestor_10_status_mpp), // @[PTW.scala:802:19] .io_ptw_10_status_spp (_ptw_io_requestor_10_status_spp), // @[PTW.scala:802:19] .io_ptw_10_status_mpie (_ptw_io_requestor_10_status_mpie), // @[PTW.scala:802:19] .io_ptw_10_status_spie (_ptw_io_requestor_10_status_spie), // @[PTW.scala:802:19] .io_ptw_10_status_mie (_ptw_io_requestor_10_status_mie), // @[PTW.scala:802:19] .io_ptw_10_status_sie (_ptw_io_requestor_10_status_sie), // @[PTW.scala:802:19] .io_ptw_10_hstatus_spvp (_ptw_io_requestor_10_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_10_hstatus_spv (_ptw_io_requestor_10_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_10_hstatus_gva (_ptw_io_requestor_10_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_10_gstatus_debug (_ptw_io_requestor_10_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_10_gstatus_cease (_ptw_io_requestor_10_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_10_gstatus_wfi (_ptw_io_requestor_10_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_10_gstatus_isa (_ptw_io_requestor_10_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_10_gstatus_dprv (_ptw_io_requestor_10_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_dv (_ptw_io_requestor_10_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_prv (_ptw_io_requestor_10_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_v (_ptw_io_requestor_10_gstatus_v), // @[PTW.scala:802:19] .io_ptw_10_gstatus_zero2 (_ptw_io_requestor_10_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpv (_ptw_io_requestor_10_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_gva (_ptw_io_requestor_10_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mbe (_ptw_io_requestor_10_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sbe (_ptw_io_requestor_10_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sxl (_ptw_io_requestor_10_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_10_gstatus_zero1 (_ptw_io_requestor_10_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tsr (_ptw_io_requestor_10_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tw (_ptw_io_requestor_10_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_10_gstatus_tvm (_ptw_io_requestor_10_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mxr (_ptw_io_requestor_10_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sum (_ptw_io_requestor_10_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mprv (_ptw_io_requestor_10_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_10_gstatus_fs (_ptw_io_requestor_10_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpp (_ptw_io_requestor_10_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_10_gstatus_vs (_ptw_io_requestor_10_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_10_gstatus_spp (_ptw_io_requestor_10_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mpie (_ptw_io_requestor_10_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_ube (_ptw_io_requestor_10_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_10_gstatus_spie (_ptw_io_requestor_10_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_upie (_ptw_io_requestor_10_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_mie (_ptw_io_requestor_10_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_hie (_ptw_io_requestor_10_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_sie (_ptw_io_requestor_10_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_10_gstatus_uie (_ptw_io_requestor_10_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_l (_ptw_io_requestor_10_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_a (_ptw_io_requestor_10_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_x (_ptw_io_requestor_10_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_w (_ptw_io_requestor_10_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_cfg_r (_ptw_io_requestor_10_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_addr (_ptw_io_requestor_10_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_0_mask (_ptw_io_requestor_10_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_l (_ptw_io_requestor_10_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_a (_ptw_io_requestor_10_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_x (_ptw_io_requestor_10_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_w (_ptw_io_requestor_10_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_cfg_r (_ptw_io_requestor_10_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_addr (_ptw_io_requestor_10_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_1_mask (_ptw_io_requestor_10_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_l (_ptw_io_requestor_10_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_a (_ptw_io_requestor_10_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_x (_ptw_io_requestor_10_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_w (_ptw_io_requestor_10_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_cfg_r (_ptw_io_requestor_10_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_addr (_ptw_io_requestor_10_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_2_mask (_ptw_io_requestor_10_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_l (_ptw_io_requestor_10_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_a (_ptw_io_requestor_10_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_x (_ptw_io_requestor_10_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_w (_ptw_io_requestor_10_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_cfg_r (_ptw_io_requestor_10_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_addr (_ptw_io_requestor_10_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_3_mask (_ptw_io_requestor_10_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_l (_ptw_io_requestor_10_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_a (_ptw_io_requestor_10_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_x (_ptw_io_requestor_10_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_w (_ptw_io_requestor_10_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_cfg_r (_ptw_io_requestor_10_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_addr (_ptw_io_requestor_10_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_4_mask (_ptw_io_requestor_10_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_l (_ptw_io_requestor_10_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_a (_ptw_io_requestor_10_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_x (_ptw_io_requestor_10_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_w (_ptw_io_requestor_10_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_cfg_r (_ptw_io_requestor_10_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_addr (_ptw_io_requestor_10_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_5_mask (_ptw_io_requestor_10_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_l (_ptw_io_requestor_10_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_a (_ptw_io_requestor_10_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_x (_ptw_io_requestor_10_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_w (_ptw_io_requestor_10_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_cfg_r (_ptw_io_requestor_10_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_addr (_ptw_io_requestor_10_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_6_mask (_ptw_io_requestor_10_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_l (_ptw_io_requestor_10_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_a (_ptw_io_requestor_10_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_x (_ptw_io_requestor_10_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_w (_ptw_io_requestor_10_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_cfg_r (_ptw_io_requestor_10_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_addr (_ptw_io_requestor_10_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_10_pmp_7_mask (_ptw_io_requestor_10_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_ren (_ptw_io_requestor_10_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_wen (_ptw_io_requestor_10_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_wdata (_ptw_io_requestor_10_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_0_value (_ptw_io_requestor_10_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_ren (_ptw_io_requestor_10_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_wen (_ptw_io_requestor_10_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_wdata (_ptw_io_requestor_10_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_1_value (_ptw_io_requestor_10_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_ren (_ptw_io_requestor_10_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_wen (_ptw_io_requestor_10_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_wdata (_ptw_io_requestor_10_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_2_value (_ptw_io_requestor_10_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_ren (_ptw_io_requestor_10_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_wen (_ptw_io_requestor_10_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_wdata (_ptw_io_requestor_10_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_10_customCSRs_csrs_3_value (_ptw_io_requestor_10_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_11_req_ready (_ptw_io_requestor_11_req_ready), // @[PTW.scala:802:19] .io_ptw_11_req_valid (_zstd_compressor_io_ptw_11_req_valid), .io_ptw_11_req_bits_bits_addr (_zstd_compressor_io_ptw_11_req_bits_bits_addr), .io_ptw_11_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_11_req_bits_bits_need_gpa), .io_ptw_11_resp_valid (_ptw_io_requestor_11_resp_valid), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_ae_ptw (_ptw_io_requestor_11_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_ae_final (_ptw_io_requestor_11_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pf (_ptw_io_requestor_11_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gf (_ptw_io_requestor_11_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hr (_ptw_io_requestor_11_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hw (_ptw_io_requestor_11_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_hx (_ptw_io_requestor_11_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_reserved_for_future (_ptw_io_requestor_11_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_ppn (_ptw_io_requestor_11_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_reserved_for_software (_ptw_io_requestor_11_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_d (_ptw_io_requestor_11_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_a (_ptw_io_requestor_11_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_g (_ptw_io_requestor_11_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_u (_ptw_io_requestor_11_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_x (_ptw_io_requestor_11_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_w (_ptw_io_requestor_11_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_r (_ptw_io_requestor_11_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_pte_v (_ptw_io_requestor_11_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_level (_ptw_io_requestor_11_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_homogeneous (_ptw_io_requestor_11_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_valid (_ptw_io_requestor_11_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_bits (_ptw_io_requestor_11_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_11_resp_bits_gpa_is_pte (_ptw_io_requestor_11_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_11_ptbr_mode (_ptw_io_requestor_11_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_11_ptbr_ppn (_ptw_io_requestor_11_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_11_status_debug (_ptw_io_requestor_11_status_debug), // @[PTW.scala:802:19] .io_ptw_11_status_cease (_ptw_io_requestor_11_status_cease), // @[PTW.scala:802:19] .io_ptw_11_status_wfi (_ptw_io_requestor_11_status_wfi), // @[PTW.scala:802:19] .io_ptw_11_status_isa (_ptw_io_requestor_11_status_isa), // @[PTW.scala:802:19] .io_ptw_11_status_dprv (_ptw_io_requestor_11_status_dprv), // @[PTW.scala:802:19] .io_ptw_11_status_dv (_ptw_io_requestor_11_status_dv), // @[PTW.scala:802:19] .io_ptw_11_status_prv (_ptw_io_requestor_11_status_prv), // @[PTW.scala:802:19] .io_ptw_11_status_v (_ptw_io_requestor_11_status_v), // @[PTW.scala:802:19] .io_ptw_11_status_mpv (_ptw_io_requestor_11_status_mpv), // @[PTW.scala:802:19] .io_ptw_11_status_gva (_ptw_io_requestor_11_status_gva), // @[PTW.scala:802:19] .io_ptw_11_status_tsr (_ptw_io_requestor_11_status_tsr), // @[PTW.scala:802:19] .io_ptw_11_status_tw (_ptw_io_requestor_11_status_tw), // @[PTW.scala:802:19] .io_ptw_11_status_tvm (_ptw_io_requestor_11_status_tvm), // @[PTW.scala:802:19] .io_ptw_11_status_mxr (_ptw_io_requestor_11_status_mxr), // @[PTW.scala:802:19] .io_ptw_11_status_sum (_ptw_io_requestor_11_status_sum), // @[PTW.scala:802:19] .io_ptw_11_status_mprv (_ptw_io_requestor_11_status_mprv), // @[PTW.scala:802:19] .io_ptw_11_status_fs (_ptw_io_requestor_11_status_fs), // @[PTW.scala:802:19] .io_ptw_11_status_mpp (_ptw_io_requestor_11_status_mpp), // @[PTW.scala:802:19] .io_ptw_11_status_spp (_ptw_io_requestor_11_status_spp), // @[PTW.scala:802:19] .io_ptw_11_status_mpie (_ptw_io_requestor_11_status_mpie), // @[PTW.scala:802:19] .io_ptw_11_status_spie (_ptw_io_requestor_11_status_spie), // @[PTW.scala:802:19] .io_ptw_11_status_mie (_ptw_io_requestor_11_status_mie), // @[PTW.scala:802:19] .io_ptw_11_status_sie (_ptw_io_requestor_11_status_sie), // @[PTW.scala:802:19] .io_ptw_11_hstatus_spvp (_ptw_io_requestor_11_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_11_hstatus_spv (_ptw_io_requestor_11_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_11_hstatus_gva (_ptw_io_requestor_11_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_11_gstatus_debug (_ptw_io_requestor_11_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_11_gstatus_cease (_ptw_io_requestor_11_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_11_gstatus_wfi (_ptw_io_requestor_11_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_11_gstatus_isa (_ptw_io_requestor_11_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_11_gstatus_dprv (_ptw_io_requestor_11_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_dv (_ptw_io_requestor_11_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_prv (_ptw_io_requestor_11_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_v (_ptw_io_requestor_11_gstatus_v), // @[PTW.scala:802:19] .io_ptw_11_gstatus_zero2 (_ptw_io_requestor_11_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpv (_ptw_io_requestor_11_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_gva (_ptw_io_requestor_11_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mbe (_ptw_io_requestor_11_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sbe (_ptw_io_requestor_11_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sxl (_ptw_io_requestor_11_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_11_gstatus_zero1 (_ptw_io_requestor_11_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tsr (_ptw_io_requestor_11_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tw (_ptw_io_requestor_11_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_11_gstatus_tvm (_ptw_io_requestor_11_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mxr (_ptw_io_requestor_11_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sum (_ptw_io_requestor_11_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mprv (_ptw_io_requestor_11_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_11_gstatus_fs (_ptw_io_requestor_11_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpp (_ptw_io_requestor_11_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_11_gstatus_vs (_ptw_io_requestor_11_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_11_gstatus_spp (_ptw_io_requestor_11_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mpie (_ptw_io_requestor_11_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_ube (_ptw_io_requestor_11_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_11_gstatus_spie (_ptw_io_requestor_11_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_upie (_ptw_io_requestor_11_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_mie (_ptw_io_requestor_11_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_hie (_ptw_io_requestor_11_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_sie (_ptw_io_requestor_11_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_11_gstatus_uie (_ptw_io_requestor_11_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_l (_ptw_io_requestor_11_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_a (_ptw_io_requestor_11_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_x (_ptw_io_requestor_11_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_w (_ptw_io_requestor_11_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_cfg_r (_ptw_io_requestor_11_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_addr (_ptw_io_requestor_11_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_0_mask (_ptw_io_requestor_11_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_l (_ptw_io_requestor_11_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_a (_ptw_io_requestor_11_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_x (_ptw_io_requestor_11_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_w (_ptw_io_requestor_11_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_cfg_r (_ptw_io_requestor_11_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_addr (_ptw_io_requestor_11_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_1_mask (_ptw_io_requestor_11_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_l (_ptw_io_requestor_11_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_a (_ptw_io_requestor_11_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_x (_ptw_io_requestor_11_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_w (_ptw_io_requestor_11_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_cfg_r (_ptw_io_requestor_11_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_addr (_ptw_io_requestor_11_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_2_mask (_ptw_io_requestor_11_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_l (_ptw_io_requestor_11_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_a (_ptw_io_requestor_11_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_x (_ptw_io_requestor_11_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_w (_ptw_io_requestor_11_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_cfg_r (_ptw_io_requestor_11_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_addr (_ptw_io_requestor_11_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_3_mask (_ptw_io_requestor_11_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_l (_ptw_io_requestor_11_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_a (_ptw_io_requestor_11_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_x (_ptw_io_requestor_11_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_w (_ptw_io_requestor_11_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_cfg_r (_ptw_io_requestor_11_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_addr (_ptw_io_requestor_11_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_4_mask (_ptw_io_requestor_11_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_l (_ptw_io_requestor_11_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_a (_ptw_io_requestor_11_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_x (_ptw_io_requestor_11_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_w (_ptw_io_requestor_11_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_cfg_r (_ptw_io_requestor_11_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_addr (_ptw_io_requestor_11_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_5_mask (_ptw_io_requestor_11_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_l (_ptw_io_requestor_11_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_a (_ptw_io_requestor_11_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_x (_ptw_io_requestor_11_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_w (_ptw_io_requestor_11_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_cfg_r (_ptw_io_requestor_11_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_addr (_ptw_io_requestor_11_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_6_mask (_ptw_io_requestor_11_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_l (_ptw_io_requestor_11_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_a (_ptw_io_requestor_11_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_x (_ptw_io_requestor_11_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_w (_ptw_io_requestor_11_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_cfg_r (_ptw_io_requestor_11_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_addr (_ptw_io_requestor_11_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_11_pmp_7_mask (_ptw_io_requestor_11_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_ren (_ptw_io_requestor_11_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_wen (_ptw_io_requestor_11_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_wdata (_ptw_io_requestor_11_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_0_value (_ptw_io_requestor_11_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_ren (_ptw_io_requestor_11_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_wen (_ptw_io_requestor_11_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_wdata (_ptw_io_requestor_11_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_1_value (_ptw_io_requestor_11_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_ren (_ptw_io_requestor_11_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_wen (_ptw_io_requestor_11_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_wdata (_ptw_io_requestor_11_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_2_value (_ptw_io_requestor_11_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_ren (_ptw_io_requestor_11_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_wen (_ptw_io_requestor_11_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_wdata (_ptw_io_requestor_11_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_11_customCSRs_csrs_3_value (_ptw_io_requestor_11_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_12_req_ready (_ptw_io_requestor_12_req_ready), // @[PTW.scala:802:19] .io_ptw_12_req_valid (_zstd_compressor_io_ptw_12_req_valid), .io_ptw_12_req_bits_bits_addr (_zstd_compressor_io_ptw_12_req_bits_bits_addr), .io_ptw_12_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_12_req_bits_bits_need_gpa), .io_ptw_12_resp_valid (_ptw_io_requestor_12_resp_valid), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_ae_ptw (_ptw_io_requestor_12_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_ae_final (_ptw_io_requestor_12_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pf (_ptw_io_requestor_12_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gf (_ptw_io_requestor_12_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hr (_ptw_io_requestor_12_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hw (_ptw_io_requestor_12_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_hx (_ptw_io_requestor_12_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_reserved_for_future (_ptw_io_requestor_12_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_ppn (_ptw_io_requestor_12_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_reserved_for_software (_ptw_io_requestor_12_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_d (_ptw_io_requestor_12_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_a (_ptw_io_requestor_12_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_g (_ptw_io_requestor_12_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_u (_ptw_io_requestor_12_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_x (_ptw_io_requestor_12_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_w (_ptw_io_requestor_12_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_r (_ptw_io_requestor_12_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_pte_v (_ptw_io_requestor_12_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_level (_ptw_io_requestor_12_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_homogeneous (_ptw_io_requestor_12_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_valid (_ptw_io_requestor_12_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_bits (_ptw_io_requestor_12_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_12_resp_bits_gpa_is_pte (_ptw_io_requestor_12_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_12_ptbr_mode (_ptw_io_requestor_12_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_12_ptbr_ppn (_ptw_io_requestor_12_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_12_status_debug (_ptw_io_requestor_12_status_debug), // @[PTW.scala:802:19] .io_ptw_12_status_cease (_ptw_io_requestor_12_status_cease), // @[PTW.scala:802:19] .io_ptw_12_status_wfi (_ptw_io_requestor_12_status_wfi), // @[PTW.scala:802:19] .io_ptw_12_status_isa (_ptw_io_requestor_12_status_isa), // @[PTW.scala:802:19] .io_ptw_12_status_dprv (_ptw_io_requestor_12_status_dprv), // @[PTW.scala:802:19] .io_ptw_12_status_dv (_ptw_io_requestor_12_status_dv), // @[PTW.scala:802:19] .io_ptw_12_status_prv (_ptw_io_requestor_12_status_prv), // @[PTW.scala:802:19] .io_ptw_12_status_v (_ptw_io_requestor_12_status_v), // @[PTW.scala:802:19] .io_ptw_12_status_mpv (_ptw_io_requestor_12_status_mpv), // @[PTW.scala:802:19] .io_ptw_12_status_gva (_ptw_io_requestor_12_status_gva), // @[PTW.scala:802:19] .io_ptw_12_status_tsr (_ptw_io_requestor_12_status_tsr), // @[PTW.scala:802:19] .io_ptw_12_status_tw (_ptw_io_requestor_12_status_tw), // @[PTW.scala:802:19] .io_ptw_12_status_tvm (_ptw_io_requestor_12_status_tvm), // @[PTW.scala:802:19] .io_ptw_12_status_mxr (_ptw_io_requestor_12_status_mxr), // @[PTW.scala:802:19] .io_ptw_12_status_sum (_ptw_io_requestor_12_status_sum), // @[PTW.scala:802:19] .io_ptw_12_status_mprv (_ptw_io_requestor_12_status_mprv), // @[PTW.scala:802:19] .io_ptw_12_status_fs (_ptw_io_requestor_12_status_fs), // @[PTW.scala:802:19] .io_ptw_12_status_mpp (_ptw_io_requestor_12_status_mpp), // @[PTW.scala:802:19] .io_ptw_12_status_spp (_ptw_io_requestor_12_status_spp), // @[PTW.scala:802:19] .io_ptw_12_status_mpie (_ptw_io_requestor_12_status_mpie), // @[PTW.scala:802:19] .io_ptw_12_status_spie (_ptw_io_requestor_12_status_spie), // @[PTW.scala:802:19] .io_ptw_12_status_mie (_ptw_io_requestor_12_status_mie), // @[PTW.scala:802:19] .io_ptw_12_status_sie (_ptw_io_requestor_12_status_sie), // @[PTW.scala:802:19] .io_ptw_12_hstatus_spvp (_ptw_io_requestor_12_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_12_hstatus_spv (_ptw_io_requestor_12_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_12_hstatus_gva (_ptw_io_requestor_12_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_12_gstatus_debug (_ptw_io_requestor_12_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_12_gstatus_cease (_ptw_io_requestor_12_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_12_gstatus_wfi (_ptw_io_requestor_12_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_12_gstatus_isa (_ptw_io_requestor_12_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_12_gstatus_dprv (_ptw_io_requestor_12_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_dv (_ptw_io_requestor_12_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_prv (_ptw_io_requestor_12_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_v (_ptw_io_requestor_12_gstatus_v), // @[PTW.scala:802:19] .io_ptw_12_gstatus_zero2 (_ptw_io_requestor_12_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpv (_ptw_io_requestor_12_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_gva (_ptw_io_requestor_12_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mbe (_ptw_io_requestor_12_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sbe (_ptw_io_requestor_12_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sxl (_ptw_io_requestor_12_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_12_gstatus_zero1 (_ptw_io_requestor_12_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tsr (_ptw_io_requestor_12_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tw (_ptw_io_requestor_12_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_12_gstatus_tvm (_ptw_io_requestor_12_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mxr (_ptw_io_requestor_12_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sum (_ptw_io_requestor_12_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mprv (_ptw_io_requestor_12_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_12_gstatus_fs (_ptw_io_requestor_12_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpp (_ptw_io_requestor_12_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_12_gstatus_vs (_ptw_io_requestor_12_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_12_gstatus_spp (_ptw_io_requestor_12_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mpie (_ptw_io_requestor_12_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_ube (_ptw_io_requestor_12_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_12_gstatus_spie (_ptw_io_requestor_12_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_upie (_ptw_io_requestor_12_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_mie (_ptw_io_requestor_12_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_hie (_ptw_io_requestor_12_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_sie (_ptw_io_requestor_12_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_12_gstatus_uie (_ptw_io_requestor_12_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_l (_ptw_io_requestor_12_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_a (_ptw_io_requestor_12_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_x (_ptw_io_requestor_12_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_w (_ptw_io_requestor_12_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_cfg_r (_ptw_io_requestor_12_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_addr (_ptw_io_requestor_12_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_0_mask (_ptw_io_requestor_12_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_l (_ptw_io_requestor_12_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_a (_ptw_io_requestor_12_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_x (_ptw_io_requestor_12_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_w (_ptw_io_requestor_12_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_cfg_r (_ptw_io_requestor_12_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_addr (_ptw_io_requestor_12_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_1_mask (_ptw_io_requestor_12_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_l (_ptw_io_requestor_12_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_a (_ptw_io_requestor_12_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_x (_ptw_io_requestor_12_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_w (_ptw_io_requestor_12_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_cfg_r (_ptw_io_requestor_12_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_addr (_ptw_io_requestor_12_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_2_mask (_ptw_io_requestor_12_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_l (_ptw_io_requestor_12_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_a (_ptw_io_requestor_12_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_x (_ptw_io_requestor_12_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_w (_ptw_io_requestor_12_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_cfg_r (_ptw_io_requestor_12_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_addr (_ptw_io_requestor_12_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_3_mask (_ptw_io_requestor_12_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_l (_ptw_io_requestor_12_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_a (_ptw_io_requestor_12_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_x (_ptw_io_requestor_12_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_w (_ptw_io_requestor_12_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_cfg_r (_ptw_io_requestor_12_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_addr (_ptw_io_requestor_12_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_4_mask (_ptw_io_requestor_12_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_l (_ptw_io_requestor_12_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_a (_ptw_io_requestor_12_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_x (_ptw_io_requestor_12_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_w (_ptw_io_requestor_12_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_cfg_r (_ptw_io_requestor_12_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_addr (_ptw_io_requestor_12_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_5_mask (_ptw_io_requestor_12_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_l (_ptw_io_requestor_12_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_a (_ptw_io_requestor_12_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_x (_ptw_io_requestor_12_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_w (_ptw_io_requestor_12_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_cfg_r (_ptw_io_requestor_12_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_addr (_ptw_io_requestor_12_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_6_mask (_ptw_io_requestor_12_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_l (_ptw_io_requestor_12_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_a (_ptw_io_requestor_12_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_x (_ptw_io_requestor_12_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_w (_ptw_io_requestor_12_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_cfg_r (_ptw_io_requestor_12_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_addr (_ptw_io_requestor_12_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_12_pmp_7_mask (_ptw_io_requestor_12_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_ren (_ptw_io_requestor_12_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_wen (_ptw_io_requestor_12_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_wdata (_ptw_io_requestor_12_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_0_value (_ptw_io_requestor_12_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_ren (_ptw_io_requestor_12_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_wen (_ptw_io_requestor_12_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_wdata (_ptw_io_requestor_12_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_1_value (_ptw_io_requestor_12_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_ren (_ptw_io_requestor_12_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_wen (_ptw_io_requestor_12_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_wdata (_ptw_io_requestor_12_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_2_value (_ptw_io_requestor_12_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_ren (_ptw_io_requestor_12_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_wen (_ptw_io_requestor_12_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_wdata (_ptw_io_requestor_12_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_12_customCSRs_csrs_3_value (_ptw_io_requestor_12_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_13_req_ready (_ptw_io_requestor_13_req_ready), // @[PTW.scala:802:19] .io_ptw_13_req_valid (_zstd_compressor_io_ptw_13_req_valid), .io_ptw_13_req_bits_bits_addr (_zstd_compressor_io_ptw_13_req_bits_bits_addr), .io_ptw_13_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_13_req_bits_bits_need_gpa), .io_ptw_13_resp_valid (_ptw_io_requestor_13_resp_valid), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_ae_ptw (_ptw_io_requestor_13_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_ae_final (_ptw_io_requestor_13_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pf (_ptw_io_requestor_13_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gf (_ptw_io_requestor_13_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hr (_ptw_io_requestor_13_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hw (_ptw_io_requestor_13_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_hx (_ptw_io_requestor_13_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_reserved_for_future (_ptw_io_requestor_13_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_ppn (_ptw_io_requestor_13_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_reserved_for_software (_ptw_io_requestor_13_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_d (_ptw_io_requestor_13_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_a (_ptw_io_requestor_13_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_g (_ptw_io_requestor_13_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_u (_ptw_io_requestor_13_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_x (_ptw_io_requestor_13_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_w (_ptw_io_requestor_13_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_r (_ptw_io_requestor_13_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_pte_v (_ptw_io_requestor_13_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_level (_ptw_io_requestor_13_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_homogeneous (_ptw_io_requestor_13_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_valid (_ptw_io_requestor_13_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_bits (_ptw_io_requestor_13_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_13_resp_bits_gpa_is_pte (_ptw_io_requestor_13_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_13_ptbr_mode (_ptw_io_requestor_13_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_13_ptbr_ppn (_ptw_io_requestor_13_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_13_status_debug (_ptw_io_requestor_13_status_debug), // @[PTW.scala:802:19] .io_ptw_13_status_cease (_ptw_io_requestor_13_status_cease), // @[PTW.scala:802:19] .io_ptw_13_status_wfi (_ptw_io_requestor_13_status_wfi), // @[PTW.scala:802:19] .io_ptw_13_status_isa (_ptw_io_requestor_13_status_isa), // @[PTW.scala:802:19] .io_ptw_13_status_dprv (_ptw_io_requestor_13_status_dprv), // @[PTW.scala:802:19] .io_ptw_13_status_dv (_ptw_io_requestor_13_status_dv), // @[PTW.scala:802:19] .io_ptw_13_status_prv (_ptw_io_requestor_13_status_prv), // @[PTW.scala:802:19] .io_ptw_13_status_v (_ptw_io_requestor_13_status_v), // @[PTW.scala:802:19] .io_ptw_13_status_mpv (_ptw_io_requestor_13_status_mpv), // @[PTW.scala:802:19] .io_ptw_13_status_gva (_ptw_io_requestor_13_status_gva), // @[PTW.scala:802:19] .io_ptw_13_status_tsr (_ptw_io_requestor_13_status_tsr), // @[PTW.scala:802:19] .io_ptw_13_status_tw (_ptw_io_requestor_13_status_tw), // @[PTW.scala:802:19] .io_ptw_13_status_tvm (_ptw_io_requestor_13_status_tvm), // @[PTW.scala:802:19] .io_ptw_13_status_mxr (_ptw_io_requestor_13_status_mxr), // @[PTW.scala:802:19] .io_ptw_13_status_sum (_ptw_io_requestor_13_status_sum), // @[PTW.scala:802:19] .io_ptw_13_status_mprv (_ptw_io_requestor_13_status_mprv), // @[PTW.scala:802:19] .io_ptw_13_status_fs (_ptw_io_requestor_13_status_fs), // @[PTW.scala:802:19] .io_ptw_13_status_mpp (_ptw_io_requestor_13_status_mpp), // @[PTW.scala:802:19] .io_ptw_13_status_spp (_ptw_io_requestor_13_status_spp), // @[PTW.scala:802:19] .io_ptw_13_status_mpie (_ptw_io_requestor_13_status_mpie), // @[PTW.scala:802:19] .io_ptw_13_status_spie (_ptw_io_requestor_13_status_spie), // @[PTW.scala:802:19] .io_ptw_13_status_mie (_ptw_io_requestor_13_status_mie), // @[PTW.scala:802:19] .io_ptw_13_status_sie (_ptw_io_requestor_13_status_sie), // @[PTW.scala:802:19] .io_ptw_13_hstatus_spvp (_ptw_io_requestor_13_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_13_hstatus_spv (_ptw_io_requestor_13_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_13_hstatus_gva (_ptw_io_requestor_13_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_13_gstatus_debug (_ptw_io_requestor_13_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_13_gstatus_cease (_ptw_io_requestor_13_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_13_gstatus_wfi (_ptw_io_requestor_13_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_13_gstatus_isa (_ptw_io_requestor_13_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_13_gstatus_dprv (_ptw_io_requestor_13_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_dv (_ptw_io_requestor_13_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_prv (_ptw_io_requestor_13_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_v (_ptw_io_requestor_13_gstatus_v), // @[PTW.scala:802:19] .io_ptw_13_gstatus_zero2 (_ptw_io_requestor_13_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpv (_ptw_io_requestor_13_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_gva (_ptw_io_requestor_13_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mbe (_ptw_io_requestor_13_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sbe (_ptw_io_requestor_13_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sxl (_ptw_io_requestor_13_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_13_gstatus_zero1 (_ptw_io_requestor_13_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tsr (_ptw_io_requestor_13_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tw (_ptw_io_requestor_13_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_13_gstatus_tvm (_ptw_io_requestor_13_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mxr (_ptw_io_requestor_13_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sum (_ptw_io_requestor_13_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mprv (_ptw_io_requestor_13_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_13_gstatus_fs (_ptw_io_requestor_13_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpp (_ptw_io_requestor_13_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_13_gstatus_vs (_ptw_io_requestor_13_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_13_gstatus_spp (_ptw_io_requestor_13_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mpie (_ptw_io_requestor_13_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_ube (_ptw_io_requestor_13_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_13_gstatus_spie (_ptw_io_requestor_13_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_upie (_ptw_io_requestor_13_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_mie (_ptw_io_requestor_13_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_hie (_ptw_io_requestor_13_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_sie (_ptw_io_requestor_13_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_13_gstatus_uie (_ptw_io_requestor_13_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_l (_ptw_io_requestor_13_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_a (_ptw_io_requestor_13_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_x (_ptw_io_requestor_13_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_w (_ptw_io_requestor_13_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_cfg_r (_ptw_io_requestor_13_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_addr (_ptw_io_requestor_13_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_0_mask (_ptw_io_requestor_13_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_l (_ptw_io_requestor_13_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_a (_ptw_io_requestor_13_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_x (_ptw_io_requestor_13_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_w (_ptw_io_requestor_13_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_cfg_r (_ptw_io_requestor_13_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_addr (_ptw_io_requestor_13_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_1_mask (_ptw_io_requestor_13_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_l (_ptw_io_requestor_13_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_a (_ptw_io_requestor_13_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_x (_ptw_io_requestor_13_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_w (_ptw_io_requestor_13_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_cfg_r (_ptw_io_requestor_13_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_addr (_ptw_io_requestor_13_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_2_mask (_ptw_io_requestor_13_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_l (_ptw_io_requestor_13_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_a (_ptw_io_requestor_13_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_x (_ptw_io_requestor_13_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_w (_ptw_io_requestor_13_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_cfg_r (_ptw_io_requestor_13_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_addr (_ptw_io_requestor_13_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_3_mask (_ptw_io_requestor_13_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_l (_ptw_io_requestor_13_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_a (_ptw_io_requestor_13_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_x (_ptw_io_requestor_13_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_w (_ptw_io_requestor_13_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_cfg_r (_ptw_io_requestor_13_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_addr (_ptw_io_requestor_13_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_4_mask (_ptw_io_requestor_13_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_l (_ptw_io_requestor_13_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_a (_ptw_io_requestor_13_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_x (_ptw_io_requestor_13_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_w (_ptw_io_requestor_13_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_cfg_r (_ptw_io_requestor_13_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_addr (_ptw_io_requestor_13_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_5_mask (_ptw_io_requestor_13_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_l (_ptw_io_requestor_13_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_a (_ptw_io_requestor_13_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_x (_ptw_io_requestor_13_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_w (_ptw_io_requestor_13_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_cfg_r (_ptw_io_requestor_13_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_addr (_ptw_io_requestor_13_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_6_mask (_ptw_io_requestor_13_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_l (_ptw_io_requestor_13_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_a (_ptw_io_requestor_13_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_x (_ptw_io_requestor_13_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_w (_ptw_io_requestor_13_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_cfg_r (_ptw_io_requestor_13_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_addr (_ptw_io_requestor_13_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_13_pmp_7_mask (_ptw_io_requestor_13_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_ren (_ptw_io_requestor_13_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_wen (_ptw_io_requestor_13_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_wdata (_ptw_io_requestor_13_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_0_value (_ptw_io_requestor_13_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_ren (_ptw_io_requestor_13_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_wen (_ptw_io_requestor_13_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_wdata (_ptw_io_requestor_13_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_1_value (_ptw_io_requestor_13_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_ren (_ptw_io_requestor_13_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_wen (_ptw_io_requestor_13_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_wdata (_ptw_io_requestor_13_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_2_value (_ptw_io_requestor_13_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_ren (_ptw_io_requestor_13_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_wen (_ptw_io_requestor_13_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_wdata (_ptw_io_requestor_13_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_13_customCSRs_csrs_3_value (_ptw_io_requestor_13_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_14_req_ready (_ptw_io_requestor_14_req_ready), // @[PTW.scala:802:19] .io_ptw_14_req_valid (_zstd_compressor_io_ptw_14_req_valid), .io_ptw_14_req_bits_bits_addr (_zstd_compressor_io_ptw_14_req_bits_bits_addr), .io_ptw_14_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_14_req_bits_bits_need_gpa), .io_ptw_14_resp_valid (_ptw_io_requestor_14_resp_valid), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_ae_ptw (_ptw_io_requestor_14_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_ae_final (_ptw_io_requestor_14_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pf (_ptw_io_requestor_14_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gf (_ptw_io_requestor_14_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hr (_ptw_io_requestor_14_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hw (_ptw_io_requestor_14_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_hx (_ptw_io_requestor_14_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_reserved_for_future (_ptw_io_requestor_14_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_ppn (_ptw_io_requestor_14_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_reserved_for_software (_ptw_io_requestor_14_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_d (_ptw_io_requestor_14_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_a (_ptw_io_requestor_14_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_g (_ptw_io_requestor_14_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_u (_ptw_io_requestor_14_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_x (_ptw_io_requestor_14_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_w (_ptw_io_requestor_14_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_r (_ptw_io_requestor_14_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_pte_v (_ptw_io_requestor_14_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_level (_ptw_io_requestor_14_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_homogeneous (_ptw_io_requestor_14_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_valid (_ptw_io_requestor_14_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_bits (_ptw_io_requestor_14_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_14_resp_bits_gpa_is_pte (_ptw_io_requestor_14_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_14_ptbr_mode (_ptw_io_requestor_14_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_14_ptbr_ppn (_ptw_io_requestor_14_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_14_status_debug (_ptw_io_requestor_14_status_debug), // @[PTW.scala:802:19] .io_ptw_14_status_cease (_ptw_io_requestor_14_status_cease), // @[PTW.scala:802:19] .io_ptw_14_status_wfi (_ptw_io_requestor_14_status_wfi), // @[PTW.scala:802:19] .io_ptw_14_status_isa (_ptw_io_requestor_14_status_isa), // @[PTW.scala:802:19] .io_ptw_14_status_dprv (_ptw_io_requestor_14_status_dprv), // @[PTW.scala:802:19] .io_ptw_14_status_dv (_ptw_io_requestor_14_status_dv), // @[PTW.scala:802:19] .io_ptw_14_status_prv (_ptw_io_requestor_14_status_prv), // @[PTW.scala:802:19] .io_ptw_14_status_v (_ptw_io_requestor_14_status_v), // @[PTW.scala:802:19] .io_ptw_14_status_mpv (_ptw_io_requestor_14_status_mpv), // @[PTW.scala:802:19] .io_ptw_14_status_gva (_ptw_io_requestor_14_status_gva), // @[PTW.scala:802:19] .io_ptw_14_status_tsr (_ptw_io_requestor_14_status_tsr), // @[PTW.scala:802:19] .io_ptw_14_status_tw (_ptw_io_requestor_14_status_tw), // @[PTW.scala:802:19] .io_ptw_14_status_tvm (_ptw_io_requestor_14_status_tvm), // @[PTW.scala:802:19] .io_ptw_14_status_mxr (_ptw_io_requestor_14_status_mxr), // @[PTW.scala:802:19] .io_ptw_14_status_sum (_ptw_io_requestor_14_status_sum), // @[PTW.scala:802:19] .io_ptw_14_status_mprv (_ptw_io_requestor_14_status_mprv), // @[PTW.scala:802:19] .io_ptw_14_status_fs (_ptw_io_requestor_14_status_fs), // @[PTW.scala:802:19] .io_ptw_14_status_mpp (_ptw_io_requestor_14_status_mpp), // @[PTW.scala:802:19] .io_ptw_14_status_spp (_ptw_io_requestor_14_status_spp), // @[PTW.scala:802:19] .io_ptw_14_status_mpie (_ptw_io_requestor_14_status_mpie), // @[PTW.scala:802:19] .io_ptw_14_status_spie (_ptw_io_requestor_14_status_spie), // @[PTW.scala:802:19] .io_ptw_14_status_mie (_ptw_io_requestor_14_status_mie), // @[PTW.scala:802:19] .io_ptw_14_status_sie (_ptw_io_requestor_14_status_sie), // @[PTW.scala:802:19] .io_ptw_14_hstatus_spvp (_ptw_io_requestor_14_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_14_hstatus_spv (_ptw_io_requestor_14_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_14_hstatus_gva (_ptw_io_requestor_14_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_14_gstatus_debug (_ptw_io_requestor_14_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_14_gstatus_cease (_ptw_io_requestor_14_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_14_gstatus_wfi (_ptw_io_requestor_14_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_14_gstatus_isa (_ptw_io_requestor_14_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_14_gstatus_dprv (_ptw_io_requestor_14_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_dv (_ptw_io_requestor_14_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_prv (_ptw_io_requestor_14_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_v (_ptw_io_requestor_14_gstatus_v), // @[PTW.scala:802:19] .io_ptw_14_gstatus_zero2 (_ptw_io_requestor_14_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpv (_ptw_io_requestor_14_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_gva (_ptw_io_requestor_14_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mbe (_ptw_io_requestor_14_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sbe (_ptw_io_requestor_14_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sxl (_ptw_io_requestor_14_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_14_gstatus_zero1 (_ptw_io_requestor_14_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tsr (_ptw_io_requestor_14_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tw (_ptw_io_requestor_14_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_14_gstatus_tvm (_ptw_io_requestor_14_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mxr (_ptw_io_requestor_14_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sum (_ptw_io_requestor_14_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mprv (_ptw_io_requestor_14_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_14_gstatus_fs (_ptw_io_requestor_14_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpp (_ptw_io_requestor_14_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_14_gstatus_vs (_ptw_io_requestor_14_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_14_gstatus_spp (_ptw_io_requestor_14_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mpie (_ptw_io_requestor_14_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_ube (_ptw_io_requestor_14_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_14_gstatus_spie (_ptw_io_requestor_14_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_upie (_ptw_io_requestor_14_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_mie (_ptw_io_requestor_14_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_hie (_ptw_io_requestor_14_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_sie (_ptw_io_requestor_14_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_14_gstatus_uie (_ptw_io_requestor_14_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_l (_ptw_io_requestor_14_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_a (_ptw_io_requestor_14_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_x (_ptw_io_requestor_14_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_w (_ptw_io_requestor_14_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_cfg_r (_ptw_io_requestor_14_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_addr (_ptw_io_requestor_14_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_0_mask (_ptw_io_requestor_14_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_l (_ptw_io_requestor_14_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_a (_ptw_io_requestor_14_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_x (_ptw_io_requestor_14_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_w (_ptw_io_requestor_14_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_cfg_r (_ptw_io_requestor_14_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_addr (_ptw_io_requestor_14_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_1_mask (_ptw_io_requestor_14_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_l (_ptw_io_requestor_14_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_a (_ptw_io_requestor_14_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_x (_ptw_io_requestor_14_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_w (_ptw_io_requestor_14_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_cfg_r (_ptw_io_requestor_14_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_addr (_ptw_io_requestor_14_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_2_mask (_ptw_io_requestor_14_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_l (_ptw_io_requestor_14_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_a (_ptw_io_requestor_14_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_x (_ptw_io_requestor_14_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_w (_ptw_io_requestor_14_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_cfg_r (_ptw_io_requestor_14_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_addr (_ptw_io_requestor_14_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_3_mask (_ptw_io_requestor_14_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_l (_ptw_io_requestor_14_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_a (_ptw_io_requestor_14_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_x (_ptw_io_requestor_14_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_w (_ptw_io_requestor_14_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_cfg_r (_ptw_io_requestor_14_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_addr (_ptw_io_requestor_14_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_4_mask (_ptw_io_requestor_14_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_l (_ptw_io_requestor_14_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_a (_ptw_io_requestor_14_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_x (_ptw_io_requestor_14_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_w (_ptw_io_requestor_14_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_cfg_r (_ptw_io_requestor_14_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_addr (_ptw_io_requestor_14_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_5_mask (_ptw_io_requestor_14_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_l (_ptw_io_requestor_14_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_a (_ptw_io_requestor_14_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_x (_ptw_io_requestor_14_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_w (_ptw_io_requestor_14_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_cfg_r (_ptw_io_requestor_14_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_addr (_ptw_io_requestor_14_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_6_mask (_ptw_io_requestor_14_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_l (_ptw_io_requestor_14_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_a (_ptw_io_requestor_14_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_x (_ptw_io_requestor_14_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_w (_ptw_io_requestor_14_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_cfg_r (_ptw_io_requestor_14_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_addr (_ptw_io_requestor_14_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_14_pmp_7_mask (_ptw_io_requestor_14_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_ren (_ptw_io_requestor_14_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_wen (_ptw_io_requestor_14_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_wdata (_ptw_io_requestor_14_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_0_value (_ptw_io_requestor_14_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_ren (_ptw_io_requestor_14_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_wen (_ptw_io_requestor_14_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_wdata (_ptw_io_requestor_14_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_1_value (_ptw_io_requestor_14_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_ren (_ptw_io_requestor_14_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_wen (_ptw_io_requestor_14_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_wdata (_ptw_io_requestor_14_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_2_value (_ptw_io_requestor_14_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_ren (_ptw_io_requestor_14_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_wen (_ptw_io_requestor_14_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_wdata (_ptw_io_requestor_14_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_14_customCSRs_csrs_3_value (_ptw_io_requestor_14_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_15_req_ready (_ptw_io_requestor_15_req_ready), // @[PTW.scala:802:19] .io_ptw_15_req_valid (_zstd_compressor_io_ptw_15_req_valid), .io_ptw_15_req_bits_bits_addr (_zstd_compressor_io_ptw_15_req_bits_bits_addr), .io_ptw_15_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_15_req_bits_bits_need_gpa), .io_ptw_15_resp_valid (_ptw_io_requestor_15_resp_valid), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_ae_ptw (_ptw_io_requestor_15_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_ae_final (_ptw_io_requestor_15_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pf (_ptw_io_requestor_15_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gf (_ptw_io_requestor_15_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hr (_ptw_io_requestor_15_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hw (_ptw_io_requestor_15_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_hx (_ptw_io_requestor_15_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_reserved_for_future (_ptw_io_requestor_15_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_ppn (_ptw_io_requestor_15_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_reserved_for_software (_ptw_io_requestor_15_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_d (_ptw_io_requestor_15_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_a (_ptw_io_requestor_15_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_g (_ptw_io_requestor_15_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_u (_ptw_io_requestor_15_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_x (_ptw_io_requestor_15_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_w (_ptw_io_requestor_15_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_r (_ptw_io_requestor_15_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_pte_v (_ptw_io_requestor_15_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_level (_ptw_io_requestor_15_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_homogeneous (_ptw_io_requestor_15_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_valid (_ptw_io_requestor_15_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_bits (_ptw_io_requestor_15_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_15_resp_bits_gpa_is_pte (_ptw_io_requestor_15_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_15_ptbr_mode (_ptw_io_requestor_15_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_15_ptbr_ppn (_ptw_io_requestor_15_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_15_status_debug (_ptw_io_requestor_15_status_debug), // @[PTW.scala:802:19] .io_ptw_15_status_cease (_ptw_io_requestor_15_status_cease), // @[PTW.scala:802:19] .io_ptw_15_status_wfi (_ptw_io_requestor_15_status_wfi), // @[PTW.scala:802:19] .io_ptw_15_status_isa (_ptw_io_requestor_15_status_isa), // @[PTW.scala:802:19] .io_ptw_15_status_dprv (_ptw_io_requestor_15_status_dprv), // @[PTW.scala:802:19] .io_ptw_15_status_dv (_ptw_io_requestor_15_status_dv), // @[PTW.scala:802:19] .io_ptw_15_status_prv (_ptw_io_requestor_15_status_prv), // @[PTW.scala:802:19] .io_ptw_15_status_v (_ptw_io_requestor_15_status_v), // @[PTW.scala:802:19] .io_ptw_15_status_mpv (_ptw_io_requestor_15_status_mpv), // @[PTW.scala:802:19] .io_ptw_15_status_gva (_ptw_io_requestor_15_status_gva), // @[PTW.scala:802:19] .io_ptw_15_status_tsr (_ptw_io_requestor_15_status_tsr), // @[PTW.scala:802:19] .io_ptw_15_status_tw (_ptw_io_requestor_15_status_tw), // @[PTW.scala:802:19] .io_ptw_15_status_tvm (_ptw_io_requestor_15_status_tvm), // @[PTW.scala:802:19] .io_ptw_15_status_mxr (_ptw_io_requestor_15_status_mxr), // @[PTW.scala:802:19] .io_ptw_15_status_sum (_ptw_io_requestor_15_status_sum), // @[PTW.scala:802:19] .io_ptw_15_status_mprv (_ptw_io_requestor_15_status_mprv), // @[PTW.scala:802:19] .io_ptw_15_status_fs (_ptw_io_requestor_15_status_fs), // @[PTW.scala:802:19] .io_ptw_15_status_mpp (_ptw_io_requestor_15_status_mpp), // @[PTW.scala:802:19] .io_ptw_15_status_spp (_ptw_io_requestor_15_status_spp), // @[PTW.scala:802:19] .io_ptw_15_status_mpie (_ptw_io_requestor_15_status_mpie), // @[PTW.scala:802:19] .io_ptw_15_status_spie (_ptw_io_requestor_15_status_spie), // @[PTW.scala:802:19] .io_ptw_15_status_mie (_ptw_io_requestor_15_status_mie), // @[PTW.scala:802:19] .io_ptw_15_status_sie (_ptw_io_requestor_15_status_sie), // @[PTW.scala:802:19] .io_ptw_15_hstatus_spvp (_ptw_io_requestor_15_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_15_hstatus_spv (_ptw_io_requestor_15_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_15_hstatus_gva (_ptw_io_requestor_15_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_15_gstatus_debug (_ptw_io_requestor_15_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_15_gstatus_cease (_ptw_io_requestor_15_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_15_gstatus_wfi (_ptw_io_requestor_15_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_15_gstatus_isa (_ptw_io_requestor_15_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_15_gstatus_dprv (_ptw_io_requestor_15_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_dv (_ptw_io_requestor_15_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_prv (_ptw_io_requestor_15_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_v (_ptw_io_requestor_15_gstatus_v), // @[PTW.scala:802:19] .io_ptw_15_gstatus_zero2 (_ptw_io_requestor_15_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpv (_ptw_io_requestor_15_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_gva (_ptw_io_requestor_15_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mbe (_ptw_io_requestor_15_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sbe (_ptw_io_requestor_15_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sxl (_ptw_io_requestor_15_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_15_gstatus_zero1 (_ptw_io_requestor_15_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tsr (_ptw_io_requestor_15_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tw (_ptw_io_requestor_15_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_15_gstatus_tvm (_ptw_io_requestor_15_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mxr (_ptw_io_requestor_15_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sum (_ptw_io_requestor_15_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mprv (_ptw_io_requestor_15_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_15_gstatus_fs (_ptw_io_requestor_15_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpp (_ptw_io_requestor_15_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_15_gstatus_vs (_ptw_io_requestor_15_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_15_gstatus_spp (_ptw_io_requestor_15_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mpie (_ptw_io_requestor_15_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_ube (_ptw_io_requestor_15_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_15_gstatus_spie (_ptw_io_requestor_15_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_upie (_ptw_io_requestor_15_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_mie (_ptw_io_requestor_15_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_hie (_ptw_io_requestor_15_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_sie (_ptw_io_requestor_15_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_15_gstatus_uie (_ptw_io_requestor_15_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_l (_ptw_io_requestor_15_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_a (_ptw_io_requestor_15_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_x (_ptw_io_requestor_15_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_w (_ptw_io_requestor_15_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_cfg_r (_ptw_io_requestor_15_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_addr (_ptw_io_requestor_15_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_0_mask (_ptw_io_requestor_15_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_l (_ptw_io_requestor_15_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_a (_ptw_io_requestor_15_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_x (_ptw_io_requestor_15_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_w (_ptw_io_requestor_15_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_cfg_r (_ptw_io_requestor_15_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_addr (_ptw_io_requestor_15_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_1_mask (_ptw_io_requestor_15_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_l (_ptw_io_requestor_15_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_a (_ptw_io_requestor_15_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_x (_ptw_io_requestor_15_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_w (_ptw_io_requestor_15_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_cfg_r (_ptw_io_requestor_15_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_addr (_ptw_io_requestor_15_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_2_mask (_ptw_io_requestor_15_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_l (_ptw_io_requestor_15_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_a (_ptw_io_requestor_15_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_x (_ptw_io_requestor_15_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_w (_ptw_io_requestor_15_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_cfg_r (_ptw_io_requestor_15_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_addr (_ptw_io_requestor_15_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_3_mask (_ptw_io_requestor_15_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_l (_ptw_io_requestor_15_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_a (_ptw_io_requestor_15_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_x (_ptw_io_requestor_15_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_w (_ptw_io_requestor_15_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_cfg_r (_ptw_io_requestor_15_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_addr (_ptw_io_requestor_15_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_4_mask (_ptw_io_requestor_15_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_l (_ptw_io_requestor_15_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_a (_ptw_io_requestor_15_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_x (_ptw_io_requestor_15_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_w (_ptw_io_requestor_15_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_cfg_r (_ptw_io_requestor_15_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_addr (_ptw_io_requestor_15_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_5_mask (_ptw_io_requestor_15_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_l (_ptw_io_requestor_15_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_a (_ptw_io_requestor_15_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_x (_ptw_io_requestor_15_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_w (_ptw_io_requestor_15_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_cfg_r (_ptw_io_requestor_15_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_addr (_ptw_io_requestor_15_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_6_mask (_ptw_io_requestor_15_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_l (_ptw_io_requestor_15_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_a (_ptw_io_requestor_15_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_x (_ptw_io_requestor_15_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_w (_ptw_io_requestor_15_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_cfg_r (_ptw_io_requestor_15_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_addr (_ptw_io_requestor_15_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_15_pmp_7_mask (_ptw_io_requestor_15_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_ren (_ptw_io_requestor_15_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_wen (_ptw_io_requestor_15_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_wdata (_ptw_io_requestor_15_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_0_value (_ptw_io_requestor_15_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_ren (_ptw_io_requestor_15_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_wen (_ptw_io_requestor_15_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_wdata (_ptw_io_requestor_15_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_1_value (_ptw_io_requestor_15_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_ren (_ptw_io_requestor_15_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_wen (_ptw_io_requestor_15_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_wdata (_ptw_io_requestor_15_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_2_value (_ptw_io_requestor_15_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_ren (_ptw_io_requestor_15_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_wen (_ptw_io_requestor_15_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_wdata (_ptw_io_requestor_15_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_15_customCSRs_csrs_3_value (_ptw_io_requestor_15_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_16_req_ready (_ptw_io_requestor_16_req_ready), // @[PTW.scala:802:19] .io_ptw_16_req_valid (_zstd_compressor_io_ptw_16_req_valid), .io_ptw_16_req_bits_bits_addr (_zstd_compressor_io_ptw_16_req_bits_bits_addr), .io_ptw_16_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_16_req_bits_bits_need_gpa), .io_ptw_16_resp_valid (_ptw_io_requestor_16_resp_valid), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_ae_ptw (_ptw_io_requestor_16_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_ae_final (_ptw_io_requestor_16_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pf (_ptw_io_requestor_16_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gf (_ptw_io_requestor_16_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hr (_ptw_io_requestor_16_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hw (_ptw_io_requestor_16_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_hx (_ptw_io_requestor_16_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_reserved_for_future (_ptw_io_requestor_16_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_ppn (_ptw_io_requestor_16_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_reserved_for_software (_ptw_io_requestor_16_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_d (_ptw_io_requestor_16_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_a (_ptw_io_requestor_16_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_g (_ptw_io_requestor_16_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_u (_ptw_io_requestor_16_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_x (_ptw_io_requestor_16_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_w (_ptw_io_requestor_16_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_r (_ptw_io_requestor_16_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_pte_v (_ptw_io_requestor_16_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_level (_ptw_io_requestor_16_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_homogeneous (_ptw_io_requestor_16_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_valid (_ptw_io_requestor_16_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_bits (_ptw_io_requestor_16_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_16_resp_bits_gpa_is_pte (_ptw_io_requestor_16_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_16_ptbr_mode (_ptw_io_requestor_16_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_16_ptbr_ppn (_ptw_io_requestor_16_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_16_status_debug (_ptw_io_requestor_16_status_debug), // @[PTW.scala:802:19] .io_ptw_16_status_cease (_ptw_io_requestor_16_status_cease), // @[PTW.scala:802:19] .io_ptw_16_status_wfi (_ptw_io_requestor_16_status_wfi), // @[PTW.scala:802:19] .io_ptw_16_status_isa (_ptw_io_requestor_16_status_isa), // @[PTW.scala:802:19] .io_ptw_16_status_dprv (_ptw_io_requestor_16_status_dprv), // @[PTW.scala:802:19] .io_ptw_16_status_dv (_ptw_io_requestor_16_status_dv), // @[PTW.scala:802:19] .io_ptw_16_status_prv (_ptw_io_requestor_16_status_prv), // @[PTW.scala:802:19] .io_ptw_16_status_v (_ptw_io_requestor_16_status_v), // @[PTW.scala:802:19] .io_ptw_16_status_mpv (_ptw_io_requestor_16_status_mpv), // @[PTW.scala:802:19] .io_ptw_16_status_gva (_ptw_io_requestor_16_status_gva), // @[PTW.scala:802:19] .io_ptw_16_status_tsr (_ptw_io_requestor_16_status_tsr), // @[PTW.scala:802:19] .io_ptw_16_status_tw (_ptw_io_requestor_16_status_tw), // @[PTW.scala:802:19] .io_ptw_16_status_tvm (_ptw_io_requestor_16_status_tvm), // @[PTW.scala:802:19] .io_ptw_16_status_mxr (_ptw_io_requestor_16_status_mxr), // @[PTW.scala:802:19] .io_ptw_16_status_sum (_ptw_io_requestor_16_status_sum), // @[PTW.scala:802:19] .io_ptw_16_status_mprv (_ptw_io_requestor_16_status_mprv), // @[PTW.scala:802:19] .io_ptw_16_status_fs (_ptw_io_requestor_16_status_fs), // @[PTW.scala:802:19] .io_ptw_16_status_mpp (_ptw_io_requestor_16_status_mpp), // @[PTW.scala:802:19] .io_ptw_16_status_spp (_ptw_io_requestor_16_status_spp), // @[PTW.scala:802:19] .io_ptw_16_status_mpie (_ptw_io_requestor_16_status_mpie), // @[PTW.scala:802:19] .io_ptw_16_status_spie (_ptw_io_requestor_16_status_spie), // @[PTW.scala:802:19] .io_ptw_16_status_mie (_ptw_io_requestor_16_status_mie), // @[PTW.scala:802:19] .io_ptw_16_status_sie (_ptw_io_requestor_16_status_sie), // @[PTW.scala:802:19] .io_ptw_16_hstatus_spvp (_ptw_io_requestor_16_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_16_hstatus_spv (_ptw_io_requestor_16_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_16_hstatus_gva (_ptw_io_requestor_16_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_16_gstatus_debug (_ptw_io_requestor_16_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_16_gstatus_cease (_ptw_io_requestor_16_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_16_gstatus_wfi (_ptw_io_requestor_16_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_16_gstatus_isa (_ptw_io_requestor_16_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_16_gstatus_dprv (_ptw_io_requestor_16_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_dv (_ptw_io_requestor_16_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_prv (_ptw_io_requestor_16_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_v (_ptw_io_requestor_16_gstatus_v), // @[PTW.scala:802:19] .io_ptw_16_gstatus_zero2 (_ptw_io_requestor_16_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpv (_ptw_io_requestor_16_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_gva (_ptw_io_requestor_16_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mbe (_ptw_io_requestor_16_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sbe (_ptw_io_requestor_16_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sxl (_ptw_io_requestor_16_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_16_gstatus_zero1 (_ptw_io_requestor_16_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tsr (_ptw_io_requestor_16_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tw (_ptw_io_requestor_16_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_16_gstatus_tvm (_ptw_io_requestor_16_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mxr (_ptw_io_requestor_16_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sum (_ptw_io_requestor_16_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mprv (_ptw_io_requestor_16_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_16_gstatus_fs (_ptw_io_requestor_16_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpp (_ptw_io_requestor_16_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_16_gstatus_vs (_ptw_io_requestor_16_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_16_gstatus_spp (_ptw_io_requestor_16_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mpie (_ptw_io_requestor_16_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_ube (_ptw_io_requestor_16_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_16_gstatus_spie (_ptw_io_requestor_16_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_upie (_ptw_io_requestor_16_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_mie (_ptw_io_requestor_16_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_hie (_ptw_io_requestor_16_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_sie (_ptw_io_requestor_16_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_16_gstatus_uie (_ptw_io_requestor_16_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_l (_ptw_io_requestor_16_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_a (_ptw_io_requestor_16_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_x (_ptw_io_requestor_16_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_w (_ptw_io_requestor_16_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_cfg_r (_ptw_io_requestor_16_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_addr (_ptw_io_requestor_16_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_0_mask (_ptw_io_requestor_16_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_l (_ptw_io_requestor_16_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_a (_ptw_io_requestor_16_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_x (_ptw_io_requestor_16_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_w (_ptw_io_requestor_16_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_cfg_r (_ptw_io_requestor_16_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_addr (_ptw_io_requestor_16_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_1_mask (_ptw_io_requestor_16_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_l (_ptw_io_requestor_16_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_a (_ptw_io_requestor_16_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_x (_ptw_io_requestor_16_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_w (_ptw_io_requestor_16_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_cfg_r (_ptw_io_requestor_16_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_addr (_ptw_io_requestor_16_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_2_mask (_ptw_io_requestor_16_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_l (_ptw_io_requestor_16_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_a (_ptw_io_requestor_16_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_x (_ptw_io_requestor_16_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_w (_ptw_io_requestor_16_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_cfg_r (_ptw_io_requestor_16_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_addr (_ptw_io_requestor_16_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_3_mask (_ptw_io_requestor_16_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_l (_ptw_io_requestor_16_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_a (_ptw_io_requestor_16_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_x (_ptw_io_requestor_16_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_w (_ptw_io_requestor_16_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_cfg_r (_ptw_io_requestor_16_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_addr (_ptw_io_requestor_16_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_4_mask (_ptw_io_requestor_16_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_l (_ptw_io_requestor_16_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_a (_ptw_io_requestor_16_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_x (_ptw_io_requestor_16_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_w (_ptw_io_requestor_16_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_cfg_r (_ptw_io_requestor_16_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_addr (_ptw_io_requestor_16_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_5_mask (_ptw_io_requestor_16_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_l (_ptw_io_requestor_16_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_a (_ptw_io_requestor_16_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_x (_ptw_io_requestor_16_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_w (_ptw_io_requestor_16_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_cfg_r (_ptw_io_requestor_16_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_addr (_ptw_io_requestor_16_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_6_mask (_ptw_io_requestor_16_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_l (_ptw_io_requestor_16_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_a (_ptw_io_requestor_16_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_x (_ptw_io_requestor_16_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_w (_ptw_io_requestor_16_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_cfg_r (_ptw_io_requestor_16_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_addr (_ptw_io_requestor_16_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_16_pmp_7_mask (_ptw_io_requestor_16_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_ren (_ptw_io_requestor_16_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_wen (_ptw_io_requestor_16_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_wdata (_ptw_io_requestor_16_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_0_value (_ptw_io_requestor_16_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_ren (_ptw_io_requestor_16_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_wen (_ptw_io_requestor_16_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_wdata (_ptw_io_requestor_16_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_1_value (_ptw_io_requestor_16_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_ren (_ptw_io_requestor_16_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_wen (_ptw_io_requestor_16_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_wdata (_ptw_io_requestor_16_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_2_value (_ptw_io_requestor_16_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_ren (_ptw_io_requestor_16_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_wen (_ptw_io_requestor_16_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_wdata (_ptw_io_requestor_16_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_16_customCSRs_csrs_3_value (_ptw_io_requestor_16_customCSRs_csrs_3_value), // @[PTW.scala:802:19] .io_ptw_17_req_ready (_ptw_io_requestor_17_req_ready), // @[PTW.scala:802:19] .io_ptw_17_req_valid (_zstd_compressor_io_ptw_17_req_valid), .io_ptw_17_req_bits_bits_addr (_zstd_compressor_io_ptw_17_req_bits_bits_addr), .io_ptw_17_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_17_req_bits_bits_need_gpa), .io_ptw_17_resp_valid (_ptw_io_requestor_17_resp_valid), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_ae_ptw (_ptw_io_requestor_17_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_ae_final (_ptw_io_requestor_17_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pf (_ptw_io_requestor_17_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gf (_ptw_io_requestor_17_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hr (_ptw_io_requestor_17_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hw (_ptw_io_requestor_17_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_hx (_ptw_io_requestor_17_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_reserved_for_future (_ptw_io_requestor_17_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_ppn (_ptw_io_requestor_17_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_reserved_for_software (_ptw_io_requestor_17_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_d (_ptw_io_requestor_17_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_a (_ptw_io_requestor_17_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_g (_ptw_io_requestor_17_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_u (_ptw_io_requestor_17_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_x (_ptw_io_requestor_17_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_w (_ptw_io_requestor_17_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_r (_ptw_io_requestor_17_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_pte_v (_ptw_io_requestor_17_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_level (_ptw_io_requestor_17_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_homogeneous (_ptw_io_requestor_17_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_valid (_ptw_io_requestor_17_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_bits (_ptw_io_requestor_17_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_17_resp_bits_gpa_is_pte (_ptw_io_requestor_17_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_17_ptbr_mode (_ptw_io_requestor_17_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_17_ptbr_ppn (_ptw_io_requestor_17_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_17_status_debug (_ptw_io_requestor_17_status_debug), // @[PTW.scala:802:19] .io_ptw_17_status_cease (_ptw_io_requestor_17_status_cease), // @[PTW.scala:802:19] .io_ptw_17_status_wfi (_ptw_io_requestor_17_status_wfi), // @[PTW.scala:802:19] .io_ptw_17_status_isa (_ptw_io_requestor_17_status_isa), // @[PTW.scala:802:19] .io_ptw_17_status_dprv (_ptw_io_requestor_17_status_dprv), // @[PTW.scala:802:19] .io_ptw_17_status_dv (_ptw_io_requestor_17_status_dv), // @[PTW.scala:802:19] .io_ptw_17_status_prv (_ptw_io_requestor_17_status_prv), // @[PTW.scala:802:19] .io_ptw_17_status_v (_ptw_io_requestor_17_status_v), // @[PTW.scala:802:19] .io_ptw_17_status_mpv (_ptw_io_requestor_17_status_mpv), // @[PTW.scala:802:19] .io_ptw_17_status_gva (_ptw_io_requestor_17_status_gva), // @[PTW.scala:802:19] .io_ptw_17_status_tsr (_ptw_io_requestor_17_status_tsr), // @[PTW.scala:802:19] .io_ptw_17_status_tw (_ptw_io_requestor_17_status_tw), // @[PTW.scala:802:19] .io_ptw_17_status_tvm (_ptw_io_requestor_17_status_tvm), // @[PTW.scala:802:19] .io_ptw_17_status_mxr (_ptw_io_requestor_17_status_mxr), // @[PTW.scala:802:19] .io_ptw_17_status_sum (_ptw_io_requestor_17_status_sum), // @[PTW.scala:802:19] .io_ptw_17_status_mprv (_ptw_io_requestor_17_status_mprv), // @[PTW.scala:802:19] .io_ptw_17_status_fs (_ptw_io_requestor_17_status_fs), // @[PTW.scala:802:19] .io_ptw_17_status_mpp (_ptw_io_requestor_17_status_mpp), // @[PTW.scala:802:19] .io_ptw_17_status_spp (_ptw_io_requestor_17_status_spp), // @[PTW.scala:802:19] .io_ptw_17_status_mpie (_ptw_io_requestor_17_status_mpie), // @[PTW.scala:802:19] .io_ptw_17_status_spie (_ptw_io_requestor_17_status_spie), // @[PTW.scala:802:19] .io_ptw_17_status_mie (_ptw_io_requestor_17_status_mie), // @[PTW.scala:802:19] .io_ptw_17_status_sie (_ptw_io_requestor_17_status_sie), // @[PTW.scala:802:19] .io_ptw_17_hstatus_spvp (_ptw_io_requestor_17_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_17_hstatus_spv (_ptw_io_requestor_17_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_17_hstatus_gva (_ptw_io_requestor_17_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_17_gstatus_debug (_ptw_io_requestor_17_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_17_gstatus_cease (_ptw_io_requestor_17_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_17_gstatus_wfi (_ptw_io_requestor_17_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_17_gstatus_isa (_ptw_io_requestor_17_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_17_gstatus_dprv (_ptw_io_requestor_17_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_dv (_ptw_io_requestor_17_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_prv (_ptw_io_requestor_17_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_v (_ptw_io_requestor_17_gstatus_v), // @[PTW.scala:802:19] .io_ptw_17_gstatus_zero2 (_ptw_io_requestor_17_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpv (_ptw_io_requestor_17_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_gva (_ptw_io_requestor_17_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mbe (_ptw_io_requestor_17_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sbe (_ptw_io_requestor_17_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sxl (_ptw_io_requestor_17_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_17_gstatus_zero1 (_ptw_io_requestor_17_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tsr (_ptw_io_requestor_17_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tw (_ptw_io_requestor_17_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_17_gstatus_tvm (_ptw_io_requestor_17_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mxr (_ptw_io_requestor_17_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sum (_ptw_io_requestor_17_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mprv (_ptw_io_requestor_17_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_17_gstatus_fs (_ptw_io_requestor_17_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpp (_ptw_io_requestor_17_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_17_gstatus_vs (_ptw_io_requestor_17_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_17_gstatus_spp (_ptw_io_requestor_17_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mpie (_ptw_io_requestor_17_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_ube (_ptw_io_requestor_17_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_17_gstatus_spie (_ptw_io_requestor_17_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_upie (_ptw_io_requestor_17_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_mie (_ptw_io_requestor_17_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_hie (_ptw_io_requestor_17_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_sie (_ptw_io_requestor_17_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_17_gstatus_uie (_ptw_io_requestor_17_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_l (_ptw_io_requestor_17_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_a (_ptw_io_requestor_17_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_x (_ptw_io_requestor_17_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_w (_ptw_io_requestor_17_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_cfg_r (_ptw_io_requestor_17_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_addr (_ptw_io_requestor_17_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_0_mask (_ptw_io_requestor_17_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_l (_ptw_io_requestor_17_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_a (_ptw_io_requestor_17_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_x (_ptw_io_requestor_17_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_w (_ptw_io_requestor_17_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_cfg_r (_ptw_io_requestor_17_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_addr (_ptw_io_requestor_17_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_1_mask (_ptw_io_requestor_17_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_l (_ptw_io_requestor_17_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_a (_ptw_io_requestor_17_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_x (_ptw_io_requestor_17_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_w (_ptw_io_requestor_17_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_cfg_r (_ptw_io_requestor_17_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_addr (_ptw_io_requestor_17_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_2_mask (_ptw_io_requestor_17_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_l (_ptw_io_requestor_17_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_a (_ptw_io_requestor_17_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_x (_ptw_io_requestor_17_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_w (_ptw_io_requestor_17_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_cfg_r (_ptw_io_requestor_17_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_addr (_ptw_io_requestor_17_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_3_mask (_ptw_io_requestor_17_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_l (_ptw_io_requestor_17_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_a (_ptw_io_requestor_17_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_x (_ptw_io_requestor_17_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_w (_ptw_io_requestor_17_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_cfg_r (_ptw_io_requestor_17_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_addr (_ptw_io_requestor_17_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_4_mask (_ptw_io_requestor_17_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_l (_ptw_io_requestor_17_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_a (_ptw_io_requestor_17_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_x (_ptw_io_requestor_17_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_w (_ptw_io_requestor_17_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_cfg_r (_ptw_io_requestor_17_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_addr (_ptw_io_requestor_17_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_5_mask (_ptw_io_requestor_17_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_l (_ptw_io_requestor_17_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_a (_ptw_io_requestor_17_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_x (_ptw_io_requestor_17_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_w (_ptw_io_requestor_17_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_cfg_r (_ptw_io_requestor_17_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_addr (_ptw_io_requestor_17_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_6_mask (_ptw_io_requestor_17_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_l (_ptw_io_requestor_17_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_a (_ptw_io_requestor_17_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_x (_ptw_io_requestor_17_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_w (_ptw_io_requestor_17_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_cfg_r (_ptw_io_requestor_17_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_addr (_ptw_io_requestor_17_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_17_pmp_7_mask (_ptw_io_requestor_17_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_ren (_ptw_io_requestor_17_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_wen (_ptw_io_requestor_17_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_wdata (_ptw_io_requestor_17_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_0_value (_ptw_io_requestor_17_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_ren (_ptw_io_requestor_17_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_wen (_ptw_io_requestor_17_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_wdata (_ptw_io_requestor_17_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_1_value (_ptw_io_requestor_17_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_ren (_ptw_io_requestor_17_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_wen (_ptw_io_requestor_17_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_wdata (_ptw_io_requestor_17_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_2_value (_ptw_io_requestor_17_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_ren (_ptw_io_requestor_17_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_wen (_ptw_io_requestor_17_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_wdata (_ptw_io_requestor_17_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_17_customCSRs_csrs_3_value (_ptw_io_requestor_17_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Configs.scala:62:39] Frontend frontend ( // @[Frontend.scala:393:28] .clock (clock), .reset (reset), .auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid), .auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address), .auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20] .io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20] .io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20] .io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20] .io_cpu_resp_valid (_frontend_io_cpu_resp_valid), .io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), .io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), .io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), .io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), .io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), .io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), .io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), .io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), .io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), .io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), .io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), .io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), .io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), .io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), .io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid), .io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits), .io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), .io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20] .io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20] .io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20] .io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20] .io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20] .io_cpu_npc (_frontend_io_cpu_npc), .io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire), .io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), .io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20] .io_ptw_req_ready (_ptw_io_requestor_19_req_ready), // @[PTW.scala:802:19] .io_ptw_req_valid (_frontend_io_ptw_req_valid), .io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid), .io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_19_resp_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_19_resp_bits_ae_ptw), // @[PTW.scala:802:19] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_19_resp_bits_ae_final), // @[PTW.scala:802:19] .io_ptw_resp_bits_pf (_ptw_io_requestor_19_resp_bits_pf), // @[PTW.scala:802:19] .io_ptw_resp_bits_gf (_ptw_io_requestor_19_resp_bits_gf), // @[PTW.scala:802:19] .io_ptw_resp_bits_hr (_ptw_io_requestor_19_resp_bits_hr), // @[PTW.scala:802:19] .io_ptw_resp_bits_hw (_ptw_io_requestor_19_resp_bits_hw), // @[PTW.scala:802:19] .io_ptw_resp_bits_hx (_ptw_io_requestor_19_resp_bits_hx), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_19_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_19_resp_bits_pte_ppn), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_19_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_19_resp_bits_pte_d), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_19_resp_bits_pte_a), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_19_resp_bits_pte_g), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_19_resp_bits_pte_u), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_19_resp_bits_pte_x), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_19_resp_bits_pte_w), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_19_resp_bits_pte_r), // @[PTW.scala:802:19] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_19_resp_bits_pte_v), // @[PTW.scala:802:19] .io_ptw_resp_bits_level (_ptw_io_requestor_19_resp_bits_level), // @[PTW.scala:802:19] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_19_resp_bits_homogeneous), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_19_resp_bits_gpa_valid), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_19_resp_bits_gpa_bits), // @[PTW.scala:802:19] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_19_resp_bits_gpa_is_pte), // @[PTW.scala:802:19] .io_ptw_ptbr_mode (_ptw_io_requestor_19_ptbr_mode), // @[PTW.scala:802:19] .io_ptw_ptbr_ppn (_ptw_io_requestor_19_ptbr_ppn), // @[PTW.scala:802:19] .io_ptw_status_debug (_ptw_io_requestor_19_status_debug), // @[PTW.scala:802:19] .io_ptw_status_cease (_ptw_io_requestor_19_status_cease), // @[PTW.scala:802:19] .io_ptw_status_wfi (_ptw_io_requestor_19_status_wfi), // @[PTW.scala:802:19] .io_ptw_status_isa (_ptw_io_requestor_19_status_isa), // @[PTW.scala:802:19] .io_ptw_status_dprv (_ptw_io_requestor_19_status_dprv), // @[PTW.scala:802:19] .io_ptw_status_dv (_ptw_io_requestor_19_status_dv), // @[PTW.scala:802:19] .io_ptw_status_prv (_ptw_io_requestor_19_status_prv), // @[PTW.scala:802:19] .io_ptw_status_v (_ptw_io_requestor_19_status_v), // @[PTW.scala:802:19] .io_ptw_status_mpv (_ptw_io_requestor_19_status_mpv), // @[PTW.scala:802:19] .io_ptw_status_gva (_ptw_io_requestor_19_status_gva), // @[PTW.scala:802:19] .io_ptw_status_tsr (_ptw_io_requestor_19_status_tsr), // @[PTW.scala:802:19] .io_ptw_status_tw (_ptw_io_requestor_19_status_tw), // @[PTW.scala:802:19] .io_ptw_status_tvm (_ptw_io_requestor_19_status_tvm), // @[PTW.scala:802:19] .io_ptw_status_mxr (_ptw_io_requestor_19_status_mxr), // @[PTW.scala:802:19] .io_ptw_status_sum (_ptw_io_requestor_19_status_sum), // @[PTW.scala:802:19] .io_ptw_status_mprv (_ptw_io_requestor_19_status_mprv), // @[PTW.scala:802:19] .io_ptw_status_fs (_ptw_io_requestor_19_status_fs), // @[PTW.scala:802:19] .io_ptw_status_mpp (_ptw_io_requestor_19_status_mpp), // @[PTW.scala:802:19] .io_ptw_status_spp (_ptw_io_requestor_19_status_spp), // @[PTW.scala:802:19] .io_ptw_status_mpie (_ptw_io_requestor_19_status_mpie), // @[PTW.scala:802:19] .io_ptw_status_spie (_ptw_io_requestor_19_status_spie), // @[PTW.scala:802:19] .io_ptw_status_mie (_ptw_io_requestor_19_status_mie), // @[PTW.scala:802:19] .io_ptw_status_sie (_ptw_io_requestor_19_status_sie), // @[PTW.scala:802:19] .io_ptw_hstatus_spvp (_ptw_io_requestor_19_hstatus_spvp), // @[PTW.scala:802:19] .io_ptw_hstatus_spv (_ptw_io_requestor_19_hstatus_spv), // @[PTW.scala:802:19] .io_ptw_hstatus_gva (_ptw_io_requestor_19_hstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_debug (_ptw_io_requestor_19_gstatus_debug), // @[PTW.scala:802:19] .io_ptw_gstatus_cease (_ptw_io_requestor_19_gstatus_cease), // @[PTW.scala:802:19] .io_ptw_gstatus_wfi (_ptw_io_requestor_19_gstatus_wfi), // @[PTW.scala:802:19] .io_ptw_gstatus_isa (_ptw_io_requestor_19_gstatus_isa), // @[PTW.scala:802:19] .io_ptw_gstatus_dprv (_ptw_io_requestor_19_gstatus_dprv), // @[PTW.scala:802:19] .io_ptw_gstatus_dv (_ptw_io_requestor_19_gstatus_dv), // @[PTW.scala:802:19] .io_ptw_gstatus_prv (_ptw_io_requestor_19_gstatus_prv), // @[PTW.scala:802:19] .io_ptw_gstatus_v (_ptw_io_requestor_19_gstatus_v), // @[PTW.scala:802:19] .io_ptw_gstatus_zero2 (_ptw_io_requestor_19_gstatus_zero2), // @[PTW.scala:802:19] .io_ptw_gstatus_mpv (_ptw_io_requestor_19_gstatus_mpv), // @[PTW.scala:802:19] .io_ptw_gstatus_gva (_ptw_io_requestor_19_gstatus_gva), // @[PTW.scala:802:19] .io_ptw_gstatus_mbe (_ptw_io_requestor_19_gstatus_mbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sbe (_ptw_io_requestor_19_gstatus_sbe), // @[PTW.scala:802:19] .io_ptw_gstatus_sxl (_ptw_io_requestor_19_gstatus_sxl), // @[PTW.scala:802:19] .io_ptw_gstatus_zero1 (_ptw_io_requestor_19_gstatus_zero1), // @[PTW.scala:802:19] .io_ptw_gstatus_tsr (_ptw_io_requestor_19_gstatus_tsr), // @[PTW.scala:802:19] .io_ptw_gstatus_tw (_ptw_io_requestor_19_gstatus_tw), // @[PTW.scala:802:19] .io_ptw_gstatus_tvm (_ptw_io_requestor_19_gstatus_tvm), // @[PTW.scala:802:19] .io_ptw_gstatus_mxr (_ptw_io_requestor_19_gstatus_mxr), // @[PTW.scala:802:19] .io_ptw_gstatus_sum (_ptw_io_requestor_19_gstatus_sum), // @[PTW.scala:802:19] .io_ptw_gstatus_mprv (_ptw_io_requestor_19_gstatus_mprv), // @[PTW.scala:802:19] .io_ptw_gstatus_fs (_ptw_io_requestor_19_gstatus_fs), // @[PTW.scala:802:19] .io_ptw_gstatus_mpp (_ptw_io_requestor_19_gstatus_mpp), // @[PTW.scala:802:19] .io_ptw_gstatus_vs (_ptw_io_requestor_19_gstatus_vs), // @[PTW.scala:802:19] .io_ptw_gstatus_spp (_ptw_io_requestor_19_gstatus_spp), // @[PTW.scala:802:19] .io_ptw_gstatus_mpie (_ptw_io_requestor_19_gstatus_mpie), // @[PTW.scala:802:19] .io_ptw_gstatus_ube (_ptw_io_requestor_19_gstatus_ube), // @[PTW.scala:802:19] .io_ptw_gstatus_spie (_ptw_io_requestor_19_gstatus_spie), // @[PTW.scala:802:19] .io_ptw_gstatus_upie (_ptw_io_requestor_19_gstatus_upie), // @[PTW.scala:802:19] .io_ptw_gstatus_mie (_ptw_io_requestor_19_gstatus_mie), // @[PTW.scala:802:19] .io_ptw_gstatus_hie (_ptw_io_requestor_19_gstatus_hie), // @[PTW.scala:802:19] .io_ptw_gstatus_sie (_ptw_io_requestor_19_gstatus_sie), // @[PTW.scala:802:19] .io_ptw_gstatus_uie (_ptw_io_requestor_19_gstatus_uie), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_l (_ptw_io_requestor_19_pmp_0_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_a (_ptw_io_requestor_19_pmp_0_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_x (_ptw_io_requestor_19_pmp_0_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_w (_ptw_io_requestor_19_pmp_0_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_0_cfg_r (_ptw_io_requestor_19_pmp_0_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_0_addr (_ptw_io_requestor_19_pmp_0_addr), // @[PTW.scala:802:19] .io_ptw_pmp_0_mask (_ptw_io_requestor_19_pmp_0_mask), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_l (_ptw_io_requestor_19_pmp_1_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_a (_ptw_io_requestor_19_pmp_1_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_x (_ptw_io_requestor_19_pmp_1_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_w (_ptw_io_requestor_19_pmp_1_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_1_cfg_r (_ptw_io_requestor_19_pmp_1_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_1_addr (_ptw_io_requestor_19_pmp_1_addr), // @[PTW.scala:802:19] .io_ptw_pmp_1_mask (_ptw_io_requestor_19_pmp_1_mask), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_l (_ptw_io_requestor_19_pmp_2_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_a (_ptw_io_requestor_19_pmp_2_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_x (_ptw_io_requestor_19_pmp_2_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_w (_ptw_io_requestor_19_pmp_2_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_2_cfg_r (_ptw_io_requestor_19_pmp_2_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_2_addr (_ptw_io_requestor_19_pmp_2_addr), // @[PTW.scala:802:19] .io_ptw_pmp_2_mask (_ptw_io_requestor_19_pmp_2_mask), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_l (_ptw_io_requestor_19_pmp_3_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_a (_ptw_io_requestor_19_pmp_3_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_x (_ptw_io_requestor_19_pmp_3_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_w (_ptw_io_requestor_19_pmp_3_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_3_cfg_r (_ptw_io_requestor_19_pmp_3_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_3_addr (_ptw_io_requestor_19_pmp_3_addr), // @[PTW.scala:802:19] .io_ptw_pmp_3_mask (_ptw_io_requestor_19_pmp_3_mask), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_l (_ptw_io_requestor_19_pmp_4_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_a (_ptw_io_requestor_19_pmp_4_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_x (_ptw_io_requestor_19_pmp_4_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_w (_ptw_io_requestor_19_pmp_4_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_4_cfg_r (_ptw_io_requestor_19_pmp_4_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_4_addr (_ptw_io_requestor_19_pmp_4_addr), // @[PTW.scala:802:19] .io_ptw_pmp_4_mask (_ptw_io_requestor_19_pmp_4_mask), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_l (_ptw_io_requestor_19_pmp_5_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_a (_ptw_io_requestor_19_pmp_5_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_x (_ptw_io_requestor_19_pmp_5_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_w (_ptw_io_requestor_19_pmp_5_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_5_cfg_r (_ptw_io_requestor_19_pmp_5_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_5_addr (_ptw_io_requestor_19_pmp_5_addr), // @[PTW.scala:802:19] .io_ptw_pmp_5_mask (_ptw_io_requestor_19_pmp_5_mask), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_l (_ptw_io_requestor_19_pmp_6_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_a (_ptw_io_requestor_19_pmp_6_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_x (_ptw_io_requestor_19_pmp_6_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_w (_ptw_io_requestor_19_pmp_6_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_6_cfg_r (_ptw_io_requestor_19_pmp_6_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_6_addr (_ptw_io_requestor_19_pmp_6_addr), // @[PTW.scala:802:19] .io_ptw_pmp_6_mask (_ptw_io_requestor_19_pmp_6_mask), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_l (_ptw_io_requestor_19_pmp_7_cfg_l), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_a (_ptw_io_requestor_19_pmp_7_cfg_a), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_x (_ptw_io_requestor_19_pmp_7_cfg_x), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_w (_ptw_io_requestor_19_pmp_7_cfg_w), // @[PTW.scala:802:19] .io_ptw_pmp_7_cfg_r (_ptw_io_requestor_19_pmp_7_cfg_r), // @[PTW.scala:802:19] .io_ptw_pmp_7_addr (_ptw_io_requestor_19_pmp_7_addr), // @[PTW.scala:802:19] .io_ptw_pmp_7_mask (_ptw_io_requestor_19_pmp_7_mask), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_19_customCSRs_csrs_0_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_19_customCSRs_csrs_0_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_19_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_19_customCSRs_csrs_0_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_19_customCSRs_csrs_1_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_19_customCSRs_csrs_1_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_19_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_19_customCSRs_csrs_1_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_19_customCSRs_csrs_2_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_19_customCSRs_csrs_2_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_19_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_19_customCSRs_csrs_2_value), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_19_customCSRs_csrs_3_ren), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_19_customCSRs_csrs_3_wen), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_19_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_19_customCSRs_csrs_3_value) // @[PTW.scala:802:19] ); // @[Frontend.scala:393:28] TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset) ); // @[Fragmenter.scala:345:34] FPU fpuOpt ( // @[RocketTile.scala:242:62] .clock (clock), .reset (reset), .io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20] .io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20] .io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20] .io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20] .io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20] .io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), .io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), .io_store_data (_fpuOpt_io_store_data), .io_toint_data (_fpuOpt_io_toint_data), .io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20] .io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20] .io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20] .io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20] .io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20] .io_fcsr_rdy (_fpuOpt_io_fcsr_rdy), .io_nack_mem (_fpuOpt_io_nack_mem), .io_illegal_rm (_fpuOpt_io_illegal_rm), .io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20] .io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20] .io_dec_ldst (_fpuOpt_io_dec_ldst), .io_dec_wen (_fpuOpt_io_dec_wen), .io_dec_ren1 (_fpuOpt_io_dec_ren1), .io_dec_ren2 (_fpuOpt_io_dec_ren2), .io_dec_ren3 (_fpuOpt_io_dec_ren3), .io_dec_swap12 (_fpuOpt_io_dec_swap12), .io_dec_swap23 (_fpuOpt_io_dec_swap23), .io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), .io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), .io_dec_fromint (_fpuOpt_io_dec_fromint), .io_dec_toint (_fpuOpt_io_dec_toint), .io_dec_fastpipe (_fpuOpt_io_dec_fastpipe), .io_dec_fma (_fpuOpt_io_dec_fma), .io_dec_div (_fpuOpt_io_dec_div), .io_dec_sqrt (_fpuOpt_io_dec_sqrt), .io_dec_wflags (_fpuOpt_io_dec_wflags), .io_dec_vec (_fpuOpt_io_dec_vec), .io_sboard_set (_fpuOpt_io_sboard_set), .io_sboard_clr (_fpuOpt_io_sboard_clr), .io_sboard_clra (_fpuOpt_io_sboard_clra), .io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20] ); // @[RocketTile.scala:242:62] HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[LazyRoCC.scala:106:24] .io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[LazyRoCC.scala:106:24] .io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[LazyRoCC.scala:106:24] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_requestor_2_req_ready (_dcacheArb_io_requestor_2_req_ready), .io_requestor_2_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20] .io_requestor_2_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20] .io_requestor_2_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20] .io_requestor_2_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20] .io_requestor_2_s2_nack (_dcacheArb_io_requestor_2_s2_nack), .io_requestor_2_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw), .io_requestor_2_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached), .io_requestor_2_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr), .io_requestor_2_resp_valid (_dcacheArb_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr), .io_requestor_2_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag), .io_requestor_2_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd), .io_requestor_2_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size), .io_requestor_2_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed), .io_requestor_2_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv), .io_requestor_2_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv), .io_requestor_2_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data), .io_requestor_2_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask), .io_requestor_2_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay), .io_requestor_2_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data), .io_requestor_2_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass), .io_requestor_2_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw), .io_requestor_2_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data), .io_requestor_2_replay_next (_dcacheArb_io_requestor_2_replay_next), .io_requestor_2_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld), .io_requestor_2_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st), .io_requestor_2_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld), .io_requestor_2_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st), .io_requestor_2_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld), .io_requestor_2_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st), .io_requestor_2_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa), .io_requestor_2_ordered (_dcacheArb_io_requestor_2_ordered), .io_requestor_2_store_pending (_dcacheArb_io_requestor_2_store_pending), .io_requestor_2_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire), .io_requestor_2_perf_release (_dcacheArb_io_requestor_2_perf_release), .io_requestor_2_perf_grant (_dcacheArb_io_requestor_2_perf_grant), .io_requestor_2_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss), .io_requestor_2_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked), .io_requestor_2_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad), .io_requestor_2_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW), .io_requestor_2_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad), .io_requestor_2_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad), .io_requestor_2_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore), .io_requestor_2_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20] .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), .io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size), .io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43] .io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43] .io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled) ); // @[HellaCache.scala:292:25] PTW ptw ( // @[PTW.scala:802:19] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_zstd_compressor_io_ptw_0_req_valid), // @[Configs.scala:62:39] .io_requestor_0_req_bits_bits_addr (_zstd_compressor_io_ptw_0_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_0_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_0_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), .io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), .io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), .io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), .io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), .io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), .io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), .io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), .io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), .io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), .io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), .io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), .io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), .io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), .io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), .io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), .io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), .io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), .io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), .io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), .io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), .io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), .io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), .io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), .io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), .io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), .io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), .io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), .io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), .io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), .io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), .io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), .io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), .io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), .io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), .io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), .io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), .io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), .io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), .io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), .io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), .io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), .io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), .io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), .io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), .io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), .io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), .io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), .io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), .io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), .io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), .io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), .io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), .io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), .io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), .io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), .io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), .io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), .io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), .io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), .io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), .io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), .io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), .io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), .io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), .io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), .io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), .io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), .io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), .io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), .io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), .io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), .io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), .io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), .io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), .io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), .io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), .io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), .io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), .io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), .io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), .io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), .io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), .io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), .io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), .io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), .io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), .io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), .io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), .io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), .io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), .io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), .io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), .io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), .io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), .io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), .io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), .io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), .io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), .io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), .io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), .io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), .io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), .io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), .io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), .io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), .io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), .io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value), .io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready), .io_requestor_1_req_valid (_zstd_compressor_io_ptw_1_req_valid), // @[Configs.scala:62:39] .io_requestor_1_req_bits_bits_addr (_zstd_compressor_io_ptw_1_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_1_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_1_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), .io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), .io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), .io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), .io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), .io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), .io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), .io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), .io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), .io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), .io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), .io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), .io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), .io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), .io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), .io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), .io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), .io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), .io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), .io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), .io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), .io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), .io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), .io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), .io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), .io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug), .io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease), .io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi), .io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa), .io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv), .io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv), .io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv), .io_requestor_1_status_v (_ptw_io_requestor_1_status_v), .io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv), .io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva), .io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr), .io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw), .io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm), .io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr), .io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum), .io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv), .io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs), .io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp), .io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp), .io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie), .io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie), .io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie), .io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie), .io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), .io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), .io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), .io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), .io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), .io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), .io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), .io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), .io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), .io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), .io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v), .io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), .io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), .io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), .io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), .io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), .io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), .io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), .io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), .io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), .io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), .io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), .io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), .io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), .io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), .io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), .io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), .io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), .io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), .io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), .io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), .io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), .io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), .io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), .io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), .io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), .io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), .io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), .io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), .io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), .io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), .io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), .io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), .io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), .io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), .io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), .io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), .io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), .io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), .io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), .io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), .io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), .io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), .io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), .io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), .io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), .io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), .io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), .io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), .io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), .io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), .io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), .io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), .io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), .io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), .io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), .io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), .io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), .io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), .io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), .io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), .io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), .io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), .io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), .io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), .io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), .io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), .io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), .io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), .io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), .io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), .io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), .io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), .io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), .io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), .io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), .io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), .io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), .io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), .io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), .io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), .io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), .io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), .io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), .io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), .io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), .io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), .io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), .io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), .io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), .io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), .io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), .io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), .io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), .io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), .io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), .io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), .io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value), .io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready), .io_requestor_2_req_valid (_zstd_compressor_io_ptw_2_req_valid), // @[Configs.scala:62:39] .io_requestor_2_req_bits_bits_addr (_zstd_compressor_io_ptw_2_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_2_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_2_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid), .io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), .io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), .io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), .io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), .io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), .io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), .io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), .io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), .io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), .io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), .io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), .io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), .io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), .io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), .io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), .io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), .io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), .io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), .io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), .io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), .io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), .io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), .io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), .io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), .io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), .io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug), .io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease), .io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi), .io_requestor_2_status_isa (_ptw_io_requestor_2_status_isa), .io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv), .io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv), .io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv), .io_requestor_2_status_v (_ptw_io_requestor_2_status_v), .io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv), .io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva), .io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr), .io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw), .io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm), .io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr), .io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum), .io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv), .io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs), .io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp), .io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp), .io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie), .io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie), .io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie), .io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie), .io_requestor_2_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp), .io_requestor_2_hstatus_spv (_ptw_io_requestor_2_hstatus_spv), .io_requestor_2_hstatus_gva (_ptw_io_requestor_2_hstatus_gva), .io_requestor_2_gstatus_debug (_ptw_io_requestor_2_gstatus_debug), .io_requestor_2_gstatus_cease (_ptw_io_requestor_2_gstatus_cease), .io_requestor_2_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi), .io_requestor_2_gstatus_isa (_ptw_io_requestor_2_gstatus_isa), .io_requestor_2_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv), .io_requestor_2_gstatus_dv (_ptw_io_requestor_2_gstatus_dv), .io_requestor_2_gstatus_prv (_ptw_io_requestor_2_gstatus_prv), .io_requestor_2_gstatus_v (_ptw_io_requestor_2_gstatus_v), .io_requestor_2_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2), .io_requestor_2_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv), .io_requestor_2_gstatus_gva (_ptw_io_requestor_2_gstatus_gva), .io_requestor_2_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe), .io_requestor_2_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe), .io_requestor_2_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl), .io_requestor_2_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1), .io_requestor_2_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr), .io_requestor_2_gstatus_tw (_ptw_io_requestor_2_gstatus_tw), .io_requestor_2_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm), .io_requestor_2_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr), .io_requestor_2_gstatus_sum (_ptw_io_requestor_2_gstatus_sum), .io_requestor_2_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv), .io_requestor_2_gstatus_fs (_ptw_io_requestor_2_gstatus_fs), .io_requestor_2_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp), .io_requestor_2_gstatus_vs (_ptw_io_requestor_2_gstatus_vs), .io_requestor_2_gstatus_spp (_ptw_io_requestor_2_gstatus_spp), .io_requestor_2_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie), .io_requestor_2_gstatus_ube (_ptw_io_requestor_2_gstatus_ube), .io_requestor_2_gstatus_spie (_ptw_io_requestor_2_gstatus_spie), .io_requestor_2_gstatus_upie (_ptw_io_requestor_2_gstatus_upie), .io_requestor_2_gstatus_mie (_ptw_io_requestor_2_gstatus_mie), .io_requestor_2_gstatus_hie (_ptw_io_requestor_2_gstatus_hie), .io_requestor_2_gstatus_sie (_ptw_io_requestor_2_gstatus_sie), .io_requestor_2_gstatus_uie (_ptw_io_requestor_2_gstatus_uie), .io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), .io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), .io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), .io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), .io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), .io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), .io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), .io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), .io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), .io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), .io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), .io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), .io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), .io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), .io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), .io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), .io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), .io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), .io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), .io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), .io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), .io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), .io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), .io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), .io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), .io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), .io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), .io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), .io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), .io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), .io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), .io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), .io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), .io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), .io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), .io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), .io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), .io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), .io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), .io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), .io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), .io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), .io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), .io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), .io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), .io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), .io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), .io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), .io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), .io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), .io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), .io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), .io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), .io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), .io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), .io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), .io_requestor_2_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren), .io_requestor_2_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen), .io_requestor_2_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata), .io_requestor_2_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value), .io_requestor_2_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren), .io_requestor_2_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen), .io_requestor_2_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata), .io_requestor_2_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value), .io_requestor_2_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren), .io_requestor_2_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen), .io_requestor_2_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata), .io_requestor_2_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value), .io_requestor_2_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren), .io_requestor_2_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen), .io_requestor_2_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata), .io_requestor_2_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value), .io_requestor_3_req_ready (_ptw_io_requestor_3_req_ready), .io_requestor_3_req_valid (_zstd_compressor_io_ptw_3_req_valid), // @[Configs.scala:62:39] .io_requestor_3_req_bits_bits_addr (_zstd_compressor_io_ptw_3_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_3_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_3_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_3_resp_valid (_ptw_io_requestor_3_resp_valid), .io_requestor_3_resp_bits_ae_ptw (_ptw_io_requestor_3_resp_bits_ae_ptw), .io_requestor_3_resp_bits_ae_final (_ptw_io_requestor_3_resp_bits_ae_final), .io_requestor_3_resp_bits_pf (_ptw_io_requestor_3_resp_bits_pf), .io_requestor_3_resp_bits_gf (_ptw_io_requestor_3_resp_bits_gf), .io_requestor_3_resp_bits_hr (_ptw_io_requestor_3_resp_bits_hr), .io_requestor_3_resp_bits_hw (_ptw_io_requestor_3_resp_bits_hw), .io_requestor_3_resp_bits_hx (_ptw_io_requestor_3_resp_bits_hx), .io_requestor_3_resp_bits_pte_reserved_for_future (_ptw_io_requestor_3_resp_bits_pte_reserved_for_future), .io_requestor_3_resp_bits_pte_ppn (_ptw_io_requestor_3_resp_bits_pte_ppn), .io_requestor_3_resp_bits_pte_reserved_for_software (_ptw_io_requestor_3_resp_bits_pte_reserved_for_software), .io_requestor_3_resp_bits_pte_d (_ptw_io_requestor_3_resp_bits_pte_d), .io_requestor_3_resp_bits_pte_a (_ptw_io_requestor_3_resp_bits_pte_a), .io_requestor_3_resp_bits_pte_g (_ptw_io_requestor_3_resp_bits_pte_g), .io_requestor_3_resp_bits_pte_u (_ptw_io_requestor_3_resp_bits_pte_u), .io_requestor_3_resp_bits_pte_x (_ptw_io_requestor_3_resp_bits_pte_x), .io_requestor_3_resp_bits_pte_w (_ptw_io_requestor_3_resp_bits_pte_w), .io_requestor_3_resp_bits_pte_r (_ptw_io_requestor_3_resp_bits_pte_r), .io_requestor_3_resp_bits_pte_v (_ptw_io_requestor_3_resp_bits_pte_v), .io_requestor_3_resp_bits_level (_ptw_io_requestor_3_resp_bits_level), .io_requestor_3_resp_bits_homogeneous (_ptw_io_requestor_3_resp_bits_homogeneous), .io_requestor_3_resp_bits_gpa_valid (_ptw_io_requestor_3_resp_bits_gpa_valid), .io_requestor_3_resp_bits_gpa_bits (_ptw_io_requestor_3_resp_bits_gpa_bits), .io_requestor_3_resp_bits_gpa_is_pte (_ptw_io_requestor_3_resp_bits_gpa_is_pte), .io_requestor_3_ptbr_mode (_ptw_io_requestor_3_ptbr_mode), .io_requestor_3_ptbr_ppn (_ptw_io_requestor_3_ptbr_ppn), .io_requestor_3_status_debug (_ptw_io_requestor_3_status_debug), .io_requestor_3_status_cease (_ptw_io_requestor_3_status_cease), .io_requestor_3_status_wfi (_ptw_io_requestor_3_status_wfi), .io_requestor_3_status_isa (_ptw_io_requestor_3_status_isa), .io_requestor_3_status_dprv (_ptw_io_requestor_3_status_dprv), .io_requestor_3_status_dv (_ptw_io_requestor_3_status_dv), .io_requestor_3_status_prv (_ptw_io_requestor_3_status_prv), .io_requestor_3_status_v (_ptw_io_requestor_3_status_v), .io_requestor_3_status_mpv (_ptw_io_requestor_3_status_mpv), .io_requestor_3_status_gva (_ptw_io_requestor_3_status_gva), .io_requestor_3_status_tsr (_ptw_io_requestor_3_status_tsr), .io_requestor_3_status_tw (_ptw_io_requestor_3_status_tw), .io_requestor_3_status_tvm (_ptw_io_requestor_3_status_tvm), .io_requestor_3_status_mxr (_ptw_io_requestor_3_status_mxr), .io_requestor_3_status_sum (_ptw_io_requestor_3_status_sum), .io_requestor_3_status_mprv (_ptw_io_requestor_3_status_mprv), .io_requestor_3_status_fs (_ptw_io_requestor_3_status_fs), .io_requestor_3_status_mpp (_ptw_io_requestor_3_status_mpp), .io_requestor_3_status_spp (_ptw_io_requestor_3_status_spp), .io_requestor_3_status_mpie (_ptw_io_requestor_3_status_mpie), .io_requestor_3_status_spie (_ptw_io_requestor_3_status_spie), .io_requestor_3_status_mie (_ptw_io_requestor_3_status_mie), .io_requestor_3_status_sie (_ptw_io_requestor_3_status_sie), .io_requestor_3_hstatus_spvp (_ptw_io_requestor_3_hstatus_spvp), .io_requestor_3_hstatus_spv (_ptw_io_requestor_3_hstatus_spv), .io_requestor_3_hstatus_gva (_ptw_io_requestor_3_hstatus_gva), .io_requestor_3_gstatus_debug (_ptw_io_requestor_3_gstatus_debug), .io_requestor_3_gstatus_cease (_ptw_io_requestor_3_gstatus_cease), .io_requestor_3_gstatus_wfi (_ptw_io_requestor_3_gstatus_wfi), .io_requestor_3_gstatus_isa (_ptw_io_requestor_3_gstatus_isa), .io_requestor_3_gstatus_dprv (_ptw_io_requestor_3_gstatus_dprv), .io_requestor_3_gstatus_dv (_ptw_io_requestor_3_gstatus_dv), .io_requestor_3_gstatus_prv (_ptw_io_requestor_3_gstatus_prv), .io_requestor_3_gstatus_v (_ptw_io_requestor_3_gstatus_v), .io_requestor_3_gstatus_zero2 (_ptw_io_requestor_3_gstatus_zero2), .io_requestor_3_gstatus_mpv (_ptw_io_requestor_3_gstatus_mpv), .io_requestor_3_gstatus_gva (_ptw_io_requestor_3_gstatus_gva), .io_requestor_3_gstatus_mbe (_ptw_io_requestor_3_gstatus_mbe), .io_requestor_3_gstatus_sbe (_ptw_io_requestor_3_gstatus_sbe), .io_requestor_3_gstatus_sxl (_ptw_io_requestor_3_gstatus_sxl), .io_requestor_3_gstatus_zero1 (_ptw_io_requestor_3_gstatus_zero1), .io_requestor_3_gstatus_tsr (_ptw_io_requestor_3_gstatus_tsr), .io_requestor_3_gstatus_tw (_ptw_io_requestor_3_gstatus_tw), .io_requestor_3_gstatus_tvm (_ptw_io_requestor_3_gstatus_tvm), .io_requestor_3_gstatus_mxr (_ptw_io_requestor_3_gstatus_mxr), .io_requestor_3_gstatus_sum (_ptw_io_requestor_3_gstatus_sum), .io_requestor_3_gstatus_mprv (_ptw_io_requestor_3_gstatus_mprv), .io_requestor_3_gstatus_fs (_ptw_io_requestor_3_gstatus_fs), .io_requestor_3_gstatus_mpp (_ptw_io_requestor_3_gstatus_mpp), .io_requestor_3_gstatus_vs (_ptw_io_requestor_3_gstatus_vs), .io_requestor_3_gstatus_spp (_ptw_io_requestor_3_gstatus_spp), .io_requestor_3_gstatus_mpie (_ptw_io_requestor_3_gstatus_mpie), .io_requestor_3_gstatus_ube (_ptw_io_requestor_3_gstatus_ube), .io_requestor_3_gstatus_spie (_ptw_io_requestor_3_gstatus_spie), .io_requestor_3_gstatus_upie (_ptw_io_requestor_3_gstatus_upie), .io_requestor_3_gstatus_mie (_ptw_io_requestor_3_gstatus_mie), .io_requestor_3_gstatus_hie (_ptw_io_requestor_3_gstatus_hie), .io_requestor_3_gstatus_sie (_ptw_io_requestor_3_gstatus_sie), .io_requestor_3_gstatus_uie (_ptw_io_requestor_3_gstatus_uie), .io_requestor_3_pmp_0_cfg_l (_ptw_io_requestor_3_pmp_0_cfg_l), .io_requestor_3_pmp_0_cfg_a (_ptw_io_requestor_3_pmp_0_cfg_a), .io_requestor_3_pmp_0_cfg_x (_ptw_io_requestor_3_pmp_0_cfg_x), .io_requestor_3_pmp_0_cfg_w (_ptw_io_requestor_3_pmp_0_cfg_w), .io_requestor_3_pmp_0_cfg_r (_ptw_io_requestor_3_pmp_0_cfg_r), .io_requestor_3_pmp_0_addr (_ptw_io_requestor_3_pmp_0_addr), .io_requestor_3_pmp_0_mask (_ptw_io_requestor_3_pmp_0_mask), .io_requestor_3_pmp_1_cfg_l (_ptw_io_requestor_3_pmp_1_cfg_l), .io_requestor_3_pmp_1_cfg_a (_ptw_io_requestor_3_pmp_1_cfg_a), .io_requestor_3_pmp_1_cfg_x (_ptw_io_requestor_3_pmp_1_cfg_x), .io_requestor_3_pmp_1_cfg_w (_ptw_io_requestor_3_pmp_1_cfg_w), .io_requestor_3_pmp_1_cfg_r (_ptw_io_requestor_3_pmp_1_cfg_r), .io_requestor_3_pmp_1_addr (_ptw_io_requestor_3_pmp_1_addr), .io_requestor_3_pmp_1_mask (_ptw_io_requestor_3_pmp_1_mask), .io_requestor_3_pmp_2_cfg_l (_ptw_io_requestor_3_pmp_2_cfg_l), .io_requestor_3_pmp_2_cfg_a (_ptw_io_requestor_3_pmp_2_cfg_a), .io_requestor_3_pmp_2_cfg_x (_ptw_io_requestor_3_pmp_2_cfg_x), .io_requestor_3_pmp_2_cfg_w (_ptw_io_requestor_3_pmp_2_cfg_w), .io_requestor_3_pmp_2_cfg_r (_ptw_io_requestor_3_pmp_2_cfg_r), .io_requestor_3_pmp_2_addr (_ptw_io_requestor_3_pmp_2_addr), .io_requestor_3_pmp_2_mask (_ptw_io_requestor_3_pmp_2_mask), .io_requestor_3_pmp_3_cfg_l (_ptw_io_requestor_3_pmp_3_cfg_l), .io_requestor_3_pmp_3_cfg_a (_ptw_io_requestor_3_pmp_3_cfg_a), .io_requestor_3_pmp_3_cfg_x (_ptw_io_requestor_3_pmp_3_cfg_x), .io_requestor_3_pmp_3_cfg_w (_ptw_io_requestor_3_pmp_3_cfg_w), .io_requestor_3_pmp_3_cfg_r (_ptw_io_requestor_3_pmp_3_cfg_r), .io_requestor_3_pmp_3_addr (_ptw_io_requestor_3_pmp_3_addr), .io_requestor_3_pmp_3_mask (_ptw_io_requestor_3_pmp_3_mask), .io_requestor_3_pmp_4_cfg_l (_ptw_io_requestor_3_pmp_4_cfg_l), .io_requestor_3_pmp_4_cfg_a (_ptw_io_requestor_3_pmp_4_cfg_a), .io_requestor_3_pmp_4_cfg_x (_ptw_io_requestor_3_pmp_4_cfg_x), .io_requestor_3_pmp_4_cfg_w (_ptw_io_requestor_3_pmp_4_cfg_w), .io_requestor_3_pmp_4_cfg_r (_ptw_io_requestor_3_pmp_4_cfg_r), .io_requestor_3_pmp_4_addr (_ptw_io_requestor_3_pmp_4_addr), .io_requestor_3_pmp_4_mask (_ptw_io_requestor_3_pmp_4_mask), .io_requestor_3_pmp_5_cfg_l (_ptw_io_requestor_3_pmp_5_cfg_l), .io_requestor_3_pmp_5_cfg_a (_ptw_io_requestor_3_pmp_5_cfg_a), .io_requestor_3_pmp_5_cfg_x (_ptw_io_requestor_3_pmp_5_cfg_x), .io_requestor_3_pmp_5_cfg_w (_ptw_io_requestor_3_pmp_5_cfg_w), .io_requestor_3_pmp_5_cfg_r (_ptw_io_requestor_3_pmp_5_cfg_r), .io_requestor_3_pmp_5_addr (_ptw_io_requestor_3_pmp_5_addr), .io_requestor_3_pmp_5_mask (_ptw_io_requestor_3_pmp_5_mask), .io_requestor_3_pmp_6_cfg_l (_ptw_io_requestor_3_pmp_6_cfg_l), .io_requestor_3_pmp_6_cfg_a (_ptw_io_requestor_3_pmp_6_cfg_a), .io_requestor_3_pmp_6_cfg_x (_ptw_io_requestor_3_pmp_6_cfg_x), .io_requestor_3_pmp_6_cfg_w (_ptw_io_requestor_3_pmp_6_cfg_w), .io_requestor_3_pmp_6_cfg_r (_ptw_io_requestor_3_pmp_6_cfg_r), .io_requestor_3_pmp_6_addr (_ptw_io_requestor_3_pmp_6_addr), .io_requestor_3_pmp_6_mask (_ptw_io_requestor_3_pmp_6_mask), .io_requestor_3_pmp_7_cfg_l (_ptw_io_requestor_3_pmp_7_cfg_l), .io_requestor_3_pmp_7_cfg_a (_ptw_io_requestor_3_pmp_7_cfg_a), .io_requestor_3_pmp_7_cfg_x (_ptw_io_requestor_3_pmp_7_cfg_x), .io_requestor_3_pmp_7_cfg_w (_ptw_io_requestor_3_pmp_7_cfg_w), .io_requestor_3_pmp_7_cfg_r (_ptw_io_requestor_3_pmp_7_cfg_r), .io_requestor_3_pmp_7_addr (_ptw_io_requestor_3_pmp_7_addr), .io_requestor_3_pmp_7_mask (_ptw_io_requestor_3_pmp_7_mask), .io_requestor_3_customCSRs_csrs_0_ren (_ptw_io_requestor_3_customCSRs_csrs_0_ren), .io_requestor_3_customCSRs_csrs_0_wen (_ptw_io_requestor_3_customCSRs_csrs_0_wen), .io_requestor_3_customCSRs_csrs_0_wdata (_ptw_io_requestor_3_customCSRs_csrs_0_wdata), .io_requestor_3_customCSRs_csrs_0_value (_ptw_io_requestor_3_customCSRs_csrs_0_value), .io_requestor_3_customCSRs_csrs_1_ren (_ptw_io_requestor_3_customCSRs_csrs_1_ren), .io_requestor_3_customCSRs_csrs_1_wen (_ptw_io_requestor_3_customCSRs_csrs_1_wen), .io_requestor_3_customCSRs_csrs_1_wdata (_ptw_io_requestor_3_customCSRs_csrs_1_wdata), .io_requestor_3_customCSRs_csrs_1_value (_ptw_io_requestor_3_customCSRs_csrs_1_value), .io_requestor_3_customCSRs_csrs_2_ren (_ptw_io_requestor_3_customCSRs_csrs_2_ren), .io_requestor_3_customCSRs_csrs_2_wen (_ptw_io_requestor_3_customCSRs_csrs_2_wen), .io_requestor_3_customCSRs_csrs_2_wdata (_ptw_io_requestor_3_customCSRs_csrs_2_wdata), .io_requestor_3_customCSRs_csrs_2_value (_ptw_io_requestor_3_customCSRs_csrs_2_value), .io_requestor_3_customCSRs_csrs_3_ren (_ptw_io_requestor_3_customCSRs_csrs_3_ren), .io_requestor_3_customCSRs_csrs_3_wen (_ptw_io_requestor_3_customCSRs_csrs_3_wen), .io_requestor_3_customCSRs_csrs_3_wdata (_ptw_io_requestor_3_customCSRs_csrs_3_wdata), .io_requestor_3_customCSRs_csrs_3_value (_ptw_io_requestor_3_customCSRs_csrs_3_value), .io_requestor_4_req_ready (_ptw_io_requestor_4_req_ready), .io_requestor_4_req_valid (_zstd_compressor_io_ptw_4_req_valid), // @[Configs.scala:62:39] .io_requestor_4_req_bits_bits_addr (_zstd_compressor_io_ptw_4_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_4_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_4_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_4_resp_valid (_ptw_io_requestor_4_resp_valid), .io_requestor_4_resp_bits_ae_ptw (_ptw_io_requestor_4_resp_bits_ae_ptw), .io_requestor_4_resp_bits_ae_final (_ptw_io_requestor_4_resp_bits_ae_final), .io_requestor_4_resp_bits_pf (_ptw_io_requestor_4_resp_bits_pf), .io_requestor_4_resp_bits_gf (_ptw_io_requestor_4_resp_bits_gf), .io_requestor_4_resp_bits_hr (_ptw_io_requestor_4_resp_bits_hr), .io_requestor_4_resp_bits_hw (_ptw_io_requestor_4_resp_bits_hw), .io_requestor_4_resp_bits_hx (_ptw_io_requestor_4_resp_bits_hx), .io_requestor_4_resp_bits_pte_reserved_for_future (_ptw_io_requestor_4_resp_bits_pte_reserved_for_future), .io_requestor_4_resp_bits_pte_ppn (_ptw_io_requestor_4_resp_bits_pte_ppn), .io_requestor_4_resp_bits_pte_reserved_for_software (_ptw_io_requestor_4_resp_bits_pte_reserved_for_software), .io_requestor_4_resp_bits_pte_d (_ptw_io_requestor_4_resp_bits_pte_d), .io_requestor_4_resp_bits_pte_a (_ptw_io_requestor_4_resp_bits_pte_a), .io_requestor_4_resp_bits_pte_g (_ptw_io_requestor_4_resp_bits_pte_g), .io_requestor_4_resp_bits_pte_u (_ptw_io_requestor_4_resp_bits_pte_u), .io_requestor_4_resp_bits_pte_x (_ptw_io_requestor_4_resp_bits_pte_x), .io_requestor_4_resp_bits_pte_w (_ptw_io_requestor_4_resp_bits_pte_w), .io_requestor_4_resp_bits_pte_r (_ptw_io_requestor_4_resp_bits_pte_r), .io_requestor_4_resp_bits_pte_v (_ptw_io_requestor_4_resp_bits_pte_v), .io_requestor_4_resp_bits_level (_ptw_io_requestor_4_resp_bits_level), .io_requestor_4_resp_bits_homogeneous (_ptw_io_requestor_4_resp_bits_homogeneous), .io_requestor_4_resp_bits_gpa_valid (_ptw_io_requestor_4_resp_bits_gpa_valid), .io_requestor_4_resp_bits_gpa_bits (_ptw_io_requestor_4_resp_bits_gpa_bits), .io_requestor_4_resp_bits_gpa_is_pte (_ptw_io_requestor_4_resp_bits_gpa_is_pte), .io_requestor_4_ptbr_mode (_ptw_io_requestor_4_ptbr_mode), .io_requestor_4_ptbr_ppn (_ptw_io_requestor_4_ptbr_ppn), .io_requestor_4_status_debug (_ptw_io_requestor_4_status_debug), .io_requestor_4_status_cease (_ptw_io_requestor_4_status_cease), .io_requestor_4_status_wfi (_ptw_io_requestor_4_status_wfi), .io_requestor_4_status_isa (_ptw_io_requestor_4_status_isa), .io_requestor_4_status_dprv (_ptw_io_requestor_4_status_dprv), .io_requestor_4_status_dv (_ptw_io_requestor_4_status_dv), .io_requestor_4_status_prv (_ptw_io_requestor_4_status_prv), .io_requestor_4_status_v (_ptw_io_requestor_4_status_v), .io_requestor_4_status_mpv (_ptw_io_requestor_4_status_mpv), .io_requestor_4_status_gva (_ptw_io_requestor_4_status_gva), .io_requestor_4_status_tsr (_ptw_io_requestor_4_status_tsr), .io_requestor_4_status_tw (_ptw_io_requestor_4_status_tw), .io_requestor_4_status_tvm (_ptw_io_requestor_4_status_tvm), .io_requestor_4_status_mxr (_ptw_io_requestor_4_status_mxr), .io_requestor_4_status_sum (_ptw_io_requestor_4_status_sum), .io_requestor_4_status_mprv (_ptw_io_requestor_4_status_mprv), .io_requestor_4_status_fs (_ptw_io_requestor_4_status_fs), .io_requestor_4_status_mpp (_ptw_io_requestor_4_status_mpp), .io_requestor_4_status_spp (_ptw_io_requestor_4_status_spp), .io_requestor_4_status_mpie (_ptw_io_requestor_4_status_mpie), .io_requestor_4_status_spie (_ptw_io_requestor_4_status_spie), .io_requestor_4_status_mie (_ptw_io_requestor_4_status_mie), .io_requestor_4_status_sie (_ptw_io_requestor_4_status_sie), .io_requestor_4_hstatus_spvp (_ptw_io_requestor_4_hstatus_spvp), .io_requestor_4_hstatus_spv (_ptw_io_requestor_4_hstatus_spv), .io_requestor_4_hstatus_gva (_ptw_io_requestor_4_hstatus_gva), .io_requestor_4_gstatus_debug (_ptw_io_requestor_4_gstatus_debug), .io_requestor_4_gstatus_cease (_ptw_io_requestor_4_gstatus_cease), .io_requestor_4_gstatus_wfi (_ptw_io_requestor_4_gstatus_wfi), .io_requestor_4_gstatus_isa (_ptw_io_requestor_4_gstatus_isa), .io_requestor_4_gstatus_dprv (_ptw_io_requestor_4_gstatus_dprv), .io_requestor_4_gstatus_dv (_ptw_io_requestor_4_gstatus_dv), .io_requestor_4_gstatus_prv (_ptw_io_requestor_4_gstatus_prv), .io_requestor_4_gstatus_v (_ptw_io_requestor_4_gstatus_v), .io_requestor_4_gstatus_zero2 (_ptw_io_requestor_4_gstatus_zero2), .io_requestor_4_gstatus_mpv (_ptw_io_requestor_4_gstatus_mpv), .io_requestor_4_gstatus_gva (_ptw_io_requestor_4_gstatus_gva), .io_requestor_4_gstatus_mbe (_ptw_io_requestor_4_gstatus_mbe), .io_requestor_4_gstatus_sbe (_ptw_io_requestor_4_gstatus_sbe), .io_requestor_4_gstatus_sxl (_ptw_io_requestor_4_gstatus_sxl), .io_requestor_4_gstatus_zero1 (_ptw_io_requestor_4_gstatus_zero1), .io_requestor_4_gstatus_tsr (_ptw_io_requestor_4_gstatus_tsr), .io_requestor_4_gstatus_tw (_ptw_io_requestor_4_gstatus_tw), .io_requestor_4_gstatus_tvm (_ptw_io_requestor_4_gstatus_tvm), .io_requestor_4_gstatus_mxr (_ptw_io_requestor_4_gstatus_mxr), .io_requestor_4_gstatus_sum (_ptw_io_requestor_4_gstatus_sum), .io_requestor_4_gstatus_mprv (_ptw_io_requestor_4_gstatus_mprv), .io_requestor_4_gstatus_fs (_ptw_io_requestor_4_gstatus_fs), .io_requestor_4_gstatus_mpp (_ptw_io_requestor_4_gstatus_mpp), .io_requestor_4_gstatus_vs (_ptw_io_requestor_4_gstatus_vs), .io_requestor_4_gstatus_spp (_ptw_io_requestor_4_gstatus_spp), .io_requestor_4_gstatus_mpie (_ptw_io_requestor_4_gstatus_mpie), .io_requestor_4_gstatus_ube (_ptw_io_requestor_4_gstatus_ube), .io_requestor_4_gstatus_spie (_ptw_io_requestor_4_gstatus_spie), .io_requestor_4_gstatus_upie (_ptw_io_requestor_4_gstatus_upie), .io_requestor_4_gstatus_mie (_ptw_io_requestor_4_gstatus_mie), .io_requestor_4_gstatus_hie (_ptw_io_requestor_4_gstatus_hie), .io_requestor_4_gstatus_sie (_ptw_io_requestor_4_gstatus_sie), .io_requestor_4_gstatus_uie (_ptw_io_requestor_4_gstatus_uie), .io_requestor_4_pmp_0_cfg_l (_ptw_io_requestor_4_pmp_0_cfg_l), .io_requestor_4_pmp_0_cfg_a (_ptw_io_requestor_4_pmp_0_cfg_a), .io_requestor_4_pmp_0_cfg_x (_ptw_io_requestor_4_pmp_0_cfg_x), .io_requestor_4_pmp_0_cfg_w (_ptw_io_requestor_4_pmp_0_cfg_w), .io_requestor_4_pmp_0_cfg_r (_ptw_io_requestor_4_pmp_0_cfg_r), .io_requestor_4_pmp_0_addr (_ptw_io_requestor_4_pmp_0_addr), .io_requestor_4_pmp_0_mask (_ptw_io_requestor_4_pmp_0_mask), .io_requestor_4_pmp_1_cfg_l (_ptw_io_requestor_4_pmp_1_cfg_l), .io_requestor_4_pmp_1_cfg_a (_ptw_io_requestor_4_pmp_1_cfg_a), .io_requestor_4_pmp_1_cfg_x (_ptw_io_requestor_4_pmp_1_cfg_x), .io_requestor_4_pmp_1_cfg_w (_ptw_io_requestor_4_pmp_1_cfg_w), .io_requestor_4_pmp_1_cfg_r (_ptw_io_requestor_4_pmp_1_cfg_r), .io_requestor_4_pmp_1_addr (_ptw_io_requestor_4_pmp_1_addr), .io_requestor_4_pmp_1_mask (_ptw_io_requestor_4_pmp_1_mask), .io_requestor_4_pmp_2_cfg_l (_ptw_io_requestor_4_pmp_2_cfg_l), .io_requestor_4_pmp_2_cfg_a (_ptw_io_requestor_4_pmp_2_cfg_a), .io_requestor_4_pmp_2_cfg_x (_ptw_io_requestor_4_pmp_2_cfg_x), .io_requestor_4_pmp_2_cfg_w (_ptw_io_requestor_4_pmp_2_cfg_w), .io_requestor_4_pmp_2_cfg_r (_ptw_io_requestor_4_pmp_2_cfg_r), .io_requestor_4_pmp_2_addr (_ptw_io_requestor_4_pmp_2_addr), .io_requestor_4_pmp_2_mask (_ptw_io_requestor_4_pmp_2_mask), .io_requestor_4_pmp_3_cfg_l (_ptw_io_requestor_4_pmp_3_cfg_l), .io_requestor_4_pmp_3_cfg_a (_ptw_io_requestor_4_pmp_3_cfg_a), .io_requestor_4_pmp_3_cfg_x (_ptw_io_requestor_4_pmp_3_cfg_x), .io_requestor_4_pmp_3_cfg_w (_ptw_io_requestor_4_pmp_3_cfg_w), .io_requestor_4_pmp_3_cfg_r (_ptw_io_requestor_4_pmp_3_cfg_r), .io_requestor_4_pmp_3_addr (_ptw_io_requestor_4_pmp_3_addr), .io_requestor_4_pmp_3_mask (_ptw_io_requestor_4_pmp_3_mask), .io_requestor_4_pmp_4_cfg_l (_ptw_io_requestor_4_pmp_4_cfg_l), .io_requestor_4_pmp_4_cfg_a (_ptw_io_requestor_4_pmp_4_cfg_a), .io_requestor_4_pmp_4_cfg_x (_ptw_io_requestor_4_pmp_4_cfg_x), .io_requestor_4_pmp_4_cfg_w (_ptw_io_requestor_4_pmp_4_cfg_w), .io_requestor_4_pmp_4_cfg_r (_ptw_io_requestor_4_pmp_4_cfg_r), .io_requestor_4_pmp_4_addr (_ptw_io_requestor_4_pmp_4_addr), .io_requestor_4_pmp_4_mask (_ptw_io_requestor_4_pmp_4_mask), .io_requestor_4_pmp_5_cfg_l (_ptw_io_requestor_4_pmp_5_cfg_l), .io_requestor_4_pmp_5_cfg_a (_ptw_io_requestor_4_pmp_5_cfg_a), .io_requestor_4_pmp_5_cfg_x (_ptw_io_requestor_4_pmp_5_cfg_x), .io_requestor_4_pmp_5_cfg_w (_ptw_io_requestor_4_pmp_5_cfg_w), .io_requestor_4_pmp_5_cfg_r (_ptw_io_requestor_4_pmp_5_cfg_r), .io_requestor_4_pmp_5_addr (_ptw_io_requestor_4_pmp_5_addr), .io_requestor_4_pmp_5_mask (_ptw_io_requestor_4_pmp_5_mask), .io_requestor_4_pmp_6_cfg_l (_ptw_io_requestor_4_pmp_6_cfg_l), .io_requestor_4_pmp_6_cfg_a (_ptw_io_requestor_4_pmp_6_cfg_a), .io_requestor_4_pmp_6_cfg_x (_ptw_io_requestor_4_pmp_6_cfg_x), .io_requestor_4_pmp_6_cfg_w (_ptw_io_requestor_4_pmp_6_cfg_w), .io_requestor_4_pmp_6_cfg_r (_ptw_io_requestor_4_pmp_6_cfg_r), .io_requestor_4_pmp_6_addr (_ptw_io_requestor_4_pmp_6_addr), .io_requestor_4_pmp_6_mask (_ptw_io_requestor_4_pmp_6_mask), .io_requestor_4_pmp_7_cfg_l (_ptw_io_requestor_4_pmp_7_cfg_l), .io_requestor_4_pmp_7_cfg_a (_ptw_io_requestor_4_pmp_7_cfg_a), .io_requestor_4_pmp_7_cfg_x (_ptw_io_requestor_4_pmp_7_cfg_x), .io_requestor_4_pmp_7_cfg_w (_ptw_io_requestor_4_pmp_7_cfg_w), .io_requestor_4_pmp_7_cfg_r (_ptw_io_requestor_4_pmp_7_cfg_r), .io_requestor_4_pmp_7_addr (_ptw_io_requestor_4_pmp_7_addr), .io_requestor_4_pmp_7_mask (_ptw_io_requestor_4_pmp_7_mask), .io_requestor_4_customCSRs_csrs_0_ren (_ptw_io_requestor_4_customCSRs_csrs_0_ren), .io_requestor_4_customCSRs_csrs_0_wen (_ptw_io_requestor_4_customCSRs_csrs_0_wen), .io_requestor_4_customCSRs_csrs_0_wdata (_ptw_io_requestor_4_customCSRs_csrs_0_wdata), .io_requestor_4_customCSRs_csrs_0_value (_ptw_io_requestor_4_customCSRs_csrs_0_value), .io_requestor_4_customCSRs_csrs_1_ren (_ptw_io_requestor_4_customCSRs_csrs_1_ren), .io_requestor_4_customCSRs_csrs_1_wen (_ptw_io_requestor_4_customCSRs_csrs_1_wen), .io_requestor_4_customCSRs_csrs_1_wdata (_ptw_io_requestor_4_customCSRs_csrs_1_wdata), .io_requestor_4_customCSRs_csrs_1_value (_ptw_io_requestor_4_customCSRs_csrs_1_value), .io_requestor_4_customCSRs_csrs_2_ren (_ptw_io_requestor_4_customCSRs_csrs_2_ren), .io_requestor_4_customCSRs_csrs_2_wen (_ptw_io_requestor_4_customCSRs_csrs_2_wen), .io_requestor_4_customCSRs_csrs_2_wdata (_ptw_io_requestor_4_customCSRs_csrs_2_wdata), .io_requestor_4_customCSRs_csrs_2_value (_ptw_io_requestor_4_customCSRs_csrs_2_value), .io_requestor_4_customCSRs_csrs_3_ren (_ptw_io_requestor_4_customCSRs_csrs_3_ren), .io_requestor_4_customCSRs_csrs_3_wen (_ptw_io_requestor_4_customCSRs_csrs_3_wen), .io_requestor_4_customCSRs_csrs_3_wdata (_ptw_io_requestor_4_customCSRs_csrs_3_wdata), .io_requestor_4_customCSRs_csrs_3_value (_ptw_io_requestor_4_customCSRs_csrs_3_value), .io_requestor_5_req_ready (_ptw_io_requestor_5_req_ready), .io_requestor_5_req_valid (_zstd_compressor_io_ptw_5_req_valid), // @[Configs.scala:62:39] .io_requestor_5_req_bits_bits_addr (_zstd_compressor_io_ptw_5_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_5_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_5_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_5_resp_valid (_ptw_io_requestor_5_resp_valid), .io_requestor_5_resp_bits_ae_ptw (_ptw_io_requestor_5_resp_bits_ae_ptw), .io_requestor_5_resp_bits_ae_final (_ptw_io_requestor_5_resp_bits_ae_final), .io_requestor_5_resp_bits_pf (_ptw_io_requestor_5_resp_bits_pf), .io_requestor_5_resp_bits_gf (_ptw_io_requestor_5_resp_bits_gf), .io_requestor_5_resp_bits_hr (_ptw_io_requestor_5_resp_bits_hr), .io_requestor_5_resp_bits_hw (_ptw_io_requestor_5_resp_bits_hw), .io_requestor_5_resp_bits_hx (_ptw_io_requestor_5_resp_bits_hx), .io_requestor_5_resp_bits_pte_reserved_for_future (_ptw_io_requestor_5_resp_bits_pte_reserved_for_future), .io_requestor_5_resp_bits_pte_ppn (_ptw_io_requestor_5_resp_bits_pte_ppn), .io_requestor_5_resp_bits_pte_reserved_for_software (_ptw_io_requestor_5_resp_bits_pte_reserved_for_software), .io_requestor_5_resp_bits_pte_d (_ptw_io_requestor_5_resp_bits_pte_d), .io_requestor_5_resp_bits_pte_a (_ptw_io_requestor_5_resp_bits_pte_a), .io_requestor_5_resp_bits_pte_g (_ptw_io_requestor_5_resp_bits_pte_g), .io_requestor_5_resp_bits_pte_u (_ptw_io_requestor_5_resp_bits_pte_u), .io_requestor_5_resp_bits_pte_x (_ptw_io_requestor_5_resp_bits_pte_x), .io_requestor_5_resp_bits_pte_w (_ptw_io_requestor_5_resp_bits_pte_w), .io_requestor_5_resp_bits_pte_r (_ptw_io_requestor_5_resp_bits_pte_r), .io_requestor_5_resp_bits_pte_v (_ptw_io_requestor_5_resp_bits_pte_v), .io_requestor_5_resp_bits_level (_ptw_io_requestor_5_resp_bits_level), .io_requestor_5_resp_bits_homogeneous (_ptw_io_requestor_5_resp_bits_homogeneous), .io_requestor_5_resp_bits_gpa_valid (_ptw_io_requestor_5_resp_bits_gpa_valid), .io_requestor_5_resp_bits_gpa_bits (_ptw_io_requestor_5_resp_bits_gpa_bits), .io_requestor_5_resp_bits_gpa_is_pte (_ptw_io_requestor_5_resp_bits_gpa_is_pte), .io_requestor_5_ptbr_mode (_ptw_io_requestor_5_ptbr_mode), .io_requestor_5_ptbr_ppn (_ptw_io_requestor_5_ptbr_ppn), .io_requestor_5_status_debug (_ptw_io_requestor_5_status_debug), .io_requestor_5_status_cease (_ptw_io_requestor_5_status_cease), .io_requestor_5_status_wfi (_ptw_io_requestor_5_status_wfi), .io_requestor_5_status_isa (_ptw_io_requestor_5_status_isa), .io_requestor_5_status_dprv (_ptw_io_requestor_5_status_dprv), .io_requestor_5_status_dv (_ptw_io_requestor_5_status_dv), .io_requestor_5_status_prv (_ptw_io_requestor_5_status_prv), .io_requestor_5_status_v (_ptw_io_requestor_5_status_v), .io_requestor_5_status_mpv (_ptw_io_requestor_5_status_mpv), .io_requestor_5_status_gva (_ptw_io_requestor_5_status_gva), .io_requestor_5_status_tsr (_ptw_io_requestor_5_status_tsr), .io_requestor_5_status_tw (_ptw_io_requestor_5_status_tw), .io_requestor_5_status_tvm (_ptw_io_requestor_5_status_tvm), .io_requestor_5_status_mxr (_ptw_io_requestor_5_status_mxr), .io_requestor_5_status_sum (_ptw_io_requestor_5_status_sum), .io_requestor_5_status_mprv (_ptw_io_requestor_5_status_mprv), .io_requestor_5_status_fs (_ptw_io_requestor_5_status_fs), .io_requestor_5_status_mpp (_ptw_io_requestor_5_status_mpp), .io_requestor_5_status_spp (_ptw_io_requestor_5_status_spp), .io_requestor_5_status_mpie (_ptw_io_requestor_5_status_mpie), .io_requestor_5_status_spie (_ptw_io_requestor_5_status_spie), .io_requestor_5_status_mie (_ptw_io_requestor_5_status_mie), .io_requestor_5_status_sie (_ptw_io_requestor_5_status_sie), .io_requestor_5_hstatus_spvp (_ptw_io_requestor_5_hstatus_spvp), .io_requestor_5_hstatus_spv (_ptw_io_requestor_5_hstatus_spv), .io_requestor_5_hstatus_gva (_ptw_io_requestor_5_hstatus_gva), .io_requestor_5_gstatus_debug (_ptw_io_requestor_5_gstatus_debug), .io_requestor_5_gstatus_cease (_ptw_io_requestor_5_gstatus_cease), .io_requestor_5_gstatus_wfi (_ptw_io_requestor_5_gstatus_wfi), .io_requestor_5_gstatus_isa (_ptw_io_requestor_5_gstatus_isa), .io_requestor_5_gstatus_dprv (_ptw_io_requestor_5_gstatus_dprv), .io_requestor_5_gstatus_dv (_ptw_io_requestor_5_gstatus_dv), .io_requestor_5_gstatus_prv (_ptw_io_requestor_5_gstatus_prv), .io_requestor_5_gstatus_v (_ptw_io_requestor_5_gstatus_v), .io_requestor_5_gstatus_zero2 (_ptw_io_requestor_5_gstatus_zero2), .io_requestor_5_gstatus_mpv (_ptw_io_requestor_5_gstatus_mpv), .io_requestor_5_gstatus_gva (_ptw_io_requestor_5_gstatus_gva), .io_requestor_5_gstatus_mbe (_ptw_io_requestor_5_gstatus_mbe), .io_requestor_5_gstatus_sbe (_ptw_io_requestor_5_gstatus_sbe), .io_requestor_5_gstatus_sxl (_ptw_io_requestor_5_gstatus_sxl), .io_requestor_5_gstatus_zero1 (_ptw_io_requestor_5_gstatus_zero1), .io_requestor_5_gstatus_tsr (_ptw_io_requestor_5_gstatus_tsr), .io_requestor_5_gstatus_tw (_ptw_io_requestor_5_gstatus_tw), .io_requestor_5_gstatus_tvm (_ptw_io_requestor_5_gstatus_tvm), .io_requestor_5_gstatus_mxr (_ptw_io_requestor_5_gstatus_mxr), .io_requestor_5_gstatus_sum (_ptw_io_requestor_5_gstatus_sum), .io_requestor_5_gstatus_mprv (_ptw_io_requestor_5_gstatus_mprv), .io_requestor_5_gstatus_fs (_ptw_io_requestor_5_gstatus_fs), .io_requestor_5_gstatus_mpp (_ptw_io_requestor_5_gstatus_mpp), .io_requestor_5_gstatus_vs (_ptw_io_requestor_5_gstatus_vs), .io_requestor_5_gstatus_spp (_ptw_io_requestor_5_gstatus_spp), .io_requestor_5_gstatus_mpie (_ptw_io_requestor_5_gstatus_mpie), .io_requestor_5_gstatus_ube (_ptw_io_requestor_5_gstatus_ube), .io_requestor_5_gstatus_spie (_ptw_io_requestor_5_gstatus_spie), .io_requestor_5_gstatus_upie (_ptw_io_requestor_5_gstatus_upie), .io_requestor_5_gstatus_mie (_ptw_io_requestor_5_gstatus_mie), .io_requestor_5_gstatus_hie (_ptw_io_requestor_5_gstatus_hie), .io_requestor_5_gstatus_sie (_ptw_io_requestor_5_gstatus_sie), .io_requestor_5_gstatus_uie (_ptw_io_requestor_5_gstatus_uie), .io_requestor_5_pmp_0_cfg_l (_ptw_io_requestor_5_pmp_0_cfg_l), .io_requestor_5_pmp_0_cfg_a (_ptw_io_requestor_5_pmp_0_cfg_a), .io_requestor_5_pmp_0_cfg_x (_ptw_io_requestor_5_pmp_0_cfg_x), .io_requestor_5_pmp_0_cfg_w (_ptw_io_requestor_5_pmp_0_cfg_w), .io_requestor_5_pmp_0_cfg_r (_ptw_io_requestor_5_pmp_0_cfg_r), .io_requestor_5_pmp_0_addr (_ptw_io_requestor_5_pmp_0_addr), .io_requestor_5_pmp_0_mask (_ptw_io_requestor_5_pmp_0_mask), .io_requestor_5_pmp_1_cfg_l (_ptw_io_requestor_5_pmp_1_cfg_l), .io_requestor_5_pmp_1_cfg_a (_ptw_io_requestor_5_pmp_1_cfg_a), .io_requestor_5_pmp_1_cfg_x (_ptw_io_requestor_5_pmp_1_cfg_x), .io_requestor_5_pmp_1_cfg_w (_ptw_io_requestor_5_pmp_1_cfg_w), .io_requestor_5_pmp_1_cfg_r (_ptw_io_requestor_5_pmp_1_cfg_r), .io_requestor_5_pmp_1_addr (_ptw_io_requestor_5_pmp_1_addr), .io_requestor_5_pmp_1_mask (_ptw_io_requestor_5_pmp_1_mask), .io_requestor_5_pmp_2_cfg_l (_ptw_io_requestor_5_pmp_2_cfg_l), .io_requestor_5_pmp_2_cfg_a (_ptw_io_requestor_5_pmp_2_cfg_a), .io_requestor_5_pmp_2_cfg_x (_ptw_io_requestor_5_pmp_2_cfg_x), .io_requestor_5_pmp_2_cfg_w (_ptw_io_requestor_5_pmp_2_cfg_w), .io_requestor_5_pmp_2_cfg_r (_ptw_io_requestor_5_pmp_2_cfg_r), .io_requestor_5_pmp_2_addr (_ptw_io_requestor_5_pmp_2_addr), .io_requestor_5_pmp_2_mask (_ptw_io_requestor_5_pmp_2_mask), .io_requestor_5_pmp_3_cfg_l (_ptw_io_requestor_5_pmp_3_cfg_l), .io_requestor_5_pmp_3_cfg_a (_ptw_io_requestor_5_pmp_3_cfg_a), .io_requestor_5_pmp_3_cfg_x (_ptw_io_requestor_5_pmp_3_cfg_x), .io_requestor_5_pmp_3_cfg_w (_ptw_io_requestor_5_pmp_3_cfg_w), .io_requestor_5_pmp_3_cfg_r (_ptw_io_requestor_5_pmp_3_cfg_r), .io_requestor_5_pmp_3_addr (_ptw_io_requestor_5_pmp_3_addr), .io_requestor_5_pmp_3_mask (_ptw_io_requestor_5_pmp_3_mask), .io_requestor_5_pmp_4_cfg_l (_ptw_io_requestor_5_pmp_4_cfg_l), .io_requestor_5_pmp_4_cfg_a (_ptw_io_requestor_5_pmp_4_cfg_a), .io_requestor_5_pmp_4_cfg_x (_ptw_io_requestor_5_pmp_4_cfg_x), .io_requestor_5_pmp_4_cfg_w (_ptw_io_requestor_5_pmp_4_cfg_w), .io_requestor_5_pmp_4_cfg_r (_ptw_io_requestor_5_pmp_4_cfg_r), .io_requestor_5_pmp_4_addr (_ptw_io_requestor_5_pmp_4_addr), .io_requestor_5_pmp_4_mask (_ptw_io_requestor_5_pmp_4_mask), .io_requestor_5_pmp_5_cfg_l (_ptw_io_requestor_5_pmp_5_cfg_l), .io_requestor_5_pmp_5_cfg_a (_ptw_io_requestor_5_pmp_5_cfg_a), .io_requestor_5_pmp_5_cfg_x (_ptw_io_requestor_5_pmp_5_cfg_x), .io_requestor_5_pmp_5_cfg_w (_ptw_io_requestor_5_pmp_5_cfg_w), .io_requestor_5_pmp_5_cfg_r (_ptw_io_requestor_5_pmp_5_cfg_r), .io_requestor_5_pmp_5_addr (_ptw_io_requestor_5_pmp_5_addr), .io_requestor_5_pmp_5_mask (_ptw_io_requestor_5_pmp_5_mask), .io_requestor_5_pmp_6_cfg_l (_ptw_io_requestor_5_pmp_6_cfg_l), .io_requestor_5_pmp_6_cfg_a (_ptw_io_requestor_5_pmp_6_cfg_a), .io_requestor_5_pmp_6_cfg_x (_ptw_io_requestor_5_pmp_6_cfg_x), .io_requestor_5_pmp_6_cfg_w (_ptw_io_requestor_5_pmp_6_cfg_w), .io_requestor_5_pmp_6_cfg_r (_ptw_io_requestor_5_pmp_6_cfg_r), .io_requestor_5_pmp_6_addr (_ptw_io_requestor_5_pmp_6_addr), .io_requestor_5_pmp_6_mask (_ptw_io_requestor_5_pmp_6_mask), .io_requestor_5_pmp_7_cfg_l (_ptw_io_requestor_5_pmp_7_cfg_l), .io_requestor_5_pmp_7_cfg_a (_ptw_io_requestor_5_pmp_7_cfg_a), .io_requestor_5_pmp_7_cfg_x (_ptw_io_requestor_5_pmp_7_cfg_x), .io_requestor_5_pmp_7_cfg_w (_ptw_io_requestor_5_pmp_7_cfg_w), .io_requestor_5_pmp_7_cfg_r (_ptw_io_requestor_5_pmp_7_cfg_r), .io_requestor_5_pmp_7_addr (_ptw_io_requestor_5_pmp_7_addr), .io_requestor_5_pmp_7_mask (_ptw_io_requestor_5_pmp_7_mask), .io_requestor_5_customCSRs_csrs_0_ren (_ptw_io_requestor_5_customCSRs_csrs_0_ren), .io_requestor_5_customCSRs_csrs_0_wen (_ptw_io_requestor_5_customCSRs_csrs_0_wen), .io_requestor_5_customCSRs_csrs_0_wdata (_ptw_io_requestor_5_customCSRs_csrs_0_wdata), .io_requestor_5_customCSRs_csrs_0_value (_ptw_io_requestor_5_customCSRs_csrs_0_value), .io_requestor_5_customCSRs_csrs_1_ren (_ptw_io_requestor_5_customCSRs_csrs_1_ren), .io_requestor_5_customCSRs_csrs_1_wen (_ptw_io_requestor_5_customCSRs_csrs_1_wen), .io_requestor_5_customCSRs_csrs_1_wdata (_ptw_io_requestor_5_customCSRs_csrs_1_wdata), .io_requestor_5_customCSRs_csrs_1_value (_ptw_io_requestor_5_customCSRs_csrs_1_value), .io_requestor_5_customCSRs_csrs_2_ren (_ptw_io_requestor_5_customCSRs_csrs_2_ren), .io_requestor_5_customCSRs_csrs_2_wen (_ptw_io_requestor_5_customCSRs_csrs_2_wen), .io_requestor_5_customCSRs_csrs_2_wdata (_ptw_io_requestor_5_customCSRs_csrs_2_wdata), .io_requestor_5_customCSRs_csrs_2_value (_ptw_io_requestor_5_customCSRs_csrs_2_value), .io_requestor_5_customCSRs_csrs_3_ren (_ptw_io_requestor_5_customCSRs_csrs_3_ren), .io_requestor_5_customCSRs_csrs_3_wen (_ptw_io_requestor_5_customCSRs_csrs_3_wen), .io_requestor_5_customCSRs_csrs_3_wdata (_ptw_io_requestor_5_customCSRs_csrs_3_wdata), .io_requestor_5_customCSRs_csrs_3_value (_ptw_io_requestor_5_customCSRs_csrs_3_value), .io_requestor_6_req_ready (_ptw_io_requestor_6_req_ready), .io_requestor_6_req_valid (_zstd_compressor_io_ptw_6_req_valid), // @[Configs.scala:62:39] .io_requestor_6_req_bits_bits_addr (_zstd_compressor_io_ptw_6_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_6_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_6_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_6_resp_valid (_ptw_io_requestor_6_resp_valid), .io_requestor_6_resp_bits_ae_ptw (_ptw_io_requestor_6_resp_bits_ae_ptw), .io_requestor_6_resp_bits_ae_final (_ptw_io_requestor_6_resp_bits_ae_final), .io_requestor_6_resp_bits_pf (_ptw_io_requestor_6_resp_bits_pf), .io_requestor_6_resp_bits_gf (_ptw_io_requestor_6_resp_bits_gf), .io_requestor_6_resp_bits_hr (_ptw_io_requestor_6_resp_bits_hr), .io_requestor_6_resp_bits_hw (_ptw_io_requestor_6_resp_bits_hw), .io_requestor_6_resp_bits_hx (_ptw_io_requestor_6_resp_bits_hx), .io_requestor_6_resp_bits_pte_reserved_for_future (_ptw_io_requestor_6_resp_bits_pte_reserved_for_future), .io_requestor_6_resp_bits_pte_ppn (_ptw_io_requestor_6_resp_bits_pte_ppn), .io_requestor_6_resp_bits_pte_reserved_for_software (_ptw_io_requestor_6_resp_bits_pte_reserved_for_software), .io_requestor_6_resp_bits_pte_d (_ptw_io_requestor_6_resp_bits_pte_d), .io_requestor_6_resp_bits_pte_a (_ptw_io_requestor_6_resp_bits_pte_a), .io_requestor_6_resp_bits_pte_g (_ptw_io_requestor_6_resp_bits_pte_g), .io_requestor_6_resp_bits_pte_u (_ptw_io_requestor_6_resp_bits_pte_u), .io_requestor_6_resp_bits_pte_x (_ptw_io_requestor_6_resp_bits_pte_x), .io_requestor_6_resp_bits_pte_w (_ptw_io_requestor_6_resp_bits_pte_w), .io_requestor_6_resp_bits_pte_r (_ptw_io_requestor_6_resp_bits_pte_r), .io_requestor_6_resp_bits_pte_v (_ptw_io_requestor_6_resp_bits_pte_v), .io_requestor_6_resp_bits_level (_ptw_io_requestor_6_resp_bits_level), .io_requestor_6_resp_bits_homogeneous (_ptw_io_requestor_6_resp_bits_homogeneous), .io_requestor_6_resp_bits_gpa_valid (_ptw_io_requestor_6_resp_bits_gpa_valid), .io_requestor_6_resp_bits_gpa_bits (_ptw_io_requestor_6_resp_bits_gpa_bits), .io_requestor_6_resp_bits_gpa_is_pte (_ptw_io_requestor_6_resp_bits_gpa_is_pte), .io_requestor_6_ptbr_mode (_ptw_io_requestor_6_ptbr_mode), .io_requestor_6_ptbr_ppn (_ptw_io_requestor_6_ptbr_ppn), .io_requestor_6_status_debug (_ptw_io_requestor_6_status_debug), .io_requestor_6_status_cease (_ptw_io_requestor_6_status_cease), .io_requestor_6_status_wfi (_ptw_io_requestor_6_status_wfi), .io_requestor_6_status_isa (_ptw_io_requestor_6_status_isa), .io_requestor_6_status_dprv (_ptw_io_requestor_6_status_dprv), .io_requestor_6_status_dv (_ptw_io_requestor_6_status_dv), .io_requestor_6_status_prv (_ptw_io_requestor_6_status_prv), .io_requestor_6_status_v (_ptw_io_requestor_6_status_v), .io_requestor_6_status_mpv (_ptw_io_requestor_6_status_mpv), .io_requestor_6_status_gva (_ptw_io_requestor_6_status_gva), .io_requestor_6_status_tsr (_ptw_io_requestor_6_status_tsr), .io_requestor_6_status_tw (_ptw_io_requestor_6_status_tw), .io_requestor_6_status_tvm (_ptw_io_requestor_6_status_tvm), .io_requestor_6_status_mxr (_ptw_io_requestor_6_status_mxr), .io_requestor_6_status_sum (_ptw_io_requestor_6_status_sum), .io_requestor_6_status_mprv (_ptw_io_requestor_6_status_mprv), .io_requestor_6_status_fs (_ptw_io_requestor_6_status_fs), .io_requestor_6_status_mpp (_ptw_io_requestor_6_status_mpp), .io_requestor_6_status_spp (_ptw_io_requestor_6_status_spp), .io_requestor_6_status_mpie (_ptw_io_requestor_6_status_mpie), .io_requestor_6_status_spie (_ptw_io_requestor_6_status_spie), .io_requestor_6_status_mie (_ptw_io_requestor_6_status_mie), .io_requestor_6_status_sie (_ptw_io_requestor_6_status_sie), .io_requestor_6_hstatus_spvp (_ptw_io_requestor_6_hstatus_spvp), .io_requestor_6_hstatus_spv (_ptw_io_requestor_6_hstatus_spv), .io_requestor_6_hstatus_gva (_ptw_io_requestor_6_hstatus_gva), .io_requestor_6_gstatus_debug (_ptw_io_requestor_6_gstatus_debug), .io_requestor_6_gstatus_cease (_ptw_io_requestor_6_gstatus_cease), .io_requestor_6_gstatus_wfi (_ptw_io_requestor_6_gstatus_wfi), .io_requestor_6_gstatus_isa (_ptw_io_requestor_6_gstatus_isa), .io_requestor_6_gstatus_dprv (_ptw_io_requestor_6_gstatus_dprv), .io_requestor_6_gstatus_dv (_ptw_io_requestor_6_gstatus_dv), .io_requestor_6_gstatus_prv (_ptw_io_requestor_6_gstatus_prv), .io_requestor_6_gstatus_v (_ptw_io_requestor_6_gstatus_v), .io_requestor_6_gstatus_zero2 (_ptw_io_requestor_6_gstatus_zero2), .io_requestor_6_gstatus_mpv (_ptw_io_requestor_6_gstatus_mpv), .io_requestor_6_gstatus_gva (_ptw_io_requestor_6_gstatus_gva), .io_requestor_6_gstatus_mbe (_ptw_io_requestor_6_gstatus_mbe), .io_requestor_6_gstatus_sbe (_ptw_io_requestor_6_gstatus_sbe), .io_requestor_6_gstatus_sxl (_ptw_io_requestor_6_gstatus_sxl), .io_requestor_6_gstatus_zero1 (_ptw_io_requestor_6_gstatus_zero1), .io_requestor_6_gstatus_tsr (_ptw_io_requestor_6_gstatus_tsr), .io_requestor_6_gstatus_tw (_ptw_io_requestor_6_gstatus_tw), .io_requestor_6_gstatus_tvm (_ptw_io_requestor_6_gstatus_tvm), .io_requestor_6_gstatus_mxr (_ptw_io_requestor_6_gstatus_mxr), .io_requestor_6_gstatus_sum (_ptw_io_requestor_6_gstatus_sum), .io_requestor_6_gstatus_mprv (_ptw_io_requestor_6_gstatus_mprv), .io_requestor_6_gstatus_fs (_ptw_io_requestor_6_gstatus_fs), .io_requestor_6_gstatus_mpp (_ptw_io_requestor_6_gstatus_mpp), .io_requestor_6_gstatus_vs (_ptw_io_requestor_6_gstatus_vs), .io_requestor_6_gstatus_spp (_ptw_io_requestor_6_gstatus_spp), .io_requestor_6_gstatus_mpie (_ptw_io_requestor_6_gstatus_mpie), .io_requestor_6_gstatus_ube (_ptw_io_requestor_6_gstatus_ube), .io_requestor_6_gstatus_spie (_ptw_io_requestor_6_gstatus_spie), .io_requestor_6_gstatus_upie (_ptw_io_requestor_6_gstatus_upie), .io_requestor_6_gstatus_mie (_ptw_io_requestor_6_gstatus_mie), .io_requestor_6_gstatus_hie (_ptw_io_requestor_6_gstatus_hie), .io_requestor_6_gstatus_sie (_ptw_io_requestor_6_gstatus_sie), .io_requestor_6_gstatus_uie (_ptw_io_requestor_6_gstatus_uie), .io_requestor_6_pmp_0_cfg_l (_ptw_io_requestor_6_pmp_0_cfg_l), .io_requestor_6_pmp_0_cfg_a (_ptw_io_requestor_6_pmp_0_cfg_a), .io_requestor_6_pmp_0_cfg_x (_ptw_io_requestor_6_pmp_0_cfg_x), .io_requestor_6_pmp_0_cfg_w (_ptw_io_requestor_6_pmp_0_cfg_w), .io_requestor_6_pmp_0_cfg_r (_ptw_io_requestor_6_pmp_0_cfg_r), .io_requestor_6_pmp_0_addr (_ptw_io_requestor_6_pmp_0_addr), .io_requestor_6_pmp_0_mask (_ptw_io_requestor_6_pmp_0_mask), .io_requestor_6_pmp_1_cfg_l (_ptw_io_requestor_6_pmp_1_cfg_l), .io_requestor_6_pmp_1_cfg_a (_ptw_io_requestor_6_pmp_1_cfg_a), .io_requestor_6_pmp_1_cfg_x (_ptw_io_requestor_6_pmp_1_cfg_x), .io_requestor_6_pmp_1_cfg_w (_ptw_io_requestor_6_pmp_1_cfg_w), .io_requestor_6_pmp_1_cfg_r (_ptw_io_requestor_6_pmp_1_cfg_r), .io_requestor_6_pmp_1_addr (_ptw_io_requestor_6_pmp_1_addr), .io_requestor_6_pmp_1_mask (_ptw_io_requestor_6_pmp_1_mask), .io_requestor_6_pmp_2_cfg_l (_ptw_io_requestor_6_pmp_2_cfg_l), .io_requestor_6_pmp_2_cfg_a (_ptw_io_requestor_6_pmp_2_cfg_a), .io_requestor_6_pmp_2_cfg_x (_ptw_io_requestor_6_pmp_2_cfg_x), .io_requestor_6_pmp_2_cfg_w (_ptw_io_requestor_6_pmp_2_cfg_w), .io_requestor_6_pmp_2_cfg_r (_ptw_io_requestor_6_pmp_2_cfg_r), .io_requestor_6_pmp_2_addr (_ptw_io_requestor_6_pmp_2_addr), .io_requestor_6_pmp_2_mask (_ptw_io_requestor_6_pmp_2_mask), .io_requestor_6_pmp_3_cfg_l (_ptw_io_requestor_6_pmp_3_cfg_l), .io_requestor_6_pmp_3_cfg_a (_ptw_io_requestor_6_pmp_3_cfg_a), .io_requestor_6_pmp_3_cfg_x (_ptw_io_requestor_6_pmp_3_cfg_x), .io_requestor_6_pmp_3_cfg_w (_ptw_io_requestor_6_pmp_3_cfg_w), .io_requestor_6_pmp_3_cfg_r (_ptw_io_requestor_6_pmp_3_cfg_r), .io_requestor_6_pmp_3_addr (_ptw_io_requestor_6_pmp_3_addr), .io_requestor_6_pmp_3_mask (_ptw_io_requestor_6_pmp_3_mask), .io_requestor_6_pmp_4_cfg_l (_ptw_io_requestor_6_pmp_4_cfg_l), .io_requestor_6_pmp_4_cfg_a (_ptw_io_requestor_6_pmp_4_cfg_a), .io_requestor_6_pmp_4_cfg_x (_ptw_io_requestor_6_pmp_4_cfg_x), .io_requestor_6_pmp_4_cfg_w (_ptw_io_requestor_6_pmp_4_cfg_w), .io_requestor_6_pmp_4_cfg_r (_ptw_io_requestor_6_pmp_4_cfg_r), .io_requestor_6_pmp_4_addr (_ptw_io_requestor_6_pmp_4_addr), .io_requestor_6_pmp_4_mask (_ptw_io_requestor_6_pmp_4_mask), .io_requestor_6_pmp_5_cfg_l (_ptw_io_requestor_6_pmp_5_cfg_l), .io_requestor_6_pmp_5_cfg_a (_ptw_io_requestor_6_pmp_5_cfg_a), .io_requestor_6_pmp_5_cfg_x (_ptw_io_requestor_6_pmp_5_cfg_x), .io_requestor_6_pmp_5_cfg_w (_ptw_io_requestor_6_pmp_5_cfg_w), .io_requestor_6_pmp_5_cfg_r (_ptw_io_requestor_6_pmp_5_cfg_r), .io_requestor_6_pmp_5_addr (_ptw_io_requestor_6_pmp_5_addr), .io_requestor_6_pmp_5_mask (_ptw_io_requestor_6_pmp_5_mask), .io_requestor_6_pmp_6_cfg_l (_ptw_io_requestor_6_pmp_6_cfg_l), .io_requestor_6_pmp_6_cfg_a (_ptw_io_requestor_6_pmp_6_cfg_a), .io_requestor_6_pmp_6_cfg_x (_ptw_io_requestor_6_pmp_6_cfg_x), .io_requestor_6_pmp_6_cfg_w (_ptw_io_requestor_6_pmp_6_cfg_w), .io_requestor_6_pmp_6_cfg_r (_ptw_io_requestor_6_pmp_6_cfg_r), .io_requestor_6_pmp_6_addr (_ptw_io_requestor_6_pmp_6_addr), .io_requestor_6_pmp_6_mask (_ptw_io_requestor_6_pmp_6_mask), .io_requestor_6_pmp_7_cfg_l (_ptw_io_requestor_6_pmp_7_cfg_l), .io_requestor_6_pmp_7_cfg_a (_ptw_io_requestor_6_pmp_7_cfg_a), .io_requestor_6_pmp_7_cfg_x (_ptw_io_requestor_6_pmp_7_cfg_x), .io_requestor_6_pmp_7_cfg_w (_ptw_io_requestor_6_pmp_7_cfg_w), .io_requestor_6_pmp_7_cfg_r (_ptw_io_requestor_6_pmp_7_cfg_r), .io_requestor_6_pmp_7_addr (_ptw_io_requestor_6_pmp_7_addr), .io_requestor_6_pmp_7_mask (_ptw_io_requestor_6_pmp_7_mask), .io_requestor_6_customCSRs_csrs_0_ren (_ptw_io_requestor_6_customCSRs_csrs_0_ren), .io_requestor_6_customCSRs_csrs_0_wen (_ptw_io_requestor_6_customCSRs_csrs_0_wen), .io_requestor_6_customCSRs_csrs_0_wdata (_ptw_io_requestor_6_customCSRs_csrs_0_wdata), .io_requestor_6_customCSRs_csrs_0_value (_ptw_io_requestor_6_customCSRs_csrs_0_value), .io_requestor_6_customCSRs_csrs_1_ren (_ptw_io_requestor_6_customCSRs_csrs_1_ren), .io_requestor_6_customCSRs_csrs_1_wen (_ptw_io_requestor_6_customCSRs_csrs_1_wen), .io_requestor_6_customCSRs_csrs_1_wdata (_ptw_io_requestor_6_customCSRs_csrs_1_wdata), .io_requestor_6_customCSRs_csrs_1_value (_ptw_io_requestor_6_customCSRs_csrs_1_value), .io_requestor_6_customCSRs_csrs_2_ren (_ptw_io_requestor_6_customCSRs_csrs_2_ren), .io_requestor_6_customCSRs_csrs_2_wen (_ptw_io_requestor_6_customCSRs_csrs_2_wen), .io_requestor_6_customCSRs_csrs_2_wdata (_ptw_io_requestor_6_customCSRs_csrs_2_wdata), .io_requestor_6_customCSRs_csrs_2_value (_ptw_io_requestor_6_customCSRs_csrs_2_value), .io_requestor_6_customCSRs_csrs_3_ren (_ptw_io_requestor_6_customCSRs_csrs_3_ren), .io_requestor_6_customCSRs_csrs_3_wen (_ptw_io_requestor_6_customCSRs_csrs_3_wen), .io_requestor_6_customCSRs_csrs_3_wdata (_ptw_io_requestor_6_customCSRs_csrs_3_wdata), .io_requestor_6_customCSRs_csrs_3_value (_ptw_io_requestor_6_customCSRs_csrs_3_value), .io_requestor_7_req_ready (_ptw_io_requestor_7_req_ready), .io_requestor_7_req_valid (_zstd_compressor_io_ptw_7_req_valid), // @[Configs.scala:62:39] .io_requestor_7_req_bits_bits_addr (_zstd_compressor_io_ptw_7_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_7_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_7_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_7_resp_valid (_ptw_io_requestor_7_resp_valid), .io_requestor_7_resp_bits_ae_ptw (_ptw_io_requestor_7_resp_bits_ae_ptw), .io_requestor_7_resp_bits_ae_final (_ptw_io_requestor_7_resp_bits_ae_final), .io_requestor_7_resp_bits_pf (_ptw_io_requestor_7_resp_bits_pf), .io_requestor_7_resp_bits_gf (_ptw_io_requestor_7_resp_bits_gf), .io_requestor_7_resp_bits_hr (_ptw_io_requestor_7_resp_bits_hr), .io_requestor_7_resp_bits_hw (_ptw_io_requestor_7_resp_bits_hw), .io_requestor_7_resp_bits_hx (_ptw_io_requestor_7_resp_bits_hx), .io_requestor_7_resp_bits_pte_reserved_for_future (_ptw_io_requestor_7_resp_bits_pte_reserved_for_future), .io_requestor_7_resp_bits_pte_ppn (_ptw_io_requestor_7_resp_bits_pte_ppn), .io_requestor_7_resp_bits_pte_reserved_for_software (_ptw_io_requestor_7_resp_bits_pte_reserved_for_software), .io_requestor_7_resp_bits_pte_d (_ptw_io_requestor_7_resp_bits_pte_d), .io_requestor_7_resp_bits_pte_a (_ptw_io_requestor_7_resp_bits_pte_a), .io_requestor_7_resp_bits_pte_g (_ptw_io_requestor_7_resp_bits_pte_g), .io_requestor_7_resp_bits_pte_u (_ptw_io_requestor_7_resp_bits_pte_u), .io_requestor_7_resp_bits_pte_x (_ptw_io_requestor_7_resp_bits_pte_x), .io_requestor_7_resp_bits_pte_w (_ptw_io_requestor_7_resp_bits_pte_w), .io_requestor_7_resp_bits_pte_r (_ptw_io_requestor_7_resp_bits_pte_r), .io_requestor_7_resp_bits_pte_v (_ptw_io_requestor_7_resp_bits_pte_v), .io_requestor_7_resp_bits_level (_ptw_io_requestor_7_resp_bits_level), .io_requestor_7_resp_bits_homogeneous (_ptw_io_requestor_7_resp_bits_homogeneous), .io_requestor_7_resp_bits_gpa_valid (_ptw_io_requestor_7_resp_bits_gpa_valid), .io_requestor_7_resp_bits_gpa_bits (_ptw_io_requestor_7_resp_bits_gpa_bits), .io_requestor_7_resp_bits_gpa_is_pte (_ptw_io_requestor_7_resp_bits_gpa_is_pte), .io_requestor_7_ptbr_mode (_ptw_io_requestor_7_ptbr_mode), .io_requestor_7_ptbr_ppn (_ptw_io_requestor_7_ptbr_ppn), .io_requestor_7_status_debug (_ptw_io_requestor_7_status_debug), .io_requestor_7_status_cease (_ptw_io_requestor_7_status_cease), .io_requestor_7_status_wfi (_ptw_io_requestor_7_status_wfi), .io_requestor_7_status_isa (_ptw_io_requestor_7_status_isa), .io_requestor_7_status_dprv (_ptw_io_requestor_7_status_dprv), .io_requestor_7_status_dv (_ptw_io_requestor_7_status_dv), .io_requestor_7_status_prv (_ptw_io_requestor_7_status_prv), .io_requestor_7_status_v (_ptw_io_requestor_7_status_v), .io_requestor_7_status_mpv (_ptw_io_requestor_7_status_mpv), .io_requestor_7_status_gva (_ptw_io_requestor_7_status_gva), .io_requestor_7_status_tsr (_ptw_io_requestor_7_status_tsr), .io_requestor_7_status_tw (_ptw_io_requestor_7_status_tw), .io_requestor_7_status_tvm (_ptw_io_requestor_7_status_tvm), .io_requestor_7_status_mxr (_ptw_io_requestor_7_status_mxr), .io_requestor_7_status_sum (_ptw_io_requestor_7_status_sum), .io_requestor_7_status_mprv (_ptw_io_requestor_7_status_mprv), .io_requestor_7_status_fs (_ptw_io_requestor_7_status_fs), .io_requestor_7_status_mpp (_ptw_io_requestor_7_status_mpp), .io_requestor_7_status_spp (_ptw_io_requestor_7_status_spp), .io_requestor_7_status_mpie (_ptw_io_requestor_7_status_mpie), .io_requestor_7_status_spie (_ptw_io_requestor_7_status_spie), .io_requestor_7_status_mie (_ptw_io_requestor_7_status_mie), .io_requestor_7_status_sie (_ptw_io_requestor_7_status_sie), .io_requestor_7_hstatus_spvp (_ptw_io_requestor_7_hstatus_spvp), .io_requestor_7_hstatus_spv (_ptw_io_requestor_7_hstatus_spv), .io_requestor_7_hstatus_gva (_ptw_io_requestor_7_hstatus_gva), .io_requestor_7_gstatus_debug (_ptw_io_requestor_7_gstatus_debug), .io_requestor_7_gstatus_cease (_ptw_io_requestor_7_gstatus_cease), .io_requestor_7_gstatus_wfi (_ptw_io_requestor_7_gstatus_wfi), .io_requestor_7_gstatus_isa (_ptw_io_requestor_7_gstatus_isa), .io_requestor_7_gstatus_dprv (_ptw_io_requestor_7_gstatus_dprv), .io_requestor_7_gstatus_dv (_ptw_io_requestor_7_gstatus_dv), .io_requestor_7_gstatus_prv (_ptw_io_requestor_7_gstatus_prv), .io_requestor_7_gstatus_v (_ptw_io_requestor_7_gstatus_v), .io_requestor_7_gstatus_zero2 (_ptw_io_requestor_7_gstatus_zero2), .io_requestor_7_gstatus_mpv (_ptw_io_requestor_7_gstatus_mpv), .io_requestor_7_gstatus_gva (_ptw_io_requestor_7_gstatus_gva), .io_requestor_7_gstatus_mbe (_ptw_io_requestor_7_gstatus_mbe), .io_requestor_7_gstatus_sbe (_ptw_io_requestor_7_gstatus_sbe), .io_requestor_7_gstatus_sxl (_ptw_io_requestor_7_gstatus_sxl), .io_requestor_7_gstatus_zero1 (_ptw_io_requestor_7_gstatus_zero1), .io_requestor_7_gstatus_tsr (_ptw_io_requestor_7_gstatus_tsr), .io_requestor_7_gstatus_tw (_ptw_io_requestor_7_gstatus_tw), .io_requestor_7_gstatus_tvm (_ptw_io_requestor_7_gstatus_tvm), .io_requestor_7_gstatus_mxr (_ptw_io_requestor_7_gstatus_mxr), .io_requestor_7_gstatus_sum (_ptw_io_requestor_7_gstatus_sum), .io_requestor_7_gstatus_mprv (_ptw_io_requestor_7_gstatus_mprv), .io_requestor_7_gstatus_fs (_ptw_io_requestor_7_gstatus_fs), .io_requestor_7_gstatus_mpp (_ptw_io_requestor_7_gstatus_mpp), .io_requestor_7_gstatus_vs (_ptw_io_requestor_7_gstatus_vs), .io_requestor_7_gstatus_spp (_ptw_io_requestor_7_gstatus_spp), .io_requestor_7_gstatus_mpie (_ptw_io_requestor_7_gstatus_mpie), .io_requestor_7_gstatus_ube (_ptw_io_requestor_7_gstatus_ube), .io_requestor_7_gstatus_spie (_ptw_io_requestor_7_gstatus_spie), .io_requestor_7_gstatus_upie (_ptw_io_requestor_7_gstatus_upie), .io_requestor_7_gstatus_mie (_ptw_io_requestor_7_gstatus_mie), .io_requestor_7_gstatus_hie (_ptw_io_requestor_7_gstatus_hie), .io_requestor_7_gstatus_sie (_ptw_io_requestor_7_gstatus_sie), .io_requestor_7_gstatus_uie (_ptw_io_requestor_7_gstatus_uie), .io_requestor_7_pmp_0_cfg_l (_ptw_io_requestor_7_pmp_0_cfg_l), .io_requestor_7_pmp_0_cfg_a (_ptw_io_requestor_7_pmp_0_cfg_a), .io_requestor_7_pmp_0_cfg_x (_ptw_io_requestor_7_pmp_0_cfg_x), .io_requestor_7_pmp_0_cfg_w (_ptw_io_requestor_7_pmp_0_cfg_w), .io_requestor_7_pmp_0_cfg_r (_ptw_io_requestor_7_pmp_0_cfg_r), .io_requestor_7_pmp_0_addr (_ptw_io_requestor_7_pmp_0_addr), .io_requestor_7_pmp_0_mask (_ptw_io_requestor_7_pmp_0_mask), .io_requestor_7_pmp_1_cfg_l (_ptw_io_requestor_7_pmp_1_cfg_l), .io_requestor_7_pmp_1_cfg_a (_ptw_io_requestor_7_pmp_1_cfg_a), .io_requestor_7_pmp_1_cfg_x (_ptw_io_requestor_7_pmp_1_cfg_x), .io_requestor_7_pmp_1_cfg_w (_ptw_io_requestor_7_pmp_1_cfg_w), .io_requestor_7_pmp_1_cfg_r (_ptw_io_requestor_7_pmp_1_cfg_r), .io_requestor_7_pmp_1_addr (_ptw_io_requestor_7_pmp_1_addr), .io_requestor_7_pmp_1_mask (_ptw_io_requestor_7_pmp_1_mask), .io_requestor_7_pmp_2_cfg_l (_ptw_io_requestor_7_pmp_2_cfg_l), .io_requestor_7_pmp_2_cfg_a (_ptw_io_requestor_7_pmp_2_cfg_a), .io_requestor_7_pmp_2_cfg_x (_ptw_io_requestor_7_pmp_2_cfg_x), .io_requestor_7_pmp_2_cfg_w (_ptw_io_requestor_7_pmp_2_cfg_w), .io_requestor_7_pmp_2_cfg_r (_ptw_io_requestor_7_pmp_2_cfg_r), .io_requestor_7_pmp_2_addr (_ptw_io_requestor_7_pmp_2_addr), .io_requestor_7_pmp_2_mask (_ptw_io_requestor_7_pmp_2_mask), .io_requestor_7_pmp_3_cfg_l (_ptw_io_requestor_7_pmp_3_cfg_l), .io_requestor_7_pmp_3_cfg_a (_ptw_io_requestor_7_pmp_3_cfg_a), .io_requestor_7_pmp_3_cfg_x (_ptw_io_requestor_7_pmp_3_cfg_x), .io_requestor_7_pmp_3_cfg_w (_ptw_io_requestor_7_pmp_3_cfg_w), .io_requestor_7_pmp_3_cfg_r (_ptw_io_requestor_7_pmp_3_cfg_r), .io_requestor_7_pmp_3_addr (_ptw_io_requestor_7_pmp_3_addr), .io_requestor_7_pmp_3_mask (_ptw_io_requestor_7_pmp_3_mask), .io_requestor_7_pmp_4_cfg_l (_ptw_io_requestor_7_pmp_4_cfg_l), .io_requestor_7_pmp_4_cfg_a (_ptw_io_requestor_7_pmp_4_cfg_a), .io_requestor_7_pmp_4_cfg_x (_ptw_io_requestor_7_pmp_4_cfg_x), .io_requestor_7_pmp_4_cfg_w (_ptw_io_requestor_7_pmp_4_cfg_w), .io_requestor_7_pmp_4_cfg_r (_ptw_io_requestor_7_pmp_4_cfg_r), .io_requestor_7_pmp_4_addr (_ptw_io_requestor_7_pmp_4_addr), .io_requestor_7_pmp_4_mask (_ptw_io_requestor_7_pmp_4_mask), .io_requestor_7_pmp_5_cfg_l (_ptw_io_requestor_7_pmp_5_cfg_l), .io_requestor_7_pmp_5_cfg_a (_ptw_io_requestor_7_pmp_5_cfg_a), .io_requestor_7_pmp_5_cfg_x (_ptw_io_requestor_7_pmp_5_cfg_x), .io_requestor_7_pmp_5_cfg_w (_ptw_io_requestor_7_pmp_5_cfg_w), .io_requestor_7_pmp_5_cfg_r (_ptw_io_requestor_7_pmp_5_cfg_r), .io_requestor_7_pmp_5_addr (_ptw_io_requestor_7_pmp_5_addr), .io_requestor_7_pmp_5_mask (_ptw_io_requestor_7_pmp_5_mask), .io_requestor_7_pmp_6_cfg_l (_ptw_io_requestor_7_pmp_6_cfg_l), .io_requestor_7_pmp_6_cfg_a (_ptw_io_requestor_7_pmp_6_cfg_a), .io_requestor_7_pmp_6_cfg_x (_ptw_io_requestor_7_pmp_6_cfg_x), .io_requestor_7_pmp_6_cfg_w (_ptw_io_requestor_7_pmp_6_cfg_w), .io_requestor_7_pmp_6_cfg_r (_ptw_io_requestor_7_pmp_6_cfg_r), .io_requestor_7_pmp_6_addr (_ptw_io_requestor_7_pmp_6_addr), .io_requestor_7_pmp_6_mask (_ptw_io_requestor_7_pmp_6_mask), .io_requestor_7_pmp_7_cfg_l (_ptw_io_requestor_7_pmp_7_cfg_l), .io_requestor_7_pmp_7_cfg_a (_ptw_io_requestor_7_pmp_7_cfg_a), .io_requestor_7_pmp_7_cfg_x (_ptw_io_requestor_7_pmp_7_cfg_x), .io_requestor_7_pmp_7_cfg_w (_ptw_io_requestor_7_pmp_7_cfg_w), .io_requestor_7_pmp_7_cfg_r (_ptw_io_requestor_7_pmp_7_cfg_r), .io_requestor_7_pmp_7_addr (_ptw_io_requestor_7_pmp_7_addr), .io_requestor_7_pmp_7_mask (_ptw_io_requestor_7_pmp_7_mask), .io_requestor_7_customCSRs_csrs_0_ren (_ptw_io_requestor_7_customCSRs_csrs_0_ren), .io_requestor_7_customCSRs_csrs_0_wen (_ptw_io_requestor_7_customCSRs_csrs_0_wen), .io_requestor_7_customCSRs_csrs_0_wdata (_ptw_io_requestor_7_customCSRs_csrs_0_wdata), .io_requestor_7_customCSRs_csrs_0_value (_ptw_io_requestor_7_customCSRs_csrs_0_value), .io_requestor_7_customCSRs_csrs_1_ren (_ptw_io_requestor_7_customCSRs_csrs_1_ren), .io_requestor_7_customCSRs_csrs_1_wen (_ptw_io_requestor_7_customCSRs_csrs_1_wen), .io_requestor_7_customCSRs_csrs_1_wdata (_ptw_io_requestor_7_customCSRs_csrs_1_wdata), .io_requestor_7_customCSRs_csrs_1_value (_ptw_io_requestor_7_customCSRs_csrs_1_value), .io_requestor_7_customCSRs_csrs_2_ren (_ptw_io_requestor_7_customCSRs_csrs_2_ren), .io_requestor_7_customCSRs_csrs_2_wen (_ptw_io_requestor_7_customCSRs_csrs_2_wen), .io_requestor_7_customCSRs_csrs_2_wdata (_ptw_io_requestor_7_customCSRs_csrs_2_wdata), .io_requestor_7_customCSRs_csrs_2_value (_ptw_io_requestor_7_customCSRs_csrs_2_value), .io_requestor_7_customCSRs_csrs_3_ren (_ptw_io_requestor_7_customCSRs_csrs_3_ren), .io_requestor_7_customCSRs_csrs_3_wen (_ptw_io_requestor_7_customCSRs_csrs_3_wen), .io_requestor_7_customCSRs_csrs_3_wdata (_ptw_io_requestor_7_customCSRs_csrs_3_wdata), .io_requestor_7_customCSRs_csrs_3_value (_ptw_io_requestor_7_customCSRs_csrs_3_value), .io_requestor_8_req_ready (_ptw_io_requestor_8_req_ready), .io_requestor_8_req_valid (_zstd_compressor_io_ptw_8_req_valid), // @[Configs.scala:62:39] .io_requestor_8_req_bits_bits_addr (_zstd_compressor_io_ptw_8_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_8_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_8_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_8_resp_valid (_ptw_io_requestor_8_resp_valid), .io_requestor_8_resp_bits_ae_ptw (_ptw_io_requestor_8_resp_bits_ae_ptw), .io_requestor_8_resp_bits_ae_final (_ptw_io_requestor_8_resp_bits_ae_final), .io_requestor_8_resp_bits_pf (_ptw_io_requestor_8_resp_bits_pf), .io_requestor_8_resp_bits_gf (_ptw_io_requestor_8_resp_bits_gf), .io_requestor_8_resp_bits_hr (_ptw_io_requestor_8_resp_bits_hr), .io_requestor_8_resp_bits_hw (_ptw_io_requestor_8_resp_bits_hw), .io_requestor_8_resp_bits_hx (_ptw_io_requestor_8_resp_bits_hx), .io_requestor_8_resp_bits_pte_reserved_for_future (_ptw_io_requestor_8_resp_bits_pte_reserved_for_future), .io_requestor_8_resp_bits_pte_ppn (_ptw_io_requestor_8_resp_bits_pte_ppn), .io_requestor_8_resp_bits_pte_reserved_for_software (_ptw_io_requestor_8_resp_bits_pte_reserved_for_software), .io_requestor_8_resp_bits_pte_d (_ptw_io_requestor_8_resp_bits_pte_d), .io_requestor_8_resp_bits_pte_a (_ptw_io_requestor_8_resp_bits_pte_a), .io_requestor_8_resp_bits_pte_g (_ptw_io_requestor_8_resp_bits_pte_g), .io_requestor_8_resp_bits_pte_u (_ptw_io_requestor_8_resp_bits_pte_u), .io_requestor_8_resp_bits_pte_x (_ptw_io_requestor_8_resp_bits_pte_x), .io_requestor_8_resp_bits_pte_w (_ptw_io_requestor_8_resp_bits_pte_w), .io_requestor_8_resp_bits_pte_r (_ptw_io_requestor_8_resp_bits_pte_r), .io_requestor_8_resp_bits_pte_v (_ptw_io_requestor_8_resp_bits_pte_v), .io_requestor_8_resp_bits_level (_ptw_io_requestor_8_resp_bits_level), .io_requestor_8_resp_bits_homogeneous (_ptw_io_requestor_8_resp_bits_homogeneous), .io_requestor_8_resp_bits_gpa_valid (_ptw_io_requestor_8_resp_bits_gpa_valid), .io_requestor_8_resp_bits_gpa_bits (_ptw_io_requestor_8_resp_bits_gpa_bits), .io_requestor_8_resp_bits_gpa_is_pte (_ptw_io_requestor_8_resp_bits_gpa_is_pte), .io_requestor_8_ptbr_mode (_ptw_io_requestor_8_ptbr_mode), .io_requestor_8_ptbr_ppn (_ptw_io_requestor_8_ptbr_ppn), .io_requestor_8_status_debug (_ptw_io_requestor_8_status_debug), .io_requestor_8_status_cease (_ptw_io_requestor_8_status_cease), .io_requestor_8_status_wfi (_ptw_io_requestor_8_status_wfi), .io_requestor_8_status_isa (_ptw_io_requestor_8_status_isa), .io_requestor_8_status_dprv (_ptw_io_requestor_8_status_dprv), .io_requestor_8_status_dv (_ptw_io_requestor_8_status_dv), .io_requestor_8_status_prv (_ptw_io_requestor_8_status_prv), .io_requestor_8_status_v (_ptw_io_requestor_8_status_v), .io_requestor_8_status_mpv (_ptw_io_requestor_8_status_mpv), .io_requestor_8_status_gva (_ptw_io_requestor_8_status_gva), .io_requestor_8_status_tsr (_ptw_io_requestor_8_status_tsr), .io_requestor_8_status_tw (_ptw_io_requestor_8_status_tw), .io_requestor_8_status_tvm (_ptw_io_requestor_8_status_tvm), .io_requestor_8_status_mxr (_ptw_io_requestor_8_status_mxr), .io_requestor_8_status_sum (_ptw_io_requestor_8_status_sum), .io_requestor_8_status_mprv (_ptw_io_requestor_8_status_mprv), .io_requestor_8_status_fs (_ptw_io_requestor_8_status_fs), .io_requestor_8_status_mpp (_ptw_io_requestor_8_status_mpp), .io_requestor_8_status_spp (_ptw_io_requestor_8_status_spp), .io_requestor_8_status_mpie (_ptw_io_requestor_8_status_mpie), .io_requestor_8_status_spie (_ptw_io_requestor_8_status_spie), .io_requestor_8_status_mie (_ptw_io_requestor_8_status_mie), .io_requestor_8_status_sie (_ptw_io_requestor_8_status_sie), .io_requestor_8_hstatus_spvp (_ptw_io_requestor_8_hstatus_spvp), .io_requestor_8_hstatus_spv (_ptw_io_requestor_8_hstatus_spv), .io_requestor_8_hstatus_gva (_ptw_io_requestor_8_hstatus_gva), .io_requestor_8_gstatus_debug (_ptw_io_requestor_8_gstatus_debug), .io_requestor_8_gstatus_cease (_ptw_io_requestor_8_gstatus_cease), .io_requestor_8_gstatus_wfi (_ptw_io_requestor_8_gstatus_wfi), .io_requestor_8_gstatus_isa (_ptw_io_requestor_8_gstatus_isa), .io_requestor_8_gstatus_dprv (_ptw_io_requestor_8_gstatus_dprv), .io_requestor_8_gstatus_dv (_ptw_io_requestor_8_gstatus_dv), .io_requestor_8_gstatus_prv (_ptw_io_requestor_8_gstatus_prv), .io_requestor_8_gstatus_v (_ptw_io_requestor_8_gstatus_v), .io_requestor_8_gstatus_zero2 (_ptw_io_requestor_8_gstatus_zero2), .io_requestor_8_gstatus_mpv (_ptw_io_requestor_8_gstatus_mpv), .io_requestor_8_gstatus_gva (_ptw_io_requestor_8_gstatus_gva), .io_requestor_8_gstatus_mbe (_ptw_io_requestor_8_gstatus_mbe), .io_requestor_8_gstatus_sbe (_ptw_io_requestor_8_gstatus_sbe), .io_requestor_8_gstatus_sxl (_ptw_io_requestor_8_gstatus_sxl), .io_requestor_8_gstatus_zero1 (_ptw_io_requestor_8_gstatus_zero1), .io_requestor_8_gstatus_tsr (_ptw_io_requestor_8_gstatus_tsr), .io_requestor_8_gstatus_tw (_ptw_io_requestor_8_gstatus_tw), .io_requestor_8_gstatus_tvm (_ptw_io_requestor_8_gstatus_tvm), .io_requestor_8_gstatus_mxr (_ptw_io_requestor_8_gstatus_mxr), .io_requestor_8_gstatus_sum (_ptw_io_requestor_8_gstatus_sum), .io_requestor_8_gstatus_mprv (_ptw_io_requestor_8_gstatus_mprv), .io_requestor_8_gstatus_fs (_ptw_io_requestor_8_gstatus_fs), .io_requestor_8_gstatus_mpp (_ptw_io_requestor_8_gstatus_mpp), .io_requestor_8_gstatus_vs (_ptw_io_requestor_8_gstatus_vs), .io_requestor_8_gstatus_spp (_ptw_io_requestor_8_gstatus_spp), .io_requestor_8_gstatus_mpie (_ptw_io_requestor_8_gstatus_mpie), .io_requestor_8_gstatus_ube (_ptw_io_requestor_8_gstatus_ube), .io_requestor_8_gstatus_spie (_ptw_io_requestor_8_gstatus_spie), .io_requestor_8_gstatus_upie (_ptw_io_requestor_8_gstatus_upie), .io_requestor_8_gstatus_mie (_ptw_io_requestor_8_gstatus_mie), .io_requestor_8_gstatus_hie (_ptw_io_requestor_8_gstatus_hie), .io_requestor_8_gstatus_sie (_ptw_io_requestor_8_gstatus_sie), .io_requestor_8_gstatus_uie (_ptw_io_requestor_8_gstatus_uie), .io_requestor_8_pmp_0_cfg_l (_ptw_io_requestor_8_pmp_0_cfg_l), .io_requestor_8_pmp_0_cfg_a (_ptw_io_requestor_8_pmp_0_cfg_a), .io_requestor_8_pmp_0_cfg_x (_ptw_io_requestor_8_pmp_0_cfg_x), .io_requestor_8_pmp_0_cfg_w (_ptw_io_requestor_8_pmp_0_cfg_w), .io_requestor_8_pmp_0_cfg_r (_ptw_io_requestor_8_pmp_0_cfg_r), .io_requestor_8_pmp_0_addr (_ptw_io_requestor_8_pmp_0_addr), .io_requestor_8_pmp_0_mask (_ptw_io_requestor_8_pmp_0_mask), .io_requestor_8_pmp_1_cfg_l (_ptw_io_requestor_8_pmp_1_cfg_l), .io_requestor_8_pmp_1_cfg_a (_ptw_io_requestor_8_pmp_1_cfg_a), .io_requestor_8_pmp_1_cfg_x (_ptw_io_requestor_8_pmp_1_cfg_x), .io_requestor_8_pmp_1_cfg_w (_ptw_io_requestor_8_pmp_1_cfg_w), .io_requestor_8_pmp_1_cfg_r (_ptw_io_requestor_8_pmp_1_cfg_r), .io_requestor_8_pmp_1_addr (_ptw_io_requestor_8_pmp_1_addr), .io_requestor_8_pmp_1_mask (_ptw_io_requestor_8_pmp_1_mask), .io_requestor_8_pmp_2_cfg_l (_ptw_io_requestor_8_pmp_2_cfg_l), .io_requestor_8_pmp_2_cfg_a (_ptw_io_requestor_8_pmp_2_cfg_a), .io_requestor_8_pmp_2_cfg_x (_ptw_io_requestor_8_pmp_2_cfg_x), .io_requestor_8_pmp_2_cfg_w (_ptw_io_requestor_8_pmp_2_cfg_w), .io_requestor_8_pmp_2_cfg_r (_ptw_io_requestor_8_pmp_2_cfg_r), .io_requestor_8_pmp_2_addr (_ptw_io_requestor_8_pmp_2_addr), .io_requestor_8_pmp_2_mask (_ptw_io_requestor_8_pmp_2_mask), .io_requestor_8_pmp_3_cfg_l (_ptw_io_requestor_8_pmp_3_cfg_l), .io_requestor_8_pmp_3_cfg_a (_ptw_io_requestor_8_pmp_3_cfg_a), .io_requestor_8_pmp_3_cfg_x (_ptw_io_requestor_8_pmp_3_cfg_x), .io_requestor_8_pmp_3_cfg_w (_ptw_io_requestor_8_pmp_3_cfg_w), .io_requestor_8_pmp_3_cfg_r (_ptw_io_requestor_8_pmp_3_cfg_r), .io_requestor_8_pmp_3_addr (_ptw_io_requestor_8_pmp_3_addr), .io_requestor_8_pmp_3_mask (_ptw_io_requestor_8_pmp_3_mask), .io_requestor_8_pmp_4_cfg_l (_ptw_io_requestor_8_pmp_4_cfg_l), .io_requestor_8_pmp_4_cfg_a (_ptw_io_requestor_8_pmp_4_cfg_a), .io_requestor_8_pmp_4_cfg_x (_ptw_io_requestor_8_pmp_4_cfg_x), .io_requestor_8_pmp_4_cfg_w (_ptw_io_requestor_8_pmp_4_cfg_w), .io_requestor_8_pmp_4_cfg_r (_ptw_io_requestor_8_pmp_4_cfg_r), .io_requestor_8_pmp_4_addr (_ptw_io_requestor_8_pmp_4_addr), .io_requestor_8_pmp_4_mask (_ptw_io_requestor_8_pmp_4_mask), .io_requestor_8_pmp_5_cfg_l (_ptw_io_requestor_8_pmp_5_cfg_l), .io_requestor_8_pmp_5_cfg_a (_ptw_io_requestor_8_pmp_5_cfg_a), .io_requestor_8_pmp_5_cfg_x (_ptw_io_requestor_8_pmp_5_cfg_x), .io_requestor_8_pmp_5_cfg_w (_ptw_io_requestor_8_pmp_5_cfg_w), .io_requestor_8_pmp_5_cfg_r (_ptw_io_requestor_8_pmp_5_cfg_r), .io_requestor_8_pmp_5_addr (_ptw_io_requestor_8_pmp_5_addr), .io_requestor_8_pmp_5_mask (_ptw_io_requestor_8_pmp_5_mask), .io_requestor_8_pmp_6_cfg_l (_ptw_io_requestor_8_pmp_6_cfg_l), .io_requestor_8_pmp_6_cfg_a (_ptw_io_requestor_8_pmp_6_cfg_a), .io_requestor_8_pmp_6_cfg_x (_ptw_io_requestor_8_pmp_6_cfg_x), .io_requestor_8_pmp_6_cfg_w (_ptw_io_requestor_8_pmp_6_cfg_w), .io_requestor_8_pmp_6_cfg_r (_ptw_io_requestor_8_pmp_6_cfg_r), .io_requestor_8_pmp_6_addr (_ptw_io_requestor_8_pmp_6_addr), .io_requestor_8_pmp_6_mask (_ptw_io_requestor_8_pmp_6_mask), .io_requestor_8_pmp_7_cfg_l (_ptw_io_requestor_8_pmp_7_cfg_l), .io_requestor_8_pmp_7_cfg_a (_ptw_io_requestor_8_pmp_7_cfg_a), .io_requestor_8_pmp_7_cfg_x (_ptw_io_requestor_8_pmp_7_cfg_x), .io_requestor_8_pmp_7_cfg_w (_ptw_io_requestor_8_pmp_7_cfg_w), .io_requestor_8_pmp_7_cfg_r (_ptw_io_requestor_8_pmp_7_cfg_r), .io_requestor_8_pmp_7_addr (_ptw_io_requestor_8_pmp_7_addr), .io_requestor_8_pmp_7_mask (_ptw_io_requestor_8_pmp_7_mask), .io_requestor_8_customCSRs_csrs_0_ren (_ptw_io_requestor_8_customCSRs_csrs_0_ren), .io_requestor_8_customCSRs_csrs_0_wen (_ptw_io_requestor_8_customCSRs_csrs_0_wen), .io_requestor_8_customCSRs_csrs_0_wdata (_ptw_io_requestor_8_customCSRs_csrs_0_wdata), .io_requestor_8_customCSRs_csrs_0_value (_ptw_io_requestor_8_customCSRs_csrs_0_value), .io_requestor_8_customCSRs_csrs_1_ren (_ptw_io_requestor_8_customCSRs_csrs_1_ren), .io_requestor_8_customCSRs_csrs_1_wen (_ptw_io_requestor_8_customCSRs_csrs_1_wen), .io_requestor_8_customCSRs_csrs_1_wdata (_ptw_io_requestor_8_customCSRs_csrs_1_wdata), .io_requestor_8_customCSRs_csrs_1_value (_ptw_io_requestor_8_customCSRs_csrs_1_value), .io_requestor_8_customCSRs_csrs_2_ren (_ptw_io_requestor_8_customCSRs_csrs_2_ren), .io_requestor_8_customCSRs_csrs_2_wen (_ptw_io_requestor_8_customCSRs_csrs_2_wen), .io_requestor_8_customCSRs_csrs_2_wdata (_ptw_io_requestor_8_customCSRs_csrs_2_wdata), .io_requestor_8_customCSRs_csrs_2_value (_ptw_io_requestor_8_customCSRs_csrs_2_value), .io_requestor_8_customCSRs_csrs_3_ren (_ptw_io_requestor_8_customCSRs_csrs_3_ren), .io_requestor_8_customCSRs_csrs_3_wen (_ptw_io_requestor_8_customCSRs_csrs_3_wen), .io_requestor_8_customCSRs_csrs_3_wdata (_ptw_io_requestor_8_customCSRs_csrs_3_wdata), .io_requestor_8_customCSRs_csrs_3_value (_ptw_io_requestor_8_customCSRs_csrs_3_value), .io_requestor_9_req_ready (_ptw_io_requestor_9_req_ready), .io_requestor_9_req_valid (_zstd_compressor_io_ptw_9_req_valid), // @[Configs.scala:62:39] .io_requestor_9_req_bits_bits_addr (_zstd_compressor_io_ptw_9_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_9_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_9_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_9_resp_valid (_ptw_io_requestor_9_resp_valid), .io_requestor_9_resp_bits_ae_ptw (_ptw_io_requestor_9_resp_bits_ae_ptw), .io_requestor_9_resp_bits_ae_final (_ptw_io_requestor_9_resp_bits_ae_final), .io_requestor_9_resp_bits_pf (_ptw_io_requestor_9_resp_bits_pf), .io_requestor_9_resp_bits_gf (_ptw_io_requestor_9_resp_bits_gf), .io_requestor_9_resp_bits_hr (_ptw_io_requestor_9_resp_bits_hr), .io_requestor_9_resp_bits_hw (_ptw_io_requestor_9_resp_bits_hw), .io_requestor_9_resp_bits_hx (_ptw_io_requestor_9_resp_bits_hx), .io_requestor_9_resp_bits_pte_reserved_for_future (_ptw_io_requestor_9_resp_bits_pte_reserved_for_future), .io_requestor_9_resp_bits_pte_ppn (_ptw_io_requestor_9_resp_bits_pte_ppn), .io_requestor_9_resp_bits_pte_reserved_for_software (_ptw_io_requestor_9_resp_bits_pte_reserved_for_software), .io_requestor_9_resp_bits_pte_d (_ptw_io_requestor_9_resp_bits_pte_d), .io_requestor_9_resp_bits_pte_a (_ptw_io_requestor_9_resp_bits_pte_a), .io_requestor_9_resp_bits_pte_g (_ptw_io_requestor_9_resp_bits_pte_g), .io_requestor_9_resp_bits_pte_u (_ptw_io_requestor_9_resp_bits_pte_u), .io_requestor_9_resp_bits_pte_x (_ptw_io_requestor_9_resp_bits_pte_x), .io_requestor_9_resp_bits_pte_w (_ptw_io_requestor_9_resp_bits_pte_w), .io_requestor_9_resp_bits_pte_r (_ptw_io_requestor_9_resp_bits_pte_r), .io_requestor_9_resp_bits_pte_v (_ptw_io_requestor_9_resp_bits_pte_v), .io_requestor_9_resp_bits_level (_ptw_io_requestor_9_resp_bits_level), .io_requestor_9_resp_bits_homogeneous (_ptw_io_requestor_9_resp_bits_homogeneous), .io_requestor_9_resp_bits_gpa_valid (_ptw_io_requestor_9_resp_bits_gpa_valid), .io_requestor_9_resp_bits_gpa_bits (_ptw_io_requestor_9_resp_bits_gpa_bits), .io_requestor_9_resp_bits_gpa_is_pte (_ptw_io_requestor_9_resp_bits_gpa_is_pte), .io_requestor_9_ptbr_mode (_ptw_io_requestor_9_ptbr_mode), .io_requestor_9_ptbr_ppn (_ptw_io_requestor_9_ptbr_ppn), .io_requestor_9_status_debug (_ptw_io_requestor_9_status_debug), .io_requestor_9_status_cease (_ptw_io_requestor_9_status_cease), .io_requestor_9_status_wfi (_ptw_io_requestor_9_status_wfi), .io_requestor_9_status_isa (_ptw_io_requestor_9_status_isa), .io_requestor_9_status_dprv (_ptw_io_requestor_9_status_dprv), .io_requestor_9_status_dv (_ptw_io_requestor_9_status_dv), .io_requestor_9_status_prv (_ptw_io_requestor_9_status_prv), .io_requestor_9_status_v (_ptw_io_requestor_9_status_v), .io_requestor_9_status_mpv (_ptw_io_requestor_9_status_mpv), .io_requestor_9_status_gva (_ptw_io_requestor_9_status_gva), .io_requestor_9_status_tsr (_ptw_io_requestor_9_status_tsr), .io_requestor_9_status_tw (_ptw_io_requestor_9_status_tw), .io_requestor_9_status_tvm (_ptw_io_requestor_9_status_tvm), .io_requestor_9_status_mxr (_ptw_io_requestor_9_status_mxr), .io_requestor_9_status_sum (_ptw_io_requestor_9_status_sum), .io_requestor_9_status_mprv (_ptw_io_requestor_9_status_mprv), .io_requestor_9_status_fs (_ptw_io_requestor_9_status_fs), .io_requestor_9_status_mpp (_ptw_io_requestor_9_status_mpp), .io_requestor_9_status_spp (_ptw_io_requestor_9_status_spp), .io_requestor_9_status_mpie (_ptw_io_requestor_9_status_mpie), .io_requestor_9_status_spie (_ptw_io_requestor_9_status_spie), .io_requestor_9_status_mie (_ptw_io_requestor_9_status_mie), .io_requestor_9_status_sie (_ptw_io_requestor_9_status_sie), .io_requestor_9_hstatus_spvp (_ptw_io_requestor_9_hstatus_spvp), .io_requestor_9_hstatus_spv (_ptw_io_requestor_9_hstatus_spv), .io_requestor_9_hstatus_gva (_ptw_io_requestor_9_hstatus_gva), .io_requestor_9_gstatus_debug (_ptw_io_requestor_9_gstatus_debug), .io_requestor_9_gstatus_cease (_ptw_io_requestor_9_gstatus_cease), .io_requestor_9_gstatus_wfi (_ptw_io_requestor_9_gstatus_wfi), .io_requestor_9_gstatus_isa (_ptw_io_requestor_9_gstatus_isa), .io_requestor_9_gstatus_dprv (_ptw_io_requestor_9_gstatus_dprv), .io_requestor_9_gstatus_dv (_ptw_io_requestor_9_gstatus_dv), .io_requestor_9_gstatus_prv (_ptw_io_requestor_9_gstatus_prv), .io_requestor_9_gstatus_v (_ptw_io_requestor_9_gstatus_v), .io_requestor_9_gstatus_zero2 (_ptw_io_requestor_9_gstatus_zero2), .io_requestor_9_gstatus_mpv (_ptw_io_requestor_9_gstatus_mpv), .io_requestor_9_gstatus_gva (_ptw_io_requestor_9_gstatus_gva), .io_requestor_9_gstatus_mbe (_ptw_io_requestor_9_gstatus_mbe), .io_requestor_9_gstatus_sbe (_ptw_io_requestor_9_gstatus_sbe), .io_requestor_9_gstatus_sxl (_ptw_io_requestor_9_gstatus_sxl), .io_requestor_9_gstatus_zero1 (_ptw_io_requestor_9_gstatus_zero1), .io_requestor_9_gstatus_tsr (_ptw_io_requestor_9_gstatus_tsr), .io_requestor_9_gstatus_tw (_ptw_io_requestor_9_gstatus_tw), .io_requestor_9_gstatus_tvm (_ptw_io_requestor_9_gstatus_tvm), .io_requestor_9_gstatus_mxr (_ptw_io_requestor_9_gstatus_mxr), .io_requestor_9_gstatus_sum (_ptw_io_requestor_9_gstatus_sum), .io_requestor_9_gstatus_mprv (_ptw_io_requestor_9_gstatus_mprv), .io_requestor_9_gstatus_fs (_ptw_io_requestor_9_gstatus_fs), .io_requestor_9_gstatus_mpp (_ptw_io_requestor_9_gstatus_mpp), .io_requestor_9_gstatus_vs (_ptw_io_requestor_9_gstatus_vs), .io_requestor_9_gstatus_spp (_ptw_io_requestor_9_gstatus_spp), .io_requestor_9_gstatus_mpie (_ptw_io_requestor_9_gstatus_mpie), .io_requestor_9_gstatus_ube (_ptw_io_requestor_9_gstatus_ube), .io_requestor_9_gstatus_spie (_ptw_io_requestor_9_gstatus_spie), .io_requestor_9_gstatus_upie (_ptw_io_requestor_9_gstatus_upie), .io_requestor_9_gstatus_mie (_ptw_io_requestor_9_gstatus_mie), .io_requestor_9_gstatus_hie (_ptw_io_requestor_9_gstatus_hie), .io_requestor_9_gstatus_sie (_ptw_io_requestor_9_gstatus_sie), .io_requestor_9_gstatus_uie (_ptw_io_requestor_9_gstatus_uie), .io_requestor_9_pmp_0_cfg_l (_ptw_io_requestor_9_pmp_0_cfg_l), .io_requestor_9_pmp_0_cfg_a (_ptw_io_requestor_9_pmp_0_cfg_a), .io_requestor_9_pmp_0_cfg_x (_ptw_io_requestor_9_pmp_0_cfg_x), .io_requestor_9_pmp_0_cfg_w (_ptw_io_requestor_9_pmp_0_cfg_w), .io_requestor_9_pmp_0_cfg_r (_ptw_io_requestor_9_pmp_0_cfg_r), .io_requestor_9_pmp_0_addr (_ptw_io_requestor_9_pmp_0_addr), .io_requestor_9_pmp_0_mask (_ptw_io_requestor_9_pmp_0_mask), .io_requestor_9_pmp_1_cfg_l (_ptw_io_requestor_9_pmp_1_cfg_l), .io_requestor_9_pmp_1_cfg_a (_ptw_io_requestor_9_pmp_1_cfg_a), .io_requestor_9_pmp_1_cfg_x (_ptw_io_requestor_9_pmp_1_cfg_x), .io_requestor_9_pmp_1_cfg_w (_ptw_io_requestor_9_pmp_1_cfg_w), .io_requestor_9_pmp_1_cfg_r (_ptw_io_requestor_9_pmp_1_cfg_r), .io_requestor_9_pmp_1_addr (_ptw_io_requestor_9_pmp_1_addr), .io_requestor_9_pmp_1_mask (_ptw_io_requestor_9_pmp_1_mask), .io_requestor_9_pmp_2_cfg_l (_ptw_io_requestor_9_pmp_2_cfg_l), .io_requestor_9_pmp_2_cfg_a (_ptw_io_requestor_9_pmp_2_cfg_a), .io_requestor_9_pmp_2_cfg_x (_ptw_io_requestor_9_pmp_2_cfg_x), .io_requestor_9_pmp_2_cfg_w (_ptw_io_requestor_9_pmp_2_cfg_w), .io_requestor_9_pmp_2_cfg_r (_ptw_io_requestor_9_pmp_2_cfg_r), .io_requestor_9_pmp_2_addr (_ptw_io_requestor_9_pmp_2_addr), .io_requestor_9_pmp_2_mask (_ptw_io_requestor_9_pmp_2_mask), .io_requestor_9_pmp_3_cfg_l (_ptw_io_requestor_9_pmp_3_cfg_l), .io_requestor_9_pmp_3_cfg_a (_ptw_io_requestor_9_pmp_3_cfg_a), .io_requestor_9_pmp_3_cfg_x (_ptw_io_requestor_9_pmp_3_cfg_x), .io_requestor_9_pmp_3_cfg_w (_ptw_io_requestor_9_pmp_3_cfg_w), .io_requestor_9_pmp_3_cfg_r (_ptw_io_requestor_9_pmp_3_cfg_r), .io_requestor_9_pmp_3_addr (_ptw_io_requestor_9_pmp_3_addr), .io_requestor_9_pmp_3_mask (_ptw_io_requestor_9_pmp_3_mask), .io_requestor_9_pmp_4_cfg_l (_ptw_io_requestor_9_pmp_4_cfg_l), .io_requestor_9_pmp_4_cfg_a (_ptw_io_requestor_9_pmp_4_cfg_a), .io_requestor_9_pmp_4_cfg_x (_ptw_io_requestor_9_pmp_4_cfg_x), .io_requestor_9_pmp_4_cfg_w (_ptw_io_requestor_9_pmp_4_cfg_w), .io_requestor_9_pmp_4_cfg_r (_ptw_io_requestor_9_pmp_4_cfg_r), .io_requestor_9_pmp_4_addr (_ptw_io_requestor_9_pmp_4_addr), .io_requestor_9_pmp_4_mask (_ptw_io_requestor_9_pmp_4_mask), .io_requestor_9_pmp_5_cfg_l (_ptw_io_requestor_9_pmp_5_cfg_l), .io_requestor_9_pmp_5_cfg_a (_ptw_io_requestor_9_pmp_5_cfg_a), .io_requestor_9_pmp_5_cfg_x (_ptw_io_requestor_9_pmp_5_cfg_x), .io_requestor_9_pmp_5_cfg_w (_ptw_io_requestor_9_pmp_5_cfg_w), .io_requestor_9_pmp_5_cfg_r (_ptw_io_requestor_9_pmp_5_cfg_r), .io_requestor_9_pmp_5_addr (_ptw_io_requestor_9_pmp_5_addr), .io_requestor_9_pmp_5_mask (_ptw_io_requestor_9_pmp_5_mask), .io_requestor_9_pmp_6_cfg_l (_ptw_io_requestor_9_pmp_6_cfg_l), .io_requestor_9_pmp_6_cfg_a (_ptw_io_requestor_9_pmp_6_cfg_a), .io_requestor_9_pmp_6_cfg_x (_ptw_io_requestor_9_pmp_6_cfg_x), .io_requestor_9_pmp_6_cfg_w (_ptw_io_requestor_9_pmp_6_cfg_w), .io_requestor_9_pmp_6_cfg_r (_ptw_io_requestor_9_pmp_6_cfg_r), .io_requestor_9_pmp_6_addr (_ptw_io_requestor_9_pmp_6_addr), .io_requestor_9_pmp_6_mask (_ptw_io_requestor_9_pmp_6_mask), .io_requestor_9_pmp_7_cfg_l (_ptw_io_requestor_9_pmp_7_cfg_l), .io_requestor_9_pmp_7_cfg_a (_ptw_io_requestor_9_pmp_7_cfg_a), .io_requestor_9_pmp_7_cfg_x (_ptw_io_requestor_9_pmp_7_cfg_x), .io_requestor_9_pmp_7_cfg_w (_ptw_io_requestor_9_pmp_7_cfg_w), .io_requestor_9_pmp_7_cfg_r (_ptw_io_requestor_9_pmp_7_cfg_r), .io_requestor_9_pmp_7_addr (_ptw_io_requestor_9_pmp_7_addr), .io_requestor_9_pmp_7_mask (_ptw_io_requestor_9_pmp_7_mask), .io_requestor_9_customCSRs_csrs_0_ren (_ptw_io_requestor_9_customCSRs_csrs_0_ren), .io_requestor_9_customCSRs_csrs_0_wen (_ptw_io_requestor_9_customCSRs_csrs_0_wen), .io_requestor_9_customCSRs_csrs_0_wdata (_ptw_io_requestor_9_customCSRs_csrs_0_wdata), .io_requestor_9_customCSRs_csrs_0_value (_ptw_io_requestor_9_customCSRs_csrs_0_value), .io_requestor_9_customCSRs_csrs_1_ren (_ptw_io_requestor_9_customCSRs_csrs_1_ren), .io_requestor_9_customCSRs_csrs_1_wen (_ptw_io_requestor_9_customCSRs_csrs_1_wen), .io_requestor_9_customCSRs_csrs_1_wdata (_ptw_io_requestor_9_customCSRs_csrs_1_wdata), .io_requestor_9_customCSRs_csrs_1_value (_ptw_io_requestor_9_customCSRs_csrs_1_value), .io_requestor_9_customCSRs_csrs_2_ren (_ptw_io_requestor_9_customCSRs_csrs_2_ren), .io_requestor_9_customCSRs_csrs_2_wen (_ptw_io_requestor_9_customCSRs_csrs_2_wen), .io_requestor_9_customCSRs_csrs_2_wdata (_ptw_io_requestor_9_customCSRs_csrs_2_wdata), .io_requestor_9_customCSRs_csrs_2_value (_ptw_io_requestor_9_customCSRs_csrs_2_value), .io_requestor_9_customCSRs_csrs_3_ren (_ptw_io_requestor_9_customCSRs_csrs_3_ren), .io_requestor_9_customCSRs_csrs_3_wen (_ptw_io_requestor_9_customCSRs_csrs_3_wen), .io_requestor_9_customCSRs_csrs_3_wdata (_ptw_io_requestor_9_customCSRs_csrs_3_wdata), .io_requestor_9_customCSRs_csrs_3_value (_ptw_io_requestor_9_customCSRs_csrs_3_value), .io_requestor_10_req_ready (_ptw_io_requestor_10_req_ready), .io_requestor_10_req_valid (_zstd_compressor_io_ptw_10_req_valid), // @[Configs.scala:62:39] .io_requestor_10_req_bits_bits_addr (_zstd_compressor_io_ptw_10_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_10_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_10_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_10_resp_valid (_ptw_io_requestor_10_resp_valid), .io_requestor_10_resp_bits_ae_ptw (_ptw_io_requestor_10_resp_bits_ae_ptw), .io_requestor_10_resp_bits_ae_final (_ptw_io_requestor_10_resp_bits_ae_final), .io_requestor_10_resp_bits_pf (_ptw_io_requestor_10_resp_bits_pf), .io_requestor_10_resp_bits_gf (_ptw_io_requestor_10_resp_bits_gf), .io_requestor_10_resp_bits_hr (_ptw_io_requestor_10_resp_bits_hr), .io_requestor_10_resp_bits_hw (_ptw_io_requestor_10_resp_bits_hw), .io_requestor_10_resp_bits_hx (_ptw_io_requestor_10_resp_bits_hx), .io_requestor_10_resp_bits_pte_reserved_for_future (_ptw_io_requestor_10_resp_bits_pte_reserved_for_future), .io_requestor_10_resp_bits_pte_ppn (_ptw_io_requestor_10_resp_bits_pte_ppn), .io_requestor_10_resp_bits_pte_reserved_for_software (_ptw_io_requestor_10_resp_bits_pte_reserved_for_software), .io_requestor_10_resp_bits_pte_d (_ptw_io_requestor_10_resp_bits_pte_d), .io_requestor_10_resp_bits_pte_a (_ptw_io_requestor_10_resp_bits_pte_a), .io_requestor_10_resp_bits_pte_g (_ptw_io_requestor_10_resp_bits_pte_g), .io_requestor_10_resp_bits_pte_u (_ptw_io_requestor_10_resp_bits_pte_u), .io_requestor_10_resp_bits_pte_x (_ptw_io_requestor_10_resp_bits_pte_x), .io_requestor_10_resp_bits_pte_w (_ptw_io_requestor_10_resp_bits_pte_w), .io_requestor_10_resp_bits_pte_r (_ptw_io_requestor_10_resp_bits_pte_r), .io_requestor_10_resp_bits_pte_v (_ptw_io_requestor_10_resp_bits_pte_v), .io_requestor_10_resp_bits_level (_ptw_io_requestor_10_resp_bits_level), .io_requestor_10_resp_bits_homogeneous (_ptw_io_requestor_10_resp_bits_homogeneous), .io_requestor_10_resp_bits_gpa_valid (_ptw_io_requestor_10_resp_bits_gpa_valid), .io_requestor_10_resp_bits_gpa_bits (_ptw_io_requestor_10_resp_bits_gpa_bits), .io_requestor_10_resp_bits_gpa_is_pte (_ptw_io_requestor_10_resp_bits_gpa_is_pte), .io_requestor_10_ptbr_mode (_ptw_io_requestor_10_ptbr_mode), .io_requestor_10_ptbr_ppn (_ptw_io_requestor_10_ptbr_ppn), .io_requestor_10_status_debug (_ptw_io_requestor_10_status_debug), .io_requestor_10_status_cease (_ptw_io_requestor_10_status_cease), .io_requestor_10_status_wfi (_ptw_io_requestor_10_status_wfi), .io_requestor_10_status_isa (_ptw_io_requestor_10_status_isa), .io_requestor_10_status_dprv (_ptw_io_requestor_10_status_dprv), .io_requestor_10_status_dv (_ptw_io_requestor_10_status_dv), .io_requestor_10_status_prv (_ptw_io_requestor_10_status_prv), .io_requestor_10_status_v (_ptw_io_requestor_10_status_v), .io_requestor_10_status_mpv (_ptw_io_requestor_10_status_mpv), .io_requestor_10_status_gva (_ptw_io_requestor_10_status_gva), .io_requestor_10_status_tsr (_ptw_io_requestor_10_status_tsr), .io_requestor_10_status_tw (_ptw_io_requestor_10_status_tw), .io_requestor_10_status_tvm (_ptw_io_requestor_10_status_tvm), .io_requestor_10_status_mxr (_ptw_io_requestor_10_status_mxr), .io_requestor_10_status_sum (_ptw_io_requestor_10_status_sum), .io_requestor_10_status_mprv (_ptw_io_requestor_10_status_mprv), .io_requestor_10_status_fs (_ptw_io_requestor_10_status_fs), .io_requestor_10_status_mpp (_ptw_io_requestor_10_status_mpp), .io_requestor_10_status_spp (_ptw_io_requestor_10_status_spp), .io_requestor_10_status_mpie (_ptw_io_requestor_10_status_mpie), .io_requestor_10_status_spie (_ptw_io_requestor_10_status_spie), .io_requestor_10_status_mie (_ptw_io_requestor_10_status_mie), .io_requestor_10_status_sie (_ptw_io_requestor_10_status_sie), .io_requestor_10_hstatus_spvp (_ptw_io_requestor_10_hstatus_spvp), .io_requestor_10_hstatus_spv (_ptw_io_requestor_10_hstatus_spv), .io_requestor_10_hstatus_gva (_ptw_io_requestor_10_hstatus_gva), .io_requestor_10_gstatus_debug (_ptw_io_requestor_10_gstatus_debug), .io_requestor_10_gstatus_cease (_ptw_io_requestor_10_gstatus_cease), .io_requestor_10_gstatus_wfi (_ptw_io_requestor_10_gstatus_wfi), .io_requestor_10_gstatus_isa (_ptw_io_requestor_10_gstatus_isa), .io_requestor_10_gstatus_dprv (_ptw_io_requestor_10_gstatus_dprv), .io_requestor_10_gstatus_dv (_ptw_io_requestor_10_gstatus_dv), .io_requestor_10_gstatus_prv (_ptw_io_requestor_10_gstatus_prv), .io_requestor_10_gstatus_v (_ptw_io_requestor_10_gstatus_v), .io_requestor_10_gstatus_zero2 (_ptw_io_requestor_10_gstatus_zero2), .io_requestor_10_gstatus_mpv (_ptw_io_requestor_10_gstatus_mpv), .io_requestor_10_gstatus_gva (_ptw_io_requestor_10_gstatus_gva), .io_requestor_10_gstatus_mbe (_ptw_io_requestor_10_gstatus_mbe), .io_requestor_10_gstatus_sbe (_ptw_io_requestor_10_gstatus_sbe), .io_requestor_10_gstatus_sxl (_ptw_io_requestor_10_gstatus_sxl), .io_requestor_10_gstatus_zero1 (_ptw_io_requestor_10_gstatus_zero1), .io_requestor_10_gstatus_tsr (_ptw_io_requestor_10_gstatus_tsr), .io_requestor_10_gstatus_tw (_ptw_io_requestor_10_gstatus_tw), .io_requestor_10_gstatus_tvm (_ptw_io_requestor_10_gstatus_tvm), .io_requestor_10_gstatus_mxr (_ptw_io_requestor_10_gstatus_mxr), .io_requestor_10_gstatus_sum (_ptw_io_requestor_10_gstatus_sum), .io_requestor_10_gstatus_mprv (_ptw_io_requestor_10_gstatus_mprv), .io_requestor_10_gstatus_fs (_ptw_io_requestor_10_gstatus_fs), .io_requestor_10_gstatus_mpp (_ptw_io_requestor_10_gstatus_mpp), .io_requestor_10_gstatus_vs (_ptw_io_requestor_10_gstatus_vs), .io_requestor_10_gstatus_spp (_ptw_io_requestor_10_gstatus_spp), .io_requestor_10_gstatus_mpie (_ptw_io_requestor_10_gstatus_mpie), .io_requestor_10_gstatus_ube (_ptw_io_requestor_10_gstatus_ube), .io_requestor_10_gstatus_spie (_ptw_io_requestor_10_gstatus_spie), .io_requestor_10_gstatus_upie (_ptw_io_requestor_10_gstatus_upie), .io_requestor_10_gstatus_mie (_ptw_io_requestor_10_gstatus_mie), .io_requestor_10_gstatus_hie (_ptw_io_requestor_10_gstatus_hie), .io_requestor_10_gstatus_sie (_ptw_io_requestor_10_gstatus_sie), .io_requestor_10_gstatus_uie (_ptw_io_requestor_10_gstatus_uie), .io_requestor_10_pmp_0_cfg_l (_ptw_io_requestor_10_pmp_0_cfg_l), .io_requestor_10_pmp_0_cfg_a (_ptw_io_requestor_10_pmp_0_cfg_a), .io_requestor_10_pmp_0_cfg_x (_ptw_io_requestor_10_pmp_0_cfg_x), .io_requestor_10_pmp_0_cfg_w (_ptw_io_requestor_10_pmp_0_cfg_w), .io_requestor_10_pmp_0_cfg_r (_ptw_io_requestor_10_pmp_0_cfg_r), .io_requestor_10_pmp_0_addr (_ptw_io_requestor_10_pmp_0_addr), .io_requestor_10_pmp_0_mask (_ptw_io_requestor_10_pmp_0_mask), .io_requestor_10_pmp_1_cfg_l (_ptw_io_requestor_10_pmp_1_cfg_l), .io_requestor_10_pmp_1_cfg_a (_ptw_io_requestor_10_pmp_1_cfg_a), .io_requestor_10_pmp_1_cfg_x (_ptw_io_requestor_10_pmp_1_cfg_x), .io_requestor_10_pmp_1_cfg_w (_ptw_io_requestor_10_pmp_1_cfg_w), .io_requestor_10_pmp_1_cfg_r (_ptw_io_requestor_10_pmp_1_cfg_r), .io_requestor_10_pmp_1_addr (_ptw_io_requestor_10_pmp_1_addr), .io_requestor_10_pmp_1_mask (_ptw_io_requestor_10_pmp_1_mask), .io_requestor_10_pmp_2_cfg_l (_ptw_io_requestor_10_pmp_2_cfg_l), .io_requestor_10_pmp_2_cfg_a (_ptw_io_requestor_10_pmp_2_cfg_a), .io_requestor_10_pmp_2_cfg_x (_ptw_io_requestor_10_pmp_2_cfg_x), .io_requestor_10_pmp_2_cfg_w (_ptw_io_requestor_10_pmp_2_cfg_w), .io_requestor_10_pmp_2_cfg_r (_ptw_io_requestor_10_pmp_2_cfg_r), .io_requestor_10_pmp_2_addr (_ptw_io_requestor_10_pmp_2_addr), .io_requestor_10_pmp_2_mask (_ptw_io_requestor_10_pmp_2_mask), .io_requestor_10_pmp_3_cfg_l (_ptw_io_requestor_10_pmp_3_cfg_l), .io_requestor_10_pmp_3_cfg_a (_ptw_io_requestor_10_pmp_3_cfg_a), .io_requestor_10_pmp_3_cfg_x (_ptw_io_requestor_10_pmp_3_cfg_x), .io_requestor_10_pmp_3_cfg_w (_ptw_io_requestor_10_pmp_3_cfg_w), .io_requestor_10_pmp_3_cfg_r (_ptw_io_requestor_10_pmp_3_cfg_r), .io_requestor_10_pmp_3_addr (_ptw_io_requestor_10_pmp_3_addr), .io_requestor_10_pmp_3_mask (_ptw_io_requestor_10_pmp_3_mask), .io_requestor_10_pmp_4_cfg_l (_ptw_io_requestor_10_pmp_4_cfg_l), .io_requestor_10_pmp_4_cfg_a (_ptw_io_requestor_10_pmp_4_cfg_a), .io_requestor_10_pmp_4_cfg_x (_ptw_io_requestor_10_pmp_4_cfg_x), .io_requestor_10_pmp_4_cfg_w (_ptw_io_requestor_10_pmp_4_cfg_w), .io_requestor_10_pmp_4_cfg_r (_ptw_io_requestor_10_pmp_4_cfg_r), .io_requestor_10_pmp_4_addr (_ptw_io_requestor_10_pmp_4_addr), .io_requestor_10_pmp_4_mask (_ptw_io_requestor_10_pmp_4_mask), .io_requestor_10_pmp_5_cfg_l (_ptw_io_requestor_10_pmp_5_cfg_l), .io_requestor_10_pmp_5_cfg_a (_ptw_io_requestor_10_pmp_5_cfg_a), .io_requestor_10_pmp_5_cfg_x (_ptw_io_requestor_10_pmp_5_cfg_x), .io_requestor_10_pmp_5_cfg_w (_ptw_io_requestor_10_pmp_5_cfg_w), .io_requestor_10_pmp_5_cfg_r (_ptw_io_requestor_10_pmp_5_cfg_r), .io_requestor_10_pmp_5_addr (_ptw_io_requestor_10_pmp_5_addr), .io_requestor_10_pmp_5_mask (_ptw_io_requestor_10_pmp_5_mask), .io_requestor_10_pmp_6_cfg_l (_ptw_io_requestor_10_pmp_6_cfg_l), .io_requestor_10_pmp_6_cfg_a (_ptw_io_requestor_10_pmp_6_cfg_a), .io_requestor_10_pmp_6_cfg_x (_ptw_io_requestor_10_pmp_6_cfg_x), .io_requestor_10_pmp_6_cfg_w (_ptw_io_requestor_10_pmp_6_cfg_w), .io_requestor_10_pmp_6_cfg_r (_ptw_io_requestor_10_pmp_6_cfg_r), .io_requestor_10_pmp_6_addr (_ptw_io_requestor_10_pmp_6_addr), .io_requestor_10_pmp_6_mask (_ptw_io_requestor_10_pmp_6_mask), .io_requestor_10_pmp_7_cfg_l (_ptw_io_requestor_10_pmp_7_cfg_l), .io_requestor_10_pmp_7_cfg_a (_ptw_io_requestor_10_pmp_7_cfg_a), .io_requestor_10_pmp_7_cfg_x (_ptw_io_requestor_10_pmp_7_cfg_x), .io_requestor_10_pmp_7_cfg_w (_ptw_io_requestor_10_pmp_7_cfg_w), .io_requestor_10_pmp_7_cfg_r (_ptw_io_requestor_10_pmp_7_cfg_r), .io_requestor_10_pmp_7_addr (_ptw_io_requestor_10_pmp_7_addr), .io_requestor_10_pmp_7_mask (_ptw_io_requestor_10_pmp_7_mask), .io_requestor_10_customCSRs_csrs_0_ren (_ptw_io_requestor_10_customCSRs_csrs_0_ren), .io_requestor_10_customCSRs_csrs_0_wen (_ptw_io_requestor_10_customCSRs_csrs_0_wen), .io_requestor_10_customCSRs_csrs_0_wdata (_ptw_io_requestor_10_customCSRs_csrs_0_wdata), .io_requestor_10_customCSRs_csrs_0_value (_ptw_io_requestor_10_customCSRs_csrs_0_value), .io_requestor_10_customCSRs_csrs_1_ren (_ptw_io_requestor_10_customCSRs_csrs_1_ren), .io_requestor_10_customCSRs_csrs_1_wen (_ptw_io_requestor_10_customCSRs_csrs_1_wen), .io_requestor_10_customCSRs_csrs_1_wdata (_ptw_io_requestor_10_customCSRs_csrs_1_wdata), .io_requestor_10_customCSRs_csrs_1_value (_ptw_io_requestor_10_customCSRs_csrs_1_value), .io_requestor_10_customCSRs_csrs_2_ren (_ptw_io_requestor_10_customCSRs_csrs_2_ren), .io_requestor_10_customCSRs_csrs_2_wen (_ptw_io_requestor_10_customCSRs_csrs_2_wen), .io_requestor_10_customCSRs_csrs_2_wdata (_ptw_io_requestor_10_customCSRs_csrs_2_wdata), .io_requestor_10_customCSRs_csrs_2_value (_ptw_io_requestor_10_customCSRs_csrs_2_value), .io_requestor_10_customCSRs_csrs_3_ren (_ptw_io_requestor_10_customCSRs_csrs_3_ren), .io_requestor_10_customCSRs_csrs_3_wen (_ptw_io_requestor_10_customCSRs_csrs_3_wen), .io_requestor_10_customCSRs_csrs_3_wdata (_ptw_io_requestor_10_customCSRs_csrs_3_wdata), .io_requestor_10_customCSRs_csrs_3_value (_ptw_io_requestor_10_customCSRs_csrs_3_value), .io_requestor_11_req_ready (_ptw_io_requestor_11_req_ready), .io_requestor_11_req_valid (_zstd_compressor_io_ptw_11_req_valid), // @[Configs.scala:62:39] .io_requestor_11_req_bits_bits_addr (_zstd_compressor_io_ptw_11_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_11_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_11_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_11_resp_valid (_ptw_io_requestor_11_resp_valid), .io_requestor_11_resp_bits_ae_ptw (_ptw_io_requestor_11_resp_bits_ae_ptw), .io_requestor_11_resp_bits_ae_final (_ptw_io_requestor_11_resp_bits_ae_final), .io_requestor_11_resp_bits_pf (_ptw_io_requestor_11_resp_bits_pf), .io_requestor_11_resp_bits_gf (_ptw_io_requestor_11_resp_bits_gf), .io_requestor_11_resp_bits_hr (_ptw_io_requestor_11_resp_bits_hr), .io_requestor_11_resp_bits_hw (_ptw_io_requestor_11_resp_bits_hw), .io_requestor_11_resp_bits_hx (_ptw_io_requestor_11_resp_bits_hx), .io_requestor_11_resp_bits_pte_reserved_for_future (_ptw_io_requestor_11_resp_bits_pte_reserved_for_future), .io_requestor_11_resp_bits_pte_ppn (_ptw_io_requestor_11_resp_bits_pte_ppn), .io_requestor_11_resp_bits_pte_reserved_for_software (_ptw_io_requestor_11_resp_bits_pte_reserved_for_software), .io_requestor_11_resp_bits_pte_d (_ptw_io_requestor_11_resp_bits_pte_d), .io_requestor_11_resp_bits_pte_a (_ptw_io_requestor_11_resp_bits_pte_a), .io_requestor_11_resp_bits_pte_g (_ptw_io_requestor_11_resp_bits_pte_g), .io_requestor_11_resp_bits_pte_u (_ptw_io_requestor_11_resp_bits_pte_u), .io_requestor_11_resp_bits_pte_x (_ptw_io_requestor_11_resp_bits_pte_x), .io_requestor_11_resp_bits_pte_w (_ptw_io_requestor_11_resp_bits_pte_w), .io_requestor_11_resp_bits_pte_r (_ptw_io_requestor_11_resp_bits_pte_r), .io_requestor_11_resp_bits_pte_v (_ptw_io_requestor_11_resp_bits_pte_v), .io_requestor_11_resp_bits_level (_ptw_io_requestor_11_resp_bits_level), .io_requestor_11_resp_bits_homogeneous (_ptw_io_requestor_11_resp_bits_homogeneous), .io_requestor_11_resp_bits_gpa_valid (_ptw_io_requestor_11_resp_bits_gpa_valid), .io_requestor_11_resp_bits_gpa_bits (_ptw_io_requestor_11_resp_bits_gpa_bits), .io_requestor_11_resp_bits_gpa_is_pte (_ptw_io_requestor_11_resp_bits_gpa_is_pte), .io_requestor_11_ptbr_mode (_ptw_io_requestor_11_ptbr_mode), .io_requestor_11_ptbr_ppn (_ptw_io_requestor_11_ptbr_ppn), .io_requestor_11_status_debug (_ptw_io_requestor_11_status_debug), .io_requestor_11_status_cease (_ptw_io_requestor_11_status_cease), .io_requestor_11_status_wfi (_ptw_io_requestor_11_status_wfi), .io_requestor_11_status_isa (_ptw_io_requestor_11_status_isa), .io_requestor_11_status_dprv (_ptw_io_requestor_11_status_dprv), .io_requestor_11_status_dv (_ptw_io_requestor_11_status_dv), .io_requestor_11_status_prv (_ptw_io_requestor_11_status_prv), .io_requestor_11_status_v (_ptw_io_requestor_11_status_v), .io_requestor_11_status_mpv (_ptw_io_requestor_11_status_mpv), .io_requestor_11_status_gva (_ptw_io_requestor_11_status_gva), .io_requestor_11_status_tsr (_ptw_io_requestor_11_status_tsr), .io_requestor_11_status_tw (_ptw_io_requestor_11_status_tw), .io_requestor_11_status_tvm (_ptw_io_requestor_11_status_tvm), .io_requestor_11_status_mxr (_ptw_io_requestor_11_status_mxr), .io_requestor_11_status_sum (_ptw_io_requestor_11_status_sum), .io_requestor_11_status_mprv (_ptw_io_requestor_11_status_mprv), .io_requestor_11_status_fs (_ptw_io_requestor_11_status_fs), .io_requestor_11_status_mpp (_ptw_io_requestor_11_status_mpp), .io_requestor_11_status_spp (_ptw_io_requestor_11_status_spp), .io_requestor_11_status_mpie (_ptw_io_requestor_11_status_mpie), .io_requestor_11_status_spie (_ptw_io_requestor_11_status_spie), .io_requestor_11_status_mie (_ptw_io_requestor_11_status_mie), .io_requestor_11_status_sie (_ptw_io_requestor_11_status_sie), .io_requestor_11_hstatus_spvp (_ptw_io_requestor_11_hstatus_spvp), .io_requestor_11_hstatus_spv (_ptw_io_requestor_11_hstatus_spv), .io_requestor_11_hstatus_gva (_ptw_io_requestor_11_hstatus_gva), .io_requestor_11_gstatus_debug (_ptw_io_requestor_11_gstatus_debug), .io_requestor_11_gstatus_cease (_ptw_io_requestor_11_gstatus_cease), .io_requestor_11_gstatus_wfi (_ptw_io_requestor_11_gstatus_wfi), .io_requestor_11_gstatus_isa (_ptw_io_requestor_11_gstatus_isa), .io_requestor_11_gstatus_dprv (_ptw_io_requestor_11_gstatus_dprv), .io_requestor_11_gstatus_dv (_ptw_io_requestor_11_gstatus_dv), .io_requestor_11_gstatus_prv (_ptw_io_requestor_11_gstatus_prv), .io_requestor_11_gstatus_v (_ptw_io_requestor_11_gstatus_v), .io_requestor_11_gstatus_zero2 (_ptw_io_requestor_11_gstatus_zero2), .io_requestor_11_gstatus_mpv (_ptw_io_requestor_11_gstatus_mpv), .io_requestor_11_gstatus_gva (_ptw_io_requestor_11_gstatus_gva), .io_requestor_11_gstatus_mbe (_ptw_io_requestor_11_gstatus_mbe), .io_requestor_11_gstatus_sbe (_ptw_io_requestor_11_gstatus_sbe), .io_requestor_11_gstatus_sxl (_ptw_io_requestor_11_gstatus_sxl), .io_requestor_11_gstatus_zero1 (_ptw_io_requestor_11_gstatus_zero1), .io_requestor_11_gstatus_tsr (_ptw_io_requestor_11_gstatus_tsr), .io_requestor_11_gstatus_tw (_ptw_io_requestor_11_gstatus_tw), .io_requestor_11_gstatus_tvm (_ptw_io_requestor_11_gstatus_tvm), .io_requestor_11_gstatus_mxr (_ptw_io_requestor_11_gstatus_mxr), .io_requestor_11_gstatus_sum (_ptw_io_requestor_11_gstatus_sum), .io_requestor_11_gstatus_mprv (_ptw_io_requestor_11_gstatus_mprv), .io_requestor_11_gstatus_fs (_ptw_io_requestor_11_gstatus_fs), .io_requestor_11_gstatus_mpp (_ptw_io_requestor_11_gstatus_mpp), .io_requestor_11_gstatus_vs (_ptw_io_requestor_11_gstatus_vs), .io_requestor_11_gstatus_spp (_ptw_io_requestor_11_gstatus_spp), .io_requestor_11_gstatus_mpie (_ptw_io_requestor_11_gstatus_mpie), .io_requestor_11_gstatus_ube (_ptw_io_requestor_11_gstatus_ube), .io_requestor_11_gstatus_spie (_ptw_io_requestor_11_gstatus_spie), .io_requestor_11_gstatus_upie (_ptw_io_requestor_11_gstatus_upie), .io_requestor_11_gstatus_mie (_ptw_io_requestor_11_gstatus_mie), .io_requestor_11_gstatus_hie (_ptw_io_requestor_11_gstatus_hie), .io_requestor_11_gstatus_sie (_ptw_io_requestor_11_gstatus_sie), .io_requestor_11_gstatus_uie (_ptw_io_requestor_11_gstatus_uie), .io_requestor_11_pmp_0_cfg_l (_ptw_io_requestor_11_pmp_0_cfg_l), .io_requestor_11_pmp_0_cfg_a (_ptw_io_requestor_11_pmp_0_cfg_a), .io_requestor_11_pmp_0_cfg_x (_ptw_io_requestor_11_pmp_0_cfg_x), .io_requestor_11_pmp_0_cfg_w (_ptw_io_requestor_11_pmp_0_cfg_w), .io_requestor_11_pmp_0_cfg_r (_ptw_io_requestor_11_pmp_0_cfg_r), .io_requestor_11_pmp_0_addr (_ptw_io_requestor_11_pmp_0_addr), .io_requestor_11_pmp_0_mask (_ptw_io_requestor_11_pmp_0_mask), .io_requestor_11_pmp_1_cfg_l (_ptw_io_requestor_11_pmp_1_cfg_l), .io_requestor_11_pmp_1_cfg_a (_ptw_io_requestor_11_pmp_1_cfg_a), .io_requestor_11_pmp_1_cfg_x (_ptw_io_requestor_11_pmp_1_cfg_x), .io_requestor_11_pmp_1_cfg_w (_ptw_io_requestor_11_pmp_1_cfg_w), .io_requestor_11_pmp_1_cfg_r (_ptw_io_requestor_11_pmp_1_cfg_r), .io_requestor_11_pmp_1_addr (_ptw_io_requestor_11_pmp_1_addr), .io_requestor_11_pmp_1_mask (_ptw_io_requestor_11_pmp_1_mask), .io_requestor_11_pmp_2_cfg_l (_ptw_io_requestor_11_pmp_2_cfg_l), .io_requestor_11_pmp_2_cfg_a (_ptw_io_requestor_11_pmp_2_cfg_a), .io_requestor_11_pmp_2_cfg_x (_ptw_io_requestor_11_pmp_2_cfg_x), .io_requestor_11_pmp_2_cfg_w (_ptw_io_requestor_11_pmp_2_cfg_w), .io_requestor_11_pmp_2_cfg_r (_ptw_io_requestor_11_pmp_2_cfg_r), .io_requestor_11_pmp_2_addr (_ptw_io_requestor_11_pmp_2_addr), .io_requestor_11_pmp_2_mask (_ptw_io_requestor_11_pmp_2_mask), .io_requestor_11_pmp_3_cfg_l (_ptw_io_requestor_11_pmp_3_cfg_l), .io_requestor_11_pmp_3_cfg_a (_ptw_io_requestor_11_pmp_3_cfg_a), .io_requestor_11_pmp_3_cfg_x (_ptw_io_requestor_11_pmp_3_cfg_x), .io_requestor_11_pmp_3_cfg_w (_ptw_io_requestor_11_pmp_3_cfg_w), .io_requestor_11_pmp_3_cfg_r (_ptw_io_requestor_11_pmp_3_cfg_r), .io_requestor_11_pmp_3_addr (_ptw_io_requestor_11_pmp_3_addr), .io_requestor_11_pmp_3_mask (_ptw_io_requestor_11_pmp_3_mask), .io_requestor_11_pmp_4_cfg_l (_ptw_io_requestor_11_pmp_4_cfg_l), .io_requestor_11_pmp_4_cfg_a (_ptw_io_requestor_11_pmp_4_cfg_a), .io_requestor_11_pmp_4_cfg_x (_ptw_io_requestor_11_pmp_4_cfg_x), .io_requestor_11_pmp_4_cfg_w (_ptw_io_requestor_11_pmp_4_cfg_w), .io_requestor_11_pmp_4_cfg_r (_ptw_io_requestor_11_pmp_4_cfg_r), .io_requestor_11_pmp_4_addr (_ptw_io_requestor_11_pmp_4_addr), .io_requestor_11_pmp_4_mask (_ptw_io_requestor_11_pmp_4_mask), .io_requestor_11_pmp_5_cfg_l (_ptw_io_requestor_11_pmp_5_cfg_l), .io_requestor_11_pmp_5_cfg_a (_ptw_io_requestor_11_pmp_5_cfg_a), .io_requestor_11_pmp_5_cfg_x (_ptw_io_requestor_11_pmp_5_cfg_x), .io_requestor_11_pmp_5_cfg_w (_ptw_io_requestor_11_pmp_5_cfg_w), .io_requestor_11_pmp_5_cfg_r (_ptw_io_requestor_11_pmp_5_cfg_r), .io_requestor_11_pmp_5_addr (_ptw_io_requestor_11_pmp_5_addr), .io_requestor_11_pmp_5_mask (_ptw_io_requestor_11_pmp_5_mask), .io_requestor_11_pmp_6_cfg_l (_ptw_io_requestor_11_pmp_6_cfg_l), .io_requestor_11_pmp_6_cfg_a (_ptw_io_requestor_11_pmp_6_cfg_a), .io_requestor_11_pmp_6_cfg_x (_ptw_io_requestor_11_pmp_6_cfg_x), .io_requestor_11_pmp_6_cfg_w (_ptw_io_requestor_11_pmp_6_cfg_w), .io_requestor_11_pmp_6_cfg_r (_ptw_io_requestor_11_pmp_6_cfg_r), .io_requestor_11_pmp_6_addr (_ptw_io_requestor_11_pmp_6_addr), .io_requestor_11_pmp_6_mask (_ptw_io_requestor_11_pmp_6_mask), .io_requestor_11_pmp_7_cfg_l (_ptw_io_requestor_11_pmp_7_cfg_l), .io_requestor_11_pmp_7_cfg_a (_ptw_io_requestor_11_pmp_7_cfg_a), .io_requestor_11_pmp_7_cfg_x (_ptw_io_requestor_11_pmp_7_cfg_x), .io_requestor_11_pmp_7_cfg_w (_ptw_io_requestor_11_pmp_7_cfg_w), .io_requestor_11_pmp_7_cfg_r (_ptw_io_requestor_11_pmp_7_cfg_r), .io_requestor_11_pmp_7_addr (_ptw_io_requestor_11_pmp_7_addr), .io_requestor_11_pmp_7_mask (_ptw_io_requestor_11_pmp_7_mask), .io_requestor_11_customCSRs_csrs_0_ren (_ptw_io_requestor_11_customCSRs_csrs_0_ren), .io_requestor_11_customCSRs_csrs_0_wen (_ptw_io_requestor_11_customCSRs_csrs_0_wen), .io_requestor_11_customCSRs_csrs_0_wdata (_ptw_io_requestor_11_customCSRs_csrs_0_wdata), .io_requestor_11_customCSRs_csrs_0_value (_ptw_io_requestor_11_customCSRs_csrs_0_value), .io_requestor_11_customCSRs_csrs_1_ren (_ptw_io_requestor_11_customCSRs_csrs_1_ren), .io_requestor_11_customCSRs_csrs_1_wen (_ptw_io_requestor_11_customCSRs_csrs_1_wen), .io_requestor_11_customCSRs_csrs_1_wdata (_ptw_io_requestor_11_customCSRs_csrs_1_wdata), .io_requestor_11_customCSRs_csrs_1_value (_ptw_io_requestor_11_customCSRs_csrs_1_value), .io_requestor_11_customCSRs_csrs_2_ren (_ptw_io_requestor_11_customCSRs_csrs_2_ren), .io_requestor_11_customCSRs_csrs_2_wen (_ptw_io_requestor_11_customCSRs_csrs_2_wen), .io_requestor_11_customCSRs_csrs_2_wdata (_ptw_io_requestor_11_customCSRs_csrs_2_wdata), .io_requestor_11_customCSRs_csrs_2_value (_ptw_io_requestor_11_customCSRs_csrs_2_value), .io_requestor_11_customCSRs_csrs_3_ren (_ptw_io_requestor_11_customCSRs_csrs_3_ren), .io_requestor_11_customCSRs_csrs_3_wen (_ptw_io_requestor_11_customCSRs_csrs_3_wen), .io_requestor_11_customCSRs_csrs_3_wdata (_ptw_io_requestor_11_customCSRs_csrs_3_wdata), .io_requestor_11_customCSRs_csrs_3_value (_ptw_io_requestor_11_customCSRs_csrs_3_value), .io_requestor_12_req_ready (_ptw_io_requestor_12_req_ready), .io_requestor_12_req_valid (_zstd_compressor_io_ptw_12_req_valid), // @[Configs.scala:62:39] .io_requestor_12_req_bits_bits_addr (_zstd_compressor_io_ptw_12_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_12_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_12_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_12_resp_valid (_ptw_io_requestor_12_resp_valid), .io_requestor_12_resp_bits_ae_ptw (_ptw_io_requestor_12_resp_bits_ae_ptw), .io_requestor_12_resp_bits_ae_final (_ptw_io_requestor_12_resp_bits_ae_final), .io_requestor_12_resp_bits_pf (_ptw_io_requestor_12_resp_bits_pf), .io_requestor_12_resp_bits_gf (_ptw_io_requestor_12_resp_bits_gf), .io_requestor_12_resp_bits_hr (_ptw_io_requestor_12_resp_bits_hr), .io_requestor_12_resp_bits_hw (_ptw_io_requestor_12_resp_bits_hw), .io_requestor_12_resp_bits_hx (_ptw_io_requestor_12_resp_bits_hx), .io_requestor_12_resp_bits_pte_reserved_for_future (_ptw_io_requestor_12_resp_bits_pte_reserved_for_future), .io_requestor_12_resp_bits_pte_ppn (_ptw_io_requestor_12_resp_bits_pte_ppn), .io_requestor_12_resp_bits_pte_reserved_for_software (_ptw_io_requestor_12_resp_bits_pte_reserved_for_software), .io_requestor_12_resp_bits_pte_d (_ptw_io_requestor_12_resp_bits_pte_d), .io_requestor_12_resp_bits_pte_a (_ptw_io_requestor_12_resp_bits_pte_a), .io_requestor_12_resp_bits_pte_g (_ptw_io_requestor_12_resp_bits_pte_g), .io_requestor_12_resp_bits_pte_u (_ptw_io_requestor_12_resp_bits_pte_u), .io_requestor_12_resp_bits_pte_x (_ptw_io_requestor_12_resp_bits_pte_x), .io_requestor_12_resp_bits_pte_w (_ptw_io_requestor_12_resp_bits_pte_w), .io_requestor_12_resp_bits_pte_r (_ptw_io_requestor_12_resp_bits_pte_r), .io_requestor_12_resp_bits_pte_v (_ptw_io_requestor_12_resp_bits_pte_v), .io_requestor_12_resp_bits_level (_ptw_io_requestor_12_resp_bits_level), .io_requestor_12_resp_bits_homogeneous (_ptw_io_requestor_12_resp_bits_homogeneous), .io_requestor_12_resp_bits_gpa_valid (_ptw_io_requestor_12_resp_bits_gpa_valid), .io_requestor_12_resp_bits_gpa_bits (_ptw_io_requestor_12_resp_bits_gpa_bits), .io_requestor_12_resp_bits_gpa_is_pte (_ptw_io_requestor_12_resp_bits_gpa_is_pte), .io_requestor_12_ptbr_mode (_ptw_io_requestor_12_ptbr_mode), .io_requestor_12_ptbr_ppn (_ptw_io_requestor_12_ptbr_ppn), .io_requestor_12_status_debug (_ptw_io_requestor_12_status_debug), .io_requestor_12_status_cease (_ptw_io_requestor_12_status_cease), .io_requestor_12_status_wfi (_ptw_io_requestor_12_status_wfi), .io_requestor_12_status_isa (_ptw_io_requestor_12_status_isa), .io_requestor_12_status_dprv (_ptw_io_requestor_12_status_dprv), .io_requestor_12_status_dv (_ptw_io_requestor_12_status_dv), .io_requestor_12_status_prv (_ptw_io_requestor_12_status_prv), .io_requestor_12_status_v (_ptw_io_requestor_12_status_v), .io_requestor_12_status_mpv (_ptw_io_requestor_12_status_mpv), .io_requestor_12_status_gva (_ptw_io_requestor_12_status_gva), .io_requestor_12_status_tsr (_ptw_io_requestor_12_status_tsr), .io_requestor_12_status_tw (_ptw_io_requestor_12_status_tw), .io_requestor_12_status_tvm (_ptw_io_requestor_12_status_tvm), .io_requestor_12_status_mxr (_ptw_io_requestor_12_status_mxr), .io_requestor_12_status_sum (_ptw_io_requestor_12_status_sum), .io_requestor_12_status_mprv (_ptw_io_requestor_12_status_mprv), .io_requestor_12_status_fs (_ptw_io_requestor_12_status_fs), .io_requestor_12_status_mpp (_ptw_io_requestor_12_status_mpp), .io_requestor_12_status_spp (_ptw_io_requestor_12_status_spp), .io_requestor_12_status_mpie (_ptw_io_requestor_12_status_mpie), .io_requestor_12_status_spie (_ptw_io_requestor_12_status_spie), .io_requestor_12_status_mie (_ptw_io_requestor_12_status_mie), .io_requestor_12_status_sie (_ptw_io_requestor_12_status_sie), .io_requestor_12_hstatus_spvp (_ptw_io_requestor_12_hstatus_spvp), .io_requestor_12_hstatus_spv (_ptw_io_requestor_12_hstatus_spv), .io_requestor_12_hstatus_gva (_ptw_io_requestor_12_hstatus_gva), .io_requestor_12_gstatus_debug (_ptw_io_requestor_12_gstatus_debug), .io_requestor_12_gstatus_cease (_ptw_io_requestor_12_gstatus_cease), .io_requestor_12_gstatus_wfi (_ptw_io_requestor_12_gstatus_wfi), .io_requestor_12_gstatus_isa (_ptw_io_requestor_12_gstatus_isa), .io_requestor_12_gstatus_dprv (_ptw_io_requestor_12_gstatus_dprv), .io_requestor_12_gstatus_dv (_ptw_io_requestor_12_gstatus_dv), .io_requestor_12_gstatus_prv (_ptw_io_requestor_12_gstatus_prv), .io_requestor_12_gstatus_v (_ptw_io_requestor_12_gstatus_v), .io_requestor_12_gstatus_zero2 (_ptw_io_requestor_12_gstatus_zero2), .io_requestor_12_gstatus_mpv (_ptw_io_requestor_12_gstatus_mpv), .io_requestor_12_gstatus_gva (_ptw_io_requestor_12_gstatus_gva), .io_requestor_12_gstatus_mbe (_ptw_io_requestor_12_gstatus_mbe), .io_requestor_12_gstatus_sbe (_ptw_io_requestor_12_gstatus_sbe), .io_requestor_12_gstatus_sxl (_ptw_io_requestor_12_gstatus_sxl), .io_requestor_12_gstatus_zero1 (_ptw_io_requestor_12_gstatus_zero1), .io_requestor_12_gstatus_tsr (_ptw_io_requestor_12_gstatus_tsr), .io_requestor_12_gstatus_tw (_ptw_io_requestor_12_gstatus_tw), .io_requestor_12_gstatus_tvm (_ptw_io_requestor_12_gstatus_tvm), .io_requestor_12_gstatus_mxr (_ptw_io_requestor_12_gstatus_mxr), .io_requestor_12_gstatus_sum (_ptw_io_requestor_12_gstatus_sum), .io_requestor_12_gstatus_mprv (_ptw_io_requestor_12_gstatus_mprv), .io_requestor_12_gstatus_fs (_ptw_io_requestor_12_gstatus_fs), .io_requestor_12_gstatus_mpp (_ptw_io_requestor_12_gstatus_mpp), .io_requestor_12_gstatus_vs (_ptw_io_requestor_12_gstatus_vs), .io_requestor_12_gstatus_spp (_ptw_io_requestor_12_gstatus_spp), .io_requestor_12_gstatus_mpie (_ptw_io_requestor_12_gstatus_mpie), .io_requestor_12_gstatus_ube (_ptw_io_requestor_12_gstatus_ube), .io_requestor_12_gstatus_spie (_ptw_io_requestor_12_gstatus_spie), .io_requestor_12_gstatus_upie (_ptw_io_requestor_12_gstatus_upie), .io_requestor_12_gstatus_mie (_ptw_io_requestor_12_gstatus_mie), .io_requestor_12_gstatus_hie (_ptw_io_requestor_12_gstatus_hie), .io_requestor_12_gstatus_sie (_ptw_io_requestor_12_gstatus_sie), .io_requestor_12_gstatus_uie (_ptw_io_requestor_12_gstatus_uie), .io_requestor_12_pmp_0_cfg_l (_ptw_io_requestor_12_pmp_0_cfg_l), .io_requestor_12_pmp_0_cfg_a (_ptw_io_requestor_12_pmp_0_cfg_a), .io_requestor_12_pmp_0_cfg_x (_ptw_io_requestor_12_pmp_0_cfg_x), .io_requestor_12_pmp_0_cfg_w (_ptw_io_requestor_12_pmp_0_cfg_w), .io_requestor_12_pmp_0_cfg_r (_ptw_io_requestor_12_pmp_0_cfg_r), .io_requestor_12_pmp_0_addr (_ptw_io_requestor_12_pmp_0_addr), .io_requestor_12_pmp_0_mask (_ptw_io_requestor_12_pmp_0_mask), .io_requestor_12_pmp_1_cfg_l (_ptw_io_requestor_12_pmp_1_cfg_l), .io_requestor_12_pmp_1_cfg_a (_ptw_io_requestor_12_pmp_1_cfg_a), .io_requestor_12_pmp_1_cfg_x (_ptw_io_requestor_12_pmp_1_cfg_x), .io_requestor_12_pmp_1_cfg_w (_ptw_io_requestor_12_pmp_1_cfg_w), .io_requestor_12_pmp_1_cfg_r (_ptw_io_requestor_12_pmp_1_cfg_r), .io_requestor_12_pmp_1_addr (_ptw_io_requestor_12_pmp_1_addr), .io_requestor_12_pmp_1_mask (_ptw_io_requestor_12_pmp_1_mask), .io_requestor_12_pmp_2_cfg_l (_ptw_io_requestor_12_pmp_2_cfg_l), .io_requestor_12_pmp_2_cfg_a (_ptw_io_requestor_12_pmp_2_cfg_a), .io_requestor_12_pmp_2_cfg_x (_ptw_io_requestor_12_pmp_2_cfg_x), .io_requestor_12_pmp_2_cfg_w (_ptw_io_requestor_12_pmp_2_cfg_w), .io_requestor_12_pmp_2_cfg_r (_ptw_io_requestor_12_pmp_2_cfg_r), .io_requestor_12_pmp_2_addr (_ptw_io_requestor_12_pmp_2_addr), .io_requestor_12_pmp_2_mask (_ptw_io_requestor_12_pmp_2_mask), .io_requestor_12_pmp_3_cfg_l (_ptw_io_requestor_12_pmp_3_cfg_l), .io_requestor_12_pmp_3_cfg_a (_ptw_io_requestor_12_pmp_3_cfg_a), .io_requestor_12_pmp_3_cfg_x (_ptw_io_requestor_12_pmp_3_cfg_x), .io_requestor_12_pmp_3_cfg_w (_ptw_io_requestor_12_pmp_3_cfg_w), .io_requestor_12_pmp_3_cfg_r (_ptw_io_requestor_12_pmp_3_cfg_r), .io_requestor_12_pmp_3_addr (_ptw_io_requestor_12_pmp_3_addr), .io_requestor_12_pmp_3_mask (_ptw_io_requestor_12_pmp_3_mask), .io_requestor_12_pmp_4_cfg_l (_ptw_io_requestor_12_pmp_4_cfg_l), .io_requestor_12_pmp_4_cfg_a (_ptw_io_requestor_12_pmp_4_cfg_a), .io_requestor_12_pmp_4_cfg_x (_ptw_io_requestor_12_pmp_4_cfg_x), .io_requestor_12_pmp_4_cfg_w (_ptw_io_requestor_12_pmp_4_cfg_w), .io_requestor_12_pmp_4_cfg_r (_ptw_io_requestor_12_pmp_4_cfg_r), .io_requestor_12_pmp_4_addr (_ptw_io_requestor_12_pmp_4_addr), .io_requestor_12_pmp_4_mask (_ptw_io_requestor_12_pmp_4_mask), .io_requestor_12_pmp_5_cfg_l (_ptw_io_requestor_12_pmp_5_cfg_l), .io_requestor_12_pmp_5_cfg_a (_ptw_io_requestor_12_pmp_5_cfg_a), .io_requestor_12_pmp_5_cfg_x (_ptw_io_requestor_12_pmp_5_cfg_x), .io_requestor_12_pmp_5_cfg_w (_ptw_io_requestor_12_pmp_5_cfg_w), .io_requestor_12_pmp_5_cfg_r (_ptw_io_requestor_12_pmp_5_cfg_r), .io_requestor_12_pmp_5_addr (_ptw_io_requestor_12_pmp_5_addr), .io_requestor_12_pmp_5_mask (_ptw_io_requestor_12_pmp_5_mask), .io_requestor_12_pmp_6_cfg_l (_ptw_io_requestor_12_pmp_6_cfg_l), .io_requestor_12_pmp_6_cfg_a (_ptw_io_requestor_12_pmp_6_cfg_a), .io_requestor_12_pmp_6_cfg_x (_ptw_io_requestor_12_pmp_6_cfg_x), .io_requestor_12_pmp_6_cfg_w (_ptw_io_requestor_12_pmp_6_cfg_w), .io_requestor_12_pmp_6_cfg_r (_ptw_io_requestor_12_pmp_6_cfg_r), .io_requestor_12_pmp_6_addr (_ptw_io_requestor_12_pmp_6_addr), .io_requestor_12_pmp_6_mask (_ptw_io_requestor_12_pmp_6_mask), .io_requestor_12_pmp_7_cfg_l (_ptw_io_requestor_12_pmp_7_cfg_l), .io_requestor_12_pmp_7_cfg_a (_ptw_io_requestor_12_pmp_7_cfg_a), .io_requestor_12_pmp_7_cfg_x (_ptw_io_requestor_12_pmp_7_cfg_x), .io_requestor_12_pmp_7_cfg_w (_ptw_io_requestor_12_pmp_7_cfg_w), .io_requestor_12_pmp_7_cfg_r (_ptw_io_requestor_12_pmp_7_cfg_r), .io_requestor_12_pmp_7_addr (_ptw_io_requestor_12_pmp_7_addr), .io_requestor_12_pmp_7_mask (_ptw_io_requestor_12_pmp_7_mask), .io_requestor_12_customCSRs_csrs_0_ren (_ptw_io_requestor_12_customCSRs_csrs_0_ren), .io_requestor_12_customCSRs_csrs_0_wen (_ptw_io_requestor_12_customCSRs_csrs_0_wen), .io_requestor_12_customCSRs_csrs_0_wdata (_ptw_io_requestor_12_customCSRs_csrs_0_wdata), .io_requestor_12_customCSRs_csrs_0_value (_ptw_io_requestor_12_customCSRs_csrs_0_value), .io_requestor_12_customCSRs_csrs_1_ren (_ptw_io_requestor_12_customCSRs_csrs_1_ren), .io_requestor_12_customCSRs_csrs_1_wen (_ptw_io_requestor_12_customCSRs_csrs_1_wen), .io_requestor_12_customCSRs_csrs_1_wdata (_ptw_io_requestor_12_customCSRs_csrs_1_wdata), .io_requestor_12_customCSRs_csrs_1_value (_ptw_io_requestor_12_customCSRs_csrs_1_value), .io_requestor_12_customCSRs_csrs_2_ren (_ptw_io_requestor_12_customCSRs_csrs_2_ren), .io_requestor_12_customCSRs_csrs_2_wen (_ptw_io_requestor_12_customCSRs_csrs_2_wen), .io_requestor_12_customCSRs_csrs_2_wdata (_ptw_io_requestor_12_customCSRs_csrs_2_wdata), .io_requestor_12_customCSRs_csrs_2_value (_ptw_io_requestor_12_customCSRs_csrs_2_value), .io_requestor_12_customCSRs_csrs_3_ren (_ptw_io_requestor_12_customCSRs_csrs_3_ren), .io_requestor_12_customCSRs_csrs_3_wen (_ptw_io_requestor_12_customCSRs_csrs_3_wen), .io_requestor_12_customCSRs_csrs_3_wdata (_ptw_io_requestor_12_customCSRs_csrs_3_wdata), .io_requestor_12_customCSRs_csrs_3_value (_ptw_io_requestor_12_customCSRs_csrs_3_value), .io_requestor_13_req_ready (_ptw_io_requestor_13_req_ready), .io_requestor_13_req_valid (_zstd_compressor_io_ptw_13_req_valid), // @[Configs.scala:62:39] .io_requestor_13_req_bits_bits_addr (_zstd_compressor_io_ptw_13_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_13_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_13_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_13_resp_valid (_ptw_io_requestor_13_resp_valid), .io_requestor_13_resp_bits_ae_ptw (_ptw_io_requestor_13_resp_bits_ae_ptw), .io_requestor_13_resp_bits_ae_final (_ptw_io_requestor_13_resp_bits_ae_final), .io_requestor_13_resp_bits_pf (_ptw_io_requestor_13_resp_bits_pf), .io_requestor_13_resp_bits_gf (_ptw_io_requestor_13_resp_bits_gf), .io_requestor_13_resp_bits_hr (_ptw_io_requestor_13_resp_bits_hr), .io_requestor_13_resp_bits_hw (_ptw_io_requestor_13_resp_bits_hw), .io_requestor_13_resp_bits_hx (_ptw_io_requestor_13_resp_bits_hx), .io_requestor_13_resp_bits_pte_reserved_for_future (_ptw_io_requestor_13_resp_bits_pte_reserved_for_future), .io_requestor_13_resp_bits_pte_ppn (_ptw_io_requestor_13_resp_bits_pte_ppn), .io_requestor_13_resp_bits_pte_reserved_for_software (_ptw_io_requestor_13_resp_bits_pte_reserved_for_software), .io_requestor_13_resp_bits_pte_d (_ptw_io_requestor_13_resp_bits_pte_d), .io_requestor_13_resp_bits_pte_a (_ptw_io_requestor_13_resp_bits_pte_a), .io_requestor_13_resp_bits_pte_g (_ptw_io_requestor_13_resp_bits_pte_g), .io_requestor_13_resp_bits_pte_u (_ptw_io_requestor_13_resp_bits_pte_u), .io_requestor_13_resp_bits_pte_x (_ptw_io_requestor_13_resp_bits_pte_x), .io_requestor_13_resp_bits_pte_w (_ptw_io_requestor_13_resp_bits_pte_w), .io_requestor_13_resp_bits_pte_r (_ptw_io_requestor_13_resp_bits_pte_r), .io_requestor_13_resp_bits_pte_v (_ptw_io_requestor_13_resp_bits_pte_v), .io_requestor_13_resp_bits_level (_ptw_io_requestor_13_resp_bits_level), .io_requestor_13_resp_bits_homogeneous (_ptw_io_requestor_13_resp_bits_homogeneous), .io_requestor_13_resp_bits_gpa_valid (_ptw_io_requestor_13_resp_bits_gpa_valid), .io_requestor_13_resp_bits_gpa_bits (_ptw_io_requestor_13_resp_bits_gpa_bits), .io_requestor_13_resp_bits_gpa_is_pte (_ptw_io_requestor_13_resp_bits_gpa_is_pte), .io_requestor_13_ptbr_mode (_ptw_io_requestor_13_ptbr_mode), .io_requestor_13_ptbr_ppn (_ptw_io_requestor_13_ptbr_ppn), .io_requestor_13_status_debug (_ptw_io_requestor_13_status_debug), .io_requestor_13_status_cease (_ptw_io_requestor_13_status_cease), .io_requestor_13_status_wfi (_ptw_io_requestor_13_status_wfi), .io_requestor_13_status_isa (_ptw_io_requestor_13_status_isa), .io_requestor_13_status_dprv (_ptw_io_requestor_13_status_dprv), .io_requestor_13_status_dv (_ptw_io_requestor_13_status_dv), .io_requestor_13_status_prv (_ptw_io_requestor_13_status_prv), .io_requestor_13_status_v (_ptw_io_requestor_13_status_v), .io_requestor_13_status_mpv (_ptw_io_requestor_13_status_mpv), .io_requestor_13_status_gva (_ptw_io_requestor_13_status_gva), .io_requestor_13_status_tsr (_ptw_io_requestor_13_status_tsr), .io_requestor_13_status_tw (_ptw_io_requestor_13_status_tw), .io_requestor_13_status_tvm (_ptw_io_requestor_13_status_tvm), .io_requestor_13_status_mxr (_ptw_io_requestor_13_status_mxr), .io_requestor_13_status_sum (_ptw_io_requestor_13_status_sum), .io_requestor_13_status_mprv (_ptw_io_requestor_13_status_mprv), .io_requestor_13_status_fs (_ptw_io_requestor_13_status_fs), .io_requestor_13_status_mpp (_ptw_io_requestor_13_status_mpp), .io_requestor_13_status_spp (_ptw_io_requestor_13_status_spp), .io_requestor_13_status_mpie (_ptw_io_requestor_13_status_mpie), .io_requestor_13_status_spie (_ptw_io_requestor_13_status_spie), .io_requestor_13_status_mie (_ptw_io_requestor_13_status_mie), .io_requestor_13_status_sie (_ptw_io_requestor_13_status_sie), .io_requestor_13_hstatus_spvp (_ptw_io_requestor_13_hstatus_spvp), .io_requestor_13_hstatus_spv (_ptw_io_requestor_13_hstatus_spv), .io_requestor_13_hstatus_gva (_ptw_io_requestor_13_hstatus_gva), .io_requestor_13_gstatus_debug (_ptw_io_requestor_13_gstatus_debug), .io_requestor_13_gstatus_cease (_ptw_io_requestor_13_gstatus_cease), .io_requestor_13_gstatus_wfi (_ptw_io_requestor_13_gstatus_wfi), .io_requestor_13_gstatus_isa (_ptw_io_requestor_13_gstatus_isa), .io_requestor_13_gstatus_dprv (_ptw_io_requestor_13_gstatus_dprv), .io_requestor_13_gstatus_dv (_ptw_io_requestor_13_gstatus_dv), .io_requestor_13_gstatus_prv (_ptw_io_requestor_13_gstatus_prv), .io_requestor_13_gstatus_v (_ptw_io_requestor_13_gstatus_v), .io_requestor_13_gstatus_zero2 (_ptw_io_requestor_13_gstatus_zero2), .io_requestor_13_gstatus_mpv (_ptw_io_requestor_13_gstatus_mpv), .io_requestor_13_gstatus_gva (_ptw_io_requestor_13_gstatus_gva), .io_requestor_13_gstatus_mbe (_ptw_io_requestor_13_gstatus_mbe), .io_requestor_13_gstatus_sbe (_ptw_io_requestor_13_gstatus_sbe), .io_requestor_13_gstatus_sxl (_ptw_io_requestor_13_gstatus_sxl), .io_requestor_13_gstatus_zero1 (_ptw_io_requestor_13_gstatus_zero1), .io_requestor_13_gstatus_tsr (_ptw_io_requestor_13_gstatus_tsr), .io_requestor_13_gstatus_tw (_ptw_io_requestor_13_gstatus_tw), .io_requestor_13_gstatus_tvm (_ptw_io_requestor_13_gstatus_tvm), .io_requestor_13_gstatus_mxr (_ptw_io_requestor_13_gstatus_mxr), .io_requestor_13_gstatus_sum (_ptw_io_requestor_13_gstatus_sum), .io_requestor_13_gstatus_mprv (_ptw_io_requestor_13_gstatus_mprv), .io_requestor_13_gstatus_fs (_ptw_io_requestor_13_gstatus_fs), .io_requestor_13_gstatus_mpp (_ptw_io_requestor_13_gstatus_mpp), .io_requestor_13_gstatus_vs (_ptw_io_requestor_13_gstatus_vs), .io_requestor_13_gstatus_spp (_ptw_io_requestor_13_gstatus_spp), .io_requestor_13_gstatus_mpie (_ptw_io_requestor_13_gstatus_mpie), .io_requestor_13_gstatus_ube (_ptw_io_requestor_13_gstatus_ube), .io_requestor_13_gstatus_spie (_ptw_io_requestor_13_gstatus_spie), .io_requestor_13_gstatus_upie (_ptw_io_requestor_13_gstatus_upie), .io_requestor_13_gstatus_mie (_ptw_io_requestor_13_gstatus_mie), .io_requestor_13_gstatus_hie (_ptw_io_requestor_13_gstatus_hie), .io_requestor_13_gstatus_sie (_ptw_io_requestor_13_gstatus_sie), .io_requestor_13_gstatus_uie (_ptw_io_requestor_13_gstatus_uie), .io_requestor_13_pmp_0_cfg_l (_ptw_io_requestor_13_pmp_0_cfg_l), .io_requestor_13_pmp_0_cfg_a (_ptw_io_requestor_13_pmp_0_cfg_a), .io_requestor_13_pmp_0_cfg_x (_ptw_io_requestor_13_pmp_0_cfg_x), .io_requestor_13_pmp_0_cfg_w (_ptw_io_requestor_13_pmp_0_cfg_w), .io_requestor_13_pmp_0_cfg_r (_ptw_io_requestor_13_pmp_0_cfg_r), .io_requestor_13_pmp_0_addr (_ptw_io_requestor_13_pmp_0_addr), .io_requestor_13_pmp_0_mask (_ptw_io_requestor_13_pmp_0_mask), .io_requestor_13_pmp_1_cfg_l (_ptw_io_requestor_13_pmp_1_cfg_l), .io_requestor_13_pmp_1_cfg_a (_ptw_io_requestor_13_pmp_1_cfg_a), .io_requestor_13_pmp_1_cfg_x (_ptw_io_requestor_13_pmp_1_cfg_x), .io_requestor_13_pmp_1_cfg_w (_ptw_io_requestor_13_pmp_1_cfg_w), .io_requestor_13_pmp_1_cfg_r (_ptw_io_requestor_13_pmp_1_cfg_r), .io_requestor_13_pmp_1_addr (_ptw_io_requestor_13_pmp_1_addr), .io_requestor_13_pmp_1_mask (_ptw_io_requestor_13_pmp_1_mask), .io_requestor_13_pmp_2_cfg_l (_ptw_io_requestor_13_pmp_2_cfg_l), .io_requestor_13_pmp_2_cfg_a (_ptw_io_requestor_13_pmp_2_cfg_a), .io_requestor_13_pmp_2_cfg_x (_ptw_io_requestor_13_pmp_2_cfg_x), .io_requestor_13_pmp_2_cfg_w (_ptw_io_requestor_13_pmp_2_cfg_w), .io_requestor_13_pmp_2_cfg_r (_ptw_io_requestor_13_pmp_2_cfg_r), .io_requestor_13_pmp_2_addr (_ptw_io_requestor_13_pmp_2_addr), .io_requestor_13_pmp_2_mask (_ptw_io_requestor_13_pmp_2_mask), .io_requestor_13_pmp_3_cfg_l (_ptw_io_requestor_13_pmp_3_cfg_l), .io_requestor_13_pmp_3_cfg_a (_ptw_io_requestor_13_pmp_3_cfg_a), .io_requestor_13_pmp_3_cfg_x (_ptw_io_requestor_13_pmp_3_cfg_x), .io_requestor_13_pmp_3_cfg_w (_ptw_io_requestor_13_pmp_3_cfg_w), .io_requestor_13_pmp_3_cfg_r (_ptw_io_requestor_13_pmp_3_cfg_r), .io_requestor_13_pmp_3_addr (_ptw_io_requestor_13_pmp_3_addr), .io_requestor_13_pmp_3_mask (_ptw_io_requestor_13_pmp_3_mask), .io_requestor_13_pmp_4_cfg_l (_ptw_io_requestor_13_pmp_4_cfg_l), .io_requestor_13_pmp_4_cfg_a (_ptw_io_requestor_13_pmp_4_cfg_a), .io_requestor_13_pmp_4_cfg_x (_ptw_io_requestor_13_pmp_4_cfg_x), .io_requestor_13_pmp_4_cfg_w (_ptw_io_requestor_13_pmp_4_cfg_w), .io_requestor_13_pmp_4_cfg_r (_ptw_io_requestor_13_pmp_4_cfg_r), .io_requestor_13_pmp_4_addr (_ptw_io_requestor_13_pmp_4_addr), .io_requestor_13_pmp_4_mask (_ptw_io_requestor_13_pmp_4_mask), .io_requestor_13_pmp_5_cfg_l (_ptw_io_requestor_13_pmp_5_cfg_l), .io_requestor_13_pmp_5_cfg_a (_ptw_io_requestor_13_pmp_5_cfg_a), .io_requestor_13_pmp_5_cfg_x (_ptw_io_requestor_13_pmp_5_cfg_x), .io_requestor_13_pmp_5_cfg_w (_ptw_io_requestor_13_pmp_5_cfg_w), .io_requestor_13_pmp_5_cfg_r (_ptw_io_requestor_13_pmp_5_cfg_r), .io_requestor_13_pmp_5_addr (_ptw_io_requestor_13_pmp_5_addr), .io_requestor_13_pmp_5_mask (_ptw_io_requestor_13_pmp_5_mask), .io_requestor_13_pmp_6_cfg_l (_ptw_io_requestor_13_pmp_6_cfg_l), .io_requestor_13_pmp_6_cfg_a (_ptw_io_requestor_13_pmp_6_cfg_a), .io_requestor_13_pmp_6_cfg_x (_ptw_io_requestor_13_pmp_6_cfg_x), .io_requestor_13_pmp_6_cfg_w (_ptw_io_requestor_13_pmp_6_cfg_w), .io_requestor_13_pmp_6_cfg_r (_ptw_io_requestor_13_pmp_6_cfg_r), .io_requestor_13_pmp_6_addr (_ptw_io_requestor_13_pmp_6_addr), .io_requestor_13_pmp_6_mask (_ptw_io_requestor_13_pmp_6_mask), .io_requestor_13_pmp_7_cfg_l (_ptw_io_requestor_13_pmp_7_cfg_l), .io_requestor_13_pmp_7_cfg_a (_ptw_io_requestor_13_pmp_7_cfg_a), .io_requestor_13_pmp_7_cfg_x (_ptw_io_requestor_13_pmp_7_cfg_x), .io_requestor_13_pmp_7_cfg_w (_ptw_io_requestor_13_pmp_7_cfg_w), .io_requestor_13_pmp_7_cfg_r (_ptw_io_requestor_13_pmp_7_cfg_r), .io_requestor_13_pmp_7_addr (_ptw_io_requestor_13_pmp_7_addr), .io_requestor_13_pmp_7_mask (_ptw_io_requestor_13_pmp_7_mask), .io_requestor_13_customCSRs_csrs_0_ren (_ptw_io_requestor_13_customCSRs_csrs_0_ren), .io_requestor_13_customCSRs_csrs_0_wen (_ptw_io_requestor_13_customCSRs_csrs_0_wen), .io_requestor_13_customCSRs_csrs_0_wdata (_ptw_io_requestor_13_customCSRs_csrs_0_wdata), .io_requestor_13_customCSRs_csrs_0_value (_ptw_io_requestor_13_customCSRs_csrs_0_value), .io_requestor_13_customCSRs_csrs_1_ren (_ptw_io_requestor_13_customCSRs_csrs_1_ren), .io_requestor_13_customCSRs_csrs_1_wen (_ptw_io_requestor_13_customCSRs_csrs_1_wen), .io_requestor_13_customCSRs_csrs_1_wdata (_ptw_io_requestor_13_customCSRs_csrs_1_wdata), .io_requestor_13_customCSRs_csrs_1_value (_ptw_io_requestor_13_customCSRs_csrs_1_value), .io_requestor_13_customCSRs_csrs_2_ren (_ptw_io_requestor_13_customCSRs_csrs_2_ren), .io_requestor_13_customCSRs_csrs_2_wen (_ptw_io_requestor_13_customCSRs_csrs_2_wen), .io_requestor_13_customCSRs_csrs_2_wdata (_ptw_io_requestor_13_customCSRs_csrs_2_wdata), .io_requestor_13_customCSRs_csrs_2_value (_ptw_io_requestor_13_customCSRs_csrs_2_value), .io_requestor_13_customCSRs_csrs_3_ren (_ptw_io_requestor_13_customCSRs_csrs_3_ren), .io_requestor_13_customCSRs_csrs_3_wen (_ptw_io_requestor_13_customCSRs_csrs_3_wen), .io_requestor_13_customCSRs_csrs_3_wdata (_ptw_io_requestor_13_customCSRs_csrs_3_wdata), .io_requestor_13_customCSRs_csrs_3_value (_ptw_io_requestor_13_customCSRs_csrs_3_value), .io_requestor_14_req_ready (_ptw_io_requestor_14_req_ready), .io_requestor_14_req_valid (_zstd_compressor_io_ptw_14_req_valid), // @[Configs.scala:62:39] .io_requestor_14_req_bits_bits_addr (_zstd_compressor_io_ptw_14_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_14_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_14_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_14_resp_valid (_ptw_io_requestor_14_resp_valid), .io_requestor_14_resp_bits_ae_ptw (_ptw_io_requestor_14_resp_bits_ae_ptw), .io_requestor_14_resp_bits_ae_final (_ptw_io_requestor_14_resp_bits_ae_final), .io_requestor_14_resp_bits_pf (_ptw_io_requestor_14_resp_bits_pf), .io_requestor_14_resp_bits_gf (_ptw_io_requestor_14_resp_bits_gf), .io_requestor_14_resp_bits_hr (_ptw_io_requestor_14_resp_bits_hr), .io_requestor_14_resp_bits_hw (_ptw_io_requestor_14_resp_bits_hw), .io_requestor_14_resp_bits_hx (_ptw_io_requestor_14_resp_bits_hx), .io_requestor_14_resp_bits_pte_reserved_for_future (_ptw_io_requestor_14_resp_bits_pte_reserved_for_future), .io_requestor_14_resp_bits_pte_ppn (_ptw_io_requestor_14_resp_bits_pte_ppn), .io_requestor_14_resp_bits_pte_reserved_for_software (_ptw_io_requestor_14_resp_bits_pte_reserved_for_software), .io_requestor_14_resp_bits_pte_d (_ptw_io_requestor_14_resp_bits_pte_d), .io_requestor_14_resp_bits_pte_a (_ptw_io_requestor_14_resp_bits_pte_a), .io_requestor_14_resp_bits_pte_g (_ptw_io_requestor_14_resp_bits_pte_g), .io_requestor_14_resp_bits_pte_u (_ptw_io_requestor_14_resp_bits_pte_u), .io_requestor_14_resp_bits_pte_x (_ptw_io_requestor_14_resp_bits_pte_x), .io_requestor_14_resp_bits_pte_w (_ptw_io_requestor_14_resp_bits_pte_w), .io_requestor_14_resp_bits_pte_r (_ptw_io_requestor_14_resp_bits_pte_r), .io_requestor_14_resp_bits_pte_v (_ptw_io_requestor_14_resp_bits_pte_v), .io_requestor_14_resp_bits_level (_ptw_io_requestor_14_resp_bits_level), .io_requestor_14_resp_bits_homogeneous (_ptw_io_requestor_14_resp_bits_homogeneous), .io_requestor_14_resp_bits_gpa_valid (_ptw_io_requestor_14_resp_bits_gpa_valid), .io_requestor_14_resp_bits_gpa_bits (_ptw_io_requestor_14_resp_bits_gpa_bits), .io_requestor_14_resp_bits_gpa_is_pte (_ptw_io_requestor_14_resp_bits_gpa_is_pte), .io_requestor_14_ptbr_mode (_ptw_io_requestor_14_ptbr_mode), .io_requestor_14_ptbr_ppn (_ptw_io_requestor_14_ptbr_ppn), .io_requestor_14_status_debug (_ptw_io_requestor_14_status_debug), .io_requestor_14_status_cease (_ptw_io_requestor_14_status_cease), .io_requestor_14_status_wfi (_ptw_io_requestor_14_status_wfi), .io_requestor_14_status_isa (_ptw_io_requestor_14_status_isa), .io_requestor_14_status_dprv (_ptw_io_requestor_14_status_dprv), .io_requestor_14_status_dv (_ptw_io_requestor_14_status_dv), .io_requestor_14_status_prv (_ptw_io_requestor_14_status_prv), .io_requestor_14_status_v (_ptw_io_requestor_14_status_v), .io_requestor_14_status_mpv (_ptw_io_requestor_14_status_mpv), .io_requestor_14_status_gva (_ptw_io_requestor_14_status_gva), .io_requestor_14_status_tsr (_ptw_io_requestor_14_status_tsr), .io_requestor_14_status_tw (_ptw_io_requestor_14_status_tw), .io_requestor_14_status_tvm (_ptw_io_requestor_14_status_tvm), .io_requestor_14_status_mxr (_ptw_io_requestor_14_status_mxr), .io_requestor_14_status_sum (_ptw_io_requestor_14_status_sum), .io_requestor_14_status_mprv (_ptw_io_requestor_14_status_mprv), .io_requestor_14_status_fs (_ptw_io_requestor_14_status_fs), .io_requestor_14_status_mpp (_ptw_io_requestor_14_status_mpp), .io_requestor_14_status_spp (_ptw_io_requestor_14_status_spp), .io_requestor_14_status_mpie (_ptw_io_requestor_14_status_mpie), .io_requestor_14_status_spie (_ptw_io_requestor_14_status_spie), .io_requestor_14_status_mie (_ptw_io_requestor_14_status_mie), .io_requestor_14_status_sie (_ptw_io_requestor_14_status_sie), .io_requestor_14_hstatus_spvp (_ptw_io_requestor_14_hstatus_spvp), .io_requestor_14_hstatus_spv (_ptw_io_requestor_14_hstatus_spv), .io_requestor_14_hstatus_gva (_ptw_io_requestor_14_hstatus_gva), .io_requestor_14_gstatus_debug (_ptw_io_requestor_14_gstatus_debug), .io_requestor_14_gstatus_cease (_ptw_io_requestor_14_gstatus_cease), .io_requestor_14_gstatus_wfi (_ptw_io_requestor_14_gstatus_wfi), .io_requestor_14_gstatus_isa (_ptw_io_requestor_14_gstatus_isa), .io_requestor_14_gstatus_dprv (_ptw_io_requestor_14_gstatus_dprv), .io_requestor_14_gstatus_dv (_ptw_io_requestor_14_gstatus_dv), .io_requestor_14_gstatus_prv (_ptw_io_requestor_14_gstatus_prv), .io_requestor_14_gstatus_v (_ptw_io_requestor_14_gstatus_v), .io_requestor_14_gstatus_zero2 (_ptw_io_requestor_14_gstatus_zero2), .io_requestor_14_gstatus_mpv (_ptw_io_requestor_14_gstatus_mpv), .io_requestor_14_gstatus_gva (_ptw_io_requestor_14_gstatus_gva), .io_requestor_14_gstatus_mbe (_ptw_io_requestor_14_gstatus_mbe), .io_requestor_14_gstatus_sbe (_ptw_io_requestor_14_gstatus_sbe), .io_requestor_14_gstatus_sxl (_ptw_io_requestor_14_gstatus_sxl), .io_requestor_14_gstatus_zero1 (_ptw_io_requestor_14_gstatus_zero1), .io_requestor_14_gstatus_tsr (_ptw_io_requestor_14_gstatus_tsr), .io_requestor_14_gstatus_tw (_ptw_io_requestor_14_gstatus_tw), .io_requestor_14_gstatus_tvm (_ptw_io_requestor_14_gstatus_tvm), .io_requestor_14_gstatus_mxr (_ptw_io_requestor_14_gstatus_mxr), .io_requestor_14_gstatus_sum (_ptw_io_requestor_14_gstatus_sum), .io_requestor_14_gstatus_mprv (_ptw_io_requestor_14_gstatus_mprv), .io_requestor_14_gstatus_fs (_ptw_io_requestor_14_gstatus_fs), .io_requestor_14_gstatus_mpp (_ptw_io_requestor_14_gstatus_mpp), .io_requestor_14_gstatus_vs (_ptw_io_requestor_14_gstatus_vs), .io_requestor_14_gstatus_spp (_ptw_io_requestor_14_gstatus_spp), .io_requestor_14_gstatus_mpie (_ptw_io_requestor_14_gstatus_mpie), .io_requestor_14_gstatus_ube (_ptw_io_requestor_14_gstatus_ube), .io_requestor_14_gstatus_spie (_ptw_io_requestor_14_gstatus_spie), .io_requestor_14_gstatus_upie (_ptw_io_requestor_14_gstatus_upie), .io_requestor_14_gstatus_mie (_ptw_io_requestor_14_gstatus_mie), .io_requestor_14_gstatus_hie (_ptw_io_requestor_14_gstatus_hie), .io_requestor_14_gstatus_sie (_ptw_io_requestor_14_gstatus_sie), .io_requestor_14_gstatus_uie (_ptw_io_requestor_14_gstatus_uie), .io_requestor_14_pmp_0_cfg_l (_ptw_io_requestor_14_pmp_0_cfg_l), .io_requestor_14_pmp_0_cfg_a (_ptw_io_requestor_14_pmp_0_cfg_a), .io_requestor_14_pmp_0_cfg_x (_ptw_io_requestor_14_pmp_0_cfg_x), .io_requestor_14_pmp_0_cfg_w (_ptw_io_requestor_14_pmp_0_cfg_w), .io_requestor_14_pmp_0_cfg_r (_ptw_io_requestor_14_pmp_0_cfg_r), .io_requestor_14_pmp_0_addr (_ptw_io_requestor_14_pmp_0_addr), .io_requestor_14_pmp_0_mask (_ptw_io_requestor_14_pmp_0_mask), .io_requestor_14_pmp_1_cfg_l (_ptw_io_requestor_14_pmp_1_cfg_l), .io_requestor_14_pmp_1_cfg_a (_ptw_io_requestor_14_pmp_1_cfg_a), .io_requestor_14_pmp_1_cfg_x (_ptw_io_requestor_14_pmp_1_cfg_x), .io_requestor_14_pmp_1_cfg_w (_ptw_io_requestor_14_pmp_1_cfg_w), .io_requestor_14_pmp_1_cfg_r (_ptw_io_requestor_14_pmp_1_cfg_r), .io_requestor_14_pmp_1_addr (_ptw_io_requestor_14_pmp_1_addr), .io_requestor_14_pmp_1_mask (_ptw_io_requestor_14_pmp_1_mask), .io_requestor_14_pmp_2_cfg_l (_ptw_io_requestor_14_pmp_2_cfg_l), .io_requestor_14_pmp_2_cfg_a (_ptw_io_requestor_14_pmp_2_cfg_a), .io_requestor_14_pmp_2_cfg_x (_ptw_io_requestor_14_pmp_2_cfg_x), .io_requestor_14_pmp_2_cfg_w (_ptw_io_requestor_14_pmp_2_cfg_w), .io_requestor_14_pmp_2_cfg_r (_ptw_io_requestor_14_pmp_2_cfg_r), .io_requestor_14_pmp_2_addr (_ptw_io_requestor_14_pmp_2_addr), .io_requestor_14_pmp_2_mask (_ptw_io_requestor_14_pmp_2_mask), .io_requestor_14_pmp_3_cfg_l (_ptw_io_requestor_14_pmp_3_cfg_l), .io_requestor_14_pmp_3_cfg_a (_ptw_io_requestor_14_pmp_3_cfg_a), .io_requestor_14_pmp_3_cfg_x (_ptw_io_requestor_14_pmp_3_cfg_x), .io_requestor_14_pmp_3_cfg_w (_ptw_io_requestor_14_pmp_3_cfg_w), .io_requestor_14_pmp_3_cfg_r (_ptw_io_requestor_14_pmp_3_cfg_r), .io_requestor_14_pmp_3_addr (_ptw_io_requestor_14_pmp_3_addr), .io_requestor_14_pmp_3_mask (_ptw_io_requestor_14_pmp_3_mask), .io_requestor_14_pmp_4_cfg_l (_ptw_io_requestor_14_pmp_4_cfg_l), .io_requestor_14_pmp_4_cfg_a (_ptw_io_requestor_14_pmp_4_cfg_a), .io_requestor_14_pmp_4_cfg_x (_ptw_io_requestor_14_pmp_4_cfg_x), .io_requestor_14_pmp_4_cfg_w (_ptw_io_requestor_14_pmp_4_cfg_w), .io_requestor_14_pmp_4_cfg_r (_ptw_io_requestor_14_pmp_4_cfg_r), .io_requestor_14_pmp_4_addr (_ptw_io_requestor_14_pmp_4_addr), .io_requestor_14_pmp_4_mask (_ptw_io_requestor_14_pmp_4_mask), .io_requestor_14_pmp_5_cfg_l (_ptw_io_requestor_14_pmp_5_cfg_l), .io_requestor_14_pmp_5_cfg_a (_ptw_io_requestor_14_pmp_5_cfg_a), .io_requestor_14_pmp_5_cfg_x (_ptw_io_requestor_14_pmp_5_cfg_x), .io_requestor_14_pmp_5_cfg_w (_ptw_io_requestor_14_pmp_5_cfg_w), .io_requestor_14_pmp_5_cfg_r (_ptw_io_requestor_14_pmp_5_cfg_r), .io_requestor_14_pmp_5_addr (_ptw_io_requestor_14_pmp_5_addr), .io_requestor_14_pmp_5_mask (_ptw_io_requestor_14_pmp_5_mask), .io_requestor_14_pmp_6_cfg_l (_ptw_io_requestor_14_pmp_6_cfg_l), .io_requestor_14_pmp_6_cfg_a (_ptw_io_requestor_14_pmp_6_cfg_a), .io_requestor_14_pmp_6_cfg_x (_ptw_io_requestor_14_pmp_6_cfg_x), .io_requestor_14_pmp_6_cfg_w (_ptw_io_requestor_14_pmp_6_cfg_w), .io_requestor_14_pmp_6_cfg_r (_ptw_io_requestor_14_pmp_6_cfg_r), .io_requestor_14_pmp_6_addr (_ptw_io_requestor_14_pmp_6_addr), .io_requestor_14_pmp_6_mask (_ptw_io_requestor_14_pmp_6_mask), .io_requestor_14_pmp_7_cfg_l (_ptw_io_requestor_14_pmp_7_cfg_l), .io_requestor_14_pmp_7_cfg_a (_ptw_io_requestor_14_pmp_7_cfg_a), .io_requestor_14_pmp_7_cfg_x (_ptw_io_requestor_14_pmp_7_cfg_x), .io_requestor_14_pmp_7_cfg_w (_ptw_io_requestor_14_pmp_7_cfg_w), .io_requestor_14_pmp_7_cfg_r (_ptw_io_requestor_14_pmp_7_cfg_r), .io_requestor_14_pmp_7_addr (_ptw_io_requestor_14_pmp_7_addr), .io_requestor_14_pmp_7_mask (_ptw_io_requestor_14_pmp_7_mask), .io_requestor_14_customCSRs_csrs_0_ren (_ptw_io_requestor_14_customCSRs_csrs_0_ren), .io_requestor_14_customCSRs_csrs_0_wen (_ptw_io_requestor_14_customCSRs_csrs_0_wen), .io_requestor_14_customCSRs_csrs_0_wdata (_ptw_io_requestor_14_customCSRs_csrs_0_wdata), .io_requestor_14_customCSRs_csrs_0_value (_ptw_io_requestor_14_customCSRs_csrs_0_value), .io_requestor_14_customCSRs_csrs_1_ren (_ptw_io_requestor_14_customCSRs_csrs_1_ren), .io_requestor_14_customCSRs_csrs_1_wen (_ptw_io_requestor_14_customCSRs_csrs_1_wen), .io_requestor_14_customCSRs_csrs_1_wdata (_ptw_io_requestor_14_customCSRs_csrs_1_wdata), .io_requestor_14_customCSRs_csrs_1_value (_ptw_io_requestor_14_customCSRs_csrs_1_value), .io_requestor_14_customCSRs_csrs_2_ren (_ptw_io_requestor_14_customCSRs_csrs_2_ren), .io_requestor_14_customCSRs_csrs_2_wen (_ptw_io_requestor_14_customCSRs_csrs_2_wen), .io_requestor_14_customCSRs_csrs_2_wdata (_ptw_io_requestor_14_customCSRs_csrs_2_wdata), .io_requestor_14_customCSRs_csrs_2_value (_ptw_io_requestor_14_customCSRs_csrs_2_value), .io_requestor_14_customCSRs_csrs_3_ren (_ptw_io_requestor_14_customCSRs_csrs_3_ren), .io_requestor_14_customCSRs_csrs_3_wen (_ptw_io_requestor_14_customCSRs_csrs_3_wen), .io_requestor_14_customCSRs_csrs_3_wdata (_ptw_io_requestor_14_customCSRs_csrs_3_wdata), .io_requestor_14_customCSRs_csrs_3_value (_ptw_io_requestor_14_customCSRs_csrs_3_value), .io_requestor_15_req_ready (_ptw_io_requestor_15_req_ready), .io_requestor_15_req_valid (_zstd_compressor_io_ptw_15_req_valid), // @[Configs.scala:62:39] .io_requestor_15_req_bits_bits_addr (_zstd_compressor_io_ptw_15_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_15_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_15_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_15_resp_valid (_ptw_io_requestor_15_resp_valid), .io_requestor_15_resp_bits_ae_ptw (_ptw_io_requestor_15_resp_bits_ae_ptw), .io_requestor_15_resp_bits_ae_final (_ptw_io_requestor_15_resp_bits_ae_final), .io_requestor_15_resp_bits_pf (_ptw_io_requestor_15_resp_bits_pf), .io_requestor_15_resp_bits_gf (_ptw_io_requestor_15_resp_bits_gf), .io_requestor_15_resp_bits_hr (_ptw_io_requestor_15_resp_bits_hr), .io_requestor_15_resp_bits_hw (_ptw_io_requestor_15_resp_bits_hw), .io_requestor_15_resp_bits_hx (_ptw_io_requestor_15_resp_bits_hx), .io_requestor_15_resp_bits_pte_reserved_for_future (_ptw_io_requestor_15_resp_bits_pte_reserved_for_future), .io_requestor_15_resp_bits_pte_ppn (_ptw_io_requestor_15_resp_bits_pte_ppn), .io_requestor_15_resp_bits_pte_reserved_for_software (_ptw_io_requestor_15_resp_bits_pte_reserved_for_software), .io_requestor_15_resp_bits_pte_d (_ptw_io_requestor_15_resp_bits_pte_d), .io_requestor_15_resp_bits_pte_a (_ptw_io_requestor_15_resp_bits_pte_a), .io_requestor_15_resp_bits_pte_g (_ptw_io_requestor_15_resp_bits_pte_g), .io_requestor_15_resp_bits_pte_u (_ptw_io_requestor_15_resp_bits_pte_u), .io_requestor_15_resp_bits_pte_x (_ptw_io_requestor_15_resp_bits_pte_x), .io_requestor_15_resp_bits_pte_w (_ptw_io_requestor_15_resp_bits_pte_w), .io_requestor_15_resp_bits_pte_r (_ptw_io_requestor_15_resp_bits_pte_r), .io_requestor_15_resp_bits_pte_v (_ptw_io_requestor_15_resp_bits_pte_v), .io_requestor_15_resp_bits_level (_ptw_io_requestor_15_resp_bits_level), .io_requestor_15_resp_bits_homogeneous (_ptw_io_requestor_15_resp_bits_homogeneous), .io_requestor_15_resp_bits_gpa_valid (_ptw_io_requestor_15_resp_bits_gpa_valid), .io_requestor_15_resp_bits_gpa_bits (_ptw_io_requestor_15_resp_bits_gpa_bits), .io_requestor_15_resp_bits_gpa_is_pte (_ptw_io_requestor_15_resp_bits_gpa_is_pte), .io_requestor_15_ptbr_mode (_ptw_io_requestor_15_ptbr_mode), .io_requestor_15_ptbr_ppn (_ptw_io_requestor_15_ptbr_ppn), .io_requestor_15_status_debug (_ptw_io_requestor_15_status_debug), .io_requestor_15_status_cease (_ptw_io_requestor_15_status_cease), .io_requestor_15_status_wfi (_ptw_io_requestor_15_status_wfi), .io_requestor_15_status_isa (_ptw_io_requestor_15_status_isa), .io_requestor_15_status_dprv (_ptw_io_requestor_15_status_dprv), .io_requestor_15_status_dv (_ptw_io_requestor_15_status_dv), .io_requestor_15_status_prv (_ptw_io_requestor_15_status_prv), .io_requestor_15_status_v (_ptw_io_requestor_15_status_v), .io_requestor_15_status_mpv (_ptw_io_requestor_15_status_mpv), .io_requestor_15_status_gva (_ptw_io_requestor_15_status_gva), .io_requestor_15_status_tsr (_ptw_io_requestor_15_status_tsr), .io_requestor_15_status_tw (_ptw_io_requestor_15_status_tw), .io_requestor_15_status_tvm (_ptw_io_requestor_15_status_tvm), .io_requestor_15_status_mxr (_ptw_io_requestor_15_status_mxr), .io_requestor_15_status_sum (_ptw_io_requestor_15_status_sum), .io_requestor_15_status_mprv (_ptw_io_requestor_15_status_mprv), .io_requestor_15_status_fs (_ptw_io_requestor_15_status_fs), .io_requestor_15_status_mpp (_ptw_io_requestor_15_status_mpp), .io_requestor_15_status_spp (_ptw_io_requestor_15_status_spp), .io_requestor_15_status_mpie (_ptw_io_requestor_15_status_mpie), .io_requestor_15_status_spie (_ptw_io_requestor_15_status_spie), .io_requestor_15_status_mie (_ptw_io_requestor_15_status_mie), .io_requestor_15_status_sie (_ptw_io_requestor_15_status_sie), .io_requestor_15_hstatus_spvp (_ptw_io_requestor_15_hstatus_spvp), .io_requestor_15_hstatus_spv (_ptw_io_requestor_15_hstatus_spv), .io_requestor_15_hstatus_gva (_ptw_io_requestor_15_hstatus_gva), .io_requestor_15_gstatus_debug (_ptw_io_requestor_15_gstatus_debug), .io_requestor_15_gstatus_cease (_ptw_io_requestor_15_gstatus_cease), .io_requestor_15_gstatus_wfi (_ptw_io_requestor_15_gstatus_wfi), .io_requestor_15_gstatus_isa (_ptw_io_requestor_15_gstatus_isa), .io_requestor_15_gstatus_dprv (_ptw_io_requestor_15_gstatus_dprv), .io_requestor_15_gstatus_dv (_ptw_io_requestor_15_gstatus_dv), .io_requestor_15_gstatus_prv (_ptw_io_requestor_15_gstatus_prv), .io_requestor_15_gstatus_v (_ptw_io_requestor_15_gstatus_v), .io_requestor_15_gstatus_zero2 (_ptw_io_requestor_15_gstatus_zero2), .io_requestor_15_gstatus_mpv (_ptw_io_requestor_15_gstatus_mpv), .io_requestor_15_gstatus_gva (_ptw_io_requestor_15_gstatus_gva), .io_requestor_15_gstatus_mbe (_ptw_io_requestor_15_gstatus_mbe), .io_requestor_15_gstatus_sbe (_ptw_io_requestor_15_gstatus_sbe), .io_requestor_15_gstatus_sxl (_ptw_io_requestor_15_gstatus_sxl), .io_requestor_15_gstatus_zero1 (_ptw_io_requestor_15_gstatus_zero1), .io_requestor_15_gstatus_tsr (_ptw_io_requestor_15_gstatus_tsr), .io_requestor_15_gstatus_tw (_ptw_io_requestor_15_gstatus_tw), .io_requestor_15_gstatus_tvm (_ptw_io_requestor_15_gstatus_tvm), .io_requestor_15_gstatus_mxr (_ptw_io_requestor_15_gstatus_mxr), .io_requestor_15_gstatus_sum (_ptw_io_requestor_15_gstatus_sum), .io_requestor_15_gstatus_mprv (_ptw_io_requestor_15_gstatus_mprv), .io_requestor_15_gstatus_fs (_ptw_io_requestor_15_gstatus_fs), .io_requestor_15_gstatus_mpp (_ptw_io_requestor_15_gstatus_mpp), .io_requestor_15_gstatus_vs (_ptw_io_requestor_15_gstatus_vs), .io_requestor_15_gstatus_spp (_ptw_io_requestor_15_gstatus_spp), .io_requestor_15_gstatus_mpie (_ptw_io_requestor_15_gstatus_mpie), .io_requestor_15_gstatus_ube (_ptw_io_requestor_15_gstatus_ube), .io_requestor_15_gstatus_spie (_ptw_io_requestor_15_gstatus_spie), .io_requestor_15_gstatus_upie (_ptw_io_requestor_15_gstatus_upie), .io_requestor_15_gstatus_mie (_ptw_io_requestor_15_gstatus_mie), .io_requestor_15_gstatus_hie (_ptw_io_requestor_15_gstatus_hie), .io_requestor_15_gstatus_sie (_ptw_io_requestor_15_gstatus_sie), .io_requestor_15_gstatus_uie (_ptw_io_requestor_15_gstatus_uie), .io_requestor_15_pmp_0_cfg_l (_ptw_io_requestor_15_pmp_0_cfg_l), .io_requestor_15_pmp_0_cfg_a (_ptw_io_requestor_15_pmp_0_cfg_a), .io_requestor_15_pmp_0_cfg_x (_ptw_io_requestor_15_pmp_0_cfg_x), .io_requestor_15_pmp_0_cfg_w (_ptw_io_requestor_15_pmp_0_cfg_w), .io_requestor_15_pmp_0_cfg_r (_ptw_io_requestor_15_pmp_0_cfg_r), .io_requestor_15_pmp_0_addr (_ptw_io_requestor_15_pmp_0_addr), .io_requestor_15_pmp_0_mask (_ptw_io_requestor_15_pmp_0_mask), .io_requestor_15_pmp_1_cfg_l (_ptw_io_requestor_15_pmp_1_cfg_l), .io_requestor_15_pmp_1_cfg_a (_ptw_io_requestor_15_pmp_1_cfg_a), .io_requestor_15_pmp_1_cfg_x (_ptw_io_requestor_15_pmp_1_cfg_x), .io_requestor_15_pmp_1_cfg_w (_ptw_io_requestor_15_pmp_1_cfg_w), .io_requestor_15_pmp_1_cfg_r (_ptw_io_requestor_15_pmp_1_cfg_r), .io_requestor_15_pmp_1_addr (_ptw_io_requestor_15_pmp_1_addr), .io_requestor_15_pmp_1_mask (_ptw_io_requestor_15_pmp_1_mask), .io_requestor_15_pmp_2_cfg_l (_ptw_io_requestor_15_pmp_2_cfg_l), .io_requestor_15_pmp_2_cfg_a (_ptw_io_requestor_15_pmp_2_cfg_a), .io_requestor_15_pmp_2_cfg_x (_ptw_io_requestor_15_pmp_2_cfg_x), .io_requestor_15_pmp_2_cfg_w (_ptw_io_requestor_15_pmp_2_cfg_w), .io_requestor_15_pmp_2_cfg_r (_ptw_io_requestor_15_pmp_2_cfg_r), .io_requestor_15_pmp_2_addr (_ptw_io_requestor_15_pmp_2_addr), .io_requestor_15_pmp_2_mask (_ptw_io_requestor_15_pmp_2_mask), .io_requestor_15_pmp_3_cfg_l (_ptw_io_requestor_15_pmp_3_cfg_l), .io_requestor_15_pmp_3_cfg_a (_ptw_io_requestor_15_pmp_3_cfg_a), .io_requestor_15_pmp_3_cfg_x (_ptw_io_requestor_15_pmp_3_cfg_x), .io_requestor_15_pmp_3_cfg_w (_ptw_io_requestor_15_pmp_3_cfg_w), .io_requestor_15_pmp_3_cfg_r (_ptw_io_requestor_15_pmp_3_cfg_r), .io_requestor_15_pmp_3_addr (_ptw_io_requestor_15_pmp_3_addr), .io_requestor_15_pmp_3_mask (_ptw_io_requestor_15_pmp_3_mask), .io_requestor_15_pmp_4_cfg_l (_ptw_io_requestor_15_pmp_4_cfg_l), .io_requestor_15_pmp_4_cfg_a (_ptw_io_requestor_15_pmp_4_cfg_a), .io_requestor_15_pmp_4_cfg_x (_ptw_io_requestor_15_pmp_4_cfg_x), .io_requestor_15_pmp_4_cfg_w (_ptw_io_requestor_15_pmp_4_cfg_w), .io_requestor_15_pmp_4_cfg_r (_ptw_io_requestor_15_pmp_4_cfg_r), .io_requestor_15_pmp_4_addr (_ptw_io_requestor_15_pmp_4_addr), .io_requestor_15_pmp_4_mask (_ptw_io_requestor_15_pmp_4_mask), .io_requestor_15_pmp_5_cfg_l (_ptw_io_requestor_15_pmp_5_cfg_l), .io_requestor_15_pmp_5_cfg_a (_ptw_io_requestor_15_pmp_5_cfg_a), .io_requestor_15_pmp_5_cfg_x (_ptw_io_requestor_15_pmp_5_cfg_x), .io_requestor_15_pmp_5_cfg_w (_ptw_io_requestor_15_pmp_5_cfg_w), .io_requestor_15_pmp_5_cfg_r (_ptw_io_requestor_15_pmp_5_cfg_r), .io_requestor_15_pmp_5_addr (_ptw_io_requestor_15_pmp_5_addr), .io_requestor_15_pmp_5_mask (_ptw_io_requestor_15_pmp_5_mask), .io_requestor_15_pmp_6_cfg_l (_ptw_io_requestor_15_pmp_6_cfg_l), .io_requestor_15_pmp_6_cfg_a (_ptw_io_requestor_15_pmp_6_cfg_a), .io_requestor_15_pmp_6_cfg_x (_ptw_io_requestor_15_pmp_6_cfg_x), .io_requestor_15_pmp_6_cfg_w (_ptw_io_requestor_15_pmp_6_cfg_w), .io_requestor_15_pmp_6_cfg_r (_ptw_io_requestor_15_pmp_6_cfg_r), .io_requestor_15_pmp_6_addr (_ptw_io_requestor_15_pmp_6_addr), .io_requestor_15_pmp_6_mask (_ptw_io_requestor_15_pmp_6_mask), .io_requestor_15_pmp_7_cfg_l (_ptw_io_requestor_15_pmp_7_cfg_l), .io_requestor_15_pmp_7_cfg_a (_ptw_io_requestor_15_pmp_7_cfg_a), .io_requestor_15_pmp_7_cfg_x (_ptw_io_requestor_15_pmp_7_cfg_x), .io_requestor_15_pmp_7_cfg_w (_ptw_io_requestor_15_pmp_7_cfg_w), .io_requestor_15_pmp_7_cfg_r (_ptw_io_requestor_15_pmp_7_cfg_r), .io_requestor_15_pmp_7_addr (_ptw_io_requestor_15_pmp_7_addr), .io_requestor_15_pmp_7_mask (_ptw_io_requestor_15_pmp_7_mask), .io_requestor_15_customCSRs_csrs_0_ren (_ptw_io_requestor_15_customCSRs_csrs_0_ren), .io_requestor_15_customCSRs_csrs_0_wen (_ptw_io_requestor_15_customCSRs_csrs_0_wen), .io_requestor_15_customCSRs_csrs_0_wdata (_ptw_io_requestor_15_customCSRs_csrs_0_wdata), .io_requestor_15_customCSRs_csrs_0_value (_ptw_io_requestor_15_customCSRs_csrs_0_value), .io_requestor_15_customCSRs_csrs_1_ren (_ptw_io_requestor_15_customCSRs_csrs_1_ren), .io_requestor_15_customCSRs_csrs_1_wen (_ptw_io_requestor_15_customCSRs_csrs_1_wen), .io_requestor_15_customCSRs_csrs_1_wdata (_ptw_io_requestor_15_customCSRs_csrs_1_wdata), .io_requestor_15_customCSRs_csrs_1_value (_ptw_io_requestor_15_customCSRs_csrs_1_value), .io_requestor_15_customCSRs_csrs_2_ren (_ptw_io_requestor_15_customCSRs_csrs_2_ren), .io_requestor_15_customCSRs_csrs_2_wen (_ptw_io_requestor_15_customCSRs_csrs_2_wen), .io_requestor_15_customCSRs_csrs_2_wdata (_ptw_io_requestor_15_customCSRs_csrs_2_wdata), .io_requestor_15_customCSRs_csrs_2_value (_ptw_io_requestor_15_customCSRs_csrs_2_value), .io_requestor_15_customCSRs_csrs_3_ren (_ptw_io_requestor_15_customCSRs_csrs_3_ren), .io_requestor_15_customCSRs_csrs_3_wen (_ptw_io_requestor_15_customCSRs_csrs_3_wen), .io_requestor_15_customCSRs_csrs_3_wdata (_ptw_io_requestor_15_customCSRs_csrs_3_wdata), .io_requestor_15_customCSRs_csrs_3_value (_ptw_io_requestor_15_customCSRs_csrs_3_value), .io_requestor_16_req_ready (_ptw_io_requestor_16_req_ready), .io_requestor_16_req_valid (_zstd_compressor_io_ptw_16_req_valid), // @[Configs.scala:62:39] .io_requestor_16_req_bits_bits_addr (_zstd_compressor_io_ptw_16_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_16_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_16_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_16_resp_valid (_ptw_io_requestor_16_resp_valid), .io_requestor_16_resp_bits_ae_ptw (_ptw_io_requestor_16_resp_bits_ae_ptw), .io_requestor_16_resp_bits_ae_final (_ptw_io_requestor_16_resp_bits_ae_final), .io_requestor_16_resp_bits_pf (_ptw_io_requestor_16_resp_bits_pf), .io_requestor_16_resp_bits_gf (_ptw_io_requestor_16_resp_bits_gf), .io_requestor_16_resp_bits_hr (_ptw_io_requestor_16_resp_bits_hr), .io_requestor_16_resp_bits_hw (_ptw_io_requestor_16_resp_bits_hw), .io_requestor_16_resp_bits_hx (_ptw_io_requestor_16_resp_bits_hx), .io_requestor_16_resp_bits_pte_reserved_for_future (_ptw_io_requestor_16_resp_bits_pte_reserved_for_future), .io_requestor_16_resp_bits_pte_ppn (_ptw_io_requestor_16_resp_bits_pte_ppn), .io_requestor_16_resp_bits_pte_reserved_for_software (_ptw_io_requestor_16_resp_bits_pte_reserved_for_software), .io_requestor_16_resp_bits_pte_d (_ptw_io_requestor_16_resp_bits_pte_d), .io_requestor_16_resp_bits_pte_a (_ptw_io_requestor_16_resp_bits_pte_a), .io_requestor_16_resp_bits_pte_g (_ptw_io_requestor_16_resp_bits_pte_g), .io_requestor_16_resp_bits_pte_u (_ptw_io_requestor_16_resp_bits_pte_u), .io_requestor_16_resp_bits_pte_x (_ptw_io_requestor_16_resp_bits_pte_x), .io_requestor_16_resp_bits_pte_w (_ptw_io_requestor_16_resp_bits_pte_w), .io_requestor_16_resp_bits_pte_r (_ptw_io_requestor_16_resp_bits_pte_r), .io_requestor_16_resp_bits_pte_v (_ptw_io_requestor_16_resp_bits_pte_v), .io_requestor_16_resp_bits_level (_ptw_io_requestor_16_resp_bits_level), .io_requestor_16_resp_bits_homogeneous (_ptw_io_requestor_16_resp_bits_homogeneous), .io_requestor_16_resp_bits_gpa_valid (_ptw_io_requestor_16_resp_bits_gpa_valid), .io_requestor_16_resp_bits_gpa_bits (_ptw_io_requestor_16_resp_bits_gpa_bits), .io_requestor_16_resp_bits_gpa_is_pte (_ptw_io_requestor_16_resp_bits_gpa_is_pte), .io_requestor_16_ptbr_mode (_ptw_io_requestor_16_ptbr_mode), .io_requestor_16_ptbr_ppn (_ptw_io_requestor_16_ptbr_ppn), .io_requestor_16_status_debug (_ptw_io_requestor_16_status_debug), .io_requestor_16_status_cease (_ptw_io_requestor_16_status_cease), .io_requestor_16_status_wfi (_ptw_io_requestor_16_status_wfi), .io_requestor_16_status_isa (_ptw_io_requestor_16_status_isa), .io_requestor_16_status_dprv (_ptw_io_requestor_16_status_dprv), .io_requestor_16_status_dv (_ptw_io_requestor_16_status_dv), .io_requestor_16_status_prv (_ptw_io_requestor_16_status_prv), .io_requestor_16_status_v (_ptw_io_requestor_16_status_v), .io_requestor_16_status_mpv (_ptw_io_requestor_16_status_mpv), .io_requestor_16_status_gva (_ptw_io_requestor_16_status_gva), .io_requestor_16_status_tsr (_ptw_io_requestor_16_status_tsr), .io_requestor_16_status_tw (_ptw_io_requestor_16_status_tw), .io_requestor_16_status_tvm (_ptw_io_requestor_16_status_tvm), .io_requestor_16_status_mxr (_ptw_io_requestor_16_status_mxr), .io_requestor_16_status_sum (_ptw_io_requestor_16_status_sum), .io_requestor_16_status_mprv (_ptw_io_requestor_16_status_mprv), .io_requestor_16_status_fs (_ptw_io_requestor_16_status_fs), .io_requestor_16_status_mpp (_ptw_io_requestor_16_status_mpp), .io_requestor_16_status_spp (_ptw_io_requestor_16_status_spp), .io_requestor_16_status_mpie (_ptw_io_requestor_16_status_mpie), .io_requestor_16_status_spie (_ptw_io_requestor_16_status_spie), .io_requestor_16_status_mie (_ptw_io_requestor_16_status_mie), .io_requestor_16_status_sie (_ptw_io_requestor_16_status_sie), .io_requestor_16_hstatus_spvp (_ptw_io_requestor_16_hstatus_spvp), .io_requestor_16_hstatus_spv (_ptw_io_requestor_16_hstatus_spv), .io_requestor_16_hstatus_gva (_ptw_io_requestor_16_hstatus_gva), .io_requestor_16_gstatus_debug (_ptw_io_requestor_16_gstatus_debug), .io_requestor_16_gstatus_cease (_ptw_io_requestor_16_gstatus_cease), .io_requestor_16_gstatus_wfi (_ptw_io_requestor_16_gstatus_wfi), .io_requestor_16_gstatus_isa (_ptw_io_requestor_16_gstatus_isa), .io_requestor_16_gstatus_dprv (_ptw_io_requestor_16_gstatus_dprv), .io_requestor_16_gstatus_dv (_ptw_io_requestor_16_gstatus_dv), .io_requestor_16_gstatus_prv (_ptw_io_requestor_16_gstatus_prv), .io_requestor_16_gstatus_v (_ptw_io_requestor_16_gstatus_v), .io_requestor_16_gstatus_zero2 (_ptw_io_requestor_16_gstatus_zero2), .io_requestor_16_gstatus_mpv (_ptw_io_requestor_16_gstatus_mpv), .io_requestor_16_gstatus_gva (_ptw_io_requestor_16_gstatus_gva), .io_requestor_16_gstatus_mbe (_ptw_io_requestor_16_gstatus_mbe), .io_requestor_16_gstatus_sbe (_ptw_io_requestor_16_gstatus_sbe), .io_requestor_16_gstatus_sxl (_ptw_io_requestor_16_gstatus_sxl), .io_requestor_16_gstatus_zero1 (_ptw_io_requestor_16_gstatus_zero1), .io_requestor_16_gstatus_tsr (_ptw_io_requestor_16_gstatus_tsr), .io_requestor_16_gstatus_tw (_ptw_io_requestor_16_gstatus_tw), .io_requestor_16_gstatus_tvm (_ptw_io_requestor_16_gstatus_tvm), .io_requestor_16_gstatus_mxr (_ptw_io_requestor_16_gstatus_mxr), .io_requestor_16_gstatus_sum (_ptw_io_requestor_16_gstatus_sum), .io_requestor_16_gstatus_mprv (_ptw_io_requestor_16_gstatus_mprv), .io_requestor_16_gstatus_fs (_ptw_io_requestor_16_gstatus_fs), .io_requestor_16_gstatus_mpp (_ptw_io_requestor_16_gstatus_mpp), .io_requestor_16_gstatus_vs (_ptw_io_requestor_16_gstatus_vs), .io_requestor_16_gstatus_spp (_ptw_io_requestor_16_gstatus_spp), .io_requestor_16_gstatus_mpie (_ptw_io_requestor_16_gstatus_mpie), .io_requestor_16_gstatus_ube (_ptw_io_requestor_16_gstatus_ube), .io_requestor_16_gstatus_spie (_ptw_io_requestor_16_gstatus_spie), .io_requestor_16_gstatus_upie (_ptw_io_requestor_16_gstatus_upie), .io_requestor_16_gstatus_mie (_ptw_io_requestor_16_gstatus_mie), .io_requestor_16_gstatus_hie (_ptw_io_requestor_16_gstatus_hie), .io_requestor_16_gstatus_sie (_ptw_io_requestor_16_gstatus_sie), .io_requestor_16_gstatus_uie (_ptw_io_requestor_16_gstatus_uie), .io_requestor_16_pmp_0_cfg_l (_ptw_io_requestor_16_pmp_0_cfg_l), .io_requestor_16_pmp_0_cfg_a (_ptw_io_requestor_16_pmp_0_cfg_a), .io_requestor_16_pmp_0_cfg_x (_ptw_io_requestor_16_pmp_0_cfg_x), .io_requestor_16_pmp_0_cfg_w (_ptw_io_requestor_16_pmp_0_cfg_w), .io_requestor_16_pmp_0_cfg_r (_ptw_io_requestor_16_pmp_0_cfg_r), .io_requestor_16_pmp_0_addr (_ptw_io_requestor_16_pmp_0_addr), .io_requestor_16_pmp_0_mask (_ptw_io_requestor_16_pmp_0_mask), .io_requestor_16_pmp_1_cfg_l (_ptw_io_requestor_16_pmp_1_cfg_l), .io_requestor_16_pmp_1_cfg_a (_ptw_io_requestor_16_pmp_1_cfg_a), .io_requestor_16_pmp_1_cfg_x (_ptw_io_requestor_16_pmp_1_cfg_x), .io_requestor_16_pmp_1_cfg_w (_ptw_io_requestor_16_pmp_1_cfg_w), .io_requestor_16_pmp_1_cfg_r (_ptw_io_requestor_16_pmp_1_cfg_r), .io_requestor_16_pmp_1_addr (_ptw_io_requestor_16_pmp_1_addr), .io_requestor_16_pmp_1_mask (_ptw_io_requestor_16_pmp_1_mask), .io_requestor_16_pmp_2_cfg_l (_ptw_io_requestor_16_pmp_2_cfg_l), .io_requestor_16_pmp_2_cfg_a (_ptw_io_requestor_16_pmp_2_cfg_a), .io_requestor_16_pmp_2_cfg_x (_ptw_io_requestor_16_pmp_2_cfg_x), .io_requestor_16_pmp_2_cfg_w (_ptw_io_requestor_16_pmp_2_cfg_w), .io_requestor_16_pmp_2_cfg_r (_ptw_io_requestor_16_pmp_2_cfg_r), .io_requestor_16_pmp_2_addr (_ptw_io_requestor_16_pmp_2_addr), .io_requestor_16_pmp_2_mask (_ptw_io_requestor_16_pmp_2_mask), .io_requestor_16_pmp_3_cfg_l (_ptw_io_requestor_16_pmp_3_cfg_l), .io_requestor_16_pmp_3_cfg_a (_ptw_io_requestor_16_pmp_3_cfg_a), .io_requestor_16_pmp_3_cfg_x (_ptw_io_requestor_16_pmp_3_cfg_x), .io_requestor_16_pmp_3_cfg_w (_ptw_io_requestor_16_pmp_3_cfg_w), .io_requestor_16_pmp_3_cfg_r (_ptw_io_requestor_16_pmp_3_cfg_r), .io_requestor_16_pmp_3_addr (_ptw_io_requestor_16_pmp_3_addr), .io_requestor_16_pmp_3_mask (_ptw_io_requestor_16_pmp_3_mask), .io_requestor_16_pmp_4_cfg_l (_ptw_io_requestor_16_pmp_4_cfg_l), .io_requestor_16_pmp_4_cfg_a (_ptw_io_requestor_16_pmp_4_cfg_a), .io_requestor_16_pmp_4_cfg_x (_ptw_io_requestor_16_pmp_4_cfg_x), .io_requestor_16_pmp_4_cfg_w (_ptw_io_requestor_16_pmp_4_cfg_w), .io_requestor_16_pmp_4_cfg_r (_ptw_io_requestor_16_pmp_4_cfg_r), .io_requestor_16_pmp_4_addr (_ptw_io_requestor_16_pmp_4_addr), .io_requestor_16_pmp_4_mask (_ptw_io_requestor_16_pmp_4_mask), .io_requestor_16_pmp_5_cfg_l (_ptw_io_requestor_16_pmp_5_cfg_l), .io_requestor_16_pmp_5_cfg_a (_ptw_io_requestor_16_pmp_5_cfg_a), .io_requestor_16_pmp_5_cfg_x (_ptw_io_requestor_16_pmp_5_cfg_x), .io_requestor_16_pmp_5_cfg_w (_ptw_io_requestor_16_pmp_5_cfg_w), .io_requestor_16_pmp_5_cfg_r (_ptw_io_requestor_16_pmp_5_cfg_r), .io_requestor_16_pmp_5_addr (_ptw_io_requestor_16_pmp_5_addr), .io_requestor_16_pmp_5_mask (_ptw_io_requestor_16_pmp_5_mask), .io_requestor_16_pmp_6_cfg_l (_ptw_io_requestor_16_pmp_6_cfg_l), .io_requestor_16_pmp_6_cfg_a (_ptw_io_requestor_16_pmp_6_cfg_a), .io_requestor_16_pmp_6_cfg_x (_ptw_io_requestor_16_pmp_6_cfg_x), .io_requestor_16_pmp_6_cfg_w (_ptw_io_requestor_16_pmp_6_cfg_w), .io_requestor_16_pmp_6_cfg_r (_ptw_io_requestor_16_pmp_6_cfg_r), .io_requestor_16_pmp_6_addr (_ptw_io_requestor_16_pmp_6_addr), .io_requestor_16_pmp_6_mask (_ptw_io_requestor_16_pmp_6_mask), .io_requestor_16_pmp_7_cfg_l (_ptw_io_requestor_16_pmp_7_cfg_l), .io_requestor_16_pmp_7_cfg_a (_ptw_io_requestor_16_pmp_7_cfg_a), .io_requestor_16_pmp_7_cfg_x (_ptw_io_requestor_16_pmp_7_cfg_x), .io_requestor_16_pmp_7_cfg_w (_ptw_io_requestor_16_pmp_7_cfg_w), .io_requestor_16_pmp_7_cfg_r (_ptw_io_requestor_16_pmp_7_cfg_r), .io_requestor_16_pmp_7_addr (_ptw_io_requestor_16_pmp_7_addr), .io_requestor_16_pmp_7_mask (_ptw_io_requestor_16_pmp_7_mask), .io_requestor_16_customCSRs_csrs_0_ren (_ptw_io_requestor_16_customCSRs_csrs_0_ren), .io_requestor_16_customCSRs_csrs_0_wen (_ptw_io_requestor_16_customCSRs_csrs_0_wen), .io_requestor_16_customCSRs_csrs_0_wdata (_ptw_io_requestor_16_customCSRs_csrs_0_wdata), .io_requestor_16_customCSRs_csrs_0_value (_ptw_io_requestor_16_customCSRs_csrs_0_value), .io_requestor_16_customCSRs_csrs_1_ren (_ptw_io_requestor_16_customCSRs_csrs_1_ren), .io_requestor_16_customCSRs_csrs_1_wen (_ptw_io_requestor_16_customCSRs_csrs_1_wen), .io_requestor_16_customCSRs_csrs_1_wdata (_ptw_io_requestor_16_customCSRs_csrs_1_wdata), .io_requestor_16_customCSRs_csrs_1_value (_ptw_io_requestor_16_customCSRs_csrs_1_value), .io_requestor_16_customCSRs_csrs_2_ren (_ptw_io_requestor_16_customCSRs_csrs_2_ren), .io_requestor_16_customCSRs_csrs_2_wen (_ptw_io_requestor_16_customCSRs_csrs_2_wen), .io_requestor_16_customCSRs_csrs_2_wdata (_ptw_io_requestor_16_customCSRs_csrs_2_wdata), .io_requestor_16_customCSRs_csrs_2_value (_ptw_io_requestor_16_customCSRs_csrs_2_value), .io_requestor_16_customCSRs_csrs_3_ren (_ptw_io_requestor_16_customCSRs_csrs_3_ren), .io_requestor_16_customCSRs_csrs_3_wen (_ptw_io_requestor_16_customCSRs_csrs_3_wen), .io_requestor_16_customCSRs_csrs_3_wdata (_ptw_io_requestor_16_customCSRs_csrs_3_wdata), .io_requestor_16_customCSRs_csrs_3_value (_ptw_io_requestor_16_customCSRs_csrs_3_value), .io_requestor_17_req_ready (_ptw_io_requestor_17_req_ready), .io_requestor_17_req_valid (_zstd_compressor_io_ptw_17_req_valid), // @[Configs.scala:62:39] .io_requestor_17_req_bits_bits_addr (_zstd_compressor_io_ptw_17_req_bits_bits_addr), // @[Configs.scala:62:39] .io_requestor_17_req_bits_bits_need_gpa (_zstd_compressor_io_ptw_17_req_bits_bits_need_gpa), // @[Configs.scala:62:39] .io_requestor_17_resp_valid (_ptw_io_requestor_17_resp_valid), .io_requestor_17_resp_bits_ae_ptw (_ptw_io_requestor_17_resp_bits_ae_ptw), .io_requestor_17_resp_bits_ae_final (_ptw_io_requestor_17_resp_bits_ae_final), .io_requestor_17_resp_bits_pf (_ptw_io_requestor_17_resp_bits_pf), .io_requestor_17_resp_bits_gf (_ptw_io_requestor_17_resp_bits_gf), .io_requestor_17_resp_bits_hr (_ptw_io_requestor_17_resp_bits_hr), .io_requestor_17_resp_bits_hw (_ptw_io_requestor_17_resp_bits_hw), .io_requestor_17_resp_bits_hx (_ptw_io_requestor_17_resp_bits_hx), .io_requestor_17_resp_bits_pte_reserved_for_future (_ptw_io_requestor_17_resp_bits_pte_reserved_for_future), .io_requestor_17_resp_bits_pte_ppn (_ptw_io_requestor_17_resp_bits_pte_ppn), .io_requestor_17_resp_bits_pte_reserved_for_software (_ptw_io_requestor_17_resp_bits_pte_reserved_for_software), .io_requestor_17_resp_bits_pte_d (_ptw_io_requestor_17_resp_bits_pte_d), .io_requestor_17_resp_bits_pte_a (_ptw_io_requestor_17_resp_bits_pte_a), .io_requestor_17_resp_bits_pte_g (_ptw_io_requestor_17_resp_bits_pte_g), .io_requestor_17_resp_bits_pte_u (_ptw_io_requestor_17_resp_bits_pte_u), .io_requestor_17_resp_bits_pte_x (_ptw_io_requestor_17_resp_bits_pte_x), .io_requestor_17_resp_bits_pte_w (_ptw_io_requestor_17_resp_bits_pte_w), .io_requestor_17_resp_bits_pte_r (_ptw_io_requestor_17_resp_bits_pte_r), .io_requestor_17_resp_bits_pte_v (_ptw_io_requestor_17_resp_bits_pte_v), .io_requestor_17_resp_bits_level (_ptw_io_requestor_17_resp_bits_level), .io_requestor_17_resp_bits_homogeneous (_ptw_io_requestor_17_resp_bits_homogeneous), .io_requestor_17_resp_bits_gpa_valid (_ptw_io_requestor_17_resp_bits_gpa_valid), .io_requestor_17_resp_bits_gpa_bits (_ptw_io_requestor_17_resp_bits_gpa_bits), .io_requestor_17_resp_bits_gpa_is_pte (_ptw_io_requestor_17_resp_bits_gpa_is_pte), .io_requestor_17_ptbr_mode (_ptw_io_requestor_17_ptbr_mode), .io_requestor_17_ptbr_ppn (_ptw_io_requestor_17_ptbr_ppn), .io_requestor_17_status_debug (_ptw_io_requestor_17_status_debug), .io_requestor_17_status_cease (_ptw_io_requestor_17_status_cease), .io_requestor_17_status_wfi (_ptw_io_requestor_17_status_wfi), .io_requestor_17_status_isa (_ptw_io_requestor_17_status_isa), .io_requestor_17_status_dprv (_ptw_io_requestor_17_status_dprv), .io_requestor_17_status_dv (_ptw_io_requestor_17_status_dv), .io_requestor_17_status_prv (_ptw_io_requestor_17_status_prv), .io_requestor_17_status_v (_ptw_io_requestor_17_status_v), .io_requestor_17_status_mpv (_ptw_io_requestor_17_status_mpv), .io_requestor_17_status_gva (_ptw_io_requestor_17_status_gva), .io_requestor_17_status_tsr (_ptw_io_requestor_17_status_tsr), .io_requestor_17_status_tw (_ptw_io_requestor_17_status_tw), .io_requestor_17_status_tvm (_ptw_io_requestor_17_status_tvm), .io_requestor_17_status_mxr (_ptw_io_requestor_17_status_mxr), .io_requestor_17_status_sum (_ptw_io_requestor_17_status_sum), .io_requestor_17_status_mprv (_ptw_io_requestor_17_status_mprv), .io_requestor_17_status_fs (_ptw_io_requestor_17_status_fs), .io_requestor_17_status_mpp (_ptw_io_requestor_17_status_mpp), .io_requestor_17_status_spp (_ptw_io_requestor_17_status_spp), .io_requestor_17_status_mpie (_ptw_io_requestor_17_status_mpie), .io_requestor_17_status_spie (_ptw_io_requestor_17_status_spie), .io_requestor_17_status_mie (_ptw_io_requestor_17_status_mie), .io_requestor_17_status_sie (_ptw_io_requestor_17_status_sie), .io_requestor_17_hstatus_spvp (_ptw_io_requestor_17_hstatus_spvp), .io_requestor_17_hstatus_spv (_ptw_io_requestor_17_hstatus_spv), .io_requestor_17_hstatus_gva (_ptw_io_requestor_17_hstatus_gva), .io_requestor_17_gstatus_debug (_ptw_io_requestor_17_gstatus_debug), .io_requestor_17_gstatus_cease (_ptw_io_requestor_17_gstatus_cease), .io_requestor_17_gstatus_wfi (_ptw_io_requestor_17_gstatus_wfi), .io_requestor_17_gstatus_isa (_ptw_io_requestor_17_gstatus_isa), .io_requestor_17_gstatus_dprv (_ptw_io_requestor_17_gstatus_dprv), .io_requestor_17_gstatus_dv (_ptw_io_requestor_17_gstatus_dv), .io_requestor_17_gstatus_prv (_ptw_io_requestor_17_gstatus_prv), .io_requestor_17_gstatus_v (_ptw_io_requestor_17_gstatus_v), .io_requestor_17_gstatus_zero2 (_ptw_io_requestor_17_gstatus_zero2), .io_requestor_17_gstatus_mpv (_ptw_io_requestor_17_gstatus_mpv), .io_requestor_17_gstatus_gva (_ptw_io_requestor_17_gstatus_gva), .io_requestor_17_gstatus_mbe (_ptw_io_requestor_17_gstatus_mbe), .io_requestor_17_gstatus_sbe (_ptw_io_requestor_17_gstatus_sbe), .io_requestor_17_gstatus_sxl (_ptw_io_requestor_17_gstatus_sxl), .io_requestor_17_gstatus_zero1 (_ptw_io_requestor_17_gstatus_zero1), .io_requestor_17_gstatus_tsr (_ptw_io_requestor_17_gstatus_tsr), .io_requestor_17_gstatus_tw (_ptw_io_requestor_17_gstatus_tw), .io_requestor_17_gstatus_tvm (_ptw_io_requestor_17_gstatus_tvm), .io_requestor_17_gstatus_mxr (_ptw_io_requestor_17_gstatus_mxr), .io_requestor_17_gstatus_sum (_ptw_io_requestor_17_gstatus_sum), .io_requestor_17_gstatus_mprv (_ptw_io_requestor_17_gstatus_mprv), .io_requestor_17_gstatus_fs (_ptw_io_requestor_17_gstatus_fs), .io_requestor_17_gstatus_mpp (_ptw_io_requestor_17_gstatus_mpp), .io_requestor_17_gstatus_vs (_ptw_io_requestor_17_gstatus_vs), .io_requestor_17_gstatus_spp (_ptw_io_requestor_17_gstatus_spp), .io_requestor_17_gstatus_mpie (_ptw_io_requestor_17_gstatus_mpie), .io_requestor_17_gstatus_ube (_ptw_io_requestor_17_gstatus_ube), .io_requestor_17_gstatus_spie (_ptw_io_requestor_17_gstatus_spie), .io_requestor_17_gstatus_upie (_ptw_io_requestor_17_gstatus_upie), .io_requestor_17_gstatus_mie (_ptw_io_requestor_17_gstatus_mie), .io_requestor_17_gstatus_hie (_ptw_io_requestor_17_gstatus_hie), .io_requestor_17_gstatus_sie (_ptw_io_requestor_17_gstatus_sie), .io_requestor_17_gstatus_uie (_ptw_io_requestor_17_gstatus_uie), .io_requestor_17_pmp_0_cfg_l (_ptw_io_requestor_17_pmp_0_cfg_l), .io_requestor_17_pmp_0_cfg_a (_ptw_io_requestor_17_pmp_0_cfg_a), .io_requestor_17_pmp_0_cfg_x (_ptw_io_requestor_17_pmp_0_cfg_x), .io_requestor_17_pmp_0_cfg_w (_ptw_io_requestor_17_pmp_0_cfg_w), .io_requestor_17_pmp_0_cfg_r (_ptw_io_requestor_17_pmp_0_cfg_r), .io_requestor_17_pmp_0_addr (_ptw_io_requestor_17_pmp_0_addr), .io_requestor_17_pmp_0_mask (_ptw_io_requestor_17_pmp_0_mask), .io_requestor_17_pmp_1_cfg_l (_ptw_io_requestor_17_pmp_1_cfg_l), .io_requestor_17_pmp_1_cfg_a (_ptw_io_requestor_17_pmp_1_cfg_a), .io_requestor_17_pmp_1_cfg_x (_ptw_io_requestor_17_pmp_1_cfg_x), .io_requestor_17_pmp_1_cfg_w (_ptw_io_requestor_17_pmp_1_cfg_w), .io_requestor_17_pmp_1_cfg_r (_ptw_io_requestor_17_pmp_1_cfg_r), .io_requestor_17_pmp_1_addr (_ptw_io_requestor_17_pmp_1_addr), .io_requestor_17_pmp_1_mask (_ptw_io_requestor_17_pmp_1_mask), .io_requestor_17_pmp_2_cfg_l (_ptw_io_requestor_17_pmp_2_cfg_l), .io_requestor_17_pmp_2_cfg_a (_ptw_io_requestor_17_pmp_2_cfg_a), .io_requestor_17_pmp_2_cfg_x (_ptw_io_requestor_17_pmp_2_cfg_x), .io_requestor_17_pmp_2_cfg_w (_ptw_io_requestor_17_pmp_2_cfg_w), .io_requestor_17_pmp_2_cfg_r (_ptw_io_requestor_17_pmp_2_cfg_r), .io_requestor_17_pmp_2_addr (_ptw_io_requestor_17_pmp_2_addr), .io_requestor_17_pmp_2_mask (_ptw_io_requestor_17_pmp_2_mask), .io_requestor_17_pmp_3_cfg_l (_ptw_io_requestor_17_pmp_3_cfg_l), .io_requestor_17_pmp_3_cfg_a (_ptw_io_requestor_17_pmp_3_cfg_a), .io_requestor_17_pmp_3_cfg_x (_ptw_io_requestor_17_pmp_3_cfg_x), .io_requestor_17_pmp_3_cfg_w (_ptw_io_requestor_17_pmp_3_cfg_w), .io_requestor_17_pmp_3_cfg_r (_ptw_io_requestor_17_pmp_3_cfg_r), .io_requestor_17_pmp_3_addr (_ptw_io_requestor_17_pmp_3_addr), .io_requestor_17_pmp_3_mask (_ptw_io_requestor_17_pmp_3_mask), .io_requestor_17_pmp_4_cfg_l (_ptw_io_requestor_17_pmp_4_cfg_l), .io_requestor_17_pmp_4_cfg_a (_ptw_io_requestor_17_pmp_4_cfg_a), .io_requestor_17_pmp_4_cfg_x (_ptw_io_requestor_17_pmp_4_cfg_x), .io_requestor_17_pmp_4_cfg_w (_ptw_io_requestor_17_pmp_4_cfg_w), .io_requestor_17_pmp_4_cfg_r (_ptw_io_requestor_17_pmp_4_cfg_r), .io_requestor_17_pmp_4_addr (_ptw_io_requestor_17_pmp_4_addr), .io_requestor_17_pmp_4_mask (_ptw_io_requestor_17_pmp_4_mask), .io_requestor_17_pmp_5_cfg_l (_ptw_io_requestor_17_pmp_5_cfg_l), .io_requestor_17_pmp_5_cfg_a (_ptw_io_requestor_17_pmp_5_cfg_a), .io_requestor_17_pmp_5_cfg_x (_ptw_io_requestor_17_pmp_5_cfg_x), .io_requestor_17_pmp_5_cfg_w (_ptw_io_requestor_17_pmp_5_cfg_w), .io_requestor_17_pmp_5_cfg_r (_ptw_io_requestor_17_pmp_5_cfg_r), .io_requestor_17_pmp_5_addr (_ptw_io_requestor_17_pmp_5_addr), .io_requestor_17_pmp_5_mask (_ptw_io_requestor_17_pmp_5_mask), .io_requestor_17_pmp_6_cfg_l (_ptw_io_requestor_17_pmp_6_cfg_l), .io_requestor_17_pmp_6_cfg_a (_ptw_io_requestor_17_pmp_6_cfg_a), .io_requestor_17_pmp_6_cfg_x (_ptw_io_requestor_17_pmp_6_cfg_x), .io_requestor_17_pmp_6_cfg_w (_ptw_io_requestor_17_pmp_6_cfg_w), .io_requestor_17_pmp_6_cfg_r (_ptw_io_requestor_17_pmp_6_cfg_r), .io_requestor_17_pmp_6_addr (_ptw_io_requestor_17_pmp_6_addr), .io_requestor_17_pmp_6_mask (_ptw_io_requestor_17_pmp_6_mask), .io_requestor_17_pmp_7_cfg_l (_ptw_io_requestor_17_pmp_7_cfg_l), .io_requestor_17_pmp_7_cfg_a (_ptw_io_requestor_17_pmp_7_cfg_a), .io_requestor_17_pmp_7_cfg_x (_ptw_io_requestor_17_pmp_7_cfg_x), .io_requestor_17_pmp_7_cfg_w (_ptw_io_requestor_17_pmp_7_cfg_w), .io_requestor_17_pmp_7_cfg_r (_ptw_io_requestor_17_pmp_7_cfg_r), .io_requestor_17_pmp_7_addr (_ptw_io_requestor_17_pmp_7_addr), .io_requestor_17_pmp_7_mask (_ptw_io_requestor_17_pmp_7_mask), .io_requestor_17_customCSRs_csrs_0_ren (_ptw_io_requestor_17_customCSRs_csrs_0_ren), .io_requestor_17_customCSRs_csrs_0_wen (_ptw_io_requestor_17_customCSRs_csrs_0_wen), .io_requestor_17_customCSRs_csrs_0_wdata (_ptw_io_requestor_17_customCSRs_csrs_0_wdata), .io_requestor_17_customCSRs_csrs_0_value (_ptw_io_requestor_17_customCSRs_csrs_0_value), .io_requestor_17_customCSRs_csrs_1_ren (_ptw_io_requestor_17_customCSRs_csrs_1_ren), .io_requestor_17_customCSRs_csrs_1_wen (_ptw_io_requestor_17_customCSRs_csrs_1_wen), .io_requestor_17_customCSRs_csrs_1_wdata (_ptw_io_requestor_17_customCSRs_csrs_1_wdata), .io_requestor_17_customCSRs_csrs_1_value (_ptw_io_requestor_17_customCSRs_csrs_1_value), .io_requestor_17_customCSRs_csrs_2_ren (_ptw_io_requestor_17_customCSRs_csrs_2_ren), .io_requestor_17_customCSRs_csrs_2_wen (_ptw_io_requestor_17_customCSRs_csrs_2_wen), .io_requestor_17_customCSRs_csrs_2_wdata (_ptw_io_requestor_17_customCSRs_csrs_2_wdata), .io_requestor_17_customCSRs_csrs_2_value (_ptw_io_requestor_17_customCSRs_csrs_2_value), .io_requestor_17_customCSRs_csrs_3_ren (_ptw_io_requestor_17_customCSRs_csrs_3_ren), .io_requestor_17_customCSRs_csrs_3_wen (_ptw_io_requestor_17_customCSRs_csrs_3_wen), .io_requestor_17_customCSRs_csrs_3_wdata (_ptw_io_requestor_17_customCSRs_csrs_3_wdata), .io_requestor_17_customCSRs_csrs_3_value (_ptw_io_requestor_17_customCSRs_csrs_3_value), .io_requestor_18_req_ready (_ptw_io_requestor_18_req_ready), .io_requestor_18_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43] .io_requestor_18_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43] .io_requestor_18_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43] .io_requestor_18_resp_valid (_ptw_io_requestor_18_resp_valid), .io_requestor_18_resp_bits_ae_ptw (_ptw_io_requestor_18_resp_bits_ae_ptw), .io_requestor_18_resp_bits_ae_final (_ptw_io_requestor_18_resp_bits_ae_final), .io_requestor_18_resp_bits_pf (_ptw_io_requestor_18_resp_bits_pf), .io_requestor_18_resp_bits_gf (_ptw_io_requestor_18_resp_bits_gf), .io_requestor_18_resp_bits_hr (_ptw_io_requestor_18_resp_bits_hr), .io_requestor_18_resp_bits_hw (_ptw_io_requestor_18_resp_bits_hw), .io_requestor_18_resp_bits_hx (_ptw_io_requestor_18_resp_bits_hx), .io_requestor_18_resp_bits_pte_reserved_for_future (_ptw_io_requestor_18_resp_bits_pte_reserved_for_future), .io_requestor_18_resp_bits_pte_ppn (_ptw_io_requestor_18_resp_bits_pte_ppn), .io_requestor_18_resp_bits_pte_reserved_for_software (_ptw_io_requestor_18_resp_bits_pte_reserved_for_software), .io_requestor_18_resp_bits_pte_d (_ptw_io_requestor_18_resp_bits_pte_d), .io_requestor_18_resp_bits_pte_a (_ptw_io_requestor_18_resp_bits_pte_a), .io_requestor_18_resp_bits_pte_g (_ptw_io_requestor_18_resp_bits_pte_g), .io_requestor_18_resp_bits_pte_u (_ptw_io_requestor_18_resp_bits_pte_u), .io_requestor_18_resp_bits_pte_x (_ptw_io_requestor_18_resp_bits_pte_x), .io_requestor_18_resp_bits_pte_w (_ptw_io_requestor_18_resp_bits_pte_w), .io_requestor_18_resp_bits_pte_r (_ptw_io_requestor_18_resp_bits_pte_r), .io_requestor_18_resp_bits_pte_v (_ptw_io_requestor_18_resp_bits_pte_v), .io_requestor_18_resp_bits_level (_ptw_io_requestor_18_resp_bits_level), .io_requestor_18_resp_bits_homogeneous (_ptw_io_requestor_18_resp_bits_homogeneous), .io_requestor_18_resp_bits_gpa_valid (_ptw_io_requestor_18_resp_bits_gpa_valid), .io_requestor_18_resp_bits_gpa_bits (_ptw_io_requestor_18_resp_bits_gpa_bits), .io_requestor_18_resp_bits_gpa_is_pte (_ptw_io_requestor_18_resp_bits_gpa_is_pte), .io_requestor_18_ptbr_mode (_ptw_io_requestor_18_ptbr_mode), .io_requestor_18_ptbr_ppn (_ptw_io_requestor_18_ptbr_ppn), .io_requestor_18_status_debug (_ptw_io_requestor_18_status_debug), .io_requestor_18_status_cease (_ptw_io_requestor_18_status_cease), .io_requestor_18_status_wfi (_ptw_io_requestor_18_status_wfi), .io_requestor_18_status_isa (_ptw_io_requestor_18_status_isa), .io_requestor_18_status_dprv (_ptw_io_requestor_18_status_dprv), .io_requestor_18_status_dv (_ptw_io_requestor_18_status_dv), .io_requestor_18_status_prv (_ptw_io_requestor_18_status_prv), .io_requestor_18_status_v (_ptw_io_requestor_18_status_v), .io_requestor_18_status_mpv (_ptw_io_requestor_18_status_mpv), .io_requestor_18_status_gva (_ptw_io_requestor_18_status_gva), .io_requestor_18_status_tsr (_ptw_io_requestor_18_status_tsr), .io_requestor_18_status_tw (_ptw_io_requestor_18_status_tw), .io_requestor_18_status_tvm (_ptw_io_requestor_18_status_tvm), .io_requestor_18_status_mxr (_ptw_io_requestor_18_status_mxr), .io_requestor_18_status_sum (_ptw_io_requestor_18_status_sum), .io_requestor_18_status_mprv (_ptw_io_requestor_18_status_mprv), .io_requestor_18_status_fs (_ptw_io_requestor_18_status_fs), .io_requestor_18_status_mpp (_ptw_io_requestor_18_status_mpp), .io_requestor_18_status_spp (_ptw_io_requestor_18_status_spp), .io_requestor_18_status_mpie (_ptw_io_requestor_18_status_mpie), .io_requestor_18_status_spie (_ptw_io_requestor_18_status_spie), .io_requestor_18_status_mie (_ptw_io_requestor_18_status_mie), .io_requestor_18_status_sie (_ptw_io_requestor_18_status_sie), .io_requestor_18_hstatus_spvp (_ptw_io_requestor_18_hstatus_spvp), .io_requestor_18_hstatus_spv (_ptw_io_requestor_18_hstatus_spv), .io_requestor_18_hstatus_gva (_ptw_io_requestor_18_hstatus_gva), .io_requestor_18_gstatus_debug (_ptw_io_requestor_18_gstatus_debug), .io_requestor_18_gstatus_cease (_ptw_io_requestor_18_gstatus_cease), .io_requestor_18_gstatus_wfi (_ptw_io_requestor_18_gstatus_wfi), .io_requestor_18_gstatus_isa (_ptw_io_requestor_18_gstatus_isa), .io_requestor_18_gstatus_dprv (_ptw_io_requestor_18_gstatus_dprv), .io_requestor_18_gstatus_dv (_ptw_io_requestor_18_gstatus_dv), .io_requestor_18_gstatus_prv (_ptw_io_requestor_18_gstatus_prv), .io_requestor_18_gstatus_v (_ptw_io_requestor_18_gstatus_v), .io_requestor_18_gstatus_zero2 (_ptw_io_requestor_18_gstatus_zero2), .io_requestor_18_gstatus_mpv (_ptw_io_requestor_18_gstatus_mpv), .io_requestor_18_gstatus_gva (_ptw_io_requestor_18_gstatus_gva), .io_requestor_18_gstatus_mbe (_ptw_io_requestor_18_gstatus_mbe), .io_requestor_18_gstatus_sbe (_ptw_io_requestor_18_gstatus_sbe), .io_requestor_18_gstatus_sxl (_ptw_io_requestor_18_gstatus_sxl), .io_requestor_18_gstatus_zero1 (_ptw_io_requestor_18_gstatus_zero1), .io_requestor_18_gstatus_tsr (_ptw_io_requestor_18_gstatus_tsr), .io_requestor_18_gstatus_tw (_ptw_io_requestor_18_gstatus_tw), .io_requestor_18_gstatus_tvm (_ptw_io_requestor_18_gstatus_tvm), .io_requestor_18_gstatus_mxr (_ptw_io_requestor_18_gstatus_mxr), .io_requestor_18_gstatus_sum (_ptw_io_requestor_18_gstatus_sum), .io_requestor_18_gstatus_mprv (_ptw_io_requestor_18_gstatus_mprv), .io_requestor_18_gstatus_fs (_ptw_io_requestor_18_gstatus_fs), .io_requestor_18_gstatus_mpp (_ptw_io_requestor_18_gstatus_mpp), .io_requestor_18_gstatus_vs (_ptw_io_requestor_18_gstatus_vs), .io_requestor_18_gstatus_spp (_ptw_io_requestor_18_gstatus_spp), .io_requestor_18_gstatus_mpie (_ptw_io_requestor_18_gstatus_mpie), .io_requestor_18_gstatus_ube (_ptw_io_requestor_18_gstatus_ube), .io_requestor_18_gstatus_spie (_ptw_io_requestor_18_gstatus_spie), .io_requestor_18_gstatus_upie (_ptw_io_requestor_18_gstatus_upie), .io_requestor_18_gstatus_mie (_ptw_io_requestor_18_gstatus_mie), .io_requestor_18_gstatus_hie (_ptw_io_requestor_18_gstatus_hie), .io_requestor_18_gstatus_sie (_ptw_io_requestor_18_gstatus_sie), .io_requestor_18_gstatus_uie (_ptw_io_requestor_18_gstatus_uie), .io_requestor_18_pmp_0_cfg_l (_ptw_io_requestor_18_pmp_0_cfg_l), .io_requestor_18_pmp_0_cfg_a (_ptw_io_requestor_18_pmp_0_cfg_a), .io_requestor_18_pmp_0_cfg_x (_ptw_io_requestor_18_pmp_0_cfg_x), .io_requestor_18_pmp_0_cfg_w (_ptw_io_requestor_18_pmp_0_cfg_w), .io_requestor_18_pmp_0_cfg_r (_ptw_io_requestor_18_pmp_0_cfg_r), .io_requestor_18_pmp_0_addr (_ptw_io_requestor_18_pmp_0_addr), .io_requestor_18_pmp_0_mask (_ptw_io_requestor_18_pmp_0_mask), .io_requestor_18_pmp_1_cfg_l (_ptw_io_requestor_18_pmp_1_cfg_l), .io_requestor_18_pmp_1_cfg_a (_ptw_io_requestor_18_pmp_1_cfg_a), .io_requestor_18_pmp_1_cfg_x (_ptw_io_requestor_18_pmp_1_cfg_x), .io_requestor_18_pmp_1_cfg_w (_ptw_io_requestor_18_pmp_1_cfg_w), .io_requestor_18_pmp_1_cfg_r (_ptw_io_requestor_18_pmp_1_cfg_r), .io_requestor_18_pmp_1_addr (_ptw_io_requestor_18_pmp_1_addr), .io_requestor_18_pmp_1_mask (_ptw_io_requestor_18_pmp_1_mask), .io_requestor_18_pmp_2_cfg_l (_ptw_io_requestor_18_pmp_2_cfg_l), .io_requestor_18_pmp_2_cfg_a (_ptw_io_requestor_18_pmp_2_cfg_a), .io_requestor_18_pmp_2_cfg_x (_ptw_io_requestor_18_pmp_2_cfg_x), .io_requestor_18_pmp_2_cfg_w (_ptw_io_requestor_18_pmp_2_cfg_w), .io_requestor_18_pmp_2_cfg_r (_ptw_io_requestor_18_pmp_2_cfg_r), .io_requestor_18_pmp_2_addr (_ptw_io_requestor_18_pmp_2_addr), .io_requestor_18_pmp_2_mask (_ptw_io_requestor_18_pmp_2_mask), .io_requestor_18_pmp_3_cfg_l (_ptw_io_requestor_18_pmp_3_cfg_l), .io_requestor_18_pmp_3_cfg_a (_ptw_io_requestor_18_pmp_3_cfg_a), .io_requestor_18_pmp_3_cfg_x (_ptw_io_requestor_18_pmp_3_cfg_x), .io_requestor_18_pmp_3_cfg_w (_ptw_io_requestor_18_pmp_3_cfg_w), .io_requestor_18_pmp_3_cfg_r (_ptw_io_requestor_18_pmp_3_cfg_r), .io_requestor_18_pmp_3_addr (_ptw_io_requestor_18_pmp_3_addr), .io_requestor_18_pmp_3_mask (_ptw_io_requestor_18_pmp_3_mask), .io_requestor_18_pmp_4_cfg_l (_ptw_io_requestor_18_pmp_4_cfg_l), .io_requestor_18_pmp_4_cfg_a (_ptw_io_requestor_18_pmp_4_cfg_a), .io_requestor_18_pmp_4_cfg_x (_ptw_io_requestor_18_pmp_4_cfg_x), .io_requestor_18_pmp_4_cfg_w (_ptw_io_requestor_18_pmp_4_cfg_w), .io_requestor_18_pmp_4_cfg_r (_ptw_io_requestor_18_pmp_4_cfg_r), .io_requestor_18_pmp_4_addr (_ptw_io_requestor_18_pmp_4_addr), .io_requestor_18_pmp_4_mask (_ptw_io_requestor_18_pmp_4_mask), .io_requestor_18_pmp_5_cfg_l (_ptw_io_requestor_18_pmp_5_cfg_l), .io_requestor_18_pmp_5_cfg_a (_ptw_io_requestor_18_pmp_5_cfg_a), .io_requestor_18_pmp_5_cfg_x (_ptw_io_requestor_18_pmp_5_cfg_x), .io_requestor_18_pmp_5_cfg_w (_ptw_io_requestor_18_pmp_5_cfg_w), .io_requestor_18_pmp_5_cfg_r (_ptw_io_requestor_18_pmp_5_cfg_r), .io_requestor_18_pmp_5_addr (_ptw_io_requestor_18_pmp_5_addr), .io_requestor_18_pmp_5_mask (_ptw_io_requestor_18_pmp_5_mask), .io_requestor_18_pmp_6_cfg_l (_ptw_io_requestor_18_pmp_6_cfg_l), .io_requestor_18_pmp_6_cfg_a (_ptw_io_requestor_18_pmp_6_cfg_a), .io_requestor_18_pmp_6_cfg_x (_ptw_io_requestor_18_pmp_6_cfg_x), .io_requestor_18_pmp_6_cfg_w (_ptw_io_requestor_18_pmp_6_cfg_w), .io_requestor_18_pmp_6_cfg_r (_ptw_io_requestor_18_pmp_6_cfg_r), .io_requestor_18_pmp_6_addr (_ptw_io_requestor_18_pmp_6_addr), .io_requestor_18_pmp_6_mask (_ptw_io_requestor_18_pmp_6_mask), .io_requestor_18_pmp_7_cfg_l (_ptw_io_requestor_18_pmp_7_cfg_l), .io_requestor_18_pmp_7_cfg_a (_ptw_io_requestor_18_pmp_7_cfg_a), .io_requestor_18_pmp_7_cfg_x (_ptw_io_requestor_18_pmp_7_cfg_x), .io_requestor_18_pmp_7_cfg_w (_ptw_io_requestor_18_pmp_7_cfg_w), .io_requestor_18_pmp_7_cfg_r (_ptw_io_requestor_18_pmp_7_cfg_r), .io_requestor_18_pmp_7_addr (_ptw_io_requestor_18_pmp_7_addr), .io_requestor_18_pmp_7_mask (_ptw_io_requestor_18_pmp_7_mask), .io_requestor_18_customCSRs_csrs_0_ren (_ptw_io_requestor_18_customCSRs_csrs_0_ren), .io_requestor_18_customCSRs_csrs_0_wen (_ptw_io_requestor_18_customCSRs_csrs_0_wen), .io_requestor_18_customCSRs_csrs_0_wdata (_ptw_io_requestor_18_customCSRs_csrs_0_wdata), .io_requestor_18_customCSRs_csrs_0_value (_ptw_io_requestor_18_customCSRs_csrs_0_value), .io_requestor_18_customCSRs_csrs_1_ren (_ptw_io_requestor_18_customCSRs_csrs_1_ren), .io_requestor_18_customCSRs_csrs_1_wen (_ptw_io_requestor_18_customCSRs_csrs_1_wen), .io_requestor_18_customCSRs_csrs_1_wdata (_ptw_io_requestor_18_customCSRs_csrs_1_wdata), .io_requestor_18_customCSRs_csrs_1_value (_ptw_io_requestor_18_customCSRs_csrs_1_value), .io_requestor_18_customCSRs_csrs_2_ren (_ptw_io_requestor_18_customCSRs_csrs_2_ren), .io_requestor_18_customCSRs_csrs_2_wen (_ptw_io_requestor_18_customCSRs_csrs_2_wen), .io_requestor_18_customCSRs_csrs_2_wdata (_ptw_io_requestor_18_customCSRs_csrs_2_wdata), .io_requestor_18_customCSRs_csrs_2_value (_ptw_io_requestor_18_customCSRs_csrs_2_value), .io_requestor_18_customCSRs_csrs_3_ren (_ptw_io_requestor_18_customCSRs_csrs_3_ren), .io_requestor_18_customCSRs_csrs_3_wen (_ptw_io_requestor_18_customCSRs_csrs_3_wen), .io_requestor_18_customCSRs_csrs_3_wdata (_ptw_io_requestor_18_customCSRs_csrs_3_wdata), .io_requestor_18_customCSRs_csrs_3_value (_ptw_io_requestor_18_customCSRs_csrs_3_value), .io_requestor_19_req_ready (_ptw_io_requestor_19_req_ready), .io_requestor_19_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28] .io_requestor_19_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28] .io_requestor_19_resp_valid (_ptw_io_requestor_19_resp_valid), .io_requestor_19_resp_bits_ae_ptw (_ptw_io_requestor_19_resp_bits_ae_ptw), .io_requestor_19_resp_bits_ae_final (_ptw_io_requestor_19_resp_bits_ae_final), .io_requestor_19_resp_bits_pf (_ptw_io_requestor_19_resp_bits_pf), .io_requestor_19_resp_bits_gf (_ptw_io_requestor_19_resp_bits_gf), .io_requestor_19_resp_bits_hr (_ptw_io_requestor_19_resp_bits_hr), .io_requestor_19_resp_bits_hw (_ptw_io_requestor_19_resp_bits_hw), .io_requestor_19_resp_bits_hx (_ptw_io_requestor_19_resp_bits_hx), .io_requestor_19_resp_bits_pte_reserved_for_future (_ptw_io_requestor_19_resp_bits_pte_reserved_for_future), .io_requestor_19_resp_bits_pte_ppn (_ptw_io_requestor_19_resp_bits_pte_ppn), .io_requestor_19_resp_bits_pte_reserved_for_software (_ptw_io_requestor_19_resp_bits_pte_reserved_for_software), .io_requestor_19_resp_bits_pte_d (_ptw_io_requestor_19_resp_bits_pte_d), .io_requestor_19_resp_bits_pte_a (_ptw_io_requestor_19_resp_bits_pte_a), .io_requestor_19_resp_bits_pte_g (_ptw_io_requestor_19_resp_bits_pte_g), .io_requestor_19_resp_bits_pte_u (_ptw_io_requestor_19_resp_bits_pte_u), .io_requestor_19_resp_bits_pte_x (_ptw_io_requestor_19_resp_bits_pte_x), .io_requestor_19_resp_bits_pte_w (_ptw_io_requestor_19_resp_bits_pte_w), .io_requestor_19_resp_bits_pte_r (_ptw_io_requestor_19_resp_bits_pte_r), .io_requestor_19_resp_bits_pte_v (_ptw_io_requestor_19_resp_bits_pte_v), .io_requestor_19_resp_bits_level (_ptw_io_requestor_19_resp_bits_level), .io_requestor_19_resp_bits_homogeneous (_ptw_io_requestor_19_resp_bits_homogeneous), .io_requestor_19_resp_bits_gpa_valid (_ptw_io_requestor_19_resp_bits_gpa_valid), .io_requestor_19_resp_bits_gpa_bits (_ptw_io_requestor_19_resp_bits_gpa_bits), .io_requestor_19_resp_bits_gpa_is_pte (_ptw_io_requestor_19_resp_bits_gpa_is_pte), .io_requestor_19_ptbr_mode (_ptw_io_requestor_19_ptbr_mode), .io_requestor_19_ptbr_ppn (_ptw_io_requestor_19_ptbr_ppn), .io_requestor_19_status_debug (_ptw_io_requestor_19_status_debug), .io_requestor_19_status_cease (_ptw_io_requestor_19_status_cease), .io_requestor_19_status_wfi (_ptw_io_requestor_19_status_wfi), .io_requestor_19_status_isa (_ptw_io_requestor_19_status_isa), .io_requestor_19_status_dprv (_ptw_io_requestor_19_status_dprv), .io_requestor_19_status_dv (_ptw_io_requestor_19_status_dv), .io_requestor_19_status_prv (_ptw_io_requestor_19_status_prv), .io_requestor_19_status_v (_ptw_io_requestor_19_status_v), .io_requestor_19_status_mpv (_ptw_io_requestor_19_status_mpv), .io_requestor_19_status_gva (_ptw_io_requestor_19_status_gva), .io_requestor_19_status_tsr (_ptw_io_requestor_19_status_tsr), .io_requestor_19_status_tw (_ptw_io_requestor_19_status_tw), .io_requestor_19_status_tvm (_ptw_io_requestor_19_status_tvm), .io_requestor_19_status_mxr (_ptw_io_requestor_19_status_mxr), .io_requestor_19_status_sum (_ptw_io_requestor_19_status_sum), .io_requestor_19_status_mprv (_ptw_io_requestor_19_status_mprv), .io_requestor_19_status_fs (_ptw_io_requestor_19_status_fs), .io_requestor_19_status_mpp (_ptw_io_requestor_19_status_mpp), .io_requestor_19_status_spp (_ptw_io_requestor_19_status_spp), .io_requestor_19_status_mpie (_ptw_io_requestor_19_status_mpie), .io_requestor_19_status_spie (_ptw_io_requestor_19_status_spie), .io_requestor_19_status_mie (_ptw_io_requestor_19_status_mie), .io_requestor_19_status_sie (_ptw_io_requestor_19_status_sie), .io_requestor_19_hstatus_spvp (_ptw_io_requestor_19_hstatus_spvp), .io_requestor_19_hstatus_spv (_ptw_io_requestor_19_hstatus_spv), .io_requestor_19_hstatus_gva (_ptw_io_requestor_19_hstatus_gva), .io_requestor_19_gstatus_debug (_ptw_io_requestor_19_gstatus_debug), .io_requestor_19_gstatus_cease (_ptw_io_requestor_19_gstatus_cease), .io_requestor_19_gstatus_wfi (_ptw_io_requestor_19_gstatus_wfi), .io_requestor_19_gstatus_isa (_ptw_io_requestor_19_gstatus_isa), .io_requestor_19_gstatus_dprv (_ptw_io_requestor_19_gstatus_dprv), .io_requestor_19_gstatus_dv (_ptw_io_requestor_19_gstatus_dv), .io_requestor_19_gstatus_prv (_ptw_io_requestor_19_gstatus_prv), .io_requestor_19_gstatus_v (_ptw_io_requestor_19_gstatus_v), .io_requestor_19_gstatus_zero2 (_ptw_io_requestor_19_gstatus_zero2), .io_requestor_19_gstatus_mpv (_ptw_io_requestor_19_gstatus_mpv), .io_requestor_19_gstatus_gva (_ptw_io_requestor_19_gstatus_gva), .io_requestor_19_gstatus_mbe (_ptw_io_requestor_19_gstatus_mbe), .io_requestor_19_gstatus_sbe (_ptw_io_requestor_19_gstatus_sbe), .io_requestor_19_gstatus_sxl (_ptw_io_requestor_19_gstatus_sxl), .io_requestor_19_gstatus_zero1 (_ptw_io_requestor_19_gstatus_zero1), .io_requestor_19_gstatus_tsr (_ptw_io_requestor_19_gstatus_tsr), .io_requestor_19_gstatus_tw (_ptw_io_requestor_19_gstatus_tw), .io_requestor_19_gstatus_tvm (_ptw_io_requestor_19_gstatus_tvm), .io_requestor_19_gstatus_mxr (_ptw_io_requestor_19_gstatus_mxr), .io_requestor_19_gstatus_sum (_ptw_io_requestor_19_gstatus_sum), .io_requestor_19_gstatus_mprv (_ptw_io_requestor_19_gstatus_mprv), .io_requestor_19_gstatus_fs (_ptw_io_requestor_19_gstatus_fs), .io_requestor_19_gstatus_mpp (_ptw_io_requestor_19_gstatus_mpp), .io_requestor_19_gstatus_vs (_ptw_io_requestor_19_gstatus_vs), .io_requestor_19_gstatus_spp (_ptw_io_requestor_19_gstatus_spp), .io_requestor_19_gstatus_mpie (_ptw_io_requestor_19_gstatus_mpie), .io_requestor_19_gstatus_ube (_ptw_io_requestor_19_gstatus_ube), .io_requestor_19_gstatus_spie (_ptw_io_requestor_19_gstatus_spie), .io_requestor_19_gstatus_upie (_ptw_io_requestor_19_gstatus_upie), .io_requestor_19_gstatus_mie (_ptw_io_requestor_19_gstatus_mie), .io_requestor_19_gstatus_hie (_ptw_io_requestor_19_gstatus_hie), .io_requestor_19_gstatus_sie (_ptw_io_requestor_19_gstatus_sie), .io_requestor_19_gstatus_uie (_ptw_io_requestor_19_gstatus_uie), .io_requestor_19_pmp_0_cfg_l (_ptw_io_requestor_19_pmp_0_cfg_l), .io_requestor_19_pmp_0_cfg_a (_ptw_io_requestor_19_pmp_0_cfg_a), .io_requestor_19_pmp_0_cfg_x (_ptw_io_requestor_19_pmp_0_cfg_x), .io_requestor_19_pmp_0_cfg_w (_ptw_io_requestor_19_pmp_0_cfg_w), .io_requestor_19_pmp_0_cfg_r (_ptw_io_requestor_19_pmp_0_cfg_r), .io_requestor_19_pmp_0_addr (_ptw_io_requestor_19_pmp_0_addr), .io_requestor_19_pmp_0_mask (_ptw_io_requestor_19_pmp_0_mask), .io_requestor_19_pmp_1_cfg_l (_ptw_io_requestor_19_pmp_1_cfg_l), .io_requestor_19_pmp_1_cfg_a (_ptw_io_requestor_19_pmp_1_cfg_a), .io_requestor_19_pmp_1_cfg_x (_ptw_io_requestor_19_pmp_1_cfg_x), .io_requestor_19_pmp_1_cfg_w (_ptw_io_requestor_19_pmp_1_cfg_w), .io_requestor_19_pmp_1_cfg_r (_ptw_io_requestor_19_pmp_1_cfg_r), .io_requestor_19_pmp_1_addr (_ptw_io_requestor_19_pmp_1_addr), .io_requestor_19_pmp_1_mask (_ptw_io_requestor_19_pmp_1_mask), .io_requestor_19_pmp_2_cfg_l (_ptw_io_requestor_19_pmp_2_cfg_l), .io_requestor_19_pmp_2_cfg_a (_ptw_io_requestor_19_pmp_2_cfg_a), .io_requestor_19_pmp_2_cfg_x (_ptw_io_requestor_19_pmp_2_cfg_x), .io_requestor_19_pmp_2_cfg_w (_ptw_io_requestor_19_pmp_2_cfg_w), .io_requestor_19_pmp_2_cfg_r (_ptw_io_requestor_19_pmp_2_cfg_r), .io_requestor_19_pmp_2_addr (_ptw_io_requestor_19_pmp_2_addr), .io_requestor_19_pmp_2_mask (_ptw_io_requestor_19_pmp_2_mask), .io_requestor_19_pmp_3_cfg_l (_ptw_io_requestor_19_pmp_3_cfg_l), .io_requestor_19_pmp_3_cfg_a (_ptw_io_requestor_19_pmp_3_cfg_a), .io_requestor_19_pmp_3_cfg_x (_ptw_io_requestor_19_pmp_3_cfg_x), .io_requestor_19_pmp_3_cfg_w (_ptw_io_requestor_19_pmp_3_cfg_w), .io_requestor_19_pmp_3_cfg_r (_ptw_io_requestor_19_pmp_3_cfg_r), .io_requestor_19_pmp_3_addr (_ptw_io_requestor_19_pmp_3_addr), .io_requestor_19_pmp_3_mask (_ptw_io_requestor_19_pmp_3_mask), .io_requestor_19_pmp_4_cfg_l (_ptw_io_requestor_19_pmp_4_cfg_l), .io_requestor_19_pmp_4_cfg_a (_ptw_io_requestor_19_pmp_4_cfg_a), .io_requestor_19_pmp_4_cfg_x (_ptw_io_requestor_19_pmp_4_cfg_x), .io_requestor_19_pmp_4_cfg_w (_ptw_io_requestor_19_pmp_4_cfg_w), .io_requestor_19_pmp_4_cfg_r (_ptw_io_requestor_19_pmp_4_cfg_r), .io_requestor_19_pmp_4_addr (_ptw_io_requestor_19_pmp_4_addr), .io_requestor_19_pmp_4_mask (_ptw_io_requestor_19_pmp_4_mask), .io_requestor_19_pmp_5_cfg_l (_ptw_io_requestor_19_pmp_5_cfg_l), .io_requestor_19_pmp_5_cfg_a (_ptw_io_requestor_19_pmp_5_cfg_a), .io_requestor_19_pmp_5_cfg_x (_ptw_io_requestor_19_pmp_5_cfg_x), .io_requestor_19_pmp_5_cfg_w (_ptw_io_requestor_19_pmp_5_cfg_w), .io_requestor_19_pmp_5_cfg_r (_ptw_io_requestor_19_pmp_5_cfg_r), .io_requestor_19_pmp_5_addr (_ptw_io_requestor_19_pmp_5_addr), .io_requestor_19_pmp_5_mask (_ptw_io_requestor_19_pmp_5_mask), .io_requestor_19_pmp_6_cfg_l (_ptw_io_requestor_19_pmp_6_cfg_l), .io_requestor_19_pmp_6_cfg_a (_ptw_io_requestor_19_pmp_6_cfg_a), .io_requestor_19_pmp_6_cfg_x (_ptw_io_requestor_19_pmp_6_cfg_x), .io_requestor_19_pmp_6_cfg_w (_ptw_io_requestor_19_pmp_6_cfg_w), .io_requestor_19_pmp_6_cfg_r (_ptw_io_requestor_19_pmp_6_cfg_r), .io_requestor_19_pmp_6_addr (_ptw_io_requestor_19_pmp_6_addr), .io_requestor_19_pmp_6_mask (_ptw_io_requestor_19_pmp_6_mask), .io_requestor_19_pmp_7_cfg_l (_ptw_io_requestor_19_pmp_7_cfg_l), .io_requestor_19_pmp_7_cfg_a (_ptw_io_requestor_19_pmp_7_cfg_a), .io_requestor_19_pmp_7_cfg_x (_ptw_io_requestor_19_pmp_7_cfg_x), .io_requestor_19_pmp_7_cfg_w (_ptw_io_requestor_19_pmp_7_cfg_w), .io_requestor_19_pmp_7_cfg_r (_ptw_io_requestor_19_pmp_7_cfg_r), .io_requestor_19_pmp_7_addr (_ptw_io_requestor_19_pmp_7_addr), .io_requestor_19_pmp_7_mask (_ptw_io_requestor_19_pmp_7_mask), .io_requestor_19_customCSRs_csrs_0_ren (_ptw_io_requestor_19_customCSRs_csrs_0_ren), .io_requestor_19_customCSRs_csrs_0_wen (_ptw_io_requestor_19_customCSRs_csrs_0_wen), .io_requestor_19_customCSRs_csrs_0_wdata (_ptw_io_requestor_19_customCSRs_csrs_0_wdata), .io_requestor_19_customCSRs_csrs_0_value (_ptw_io_requestor_19_customCSRs_csrs_0_value), .io_requestor_19_customCSRs_csrs_1_ren (_ptw_io_requestor_19_customCSRs_csrs_1_ren), .io_requestor_19_customCSRs_csrs_1_wen (_ptw_io_requestor_19_customCSRs_csrs_1_wen), .io_requestor_19_customCSRs_csrs_1_wdata (_ptw_io_requestor_19_customCSRs_csrs_1_wdata), .io_requestor_19_customCSRs_csrs_1_value (_ptw_io_requestor_19_customCSRs_csrs_1_value), .io_requestor_19_customCSRs_csrs_2_ren (_ptw_io_requestor_19_customCSRs_csrs_2_ren), .io_requestor_19_customCSRs_csrs_2_wen (_ptw_io_requestor_19_customCSRs_csrs_2_wen), .io_requestor_19_customCSRs_csrs_2_wdata (_ptw_io_requestor_19_customCSRs_csrs_2_wdata), .io_requestor_19_customCSRs_csrs_2_value (_ptw_io_requestor_19_customCSRs_csrs_2_value), .io_requestor_19_customCSRs_csrs_3_ren (_ptw_io_requestor_19_customCSRs_csrs_3_ren), .io_requestor_19_customCSRs_csrs_3_wen (_ptw_io_requestor_19_customCSRs_csrs_3_wen), .io_requestor_19_customCSRs_csrs_3_wdata (_ptw_io_requestor_19_customCSRs_csrs_3_wdata), .io_requestor_19_customCSRs_csrs_3_value (_ptw_io_requestor_19_customCSRs_csrs_3_value), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20] .io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20] .io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20] .io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20] .io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20] .io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20] .io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20] .io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20] .io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20] .io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20] .io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20] .io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20] .io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20] .io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20] .io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20] .io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20] .io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20] .io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20] .io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20] .io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20] .io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20] .io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20] .io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20] .io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20] .io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20] .io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20] .io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20] .io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20] .io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20] .io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20] .io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20] .io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20] .io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20] .io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20] .io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20] .io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20] .io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20] .io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), .io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20] .io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20] .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[PTW.scala:802:19] RRArbiter respArb ( // @[LazyRoCC.scala:101:25] .clock (clock), .reset (reset), .io_in_0_ready (_respArb_io_in_0_ready), .io_in_0_valid (_respArb_io_in_0_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_0_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd), // @[Decoupled.scala:362:21] .io_in_0_bits_data (_respArb_io_in_0_q_io_deq_bits_data), // @[Decoupled.scala:362:21] .io_out_ready (_core_io_rocc_resp_ready), // @[RocketTile.scala:147:20] .io_out_valid (_respArb_io_out_valid), .io_out_bits_rd (_respArb_io_out_bits_rd), .io_out_bits_data (_respArb_io_out_bits_data) ); // @[LazyRoCC.scala:101:25] RoccCommandRouter cmdRouter ( // @[LazyRoCC.scala:102:27] .clock (clock), .reset (reset), .io_in_ready (_cmdRouter_io_in_ready), .io_in_valid (_core_io_rocc_cmd_valid), // @[RocketTile.scala:147:20] .io_in_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct), // @[RocketTile.scala:147:20] .io_in_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2), // @[RocketTile.scala:147:20] .io_in_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1), // @[RocketTile.scala:147:20] .io_in_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd), // @[RocketTile.scala:147:20] .io_in_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1), // @[RocketTile.scala:147:20] .io_in_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2), // @[RocketTile.scala:147:20] .io_in_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd), // @[RocketTile.scala:147:20] .io_in_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode), // @[RocketTile.scala:147:20] .io_in_bits_rs1 (_core_io_rocc_cmd_bits_rs1), // @[RocketTile.scala:147:20] .io_in_bits_rs2 (_core_io_rocc_cmd_bits_rs2), // @[RocketTile.scala:147:20] .io_in_bits_status_debug (_core_io_rocc_cmd_bits_status_debug), // @[RocketTile.scala:147:20] .io_in_bits_status_cease (_core_io_rocc_cmd_bits_status_cease), // @[RocketTile.scala:147:20] .io_in_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi), // @[RocketTile.scala:147:20] .io_in_bits_status_isa (_core_io_rocc_cmd_bits_status_isa), // @[RocketTile.scala:147:20] .io_in_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv), // @[RocketTile.scala:147:20] .io_in_bits_status_dv (_core_io_rocc_cmd_bits_status_dv), // @[RocketTile.scala:147:20] .io_in_bits_status_prv (_core_io_rocc_cmd_bits_status_prv), // @[RocketTile.scala:147:20] .io_in_bits_status_v (_core_io_rocc_cmd_bits_status_v), // @[RocketTile.scala:147:20] .io_in_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv), // @[RocketTile.scala:147:20] .io_in_bits_status_gva (_core_io_rocc_cmd_bits_status_gva), // @[RocketTile.scala:147:20] .io_in_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr), // @[RocketTile.scala:147:20] .io_in_bits_status_tw (_core_io_rocc_cmd_bits_status_tw), // @[RocketTile.scala:147:20] .io_in_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm), // @[RocketTile.scala:147:20] .io_in_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr), // @[RocketTile.scala:147:20] .io_in_bits_status_sum (_core_io_rocc_cmd_bits_status_sum), // @[RocketTile.scala:147:20] .io_in_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv), // @[RocketTile.scala:147:20] .io_in_bits_status_fs (_core_io_rocc_cmd_bits_status_fs), // @[RocketTile.scala:147:20] .io_in_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp), // @[RocketTile.scala:147:20] .io_in_bits_status_spp (_core_io_rocc_cmd_bits_status_spp), // @[RocketTile.scala:147:20] .io_in_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie), // @[RocketTile.scala:147:20] .io_in_bits_status_spie (_core_io_rocc_cmd_bits_status_spie), // @[RocketTile.scala:147:20] .io_in_bits_status_mie (_core_io_rocc_cmd_bits_status_mie), // @[RocketTile.scala:147:20] .io_in_bits_status_sie (_core_io_rocc_cmd_bits_status_sie), // @[RocketTile.scala:147:20] .io_out_0_ready (_zstd_compressor_io_cmd_ready), // @[Configs.scala:62:39] .io_out_0_valid (_cmdRouter_io_out_0_valid), .io_out_0_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct), .io_out_0_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2), .io_out_0_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1), .io_out_0_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd), .io_out_0_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1), .io_out_0_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2), .io_out_0_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd), .io_out_0_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode), .io_out_0_bits_rs1 (_cmdRouter_io_out_0_bits_rs1), .io_out_0_bits_rs2 (_cmdRouter_io_out_0_bits_rs2), .io_out_0_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug), .io_out_0_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease), .io_out_0_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi), .io_out_0_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa), .io_out_0_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv), .io_out_0_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv), .io_out_0_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv), .io_out_0_bits_status_v (_cmdRouter_io_out_0_bits_status_v), .io_out_0_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd), .io_out_0_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2), .io_out_0_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv), .io_out_0_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva), .io_out_0_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe), .io_out_0_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe), .io_out_0_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl), .io_out_0_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl), .io_out_0_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32), .io_out_0_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1), .io_out_0_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr), .io_out_0_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw), .io_out_0_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm), .io_out_0_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr), .io_out_0_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum), .io_out_0_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv), .io_out_0_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs), .io_out_0_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs), .io_out_0_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp), .io_out_0_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs), .io_out_0_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp), .io_out_0_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie), .io_out_0_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube), .io_out_0_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie), .io_out_0_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie), .io_out_0_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie), .io_out_0_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie), .io_out_0_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie), .io_out_0_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie), .io_busy (_core_io_rocc_busy_T) ); // @[LazyRoCC.scala:102:27] SimpleHellaCacheIF dcIF ( // @[LazyRoCC.scala:106:24] .clock (clock), .reset (reset), .io_requestor_req_ready (_dcIF_io_requestor_req_ready), .io_requestor_resp_valid (_dcIF_io_requestor_resp_valid), .io_requestor_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr), .io_requestor_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag), .io_requestor_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd), .io_requestor_resp_bits_size (_dcIF_io_requestor_resp_bits_size), .io_requestor_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed), .io_requestor_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv), .io_requestor_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv), .io_requestor_resp_bits_data (_dcIF_io_requestor_resp_bits_data), .io_requestor_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask), .io_requestor_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay), .io_requestor_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data), .io_requestor_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass), .io_requestor_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw), .io_requestor_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data), .io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25] .io_cache_req_valid (_dcIF_io_cache_req_valid), .io_cache_s1_data_data (_dcIF_io_cache_s1_data_data), .io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask), .io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25] .io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25] .io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25] .io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25] .io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25] .io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25] .io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25] .io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25] .io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25] .io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25] .io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25] .io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25] .io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25] .io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25] .io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25] .io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25] .io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25] .io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[HellaCache.scala:292:25] ); // @[LazyRoCC.scala:106:24] Queue2_RoCCResponse respArb_io_in_0_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_respArb_io_in_0_q_io_enq_ready), .io_enq_valid (_zstd_compressor_io_resp_valid), // @[Configs.scala:62:39] .io_enq_bits_rd (_zstd_compressor_io_resp_bits_rd), // @[Configs.scala:62:39] .io_enq_bits_data (_zstd_compressor_io_resp_bits_data), // @[Configs.scala:62:39] .io_deq_ready (_respArb_io_in_0_ready), // @[LazyRoCC.scala:101:25] .io_deq_valid (_respArb_io_in_0_q_io_deq_valid), .io_deq_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd), .io_deq_bits_data (_respArb_io_in_0_q_io_deq_bits_data) ); // @[Decoupled.scala:362:21] Rocket core ( // @[RocketTile.scala:147:20] .clock (clock), .reset (reset), .io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17] .io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17] .io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17] .io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17] .io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17] .io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17] .io_imem_might_request (_core_io_imem_might_request), .io_imem_req_valid (_core_io_imem_req_valid), .io_imem_req_bits_pc (_core_io_imem_req_bits_pc), .io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative), .io_imem_sfence_valid (_core_io_imem_sfence_valid), .io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), .io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), .io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr), .io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid), .io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv), .io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg), .io_imem_resp_ready (_core_io_imem_resp_ready), .io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28] .io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28] .io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28] .io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28] .io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28] .io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28] .io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28] .io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28] .io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28] .io_imem_btb_update_valid (_core_io_imem_btb_update_valid), .io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), .io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), .io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), .io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), .io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), .io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), .io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), .io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), .io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), .io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target), .io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), .io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), .io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), .io_imem_bht_update_valid (_core_io_imem_bht_update_valid), .io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), .io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), .io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), .io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), .io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), .io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), .io_imem_flush_icache (_core_io_imem_flush_icache), .io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28] .io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28] .io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28] .io_imem_progress (_core_io_imem_progress), .io_dmem_req_ready (_dcacheArb_io_requestor_2_req_ready), // @[HellaCache.scala:292:25] .io_dmem_req_valid (_core_io_dmem_req_valid), .io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr), .io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag), .io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd), .io_dmem_req_bits_size (_core_io_dmem_req_bits_size), .io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed), .io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv), .io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv), .io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), .io_dmem_s1_kill (_core_io_dmem_s1_kill), .io_dmem_s1_data_data (_core_io_dmem_s1_data_data), .io_dmem_s2_nack (_dcacheArb_io_requestor_2_s2_nack), // @[HellaCache.scala:292:25] .io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw), // @[HellaCache.scala:292:25] .io_dmem_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached), // @[HellaCache.scala:292:25] .io_dmem_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr), // @[HellaCache.scala:292:25] .io_dmem_resp_valid (_dcacheArb_io_requestor_2_resp_valid), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw), // @[HellaCache.scala:292:25] .io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data), // @[HellaCache.scala:292:25] .io_dmem_replay_next (_dcacheArb_io_requestor_2_replay_next), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25] .io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st), // @[HellaCache.scala:292:25] .io_dmem_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa), // @[HellaCache.scala:292:25] .io_dmem_ordered (_dcacheArb_io_requestor_2_ordered), // @[HellaCache.scala:292:25] .io_dmem_store_pending (_dcacheArb_io_requestor_2_store_pending), // @[HellaCache.scala:292:25] .io_dmem_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire), // @[HellaCache.scala:292:25] .io_dmem_perf_release (_dcacheArb_io_requestor_2_perf_release), // @[HellaCache.scala:292:25] .io_dmem_perf_grant (_dcacheArb_io_requestor_2_perf_grant), // @[HellaCache.scala:292:25] .io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss), // @[HellaCache.scala:292:25] .io_dmem_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25] .io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25] .io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25] .io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), .io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode), .io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_core_io_ptw_sfence_valid), .io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), .io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), .io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), .io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), .io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), .io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), .io_ptw_status_debug (_core_io_ptw_status_debug), .io_ptw_status_cease (_core_io_ptw_status_cease), .io_ptw_status_wfi (_core_io_ptw_status_wfi), .io_ptw_status_isa (_core_io_ptw_status_isa), .io_ptw_status_dprv (_core_io_ptw_status_dprv), .io_ptw_status_dv (_core_io_ptw_status_dv), .io_ptw_status_prv (_core_io_ptw_status_prv), .io_ptw_status_v (_core_io_ptw_status_v), .io_ptw_status_mpv (_core_io_ptw_status_mpv), .io_ptw_status_gva (_core_io_ptw_status_gva), .io_ptw_status_tsr (_core_io_ptw_status_tsr), .io_ptw_status_tw (_core_io_ptw_status_tw), .io_ptw_status_tvm (_core_io_ptw_status_tvm), .io_ptw_status_mxr (_core_io_ptw_status_mxr), .io_ptw_status_sum (_core_io_ptw_status_sum), .io_ptw_status_mprv (_core_io_ptw_status_mprv), .io_ptw_status_fs (_core_io_ptw_status_fs), .io_ptw_status_mpp (_core_io_ptw_status_mpp), .io_ptw_status_spp (_core_io_ptw_status_spp), .io_ptw_status_mpie (_core_io_ptw_status_mpie), .io_ptw_status_spie (_core_io_ptw_status_spie), .io_ptw_status_mie (_core_io_ptw_status_mie), .io_ptw_status_sie (_core_io_ptw_status_sie), .io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp), .io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv), .io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva), .io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug), .io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease), .io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi), .io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa), .io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv), .io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv), .io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv), .io_ptw_gstatus_v (_core_io_ptw_gstatus_v), .io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2), .io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv), .io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva), .io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe), .io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe), .io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl), .io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1), .io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr), .io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw), .io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm), .io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr), .io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum), .io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv), .io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs), .io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp), .io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs), .io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp), .io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie), .io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube), .io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie), .io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie), .io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie), .io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie), .io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie), .io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie), .io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), .io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), .io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), .io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), .io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), .io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr), .io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask), .io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), .io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), .io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), .io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), .io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), .io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr), .io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask), .io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), .io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), .io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), .io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), .io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), .io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr), .io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask), .io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), .io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), .io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), .io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), .io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), .io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr), .io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask), .io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), .io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), .io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), .io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), .io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), .io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr), .io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask), .io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), .io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), .io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), .io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), .io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), .io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr), .io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask), .io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), .io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), .io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), .io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), .io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), .io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr), .io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask), .io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), .io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), .io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), .io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), .io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), .io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr), .io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19] .io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19] .io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), .io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), .io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), .io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), .io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), .io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), .io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), .io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), .io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), .io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), .io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), .io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), .io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), .io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), .io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), .io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19] .io_fpu_hartid (_core_io_fpu_hartid), .io_fpu_time (_core_io_fpu_time), .io_fpu_inst (_core_io_fpu_inst), .io_fpu_fromint_data (_core_io_fpu_fromint_data), .io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm), .io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62] .io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62] .io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62] .io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62] .io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val), .io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type), .io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag), .io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data), .io_fpu_valid (_core_io_fpu_valid), .io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62] .io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62] .io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62] .io_fpu_killx (_core_io_fpu_killx), .io_fpu_killm (_core_io_fpu_killm), .io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62] .io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62] .io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62] .io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62] .io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62] .io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62] .io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62] .io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62] .io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62] .io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62] .io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62] .io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62] .io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62] .io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62] .io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62] .io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62] .io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62] .io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62] .io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62] .io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled), .io_rocc_cmd_ready (_cmdRouter_io_in_ready), // @[LazyRoCC.scala:102:27] .io_rocc_cmd_valid (_core_io_rocc_cmd_valid), .io_rocc_cmd_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct), .io_rocc_cmd_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2), .io_rocc_cmd_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1), .io_rocc_cmd_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd), .io_rocc_cmd_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1), .io_rocc_cmd_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2), .io_rocc_cmd_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd), .io_rocc_cmd_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode), .io_rocc_cmd_bits_rs1 (_core_io_rocc_cmd_bits_rs1), .io_rocc_cmd_bits_rs2 (_core_io_rocc_cmd_bits_rs2), .io_rocc_cmd_bits_status_debug (_core_io_rocc_cmd_bits_status_debug), .io_rocc_cmd_bits_status_cease (_core_io_rocc_cmd_bits_status_cease), .io_rocc_cmd_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi), .io_rocc_cmd_bits_status_isa (_core_io_rocc_cmd_bits_status_isa), .io_rocc_cmd_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv), .io_rocc_cmd_bits_status_dv (_core_io_rocc_cmd_bits_status_dv), .io_rocc_cmd_bits_status_prv (_core_io_rocc_cmd_bits_status_prv), .io_rocc_cmd_bits_status_v (_core_io_rocc_cmd_bits_status_v), .io_rocc_cmd_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv), .io_rocc_cmd_bits_status_gva (_core_io_rocc_cmd_bits_status_gva), .io_rocc_cmd_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr), .io_rocc_cmd_bits_status_tw (_core_io_rocc_cmd_bits_status_tw), .io_rocc_cmd_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm), .io_rocc_cmd_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr), .io_rocc_cmd_bits_status_sum (_core_io_rocc_cmd_bits_status_sum), .io_rocc_cmd_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv), .io_rocc_cmd_bits_status_fs (_core_io_rocc_cmd_bits_status_fs), .io_rocc_cmd_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp), .io_rocc_cmd_bits_status_spp (_core_io_rocc_cmd_bits_status_spp), .io_rocc_cmd_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie), .io_rocc_cmd_bits_status_spie (_core_io_rocc_cmd_bits_status_spie), .io_rocc_cmd_bits_status_mie (_core_io_rocc_cmd_bits_status_mie), .io_rocc_cmd_bits_status_sie (_core_io_rocc_cmd_bits_status_sie), .io_rocc_resp_ready (_core_io_rocc_resp_ready), .io_rocc_resp_valid (_respArb_io_out_valid), // @[LazyRoCC.scala:101:25] .io_rocc_resp_bits_rd (_respArb_io_out_bits_rd), // @[LazyRoCC.scala:101:25] .io_rocc_resp_bits_data (_respArb_io_out_bits_data), // @[LazyRoCC.scala:101:25] .io_rocc_busy (_core_io_rocc_busy_T), // @[RocketTile.scala:213:49] .io_rocc_exception (_core_io_rocc_exception), .io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid), .io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr), .io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn), .io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv), .io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception), .io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt), .io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause), .io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval), .io_trace_time (traceSourceNodeOut_time), .io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0), .io_bpwatch_0_action (bpwatchSourceNodeOut_0_action), .io_wfi (_core_io_wfi) ); // @[RocketTile.scala:147:20] assign auto_buffer_out_18_a_valid = auto_buffer_out_18_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_opcode = auto_buffer_out_18_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_param = auto_buffer_out_18_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_size = auto_buffer_out_18_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_source = auto_buffer_out_18_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_address = auto_buffer_out_18_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_mask = auto_buffer_out_18_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_a_bits_data = auto_buffer_out_18_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_b_ready = auto_buffer_out_18_b_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_valid = auto_buffer_out_18_c_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_opcode = auto_buffer_out_18_c_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_param = auto_buffer_out_18_c_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_size = auto_buffer_out_18_c_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_source = auto_buffer_out_18_c_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_address = auto_buffer_out_18_c_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_c_bits_data = auto_buffer_out_18_c_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_d_ready = auto_buffer_out_18_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_e_valid = auto_buffer_out_18_e_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_18_e_bits_sink = auto_buffer_out_18_e_bits_sink_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_valid = auto_buffer_out_17_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_opcode = auto_buffer_out_17_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_param = auto_buffer_out_17_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_size = auto_buffer_out_17_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_source = auto_buffer_out_17_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_address = auto_buffer_out_17_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_mask = auto_buffer_out_17_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_data = auto_buffer_out_17_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_a_bits_corrupt = auto_buffer_out_17_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_17_d_ready = auto_buffer_out_17_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_valid = auto_buffer_out_16_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_opcode = auto_buffer_out_16_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_param = auto_buffer_out_16_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_size = auto_buffer_out_16_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_source = auto_buffer_out_16_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_address = auto_buffer_out_16_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_mask = auto_buffer_out_16_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_data = auto_buffer_out_16_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_a_bits_corrupt = auto_buffer_out_16_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_16_d_ready = auto_buffer_out_16_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_valid = auto_buffer_out_15_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_opcode = auto_buffer_out_15_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_param = auto_buffer_out_15_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_size = auto_buffer_out_15_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_source = auto_buffer_out_15_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_address = auto_buffer_out_15_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_mask = auto_buffer_out_15_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_data = auto_buffer_out_15_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_a_bits_corrupt = auto_buffer_out_15_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_15_d_ready = auto_buffer_out_15_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_valid = auto_buffer_out_14_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_opcode = auto_buffer_out_14_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_param = auto_buffer_out_14_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_size = auto_buffer_out_14_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_source = auto_buffer_out_14_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_address = auto_buffer_out_14_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_mask = auto_buffer_out_14_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_data = auto_buffer_out_14_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_a_bits_corrupt = auto_buffer_out_14_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_14_d_ready = auto_buffer_out_14_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_valid = auto_buffer_out_13_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_opcode = auto_buffer_out_13_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_param = auto_buffer_out_13_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_size = auto_buffer_out_13_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_source = auto_buffer_out_13_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_address = auto_buffer_out_13_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_mask = auto_buffer_out_13_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_data = auto_buffer_out_13_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_a_bits_corrupt = auto_buffer_out_13_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_13_d_ready = auto_buffer_out_13_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_valid = auto_buffer_out_12_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_opcode = auto_buffer_out_12_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_param = auto_buffer_out_12_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_size = auto_buffer_out_12_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_source = auto_buffer_out_12_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_address = auto_buffer_out_12_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_mask = auto_buffer_out_12_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_data = auto_buffer_out_12_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_a_bits_corrupt = auto_buffer_out_12_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_12_d_ready = auto_buffer_out_12_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_valid = auto_buffer_out_11_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_opcode = auto_buffer_out_11_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_param = auto_buffer_out_11_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_size = auto_buffer_out_11_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_source = auto_buffer_out_11_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_address = auto_buffer_out_11_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_mask = auto_buffer_out_11_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_data = auto_buffer_out_11_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_a_bits_corrupt = auto_buffer_out_11_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_11_d_ready = auto_buffer_out_11_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_valid = auto_buffer_out_10_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_opcode = auto_buffer_out_10_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_param = auto_buffer_out_10_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_size = auto_buffer_out_10_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_source = auto_buffer_out_10_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_address = auto_buffer_out_10_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_mask = auto_buffer_out_10_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_data = auto_buffer_out_10_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_a_bits_corrupt = auto_buffer_out_10_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_10_d_ready = auto_buffer_out_10_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_valid = auto_buffer_out_9_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_opcode = auto_buffer_out_9_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_param = auto_buffer_out_9_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_size = auto_buffer_out_9_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_source = auto_buffer_out_9_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_address = auto_buffer_out_9_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_mask = auto_buffer_out_9_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_data = auto_buffer_out_9_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_a_bits_corrupt = auto_buffer_out_9_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_9_d_ready = auto_buffer_out_9_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_valid = auto_buffer_out_8_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_opcode = auto_buffer_out_8_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_param = auto_buffer_out_8_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_size = auto_buffer_out_8_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_source = auto_buffer_out_8_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_address = auto_buffer_out_8_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_mask = auto_buffer_out_8_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_data = auto_buffer_out_8_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_a_bits_corrupt = auto_buffer_out_8_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_8_d_ready = auto_buffer_out_8_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_valid = auto_buffer_out_7_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_opcode = auto_buffer_out_7_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_param = auto_buffer_out_7_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_size = auto_buffer_out_7_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_source = auto_buffer_out_7_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_address = auto_buffer_out_7_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_mask = auto_buffer_out_7_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_data = auto_buffer_out_7_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_a_bits_corrupt = auto_buffer_out_7_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_7_d_ready = auto_buffer_out_7_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_valid = auto_buffer_out_6_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_opcode = auto_buffer_out_6_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_param = auto_buffer_out_6_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_size = auto_buffer_out_6_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_source = auto_buffer_out_6_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_address = auto_buffer_out_6_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_mask = auto_buffer_out_6_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_data = auto_buffer_out_6_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_a_bits_corrupt = auto_buffer_out_6_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_6_d_ready = auto_buffer_out_6_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_valid = auto_buffer_out_5_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_opcode = auto_buffer_out_5_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_param = auto_buffer_out_5_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_size = auto_buffer_out_5_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_source = auto_buffer_out_5_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_address = auto_buffer_out_5_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_mask = auto_buffer_out_5_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_data = auto_buffer_out_5_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_a_bits_corrupt = auto_buffer_out_5_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_5_d_ready = auto_buffer_out_5_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_valid = auto_buffer_out_4_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_opcode = auto_buffer_out_4_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_param = auto_buffer_out_4_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_size = auto_buffer_out_4_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_source = auto_buffer_out_4_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_address = auto_buffer_out_4_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_mask = auto_buffer_out_4_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_data = auto_buffer_out_4_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_a_bits_corrupt = auto_buffer_out_4_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_4_d_ready = auto_buffer_out_4_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_valid = auto_buffer_out_3_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_opcode = auto_buffer_out_3_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_param = auto_buffer_out_3_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_size = auto_buffer_out_3_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_source = auto_buffer_out_3_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_address = auto_buffer_out_3_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_mask = auto_buffer_out_3_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_data = auto_buffer_out_3_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_a_bits_corrupt = auto_buffer_out_3_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_3_d_ready = auto_buffer_out_3_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_valid = auto_buffer_out_2_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_opcode = auto_buffer_out_2_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_param = auto_buffer_out_2_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_size = auto_buffer_out_2_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_source = auto_buffer_out_2_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_address = auto_buffer_out_2_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_mask = auto_buffer_out_2_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_data = auto_buffer_out_2_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_a_bits_corrupt = auto_buffer_out_2_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_2_d_ready = auto_buffer_out_2_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_valid = auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_opcode = auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_param = auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_size = auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_source = auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_address = auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_mask = auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_data = auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_a_bits_corrupt = auto_buffer_out_1_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_1_d_ready = auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_valid = auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_opcode = auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_param = auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_size = auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_source = auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_address = auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_mask = auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_data = auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_a_bits_corrupt = auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7] assign auto_buffer_out_0_d_ready = auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7] assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7] assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BankedStore : input clock : Clock input reset : Reset output io : { flip sinkC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, flip sinkC_dat : { data : UInt<128>}, flip sinkD_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkD_dat : { data : UInt<64>}, flip sourceC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceC_dat : { data : UInt<64>}, flip sourceD_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, sourceD_rdat : { data : UInt<128>}, flip sourceD_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<2>, mask : UInt<2>}}, flip sourceD_wdat : { data : UInt<128>}} smem cc_banks_0 : UInt<64> [8192] smem cc_banks_1 : UInt<64> [8192] smem cc_banks_2 : UInt<64> [8192] smem cc_banks_3 : UInt<64> [8192] smem cc_banks_4 : UInt<64> [8192] smem cc_banks_5 : UInt<64> [8192] smem cc_banks_6 : UInt<64> [8192] smem cc_banks_7 : UInt<64> [8192] node sinkC_req_words_0 = bits(io.sinkC_dat.data, 63, 0) node sinkC_req_words_1 = bits(io.sinkC_dat.data, 127, 64) node sinkC_req_a_hi = cat(io.sinkC_adr.bits.way, io.sinkC_adr.bits.set) node sinkC_req_a = cat(sinkC_req_a_hi, io.sinkC_adr.bits.beat) wire sinkC_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkC_req_select_T = bits(sinkC_req_a, 1, 0) node sinkC_req_select_shiftAmount = bits(_sinkC_req_select_T, 1, 0) node _sinkC_req_select_T_1 = dshl(UInt<1>(0h1), sinkC_req_select_shiftAmount) node sinkC_req_select = bits(_sinkC_req_select_T_1, 3, 0) node _sinkC_req_ready_T = bits(sinkC_req.bankSum, 1, 0) node _sinkC_req_ready_T_1 = and(_sinkC_req_ready_T, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_2 = orr(_sinkC_req_ready_T_1) node _sinkC_req_ready_T_3 = eq(_sinkC_req_ready_T_2, UInt<1>(0h0)) node _sinkC_req_ready_T_4 = bits(sinkC_req.bankSum, 3, 2) node _sinkC_req_ready_T_5 = and(_sinkC_req_ready_T_4, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_6 = orr(_sinkC_req_ready_T_5) node _sinkC_req_ready_T_7 = eq(_sinkC_req_ready_T_6, UInt<1>(0h0)) node _sinkC_req_ready_T_8 = bits(sinkC_req.bankSum, 5, 4) node _sinkC_req_ready_T_9 = and(_sinkC_req_ready_T_8, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_10 = orr(_sinkC_req_ready_T_9) node _sinkC_req_ready_T_11 = eq(_sinkC_req_ready_T_10, UInt<1>(0h0)) node _sinkC_req_ready_T_12 = bits(sinkC_req.bankSum, 7, 6) node _sinkC_req_ready_T_13 = and(_sinkC_req_ready_T_12, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_14 = orr(_sinkC_req_ready_T_13) node _sinkC_req_ready_T_15 = eq(_sinkC_req_ready_T_14, UInt<1>(0h0)) node sinkC_req_ready_lo = cat(_sinkC_req_ready_T_7, _sinkC_req_ready_T_3) node sinkC_req_ready_hi = cat(_sinkC_req_ready_T_15, _sinkC_req_ready_T_11) node sinkC_req_ready = cat(sinkC_req_ready_hi, sinkC_req_ready_lo) node _sinkC_req_io_sinkC_adr_ready_T = bits(sinkC_req_a, 1, 0) node _sinkC_req_io_sinkC_adr_ready_T_1 = dshr(sinkC_req_ready, _sinkC_req_io_sinkC_adr_ready_T) node _sinkC_req_io_sinkC_adr_ready_T_2 = bits(_sinkC_req_io_sinkC_adr_ready_T_1, 0, 0) connect io.sinkC_adr.ready, _sinkC_req_io_sinkC_adr_ready_T_2 connect sinkC_req.wen, UInt<1>(0h1) node _sinkC_req_out_index_T = shr(sinkC_req_a, 2) connect sinkC_req.index, _sinkC_req_out_index_T node _sinkC_req_out_bankSel_T = bits(sinkC_req_select, 0, 0) node _sinkC_req_out_bankSel_T_1 = bits(sinkC_req_select, 1, 1) node _sinkC_req_out_bankSel_T_2 = bits(sinkC_req_select, 2, 2) node _sinkC_req_out_bankSel_T_3 = bits(sinkC_req_select, 3, 3) node _sinkC_req_out_bankSel_T_4 = mux(_sinkC_req_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_5 = mux(_sinkC_req_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_6 = mux(_sinkC_req_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankSel_T_7 = mux(_sinkC_req_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankSel_lo = cat(_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4) node sinkC_req_out_bankSel_hi = cat(_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6) node _sinkC_req_out_bankSel_T_8 = cat(sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo) node _sinkC_req_out_bankSel_T_9 = cat(io.sinkC_adr.bits.mask, io.sinkC_adr.bits.mask) node _sinkC_req_out_bankSel_T_10 = cat(_sinkC_req_out_bankSel_T_9, _sinkC_req_out_bankSel_T_9) node _sinkC_req_out_bankSel_T_11 = and(_sinkC_req_out_bankSel_T_8, _sinkC_req_out_bankSel_T_10) node _sinkC_req_out_bankSel_T_12 = mux(io.sinkC_adr.valid, _sinkC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkC_req.bankSel, _sinkC_req_out_bankSel_T_12 node _sinkC_req_out_bankEn_T = bits(sinkC_req_ready, 0, 0) node _sinkC_req_out_bankEn_T_1 = bits(sinkC_req_ready, 1, 1) node _sinkC_req_out_bankEn_T_2 = bits(sinkC_req_ready, 2, 2) node _sinkC_req_out_bankEn_T_3 = bits(sinkC_req_ready, 3, 3) node _sinkC_req_out_bankEn_T_4 = mux(_sinkC_req_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_5 = mux(_sinkC_req_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_6 = mux(_sinkC_req_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sinkC_req_out_bankEn_T_7 = mux(_sinkC_req_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sinkC_req_out_bankEn_lo = cat(_sinkC_req_out_bankEn_T_5, _sinkC_req_out_bankEn_T_4) node sinkC_req_out_bankEn_hi = cat(_sinkC_req_out_bankEn_T_7, _sinkC_req_out_bankEn_T_6) node _sinkC_req_out_bankEn_T_8 = cat(sinkC_req_out_bankEn_hi, sinkC_req_out_bankEn_lo) node _sinkC_req_out_bankEn_T_9 = and(sinkC_req.bankSel, _sinkC_req_out_bankEn_T_8) node _sinkC_req_out_bankEn_T_10 = mux(io.sinkC_adr.bits.noop, UInt<1>(0h0), _sinkC_req_out_bankEn_T_9) connect sinkC_req.bankEn, _sinkC_req_out_bankEn_T_10 connect sinkC_req.data[0], sinkC_req_words_0 connect sinkC_req.data[1], sinkC_req_words_1 connect sinkC_req.data[2], sinkC_req_words_0 connect sinkC_req.data[3], sinkC_req_words_1 connect sinkC_req.data[4], sinkC_req_words_0 connect sinkC_req.data[5], sinkC_req_words_1 connect sinkC_req.data[6], sinkC_req_words_0 connect sinkC_req.data[7], sinkC_req_words_1 node sinkD_req_words_0 = bits(io.sinkD_dat.data, 63, 0) node sinkD_req_a_hi = cat(io.sinkD_adr.bits.way, io.sinkD_adr.bits.set) node sinkD_req_a = cat(sinkD_req_a_hi, io.sinkD_adr.bits.beat) wire sinkD_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sinkD_req_select_T = bits(sinkD_req_a, 2, 0) node sinkD_req_select_shiftAmount = bits(_sinkD_req_select_T, 2, 0) node _sinkD_req_select_T_1 = dshl(UInt<1>(0h1), sinkD_req_select_shiftAmount) node sinkD_req_select = bits(_sinkD_req_select_T_1, 7, 0) node _sinkD_req_ready_T = bits(sinkD_req.bankSum, 0, 0) node _sinkD_req_ready_T_1 = and(_sinkD_req_ready_T, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_2 = orr(_sinkD_req_ready_T_1) node _sinkD_req_ready_T_3 = eq(_sinkD_req_ready_T_2, UInt<1>(0h0)) node _sinkD_req_ready_T_4 = bits(sinkD_req.bankSum, 1, 1) node _sinkD_req_ready_T_5 = and(_sinkD_req_ready_T_4, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_6 = orr(_sinkD_req_ready_T_5) node _sinkD_req_ready_T_7 = eq(_sinkD_req_ready_T_6, UInt<1>(0h0)) node _sinkD_req_ready_T_8 = bits(sinkD_req.bankSum, 2, 2) node _sinkD_req_ready_T_9 = and(_sinkD_req_ready_T_8, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_10 = orr(_sinkD_req_ready_T_9) node _sinkD_req_ready_T_11 = eq(_sinkD_req_ready_T_10, UInt<1>(0h0)) node _sinkD_req_ready_T_12 = bits(sinkD_req.bankSum, 3, 3) node _sinkD_req_ready_T_13 = and(_sinkD_req_ready_T_12, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_14 = orr(_sinkD_req_ready_T_13) node _sinkD_req_ready_T_15 = eq(_sinkD_req_ready_T_14, UInt<1>(0h0)) node _sinkD_req_ready_T_16 = bits(sinkD_req.bankSum, 4, 4) node _sinkD_req_ready_T_17 = and(_sinkD_req_ready_T_16, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_18 = orr(_sinkD_req_ready_T_17) node _sinkD_req_ready_T_19 = eq(_sinkD_req_ready_T_18, UInt<1>(0h0)) node _sinkD_req_ready_T_20 = bits(sinkD_req.bankSum, 5, 5) node _sinkD_req_ready_T_21 = and(_sinkD_req_ready_T_20, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_22 = orr(_sinkD_req_ready_T_21) node _sinkD_req_ready_T_23 = eq(_sinkD_req_ready_T_22, UInt<1>(0h0)) node _sinkD_req_ready_T_24 = bits(sinkD_req.bankSum, 6, 6) node _sinkD_req_ready_T_25 = and(_sinkD_req_ready_T_24, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_26 = orr(_sinkD_req_ready_T_25) node _sinkD_req_ready_T_27 = eq(_sinkD_req_ready_T_26, UInt<1>(0h0)) node _sinkD_req_ready_T_28 = bits(sinkD_req.bankSum, 7, 7) node _sinkD_req_ready_T_29 = and(_sinkD_req_ready_T_28, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_30 = orr(_sinkD_req_ready_T_29) node _sinkD_req_ready_T_31 = eq(_sinkD_req_ready_T_30, UInt<1>(0h0)) node sinkD_req_ready_lo_lo = cat(_sinkD_req_ready_T_7, _sinkD_req_ready_T_3) node sinkD_req_ready_lo_hi = cat(_sinkD_req_ready_T_15, _sinkD_req_ready_T_11) node sinkD_req_ready_lo = cat(sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo) node sinkD_req_ready_hi_lo = cat(_sinkD_req_ready_T_23, _sinkD_req_ready_T_19) node sinkD_req_ready_hi_hi = cat(_sinkD_req_ready_T_31, _sinkD_req_ready_T_27) node sinkD_req_ready_hi = cat(sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo) node sinkD_req_ready = cat(sinkD_req_ready_hi, sinkD_req_ready_lo) node _sinkD_req_io_sinkD_adr_ready_T = bits(sinkD_req_a, 2, 0) node _sinkD_req_io_sinkD_adr_ready_T_1 = dshr(sinkD_req_ready, _sinkD_req_io_sinkD_adr_ready_T) node _sinkD_req_io_sinkD_adr_ready_T_2 = bits(_sinkD_req_io_sinkD_adr_ready_T_1, 0, 0) connect io.sinkD_adr.ready, _sinkD_req_io_sinkD_adr_ready_T_2 connect sinkD_req.wen, UInt<1>(0h1) node _sinkD_req_out_index_T = shr(sinkD_req_a, 3) connect sinkD_req.index, _sinkD_req_out_index_T node _sinkD_req_out_bankSel_T = bits(sinkD_req_select, 0, 0) node _sinkD_req_out_bankSel_T_1 = bits(sinkD_req_select, 1, 1) node _sinkD_req_out_bankSel_T_2 = bits(sinkD_req_select, 2, 2) node _sinkD_req_out_bankSel_T_3 = bits(sinkD_req_select, 3, 3) node _sinkD_req_out_bankSel_T_4 = bits(sinkD_req_select, 4, 4) node _sinkD_req_out_bankSel_T_5 = bits(sinkD_req_select, 5, 5) node _sinkD_req_out_bankSel_T_6 = bits(sinkD_req_select, 6, 6) node _sinkD_req_out_bankSel_T_7 = bits(sinkD_req_select, 7, 7) node sinkD_req_out_bankSel_lo_lo = cat(_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T) node sinkD_req_out_bankSel_lo_hi = cat(_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2) node sinkD_req_out_bankSel_lo = cat(sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo) node sinkD_req_out_bankSel_hi_lo = cat(_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4) node sinkD_req_out_bankSel_hi_hi = cat(_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6) node sinkD_req_out_bankSel_hi = cat(sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo) node _sinkD_req_out_bankSel_T_8 = cat(sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo) node _sinkD_req_out_bankSel_T_9 = bits(io.sinkD_adr.bits.mask, 0, 0) node _sinkD_req_out_bankSel_T_10 = mux(_sinkD_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sinkD_req_out_bankSel_T_11 = and(_sinkD_req_out_bankSel_T_8, _sinkD_req_out_bankSel_T_10) node _sinkD_req_out_bankSel_T_12 = mux(io.sinkD_adr.valid, _sinkD_req_out_bankSel_T_11, UInt<1>(0h0)) connect sinkD_req.bankSel, _sinkD_req_out_bankSel_T_12 node _sinkD_req_out_bankEn_T = bits(sinkD_req_ready, 0, 0) node _sinkD_req_out_bankEn_T_1 = bits(sinkD_req_ready, 1, 1) node _sinkD_req_out_bankEn_T_2 = bits(sinkD_req_ready, 2, 2) node _sinkD_req_out_bankEn_T_3 = bits(sinkD_req_ready, 3, 3) node _sinkD_req_out_bankEn_T_4 = bits(sinkD_req_ready, 4, 4) node _sinkD_req_out_bankEn_T_5 = bits(sinkD_req_ready, 5, 5) node _sinkD_req_out_bankEn_T_6 = bits(sinkD_req_ready, 6, 6) node _sinkD_req_out_bankEn_T_7 = bits(sinkD_req_ready, 7, 7) node sinkD_req_out_bankEn_lo_lo = cat(_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T) node sinkD_req_out_bankEn_lo_hi = cat(_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2) node sinkD_req_out_bankEn_lo = cat(sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo) node sinkD_req_out_bankEn_hi_lo = cat(_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4) node sinkD_req_out_bankEn_hi_hi = cat(_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6) node sinkD_req_out_bankEn_hi = cat(sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo) node _sinkD_req_out_bankEn_T_8 = cat(sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo) node _sinkD_req_out_bankEn_T_9 = and(sinkD_req.bankSel, _sinkD_req_out_bankEn_T_8) node _sinkD_req_out_bankEn_T_10 = mux(io.sinkD_adr.bits.noop, UInt<1>(0h0), _sinkD_req_out_bankEn_T_9) connect sinkD_req.bankEn, _sinkD_req_out_bankEn_T_10 connect sinkD_req.data[0], sinkD_req_words_0 connect sinkD_req.data[1], sinkD_req_words_0 connect sinkD_req.data[2], sinkD_req_words_0 connect sinkD_req.data[3], sinkD_req_words_0 connect sinkD_req.data[4], sinkD_req_words_0 connect sinkD_req.data[5], sinkD_req_words_0 connect sinkD_req.data[6], sinkD_req_words_0 connect sinkD_req.data[7], sinkD_req_words_0 node sourceC_req_a_hi = cat(io.sourceC_adr.bits.way, io.sourceC_adr.bits.set) node sourceC_req_a = cat(sourceC_req_a_hi, io.sourceC_adr.bits.beat) wire sourceC_req : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceC_req_select_T = bits(sourceC_req_a, 2, 0) node sourceC_req_select_shiftAmount = bits(_sourceC_req_select_T, 2, 0) node _sourceC_req_select_T_1 = dshl(UInt<1>(0h1), sourceC_req_select_shiftAmount) node sourceC_req_select = bits(_sourceC_req_select_T_1, 7, 0) node _sourceC_req_ready_T = bits(sourceC_req.bankSum, 0, 0) node _sourceC_req_ready_T_1 = and(_sourceC_req_ready_T, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_2 = orr(_sourceC_req_ready_T_1) node _sourceC_req_ready_T_3 = eq(_sourceC_req_ready_T_2, UInt<1>(0h0)) node _sourceC_req_ready_T_4 = bits(sourceC_req.bankSum, 1, 1) node _sourceC_req_ready_T_5 = and(_sourceC_req_ready_T_4, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_6 = orr(_sourceC_req_ready_T_5) node _sourceC_req_ready_T_7 = eq(_sourceC_req_ready_T_6, UInt<1>(0h0)) node _sourceC_req_ready_T_8 = bits(sourceC_req.bankSum, 2, 2) node _sourceC_req_ready_T_9 = and(_sourceC_req_ready_T_8, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_10 = orr(_sourceC_req_ready_T_9) node _sourceC_req_ready_T_11 = eq(_sourceC_req_ready_T_10, UInt<1>(0h0)) node _sourceC_req_ready_T_12 = bits(sourceC_req.bankSum, 3, 3) node _sourceC_req_ready_T_13 = and(_sourceC_req_ready_T_12, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_14 = orr(_sourceC_req_ready_T_13) node _sourceC_req_ready_T_15 = eq(_sourceC_req_ready_T_14, UInt<1>(0h0)) node _sourceC_req_ready_T_16 = bits(sourceC_req.bankSum, 4, 4) node _sourceC_req_ready_T_17 = and(_sourceC_req_ready_T_16, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_18 = orr(_sourceC_req_ready_T_17) node _sourceC_req_ready_T_19 = eq(_sourceC_req_ready_T_18, UInt<1>(0h0)) node _sourceC_req_ready_T_20 = bits(sourceC_req.bankSum, 5, 5) node _sourceC_req_ready_T_21 = and(_sourceC_req_ready_T_20, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_22 = orr(_sourceC_req_ready_T_21) node _sourceC_req_ready_T_23 = eq(_sourceC_req_ready_T_22, UInt<1>(0h0)) node _sourceC_req_ready_T_24 = bits(sourceC_req.bankSum, 6, 6) node _sourceC_req_ready_T_25 = and(_sourceC_req_ready_T_24, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_26 = orr(_sourceC_req_ready_T_25) node _sourceC_req_ready_T_27 = eq(_sourceC_req_ready_T_26, UInt<1>(0h0)) node _sourceC_req_ready_T_28 = bits(sourceC_req.bankSum, 7, 7) node _sourceC_req_ready_T_29 = and(_sourceC_req_ready_T_28, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_30 = orr(_sourceC_req_ready_T_29) node _sourceC_req_ready_T_31 = eq(_sourceC_req_ready_T_30, UInt<1>(0h0)) node sourceC_req_ready_lo_lo = cat(_sourceC_req_ready_T_7, _sourceC_req_ready_T_3) node sourceC_req_ready_lo_hi = cat(_sourceC_req_ready_T_15, _sourceC_req_ready_T_11) node sourceC_req_ready_lo = cat(sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo) node sourceC_req_ready_hi_lo = cat(_sourceC_req_ready_T_23, _sourceC_req_ready_T_19) node sourceC_req_ready_hi_hi = cat(_sourceC_req_ready_T_31, _sourceC_req_ready_T_27) node sourceC_req_ready_hi = cat(sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo) node sourceC_req_ready = cat(sourceC_req_ready_hi, sourceC_req_ready_lo) node _sourceC_req_io_sourceC_adr_ready_T = bits(sourceC_req_a, 2, 0) node _sourceC_req_io_sourceC_adr_ready_T_1 = dshr(sourceC_req_ready, _sourceC_req_io_sourceC_adr_ready_T) node _sourceC_req_io_sourceC_adr_ready_T_2 = bits(_sourceC_req_io_sourceC_adr_ready_T_1, 0, 0) connect io.sourceC_adr.ready, _sourceC_req_io_sourceC_adr_ready_T_2 connect sourceC_req.wen, UInt<1>(0h0) node _sourceC_req_out_index_T = shr(sourceC_req_a, 3) connect sourceC_req.index, _sourceC_req_out_index_T node _sourceC_req_out_bankSel_T = bits(sourceC_req_select, 0, 0) node _sourceC_req_out_bankSel_T_1 = bits(sourceC_req_select, 1, 1) node _sourceC_req_out_bankSel_T_2 = bits(sourceC_req_select, 2, 2) node _sourceC_req_out_bankSel_T_3 = bits(sourceC_req_select, 3, 3) node _sourceC_req_out_bankSel_T_4 = bits(sourceC_req_select, 4, 4) node _sourceC_req_out_bankSel_T_5 = bits(sourceC_req_select, 5, 5) node _sourceC_req_out_bankSel_T_6 = bits(sourceC_req_select, 6, 6) node _sourceC_req_out_bankSel_T_7 = bits(sourceC_req_select, 7, 7) node sourceC_req_out_bankSel_lo_lo = cat(_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T) node sourceC_req_out_bankSel_lo_hi = cat(_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2) node sourceC_req_out_bankSel_lo = cat(sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo) node sourceC_req_out_bankSel_hi_lo = cat(_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4) node sourceC_req_out_bankSel_hi_hi = cat(_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6) node sourceC_req_out_bankSel_hi = cat(sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo) node _sourceC_req_out_bankSel_T_8 = cat(sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo) node _sourceC_req_out_bankSel_T_9 = bits(io.sourceC_adr.bits.mask, 0, 0) node _sourceC_req_out_bankSel_T_10 = mux(_sourceC_req_out_bankSel_T_9, UInt<8>(0hff), UInt<8>(0h0)) node _sourceC_req_out_bankSel_T_11 = and(_sourceC_req_out_bankSel_T_8, _sourceC_req_out_bankSel_T_10) node _sourceC_req_out_bankSel_T_12 = mux(io.sourceC_adr.valid, _sourceC_req_out_bankSel_T_11, UInt<1>(0h0)) connect sourceC_req.bankSel, _sourceC_req_out_bankSel_T_12 node _sourceC_req_out_bankEn_T = bits(sourceC_req_ready, 0, 0) node _sourceC_req_out_bankEn_T_1 = bits(sourceC_req_ready, 1, 1) node _sourceC_req_out_bankEn_T_2 = bits(sourceC_req_ready, 2, 2) node _sourceC_req_out_bankEn_T_3 = bits(sourceC_req_ready, 3, 3) node _sourceC_req_out_bankEn_T_4 = bits(sourceC_req_ready, 4, 4) node _sourceC_req_out_bankEn_T_5 = bits(sourceC_req_ready, 5, 5) node _sourceC_req_out_bankEn_T_6 = bits(sourceC_req_ready, 6, 6) node _sourceC_req_out_bankEn_T_7 = bits(sourceC_req_ready, 7, 7) node sourceC_req_out_bankEn_lo_lo = cat(_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T) node sourceC_req_out_bankEn_lo_hi = cat(_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2) node sourceC_req_out_bankEn_lo = cat(sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo) node sourceC_req_out_bankEn_hi_lo = cat(_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4) node sourceC_req_out_bankEn_hi_hi = cat(_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6) node sourceC_req_out_bankEn_hi = cat(sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo) node _sourceC_req_out_bankEn_T_8 = cat(sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo) node _sourceC_req_out_bankEn_T_9 = and(sourceC_req.bankSel, _sourceC_req_out_bankEn_T_8) node _sourceC_req_out_bankEn_T_10 = mux(io.sourceC_adr.bits.noop, UInt<1>(0h0), _sourceC_req_out_bankEn_T_9) connect sourceC_req.bankEn, _sourceC_req_out_bankEn_T_10 connect sourceC_req.data[0], UInt<64>(0h0) connect sourceC_req.data[1], UInt<64>(0h0) connect sourceC_req.data[2], UInt<64>(0h0) connect sourceC_req.data[3], UInt<64>(0h0) connect sourceC_req.data[4], UInt<64>(0h0) connect sourceC_req.data[5], UInt<64>(0h0) connect sourceC_req.data[6], UInt<64>(0h0) connect sourceC_req.data[7], UInt<64>(0h0) node sourceD_rreq_a_hi = cat(io.sourceD_radr.bits.way, io.sourceD_radr.bits.set) node sourceD_rreq_a = cat(sourceD_rreq_a_hi, io.sourceD_radr.bits.beat) wire sourceD_rreq : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_rreq_select_T = bits(sourceD_rreq_a, 1, 0) node sourceD_rreq_select_shiftAmount = bits(_sourceD_rreq_select_T, 1, 0) node _sourceD_rreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_rreq_select_shiftAmount) node sourceD_rreq_select = bits(_sourceD_rreq_select_T_1, 3, 0) node _sourceD_rreq_ready_T = bits(sourceD_rreq.bankSum, 1, 0) node _sourceD_rreq_ready_T_1 = and(_sourceD_rreq_ready_T, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_2 = orr(_sourceD_rreq_ready_T_1) node _sourceD_rreq_ready_T_3 = eq(_sourceD_rreq_ready_T_2, UInt<1>(0h0)) node _sourceD_rreq_ready_T_4 = bits(sourceD_rreq.bankSum, 3, 2) node _sourceD_rreq_ready_T_5 = and(_sourceD_rreq_ready_T_4, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_6 = orr(_sourceD_rreq_ready_T_5) node _sourceD_rreq_ready_T_7 = eq(_sourceD_rreq_ready_T_6, UInt<1>(0h0)) node _sourceD_rreq_ready_T_8 = bits(sourceD_rreq.bankSum, 5, 4) node _sourceD_rreq_ready_T_9 = and(_sourceD_rreq_ready_T_8, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_10 = orr(_sourceD_rreq_ready_T_9) node _sourceD_rreq_ready_T_11 = eq(_sourceD_rreq_ready_T_10, UInt<1>(0h0)) node _sourceD_rreq_ready_T_12 = bits(sourceD_rreq.bankSum, 7, 6) node _sourceD_rreq_ready_T_13 = and(_sourceD_rreq_ready_T_12, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_14 = orr(_sourceD_rreq_ready_T_13) node _sourceD_rreq_ready_T_15 = eq(_sourceD_rreq_ready_T_14, UInt<1>(0h0)) node sourceD_rreq_ready_lo = cat(_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3) node sourceD_rreq_ready_hi = cat(_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11) node sourceD_rreq_ready = cat(sourceD_rreq_ready_hi, sourceD_rreq_ready_lo) node _sourceD_rreq_io_sourceD_radr_ready_T = bits(sourceD_rreq_a, 1, 0) node _sourceD_rreq_io_sourceD_radr_ready_T_1 = dshr(sourceD_rreq_ready, _sourceD_rreq_io_sourceD_radr_ready_T) node _sourceD_rreq_io_sourceD_radr_ready_T_2 = bits(_sourceD_rreq_io_sourceD_radr_ready_T_1, 0, 0) connect io.sourceD_radr.ready, _sourceD_rreq_io_sourceD_radr_ready_T_2 connect sourceD_rreq.wen, UInt<1>(0h0) node _sourceD_rreq_out_index_T = shr(sourceD_rreq_a, 2) connect sourceD_rreq.index, _sourceD_rreq_out_index_T node _sourceD_rreq_out_bankSel_T = bits(sourceD_rreq_select, 0, 0) node _sourceD_rreq_out_bankSel_T_1 = bits(sourceD_rreq_select, 1, 1) node _sourceD_rreq_out_bankSel_T_2 = bits(sourceD_rreq_select, 2, 2) node _sourceD_rreq_out_bankSel_T_3 = bits(sourceD_rreq_select, 3, 3) node _sourceD_rreq_out_bankSel_T_4 = mux(_sourceD_rreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_5 = mux(_sourceD_rreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_6 = mux(_sourceD_rreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankSel_T_7 = mux(_sourceD_rreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankSel_lo = cat(_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4) node sourceD_rreq_out_bankSel_hi = cat(_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6) node _sourceD_rreq_out_bankSel_T_8 = cat(sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo) node _sourceD_rreq_out_bankSel_T_9 = cat(io.sourceD_radr.bits.mask, io.sourceD_radr.bits.mask) node _sourceD_rreq_out_bankSel_T_10 = cat(_sourceD_rreq_out_bankSel_T_9, _sourceD_rreq_out_bankSel_T_9) node _sourceD_rreq_out_bankSel_T_11 = and(_sourceD_rreq_out_bankSel_T_8, _sourceD_rreq_out_bankSel_T_10) node _sourceD_rreq_out_bankSel_T_12 = mux(io.sourceD_radr.valid, _sourceD_rreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_rreq.bankSel, _sourceD_rreq_out_bankSel_T_12 node _sourceD_rreq_out_bankEn_T = bits(sourceD_rreq_ready, 0, 0) node _sourceD_rreq_out_bankEn_T_1 = bits(sourceD_rreq_ready, 1, 1) node _sourceD_rreq_out_bankEn_T_2 = bits(sourceD_rreq_ready, 2, 2) node _sourceD_rreq_out_bankEn_T_3 = bits(sourceD_rreq_ready, 3, 3) node _sourceD_rreq_out_bankEn_T_4 = mux(_sourceD_rreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_5 = mux(_sourceD_rreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_6 = mux(_sourceD_rreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_rreq_out_bankEn_T_7 = mux(_sourceD_rreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_rreq_out_bankEn_lo = cat(_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4) node sourceD_rreq_out_bankEn_hi = cat(_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6) node _sourceD_rreq_out_bankEn_T_8 = cat(sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo) node _sourceD_rreq_out_bankEn_T_9 = and(sourceD_rreq.bankSel, _sourceD_rreq_out_bankEn_T_8) node _sourceD_rreq_out_bankEn_T_10 = mux(io.sourceD_radr.bits.noop, UInt<1>(0h0), _sourceD_rreq_out_bankEn_T_9) connect sourceD_rreq.bankEn, _sourceD_rreq_out_bankEn_T_10 connect sourceD_rreq.data[0], UInt<64>(0h0) connect sourceD_rreq.data[1], UInt<64>(0h0) connect sourceD_rreq.data[2], UInt<64>(0h0) connect sourceD_rreq.data[3], UInt<64>(0h0) connect sourceD_rreq.data[4], UInt<64>(0h0) connect sourceD_rreq.data[5], UInt<64>(0h0) connect sourceD_rreq.data[6], UInt<64>(0h0) connect sourceD_rreq.data[7], UInt<64>(0h0) node sourceD_wreq_words_0 = bits(io.sourceD_wdat.data, 63, 0) node sourceD_wreq_words_1 = bits(io.sourceD_wdat.data, 127, 64) node sourceD_wreq_a_hi = cat(io.sourceD_wadr.bits.way, io.sourceD_wadr.bits.set) node sourceD_wreq_a = cat(sourceD_wreq_a_hi, io.sourceD_wadr.bits.beat) wire sourceD_wreq : { wen : UInt<1>, index : UInt<13>, bankSel : UInt<8>, bankSum : UInt<8>, bankEn : UInt<8>, data : UInt<64>[8]} node _sourceD_wreq_select_T = bits(sourceD_wreq_a, 1, 0) node sourceD_wreq_select_shiftAmount = bits(_sourceD_wreq_select_T, 1, 0) node _sourceD_wreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_wreq_select_shiftAmount) node sourceD_wreq_select = bits(_sourceD_wreq_select_T_1, 3, 0) node _sourceD_wreq_ready_T = bits(sourceD_wreq.bankSum, 1, 0) node _sourceD_wreq_ready_T_1 = and(_sourceD_wreq_ready_T, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_2 = orr(_sourceD_wreq_ready_T_1) node _sourceD_wreq_ready_T_3 = eq(_sourceD_wreq_ready_T_2, UInt<1>(0h0)) node _sourceD_wreq_ready_T_4 = bits(sourceD_wreq.bankSum, 3, 2) node _sourceD_wreq_ready_T_5 = and(_sourceD_wreq_ready_T_4, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_6 = orr(_sourceD_wreq_ready_T_5) node _sourceD_wreq_ready_T_7 = eq(_sourceD_wreq_ready_T_6, UInt<1>(0h0)) node _sourceD_wreq_ready_T_8 = bits(sourceD_wreq.bankSum, 5, 4) node _sourceD_wreq_ready_T_9 = and(_sourceD_wreq_ready_T_8, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_10 = orr(_sourceD_wreq_ready_T_9) node _sourceD_wreq_ready_T_11 = eq(_sourceD_wreq_ready_T_10, UInt<1>(0h0)) node _sourceD_wreq_ready_T_12 = bits(sourceD_wreq.bankSum, 7, 6) node _sourceD_wreq_ready_T_13 = and(_sourceD_wreq_ready_T_12, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_14 = orr(_sourceD_wreq_ready_T_13) node _sourceD_wreq_ready_T_15 = eq(_sourceD_wreq_ready_T_14, UInt<1>(0h0)) node sourceD_wreq_ready_lo = cat(_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3) node sourceD_wreq_ready_hi = cat(_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11) node sourceD_wreq_ready = cat(sourceD_wreq_ready_hi, sourceD_wreq_ready_lo) node _sourceD_wreq_io_sourceD_wadr_ready_T = bits(sourceD_wreq_a, 1, 0) node _sourceD_wreq_io_sourceD_wadr_ready_T_1 = dshr(sourceD_wreq_ready, _sourceD_wreq_io_sourceD_wadr_ready_T) node _sourceD_wreq_io_sourceD_wadr_ready_T_2 = bits(_sourceD_wreq_io_sourceD_wadr_ready_T_1, 0, 0) connect io.sourceD_wadr.ready, _sourceD_wreq_io_sourceD_wadr_ready_T_2 connect sourceD_wreq.wen, UInt<1>(0h1) node _sourceD_wreq_out_index_T = shr(sourceD_wreq_a, 2) connect sourceD_wreq.index, _sourceD_wreq_out_index_T node _sourceD_wreq_out_bankSel_T = bits(sourceD_wreq_select, 0, 0) node _sourceD_wreq_out_bankSel_T_1 = bits(sourceD_wreq_select, 1, 1) node _sourceD_wreq_out_bankSel_T_2 = bits(sourceD_wreq_select, 2, 2) node _sourceD_wreq_out_bankSel_T_3 = bits(sourceD_wreq_select, 3, 3) node _sourceD_wreq_out_bankSel_T_4 = mux(_sourceD_wreq_out_bankSel_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_5 = mux(_sourceD_wreq_out_bankSel_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_6 = mux(_sourceD_wreq_out_bankSel_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankSel_T_7 = mux(_sourceD_wreq_out_bankSel_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankSel_lo = cat(_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4) node sourceD_wreq_out_bankSel_hi = cat(_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6) node _sourceD_wreq_out_bankSel_T_8 = cat(sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo) node _sourceD_wreq_out_bankSel_T_9 = cat(io.sourceD_wadr.bits.mask, io.sourceD_wadr.bits.mask) node _sourceD_wreq_out_bankSel_T_10 = cat(_sourceD_wreq_out_bankSel_T_9, _sourceD_wreq_out_bankSel_T_9) node _sourceD_wreq_out_bankSel_T_11 = and(_sourceD_wreq_out_bankSel_T_8, _sourceD_wreq_out_bankSel_T_10) node _sourceD_wreq_out_bankSel_T_12 = mux(io.sourceD_wadr.valid, _sourceD_wreq_out_bankSel_T_11, UInt<1>(0h0)) connect sourceD_wreq.bankSel, _sourceD_wreq_out_bankSel_T_12 node _sourceD_wreq_out_bankEn_T = bits(sourceD_wreq_ready, 0, 0) node _sourceD_wreq_out_bankEn_T_1 = bits(sourceD_wreq_ready, 1, 1) node _sourceD_wreq_out_bankEn_T_2 = bits(sourceD_wreq_ready, 2, 2) node _sourceD_wreq_out_bankEn_T_3 = bits(sourceD_wreq_ready, 3, 3) node _sourceD_wreq_out_bankEn_T_4 = mux(_sourceD_wreq_out_bankEn_T, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_5 = mux(_sourceD_wreq_out_bankEn_T_1, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_6 = mux(_sourceD_wreq_out_bankEn_T_2, UInt<2>(0h3), UInt<2>(0h0)) node _sourceD_wreq_out_bankEn_T_7 = mux(_sourceD_wreq_out_bankEn_T_3, UInt<2>(0h3), UInt<2>(0h0)) node sourceD_wreq_out_bankEn_lo = cat(_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4) node sourceD_wreq_out_bankEn_hi = cat(_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6) node _sourceD_wreq_out_bankEn_T_8 = cat(sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo) node _sourceD_wreq_out_bankEn_T_9 = and(sourceD_wreq.bankSel, _sourceD_wreq_out_bankEn_T_8) node _sourceD_wreq_out_bankEn_T_10 = mux(io.sourceD_wadr.bits.noop, UInt<1>(0h0), _sourceD_wreq_out_bankEn_T_9) connect sourceD_wreq.bankEn, _sourceD_wreq_out_bankEn_T_10 connect sourceD_wreq.data[0], sourceD_wreq_words_0 connect sourceD_wreq.data[1], sourceD_wreq_words_1 connect sourceD_wreq.data[2], sourceD_wreq_words_0 connect sourceD_wreq.data[3], sourceD_wreq_words_1 connect sourceD_wreq.data[4], sourceD_wreq_words_0 connect sourceD_wreq.data[5], sourceD_wreq_words_1 connect sourceD_wreq.data[6], sourceD_wreq_words_0 connect sourceD_wreq.data[7], sourceD_wreq_words_1 connect sinkC_req.bankSum, UInt<1>(0h0) node _T = or(sinkC_req.bankSel, UInt<1>(0h0)) connect sourceC_req.bankSum, _T node _T_1 = or(sourceC_req.bankSel, _T) connect sinkD_req.bankSum, _T_1 node _T_2 = or(sinkD_req.bankSel, _T_1) connect sourceD_wreq.bankSum, _T_2 node _T_3 = or(sourceD_wreq.bankSel, _T_2) connect sourceD_rreq.bankSum, _T_3 node _T_4 = or(sourceD_rreq.bankSel, _T_3) node _regout_en_T = bits(sinkC_req.bankEn, 0, 0) node _regout_en_T_1 = bits(sourceC_req.bankEn, 0, 0) node _regout_en_T_2 = bits(sinkD_req.bankEn, 0, 0) node _regout_en_T_3 = bits(sourceD_wreq.bankEn, 0, 0) node _regout_en_T_4 = bits(sourceD_rreq.bankEn, 0, 0) node _regout_en_T_5 = or(_regout_en_T, _regout_en_T_1) node _regout_en_T_6 = or(_regout_en_T_5, _regout_en_T_2) node _regout_en_T_7 = or(_regout_en_T_6, _regout_en_T_3) node regout_en = or(_regout_en_T_7, _regout_en_T_4) node regout_sel_0 = bits(sinkC_req.bankSel, 0, 0) node regout_sel_1 = bits(sourceC_req.bankSel, 0, 0) node regout_sel_2 = bits(sinkD_req.bankSel, 0, 0) node regout_sel_3 = bits(sourceD_wreq.bankSel, 0, 0) node regout_sel_4 = bits(sourceD_rreq.bankSel, 0, 0) node _regout_wen_T = mux(regout_sel_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_1 = mux(regout_sel_2, sinkD_req.wen, _regout_wen_T) node _regout_wen_T_2 = mux(regout_sel_1, sourceC_req.wen, _regout_wen_T_1) node regout_wen = mux(regout_sel_0, sinkC_req.wen, _regout_wen_T_2) node _regout_idx_T = mux(regout_sel_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_1 = mux(regout_sel_2, sinkD_req.index, _regout_idx_T) node _regout_idx_T_2 = mux(regout_sel_1, sourceC_req.index, _regout_idx_T_1) node regout_idx = mux(regout_sel_0, sinkC_req.index, _regout_idx_T_2) node _regout_data_T = mux(regout_sel_3, sourceD_wreq.data[0], sourceD_rreq.data[0]) node _regout_data_T_1 = mux(regout_sel_2, sinkD_req.data[0], _regout_data_T) node _regout_data_T_2 = mux(regout_sel_1, sourceC_req.data[0], _regout_data_T_1) node regout_data = mux(regout_sel_0, sinkC_req.data[0], _regout_data_T_2) node _regout_T = and(regout_wen, regout_en) when _regout_T : write mport regout_MPORT = cc_banks_0[regout_idx], clock connect regout_MPORT, regout_data node _regout_T_1 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_2 = and(_regout_T_1, regout_en) wire _regout_WIRE : UInt<13> invalidate _regout_WIRE when _regout_T_2 : connect _regout_WIRE, regout_idx read mport regout_MPORT_1 = cc_banks_0[_regout_WIRE], clock node _regout_T_3 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_4 = and(_regout_T_3, regout_en) reg regout_REG : UInt<1>, clock connect regout_REG, _regout_T_4 reg regout_r : UInt<64>, clock when regout_REG : connect regout_r, regout_MPORT_1 node _regout_en_T_8 = bits(sinkC_req.bankEn, 1, 1) node _regout_en_T_9 = bits(sourceC_req.bankEn, 1, 1) node _regout_en_T_10 = bits(sinkD_req.bankEn, 1, 1) node _regout_en_T_11 = bits(sourceD_wreq.bankEn, 1, 1) node _regout_en_T_12 = bits(sourceD_rreq.bankEn, 1, 1) node _regout_en_T_13 = or(_regout_en_T_8, _regout_en_T_9) node _regout_en_T_14 = or(_regout_en_T_13, _regout_en_T_10) node _regout_en_T_15 = or(_regout_en_T_14, _regout_en_T_11) node regout_en_1 = or(_regout_en_T_15, _regout_en_T_12) node regout_sel_0_1 = bits(sinkC_req.bankSel, 1, 1) node regout_sel_1_1 = bits(sourceC_req.bankSel, 1, 1) node regout_sel_2_1 = bits(sinkD_req.bankSel, 1, 1) node regout_sel_3_1 = bits(sourceD_wreq.bankSel, 1, 1) node regout_sel_4_1 = bits(sourceD_rreq.bankSel, 1, 1) node _regout_wen_T_3 = mux(regout_sel_3_1, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_4 = mux(regout_sel_2_1, sinkD_req.wen, _regout_wen_T_3) node _regout_wen_T_5 = mux(regout_sel_1_1, sourceC_req.wen, _regout_wen_T_4) node regout_wen_1 = mux(regout_sel_0_1, sinkC_req.wen, _regout_wen_T_5) node _regout_idx_T_3 = mux(regout_sel_3_1, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_4 = mux(regout_sel_2_1, sinkD_req.index, _regout_idx_T_3) node _regout_idx_T_5 = mux(regout_sel_1_1, sourceC_req.index, _regout_idx_T_4) node regout_idx_1 = mux(regout_sel_0_1, sinkC_req.index, _regout_idx_T_5) node _regout_data_T_3 = mux(regout_sel_3_1, sourceD_wreq.data[1], sourceD_rreq.data[1]) node _regout_data_T_4 = mux(regout_sel_2_1, sinkD_req.data[1], _regout_data_T_3) node _regout_data_T_5 = mux(regout_sel_1_1, sourceC_req.data[1], _regout_data_T_4) node regout_data_1 = mux(regout_sel_0_1, sinkC_req.data[1], _regout_data_T_5) node _regout_T_5 = and(regout_wen_1, regout_en_1) when _regout_T_5 : write mport regout_MPORT_2 = cc_banks_1[regout_idx_1], clock connect regout_MPORT_2, regout_data_1 node _regout_T_6 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_7 = and(_regout_T_6, regout_en_1) wire _regout_WIRE_1 : UInt<13> invalidate _regout_WIRE_1 when _regout_T_7 : connect _regout_WIRE_1, regout_idx_1 read mport regout_MPORT_3 = cc_banks_1[_regout_WIRE_1], clock node _regout_T_8 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_9 = and(_regout_T_8, regout_en_1) reg regout_REG_1 : UInt<1>, clock connect regout_REG_1, _regout_T_9 reg regout_r_1 : UInt<64>, clock when regout_REG_1 : connect regout_r_1, regout_MPORT_3 node _regout_en_T_16 = bits(sinkC_req.bankEn, 2, 2) node _regout_en_T_17 = bits(sourceC_req.bankEn, 2, 2) node _regout_en_T_18 = bits(sinkD_req.bankEn, 2, 2) node _regout_en_T_19 = bits(sourceD_wreq.bankEn, 2, 2) node _regout_en_T_20 = bits(sourceD_rreq.bankEn, 2, 2) node _regout_en_T_21 = or(_regout_en_T_16, _regout_en_T_17) node _regout_en_T_22 = or(_regout_en_T_21, _regout_en_T_18) node _regout_en_T_23 = or(_regout_en_T_22, _regout_en_T_19) node regout_en_2 = or(_regout_en_T_23, _regout_en_T_20) node regout_sel_0_2 = bits(sinkC_req.bankSel, 2, 2) node regout_sel_1_2 = bits(sourceC_req.bankSel, 2, 2) node regout_sel_2_2 = bits(sinkD_req.bankSel, 2, 2) node regout_sel_3_2 = bits(sourceD_wreq.bankSel, 2, 2) node regout_sel_4_2 = bits(sourceD_rreq.bankSel, 2, 2) node _regout_wen_T_6 = mux(regout_sel_3_2, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_7 = mux(regout_sel_2_2, sinkD_req.wen, _regout_wen_T_6) node _regout_wen_T_8 = mux(regout_sel_1_2, sourceC_req.wen, _regout_wen_T_7) node regout_wen_2 = mux(regout_sel_0_2, sinkC_req.wen, _regout_wen_T_8) node _regout_idx_T_6 = mux(regout_sel_3_2, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_7 = mux(regout_sel_2_2, sinkD_req.index, _regout_idx_T_6) node _regout_idx_T_8 = mux(regout_sel_1_2, sourceC_req.index, _regout_idx_T_7) node regout_idx_2 = mux(regout_sel_0_2, sinkC_req.index, _regout_idx_T_8) node _regout_data_T_6 = mux(regout_sel_3_2, sourceD_wreq.data[2], sourceD_rreq.data[2]) node _regout_data_T_7 = mux(regout_sel_2_2, sinkD_req.data[2], _regout_data_T_6) node _regout_data_T_8 = mux(regout_sel_1_2, sourceC_req.data[2], _regout_data_T_7) node regout_data_2 = mux(regout_sel_0_2, sinkC_req.data[2], _regout_data_T_8) node _regout_T_10 = and(regout_wen_2, regout_en_2) when _regout_T_10 : write mport regout_MPORT_4 = cc_banks_2[regout_idx_2], clock connect regout_MPORT_4, regout_data_2 node _regout_T_11 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_12 = and(_regout_T_11, regout_en_2) wire _regout_WIRE_2 : UInt<13> invalidate _regout_WIRE_2 when _regout_T_12 : connect _regout_WIRE_2, regout_idx_2 read mport regout_MPORT_5 = cc_banks_2[_regout_WIRE_2], clock node _regout_T_13 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_14 = and(_regout_T_13, regout_en_2) reg regout_REG_2 : UInt<1>, clock connect regout_REG_2, _regout_T_14 reg regout_r_2 : UInt<64>, clock when regout_REG_2 : connect regout_r_2, regout_MPORT_5 node _regout_en_T_24 = bits(sinkC_req.bankEn, 3, 3) node _regout_en_T_25 = bits(sourceC_req.bankEn, 3, 3) node _regout_en_T_26 = bits(sinkD_req.bankEn, 3, 3) node _regout_en_T_27 = bits(sourceD_wreq.bankEn, 3, 3) node _regout_en_T_28 = bits(sourceD_rreq.bankEn, 3, 3) node _regout_en_T_29 = or(_regout_en_T_24, _regout_en_T_25) node _regout_en_T_30 = or(_regout_en_T_29, _regout_en_T_26) node _regout_en_T_31 = or(_regout_en_T_30, _regout_en_T_27) node regout_en_3 = or(_regout_en_T_31, _regout_en_T_28) node regout_sel_0_3 = bits(sinkC_req.bankSel, 3, 3) node regout_sel_1_3 = bits(sourceC_req.bankSel, 3, 3) node regout_sel_2_3 = bits(sinkD_req.bankSel, 3, 3) node regout_sel_3_3 = bits(sourceD_wreq.bankSel, 3, 3) node regout_sel_4_3 = bits(sourceD_rreq.bankSel, 3, 3) node _regout_wen_T_9 = mux(regout_sel_3_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_10 = mux(regout_sel_2_3, sinkD_req.wen, _regout_wen_T_9) node _regout_wen_T_11 = mux(regout_sel_1_3, sourceC_req.wen, _regout_wen_T_10) node regout_wen_3 = mux(regout_sel_0_3, sinkC_req.wen, _regout_wen_T_11) node _regout_idx_T_9 = mux(regout_sel_3_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_10 = mux(regout_sel_2_3, sinkD_req.index, _regout_idx_T_9) node _regout_idx_T_11 = mux(regout_sel_1_3, sourceC_req.index, _regout_idx_T_10) node regout_idx_3 = mux(regout_sel_0_3, sinkC_req.index, _regout_idx_T_11) node _regout_data_T_9 = mux(regout_sel_3_3, sourceD_wreq.data[3], sourceD_rreq.data[3]) node _regout_data_T_10 = mux(regout_sel_2_3, sinkD_req.data[3], _regout_data_T_9) node _regout_data_T_11 = mux(regout_sel_1_3, sourceC_req.data[3], _regout_data_T_10) node regout_data_3 = mux(regout_sel_0_3, sinkC_req.data[3], _regout_data_T_11) node _regout_T_15 = and(regout_wen_3, regout_en_3) when _regout_T_15 : write mport regout_MPORT_6 = cc_banks_3[regout_idx_3], clock connect regout_MPORT_6, regout_data_3 node _regout_T_16 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_17 = and(_regout_T_16, regout_en_3) wire _regout_WIRE_3 : UInt<13> invalidate _regout_WIRE_3 when _regout_T_17 : connect _regout_WIRE_3, regout_idx_3 read mport regout_MPORT_7 = cc_banks_3[_regout_WIRE_3], clock node _regout_T_18 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_19 = and(_regout_T_18, regout_en_3) reg regout_REG_3 : UInt<1>, clock connect regout_REG_3, _regout_T_19 reg regout_r_3 : UInt<64>, clock when regout_REG_3 : connect regout_r_3, regout_MPORT_7 node _regout_en_T_32 = bits(sinkC_req.bankEn, 4, 4) node _regout_en_T_33 = bits(sourceC_req.bankEn, 4, 4) node _regout_en_T_34 = bits(sinkD_req.bankEn, 4, 4) node _regout_en_T_35 = bits(sourceD_wreq.bankEn, 4, 4) node _regout_en_T_36 = bits(sourceD_rreq.bankEn, 4, 4) node _regout_en_T_37 = or(_regout_en_T_32, _regout_en_T_33) node _regout_en_T_38 = or(_regout_en_T_37, _regout_en_T_34) node _regout_en_T_39 = or(_regout_en_T_38, _regout_en_T_35) node regout_en_4 = or(_regout_en_T_39, _regout_en_T_36) node regout_sel_0_4 = bits(sinkC_req.bankSel, 4, 4) node regout_sel_1_4 = bits(sourceC_req.bankSel, 4, 4) node regout_sel_2_4 = bits(sinkD_req.bankSel, 4, 4) node regout_sel_3_4 = bits(sourceD_wreq.bankSel, 4, 4) node regout_sel_4_4 = bits(sourceD_rreq.bankSel, 4, 4) node _regout_wen_T_12 = mux(regout_sel_3_4, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_13 = mux(regout_sel_2_4, sinkD_req.wen, _regout_wen_T_12) node _regout_wen_T_14 = mux(regout_sel_1_4, sourceC_req.wen, _regout_wen_T_13) node regout_wen_4 = mux(regout_sel_0_4, sinkC_req.wen, _regout_wen_T_14) node _regout_idx_T_12 = mux(regout_sel_3_4, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_13 = mux(regout_sel_2_4, sinkD_req.index, _regout_idx_T_12) node _regout_idx_T_14 = mux(regout_sel_1_4, sourceC_req.index, _regout_idx_T_13) node regout_idx_4 = mux(regout_sel_0_4, sinkC_req.index, _regout_idx_T_14) node _regout_data_T_12 = mux(regout_sel_3_4, sourceD_wreq.data[4], sourceD_rreq.data[4]) node _regout_data_T_13 = mux(regout_sel_2_4, sinkD_req.data[4], _regout_data_T_12) node _regout_data_T_14 = mux(regout_sel_1_4, sourceC_req.data[4], _regout_data_T_13) node regout_data_4 = mux(regout_sel_0_4, sinkC_req.data[4], _regout_data_T_14) node _regout_T_20 = and(regout_wen_4, regout_en_4) when _regout_T_20 : write mport regout_MPORT_8 = cc_banks_4[regout_idx_4], clock connect regout_MPORT_8, regout_data_4 node _regout_T_21 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_22 = and(_regout_T_21, regout_en_4) wire _regout_WIRE_4 : UInt<13> invalidate _regout_WIRE_4 when _regout_T_22 : connect _regout_WIRE_4, regout_idx_4 read mport regout_MPORT_9 = cc_banks_4[_regout_WIRE_4], clock node _regout_T_23 = eq(regout_wen_4, UInt<1>(0h0)) node _regout_T_24 = and(_regout_T_23, regout_en_4) reg regout_REG_4 : UInt<1>, clock connect regout_REG_4, _regout_T_24 reg regout_r_4 : UInt<64>, clock when regout_REG_4 : connect regout_r_4, regout_MPORT_9 node _regout_en_T_40 = bits(sinkC_req.bankEn, 5, 5) node _regout_en_T_41 = bits(sourceC_req.bankEn, 5, 5) node _regout_en_T_42 = bits(sinkD_req.bankEn, 5, 5) node _regout_en_T_43 = bits(sourceD_wreq.bankEn, 5, 5) node _regout_en_T_44 = bits(sourceD_rreq.bankEn, 5, 5) node _regout_en_T_45 = or(_regout_en_T_40, _regout_en_T_41) node _regout_en_T_46 = or(_regout_en_T_45, _regout_en_T_42) node _regout_en_T_47 = or(_regout_en_T_46, _regout_en_T_43) node regout_en_5 = or(_regout_en_T_47, _regout_en_T_44) node regout_sel_0_5 = bits(sinkC_req.bankSel, 5, 5) node regout_sel_1_5 = bits(sourceC_req.bankSel, 5, 5) node regout_sel_2_5 = bits(sinkD_req.bankSel, 5, 5) node regout_sel_3_5 = bits(sourceD_wreq.bankSel, 5, 5) node regout_sel_4_5 = bits(sourceD_rreq.bankSel, 5, 5) node _regout_wen_T_15 = mux(regout_sel_3_5, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_16 = mux(regout_sel_2_5, sinkD_req.wen, _regout_wen_T_15) node _regout_wen_T_17 = mux(regout_sel_1_5, sourceC_req.wen, _regout_wen_T_16) node regout_wen_5 = mux(regout_sel_0_5, sinkC_req.wen, _regout_wen_T_17) node _regout_idx_T_15 = mux(regout_sel_3_5, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_16 = mux(regout_sel_2_5, sinkD_req.index, _regout_idx_T_15) node _regout_idx_T_17 = mux(regout_sel_1_5, sourceC_req.index, _regout_idx_T_16) node regout_idx_5 = mux(regout_sel_0_5, sinkC_req.index, _regout_idx_T_17) node _regout_data_T_15 = mux(regout_sel_3_5, sourceD_wreq.data[5], sourceD_rreq.data[5]) node _regout_data_T_16 = mux(regout_sel_2_5, sinkD_req.data[5], _regout_data_T_15) node _regout_data_T_17 = mux(regout_sel_1_5, sourceC_req.data[5], _regout_data_T_16) node regout_data_5 = mux(regout_sel_0_5, sinkC_req.data[5], _regout_data_T_17) node _regout_T_25 = and(regout_wen_5, regout_en_5) when _regout_T_25 : write mport regout_MPORT_10 = cc_banks_5[regout_idx_5], clock connect regout_MPORT_10, regout_data_5 node _regout_T_26 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_27 = and(_regout_T_26, regout_en_5) wire _regout_WIRE_5 : UInt<13> invalidate _regout_WIRE_5 when _regout_T_27 : connect _regout_WIRE_5, regout_idx_5 read mport regout_MPORT_11 = cc_banks_5[_regout_WIRE_5], clock node _regout_T_28 = eq(regout_wen_5, UInt<1>(0h0)) node _regout_T_29 = and(_regout_T_28, regout_en_5) reg regout_REG_5 : UInt<1>, clock connect regout_REG_5, _regout_T_29 reg regout_r_5 : UInt<64>, clock when regout_REG_5 : connect regout_r_5, regout_MPORT_11 node _regout_en_T_48 = bits(sinkC_req.bankEn, 6, 6) node _regout_en_T_49 = bits(sourceC_req.bankEn, 6, 6) node _regout_en_T_50 = bits(sinkD_req.bankEn, 6, 6) node _regout_en_T_51 = bits(sourceD_wreq.bankEn, 6, 6) node _regout_en_T_52 = bits(sourceD_rreq.bankEn, 6, 6) node _regout_en_T_53 = or(_regout_en_T_48, _regout_en_T_49) node _regout_en_T_54 = or(_regout_en_T_53, _regout_en_T_50) node _regout_en_T_55 = or(_regout_en_T_54, _regout_en_T_51) node regout_en_6 = or(_regout_en_T_55, _regout_en_T_52) node regout_sel_0_6 = bits(sinkC_req.bankSel, 6, 6) node regout_sel_1_6 = bits(sourceC_req.bankSel, 6, 6) node regout_sel_2_6 = bits(sinkD_req.bankSel, 6, 6) node regout_sel_3_6 = bits(sourceD_wreq.bankSel, 6, 6) node regout_sel_4_6 = bits(sourceD_rreq.bankSel, 6, 6) node _regout_wen_T_18 = mux(regout_sel_3_6, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_19 = mux(regout_sel_2_6, sinkD_req.wen, _regout_wen_T_18) node _regout_wen_T_20 = mux(regout_sel_1_6, sourceC_req.wen, _regout_wen_T_19) node regout_wen_6 = mux(regout_sel_0_6, sinkC_req.wen, _regout_wen_T_20) node _regout_idx_T_18 = mux(regout_sel_3_6, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_19 = mux(regout_sel_2_6, sinkD_req.index, _regout_idx_T_18) node _regout_idx_T_20 = mux(regout_sel_1_6, sourceC_req.index, _regout_idx_T_19) node regout_idx_6 = mux(regout_sel_0_6, sinkC_req.index, _regout_idx_T_20) node _regout_data_T_18 = mux(regout_sel_3_6, sourceD_wreq.data[6], sourceD_rreq.data[6]) node _regout_data_T_19 = mux(regout_sel_2_6, sinkD_req.data[6], _regout_data_T_18) node _regout_data_T_20 = mux(regout_sel_1_6, sourceC_req.data[6], _regout_data_T_19) node regout_data_6 = mux(regout_sel_0_6, sinkC_req.data[6], _regout_data_T_20) node _regout_T_30 = and(regout_wen_6, regout_en_6) when _regout_T_30 : write mport regout_MPORT_12 = cc_banks_6[regout_idx_6], clock connect regout_MPORT_12, regout_data_6 node _regout_T_31 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_32 = and(_regout_T_31, regout_en_6) wire _regout_WIRE_6 : UInt<13> invalidate _regout_WIRE_6 when _regout_T_32 : connect _regout_WIRE_6, regout_idx_6 read mport regout_MPORT_13 = cc_banks_6[_regout_WIRE_6], clock node _regout_T_33 = eq(regout_wen_6, UInt<1>(0h0)) node _regout_T_34 = and(_regout_T_33, regout_en_6) reg regout_REG_6 : UInt<1>, clock connect regout_REG_6, _regout_T_34 reg regout_r_6 : UInt<64>, clock when regout_REG_6 : connect regout_r_6, regout_MPORT_13 node _regout_en_T_56 = bits(sinkC_req.bankEn, 7, 7) node _regout_en_T_57 = bits(sourceC_req.bankEn, 7, 7) node _regout_en_T_58 = bits(sinkD_req.bankEn, 7, 7) node _regout_en_T_59 = bits(sourceD_wreq.bankEn, 7, 7) node _regout_en_T_60 = bits(sourceD_rreq.bankEn, 7, 7) node _regout_en_T_61 = or(_regout_en_T_56, _regout_en_T_57) node _regout_en_T_62 = or(_regout_en_T_61, _regout_en_T_58) node _regout_en_T_63 = or(_regout_en_T_62, _regout_en_T_59) node regout_en_7 = or(_regout_en_T_63, _regout_en_T_60) node regout_sel_0_7 = bits(sinkC_req.bankSel, 7, 7) node regout_sel_1_7 = bits(sourceC_req.bankSel, 7, 7) node regout_sel_2_7 = bits(sinkD_req.bankSel, 7, 7) node regout_sel_3_7 = bits(sourceD_wreq.bankSel, 7, 7) node regout_sel_4_7 = bits(sourceD_rreq.bankSel, 7, 7) node _regout_wen_T_21 = mux(regout_sel_3_7, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_22 = mux(regout_sel_2_7, sinkD_req.wen, _regout_wen_T_21) node _regout_wen_T_23 = mux(regout_sel_1_7, sourceC_req.wen, _regout_wen_T_22) node regout_wen_7 = mux(regout_sel_0_7, sinkC_req.wen, _regout_wen_T_23) node _regout_idx_T_21 = mux(regout_sel_3_7, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_22 = mux(regout_sel_2_7, sinkD_req.index, _regout_idx_T_21) node _regout_idx_T_23 = mux(regout_sel_1_7, sourceC_req.index, _regout_idx_T_22) node regout_idx_7 = mux(regout_sel_0_7, sinkC_req.index, _regout_idx_T_23) node _regout_data_T_21 = mux(regout_sel_3_7, sourceD_wreq.data[7], sourceD_rreq.data[7]) node _regout_data_T_22 = mux(regout_sel_2_7, sinkD_req.data[7], _regout_data_T_21) node _regout_data_T_23 = mux(regout_sel_1_7, sourceC_req.data[7], _regout_data_T_22) node regout_data_7 = mux(regout_sel_0_7, sinkC_req.data[7], _regout_data_T_23) node _regout_T_35 = and(regout_wen_7, regout_en_7) when _regout_T_35 : write mport regout_MPORT_14 = cc_banks_7[regout_idx_7], clock connect regout_MPORT_14, regout_data_7 node _regout_T_36 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_37 = and(_regout_T_36, regout_en_7) wire _regout_WIRE_7 : UInt<13> invalidate _regout_WIRE_7 when _regout_T_37 : connect _regout_WIRE_7, regout_idx_7 read mport regout_MPORT_15 = cc_banks_7[_regout_WIRE_7], clock node _regout_T_38 = eq(regout_wen_7, UInt<1>(0h0)) node _regout_T_39 = and(_regout_T_38, regout_en_7) reg regout_REG_7 : UInt<1>, clock connect regout_REG_7, _regout_T_39 reg regout_r_7 : UInt<64>, clock when regout_REG_7 : connect regout_r_7, regout_MPORT_15 wire regout : UInt<64>[8] connect regout[0], regout_r connect regout[1], regout_r_1 connect regout[2], regout_r_2 connect regout[3], regout_r_3 connect regout[4], regout_r_4 connect regout[5], regout_r_5 connect regout[6], regout_r_6 connect regout[7], regout_r_7 reg regsel_sourceC_REG : UInt, clock connect regsel_sourceC_REG, sourceC_req.bankEn reg regsel_sourceC : UInt, clock connect regsel_sourceC, regsel_sourceC_REG reg regsel_sourceD_REG : UInt, clock connect regsel_sourceD_REG, sourceD_rreq.bankEn reg regsel_sourceD : UInt, clock connect regsel_sourceD, regsel_sourceD_REG node _decodeC_T = bits(regsel_sourceC, 0, 0) node _decodeC_T_1 = mux(_decodeC_T, regout[0], UInt<1>(0h0)) node _decodeC_T_2 = bits(regsel_sourceC, 1, 1) node _decodeC_T_3 = mux(_decodeC_T_2, regout[1], UInt<1>(0h0)) node _decodeC_T_4 = bits(regsel_sourceC, 2, 2) node _decodeC_T_5 = mux(_decodeC_T_4, regout[2], UInt<1>(0h0)) node _decodeC_T_6 = bits(regsel_sourceC, 3, 3) node _decodeC_T_7 = mux(_decodeC_T_6, regout[3], UInt<1>(0h0)) node _decodeC_T_8 = bits(regsel_sourceC, 4, 4) node _decodeC_T_9 = mux(_decodeC_T_8, regout[4], UInt<1>(0h0)) node _decodeC_T_10 = bits(regsel_sourceC, 5, 5) node _decodeC_T_11 = mux(_decodeC_T_10, regout[5], UInt<1>(0h0)) node _decodeC_T_12 = bits(regsel_sourceC, 6, 6) node _decodeC_T_13 = mux(_decodeC_T_12, regout[6], UInt<1>(0h0)) node _decodeC_T_14 = bits(regsel_sourceC, 7, 7) node _decodeC_T_15 = mux(_decodeC_T_14, regout[7], UInt<1>(0h0)) node _decodeC_T_16 = or(_decodeC_T_1, _decodeC_T_3) node _decodeC_T_17 = or(_decodeC_T_16, _decodeC_T_5) node _decodeC_T_18 = or(_decodeC_T_17, _decodeC_T_7) node _decodeC_T_19 = or(_decodeC_T_18, _decodeC_T_9) node _decodeC_T_20 = or(_decodeC_T_19, _decodeC_T_11) node _decodeC_T_21 = or(_decodeC_T_20, _decodeC_T_13) node decodeC_0 = or(_decodeC_T_21, _decodeC_T_15) connect io.sourceC_dat.data, decodeC_0 node _decodeD_T = bits(regsel_sourceD, 0, 0) node _decodeD_T_1 = mux(_decodeD_T, regout[0], UInt<1>(0h0)) node _decodeD_T_2 = bits(regsel_sourceD, 1, 1) node _decodeD_T_3 = mux(_decodeD_T_2, regout[1], UInt<1>(0h0)) node _decodeD_T_4 = bits(regsel_sourceD, 2, 2) node _decodeD_T_5 = mux(_decodeD_T_4, regout[2], UInt<1>(0h0)) node _decodeD_T_6 = bits(regsel_sourceD, 3, 3) node _decodeD_T_7 = mux(_decodeD_T_6, regout[3], UInt<1>(0h0)) node _decodeD_T_8 = bits(regsel_sourceD, 4, 4) node _decodeD_T_9 = mux(_decodeD_T_8, regout[4], UInt<1>(0h0)) node _decodeD_T_10 = bits(regsel_sourceD, 5, 5) node _decodeD_T_11 = mux(_decodeD_T_10, regout[5], UInt<1>(0h0)) node _decodeD_T_12 = bits(regsel_sourceD, 6, 6) node _decodeD_T_13 = mux(_decodeD_T_12, regout[6], UInt<1>(0h0)) node _decodeD_T_14 = bits(regsel_sourceD, 7, 7) node _decodeD_T_15 = mux(_decodeD_T_14, regout[7], UInt<1>(0h0)) node _decodeD_T_16 = or(_decodeD_T_1, _decodeD_T_5) node _decodeD_T_17 = or(_decodeD_T_16, _decodeD_T_9) node decodeD_0 = or(_decodeD_T_17, _decodeD_T_13) node _decodeD_T_18 = or(_decodeD_T_3, _decodeD_T_7) node _decodeD_T_19 = or(_decodeD_T_18, _decodeD_T_11) node decodeD_1 = or(_decodeD_T_19, _decodeD_T_15) node _io_sourceD_rdat_data_T = cat(decodeD_1, decodeD_0) connect io.sourceD_rdat.data, _io_sourceD_rdat_data_T

module BankedStore( // @[BankedStore.scala:59:7] input clock, // @[BankedStore.scala:59:7] input reset, // @[BankedStore.scala:59:7] output io_sinkC_adr_ready, // @[BankedStore.scala:61:14] input io_sinkC_adr_valid, // @[BankedStore.scala:61:14] input io_sinkC_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkC_adr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sinkC_adr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sinkC_dat_data, // @[BankedStore.scala:61:14] output io_sinkD_adr_ready, // @[BankedStore.scala:61:14] input io_sinkD_adr_valid, // @[BankedStore.scala:61:14] input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14] input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14] output io_sourceC_adr_ready, // @[BankedStore.scala:61:14] input io_sourceC_adr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14] output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14] output io_sourceD_radr_ready, // @[BankedStore.scala:61:14] input io_sourceD_radr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14] output [127:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14] output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14] input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14] input [1:0] io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14] input [127:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14] ); wire [7:0] sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [63:0] _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_sinkC_adr_valid_0 = io_sinkC_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkC_adr_bits_noop_0 = io_sinkC_adr_bits_noop; // @[BankedStore.scala:59:7] wire [2:0] io_sinkC_adr_bits_way_0 = io_sinkC_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sinkC_adr_bits_set_0 = io_sinkC_adr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_beat_0 = io_sinkC_adr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sinkC_adr_bits_mask_0 = io_sinkC_adr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sinkC_dat_data_0 = io_sinkC_dat_data; // @[BankedStore.scala:59:7] wire io_sinkD_adr_valid_0 = io_sinkD_adr_valid; // @[BankedStore.scala:59:7] wire io_sinkD_adr_bits_noop_0 = io_sinkD_adr_bits_noop; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_way_0 = io_sinkD_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sinkD_adr_bits_set_0 = io_sinkD_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sinkD_adr_bits_beat_0 = io_sinkD_adr_bits_beat; // @[BankedStore.scala:59:7] wire [63:0] io_sinkD_dat_data_0 = io_sinkD_dat_data; // @[BankedStore.scala:59:7] wire io_sourceC_adr_valid_0 = io_sourceC_adr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_way_0 = io_sourceC_adr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceC_adr_bits_set_0 = io_sourceC_adr_bits_set; // @[BankedStore.scala:59:7] wire [2:0] io_sourceC_adr_bits_beat_0 = io_sourceC_adr_bits_beat; // @[BankedStore.scala:59:7] wire io_sourceD_radr_valid_0 = io_sourceD_radr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_radr_bits_way_0 = io_sourceD_radr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_radr_bits_set_0 = io_sourceD_radr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_beat_0 = io_sourceD_radr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_radr_bits_mask_0 = io_sourceD_radr_bits_mask; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_valid_0 = io_sourceD_wadr_valid; // @[BankedStore.scala:59:7] wire [2:0] io_sourceD_wadr_bits_way_0 = io_sourceD_wadr_bits_way; // @[BankedStore.scala:59:7] wire [9:0] io_sourceD_wadr_bits_set_0 = io_sourceD_wadr_bits_set; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_beat_0 = io_sourceD_wadr_bits_beat; // @[BankedStore.scala:59:7] wire [1:0] io_sourceD_wadr_bits_mask_0 = io_sourceD_wadr_bits_mask; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_wdat_data_0 = io_sourceD_wdat_data; // @[BankedStore.scala:59:7] wire [7:0] sinkC_req_bankSum = 8'h0; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_ready_T = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_1 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_4 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_5 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_8 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_9 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] _sinkC_req_ready_T_12 = 2'h0; // @[BankedStore.scala:131:71] wire [1:0] _sinkC_req_ready_T_13 = 2'h0; // @[BankedStore.scala:131:96] wire [1:0] sinkC_req_ready_lo = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] sinkC_req_ready_hi = 2'h3; // @[BankedStore.scala:131:21] wire [1:0] _sinkC_req_out_bankEn_T_4 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_5 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_6 = 2'h3; // @[BankedStore.scala:137:72] wire [1:0] _sinkC_req_out_bankEn_T_7 = 2'h3; // @[BankedStore.scala:137:72] wire [3:0] sinkC_req_ready = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_lo = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [3:0] sinkC_req_out_bankEn_hi = 4'hF; // @[BankedStore.scala:131:21, :137:72] wire [7:0] _sinkC_req_out_bankEn_T_8 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sinkD_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [7:0] _sourceC_req_out_bankSel_T_10 = 8'hFF; // @[BankedStore.scala:136:71, :137:72] wire [63:0] sourceC_req_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceC_req_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_0 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_1 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_2 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_3 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_4 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_5 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_6 = 64'h0; // @[BankedStore.scala:128:19] wire [63:0] sourceD_rreq_data_7 = 64'h0; // @[BankedStore.scala:128:19] wire io_sourceC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_bits_noop = 1'h0; // @[BankedStore.scala:59:7] wire _sinkC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101] wire _sinkC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101] wire sourceC_req_wen = 1'h0; // @[BankedStore.scala:128:19] wire sourceD_rreq_wen = 1'h0; // @[BankedStore.scala:128:19] wire io_sinkD_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire io_sourceC_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7] wire sinkC_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58] wire _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire _sinkC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72] wire _sinkC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72] wire sinkD_req_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire _sourceC_req_out_bankSel_T_9 = 1'h1; // @[BankedStore.scala:136:71] wire sourceD_wreq_wen = 1'h1; // @[BankedStore.scala:128:19] wire _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] sinkD_req_words_0 = io_sinkD_dat_data_0; // @[BankedStore.scala:59:7, :123:19] wire _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:132:21] wire [63:0] decodeC_0; // @[BankedStore.scala:180:85] wire _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:132:21] wire [127:0] _io_sourceD_rdat_data_T; // @[BankedStore.scala:189:30] wire _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:132:21] wire io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] wire io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] wire [63:0] io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] wire [127:0] io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] wire io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] wire [12:0] regout_idx; // @[Mux.scala:50:70] wire _regout_T; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE; // @[BankedStore.scala:172:21] wire _regout_T_2; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_1; // @[Mux.scala:50:70] wire _regout_T_5; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_1; // @[BankedStore.scala:172:21] wire _regout_T_7; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_2; // @[Mux.scala:50:70] wire _regout_T_10; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_2; // @[BankedStore.scala:172:21] wire _regout_T_12; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_3; // @[Mux.scala:50:70] wire _regout_T_15; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_3; // @[BankedStore.scala:172:21] wire _regout_T_17; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_4; // @[Mux.scala:50:70] wire _regout_T_20; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_4; // @[BankedStore.scala:172:21] wire _regout_T_22; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_5; // @[Mux.scala:50:70] wire _regout_T_25; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_5; // @[BankedStore.scala:172:21] wire _regout_T_27; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_6; // @[Mux.scala:50:70] wire _regout_T_30; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_6; // @[BankedStore.scala:172:21] wire _regout_T_32; // @[BankedStore.scala:172:32] wire [12:0] regout_idx_7; // @[Mux.scala:50:70] wire _regout_T_35; // @[BankedStore.scala:171:15] wire [12:0] _regout_WIRE_7; // @[BankedStore.scala:172:21] wire _regout_T_37; // @[BankedStore.scala:172:32] wire [63:0] sinkC_req_words_0 = io_sinkC_dat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_0 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_2 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_4 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_6 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_words_1 = io_sinkC_dat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sinkC_req_data_1 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_3 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_5 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkC_req_data_7 = sinkC_req_words_1; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sinkC_req_a_hi = {io_sinkC_adr_bits_way_0, io_sinkC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sinkC_req_a = {sinkC_req_a_hi, io_sinkC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sinkC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkC_req_out_bankEn_T_9 = sinkC_req_bankSel; // @[BankedStore.scala:128:19, :137:55] wire [7:0] sourceC_req_bankSum = sinkC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sinkC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkC_req_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sinkC_req_select_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sinkC_req_io_sinkC_adr_ready_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sinkC_req_select_shiftAmount = _sinkC_req_select_T; // @[OneHot.scala:64:49] wire [3:0] _sinkC_req_select_T_1 = 4'h1 << sinkC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sinkC_req_select = _sinkC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hF >> _sinkC_req_io_sinkC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}, :137:72] assign _sinkC_req_io_sinkC_adr_ready_T_2 = _sinkC_req_io_sinkC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkC_adr_ready_0 = _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkC_req_out_index_T = sinkC_req_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sinkC_req_index = _sinkC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkC_req_out_bankSel_T = sinkC_req_select[0]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_1 = sinkC_req_select[1]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_2 = sinkC_req_select[2]; // @[OneHot.scala:65:27] wire _sinkC_req_out_bankSel_T_3 = sinkC_req_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sinkC_req_out_bankSel_T_4 = {2{_sinkC_req_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_5 = {2{_sinkC_req_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_6 = {2{_sinkC_req_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sinkC_req_out_bankSel_T_7 = {2{_sinkC_req_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_lo = {_sinkC_req_out_bankSel_T_5, _sinkC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sinkC_req_out_bankSel_hi = {_sinkC_req_out_bankSel_T_7, _sinkC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sinkC_req_out_bankSel_T_8 = {sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sinkC_req_out_bankSel_T_9 = {2{io_sinkC_adr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sinkC_req_out_bankSel_T_10 = {2{_sinkC_req_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sinkC_req_out_bankSel_T_11 = _sinkC_req_out_bankSel_T_8 & _sinkC_req_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sinkC_req_out_bankSel_T_12 = io_sinkC_adr_valid_0 ? _sinkC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkC_req_bankSel = _sinkC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] assign _sinkC_req_out_bankEn_T_10 = io_sinkC_adr_bits_noop_0 ? 8'h0 : _sinkC_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkC_req_bankEn = _sinkC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sinkD_req_data_0 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_1 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_2 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_3 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_4 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_5 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_6 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sinkD_req_data_7 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sinkD_req_a_hi = {io_sinkD_adr_bits_way_0, io_sinkD_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sinkD_req_a = {sinkD_req_a_hi, io_sinkD_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sinkD_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sinkD_req_index; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sinkD_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sinkD_req_select_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sinkD_req_io_sinkD_adr_ready_T = sinkD_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sinkD_req_select_shiftAmount = _sinkD_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sinkD_req_select_T_1 = 8'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sinkD_req_select = _sinkD_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sinkD_req_ready_T = sinkD_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_1 = _sinkD_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_2 = _sinkD_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_3 = ~_sinkD_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_4 = sinkD_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_5 = _sinkD_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_6 = _sinkD_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_7 = ~_sinkD_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_8 = sinkD_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_9 = _sinkD_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_10 = _sinkD_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_11 = ~_sinkD_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_12 = sinkD_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_13 = _sinkD_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_14 = _sinkD_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_15 = ~_sinkD_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_16 = sinkD_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_17 = _sinkD_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_18 = _sinkD_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_19 = ~_sinkD_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_20 = sinkD_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_21 = _sinkD_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_22 = _sinkD_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_23 = ~_sinkD_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_24 = sinkD_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_25 = _sinkD_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_26 = _sinkD_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_27 = ~_sinkD_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sinkD_req_ready_T_28 = sinkD_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sinkD_req_ready_T_29 = _sinkD_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sinkD_req_ready_T_30 = _sinkD_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sinkD_req_ready_T_31 = ~_sinkD_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sinkD_req_ready_lo_lo = {_sinkD_req_ready_T_7, _sinkD_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_lo_hi = {_sinkD_req_ready_T_15, _sinkD_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_lo = {sinkD_req_ready_lo_hi, sinkD_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sinkD_req_ready_hi_lo = {_sinkD_req_ready_T_23, _sinkD_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sinkD_req_ready_hi_hi = {_sinkD_req_ready_T_31, _sinkD_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sinkD_req_ready_hi = {sinkD_req_ready_hi_hi, sinkD_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sinkD_req_ready = {sinkD_req_ready_hi, sinkD_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _sinkD_req_io_sinkD_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sinkD_req_io_sinkD_adr_ready_T_2 = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sinkD_adr_ready_0 = _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sinkD_req_out_index_T = sinkD_req_a[15:3]; // @[BankedStore.scala:126:91, :135:23] assign sinkD_req_index = _sinkD_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sinkD_req_out_bankSel_T = sinkD_req_select[0]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_1 = sinkD_req_select[1]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_2 = sinkD_req_select[2]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_3 = sinkD_req_select[3]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_4 = sinkD_req_select[4]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_5 = sinkD_req_select[5]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_6 = sinkD_req_select[6]; // @[OneHot.scala:65:27] wire _sinkD_req_out_bankSel_T_7 = sinkD_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sinkD_req_out_bankSel_lo_lo = {_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_lo_hi = {_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_lo = {sinkD_req_out_bankSel_lo_hi, sinkD_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_lo = {_sinkD_req_out_bankSel_T_5, _sinkD_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sinkD_req_out_bankSel_hi_hi = {_sinkD_req_out_bankSel_T_7, _sinkD_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sinkD_req_out_bankSel_hi = {sinkD_req_out_bankSel_hi_hi, sinkD_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_8 = {sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sinkD_req_out_bankSel_T_11 = _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sinkD_req_out_bankSel_T_12 = io_sinkD_adr_valid_0 ? _sinkD_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sinkD_req_bankSel = _sinkD_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sinkD_req_out_bankEn_T = sinkD_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_1 = sinkD_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_2 = sinkD_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_3 = sinkD_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_4 = sinkD_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_5 = sinkD_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_6 = sinkD_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sinkD_req_out_bankEn_T_7 = sinkD_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sinkD_req_out_bankEn_lo_lo = {_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_lo_hi = {_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_lo = {sinkD_req_out_bankEn_lo_hi, sinkD_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_lo = {_sinkD_req_out_bankEn_T_5, _sinkD_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sinkD_req_out_bankEn_hi_hi = {_sinkD_req_out_bankEn_T_7, _sinkD_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sinkD_req_out_bankEn_hi = {sinkD_req_out_bankEn_hi_hi, sinkD_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_8 = {sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sinkD_req_out_bankEn_T_9 = sinkD_req_bankSel & _sinkD_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sinkD_req_out_bankEn_T_10 = io_sinkD_adr_bits_noop_0 ? 8'h0 : _sinkD_req_out_bankEn_T_9; // @[BankedStore.scala:59:7, :137:{24,55}] assign sinkD_req_bankEn = _sinkD_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceC_req_a_hi = {io_sourceC_adr_bits_way_0, io_sourceC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [15:0] sourceC_req_a = {sourceC_req_a_hi, io_sourceC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceC_req_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceC_req_index; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceC_req_bankEn; // @[BankedStore.scala:128:19] wire [2:0] _sourceC_req_select_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28] wire [2:0] _sourceC_req_io_sourceC_adr_ready_T = sourceC_req_a[2:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [2:0] sourceC_req_select_shiftAmount = _sourceC_req_select_T; // @[OneHot.scala:64:49] wire [7:0] _sourceC_req_select_T_1 = 8'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [7:0] sourceC_req_select = _sourceC_req_select_T_1; // @[OneHot.scala:65:{12,27}] wire _sourceC_req_ready_T = sourceC_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_1 = _sourceC_req_ready_T; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_2 = _sourceC_req_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_3 = ~_sourceC_req_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_4 = sourceC_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_5 = _sourceC_req_ready_T_4; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_6 = _sourceC_req_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_7 = ~_sourceC_req_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_8 = sourceC_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_9 = _sourceC_req_ready_T_8; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_10 = _sourceC_req_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_11 = ~_sourceC_req_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_12 = sourceC_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_13 = _sourceC_req_ready_T_12; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_14 = _sourceC_req_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_15 = ~_sourceC_req_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_16 = sourceC_req_bankSum[4]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_17 = _sourceC_req_ready_T_16; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_18 = _sourceC_req_ready_T_17; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_19 = ~_sourceC_req_ready_T_18; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_20 = sourceC_req_bankSum[5]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_21 = _sourceC_req_ready_T_20; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_22 = _sourceC_req_ready_T_21; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_23 = ~_sourceC_req_ready_T_22; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_24 = sourceC_req_bankSum[6]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_25 = _sourceC_req_ready_T_24; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_26 = _sourceC_req_ready_T_25; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_27 = ~_sourceC_req_ready_T_26; // @[BankedStore.scala:131:{58,101}] wire _sourceC_req_ready_T_28 = sourceC_req_bankSum[7]; // @[BankedStore.scala:128:19, :131:71] wire _sourceC_req_ready_T_29 = _sourceC_req_ready_T_28; // @[BankedStore.scala:131:{71,96}] wire _sourceC_req_ready_T_30 = _sourceC_req_ready_T_29; // @[BankedStore.scala:131:{96,101}] wire _sourceC_req_ready_T_31 = ~_sourceC_req_ready_T_30; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceC_req_ready_lo_lo = {_sourceC_req_ready_T_7, _sourceC_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_lo_hi = {_sourceC_req_ready_T_15, _sourceC_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_lo = {sourceC_req_ready_lo_hi, sourceC_req_ready_lo_lo}; // @[BankedStore.scala:131:21] wire [1:0] sourceC_req_ready_hi_lo = {_sourceC_req_ready_T_23, _sourceC_req_ready_T_19}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceC_req_ready_hi_hi = {_sourceC_req_ready_T_31, _sourceC_req_ready_T_27}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceC_req_ready_hi = {sourceC_req_ready_hi_hi, sourceC_req_ready_hi_lo}; // @[BankedStore.scala:131:21] wire [7:0] sourceC_req_ready = {sourceC_req_ready_hi, sourceC_req_ready_lo}; // @[BankedStore.scala:131:21] wire [7:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> _sourceC_req_io_sourceC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceC_req_io_sourceC_adr_ready_T_2 = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceC_adr_ready_0 = _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceC_req_out_index_T = sourceC_req_a[15:3]; // @[BankedStore.scala:126:91, :135:23] assign sourceC_req_index = _sourceC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceC_req_out_bankSel_T = sourceC_req_select[0]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_1 = sourceC_req_select[1]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_2 = sourceC_req_select[2]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_3 = sourceC_req_select[3]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_4 = sourceC_req_select[4]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_5 = sourceC_req_select[5]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_6 = sourceC_req_select[6]; // @[OneHot.scala:65:27] wire _sourceC_req_out_bankSel_T_7 = sourceC_req_select[7]; // @[OneHot.scala:65:27] wire [1:0] sourceC_req_out_bankSel_lo_lo = {_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_lo_hi = {_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_lo = {sourceC_req_out_bankSel_lo_hi, sourceC_req_out_bankSel_lo_lo}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_lo = {_sourceC_req_out_bankSel_T_5, _sourceC_req_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [1:0] sourceC_req_out_bankSel_hi_hi = {_sourceC_req_out_bankSel_T_7, _sourceC_req_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [3:0] sourceC_req_out_bankSel_hi = {sourceC_req_out_bankSel_hi_hi, sourceC_req_out_bankSel_hi_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_8 = {sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [7:0] _sourceC_req_out_bankSel_T_11 = _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:136:{49,65}] assign _sourceC_req_out_bankSel_T_12 = io_sourceC_adr_valid_0 ? _sourceC_req_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceC_req_bankSel = _sourceC_req_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceC_req_out_bankEn_T = sourceC_req_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_1 = sourceC_req_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_2 = sourceC_req_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_3 = sourceC_req_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_4 = sourceC_req_ready[4]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_5 = sourceC_req_ready[5]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_6 = sourceC_req_ready[6]; // @[BankedStore.scala:131:21, :137:72] wire _sourceC_req_out_bankEn_T_7 = sourceC_req_ready[7]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] sourceC_req_out_bankEn_lo_lo = {_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_lo_hi = {_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_lo = {sourceC_req_out_bankEn_lo_hi, sourceC_req_out_bankEn_lo_lo}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_lo = {_sourceC_req_out_bankEn_T_5, _sourceC_req_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [1:0] sourceC_req_out_bankEn_hi_hi = {_sourceC_req_out_bankEn_T_7, _sourceC_req_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [3:0] sourceC_req_out_bankEn_hi = {sourceC_req_out_bankEn_hi_hi, sourceC_req_out_bankEn_hi_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_8 = {sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceC_req_out_bankEn_T_9 = sourceC_req_bankSel & _sourceC_req_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceC_req_out_bankEn_T_10 = _sourceC_req_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceC_req_bankEn = _sourceC_req_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [12:0] sourceD_rreq_a_hi = {io_sourceD_radr_bits_way_0, io_sourceD_radr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sourceD_rreq_a = {sourceD_rreq_a_hi, io_sourceD_radr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceD_rreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceD_rreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_rreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_rreq_select_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_rreq_io_sourceD_radr_ready_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_rreq_select_shiftAmount = _sourceD_rreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_rreq_select_T_1 = 4'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_rreq_select = _sourceD_rreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_rreq_ready_T = sourceD_rreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_1 = _sourceD_rreq_ready_T & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_2 = |_sourceD_rreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_3 = ~_sourceD_rreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_4 = sourceD_rreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_5 = _sourceD_rreq_ready_T_4 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_6 = |_sourceD_rreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_7 = ~_sourceD_rreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_8 = sourceD_rreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_9 = _sourceD_rreq_ready_T_8 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_10 = |_sourceD_rreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_11 = ~_sourceD_rreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_rreq_ready_T_12 = sourceD_rreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_rreq_ready_T_13 = _sourceD_rreq_ready_T_12 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_rreq_ready_T_14 = |_sourceD_rreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_rreq_ready_T_15 = ~_sourceD_rreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_rreq_ready_lo = {_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_rreq_ready_hi = {_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_rreq_ready = {sourceD_rreq_ready_hi, sourceD_rreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _sourceD_rreq_io_sourceD_radr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_rreq_io_sourceD_radr_ready_T_2 = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_radr_ready_0 = _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_rreq_out_index_T = sourceD_rreq_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_rreq_index = _sourceD_rreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_rreq_out_bankSel_T = sourceD_rreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_1 = sourceD_rreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_2 = sourceD_rreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_rreq_out_bankSel_T_3 = sourceD_rreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_rreq_out_bankSel_T_4 = {2{_sourceD_rreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_5 = {2{_sourceD_rreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_6 = {2{_sourceD_rreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_rreq_out_bankSel_T_7 = {2{_sourceD_rreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_lo = {_sourceD_rreq_out_bankSel_T_5, _sourceD_rreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_rreq_out_bankSel_hi = {_sourceD_rreq_out_bankSel_T_7, _sourceD_rreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_rreq_out_bankSel_T_8 = {sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_rreq_out_bankSel_T_9 = {2{io_sourceD_radr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_10 = {2{_sourceD_rreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_rreq_out_bankSel_T_11 = _sourceD_rreq_out_bankSel_T_8 & _sourceD_rreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_rreq_out_bankSel_T_12 = io_sourceD_radr_valid_0 ? _sourceD_rreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_rreq_bankSel = _sourceD_rreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_rreq_out_bankEn_T = sourceD_rreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_1 = sourceD_rreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_2 = sourceD_rreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_rreq_out_bankEn_T_3 = sourceD_rreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_4 = {2{_sourceD_rreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_5 = {2{_sourceD_rreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_6 = {2{_sourceD_rreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_rreq_out_bankEn_T_7 = {2{_sourceD_rreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_lo = {_sourceD_rreq_out_bankEn_T_5, _sourceD_rreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_rreq_out_bankEn_hi = {_sourceD_rreq_out_bankEn_T_7, _sourceD_rreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_8 = {sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_rreq_out_bankEn_T_9 = sourceD_rreq_bankSel & _sourceD_rreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_rreq_out_bankEn_T_10 = _sourceD_rreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_rreq_bankEn = _sourceD_rreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] wire [63:0] sourceD_wreq_words_0 = io_sourceD_wdat_data_0[63:0]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_0 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_2 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_4 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_6 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_words_1 = io_sourceD_wdat_data_0[127:64]; // @[BankedStore.scala:59:7, :123:19] wire [63:0] sourceD_wreq_data_1 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_3 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_5 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [63:0] sourceD_wreq_data_7 = sourceD_wreq_words_1; // @[BankedStore.scala:123:19, :128:19] wire [12:0] sourceD_wreq_a_hi = {io_sourceD_wadr_bits_way_0, io_sourceD_wadr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91] wire [14:0] sourceD_wreq_a = {sourceD_wreq_a_hi, io_sourceD_wadr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91] wire [12:0] _sourceD_wreq_out_index_T; // @[BankedStore.scala:135:23] wire [7:0] _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:136:24] wire [7:0] _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:137:24] wire [12:0] sourceD_wreq_index; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSel; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankSum; // @[BankedStore.scala:128:19] wire [7:0] sourceD_wreq_bankEn; // @[BankedStore.scala:128:19] wire [1:0] _sourceD_wreq_select_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28] wire [1:0] _sourceD_wreq_io_sourceD_wadr_ready_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23] wire [1:0] sourceD_wreq_select_shiftAmount = _sourceD_wreq_select_T; // @[OneHot.scala:64:49] wire [3:0] _sourceD_wreq_select_T_1 = 4'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] sourceD_wreq_select = _sourceD_wreq_select_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] _sourceD_wreq_ready_T = sourceD_wreq_bankSum[1:0]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_1 = _sourceD_wreq_ready_T & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_2 = |_sourceD_wreq_ready_T_1; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_3 = ~_sourceD_wreq_ready_T_2; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_4 = sourceD_wreq_bankSum[3:2]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_5 = _sourceD_wreq_ready_T_4 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_6 = |_sourceD_wreq_ready_T_5; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_7 = ~_sourceD_wreq_ready_T_6; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_8 = sourceD_wreq_bankSum[5:4]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_9 = _sourceD_wreq_ready_T_8 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_10 = |_sourceD_wreq_ready_T_9; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_11 = ~_sourceD_wreq_ready_T_10; // @[BankedStore.scala:131:{58,101}] wire [1:0] _sourceD_wreq_ready_T_12 = sourceD_wreq_bankSum[7:6]; // @[BankedStore.scala:128:19, :131:71] wire [1:0] _sourceD_wreq_ready_T_13 = _sourceD_wreq_ready_T_12 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}] wire _sourceD_wreq_ready_T_14 = |_sourceD_wreq_ready_T_13; // @[BankedStore.scala:131:{96,101}] wire _sourceD_wreq_ready_T_15 = ~_sourceD_wreq_ready_T_14; // @[BankedStore.scala:131:{58,101}] wire [1:0] sourceD_wreq_ready_lo = {_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}] wire [1:0] sourceD_wreq_ready_hi = {_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}] wire [3:0] sourceD_wreq_ready = {sourceD_wreq_ready_hi, sourceD_wreq_ready_lo}; // @[BankedStore.scala:131:21] wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _sourceD_wreq_io_sourceD_wadr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}] assign _sourceD_wreq_io_sourceD_wadr_ready_T_2 = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala:132:21] assign io_sourceD_wadr_ready_0 = _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:59:7, :132:21] assign _sourceD_wreq_out_index_T = sourceD_wreq_a[14:2]; // @[BankedStore.scala:126:91, :135:23] assign sourceD_wreq_index = _sourceD_wreq_out_index_T; // @[BankedStore.scala:128:19, :135:23] wire _sourceD_wreq_out_bankSel_T = sourceD_wreq_select[0]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_1 = sourceD_wreq_select[1]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_2 = sourceD_wreq_select[2]; // @[OneHot.scala:65:27] wire _sourceD_wreq_out_bankSel_T_3 = sourceD_wreq_select[3]; // @[OneHot.scala:65:27] wire [1:0] _sourceD_wreq_out_bankSel_T_4 = {2{_sourceD_wreq_out_bankSel_T}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_5 = {2{_sourceD_wreq_out_bankSel_T_1}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_6 = {2{_sourceD_wreq_out_bankSel_T_2}}; // @[BankedStore.scala:136:49] wire [1:0] _sourceD_wreq_out_bankSel_T_7 = {2{_sourceD_wreq_out_bankSel_T_3}}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_lo = {_sourceD_wreq_out_bankSel_T_5, _sourceD_wreq_out_bankSel_T_4}; // @[BankedStore.scala:136:49] wire [3:0] sourceD_wreq_out_bankSel_hi = {_sourceD_wreq_out_bankSel_T_7, _sourceD_wreq_out_bankSel_T_6}; // @[BankedStore.scala:136:49] wire [7:0] _sourceD_wreq_out_bankSel_T_8 = {sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo}; // @[BankedStore.scala:136:49] wire [3:0] _sourceD_wreq_out_bankSel_T_9 = {2{io_sourceD_wadr_bits_mask_0}}; // @[BankedStore.scala:59:7, :136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_10 = {2{_sourceD_wreq_out_bankSel_T_9}}; // @[BankedStore.scala:136:71] wire [7:0] _sourceD_wreq_out_bankSel_T_11 = _sourceD_wreq_out_bankSel_T_8 & _sourceD_wreq_out_bankSel_T_10; // @[BankedStore.scala:136:{49,65,71}] assign _sourceD_wreq_out_bankSel_T_12 = io_sourceD_wadr_valid_0 ? _sourceD_wreq_out_bankSel_T_11 : 8'h0; // @[BankedStore.scala:59:7, :136:{24,65}] assign sourceD_wreq_bankSel = _sourceD_wreq_out_bankSel_T_12; // @[BankedStore.scala:128:19, :136:24] wire _sourceD_wreq_out_bankEn_T = sourceD_wreq_ready[0]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_1 = sourceD_wreq_ready[1]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_2 = sourceD_wreq_ready[2]; // @[BankedStore.scala:131:21, :137:72] wire _sourceD_wreq_out_bankEn_T_3 = sourceD_wreq_ready[3]; // @[BankedStore.scala:131:21, :137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_4 = {2{_sourceD_wreq_out_bankEn_T}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_5 = {2{_sourceD_wreq_out_bankEn_T_1}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_6 = {2{_sourceD_wreq_out_bankEn_T_2}}; // @[BankedStore.scala:137:72] wire [1:0] _sourceD_wreq_out_bankEn_T_7 = {2{_sourceD_wreq_out_bankEn_T_3}}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_lo = {_sourceD_wreq_out_bankEn_T_5, _sourceD_wreq_out_bankEn_T_4}; // @[BankedStore.scala:137:72] wire [3:0] sourceD_wreq_out_bankEn_hi = {_sourceD_wreq_out_bankEn_T_7, _sourceD_wreq_out_bankEn_T_6}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_8 = {sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo}; // @[BankedStore.scala:137:72] wire [7:0] _sourceD_wreq_out_bankEn_T_9 = sourceD_wreq_bankSel & _sourceD_wreq_out_bankEn_T_8; // @[BankedStore.scala:128:19, :137:{55,72}] assign _sourceD_wreq_out_bankEn_T_10 = _sourceD_wreq_out_bankEn_T_9; // @[BankedStore.scala:137:{24,55}] assign sourceD_wreq_bankEn = _sourceD_wreq_out_bankEn_T_10; // @[BankedStore.scala:128:19, :137:24] assign sinkD_req_bankSum = sourceC_req_bankSel | sinkC_req_bankSel; // @[BankedStore.scala:128:19, :161:17] assign sourceD_wreq_bankSum = sinkD_req_bankSel | sinkD_req_bankSum; // @[BankedStore.scala:128:19, :161:17] assign sourceD_rreq_bankSum = sourceD_wreq_bankSel | sourceD_wreq_bankSum; // @[BankedStore.scala:128:19, :161:17] wire _regout_en_T = sinkC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_1 = sourceC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_2 = sinkD_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_3 = sourceD_wreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_4 = sourceD_rreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_5 = _regout_en_T | _regout_en_T_1; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_6 = _regout_en_T_5 | _regout_en_T_2; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_7 = _regout_en_T_6 | _regout_en_T_3; // @[BankedStore.scala:165:{32,45}] wire regout_en = _regout_en_T_7 | _regout_en_T_4; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0 = sinkC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1 = sourceC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2 = sinkD_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3 = sourceD_wreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T = regout_sel_3; // @[Mux.scala:50:70] wire regout_sel_4 = sourceD_rreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_1 = regout_sel_2 | _regout_wen_T; // @[Mux.scala:50:70] wire _regout_wen_T_2 = ~regout_sel_1 & _regout_wen_T_1; // @[Mux.scala:50:70] wire regout_wen = regout_sel_0 | _regout_wen_T_2; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T = regout_sel_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_1 = regout_sel_2 ? sinkD_req_index : _regout_idx_T; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_2 = regout_sel_1 ? sourceC_req_index : _regout_idx_T_1; // @[Mux.scala:50:70] assign regout_idx = regout_sel_0 ? sinkC_req_index : _regout_idx_T_2; // @[Mux.scala:50:70] assign _regout_WIRE = regout_idx; // @[Mux.scala:50:70] wire [63:0] _regout_data_T = regout_sel_3 ? sourceD_wreq_data_0 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_1 = regout_sel_2 ? sinkD_req_data_0 : _regout_data_T; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_2 = regout_sel_1 ? 64'h0 : _regout_data_T_1; // @[Mux.scala:50:70] wire [63:0] regout_data = regout_sel_0 ? sinkC_req_data_0 : _regout_data_T_2; // @[Mux.scala:50:70] assign _regout_T = regout_wen & regout_en; // @[Mux.scala:50:70] wire _regout_T_1 = ~regout_wen; // @[Mux.scala:50:70] assign _regout_T_2 = _regout_T_1 & regout_en; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_3 = ~regout_wen; // @[Mux.scala:50:70] wire _regout_T_4 = _regout_T_3 & regout_en; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG; // @[BankedStore.scala:172:47] reg [63:0] regout_r; // @[BankedStore.scala:172:14] wire [63:0] regout_0 = regout_r; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_8 = sinkC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_9 = sourceC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_10 = sinkD_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_11 = sourceD_wreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_12 = sourceD_rreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_13 = _regout_en_T_8 | _regout_en_T_9; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_14 = _regout_en_T_13 | _regout_en_T_10; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_15 = _regout_en_T_14 | _regout_en_T_11; // @[BankedStore.scala:165:{32,45}] wire regout_en_1 = _regout_en_T_15 | _regout_en_T_12; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_1 = sinkC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_1 = sourceC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_1 = sinkD_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_1 = sourceD_wreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_3 = regout_sel_3_1; // @[Mux.scala:50:70] wire regout_sel_4_1 = sourceD_rreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_4 = regout_sel_2_1 | _regout_wen_T_3; // @[Mux.scala:50:70] wire _regout_wen_T_5 = ~regout_sel_1_1 & _regout_wen_T_4; // @[Mux.scala:50:70] wire regout_wen_1 = regout_sel_0_1 | _regout_wen_T_5; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_3 = regout_sel_3_1 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_4 = regout_sel_2_1 ? sinkD_req_index : _regout_idx_T_3; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_5 = regout_sel_1_1 ? sourceC_req_index : _regout_idx_T_4; // @[Mux.scala:50:70] assign regout_idx_1 = regout_sel_0_1 ? sinkC_req_index : _regout_idx_T_5; // @[Mux.scala:50:70] assign _regout_WIRE_1 = regout_idx_1; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_3 = regout_sel_3_1 ? sourceD_wreq_data_1 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_4 = regout_sel_2_1 ? sinkD_req_data_1 : _regout_data_T_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_5 = regout_sel_1_1 ? 64'h0 : _regout_data_T_4; // @[Mux.scala:50:70] wire [63:0] regout_data_1 = regout_sel_0_1 ? sinkC_req_data_1 : _regout_data_T_5; // @[Mux.scala:50:70] assign _regout_T_5 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] wire _regout_T_6 = ~regout_wen_1; // @[Mux.scala:50:70] assign _regout_T_7 = _regout_T_6 & regout_en_1; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_8 = ~regout_wen_1; // @[Mux.scala:50:70] wire _regout_T_9 = _regout_T_8 & regout_en_1; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_1; // @[BankedStore.scala:172:47] reg [63:0] regout_r_1; // @[BankedStore.scala:172:14] wire [63:0] regout_1 = regout_r_1; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_16 = sinkC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_17 = sourceC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_18 = sinkD_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_19 = sourceD_wreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_20 = sourceD_rreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_21 = _regout_en_T_16 | _regout_en_T_17; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_22 = _regout_en_T_21 | _regout_en_T_18; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_23 = _regout_en_T_22 | _regout_en_T_19; // @[BankedStore.scala:165:{32,45}] wire regout_en_2 = _regout_en_T_23 | _regout_en_T_20; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_2 = sinkC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_2 = sourceC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_2 = sinkD_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_2 = sourceD_wreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_6 = regout_sel_3_2; // @[Mux.scala:50:70] wire regout_sel_4_2 = sourceD_rreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_7 = regout_sel_2_2 | _regout_wen_T_6; // @[Mux.scala:50:70] wire _regout_wen_T_8 = ~regout_sel_1_2 & _regout_wen_T_7; // @[Mux.scala:50:70] wire regout_wen_2 = regout_sel_0_2 | _regout_wen_T_8; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_6 = regout_sel_3_2 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_7 = regout_sel_2_2 ? sinkD_req_index : _regout_idx_T_6; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_8 = regout_sel_1_2 ? sourceC_req_index : _regout_idx_T_7; // @[Mux.scala:50:70] assign regout_idx_2 = regout_sel_0_2 ? sinkC_req_index : _regout_idx_T_8; // @[Mux.scala:50:70] assign _regout_WIRE_2 = regout_idx_2; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_6 = regout_sel_3_2 ? sourceD_wreq_data_2 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_7 = regout_sel_2_2 ? sinkD_req_data_2 : _regout_data_T_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_8 = regout_sel_1_2 ? 64'h0 : _regout_data_T_7; // @[Mux.scala:50:70] wire [63:0] regout_data_2 = regout_sel_0_2 ? sinkC_req_data_2 : _regout_data_T_8; // @[Mux.scala:50:70] assign _regout_T_10 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] wire _regout_T_11 = ~regout_wen_2; // @[Mux.scala:50:70] assign _regout_T_12 = _regout_T_11 & regout_en_2; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_13 = ~regout_wen_2; // @[Mux.scala:50:70] wire _regout_T_14 = _regout_T_13 & regout_en_2; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_2; // @[BankedStore.scala:172:47] reg [63:0] regout_r_2; // @[BankedStore.scala:172:14] wire [63:0] regout_2 = regout_r_2; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_24 = sinkC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_25 = sourceC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_26 = sinkD_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_27 = sourceD_wreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_28 = sourceD_rreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_29 = _regout_en_T_24 | _regout_en_T_25; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_30 = _regout_en_T_29 | _regout_en_T_26; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_31 = _regout_en_T_30 | _regout_en_T_27; // @[BankedStore.scala:165:{32,45}] wire regout_en_3 = _regout_en_T_31 | _regout_en_T_28; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_3 = sinkC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_3 = sourceC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_3 = sinkD_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_3 = sourceD_wreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_9 = regout_sel_3_3; // @[Mux.scala:50:70] wire regout_sel_4_3 = sourceD_rreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_10 = regout_sel_2_3 | _regout_wen_T_9; // @[Mux.scala:50:70] wire _regout_wen_T_11 = ~regout_sel_1_3 & _regout_wen_T_10; // @[Mux.scala:50:70] wire regout_wen_3 = regout_sel_0_3 | _regout_wen_T_11; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_9 = regout_sel_3_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_10 = regout_sel_2_3 ? sinkD_req_index : _regout_idx_T_9; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_11 = regout_sel_1_3 ? sourceC_req_index : _regout_idx_T_10; // @[Mux.scala:50:70] assign regout_idx_3 = regout_sel_0_3 ? sinkC_req_index : _regout_idx_T_11; // @[Mux.scala:50:70] assign _regout_WIRE_3 = regout_idx_3; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_9 = regout_sel_3_3 ? sourceD_wreq_data_3 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_10 = regout_sel_2_3 ? sinkD_req_data_3 : _regout_data_T_9; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_11 = regout_sel_1_3 ? 64'h0 : _regout_data_T_10; // @[Mux.scala:50:70] wire [63:0] regout_data_3 = regout_sel_0_3 ? sinkC_req_data_3 : _regout_data_T_11; // @[Mux.scala:50:70] assign _regout_T_15 = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] wire _regout_T_16 = ~regout_wen_3; // @[Mux.scala:50:70] assign _regout_T_17 = _regout_T_16 & regout_en_3; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_18 = ~regout_wen_3; // @[Mux.scala:50:70] wire _regout_T_19 = _regout_T_18 & regout_en_3; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_3; // @[BankedStore.scala:172:47] reg [63:0] regout_r_3; // @[BankedStore.scala:172:14] wire [63:0] regout_3 = regout_r_3; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_32 = sinkC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_33 = sourceC_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_34 = sinkD_req_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_35 = sourceD_wreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_36 = sourceD_rreq_bankEn[4]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_37 = _regout_en_T_32 | _regout_en_T_33; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_38 = _regout_en_T_37 | _regout_en_T_34; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_39 = _regout_en_T_38 | _regout_en_T_35; // @[BankedStore.scala:165:{32,45}] wire regout_en_4 = _regout_en_T_39 | _regout_en_T_36; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_4 = sinkC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_4 = sourceC_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_4 = sinkD_req_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_4 = sourceD_wreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_12 = regout_sel_3_4; // @[Mux.scala:50:70] wire regout_sel_4_4 = sourceD_rreq_bankSel[4]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_13 = regout_sel_2_4 | _regout_wen_T_12; // @[Mux.scala:50:70] wire _regout_wen_T_14 = ~regout_sel_1_4 & _regout_wen_T_13; // @[Mux.scala:50:70] wire regout_wen_4 = regout_sel_0_4 | _regout_wen_T_14; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_12 = regout_sel_3_4 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_13 = regout_sel_2_4 ? sinkD_req_index : _regout_idx_T_12; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_14 = regout_sel_1_4 ? sourceC_req_index : _regout_idx_T_13; // @[Mux.scala:50:70] assign regout_idx_4 = regout_sel_0_4 ? sinkC_req_index : _regout_idx_T_14; // @[Mux.scala:50:70] assign _regout_WIRE_4 = regout_idx_4; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_12 = regout_sel_3_4 ? sourceD_wreq_data_4 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_13 = regout_sel_2_4 ? sinkD_req_data_4 : _regout_data_T_12; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_14 = regout_sel_1_4 ? 64'h0 : _regout_data_T_13; // @[Mux.scala:50:70] wire [63:0] regout_data_4 = regout_sel_0_4 ? sinkC_req_data_4 : _regout_data_T_14; // @[Mux.scala:50:70] assign _regout_T_20 = regout_wen_4 & regout_en_4; // @[Mux.scala:50:70] wire _regout_T_21 = ~regout_wen_4; // @[Mux.scala:50:70] assign _regout_T_22 = _regout_T_21 & regout_en_4; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_23 = ~regout_wen_4; // @[Mux.scala:50:70] wire _regout_T_24 = _regout_T_23 & regout_en_4; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_4; // @[BankedStore.scala:172:47] reg [63:0] regout_r_4; // @[BankedStore.scala:172:14] wire [63:0] regout_4 = regout_r_4; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_40 = sinkC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_41 = sourceC_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_42 = sinkD_req_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_43 = sourceD_wreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_44 = sourceD_rreq_bankEn[5]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_45 = _regout_en_T_40 | _regout_en_T_41; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_46 = _regout_en_T_45 | _regout_en_T_42; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_47 = _regout_en_T_46 | _regout_en_T_43; // @[BankedStore.scala:165:{32,45}] wire regout_en_5 = _regout_en_T_47 | _regout_en_T_44; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_5 = sinkC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_5 = sourceC_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_5 = sinkD_req_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_5 = sourceD_wreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_15 = regout_sel_3_5; // @[Mux.scala:50:70] wire regout_sel_4_5 = sourceD_rreq_bankSel[5]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_16 = regout_sel_2_5 | _regout_wen_T_15; // @[Mux.scala:50:70] wire _regout_wen_T_17 = ~regout_sel_1_5 & _regout_wen_T_16; // @[Mux.scala:50:70] wire regout_wen_5 = regout_sel_0_5 | _regout_wen_T_17; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_15 = regout_sel_3_5 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_16 = regout_sel_2_5 ? sinkD_req_index : _regout_idx_T_15; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_17 = regout_sel_1_5 ? sourceC_req_index : _regout_idx_T_16; // @[Mux.scala:50:70] assign regout_idx_5 = regout_sel_0_5 ? sinkC_req_index : _regout_idx_T_17; // @[Mux.scala:50:70] assign _regout_WIRE_5 = regout_idx_5; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_15 = regout_sel_3_5 ? sourceD_wreq_data_5 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_16 = regout_sel_2_5 ? sinkD_req_data_5 : _regout_data_T_15; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_17 = regout_sel_1_5 ? 64'h0 : _regout_data_T_16; // @[Mux.scala:50:70] wire [63:0] regout_data_5 = regout_sel_0_5 ? sinkC_req_data_5 : _regout_data_T_17; // @[Mux.scala:50:70] assign _regout_T_25 = regout_wen_5 & regout_en_5; // @[Mux.scala:50:70] wire _regout_T_26 = ~regout_wen_5; // @[Mux.scala:50:70] assign _regout_T_27 = _regout_T_26 & regout_en_5; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_28 = ~regout_wen_5; // @[Mux.scala:50:70] wire _regout_T_29 = _regout_T_28 & regout_en_5; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_5; // @[BankedStore.scala:172:47] reg [63:0] regout_r_5; // @[BankedStore.scala:172:14] wire [63:0] regout_5 = regout_r_5; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_48 = sinkC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_49 = sourceC_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_50 = sinkD_req_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_51 = sourceD_wreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_52 = sourceD_rreq_bankEn[6]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_53 = _regout_en_T_48 | _regout_en_T_49; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_54 = _regout_en_T_53 | _regout_en_T_50; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_55 = _regout_en_T_54 | _regout_en_T_51; // @[BankedStore.scala:165:{32,45}] wire regout_en_6 = _regout_en_T_55 | _regout_en_T_52; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_6 = sinkC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_6 = sourceC_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_6 = sinkD_req_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_6 = sourceD_wreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_18 = regout_sel_3_6; // @[Mux.scala:50:70] wire regout_sel_4_6 = sourceD_rreq_bankSel[6]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_19 = regout_sel_2_6 | _regout_wen_T_18; // @[Mux.scala:50:70] wire _regout_wen_T_20 = ~regout_sel_1_6 & _regout_wen_T_19; // @[Mux.scala:50:70] wire regout_wen_6 = regout_sel_0_6 | _regout_wen_T_20; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_18 = regout_sel_3_6 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_19 = regout_sel_2_6 ? sinkD_req_index : _regout_idx_T_18; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_20 = regout_sel_1_6 ? sourceC_req_index : _regout_idx_T_19; // @[Mux.scala:50:70] assign regout_idx_6 = regout_sel_0_6 ? sinkC_req_index : _regout_idx_T_20; // @[Mux.scala:50:70] assign _regout_WIRE_6 = regout_idx_6; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_18 = regout_sel_3_6 ? sourceD_wreq_data_6 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_19 = regout_sel_2_6 ? sinkD_req_data_6 : _regout_data_T_18; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_20 = regout_sel_1_6 ? 64'h0 : _regout_data_T_19; // @[Mux.scala:50:70] wire [63:0] regout_data_6 = regout_sel_0_6 ? sinkC_req_data_6 : _regout_data_T_20; // @[Mux.scala:50:70] assign _regout_T_30 = regout_wen_6 & regout_en_6; // @[Mux.scala:50:70] wire _regout_T_31 = ~regout_wen_6; // @[Mux.scala:50:70] assign _regout_T_32 = _regout_T_31 & regout_en_6; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_33 = ~regout_wen_6; // @[Mux.scala:50:70] wire _regout_T_34 = _regout_T_33 & regout_en_6; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_6; // @[BankedStore.scala:172:47] reg [63:0] regout_r_6; // @[BankedStore.scala:172:14] wire [63:0] regout_6 = regout_r_6; // @[BankedStore.scala:164:23, :172:14] wire _regout_en_T_56 = sinkC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_57 = sourceC_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_58 = sinkD_req_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_59 = sourceD_wreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_60 = sourceD_rreq_bankEn[7]; // @[BankedStore.scala:128:19, :165:32] wire _regout_en_T_61 = _regout_en_T_56 | _regout_en_T_57; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_62 = _regout_en_T_61 | _regout_en_T_58; // @[BankedStore.scala:165:{32,45}] wire _regout_en_T_63 = _regout_en_T_62 | _regout_en_T_59; // @[BankedStore.scala:165:{32,45}] wire regout_en_7 = _regout_en_T_63 | _regout_en_T_60; // @[BankedStore.scala:165:{32,45}] wire regout_sel_0_7 = sinkC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_1_7 = sourceC_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_2_7 = sinkD_req_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire regout_sel_3_7 = sourceD_wreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_21 = regout_sel_3_7; // @[Mux.scala:50:70] wire regout_sel_4_7 = sourceD_rreq_bankSel[7]; // @[BankedStore.scala:128:19, :166:33] wire _regout_wen_T_22 = regout_sel_2_7 | _regout_wen_T_21; // @[Mux.scala:50:70] wire _regout_wen_T_23 = ~regout_sel_1_7 & _regout_wen_T_22; // @[Mux.scala:50:70] wire regout_wen_7 = regout_sel_0_7 | _regout_wen_T_23; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_21 = regout_sel_3_7 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_22 = regout_sel_2_7 ? sinkD_req_index : _regout_idx_T_21; // @[Mux.scala:50:70] wire [12:0] _regout_idx_T_23 = regout_sel_1_7 ? sourceC_req_index : _regout_idx_T_22; // @[Mux.scala:50:70] assign regout_idx_7 = regout_sel_0_7 ? sinkC_req_index : _regout_idx_T_23; // @[Mux.scala:50:70] assign _regout_WIRE_7 = regout_idx_7; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_21 = regout_sel_3_7 ? sourceD_wreq_data_7 : 64'h0; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_22 = regout_sel_2_7 ? sinkD_req_data_7 : _regout_data_T_21; // @[Mux.scala:50:70] wire [63:0] _regout_data_T_23 = regout_sel_1_7 ? 64'h0 : _regout_data_T_22; // @[Mux.scala:50:70] wire [63:0] regout_data_7 = regout_sel_0_7 ? sinkC_req_data_7 : _regout_data_T_23; // @[Mux.scala:50:70] assign _regout_T_35 = regout_wen_7 & regout_en_7; // @[Mux.scala:50:70] wire _regout_T_36 = ~regout_wen_7; // @[Mux.scala:50:70] assign _regout_T_37 = _regout_T_36 & regout_en_7; // @[BankedStore.scala:165:45, :172:{27,32}] wire _regout_T_38 = ~regout_wen_7; // @[Mux.scala:50:70] wire _regout_T_39 = _regout_T_38 & regout_en_7; // @[BankedStore.scala:165:45, :172:{48,53}] reg regout_REG_7; // @[BankedStore.scala:172:47] reg [63:0] regout_r_7; // @[BankedStore.scala:172:14] wire [63:0] regout_7 = regout_r_7; // @[BankedStore.scala:164:23, :172:14] reg [7:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39] reg [7:0] regsel_sourceC; // @[BankedStore.scala:175:31] reg [7:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39] reg [7:0] regsel_sourceD; // @[BankedStore.scala:176:31] wire _decodeC_T = regsel_sourceC[0]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_1 = _decodeC_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_2 = regsel_sourceC[1]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_3 = _decodeC_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_4 = regsel_sourceC[2]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_5 = _decodeC_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_6 = regsel_sourceC[3]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_7 = _decodeC_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_8 = regsel_sourceC[4]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_9 = _decodeC_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_10 = regsel_sourceC[5]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_11 = _decodeC_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_12 = regsel_sourceC[6]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_13 = _decodeC_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire _decodeC_T_14 = regsel_sourceC[7]; // @[BankedStore.scala:175:31, :179:38] wire [63:0] _decodeC_T_15 = _decodeC_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}] wire [63:0] _decodeC_T_16 = _decodeC_T_1 | _decodeC_T_3; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_17 = _decodeC_T_16 | _decodeC_T_5; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_18 = _decodeC_T_17 | _decodeC_T_7; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_19 = _decodeC_T_18 | _decodeC_T_9; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_20 = _decodeC_T_19 | _decodeC_T_11; // @[BankedStore.scala:179:23, :180:85] wire [63:0] _decodeC_T_21 = _decodeC_T_20 | _decodeC_T_13; // @[BankedStore.scala:179:23, :180:85] assign decodeC_0 = _decodeC_T_21 | _decodeC_T_15; // @[BankedStore.scala:179:23, :180:85] assign io_sourceC_dat_data_0 = decodeC_0; // @[BankedStore.scala:59:7, :180:85] wire _decodeD_T = regsel_sourceD[0]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_1 = _decodeD_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_2 = regsel_sourceD[1]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_3 = _decodeD_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_4 = regsel_sourceD[2]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_5 = _decodeD_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_6 = regsel_sourceD[3]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_7 = _decodeD_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_8 = regsel_sourceD[4]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_9 = _decodeD_T_8 ? regout_4 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_10 = regsel_sourceD[5]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_11 = _decodeD_T_10 ? regout_5 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_12 = regsel_sourceD[6]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_13 = _decodeD_T_12 ? regout_6 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire _decodeD_T_14 = regsel_sourceD[7]; // @[BankedStore.scala:176:31, :186:38] wire [63:0] _decodeD_T_15 = _decodeD_T_14 ? regout_7 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}] wire [63:0] _decodeD_T_16 = _decodeD_T_1 | _decodeD_T_5; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_17 = _decodeD_T_16 | _decodeD_T_9; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_0 = _decodeD_T_17 | _decodeD_T_13; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_18 = _decodeD_T_3 | _decodeD_T_7; // @[BankedStore.scala:186:23, :187:85] wire [63:0] _decodeD_T_19 = _decodeD_T_18 | _decodeD_T_11; // @[BankedStore.scala:186:23, :187:85] wire [63:0] decodeD_1 = _decodeD_T_19 | _decodeD_T_15; // @[BankedStore.scala:186:23, :187:85] assign _io_sourceD_rdat_data_T = {decodeD_1, decodeD_0}; // @[BankedStore.scala:187:85, :189:30] assign io_sourceD_rdat_data_0 = _io_sourceD_rdat_data_T; // @[BankedStore.scala:59:7, :189:30] always @(posedge clock) begin // @[BankedStore.scala:59:7] regout_REG <= _regout_T_4; // @[BankedStore.scala:172:{47,53}] if (regout_REG) // @[BankedStore.scala:172:47] regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_1 <= _regout_T_9; // @[BankedStore.scala:172:{47,53}] if (regout_REG_1) // @[BankedStore.scala:172:47] regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_2 <= _regout_T_14; // @[BankedStore.scala:172:{47,53}] if (regout_REG_2) // @[BankedStore.scala:172:47] regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_3 <= _regout_T_19; // @[BankedStore.scala:172:{47,53}] if (regout_REG_3) // @[BankedStore.scala:172:47] regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_4 <= _regout_T_24; // @[BankedStore.scala:172:{47,53}] if (regout_REG_4) // @[BankedStore.scala:172:47] regout_r_4 <= _cc_banks_4_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_5 <= _regout_T_29; // @[BankedStore.scala:172:{47,53}] if (regout_REG_5) // @[BankedStore.scala:172:47] regout_r_5 <= _cc_banks_5_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_6 <= _regout_T_34; // @[BankedStore.scala:172:{47,53}] if (regout_REG_6) // @[BankedStore.scala:172:47] regout_r_6 <= _cc_banks_6_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_7 <= _regout_T_39; // @[BankedStore.scala:172:{47,53}] if (regout_REG_7) // @[BankedStore.scala:172:47] regout_r_7 <= _cc_banks_7_RW0_rdata; // @[DescribedSRAM.scala:17:26] regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:128:19, :175:39] regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}] regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:128:19, :176:39] regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}] always @(posedge) cc_banks_0 cc_banks_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T ? regout_idx : _regout_WIRE), // @[Mux.scala:50:70] .RW0_en (_regout_T_2 | _regout_T), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen), // @[Mux.scala:50:70] .RW0_wdata (regout_data), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_1 cc_banks_1 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_5 ? regout_idx_1 : _regout_WIRE_1), // @[Mux.scala:50:70] .RW0_en (_regout_T_7 | _regout_T_5), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_1), // @[Mux.scala:50:70] .RW0_wdata (regout_data_1), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_1_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_2 cc_banks_2 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_10 ? regout_idx_2 : _regout_WIRE_2), // @[Mux.scala:50:70] .RW0_en (_regout_T_12 | _regout_T_10), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_2), // @[Mux.scala:50:70] .RW0_wdata (regout_data_2), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_2_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_3 cc_banks_3 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_15 ? regout_idx_3 : _regout_WIRE_3), // @[Mux.scala:50:70] .RW0_en (_regout_T_17 | _regout_T_15), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_3), // @[Mux.scala:50:70] .RW0_wdata (regout_data_3), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_3_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_4 cc_banks_4 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_20 ? regout_idx_4 : _regout_WIRE_4), // @[Mux.scala:50:70] .RW0_en (_regout_T_22 | _regout_T_20), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_4), // @[Mux.scala:50:70] .RW0_wdata (regout_data_4), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_4_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_5 cc_banks_5 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_25 ? regout_idx_5 : _regout_WIRE_5), // @[Mux.scala:50:70] .RW0_en (_regout_T_27 | _regout_T_25), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_5), // @[Mux.scala:50:70] .RW0_wdata (regout_data_5), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_5_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_6 cc_banks_6 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_30 ? regout_idx_6 : _regout_WIRE_6), // @[Mux.scala:50:70] .RW0_en (_regout_T_32 | _regout_T_30), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_6), // @[Mux.scala:50:70] .RW0_wdata (regout_data_6), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_6_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] cc_banks_7 cc_banks_7 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (_regout_T_35 ? regout_idx_7 : _regout_WIRE_7), // @[Mux.scala:50:70] .RW0_en (_regout_T_37 | _regout_T_35), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (regout_wen_7), // @[Mux.scala:50:70] .RW0_wdata (regout_data_7), // @[Mux.scala:50:70] .RW0_rdata (_cc_banks_7_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] assign io_sinkC_adr_ready = io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sinkD_adr_ready = io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_adr_ready = io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceC_dat_data = io_sourceC_dat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_radr_ready = io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7] assign io_sourceD_rdat_data = io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7] assign io_sourceD_wadr_ready = io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_247 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_247( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_17 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_17(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_6 : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a32d256s5k3z4u_6( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [31:0] saved_address; // @[Repeater.scala:21:18] reg [31:0] saved_mask; // @[Repeater.scala:21:18] reg [255:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget16 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_2 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a29d128s6k1z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 3, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonOut_a_bits_data_mux : UInt<64>[2] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[2] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<4>(0hf), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[1], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<6>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<6>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<6>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [5:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25] wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25] wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24] wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25] wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23] anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] always @(posedge) TLMonitor_2 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleA_a29d128s6k1z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonIn_a_ready), .io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_address (cated_bits_address), .io_deq_bits_mask (cated_bits_mask), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_3 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T

module MulAddRecFNToRaw_preMul_e8_s24_3( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_387 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_387( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<13>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_70 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<13>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_71 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<13>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_86 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[20] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18]) node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = and(_T_11, _T_24) node _T_185 = and(_T_184, _T_37) node _T_186 = and(_T_185, _T_50) node _T_187 = and(_T_186, _T_63) node _T_188 = and(_T_187, _T_71) node _T_189 = and(_T_188, _T_79) node _T_190 = and(_T_189, _T_87) node _T_191 = and(_T_190, _T_95) node _T_192 = and(_T_191, _T_103) node _T_193 = and(_T_192, _T_111) node _T_194 = and(_T_193, _T_119) node _T_195 = and(_T_194, _T_127) node _T_196 = and(_T_195, _T_135) node _T_197 = and(_T_196, _T_143) node _T_198 = and(_T_197, _T_151) node _T_199 = and(_T_198, _T_159) node _T_200 = and(_T_199, _T_167) node _T_201 = and(_T_200, _T_175) node _T_202 = and(_T_201, _T_183) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_202, UInt<1>(0h1), "") : assert_1 node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_206 : node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_4) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<1>(0h1)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_5) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h2)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_6) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_229 = shr(io.in.a.bits.source, 2) node _T_230 = eq(_T_229, UInt<2>(0h3)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_7) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_250 = or(_T_210, _T_216) node _T_251 = or(_T_250, _T_222) node _T_252 = or(_T_251, _T_228) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_235) node _T_255 = or(_T_254, _T_236) node _T_256 = or(_T_255, _T_237) node _T_257 = or(_T_256, _T_238) node _T_258 = or(_T_257, _T_239) node _T_259 = or(_T_258, _T_240) node _T_260 = or(_T_259, _T_241) node _T_261 = or(_T_260, _T_242) node _T_262 = or(_T_261, _T_243) node _T_263 = or(_T_262, _T_244) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_246) node _T_266 = or(_T_265, _T_247) node _T_267 = or(_T_266, _T_248) node _T_268 = or(_T_267, _T_249) node _T_269 = and(_T_209, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<13>(0h1000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = and(_T_270, _T_278) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_279, UInt<1>(0h1), "") : assert_2 node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_8) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<1>(0h1)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_9) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h2)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_10) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<2>(0h3)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_11) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_317 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[20] connect _WIRE[0], _T_283 connect _WIRE[1], _T_289 connect _WIRE[2], _T_295 connect _WIRE[3], _T_301 connect _WIRE[4], _T_307 connect _WIRE[5], _T_308 connect _WIRE[6], _T_309 connect _WIRE[7], _T_310 connect _WIRE[8], _T_311 connect _WIRE[9], _T_312 connect _WIRE[10], _T_313 connect _WIRE[11], _T_314 connect _WIRE[12], _T_315 connect _WIRE[13], _T_316 connect _WIRE[14], _T_317 connect _WIRE[15], _T_318 connect _WIRE[16], _T_319 connect _WIRE[17], _T_320 connect _WIRE[18], _T_321 connect _WIRE[19], _T_322 node _T_323 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_324 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_325 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_326 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_327 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_328 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_329 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_331 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_332 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE[5], _T_323, UInt<1>(0h0)) node _T_335 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE[8], _T_324, UInt<1>(0h0)) node _T_338 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE[10], _T_325, UInt<1>(0h0)) node _T_340 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = mux(_WIRE[12], _T_326, UInt<1>(0h0)) node _T_342 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE[14], _T_327, UInt<1>(0h0)) node _T_344 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_345 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_346 = mux(_WIRE[17], _T_328, UInt<1>(0h0)) node _T_347 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_348 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_349 = or(_T_329, _T_330) node _T_350 = or(_T_349, _T_331) node _T_351 = or(_T_350, _T_332) node _T_352 = or(_T_351, _T_333) node _T_353 = or(_T_352, _T_334) node _T_354 = or(_T_353, _T_335) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_338) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_340) node _T_360 = or(_T_359, _T_341) node _T_361 = or(_T_360, _T_342) node _T_362 = or(_T_361, _T_343) node _T_363 = or(_T_362, _T_344) node _T_364 = or(_T_363, _T_345) node _T_365 = or(_T_364, _T_346) node _T_366 = or(_T_365, _T_347) node _T_367 = or(_T_366, _T_348) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_1, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_379, UInt<1>(0h1), "") : assert_3 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_386, UInt<1>(0h1), "") : assert_5 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_393, UInt<1>(0h1), "") : assert_7 node _T_397 = not(io.in.a.bits.mask) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_398, UInt<1>(0h1), "") : assert_8 node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_402, UInt<1>(0h1), "") : assert_9 node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_406 : node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<1>(0h0)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_12) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_417 = shr(io.in.a.bits.source, 2) node _T_418 = eq(_T_417, UInt<1>(0h1)) node _T_419 = leq(UInt<1>(0h0), uncommonBits_13) node _T_420 = and(_T_418, _T_419) node _T_421 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_422 = and(_T_420, _T_421) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_423 = shr(io.in.a.bits.source, 2) node _T_424 = eq(_T_423, UInt<2>(0h2)) node _T_425 = leq(UInt<1>(0h0), uncommonBits_14) node _T_426 = and(_T_424, _T_425) node _T_427 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_428 = and(_T_426, _T_427) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<2>(0h3)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_15) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_450 = or(_T_410, _T_416) node _T_451 = or(_T_450, _T_422) node _T_452 = or(_T_451, _T_428) node _T_453 = or(_T_452, _T_434) node _T_454 = or(_T_453, _T_435) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_437) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_439) node _T_459 = or(_T_458, _T_440) node _T_460 = or(_T_459, _T_441) node _T_461 = or(_T_460, _T_442) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_444) node _T_464 = or(_T_463, _T_445) node _T_465 = or(_T_464, _T_446) node _T_466 = or(_T_465, _T_447) node _T_467 = or(_T_466, _T_448) node _T_468 = or(_T_467, _T_449) node _T_469 = and(_T_409, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = and(_T_471, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_479, UInt<1>(0h1), "") : assert_10 node _T_483 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<1>(0h0)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_16) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<1>(0h1)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_17) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<2>(0h2)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_18) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<2>(0h3)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_19) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_510 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[20] connect _WIRE_2[0], _T_483 connect _WIRE_2[1], _T_489 connect _WIRE_2[2], _T_495 connect _WIRE_2[3], _T_501 connect _WIRE_2[4], _T_507 connect _WIRE_2[5], _T_508 connect _WIRE_2[6], _T_509 connect _WIRE_2[7], _T_510 connect _WIRE_2[8], _T_511 connect _WIRE_2[9], _T_512 connect _WIRE_2[10], _T_513 connect _WIRE_2[11], _T_514 connect _WIRE_2[12], _T_515 connect _WIRE_2[13], _T_516 connect _WIRE_2[14], _T_517 connect _WIRE_2[15], _T_518 connect _WIRE_2[16], _T_519 connect _WIRE_2[17], _T_520 connect _WIRE_2[18], _T_521 connect _WIRE_2[19], _T_522 node _T_523 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_526 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_527 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_528 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_529 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[5], _T_523, UInt<1>(0h0)) node _T_535 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_536 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_537 = mux(_WIRE_2[8], _T_524, UInt<1>(0h0)) node _T_538 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_539 = mux(_WIRE_2[10], _T_525, UInt<1>(0h0)) node _T_540 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_541 = mux(_WIRE_2[12], _T_526, UInt<1>(0h0)) node _T_542 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[14], _T_527, UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[17], _T_528, UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = or(_T_529, _T_530) node _T_550 = or(_T_549, _T_531) node _T_551 = or(_T_550, _T_532) node _T_552 = or(_T_551, _T_533) node _T_553 = or(_T_552, _T_534) node _T_554 = or(_T_553, _T_535) node _T_555 = or(_T_554, _T_536) node _T_556 = or(_T_555, _T_537) node _T_557 = or(_T_556, _T_538) node _T_558 = or(_T_557, _T_539) node _T_559 = or(_T_558, _T_540) node _T_560 = or(_T_559, _T_541) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_543) node _T_563 = or(_T_562, _T_544) node _T_564 = or(_T_563, _T_545) node _T_565 = or(_T_564, _T_546) node _T_566 = or(_T_565, _T_547) node _T_567 = or(_T_566, _T_548) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_567 node _T_568 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_569 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_570 = and(_T_568, _T_569) node _T_571 = or(UInt<1>(0h0), _T_570) node _T_572 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = and(_T_571, _T_576) node _T_578 = or(UInt<1>(0h0), _T_577) node _T_579 = and(_WIRE_3, _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_579, UInt<1>(0h1), "") : assert_11 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_586 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_586, UInt<1>(0h1), "") : assert_13 node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(is_aligned, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_593 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_593, UInt<1>(0h1), "") : assert_15 node _T_597 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_597, UInt<1>(0h1), "") : assert_16 node _T_601 = not(io.in.a.bits.mask) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_602, UInt<1>(0h1), "") : assert_17 node _T_606 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_607 = asUInt(reset) node _T_608 = eq(_T_607, UInt<1>(0h0)) when _T_608 : node _T_609 = eq(_T_606, UInt<1>(0h0)) when _T_609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_606, UInt<1>(0h1), "") : assert_18 node _T_610 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_610 : node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_615 = shr(io.in.a.bits.source, 2) node _T_616 = eq(_T_615, UInt<1>(0h0)) node _T_617 = leq(UInt<1>(0h0), uncommonBits_20) node _T_618 = and(_T_616, _T_617) node _T_619 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h1)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_21) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_626 = and(_T_624, _T_625) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_627 = shr(io.in.a.bits.source, 2) node _T_628 = eq(_T_627, UInt<2>(0h2)) node _T_629 = leq(UInt<1>(0h0), uncommonBits_22) node _T_630 = and(_T_628, _T_629) node _T_631 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_632 = and(_T_630, _T_631) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<2>(0h3)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_23) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_654 = or(_T_614, _T_620) node _T_655 = or(_T_654, _T_626) node _T_656 = or(_T_655, _T_632) node _T_657 = or(_T_656, _T_638) node _T_658 = or(_T_657, _T_639) node _T_659 = or(_T_658, _T_640) node _T_660 = or(_T_659, _T_641) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_643) node _T_663 = or(_T_662, _T_644) node _T_664 = or(_T_663, _T_645) node _T_665 = or(_T_664, _T_646) node _T_666 = or(_T_665, _T_647) node _T_667 = or(_T_666, _T_648) node _T_668 = or(_T_667, _T_649) node _T_669 = or(_T_668, _T_650) node _T_670 = or(_T_669, _T_651) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_653) node _T_673 = and(_T_613, _T_672) node _T_674 = or(UInt<1>(0h0), _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_674, UInt<1>(0h1), "") : assert_19 node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_680 = and(_T_678, _T_679) node _T_681 = or(UInt<1>(0h0), _T_680) node _T_682 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = and(_T_681, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_688, UInt<1>(0h1), "") : assert_20 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_698, UInt<1>(0h1), "") : assert_23 node _T_702 = eq(io.in.a.bits.mask, mask) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_702, UInt<1>(0h1), "") : assert_24 node _T_706 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_706, UInt<1>(0h1), "") : assert_25 node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_710 : node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_24) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_721 = shr(io.in.a.bits.source, 2) node _T_722 = eq(_T_721, UInt<1>(0h1)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_25) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_26) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_733 = shr(io.in.a.bits.source, 2) node _T_734 = eq(_T_733, UInt<2>(0h3)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_27) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_740 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_747 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_748 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_752 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_754 = or(_T_714, _T_720) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_732) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_739) node _T_759 = or(_T_758, _T_740) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_743) node _T_763 = or(_T_762, _T_744) node _T_764 = or(_T_763, _T_745) node _T_765 = or(_T_764, _T_746) node _T_766 = or(_T_765, _T_747) node _T_767 = or(_T_766, _T_748) node _T_768 = or(_T_767, _T_749) node _T_769 = or(_T_768, _T_750) node _T_770 = or(_T_769, _T_751) node _T_771 = or(_T_770, _T_752) node _T_772 = or(_T_771, _T_753) node _T_773 = and(_T_713, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_776 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = and(_T_778, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = and(_T_774, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_786, UInt<1>(0h1), "") : assert_26 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_796 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_796, UInt<1>(0h1), "") : assert_29 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_800, UInt<1>(0h1), "") : assert_30 node _T_804 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_28) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_29) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_30) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_31) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_847 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_848 = or(_T_808, _T_814) node _T_849 = or(_T_848, _T_820) node _T_850 = or(_T_849, _T_826) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_833) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_835) node _T_855 = or(_T_854, _T_836) node _T_856 = or(_T_855, _T_837) node _T_857 = or(_T_856, _T_838) node _T_858 = or(_T_857, _T_839) node _T_859 = or(_T_858, _T_840) node _T_860 = or(_T_859, _T_841) node _T_861 = or(_T_860, _T_842) node _T_862 = or(_T_861, _T_843) node _T_863 = or(_T_862, _T_844) node _T_864 = or(_T_863, _T_845) node _T_865 = or(_T_864, _T_846) node _T_866 = or(_T_865, _T_847) node _T_867 = and(_T_807, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_870 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _T_872 = or(UInt<1>(0h0), _T_871) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_880, UInt<1>(0h1), "") : assert_31 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_890, UInt<1>(0h1), "") : assert_34 node _T_894 = not(mask) node _T_895 = and(io.in.a.bits.mask, _T_894) node _T_896 = eq(_T_895, UInt<1>(0h0)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_896, UInt<1>(0h1), "") : assert_35 node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_32) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_33) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_34) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_35) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_933 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_936 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_939 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_942 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_943 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_944 = or(_T_904, _T_910) node _T_945 = or(_T_944, _T_916) node _T_946 = or(_T_945, _T_922) node _T_947 = or(_T_946, _T_928) node _T_948 = or(_T_947, _T_929) node _T_949 = or(_T_948, _T_930) node _T_950 = or(_T_949, _T_931) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_933) node _T_953 = or(_T_952, _T_934) node _T_954 = or(_T_953, _T_935) node _T_955 = or(_T_954, _T_936) node _T_956 = or(_T_955, _T_937) node _T_957 = or(_T_956, _T_938) node _T_958 = or(_T_957, _T_939) node _T_959 = or(_T_958, _T_940) node _T_960 = or(_T_959, _T_941) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_943) node _T_963 = and(_T_903, _T_962) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_966 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = and(_T_965, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = and(_T_964, _T_972) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_973, UInt<1>(0h1), "") : assert_36 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(source_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(is_aligned, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_983 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_983, UInt<1>(0h1), "") : assert_39 node _T_987 = eq(io.in.a.bits.mask, mask) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_987, UInt<1>(0h1), "") : assert_40 node _T_991 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_991 : node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_994 = and(_T_992, _T_993) node _T_995 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<1>(0h0)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_36) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1002 = shr(io.in.a.bits.source, 2) node _T_1003 = eq(_T_1002, UInt<1>(0h1)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1007 = and(_T_1005, _T_1006) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1008 = shr(io.in.a.bits.source, 2) node _T_1009 = eq(_T_1008, UInt<2>(0h2)) node _T_1010 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1013 = and(_T_1011, _T_1012) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1014 = shr(io.in.a.bits.source, 2) node _T_1015 = eq(_T_1014, UInt<2>(0h3)) node _T_1016 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1034 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1035 = or(_T_995, _T_1001) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1013) node _T_1038 = or(_T_1037, _T_1019) node _T_1039 = or(_T_1038, _T_1020) node _T_1040 = or(_T_1039, _T_1021) node _T_1041 = or(_T_1040, _T_1022) node _T_1042 = or(_T_1041, _T_1023) node _T_1043 = or(_T_1042, _T_1024) node _T_1044 = or(_T_1043, _T_1025) node _T_1045 = or(_T_1044, _T_1026) node _T_1046 = or(_T_1045, _T_1027) node _T_1047 = or(_T_1046, _T_1028) node _T_1048 = or(_T_1047, _T_1029) node _T_1049 = or(_T_1048, _T_1030) node _T_1050 = or(_T_1049, _T_1031) node _T_1051 = or(_T_1050, _T_1032) node _T_1052 = or(_T_1051, _T_1033) node _T_1053 = or(_T_1052, _T_1034) node _T_1054 = and(_T_994, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1057 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1058 = cvt(_T_1057) node _T_1059 = and(_T_1058, asSInt(UInt<13>(0h1000))) node _T_1060 = asSInt(_T_1059) node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0))) node _T_1062 = and(_T_1056, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1055, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_41 node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(is_aligned, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1074 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_44 node _T_1078 = eq(io.in.a.bits.mask, mask) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_45 node _T_1082 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1082 : node _T_1083 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1084 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h1)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<2>(0h2)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1125 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1126 = or(_T_1086, _T_1092) node _T_1127 = or(_T_1126, _T_1098) node _T_1128 = or(_T_1127, _T_1104) node _T_1129 = or(_T_1128, _T_1110) node _T_1130 = or(_T_1129, _T_1111) node _T_1131 = or(_T_1130, _T_1112) node _T_1132 = or(_T_1131, _T_1113) node _T_1133 = or(_T_1132, _T_1114) node _T_1134 = or(_T_1133, _T_1115) node _T_1135 = or(_T_1134, _T_1116) node _T_1136 = or(_T_1135, _T_1117) node _T_1137 = or(_T_1136, _T_1118) node _T_1138 = or(_T_1137, _T_1119) node _T_1139 = or(_T_1138, _T_1120) node _T_1140 = or(_T_1139, _T_1121) node _T_1141 = or(_T_1140, _T_1122) node _T_1142 = or(_T_1141, _T_1123) node _T_1143 = or(_T_1142, _T_1124) node _T_1144 = or(_T_1143, _T_1125) node _T_1145 = and(_T_1085, _T_1144) node _T_1146 = or(UInt<1>(0h0), _T_1145) node _T_1147 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = and(_T_1147, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = and(_T_1146, _T_1154) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46 node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(is_aligned, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49 node _T_1169 = eq(io.in.a.bits.mask, mask) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50 node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52 node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_59 = shr(io.in.d.bits.source, 2) node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0)) node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[20] connect _source_ok_WIRE_1[0], _source_ok_T_58 connect _source_ok_WIRE_1[1], _source_ok_T_64 connect _source_ok_WIRE_1[2], _source_ok_T_70 connect _source_ok_WIRE_1[3], _source_ok_T_76 connect _source_ok_WIRE_1[4], _source_ok_T_82 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 connect _source_ok_WIRE_1[10], _source_ok_T_88 connect _source_ok_WIRE_1[11], _source_ok_T_89 connect _source_ok_WIRE_1[12], _source_ok_T_90 connect _source_ok_WIRE_1[13], _source_ok_T_91 connect _source_ok_WIRE_1[14], _source_ok_T_92 connect _source_ok_WIRE_1[15], _source_ok_T_93 connect _source_ok_WIRE_1[16], _source_ok_T_94 connect _source_ok_WIRE_1[17], _source_ok_T_95 connect _source_ok_WIRE_1[18], _source_ok_T_96 connect _source_ok_WIRE_1[19], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18]) node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1181 : node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(source_ok_1, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54 node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55 node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56 node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57 node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1201 : node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(source_ok_1, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(sink_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60 node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61 node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62 node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63 node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1225 = or(UInt<1>(0h0), _T_1224) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64 node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1229 : node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(source_ok_1, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(sink_ok, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67 node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68 node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69 node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1249 = or(_T_1248, io.in.d.bits.corrupt) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70 node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1254 = or(UInt<1>(0h0), _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71 node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1258 : node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(source_ok_1, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73 node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74 node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1271 = or(UInt<1>(0h0), _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75 node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1275 : node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(source_ok_1, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77 node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1284 = or(_T_1283, io.in.d.bits.corrupt) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78 node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1289 = or(UInt<1>(0h0), _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79 node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1293 : node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(source_ok_1, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81 node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82 node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1306 = or(UInt<1>(0h0), _T_1305) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1322 = eq(a_first, UInt<1>(0h0)) node _T_1323 = and(io.in.a.valid, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.a.bits.opcode, opcode) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87 node _T_1328 = eq(io.in.a.bits.param, param) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88 node _T_1332 = eq(io.in.a.bits.size, size) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89 node _T_1336 = eq(io.in.a.bits.source, source) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90 node _T_1340 = eq(io.in.a.bits.address, address) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91 node _T_1344 = and(io.in.a.ready, io.in.a.valid) node _T_1345 = and(_T_1344, a_first) when _T_1345 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1346 = eq(d_first, UInt<1>(0h0)) node _T_1347 = and(io.in.d.valid, _T_1346) when _T_1347 : node _T_1348 = eq(io.in.d.bits.opcode, opcode_1) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92 node _T_1352 = eq(io.in.d.bits.param, param_1) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93 node _T_1356 = eq(io.in.d.bits.size, size_1) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94 node _T_1360 = eq(io.in.d.bits.source, source_1) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95 node _T_1364 = eq(io.in.d.bits.sink, sink) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96 node _T_1368 = eq(io.in.d.bits.denied, denied) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97 node _T_1372 = and(io.in.d.ready, io.in.d.valid) node _T_1373 = and(_T_1372, d_first) when _T_1373 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1374 = and(io.in.a.valid, a_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) when _T_1375 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1376 = and(io.in.a.ready, io.in.a.valid) node _T_1377 = and(_T_1376, a_first_1) node _T_1378 = and(_T_1377, UInt<1>(0h1)) when _T_1378 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1379 = dshr(inflight, io.in.a.bits.source) node _T_1380 = bits(_T_1379, 0, 0) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1385 = and(io.in.d.valid, d_first_1) node _T_1386 = and(_T_1385, UInt<1>(0h1)) node _T_1387 = eq(d_release_ack, UInt<1>(0h0)) node _T_1388 = and(_T_1386, _T_1387) when _T_1388 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1389 = and(io.in.d.ready, io.in.d.valid) node _T_1390 = and(_T_1389, d_first_1) node _T_1391 = and(_T_1390, UInt<1>(0h1)) node _T_1392 = eq(d_release_ack, UInt<1>(0h0)) node _T_1393 = and(_T_1391, _T_1392) when _T_1393 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1394 = and(io.in.d.valid, d_first_1) node _T_1395 = and(_T_1394, UInt<1>(0h1)) node _T_1396 = eq(d_release_ack, UInt<1>(0h0)) node _T_1397 = and(_T_1395, _T_1396) when _T_1397 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1398 = dshr(inflight, io.in.d.bits.source) node _T_1399 = bits(_T_1398, 0, 0) node _T_1400 = or(_T_1399, same_cycle_resp) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100 node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101 else : node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1416 = or(_T_1414, _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102 node _T_1420 = eq(io.in.d.bits.size, a_size_lookup) node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(_T_1420, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103 node _T_1424 = and(io.in.d.valid, d_first_1) node _T_1425 = and(_T_1424, a_first_1) node _T_1426 = and(_T_1425, io.in.a.valid) node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1428 = and(_T_1426, _T_1427) node _T_1429 = eq(d_release_ack, UInt<1>(0h0)) node _T_1430 = and(_T_1428, _T_1429) when _T_1430 : node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1432 = or(_T_1431, io.in.a.ready) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104 node _T_1436 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1437 = orr(a_set_wo_ready) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) node _T_1439 = or(_T_1436, _T_1438) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_175 node _T_1443 = orr(inflight) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) node _T_1445 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1446 = or(_T_1444, _T_1445) node _T_1447 = lt(watchdog, plusarg_reader.out) node _T_1448 = or(_T_1446, _T_1447) node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(_T_1448, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1448, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1452 = and(io.in.a.ready, io.in.a.valid) node _T_1453 = and(io.in.d.ready, io.in.d.valid) node _T_1454 = or(_T_1452, _T_1453) when _T_1454 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1455 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1456 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1457 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1458 = and(_T_1456, _T_1457) node _T_1459 = and(_T_1455, _T_1458) when _T_1459 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1460 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1461 = and(_T_1460, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1462 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1463 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = and(_T_1461, _T_1464) when _T_1465 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1466 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1467 = bits(_T_1466, 0, 0) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1472 = and(io.in.d.valid, d_first_2) node _T_1473 = and(_T_1472, UInt<1>(0h1)) node _T_1474 = and(_T_1473, d_release_ack_1) when _T_1474 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1475 = and(io.in.d.ready, io.in.d.valid) node _T_1476 = and(_T_1475, d_first_2) node _T_1477 = and(_T_1476, UInt<1>(0h1)) node _T_1478 = and(_T_1477, d_release_ack_1) when _T_1478 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1479 = and(io.in.d.valid, d_first_2) node _T_1480 = and(_T_1479, UInt<1>(0h1)) node _T_1481 = and(_T_1480, d_release_ack_1) when _T_1481 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1482 = dshr(inflight_1, io.in.d.bits.source) node _T_1483 = bits(_T_1482, 0, 0) node _T_1484 = or(_T_1483, same_cycle_resp_1) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1488 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_109 else : node _T_1492 = eq(io.in.d.bits.size, c_size_lookup) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_110 node _T_1496 = and(io.in.d.valid, d_first_2) node _T_1497 = and(_T_1496, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1498 = and(_T_1497, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1499 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = and(_T_1500, d_release_ack_1) node _T_1502 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1503 = and(_T_1501, _T_1502) when _T_1503 : node _T_1504 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1505 = or(_T_1504, _WIRE_27.ready) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_111 node _T_1509 = orr(c_set_wo_ready) when _T_1509 : node _T_1510 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_176 node _T_1514 = orr(inflight_1) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) node _T_1516 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1517 = or(_T_1515, _T_1516) node _T_1518 = lt(watchdog_1, plusarg_reader_1.out) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1523 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1524 = and(io.in.d.ready, io.in.d.valid) node _T_1525 = or(_T_1523, _T_1524) when _T_1525 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_86( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_57 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_111 = _source_ok_T_110 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_115 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _T_1452 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1452; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1452; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1525; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1378 = _T_1452 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1496 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1496 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1478 = _T_1525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1478 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1478 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1478 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_54 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)

module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_54 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NullLocalBranchPredictorBank_1 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, f1_lhist : UInt<1>, f3_lhist : UInt<1>, flip f3_taken_br : UInt<1>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, mispredict : UInt<1>, repair : UInt<1>, pc : UInt<40>, lhist : UInt<1>}} connect io.f1_lhist, UInt<1>(0h0) connect io.f3_lhist, UInt<1>(0h0)

module NullLocalBranchPredictorBank_1( // @[local.scala:38:7] input clock, // @[local.scala:38:7] input reset, // @[local.scala:38:7] input io_f0_valid, // @[local.scala:17:14] input [39:0] io_f0_pc, // @[local.scala:17:14] input io_f3_taken_br, // @[local.scala:17:14] input io_f3_fire, // @[local.scala:17:14] input io_update_valid, // @[local.scala:17:14] input io_update_mispredict, // @[local.scala:17:14] input io_update_repair, // @[local.scala:17:14] input [39:0] io_update_pc, // @[local.scala:17:14] input io_update_lhist // @[local.scala:17:14] ); wire io_f0_valid_0 = io_f0_valid; // @[local.scala:38:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[local.scala:38:7] wire io_f3_taken_br_0 = io_f3_taken_br; // @[local.scala:38:7] wire io_f3_fire_0 = io_f3_fire; // @[local.scala:38:7] wire io_update_valid_0 = io_update_valid; // @[local.scala:38:7] wire io_update_mispredict_0 = io_update_mispredict; // @[local.scala:38:7] wire io_update_repair_0 = io_update_repair; // @[local.scala:38:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[local.scala:38:7] wire io_update_lhist_0 = io_update_lhist; // @[local.scala:38:7] wire io_f1_lhist = 1'h0; // @[local.scala:38:7] wire io_f3_lhist = 1'h0; // @[local.scala:38:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_185 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_185( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_16 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_16( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_84 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_84( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_15 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 9, 6) node req_tag = shr(req.addr, 10) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_16 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock reg refill_ctr : UInt<3>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) invalidate io.meta_write.bits.data.tag invalidate io.meta_write.bits.data.coh.state invalidate io.meta_write.bits.tag invalidate io.meta_write.bits.way_en invalidate io.meta_write.bits.idx connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) invalidate io.mem_acquire.bits.corrupt invalidate io.mem_acquire.bits.data invalidate io.mem_acquire.bits.mask invalidate io.mem_acquire.bits.address invalidate io.mem_acquire.bits.source invalidate io.mem_acquire.bits.size invalidate io.mem_acquire.bits.param invalidate io.mem_acquire.bits.opcode connect io.refill.valid, UInt<1>(0h0) invalidate io.refill.bits.data invalidate io.refill.bits.wmask invalidate io.refill.bits.addr invalidate io.refill.bits.way_en connect io.replay.valid, UInt<1>(0h0) invalidate io.replay.bits.sdq_id invalidate io.replay.bits.way_en invalidate io.replay.bits.old_meta.tag invalidate io.replay.bits.old_meta.coh.state invalidate io.replay.bits.tag_match invalidate io.replay.bits.is_hella invalidate io.replay.bits.data invalidate io.replay.bits.addr invalidate io.replay.bits.uop.debug_tsrc invalidate io.replay.bits.uop.debug_fsrc invalidate io.replay.bits.uop.bp_xcpt_if invalidate io.replay.bits.uop.bp_debug_if invalidate io.replay.bits.uop.xcpt_ma_if invalidate io.replay.bits.uop.xcpt_ae_if invalidate io.replay.bits.uop.xcpt_pf_if invalidate io.replay.bits.uop.fp_single invalidate io.replay.bits.uop.fp_val invalidate io.replay.bits.uop.frs3_en invalidate io.replay.bits.uop.lrs2_rtype invalidate io.replay.bits.uop.lrs1_rtype invalidate io.replay.bits.uop.dst_rtype invalidate io.replay.bits.uop.ldst_val invalidate io.replay.bits.uop.lrs3 invalidate io.replay.bits.uop.lrs2 invalidate io.replay.bits.uop.lrs1 invalidate io.replay.bits.uop.ldst invalidate io.replay.bits.uop.ldst_is_rs1 invalidate io.replay.bits.uop.flush_on_commit invalidate io.replay.bits.uop.is_unique invalidate io.replay.bits.uop.is_sys_pc2epc invalidate io.replay.bits.uop.uses_stq invalidate io.replay.bits.uop.uses_ldq invalidate io.replay.bits.uop.is_amo invalidate io.replay.bits.uop.is_fencei invalidate io.replay.bits.uop.is_fence invalidate io.replay.bits.uop.mem_signed invalidate io.replay.bits.uop.mem_size invalidate io.replay.bits.uop.mem_cmd invalidate io.replay.bits.uop.bypassable invalidate io.replay.bits.uop.exc_cause invalidate io.replay.bits.uop.exception invalidate io.replay.bits.uop.stale_pdst invalidate io.replay.bits.uop.ppred_busy invalidate io.replay.bits.uop.prs3_busy invalidate io.replay.bits.uop.prs2_busy invalidate io.replay.bits.uop.prs1_busy invalidate io.replay.bits.uop.ppred invalidate io.replay.bits.uop.prs3 invalidate io.replay.bits.uop.prs2 invalidate io.replay.bits.uop.prs1 invalidate io.replay.bits.uop.pdst invalidate io.replay.bits.uop.rxq_idx invalidate io.replay.bits.uop.stq_idx invalidate io.replay.bits.uop.ldq_idx invalidate io.replay.bits.uop.rob_idx invalidate io.replay.bits.uop.csr_addr invalidate io.replay.bits.uop.imm_packed invalidate io.replay.bits.uop.taken invalidate io.replay.bits.uop.pc_lob invalidate io.replay.bits.uop.edge_inst invalidate io.replay.bits.uop.ftq_idx invalidate io.replay.bits.uop.br_tag invalidate io.replay.bits.uop.br_mask invalidate io.replay.bits.uop.is_sfb invalidate io.replay.bits.uop.is_jal invalidate io.replay.bits.uop.is_jalr invalidate io.replay.bits.uop.is_br invalidate io.replay.bits.uop.iw_p2_poisoned invalidate io.replay.bits.uop.iw_p1_poisoned invalidate io.replay.bits.uop.iw_state invalidate io.replay.bits.uop.ctrl.is_std invalidate io.replay.bits.uop.ctrl.is_sta invalidate io.replay.bits.uop.ctrl.is_load invalidate io.replay.bits.uop.ctrl.csr_cmd invalidate io.replay.bits.uop.ctrl.fcn_dw invalidate io.replay.bits.uop.ctrl.op_fcn invalidate io.replay.bits.uop.ctrl.imm_sel invalidate io.replay.bits.uop.ctrl.op2_sel invalidate io.replay.bits.uop.ctrl.op1_sel invalidate io.replay.bits.uop.ctrl.br_type invalidate io.replay.bits.uop.fu_code invalidate io.replay.bits.uop.iq_type invalidate io.replay.bits.uop.debug_pc invalidate io.replay.bits.uop.is_rvc invalidate io.replay.bits.uop.debug_inst invalidate io.replay.bits.uop.inst invalidate io.replay.bits.uop.uopc connect io.wb_req.valid, UInt<1>(0h0) invalidate io.wb_req.bits.voluntary invalidate io.wb_req.bits.way_en invalidate io.wb_req.bits.param invalidate io.wb_req.bits.source invalidate io.wb_req.bits.idx invalidate io.wb_req.bits.tag connect io.resp.valid, UInt<1>(0h0) invalidate io.resp.bits.is_hella invalidate io.resp.bits.data invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_single invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.ldst_val invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.bypassable invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.csr_addr invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.is_jal invalidate io.resp.bits.uop.is_jalr invalidate io.resp.bits.uop.is_br invalidate io.resp.bits.uop.iw_p2_poisoned invalidate io.resp.bits.uop.iw_p1_poisoned invalidate io.resp.bits.uop.iw_state invalidate io.resp.bits.uop.ctrl.is_std invalidate io.resp.bits.uop.ctrl.is_sta invalidate io.resp.bits.uop.ctrl.is_load invalidate io.resp.bits.uop.ctrl.csr_cmd invalidate io.resp.bits.uop.ctrl.fcn_dw invalidate io.resp.bits.uop.ctrl.op_fcn invalidate io.resp.bits.uop.ctrl.imm_sel invalidate io.resp.bits.uop.ctrl.op2_sel invalidate io.resp.bits.uop.ctrl.op1_sel invalidate io.resp.bits.uop.ctrl.br_type invalidate io.resp.bits.uop.fu_code invalidate io.resp.bits.uop.iq_type invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.uop.uopc connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) invalidate io.meta_read.bits.tag invalidate io.meta_read.bits.way_en invalidate io.meta_read.bits.idx connect io.mem_finish.valid, UInt<1>(0h0) invalidate io.mem_finish.bits.sink connect io.lb_write.valid, UInt<1>(0h0) invalidate io.lb_write.bits.data invalidate io.lb_write.bits.offset invalidate io.lb_write.bits.id connect io.lb_read.valid, UInt<1>(0h0) invalidate io.lb_read.bits.offset invalidate io.lb_read.bits.id connect io.mem_grant.ready, UInt<1>(0h0) node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5) node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7) node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9) node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.mem_grant.ready, io.lb_write.ready connect io.lb_write.valid, io.mem_grant.valid connect io.lb_write.bits.id, io.id node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<3>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready) node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1 node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load) connect io.lb_read.valid, _io_lb_read_valid_T connect io.lb_read.bits.id, io.id node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid) node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T) node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load) connect io.resp.valid, _io_resp_valid_T_2 connect io.resp.bits.uop, rpq.io.deq.bits.uop node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.valid, UInt<1>(0h1) connect io.lb_read.bits.id, io.id connect io.lb_read.bits.offset, refill_ctr node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid) connect io.refill.valid, _io_refill_valid_T node _io_refill_bits_addr_T = shl(refill_ctr, 3) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<1>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<3>(0h7)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid connect io.mem_finish.bits, grantack.bits node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1

module BoomMSHR_15( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h7; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h7; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h7; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h7; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h7; // @[mshrs.scala:36:7] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h7; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = |state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = |state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_fbus_i2_o1_a32d64s5k6z4u : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_22 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_23 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<5>(0h10)) connect in[0].a.bits.source, _in_0_a_bits_source_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready invalidate _WIRE_3.bits.corrupt invalidate _WIRE_3.bits.data invalidate _WIRE_3.bits.mask invalidate _WIRE_3.bits.address invalidate _WIRE_3.bits.source invalidate _WIRE_3.bits.size invalidate _WIRE_3.bits.param invalidate _WIRE_3.bits.opcode invalidate _WIRE_3.valid invalidate _WIRE_3.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.valid, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.corrupt invalidate _WIRE_9.bits.data invalidate _WIRE_9.bits.address invalidate _WIRE_9.bits.source invalidate _WIRE_9.bits.size invalidate _WIRE_9.bits.param invalidate _WIRE_9.bits.opcode invalidate _WIRE_9.valid invalidate _WIRE_9.ready wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready invalidate _WIRE_11.bits.corrupt invalidate _WIRE_11.bits.data invalidate _WIRE_11.bits.address invalidate _WIRE_11.bits.source invalidate _WIRE_11.bits.size invalidate _WIRE_11.bits.param invalidate _WIRE_11.bits.opcode invalidate _WIRE_11.valid invalidate _WIRE_11.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready connect anonIn.d.bits.source, UInt<1>(0h0) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_16.bits.sink, UInt<6>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.sink invalidate _WIRE_17.valid invalidate _WIRE_17.ready wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_18.bits.sink, UInt<6>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready invalidate _WIRE_19.bits.sink invalidate _WIRE_19.valid invalidate _WIRE_19.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_20.bits.sink, UInt<6>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_22.bits.sink, UInt<6>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) connect in[1].a.bits.source, _in_1_a_bits_source_T wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<4>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready invalidate _WIRE_27.bits.corrupt invalidate _WIRE_27.bits.data invalidate _WIRE_27.bits.mask invalidate _WIRE_27.bits.address invalidate _WIRE_27.bits.source invalidate _WIRE_27.bits.size invalidate _WIRE_27.bits.param invalidate _WIRE_27.bits.opcode invalidate _WIRE_27.valid invalidate _WIRE_27.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.mask, UInt<8>(0h0) connect _WIRE_28.bits.address, UInt<32>(0h0) connect _WIRE_28.bits.source, UInt<5>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<2>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<4>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<5>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.corrupt invalidate _WIRE_33.bits.data invalidate _WIRE_33.bits.address invalidate _WIRE_33.bits.source invalidate _WIRE_33.bits.size invalidate _WIRE_33.bits.param invalidate _WIRE_33.bits.opcode invalidate _WIRE_33.valid invalidate _WIRE_33.ready wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_34.bits.corrupt, UInt<1>(0h0) connect _WIRE_34.bits.data, UInt<64>(0h0) connect _WIRE_34.bits.address, UInt<32>(0h0) connect _WIRE_34.bits.source, UInt<4>(0h0) connect _WIRE_34.bits.size, UInt<4>(0h0) connect _WIRE_34.bits.param, UInt<3>(0h0) connect _WIRE_34.bits.opcode, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready invalidate _WIRE_35.bits.corrupt invalidate _WIRE_35.bits.data invalidate _WIRE_35.bits.address invalidate _WIRE_35.bits.source invalidate _WIRE_35.bits.size invalidate _WIRE_35.bits.param invalidate _WIRE_35.bits.opcode invalidate _WIRE_35.valid invalidate _WIRE_35.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<5>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<3>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<4>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T = bits(in[1].d.bits.source, 3, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_40.bits.sink, UInt<6>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready invalidate _WIRE_41.bits.sink invalidate _WIRE_41.valid invalidate _WIRE_41.ready wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_42.bits.sink, UInt<6>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready invalidate _WIRE_43.bits.sink invalidate _WIRE_43.valid invalidate _WIRE_43.ready wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_44.bits.sink, UInt<6>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_46.bits.sink, UInt<6>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<5>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready invalidate _WIRE_49.bits.corrupt invalidate _WIRE_49.bits.data invalidate _WIRE_49.bits.mask invalidate _WIRE_49.bits.address invalidate _WIRE_49.bits.source invalidate _WIRE_49.bits.size invalidate _WIRE_49.bits.param invalidate _WIRE_49.bits.opcode invalidate _WIRE_49.valid invalidate _WIRE_49.ready wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.mask, UInt<8>(0h0) connect _WIRE_50.bits.address, UInt<32>(0h0) connect _WIRE_50.bits.source, UInt<5>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<2>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready invalidate _WIRE_51.bits.corrupt invalidate _WIRE_51.bits.data invalidate _WIRE_51.bits.mask invalidate _WIRE_51.bits.address invalidate _WIRE_51.bits.source invalidate _WIRE_51.bits.size invalidate _WIRE_51.bits.param invalidate _WIRE_51.bits.opcode invalidate _WIRE_51.valid invalidate _WIRE_51.ready wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_52.bits.corrupt, UInt<1>(0h0) connect _WIRE_52.bits.data, UInt<64>(0h0) connect _WIRE_52.bits.mask, UInt<8>(0h0) connect _WIRE_52.bits.address, UInt<32>(0h0) connect _WIRE_52.bits.source, UInt<5>(0h0) connect _WIRE_52.bits.size, UInt<4>(0h0) connect _WIRE_52.bits.param, UInt<2>(0h0) connect _WIRE_52.bits.opcode, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.valid, UInt<1>(0h0) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<32>(0h0) connect _WIRE_54.bits.source, UInt<5>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<5>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready invalidate _WIRE_57.bits.corrupt invalidate _WIRE_57.bits.data invalidate _WIRE_57.bits.address invalidate _WIRE_57.bits.source invalidate _WIRE_57.bits.size invalidate _WIRE_57.bits.param invalidate _WIRE_57.bits.opcode invalidate _WIRE_57.valid invalidate _WIRE_57.ready wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_58.bits.corrupt, UInt<1>(0h0) connect _WIRE_58.bits.data, UInt<64>(0h0) connect _WIRE_58.bits.address, UInt<32>(0h0) connect _WIRE_58.bits.source, UInt<5>(0h0) connect _WIRE_58.bits.size, UInt<4>(0h0) connect _WIRE_58.bits.param, UInt<3>(0h0) connect _WIRE_58.bits.opcode, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready invalidate _WIRE_59.bits.corrupt invalidate _WIRE_59.bits.data invalidate _WIRE_59.bits.address invalidate _WIRE_59.bits.source invalidate _WIRE_59.bits.size invalidate _WIRE_59.bits.param invalidate _WIRE_59.bits.opcode invalidate _WIRE_59.valid invalidate _WIRE_59.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<5>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<3>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.ready, UInt<1>(0h1) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<32>(0h0) connect _WIRE_62.bits.source, UInt<5>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_64.bits.sink, UInt<6>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready invalidate _WIRE_65.bits.sink invalidate _WIRE_65.valid invalidate _WIRE_65.ready wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_66.bits.sink, UInt<6>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready invalidate _WIRE_67.bits.sink invalidate _WIRE_67.valid invalidate _WIRE_67.ready wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_68.bits.sink, UInt<6>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.ready, UInt<1>(0h1) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_70.bits.sink, UInt<6>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE.bits.data, UInt<64>(0h0) connect _addressC_WIRE.bits.address, UInt<32>(0h0) connect _addressC_WIRE.bits.source, UInt<5>(0h0) connect _addressC_WIRE.bits.size, UInt<4>(0h0) connect _addressC_WIRE.bits.param, UInt<3>(0h0) connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE.valid, UInt<1>(0h0) connect _addressC_WIRE.ready, UInt<1>(0h0) wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_1.bits, _addressC_WIRE.bits connect _addressC_WIRE_1.valid, _addressC_WIRE.valid connect _addressC_WIRE_1.ready, _addressC_WIRE.ready wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _addressC_WIRE_2.bits.data, UInt<64>(0h0) connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) connect _addressC_WIRE_2.bits.source, UInt<5>(0h0) connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) connect _addressC_WIRE_2.valid, UInt<1>(0h0) connect _addressC_WIRE_2.ready, UInt<1>(0h0) wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE.valid, UInt<1>(0h0) connect _requestBOI_WIRE.ready, UInt<1>(0h0) wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<5>(0h10)) wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0) connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0) connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0) connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_3.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 3, 0) node _requestBOI_T = shr(_requestBOI_WIRE_3.bits.source, 4) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<4>(0hf)) node requestBOI_0_1 = and(_requestBOI_T_3, _requestBOI_T_4) node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<5>(0h10)) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 3, 0) node _requestDOI_T = shr(out[0].d.bits.source, 4) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<4>(0hf)) node requestDOI_0_1 = and(_requestDOI_T_3, _requestDOI_T_4) wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE.bits.sink, UInt<6>(0h0) connect _requestEIO_WIRE.valid, UInt<1>(0h0) connect _requestEIO_WIRE.ready, UInt<1>(0h0) wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_1.bits.sink, UInt<6>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 5, 0) node _requestEIO_T = shr(_requestEIO_WIRE_1.bits.sink, 6) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<6>(0h3f)) node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_2.bits.sink, UInt<6>(0h0) connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_3.bits.sink, UInt<6>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 5, 0) node _requestEIO_T_5 = shr(_requestEIO_WIRE_3.bits.sink, 6) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<6>(0h3f)) node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsBO_WIRE.bits.data, UInt<64>(0h0) connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0) connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) connect _beatsBO_WIRE.bits.source, UInt<5>(0h0) connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsBO_WIRE.valid, UInt<1>(0h0) connect _beatsBO_WIRE.ready, UInt<1>(0h0) wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE.valid, UInt<1>(0h0) connect _beatsCI_WIRE.ready, UInt<1>(0h0) wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0) connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) connect _beatsCI_WIRE_2.bits.source, UInt<5>(0h0) connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE.bits.sink, UInt<6>(0h0) connect _beatsEI_WIRE.valid, UInt<1>(0h0) connect _beatsEI_WIRE.ready, UInt<1>(0h0) wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_2.bits.sink, UInt<6>(0h0) connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsBIO_WIRE.bits.data, UInt<64>(0h0) connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0) connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) connect _portsBIO_WIRE.bits.source, UInt<5>(0h0) connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) connect _portsBIO_WIRE.valid, UInt<1>(0h0) connect _portsBIO_WIRE.ready, UInt<1>(0h0) wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) wire _portsBIO_WIRE_2 : UInt<1> connect _portsBIO_WIRE_2, _portsBIO_T_2 connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE.valid, UInt<1>(0h0) connect _portsCOI_WIRE.ready, UInt<1>(0h0) wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0) connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) connect _portsCOI_WIRE_2.bits.source, UInt<5>(0h0) connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE.bits.sink, UInt<6>(0h0) connect _portsEOI_WIRE.valid, UInt<1>(0h0) connect _portsEOI_WIRE.ready, UInt<1>(0h0) wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}[1] connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_2.bits.sink, UInt<6>(0h0) connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}[1] connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<5> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<5>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<3>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready invalidate _WIRE_73.bits.corrupt invalidate _WIRE_73.bits.data invalidate _WIRE_73.bits.address invalidate _WIRE_73.bits.source invalidate _WIRE_73.bits.size invalidate _WIRE_73.bits.param invalidate _WIRE_73.bits.opcode wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_74.bits.sink, UInt<6>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready invalidate _WIRE_75.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_76.bits.corrupt, UInt<1>(0h0) connect _WIRE_76.bits.data, UInt<64>(0h0) connect _WIRE_76.bits.mask, UInt<8>(0h0) connect _WIRE_76.bits.address, UInt<32>(0h0) connect _WIRE_76.bits.source, UInt<5>(0h0) connect _WIRE_76.bits.size, UInt<4>(0h0) connect _WIRE_76.bits.param, UInt<2>(0h0) connect _WIRE_76.bits.opcode, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready invalidate _WIRE_77.bits.corrupt invalidate _WIRE_77.bits.data invalidate _WIRE_77.bits.mask invalidate _WIRE_77.bits.address invalidate _WIRE_77.bits.source invalidate _WIRE_77.bits.size invalidate _WIRE_77.bits.param invalidate _WIRE_77.bits.opcode connect in[0].d, portsDIO_filtered[0] connect portsBIO_filtered[0].ready, UInt<1>(0h0) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<5>(0h0) connect _WIRE_78.bits.size, UInt<4>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready invalidate _WIRE_79.bits.corrupt invalidate _WIRE_79.bits.data invalidate _WIRE_79.bits.mask invalidate _WIRE_79.bits.address invalidate _WIRE_79.bits.source invalidate _WIRE_79.bits.size invalidate _WIRE_79.bits.param invalidate _WIRE_79.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0) extmodule plusarg_reader_80 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_81 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLXbar_fbus_i2_o1_a32d64s5k6z4u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [5:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire requestDOI_0_0 = auto_anon_out_d_bits_source == 5'h10; // @[Parameters.scala:46:9] wire portsDIO_filtered_0_valid = auto_anon_out_d_valid & requestDOI_0_0; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_valid = auto_anon_out_d_valid & ~(auto_anon_out_d_bits_source[4]); // @[Xbar.scala:355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid = {auto_anon_in_1_a_valid, auto_anon_in_0_a_valid}; // @[Arbiter.scala:68:51] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys = ~({readys_mask[1], _readys_filter_T_1[1] | readys_mask[0]} & ({_readys_filter_T_1[0], auto_anon_in_1_a_valid} | _readys_filter_T_1)); // @[package.scala:262:43] wire winner_0 = readys_readys[0] & auto_anon_in_0_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire winner_1 = readys_readys[1] & auto_anon_in_1_a_valid; // @[Arbiter.scala:26:18, :68:76, :71:69] wire _out_0_a_valid_T = auto_anon_in_0_a_valid | auto_anon_in_1_a_valid; // @[Arbiter.scala:79:31]

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_16 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<4>, vc_free : UInt<4>}} wire _in_flight_WIRE : UInt<1>[4] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) regreset in_flight : UInt<1>[4], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = or(_T_12, _T_19) node _T_63 = or(_T_62, _T_26) node _T_64 = or(_T_63, _T_33) node _T_65 = or(_T_64, _T_40) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_54) node _T_68 = or(_T_67, _T_61) node _T_69 = or(_T_5, _T_68) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_69, UInt<1>(0h1), "") : assert_1 node _T_73 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_104 = and(_T_102, _T_103) node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_111 = and(_T_109, _T_110) node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_118 = and(_T_116, _T_117) node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_122 = and(_T_120, _T_121) node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_125 = and(_T_123, _T_124) node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_141 = and(_T_139, _T_140) node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_148 = and(_T_146, _T_147) node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_150 = and(_T_148, _T_149) node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2)) node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_153 = and(_T_151, _T_152) node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_157 = and(_T_155, _T_156) node _T_158 = or(_T_80, _T_87) node _T_159 = or(_T_158, _T_94) node _T_160 = or(_T_159, _T_101) node _T_161 = or(_T_160, _T_108) node _T_162 = or(_T_161, _T_115) node _T_163 = or(_T_162, _T_122) node _T_164 = or(_T_163, _T_129) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_143) node _T_167 = or(_T_166, _T_150) node _T_168 = or(_T_167, _T_157) node _T_169 = or(_T_73, _T_168) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_169, UInt<1>(0h1), "") : assert_2 node _T_173 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_176 = and(_T_174, _T_175) node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_178 = and(_T_176, _T_177) node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_180 = and(_T_178, _T_179) node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_183 = and(_T_181, _T_182) node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_185 = and(_T_183, _T_184) node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_187 = and(_T_185, _T_186) node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_192 = and(_T_190, _T_191) node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_194 = and(_T_192, _T_193) node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_201 = and(_T_199, _T_200) node _T_202 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_203 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_206 = and(_T_204, _T_205) node _T_207 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_210 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_215 = and(_T_213, _T_214) node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_217 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_220 = and(_T_218, _T_219) node _T_221 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_224 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_227 = and(_T_225, _T_226) node _T_228 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_229 = and(_T_227, _T_228) node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_236 = and(_T_234, _T_235) node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_241 = and(_T_239, _T_240) node _T_242 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_245 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_278 = and(_T_276, _T_277) node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_285 = and(_T_283, _T_284) node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_309 = and(_T_307, _T_308) node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_311 = and(_T_309, _T_310) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(_T_180, _T_187) node _T_315 = or(_T_314, _T_194) node _T_316 = or(_T_315, _T_201) node _T_317 = or(_T_316, _T_208) node _T_318 = or(_T_317, _T_215) node _T_319 = or(_T_318, _T_222) node _T_320 = or(_T_319, _T_229) node _T_321 = or(_T_320, _T_236) node _T_322 = or(_T_321, _T_243) node _T_323 = or(_T_322, _T_250) node _T_324 = or(_T_323, _T_257) node _T_325 = or(_T_324, _T_264) node _T_326 = or(_T_325, _T_271) node _T_327 = or(_T_326, _T_278) node _T_328 = or(_T_327, _T_285) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_299) node _T_331 = or(_T_330, _T_306) node _T_332 = or(_T_331, _T_313) node _T_333 = or(_T_173, _T_332) node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : node _T_336 = eq(_T_333, UInt<1>(0h0)) when _T_336 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_333, UInt<1>(0h1), "") : assert_3 node _T_337 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_339 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_340 = and(_T_338, _T_339) node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_346 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_353 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_356 = and(_T_354, _T_355) node _T_357 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_360 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_361 = and(_T_359, _T_360) node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_363 = and(_T_361, _T_362) node _T_364 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc)) node _T_367 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_372 = and(_T_370, _T_371) node _T_373 = or(_T_344, _T_351) node _T_374 = or(_T_373, _T_358) node _T_375 = or(_T_374, _T_365) node _T_376 = or(_T_375, _T_372) node _T_377 = or(_T_337, _T_376) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_377, UInt<1>(0h1), "") : assert_4

module NoCMonitor_16( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_52 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h70)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h71)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h72)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h73)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<7>(0h7c)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 2) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<7>(0h7b)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_37 = shr(io.in.a.bits.source, 5) node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0hd)) node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_43 = shr(io.in.a.bits.source, 5) node _source_ok_T_44 = eq(_source_ok_T_43, UInt<4>(0hc)) node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_T_47 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_49 = shr(io.in.a.bits.source, 5) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<4>(0hb)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_55 = shr(io.in.a.bits.source, 5) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<4>(0ha)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_61 = shr(io.in.a.bits.source, 5) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<4>(0h9)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_67 = shr(io.in.a.bits.source, 5) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<4>(0h8)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_73 = shr(io.in.a.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<7>(0h7a)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_79 = shr(io.in.a.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<7>(0h79)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 4, 0) node _source_ok_T_85 = shr(io.in.a.bits.source, 5) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<3>(0h7)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_14, UInt<5>(0h1f)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 4, 0) node _source_ok_T_91 = shr(io.in.a.bits.source, 5) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<3>(0h6)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_15, UInt<5>(0h1f)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_97 = shr(io.in.a.bits.source, 5) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<3>(0h5)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_103 = shr(io.in.a.bits.source, 5) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_109 = shr(io.in.a.bits.source, 5) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<2>(0h3)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_115 = shr(io.in.a.bits.source, 5) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_121 = shr(io.in.a.bits.source, 5) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h1)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_127 = shr(io.in.a.bits.source, 5) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h0)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_T_133 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _source_ok_T_134 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE : UInt<1>[25] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_42 connect _source_ok_WIRE[8], _source_ok_T_48 connect _source_ok_WIRE[9], _source_ok_T_54 connect _source_ok_WIRE[10], _source_ok_T_60 connect _source_ok_WIRE[11], _source_ok_T_66 connect _source_ok_WIRE[12], _source_ok_T_72 connect _source_ok_WIRE[13], _source_ok_T_78 connect _source_ok_WIRE[14], _source_ok_T_84 connect _source_ok_WIRE[15], _source_ok_T_90 connect _source_ok_WIRE[16], _source_ok_T_96 connect _source_ok_WIRE[17], _source_ok_T_102 connect _source_ok_WIRE[18], _source_ok_T_108 connect _source_ok_WIRE[19], _source_ok_T_114 connect _source_ok_WIRE[20], _source_ok_T_120 connect _source_ok_WIRE[21], _source_ok_T_126 connect _source_ok_WIRE[22], _source_ok_T_132 connect _source_ok_WIRE[23], _source_ok_T_133 connect _source_ok_WIRE[24], _source_ok_T_134 node _source_ok_T_135 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE[2]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE[3]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE[4]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE[5]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE[6]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE[7]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE[8]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE[9]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE[10]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE[11]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE[12]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE[13]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE[14]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE[15]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE[16]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE[17]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE[18]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE[19]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE[20]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE[21]) node _source_ok_T_156 = or(_source_ok_T_155, _source_ok_WIRE[22]) node _source_ok_T_157 = or(_source_ok_T_156, _source_ok_WIRE[23]) node source_ok = or(_source_ok_T_157, _source_ok_WIRE[24]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h70)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h71)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h72)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h73)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<7>(0h7c)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_77 = shr(io.in.a.bits.source, 2) node _T_78 = eq(_T_77, UInt<7>(0h7b)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_90 = shr(io.in.a.bits.source, 5) node _T_91 = eq(_T_90, UInt<4>(0hd)) node _T_92 = leq(UInt<1>(0h0), uncommonBits_6) node _T_93 = and(_T_91, _T_92) node _T_94 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(_T_95, UInt<1>(0h0)) node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_98 = cvt(_T_97) node _T_99 = and(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = asSInt(_T_99) node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0))) node _T_102 = or(_T_96, _T_101) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_103 = shr(io.in.a.bits.source, 5) node _T_104 = eq(_T_103, UInt<4>(0hc)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_7) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_116 = shr(io.in.a.bits.source, 5) node _T_117 = eq(_T_116, UInt<4>(0hb)) node _T_118 = leq(UInt<1>(0h0), uncommonBits_8) node _T_119 = and(_T_117, _T_118) node _T_120 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_124 = cvt(_T_123) node _T_125 = and(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = asSInt(_T_125) node _T_127 = eq(_T_126, asSInt(UInt<1>(0h0))) node _T_128 = or(_T_122, _T_127) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_129 = shr(io.in.a.bits.source, 5) node _T_130 = eq(_T_129, UInt<4>(0ha)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_9) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_134 = and(_T_132, _T_133) node _T_135 = eq(_T_134, UInt<1>(0h0)) node _T_136 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = or(_T_135, _T_140) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_142 = shr(io.in.a.bits.source, 5) node _T_143 = eq(_T_142, UInt<4>(0h9)) node _T_144 = leq(UInt<1>(0h0), uncommonBits_10) node _T_145 = and(_T_143, _T_144) node _T_146 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = or(_T_148, _T_153) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_155 = shr(io.in.a.bits.source, 5) node _T_156 = eq(_T_155, UInt<4>(0h8)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_11) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_160 = and(_T_158, _T_159) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_168 = shr(io.in.a.bits.source, 2) node _T_169 = eq(_T_168, UInt<7>(0h7a)) node _T_170 = leq(UInt<1>(0h0), uncommonBits_12) node _T_171 = and(_T_169, _T_170) node _T_172 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_173 = and(_T_171, _T_172) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_174, _T_179) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_181 = shr(io.in.a.bits.source, 2) node _T_182 = eq(_T_181, UInt<7>(0h79)) node _T_183 = leq(UInt<1>(0h0), uncommonBits_13) node _T_184 = and(_T_182, _T_183) node _T_185 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = or(_T_187, _T_192) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 4, 0) node _T_194 = shr(io.in.a.bits.source, 5) node _T_195 = eq(_T_194, UInt<3>(0h7)) node _T_196 = leq(UInt<1>(0h0), uncommonBits_14) node _T_197 = and(_T_195, _T_196) node _T_198 = leq(uncommonBits_14, UInt<5>(0h1f)) node _T_199 = and(_T_197, _T_198) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 4, 0) node _T_207 = shr(io.in.a.bits.source, 5) node _T_208 = eq(_T_207, UInt<3>(0h6)) node _T_209 = leq(UInt<1>(0h0), uncommonBits_15) node _T_210 = and(_T_208, _T_209) node _T_211 = leq(uncommonBits_15, UInt<5>(0h1f)) node _T_212 = and(_T_210, _T_211) node _T_213 = eq(_T_212, UInt<1>(0h0)) node _T_214 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = or(_T_213, _T_218) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_220 = shr(io.in.a.bits.source, 5) node _T_221 = eq(_T_220, UInt<3>(0h5)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_16) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(_T_225, UInt<1>(0h0)) node _T_227 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = or(_T_226, _T_231) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_233 = shr(io.in.a.bits.source, 5) node _T_234 = eq(_T_233, UInt<3>(0h4)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_17) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<1>(0h0))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = or(_T_239, _T_244) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_246 = shr(io.in.a.bits.source, 5) node _T_247 = eq(_T_246, UInt<2>(0h3)) node _T_248 = leq(UInt<1>(0h0), uncommonBits_18) node _T_249 = and(_T_247, _T_248) node _T_250 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_251 = and(_T_249, _T_250) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_254 = cvt(_T_253) node _T_255 = and(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = asSInt(_T_255) node _T_257 = eq(_T_256, asSInt(UInt<1>(0h0))) node _T_258 = or(_T_252, _T_257) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_259 = shr(io.in.a.bits.source, 5) node _T_260 = eq(_T_259, UInt<2>(0h2)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_19) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_272 = shr(io.in.a.bits.source, 5) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_20) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_278, _T_283) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_285 = shr(io.in.a.bits.source, 5) node _T_286 = eq(_T_285, UInt<1>(0h0)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_21) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(_T_290, UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = or(_T_291, _T_296) node _T_298 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_299 = eq(_T_298, UInt<1>(0h0)) node _T_300 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = or(_T_299, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_307 = eq(_T_306, UInt<1>(0h0)) node _T_308 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_307, _T_312) node _T_314 = and(_T_11, _T_24) node _T_315 = and(_T_314, _T_37) node _T_316 = and(_T_315, _T_50) node _T_317 = and(_T_316, _T_63) node _T_318 = and(_T_317, _T_76) node _T_319 = and(_T_318, _T_89) node _T_320 = and(_T_319, _T_102) node _T_321 = and(_T_320, _T_115) node _T_322 = and(_T_321, _T_128) node _T_323 = and(_T_322, _T_141) node _T_324 = and(_T_323, _T_154) node _T_325 = and(_T_324, _T_167) node _T_326 = and(_T_325, _T_180) node _T_327 = and(_T_326, _T_193) node _T_328 = and(_T_327, _T_206) node _T_329 = and(_T_328, _T_219) node _T_330 = and(_T_329, _T_232) node _T_331 = and(_T_330, _T_245) node _T_332 = and(_T_331, _T_258) node _T_333 = and(_T_332, _T_271) node _T_334 = and(_T_333, _T_284) node _T_335 = and(_T_334, _T_297) node _T_336 = and(_T_335, _T_305) node _T_337 = and(_T_336, _T_313) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_337, UInt<1>(0h1), "") : assert_1 node _T_341 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_341 : node _T_342 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_343 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_346 = shr(io.in.a.bits.source, 2) node _T_347 = eq(_T_346, UInt<7>(0h70)) node _T_348 = leq(UInt<1>(0h0), uncommonBits_22) node _T_349 = and(_T_347, _T_348) node _T_350 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_351 = and(_T_349, _T_350) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_352 = shr(io.in.a.bits.source, 2) node _T_353 = eq(_T_352, UInt<7>(0h71)) node _T_354 = leq(UInt<1>(0h0), uncommonBits_23) node _T_355 = and(_T_353, _T_354) node _T_356 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_357 = and(_T_355, _T_356) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_358 = shr(io.in.a.bits.source, 2) node _T_359 = eq(_T_358, UInt<7>(0h72)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_24) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_364 = shr(io.in.a.bits.source, 2) node _T_365 = eq(_T_364, UInt<7>(0h73)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_25) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_370 = shr(io.in.a.bits.source, 2) node _T_371 = eq(_T_370, UInt<7>(0h7c)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_26) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_376 = shr(io.in.a.bits.source, 2) node _T_377 = eq(_T_376, UInt<7>(0h7b)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_27) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_382 = shr(io.in.a.bits.source, 5) node _T_383 = eq(_T_382, UInt<4>(0hd)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_28) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_388 = shr(io.in.a.bits.source, 5) node _T_389 = eq(_T_388, UInt<4>(0hc)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_29) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_394 = shr(io.in.a.bits.source, 5) node _T_395 = eq(_T_394, UInt<4>(0hb)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_30) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<4>(0ha)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_31) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_406 = shr(io.in.a.bits.source, 5) node _T_407 = eq(_T_406, UInt<4>(0h9)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_32) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_412 = shr(io.in.a.bits.source, 5) node _T_413 = eq(_T_412, UInt<4>(0h8)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_33) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<7>(0h7a)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_34) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<7>(0h79)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_35) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 4, 0) node _T_430 = shr(io.in.a.bits.source, 5) node _T_431 = eq(_T_430, UInt<3>(0h7)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_36) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_36, UInt<5>(0h1f)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 4, 0) node _T_436 = shr(io.in.a.bits.source, 5) node _T_437 = eq(_T_436, UInt<3>(0h6)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_37) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_37, UInt<5>(0h1f)) node _T_441 = and(_T_439, _T_440) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 4, 0) node _T_442 = shr(io.in.a.bits.source, 5) node _T_443 = eq(_T_442, UInt<3>(0h5)) node _T_444 = leq(UInt<1>(0h0), uncommonBits_38) node _T_445 = and(_T_443, _T_444) node _T_446 = leq(uncommonBits_38, UInt<5>(0h1f)) node _T_447 = and(_T_445, _T_446) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 4, 0) node _T_448 = shr(io.in.a.bits.source, 5) node _T_449 = eq(_T_448, UInt<3>(0h4)) node _T_450 = leq(UInt<1>(0h0), uncommonBits_39) node _T_451 = and(_T_449, _T_450) node _T_452 = leq(uncommonBits_39, UInt<5>(0h1f)) node _T_453 = and(_T_451, _T_452) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_454 = shr(io.in.a.bits.source, 5) node _T_455 = eq(_T_454, UInt<2>(0h3)) node _T_456 = leq(UInt<1>(0h0), uncommonBits_40) node _T_457 = and(_T_455, _T_456) node _T_458 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_459 = and(_T_457, _T_458) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_460 = shr(io.in.a.bits.source, 5) node _T_461 = eq(_T_460, UInt<2>(0h2)) node _T_462 = leq(UInt<1>(0h0), uncommonBits_41) node _T_463 = and(_T_461, _T_462) node _T_464 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_465 = and(_T_463, _T_464) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_466 = shr(io.in.a.bits.source, 5) node _T_467 = eq(_T_466, UInt<1>(0h1)) node _T_468 = leq(UInt<1>(0h0), uncommonBits_42) node _T_469 = and(_T_467, _T_468) node _T_470 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_471 = and(_T_469, _T_470) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_472 = shr(io.in.a.bits.source, 5) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_43) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_479 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_480 = or(_T_345, _T_351) node _T_481 = or(_T_480, _T_357) node _T_482 = or(_T_481, _T_363) node _T_483 = or(_T_482, _T_369) node _T_484 = or(_T_483, _T_375) node _T_485 = or(_T_484, _T_381) node _T_486 = or(_T_485, _T_387) node _T_487 = or(_T_486, _T_393) node _T_488 = or(_T_487, _T_399) node _T_489 = or(_T_488, _T_405) node _T_490 = or(_T_489, _T_411) node _T_491 = or(_T_490, _T_417) node _T_492 = or(_T_491, _T_423) node _T_493 = or(_T_492, _T_429) node _T_494 = or(_T_493, _T_435) node _T_495 = or(_T_494, _T_441) node _T_496 = or(_T_495, _T_447) node _T_497 = or(_T_496, _T_453) node _T_498 = or(_T_497, _T_459) node _T_499 = or(_T_498, _T_465) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_477) node _T_502 = or(_T_501, _T_478) node _T_503 = or(_T_502, _T_479) node _T_504 = and(_T_344, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_507 = or(UInt<1>(0h0), _T_506) node _T_508 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_509 = cvt(_T_508) node _T_510 = and(_T_509, asSInt(UInt<17>(0h10000))) node _T_511 = asSInt(_T_510) node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0))) node _T_513 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_514 = cvt(_T_513) node _T_515 = and(_T_514, asSInt(UInt<29>(0h10000000))) node _T_516 = asSInt(_T_515) node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0))) node _T_518 = or(_T_512, _T_517) node _T_519 = and(_T_507, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_505, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<7>(0h70)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_44) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<7>(0h71)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_45) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<7>(0h72)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_46) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<7>(0h73)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_47) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_550 = shr(io.in.a.bits.source, 2) node _T_551 = eq(_T_550, UInt<7>(0h7c)) node _T_552 = leq(UInt<1>(0h0), uncommonBits_48) node _T_553 = and(_T_551, _T_552) node _T_554 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_555 = and(_T_553, _T_554) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_556 = shr(io.in.a.bits.source, 2) node _T_557 = eq(_T_556, UInt<7>(0h7b)) node _T_558 = leq(UInt<1>(0h0), uncommonBits_49) node _T_559 = and(_T_557, _T_558) node _T_560 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_561 = and(_T_559, _T_560) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 4, 0) node _T_562 = shr(io.in.a.bits.source, 5) node _T_563 = eq(_T_562, UInt<4>(0hd)) node _T_564 = leq(UInt<1>(0h0), uncommonBits_50) node _T_565 = and(_T_563, _T_564) node _T_566 = leq(uncommonBits_50, UInt<5>(0h1f)) node _T_567 = and(_T_565, _T_566) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 4, 0) node _T_568 = shr(io.in.a.bits.source, 5) node _T_569 = eq(_T_568, UInt<4>(0hc)) node _T_570 = leq(UInt<1>(0h0), uncommonBits_51) node _T_571 = and(_T_569, _T_570) node _T_572 = leq(uncommonBits_51, UInt<5>(0h1f)) node _T_573 = and(_T_571, _T_572) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_574 = shr(io.in.a.bits.source, 5) node _T_575 = eq(_T_574, UInt<4>(0hb)) node _T_576 = leq(UInt<1>(0h0), uncommonBits_52) node _T_577 = and(_T_575, _T_576) node _T_578 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_579 = and(_T_577, _T_578) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_580 = shr(io.in.a.bits.source, 5) node _T_581 = eq(_T_580, UInt<4>(0ha)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_53) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_586 = shr(io.in.a.bits.source, 5) node _T_587 = eq(_T_586, UInt<4>(0h9)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_54) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_592 = shr(io.in.a.bits.source, 5) node _T_593 = eq(_T_592, UInt<4>(0h8)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_55) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<7>(0h7a)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_56) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<7>(0h79)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_57) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_610 = shr(io.in.a.bits.source, 5) node _T_611 = eq(_T_610, UInt<3>(0h7)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_58) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_615 = and(_T_613, _T_614) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_616 = shr(io.in.a.bits.source, 5) node _T_617 = eq(_T_616, UInt<3>(0h6)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_59) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 4, 0) node _T_622 = shr(io.in.a.bits.source, 5) node _T_623 = eq(_T_622, UInt<3>(0h5)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_60) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_60, UInt<5>(0h1f)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 4, 0) node _T_628 = shr(io.in.a.bits.source, 5) node _T_629 = eq(_T_628, UInt<3>(0h4)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_61) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_61, UInt<5>(0h1f)) node _T_633 = and(_T_631, _T_632) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 4, 0) node _T_634 = shr(io.in.a.bits.source, 5) node _T_635 = eq(_T_634, UInt<2>(0h3)) node _T_636 = leq(UInt<1>(0h0), uncommonBits_62) node _T_637 = and(_T_635, _T_636) node _T_638 = leq(uncommonBits_62, UInt<5>(0h1f)) node _T_639 = and(_T_637, _T_638) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 4, 0) node _T_640 = shr(io.in.a.bits.source, 5) node _T_641 = eq(_T_640, UInt<2>(0h2)) node _T_642 = leq(UInt<1>(0h0), uncommonBits_63) node _T_643 = and(_T_641, _T_642) node _T_644 = leq(uncommonBits_63, UInt<5>(0h1f)) node _T_645 = and(_T_643, _T_644) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_646 = shr(io.in.a.bits.source, 5) node _T_647 = eq(_T_646, UInt<1>(0h1)) node _T_648 = leq(UInt<1>(0h0), uncommonBits_64) node _T_649 = and(_T_647, _T_648) node _T_650 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_651 = and(_T_649, _T_650) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_652 = shr(io.in.a.bits.source, 5) node _T_653 = eq(_T_652, UInt<1>(0h0)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_65) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_657 = and(_T_655, _T_656) node _T_658 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_659 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _WIRE : UInt<1>[25] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_555 connect _WIRE[6], _T_561 connect _WIRE[7], _T_567 connect _WIRE[8], _T_573 connect _WIRE[9], _T_579 connect _WIRE[10], _T_585 connect _WIRE[11], _T_591 connect _WIRE[12], _T_597 connect _WIRE[13], _T_603 connect _WIRE[14], _T_609 connect _WIRE[15], _T_615 connect _WIRE[16], _T_621 connect _WIRE[17], _T_627 connect _WIRE[18], _T_633 connect _WIRE[19], _T_639 connect _WIRE[20], _T_645 connect _WIRE[21], _T_651 connect _WIRE[22], _T_657 connect _WIRE[23], _T_658 connect _WIRE[24], _T_659 node _T_660 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_661 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_662 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_663 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_664 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_665 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_666 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_668 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_673 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_674 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_676 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE[23], _T_660, UInt<1>(0h0)) node _T_685 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = or(_T_661, _T_662) node _T_687 = or(_T_686, _T_663) node _T_688 = or(_T_687, _T_664) node _T_689 = or(_T_688, _T_665) node _T_690 = or(_T_689, _T_666) node _T_691 = or(_T_690, _T_667) node _T_692 = or(_T_691, _T_668) node _T_693 = or(_T_692, _T_669) node _T_694 = or(_T_693, _T_670) node _T_695 = or(_T_694, _T_671) node _T_696 = or(_T_695, _T_672) node _T_697 = or(_T_696, _T_673) node _T_698 = or(_T_697, _T_674) node _T_699 = or(_T_698, _T_675) node _T_700 = or(_T_699, _T_676) node _T_701 = or(_T_700, _T_677) node _T_702 = or(_T_701, _T_678) node _T_703 = or(_T_702, _T_679) node _T_704 = or(_T_703, _T_680) node _T_705 = or(_T_704, _T_681) node _T_706 = or(_T_705, _T_682) node _T_707 = or(_T_706, _T_683) node _T_708 = or(_T_707, _T_684) node _T_709 = or(_T_708, _T_685) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_709 node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_711 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_712 = and(_T_710, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_715 = cvt(_T_714) node _T_716 = and(_T_715, asSInt(UInt<17>(0h10000))) node _T_717 = asSInt(_T_716) node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) node _T_719 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<29>(0h10000000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = or(_T_718, _T_723) node _T_725 = and(_T_713, _T_724) node _T_726 = or(UInt<1>(0h0), _T_725) node _T_727 = and(_WIRE_1, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_727, UInt<1>(0h1), "") : assert_3 node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(source_ok, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_734 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_T_734, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_734, UInt<1>(0h1), "") : assert_5 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_741 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_741, UInt<1>(0h1), "") : assert_7 node _T_745 = not(io.in.a.bits.mask) node _T_746 = eq(_T_745, UInt<1>(0h0)) node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_T_746, UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_746, UInt<1>(0h1), "") : assert_8 node _T_750 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_750, UInt<1>(0h1), "") : assert_9 node _T_754 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_754 : node _T_755 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_756 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_759 = shr(io.in.a.bits.source, 2) node _T_760 = eq(_T_759, UInt<7>(0h70)) node _T_761 = leq(UInt<1>(0h0), uncommonBits_66) node _T_762 = and(_T_760, _T_761) node _T_763 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_764 = and(_T_762, _T_763) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_765 = shr(io.in.a.bits.source, 2) node _T_766 = eq(_T_765, UInt<7>(0h71)) node _T_767 = leq(UInt<1>(0h0), uncommonBits_67) node _T_768 = and(_T_766, _T_767) node _T_769 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_770 = and(_T_768, _T_769) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_771 = shr(io.in.a.bits.source, 2) node _T_772 = eq(_T_771, UInt<7>(0h72)) node _T_773 = leq(UInt<1>(0h0), uncommonBits_68) node _T_774 = and(_T_772, _T_773) node _T_775 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_776 = and(_T_774, _T_775) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_777 = shr(io.in.a.bits.source, 2) node _T_778 = eq(_T_777, UInt<7>(0h73)) node _T_779 = leq(UInt<1>(0h0), uncommonBits_69) node _T_780 = and(_T_778, _T_779) node _T_781 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<7>(0h7c)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_70) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_789 = shr(io.in.a.bits.source, 2) node _T_790 = eq(_T_789, UInt<7>(0h7b)) node _T_791 = leq(UInt<1>(0h0), uncommonBits_71) node _T_792 = and(_T_790, _T_791) node _T_793 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_794 = and(_T_792, _T_793) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 4, 0) node _T_795 = shr(io.in.a.bits.source, 5) node _T_796 = eq(_T_795, UInt<4>(0hd)) node _T_797 = leq(UInt<1>(0h0), uncommonBits_72) node _T_798 = and(_T_796, _T_797) node _T_799 = leq(uncommonBits_72, UInt<5>(0h1f)) node _T_800 = and(_T_798, _T_799) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 4, 0) node _T_801 = shr(io.in.a.bits.source, 5) node _T_802 = eq(_T_801, UInt<4>(0hc)) node _T_803 = leq(UInt<1>(0h0), uncommonBits_73) node _T_804 = and(_T_802, _T_803) node _T_805 = leq(uncommonBits_73, UInt<5>(0h1f)) node _T_806 = and(_T_804, _T_805) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 4, 0) node _T_807 = shr(io.in.a.bits.source, 5) node _T_808 = eq(_T_807, UInt<4>(0hb)) node _T_809 = leq(UInt<1>(0h0), uncommonBits_74) node _T_810 = and(_T_808, _T_809) node _T_811 = leq(uncommonBits_74, UInt<5>(0h1f)) node _T_812 = and(_T_810, _T_811) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 4, 0) node _T_813 = shr(io.in.a.bits.source, 5) node _T_814 = eq(_T_813, UInt<4>(0ha)) node _T_815 = leq(UInt<1>(0h0), uncommonBits_75) node _T_816 = and(_T_814, _T_815) node _T_817 = leq(uncommonBits_75, UInt<5>(0h1f)) node _T_818 = and(_T_816, _T_817) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_819 = shr(io.in.a.bits.source, 5) node _T_820 = eq(_T_819, UInt<4>(0h9)) node _T_821 = leq(UInt<1>(0h0), uncommonBits_76) node _T_822 = and(_T_820, _T_821) node _T_823 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_824 = and(_T_822, _T_823) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_825 = shr(io.in.a.bits.source, 5) node _T_826 = eq(_T_825, UInt<4>(0h8)) node _T_827 = leq(UInt<1>(0h0), uncommonBits_77) node _T_828 = and(_T_826, _T_827) node _T_829 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_830 = and(_T_828, _T_829) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0) node _T_831 = shr(io.in.a.bits.source, 2) node _T_832 = eq(_T_831, UInt<7>(0h7a)) node _T_833 = leq(UInt<1>(0h0), uncommonBits_78) node _T_834 = and(_T_832, _T_833) node _T_835 = leq(uncommonBits_78, UInt<2>(0h3)) node _T_836 = and(_T_834, _T_835) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0) node _T_837 = shr(io.in.a.bits.source, 2) node _T_838 = eq(_T_837, UInt<7>(0h79)) node _T_839 = leq(UInt<1>(0h0), uncommonBits_79) node _T_840 = and(_T_838, _T_839) node _T_841 = leq(uncommonBits_79, UInt<2>(0h3)) node _T_842 = and(_T_840, _T_841) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_843 = shr(io.in.a.bits.source, 5) node _T_844 = eq(_T_843, UInt<3>(0h7)) node _T_845 = leq(UInt<1>(0h0), uncommonBits_80) node _T_846 = and(_T_844, _T_845) node _T_847 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_849 = shr(io.in.a.bits.source, 5) node _T_850 = eq(_T_849, UInt<3>(0h6)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_81) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_855 = shr(io.in.a.bits.source, 5) node _T_856 = eq(_T_855, UInt<3>(0h5)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_82) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_861 = shr(io.in.a.bits.source, 5) node _T_862 = eq(_T_861, UInt<3>(0h4)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_83) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_866 = and(_T_864, _T_865) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 4, 0) node _T_867 = shr(io.in.a.bits.source, 5) node _T_868 = eq(_T_867, UInt<2>(0h3)) node _T_869 = leq(UInt<1>(0h0), uncommonBits_84) node _T_870 = and(_T_868, _T_869) node _T_871 = leq(uncommonBits_84, UInt<5>(0h1f)) node _T_872 = and(_T_870, _T_871) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 4, 0) node _T_873 = shr(io.in.a.bits.source, 5) node _T_874 = eq(_T_873, UInt<2>(0h2)) node _T_875 = leq(UInt<1>(0h0), uncommonBits_85) node _T_876 = and(_T_874, _T_875) node _T_877 = leq(uncommonBits_85, UInt<5>(0h1f)) node _T_878 = and(_T_876, _T_877) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 4, 0) node _T_879 = shr(io.in.a.bits.source, 5) node _T_880 = eq(_T_879, UInt<1>(0h1)) node _T_881 = leq(UInt<1>(0h0), uncommonBits_86) node _T_882 = and(_T_880, _T_881) node _T_883 = leq(uncommonBits_86, UInt<5>(0h1f)) node _T_884 = and(_T_882, _T_883) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 4, 0) node _T_885 = shr(io.in.a.bits.source, 5) node _T_886 = eq(_T_885, UInt<1>(0h0)) node _T_887 = leq(UInt<1>(0h0), uncommonBits_87) node _T_888 = and(_T_886, _T_887) node _T_889 = leq(uncommonBits_87, UInt<5>(0h1f)) node _T_890 = and(_T_888, _T_889) node _T_891 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_892 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_893 = or(_T_758, _T_764) node _T_894 = or(_T_893, _T_770) node _T_895 = or(_T_894, _T_776) node _T_896 = or(_T_895, _T_782) node _T_897 = or(_T_896, _T_788) node _T_898 = or(_T_897, _T_794) node _T_899 = or(_T_898, _T_800) node _T_900 = or(_T_899, _T_806) node _T_901 = or(_T_900, _T_812) node _T_902 = or(_T_901, _T_818) node _T_903 = or(_T_902, _T_824) node _T_904 = or(_T_903, _T_830) node _T_905 = or(_T_904, _T_836) node _T_906 = or(_T_905, _T_842) node _T_907 = or(_T_906, _T_848) node _T_908 = or(_T_907, _T_854) node _T_909 = or(_T_908, _T_860) node _T_910 = or(_T_909, _T_866) node _T_911 = or(_T_910, _T_872) node _T_912 = or(_T_911, _T_878) node _T_913 = or(_T_912, _T_884) node _T_914 = or(_T_913, _T_890) node _T_915 = or(_T_914, _T_891) node _T_916 = or(_T_915, _T_892) node _T_917 = and(_T_757, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_920 = or(UInt<1>(0h0), _T_919) node _T_921 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_927 = cvt(_T_926) node _T_928 = and(_T_927, asSInt(UInt<29>(0h10000000))) node _T_929 = asSInt(_T_928) node _T_930 = eq(_T_929, asSInt(UInt<1>(0h0))) node _T_931 = or(_T_925, _T_930) node _T_932 = and(_T_920, _T_931) node _T_933 = or(UInt<1>(0h0), _T_932) node _T_934 = and(_T_918, _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_934, UInt<1>(0h1), "") : assert_10 node _T_938 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 1, 0) node _T_939 = shr(io.in.a.bits.source, 2) node _T_940 = eq(_T_939, UInt<7>(0h70)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_88) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_88, UInt<2>(0h3)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 1, 0) node _T_945 = shr(io.in.a.bits.source, 2) node _T_946 = eq(_T_945, UInt<7>(0h71)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_89) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_89, UInt<2>(0h3)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0) node _T_951 = shr(io.in.a.bits.source, 2) node _T_952 = eq(_T_951, UInt<7>(0h72)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_90) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_90, UInt<2>(0h3)) node _T_956 = and(_T_954, _T_955) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0) node _T_957 = shr(io.in.a.bits.source, 2) node _T_958 = eq(_T_957, UInt<7>(0h73)) node _T_959 = leq(UInt<1>(0h0), uncommonBits_91) node _T_960 = and(_T_958, _T_959) node _T_961 = leq(uncommonBits_91, UInt<2>(0h3)) node _T_962 = and(_T_960, _T_961) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0) node _T_963 = shr(io.in.a.bits.source, 2) node _T_964 = eq(_T_963, UInt<7>(0h7c)) node _T_965 = leq(UInt<1>(0h0), uncommonBits_92) node _T_966 = and(_T_964, _T_965) node _T_967 = leq(uncommonBits_92, UInt<2>(0h3)) node _T_968 = and(_T_966, _T_967) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0) node _T_969 = shr(io.in.a.bits.source, 2) node _T_970 = eq(_T_969, UInt<7>(0h7b)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_93) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_93, UInt<2>(0h3)) node _T_974 = and(_T_972, _T_973) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_975 = shr(io.in.a.bits.source, 5) node _T_976 = eq(_T_975, UInt<4>(0hd)) node _T_977 = leq(UInt<1>(0h0), uncommonBits_94) node _T_978 = and(_T_976, _T_977) node _T_979 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_980 = and(_T_978, _T_979) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_981 = shr(io.in.a.bits.source, 5) node _T_982 = eq(_T_981, UInt<4>(0hc)) node _T_983 = leq(UInt<1>(0h0), uncommonBits_95) node _T_984 = and(_T_982, _T_983) node _T_985 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_986 = and(_T_984, _T_985) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 4, 0) node _T_987 = shr(io.in.a.bits.source, 5) node _T_988 = eq(_T_987, UInt<4>(0hb)) node _T_989 = leq(UInt<1>(0h0), uncommonBits_96) node _T_990 = and(_T_988, _T_989) node _T_991 = leq(uncommonBits_96, UInt<5>(0h1f)) node _T_992 = and(_T_990, _T_991) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 4, 0) node _T_993 = shr(io.in.a.bits.source, 5) node _T_994 = eq(_T_993, UInt<4>(0ha)) node _T_995 = leq(UInt<1>(0h0), uncommonBits_97) node _T_996 = and(_T_994, _T_995) node _T_997 = leq(uncommonBits_97, UInt<5>(0h1f)) node _T_998 = and(_T_996, _T_997) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 4, 0) node _T_999 = shr(io.in.a.bits.source, 5) node _T_1000 = eq(_T_999, UInt<4>(0h9)) node _T_1001 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1002 = and(_T_1000, _T_1001) node _T_1003 = leq(uncommonBits_98, UInt<5>(0h1f)) node _T_1004 = and(_T_1002, _T_1003) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 4, 0) node _T_1005 = shr(io.in.a.bits.source, 5) node _T_1006 = eq(_T_1005, UInt<4>(0h8)) node _T_1007 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = leq(uncommonBits_99, UInt<5>(0h1f)) node _T_1010 = and(_T_1008, _T_1009) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 1, 0) node _T_1011 = shr(io.in.a.bits.source, 2) node _T_1012 = eq(_T_1011, UInt<7>(0h7a)) node _T_1013 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1014 = and(_T_1012, _T_1013) node _T_1015 = leq(uncommonBits_100, UInt<2>(0h3)) node _T_1016 = and(_T_1014, _T_1015) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 1, 0) node _T_1017 = shr(io.in.a.bits.source, 2) node _T_1018 = eq(_T_1017, UInt<7>(0h79)) node _T_1019 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1020 = and(_T_1018, _T_1019) node _T_1021 = leq(uncommonBits_101, UInt<2>(0h3)) node _T_1022 = and(_T_1020, _T_1021) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1023 = shr(io.in.a.bits.source, 5) node _T_1024 = eq(_T_1023, UInt<3>(0h7)) node _T_1025 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1028 = and(_T_1026, _T_1027) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1029 = shr(io.in.a.bits.source, 5) node _T_1030 = eq(_T_1029, UInt<3>(0h6)) node _T_1031 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1032 = and(_T_1030, _T_1031) node _T_1033 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1034 = and(_T_1032, _T_1033) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1035 = shr(io.in.a.bits.source, 5) node _T_1036 = eq(_T_1035, UInt<3>(0h5)) node _T_1037 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1040 = and(_T_1038, _T_1039) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1041 = shr(io.in.a.bits.source, 5) node _T_1042 = eq(_T_1041, UInt<3>(0h4)) node _T_1043 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1046 = and(_T_1044, _T_1045) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1047 = shr(io.in.a.bits.source, 5) node _T_1048 = eq(_T_1047, UInt<2>(0h3)) node _T_1049 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1050 = and(_T_1048, _T_1049) node _T_1051 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1052 = and(_T_1050, _T_1051) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1053 = shr(io.in.a.bits.source, 5) node _T_1054 = eq(_T_1053, UInt<2>(0h2)) node _T_1055 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1056 = and(_T_1054, _T_1055) node _T_1057 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1058 = and(_T_1056, _T_1057) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 4, 0) node _T_1059 = shr(io.in.a.bits.source, 5) node _T_1060 = eq(_T_1059, UInt<1>(0h1)) node _T_1061 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1062 = and(_T_1060, _T_1061) node _T_1063 = leq(uncommonBits_108, UInt<5>(0h1f)) node _T_1064 = and(_T_1062, _T_1063) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 4, 0) node _T_1065 = shr(io.in.a.bits.source, 5) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) node _T_1067 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = leq(uncommonBits_109, UInt<5>(0h1f)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1072 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) wire _WIRE_2 : UInt<1>[25] connect _WIRE_2[0], _T_938 connect _WIRE_2[1], _T_944 connect _WIRE_2[2], _T_950 connect _WIRE_2[3], _T_956 connect _WIRE_2[4], _T_962 connect _WIRE_2[5], _T_968 connect _WIRE_2[6], _T_974 connect _WIRE_2[7], _T_980 connect _WIRE_2[8], _T_986 connect _WIRE_2[9], _T_992 connect _WIRE_2[10], _T_998 connect _WIRE_2[11], _T_1004 connect _WIRE_2[12], _T_1010 connect _WIRE_2[13], _T_1016 connect _WIRE_2[14], _T_1022 connect _WIRE_2[15], _T_1028 connect _WIRE_2[16], _T_1034 connect _WIRE_2[17], _T_1040 connect _WIRE_2[18], _T_1046 connect _WIRE_2[19], _T_1052 connect _WIRE_2[20], _T_1058 connect _WIRE_2[21], _T_1064 connect _WIRE_2[22], _T_1070 connect _WIRE_2[23], _T_1071 connect _WIRE_2[24], _T_1072 node _T_1073 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_1074 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1075 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1076 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1077 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1078 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1079 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_1080 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1081 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_1082 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1083 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_1084 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1085 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1086 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1087 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_1088 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1089 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_1090 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1091 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_1092 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_1094 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_1096 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_1097 = mux(_WIRE_2[23], _T_1073, UInt<1>(0h0)) node _T_1098 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_1099 = or(_T_1074, _T_1075) node _T_1100 = or(_T_1099, _T_1076) node _T_1101 = or(_T_1100, _T_1077) node _T_1102 = or(_T_1101, _T_1078) node _T_1103 = or(_T_1102, _T_1079) node _T_1104 = or(_T_1103, _T_1080) node _T_1105 = or(_T_1104, _T_1081) node _T_1106 = or(_T_1105, _T_1082) node _T_1107 = or(_T_1106, _T_1083) node _T_1108 = or(_T_1107, _T_1084) node _T_1109 = or(_T_1108, _T_1085) node _T_1110 = or(_T_1109, _T_1086) node _T_1111 = or(_T_1110, _T_1087) node _T_1112 = or(_T_1111, _T_1088) node _T_1113 = or(_T_1112, _T_1089) node _T_1114 = or(_T_1113, _T_1090) node _T_1115 = or(_T_1114, _T_1091) node _T_1116 = or(_T_1115, _T_1092) node _T_1117 = or(_T_1116, _T_1093) node _T_1118 = or(_T_1117, _T_1094) node _T_1119 = or(_T_1118, _T_1095) node _T_1120 = or(_T_1119, _T_1096) node _T_1121 = or(_T_1120, _T_1097) node _T_1122 = or(_T_1121, _T_1098) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_1122 node _T_1123 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1124 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1125 = and(_T_1123, _T_1124) node _T_1126 = or(UInt<1>(0h0), _T_1125) node _T_1127 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<17>(0h10000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<29>(0h10000000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = or(_T_1131, _T_1136) node _T_1138 = and(_T_1126, _T_1137) node _T_1139 = or(UInt<1>(0h0), _T_1138) node _T_1140 = and(_WIRE_3, _T_1139) node _T_1141 = asUInt(reset) node _T_1142 = eq(_T_1141, UInt<1>(0h0)) when _T_1142 : node _T_1143 = eq(_T_1140, UInt<1>(0h0)) when _T_1143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1140, UInt<1>(0h1), "") : assert_11 node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1147 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_13 node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(is_aligned, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1154 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_15 node _T_1158 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(_T_1158, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1158, UInt<1>(0h1), "") : assert_16 node _T_1162 = not(io.in.a.bits.mask) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_17 node _T_1167 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_18 node _T_1171 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1171 : node _T_1172 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1173 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1176 = shr(io.in.a.bits.source, 2) node _T_1177 = eq(_T_1176, UInt<7>(0h70)) node _T_1178 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1181 = and(_T_1179, _T_1180) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1182 = shr(io.in.a.bits.source, 2) node _T_1183 = eq(_T_1182, UInt<7>(0h71)) node _T_1184 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1185 = and(_T_1183, _T_1184) node _T_1186 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1187 = and(_T_1185, _T_1186) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<7>(0h72)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_112, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<7>(0h73)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_113, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<7>(0h7c)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_114, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 1, 0) node _T_1206 = shr(io.in.a.bits.source, 2) node _T_1207 = eq(_T_1206, UInt<7>(0h7b)) node _T_1208 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1209 = and(_T_1207, _T_1208) node _T_1210 = leq(uncommonBits_115, UInt<2>(0h3)) node _T_1211 = and(_T_1209, _T_1210) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1212 = shr(io.in.a.bits.source, 5) node _T_1213 = eq(_T_1212, UInt<4>(0hd)) node _T_1214 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1217 = and(_T_1215, _T_1216) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1218 = shr(io.in.a.bits.source, 5) node _T_1219 = eq(_T_1218, UInt<4>(0hc)) node _T_1220 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1221 = and(_T_1219, _T_1220) node _T_1222 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1223 = and(_T_1221, _T_1222) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1224 = shr(io.in.a.bits.source, 5) node _T_1225 = eq(_T_1224, UInt<4>(0hb)) node _T_1226 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1229 = and(_T_1227, _T_1228) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1230 = shr(io.in.a.bits.source, 5) node _T_1231 = eq(_T_1230, UInt<4>(0ha)) node _T_1232 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1235 = and(_T_1233, _T_1234) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 4, 0) node _T_1236 = shr(io.in.a.bits.source, 5) node _T_1237 = eq(_T_1236, UInt<4>(0h9)) node _T_1238 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = leq(uncommonBits_120, UInt<5>(0h1f)) node _T_1241 = and(_T_1239, _T_1240) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 4, 0) node _T_1242 = shr(io.in.a.bits.source, 5) node _T_1243 = eq(_T_1242, UInt<4>(0h8)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_121, UInt<5>(0h1f)) node _T_1247 = and(_T_1245, _T_1246) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1248 = shr(io.in.a.bits.source, 2) node _T_1249 = eq(_T_1248, UInt<7>(0h7a)) node _T_1250 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1253 = and(_T_1251, _T_1252) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1254 = shr(io.in.a.bits.source, 2) node _T_1255 = eq(_T_1254, UInt<7>(0h79)) node _T_1256 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1259 = and(_T_1257, _T_1258) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1260 = shr(io.in.a.bits.source, 5) node _T_1261 = eq(_T_1260, UInt<3>(0h7)) node _T_1262 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1265 = and(_T_1263, _T_1264) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1266 = shr(io.in.a.bits.source, 5) node _T_1267 = eq(_T_1266, UInt<3>(0h6)) node _T_1268 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1271 = and(_T_1269, _T_1270) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1272 = shr(io.in.a.bits.source, 5) node _T_1273 = eq(_T_1272, UInt<3>(0h5)) node _T_1274 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1277 = and(_T_1275, _T_1276) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1278 = shr(io.in.a.bits.source, 5) node _T_1279 = eq(_T_1278, UInt<3>(0h4)) node _T_1280 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1281 = and(_T_1279, _T_1280) node _T_1282 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1283 = and(_T_1281, _T_1282) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1284 = shr(io.in.a.bits.source, 5) node _T_1285 = eq(_T_1284, UInt<2>(0h3)) node _T_1286 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1289 = and(_T_1287, _T_1288) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1290 = shr(io.in.a.bits.source, 5) node _T_1291 = eq(_T_1290, UInt<2>(0h2)) node _T_1292 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1293 = and(_T_1291, _T_1292) node _T_1294 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1295 = and(_T_1293, _T_1294) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1296 = shr(io.in.a.bits.source, 5) node _T_1297 = eq(_T_1296, UInt<1>(0h1)) node _T_1298 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1301 = and(_T_1299, _T_1300) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1302 = shr(io.in.a.bits.source, 5) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) node _T_1304 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1307 = and(_T_1305, _T_1306) node _T_1308 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1309 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1310 = or(_T_1175, _T_1181) node _T_1311 = or(_T_1310, _T_1187) node _T_1312 = or(_T_1311, _T_1193) node _T_1313 = or(_T_1312, _T_1199) node _T_1314 = or(_T_1313, _T_1205) node _T_1315 = or(_T_1314, _T_1211) node _T_1316 = or(_T_1315, _T_1217) node _T_1317 = or(_T_1316, _T_1223) node _T_1318 = or(_T_1317, _T_1229) node _T_1319 = or(_T_1318, _T_1235) node _T_1320 = or(_T_1319, _T_1241) node _T_1321 = or(_T_1320, _T_1247) node _T_1322 = or(_T_1321, _T_1253) node _T_1323 = or(_T_1322, _T_1259) node _T_1324 = or(_T_1323, _T_1265) node _T_1325 = or(_T_1324, _T_1271) node _T_1326 = or(_T_1325, _T_1277) node _T_1327 = or(_T_1326, _T_1283) node _T_1328 = or(_T_1327, _T_1289) node _T_1329 = or(_T_1328, _T_1295) node _T_1330 = or(_T_1329, _T_1301) node _T_1331 = or(_T_1330, _T_1307) node _T_1332 = or(_T_1331, _T_1308) node _T_1333 = or(_T_1332, _T_1309) node _T_1334 = and(_T_1174, _T_1333) node _T_1335 = or(UInt<1>(0h0), _T_1334) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_19 node _T_1339 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1340 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = or(UInt<1>(0h0), _T_1341) node _T_1343 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1344 = cvt(_T_1343) node _T_1345 = and(_T_1344, asSInt(UInt<17>(0h10000))) node _T_1346 = asSInt(_T_1345) node _T_1347 = eq(_T_1346, asSInt(UInt<1>(0h0))) node _T_1348 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1349 = cvt(_T_1348) node _T_1350 = and(_T_1349, asSInt(UInt<29>(0h10000000))) node _T_1351 = asSInt(_T_1350) node _T_1352 = eq(_T_1351, asSInt(UInt<1>(0h0))) node _T_1353 = or(_T_1347, _T_1352) node _T_1354 = and(_T_1342, _T_1353) node _T_1355 = or(UInt<1>(0h0), _T_1354) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_20 node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(source_ok, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(is_aligned, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1365 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_23 node _T_1369 = eq(io.in.a.bits.mask, mask) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_24 node _T_1373 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_25 node _T_1377 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1377 : node _T_1378 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1379 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1380 = and(_T_1378, _T_1379) node _T_1381 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_132 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_132 = bits(_uncommonBits_T_132, 1, 0) node _T_1382 = shr(io.in.a.bits.source, 2) node _T_1383 = eq(_T_1382, UInt<7>(0h70)) node _T_1384 = leq(UInt<1>(0h0), uncommonBits_132) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = leq(uncommonBits_132, UInt<2>(0h3)) node _T_1387 = and(_T_1385, _T_1386) node _uncommonBits_T_133 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_133 = bits(_uncommonBits_T_133, 1, 0) node _T_1388 = shr(io.in.a.bits.source, 2) node _T_1389 = eq(_T_1388, UInt<7>(0h71)) node _T_1390 = leq(UInt<1>(0h0), uncommonBits_133) node _T_1391 = and(_T_1389, _T_1390) node _T_1392 = leq(uncommonBits_133, UInt<2>(0h3)) node _T_1393 = and(_T_1391, _T_1392) node _uncommonBits_T_134 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_134 = bits(_uncommonBits_T_134, 1, 0) node _T_1394 = shr(io.in.a.bits.source, 2) node _T_1395 = eq(_T_1394, UInt<7>(0h72)) node _T_1396 = leq(UInt<1>(0h0), uncommonBits_134) node _T_1397 = and(_T_1395, _T_1396) node _T_1398 = leq(uncommonBits_134, UInt<2>(0h3)) node _T_1399 = and(_T_1397, _T_1398) node _uncommonBits_T_135 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_135 = bits(_uncommonBits_T_135, 1, 0) node _T_1400 = shr(io.in.a.bits.source, 2) node _T_1401 = eq(_T_1400, UInt<7>(0h73)) node _T_1402 = leq(UInt<1>(0h0), uncommonBits_135) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = leq(uncommonBits_135, UInt<2>(0h3)) node _T_1405 = and(_T_1403, _T_1404) node _uncommonBits_T_136 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_136 = bits(_uncommonBits_T_136, 1, 0) node _T_1406 = shr(io.in.a.bits.source, 2) node _T_1407 = eq(_T_1406, UInt<7>(0h7c)) node _T_1408 = leq(UInt<1>(0h0), uncommonBits_136) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = leq(uncommonBits_136, UInt<2>(0h3)) node _T_1411 = and(_T_1409, _T_1410) node _uncommonBits_T_137 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_137 = bits(_uncommonBits_T_137, 1, 0) node _T_1412 = shr(io.in.a.bits.source, 2) node _T_1413 = eq(_T_1412, UInt<7>(0h7b)) node _T_1414 = leq(UInt<1>(0h0), uncommonBits_137) node _T_1415 = and(_T_1413, _T_1414) node _T_1416 = leq(uncommonBits_137, UInt<2>(0h3)) node _T_1417 = and(_T_1415, _T_1416) node _uncommonBits_T_138 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_138 = bits(_uncommonBits_T_138, 4, 0) node _T_1418 = shr(io.in.a.bits.source, 5) node _T_1419 = eq(_T_1418, UInt<4>(0hd)) node _T_1420 = leq(UInt<1>(0h0), uncommonBits_138) node _T_1421 = and(_T_1419, _T_1420) node _T_1422 = leq(uncommonBits_138, UInt<5>(0h1f)) node _T_1423 = and(_T_1421, _T_1422) node _uncommonBits_T_139 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_139 = bits(_uncommonBits_T_139, 4, 0) node _T_1424 = shr(io.in.a.bits.source, 5) node _T_1425 = eq(_T_1424, UInt<4>(0hc)) node _T_1426 = leq(UInt<1>(0h0), uncommonBits_139) node _T_1427 = and(_T_1425, _T_1426) node _T_1428 = leq(uncommonBits_139, UInt<5>(0h1f)) node _T_1429 = and(_T_1427, _T_1428) node _uncommonBits_T_140 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_140 = bits(_uncommonBits_T_140, 4, 0) node _T_1430 = shr(io.in.a.bits.source, 5) node _T_1431 = eq(_T_1430, UInt<4>(0hb)) node _T_1432 = leq(UInt<1>(0h0), uncommonBits_140) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = leq(uncommonBits_140, UInt<5>(0h1f)) node _T_1435 = and(_T_1433, _T_1434) node _uncommonBits_T_141 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_141 = bits(_uncommonBits_T_141, 4, 0) node _T_1436 = shr(io.in.a.bits.source, 5) node _T_1437 = eq(_T_1436, UInt<4>(0ha)) node _T_1438 = leq(UInt<1>(0h0), uncommonBits_141) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = leq(uncommonBits_141, UInt<5>(0h1f)) node _T_1441 = and(_T_1439, _T_1440) node _uncommonBits_T_142 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_142 = bits(_uncommonBits_T_142, 4, 0) node _T_1442 = shr(io.in.a.bits.source, 5) node _T_1443 = eq(_T_1442, UInt<4>(0h9)) node _T_1444 = leq(UInt<1>(0h0), uncommonBits_142) node _T_1445 = and(_T_1443, _T_1444) node _T_1446 = leq(uncommonBits_142, UInt<5>(0h1f)) node _T_1447 = and(_T_1445, _T_1446) node _uncommonBits_T_143 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_143 = bits(_uncommonBits_T_143, 4, 0) node _T_1448 = shr(io.in.a.bits.source, 5) node _T_1449 = eq(_T_1448, UInt<4>(0h8)) node _T_1450 = leq(UInt<1>(0h0), uncommonBits_143) node _T_1451 = and(_T_1449, _T_1450) node _T_1452 = leq(uncommonBits_143, UInt<5>(0h1f)) node _T_1453 = and(_T_1451, _T_1452) node _uncommonBits_T_144 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_144 = bits(_uncommonBits_T_144, 1, 0) node _T_1454 = shr(io.in.a.bits.source, 2) node _T_1455 = eq(_T_1454, UInt<7>(0h7a)) node _T_1456 = leq(UInt<1>(0h0), uncommonBits_144) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = leq(uncommonBits_144, UInt<2>(0h3)) node _T_1459 = and(_T_1457, _T_1458) node _uncommonBits_T_145 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_145 = bits(_uncommonBits_T_145, 1, 0) node _T_1460 = shr(io.in.a.bits.source, 2) node _T_1461 = eq(_T_1460, UInt<7>(0h79)) node _T_1462 = leq(UInt<1>(0h0), uncommonBits_145) node _T_1463 = and(_T_1461, _T_1462) node _T_1464 = leq(uncommonBits_145, UInt<2>(0h3)) node _T_1465 = and(_T_1463, _T_1464) node _uncommonBits_T_146 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_146 = bits(_uncommonBits_T_146, 4, 0) node _T_1466 = shr(io.in.a.bits.source, 5) node _T_1467 = eq(_T_1466, UInt<3>(0h7)) node _T_1468 = leq(UInt<1>(0h0), uncommonBits_146) node _T_1469 = and(_T_1467, _T_1468) node _T_1470 = leq(uncommonBits_146, UInt<5>(0h1f)) node _T_1471 = and(_T_1469, _T_1470) node _uncommonBits_T_147 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_147 = bits(_uncommonBits_T_147, 4, 0) node _T_1472 = shr(io.in.a.bits.source, 5) node _T_1473 = eq(_T_1472, UInt<3>(0h6)) node _T_1474 = leq(UInt<1>(0h0), uncommonBits_147) node _T_1475 = and(_T_1473, _T_1474) node _T_1476 = leq(uncommonBits_147, UInt<5>(0h1f)) node _T_1477 = and(_T_1475, _T_1476) node _uncommonBits_T_148 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_148 = bits(_uncommonBits_T_148, 4, 0) node _T_1478 = shr(io.in.a.bits.source, 5) node _T_1479 = eq(_T_1478, UInt<3>(0h5)) node _T_1480 = leq(UInt<1>(0h0), uncommonBits_148) node _T_1481 = and(_T_1479, _T_1480) node _T_1482 = leq(uncommonBits_148, UInt<5>(0h1f)) node _T_1483 = and(_T_1481, _T_1482) node _uncommonBits_T_149 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_149 = bits(_uncommonBits_T_149, 4, 0) node _T_1484 = shr(io.in.a.bits.source, 5) node _T_1485 = eq(_T_1484, UInt<3>(0h4)) node _T_1486 = leq(UInt<1>(0h0), uncommonBits_149) node _T_1487 = and(_T_1485, _T_1486) node _T_1488 = leq(uncommonBits_149, UInt<5>(0h1f)) node _T_1489 = and(_T_1487, _T_1488) node _uncommonBits_T_150 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_150 = bits(_uncommonBits_T_150, 4, 0) node _T_1490 = shr(io.in.a.bits.source, 5) node _T_1491 = eq(_T_1490, UInt<2>(0h3)) node _T_1492 = leq(UInt<1>(0h0), uncommonBits_150) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = leq(uncommonBits_150, UInt<5>(0h1f)) node _T_1495 = and(_T_1493, _T_1494) node _uncommonBits_T_151 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_151 = bits(_uncommonBits_T_151, 4, 0) node _T_1496 = shr(io.in.a.bits.source, 5) node _T_1497 = eq(_T_1496, UInt<2>(0h2)) node _T_1498 = leq(UInt<1>(0h0), uncommonBits_151) node _T_1499 = and(_T_1497, _T_1498) node _T_1500 = leq(uncommonBits_151, UInt<5>(0h1f)) node _T_1501 = and(_T_1499, _T_1500) node _uncommonBits_T_152 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_152 = bits(_uncommonBits_T_152, 4, 0) node _T_1502 = shr(io.in.a.bits.source, 5) node _T_1503 = eq(_T_1502, UInt<1>(0h1)) node _T_1504 = leq(UInt<1>(0h0), uncommonBits_152) node _T_1505 = and(_T_1503, _T_1504) node _T_1506 = leq(uncommonBits_152, UInt<5>(0h1f)) node _T_1507 = and(_T_1505, _T_1506) node _uncommonBits_T_153 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_153 = bits(_uncommonBits_T_153, 4, 0) node _T_1508 = shr(io.in.a.bits.source, 5) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) node _T_1510 = leq(UInt<1>(0h0), uncommonBits_153) node _T_1511 = and(_T_1509, _T_1510) node _T_1512 = leq(uncommonBits_153, UInt<5>(0h1f)) node _T_1513 = and(_T_1511, _T_1512) node _T_1514 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1515 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1516 = or(_T_1381, _T_1387) node _T_1517 = or(_T_1516, _T_1393) node _T_1518 = or(_T_1517, _T_1399) node _T_1519 = or(_T_1518, _T_1405) node _T_1520 = or(_T_1519, _T_1411) node _T_1521 = or(_T_1520, _T_1417) node _T_1522 = or(_T_1521, _T_1423) node _T_1523 = or(_T_1522, _T_1429) node _T_1524 = or(_T_1523, _T_1435) node _T_1525 = or(_T_1524, _T_1441) node _T_1526 = or(_T_1525, _T_1447) node _T_1527 = or(_T_1526, _T_1453) node _T_1528 = or(_T_1527, _T_1459) node _T_1529 = or(_T_1528, _T_1465) node _T_1530 = or(_T_1529, _T_1471) node _T_1531 = or(_T_1530, _T_1477) node _T_1532 = or(_T_1531, _T_1483) node _T_1533 = or(_T_1532, _T_1489) node _T_1534 = or(_T_1533, _T_1495) node _T_1535 = or(_T_1534, _T_1501) node _T_1536 = or(_T_1535, _T_1507) node _T_1537 = or(_T_1536, _T_1513) node _T_1538 = or(_T_1537, _T_1514) node _T_1539 = or(_T_1538, _T_1515) node _T_1540 = and(_T_1380, _T_1539) node _T_1541 = or(UInt<1>(0h0), _T_1540) node _T_1542 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1543 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1544 = and(_T_1542, _T_1543) node _T_1545 = or(UInt<1>(0h0), _T_1544) node _T_1546 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1547 = cvt(_T_1546) node _T_1548 = and(_T_1547, asSInt(UInt<17>(0h10000))) node _T_1549 = asSInt(_T_1548) node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0))) node _T_1551 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1552 = cvt(_T_1551) node _T_1553 = and(_T_1552, asSInt(UInt<29>(0h10000000))) node _T_1554 = asSInt(_T_1553) node _T_1555 = eq(_T_1554, asSInt(UInt<1>(0h0))) node _T_1556 = or(_T_1550, _T_1555) node _T_1557 = and(_T_1545, _T_1556) node _T_1558 = or(UInt<1>(0h0), _T_1557) node _T_1559 = and(_T_1541, _T_1558) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_26 node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(source_ok, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(is_aligned, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_29 node _T_1573 = eq(io.in.a.bits.mask, mask) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_30 node _T_1577 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1577 : node _T_1578 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1579 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1580 = and(_T_1578, _T_1579) node _T_1581 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_154 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_154 = bits(_uncommonBits_T_154, 1, 0) node _T_1582 = shr(io.in.a.bits.source, 2) node _T_1583 = eq(_T_1582, UInt<7>(0h70)) node _T_1584 = leq(UInt<1>(0h0), uncommonBits_154) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = leq(uncommonBits_154, UInt<2>(0h3)) node _T_1587 = and(_T_1585, _T_1586) node _uncommonBits_T_155 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_155 = bits(_uncommonBits_T_155, 1, 0) node _T_1588 = shr(io.in.a.bits.source, 2) node _T_1589 = eq(_T_1588, UInt<7>(0h71)) node _T_1590 = leq(UInt<1>(0h0), uncommonBits_155) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = leq(uncommonBits_155, UInt<2>(0h3)) node _T_1593 = and(_T_1591, _T_1592) node _uncommonBits_T_156 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_156 = bits(_uncommonBits_T_156, 1, 0) node _T_1594 = shr(io.in.a.bits.source, 2) node _T_1595 = eq(_T_1594, UInt<7>(0h72)) node _T_1596 = leq(UInt<1>(0h0), uncommonBits_156) node _T_1597 = and(_T_1595, _T_1596) node _T_1598 = leq(uncommonBits_156, UInt<2>(0h3)) node _T_1599 = and(_T_1597, _T_1598) node _uncommonBits_T_157 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_157 = bits(_uncommonBits_T_157, 1, 0) node _T_1600 = shr(io.in.a.bits.source, 2) node _T_1601 = eq(_T_1600, UInt<7>(0h73)) node _T_1602 = leq(UInt<1>(0h0), uncommonBits_157) node _T_1603 = and(_T_1601, _T_1602) node _T_1604 = leq(uncommonBits_157, UInt<2>(0h3)) node _T_1605 = and(_T_1603, _T_1604) node _uncommonBits_T_158 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_158 = bits(_uncommonBits_T_158, 1, 0) node _T_1606 = shr(io.in.a.bits.source, 2) node _T_1607 = eq(_T_1606, UInt<7>(0h7c)) node _T_1608 = leq(UInt<1>(0h0), uncommonBits_158) node _T_1609 = and(_T_1607, _T_1608) node _T_1610 = leq(uncommonBits_158, UInt<2>(0h3)) node _T_1611 = and(_T_1609, _T_1610) node _uncommonBits_T_159 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_159 = bits(_uncommonBits_T_159, 1, 0) node _T_1612 = shr(io.in.a.bits.source, 2) node _T_1613 = eq(_T_1612, UInt<7>(0h7b)) node _T_1614 = leq(UInt<1>(0h0), uncommonBits_159) node _T_1615 = and(_T_1613, _T_1614) node _T_1616 = leq(uncommonBits_159, UInt<2>(0h3)) node _T_1617 = and(_T_1615, _T_1616) node _uncommonBits_T_160 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_160 = bits(_uncommonBits_T_160, 4, 0) node _T_1618 = shr(io.in.a.bits.source, 5) node _T_1619 = eq(_T_1618, UInt<4>(0hd)) node _T_1620 = leq(UInt<1>(0h0), uncommonBits_160) node _T_1621 = and(_T_1619, _T_1620) node _T_1622 = leq(uncommonBits_160, UInt<5>(0h1f)) node _T_1623 = and(_T_1621, _T_1622) node _uncommonBits_T_161 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_161 = bits(_uncommonBits_T_161, 4, 0) node _T_1624 = shr(io.in.a.bits.source, 5) node _T_1625 = eq(_T_1624, UInt<4>(0hc)) node _T_1626 = leq(UInt<1>(0h0), uncommonBits_161) node _T_1627 = and(_T_1625, _T_1626) node _T_1628 = leq(uncommonBits_161, UInt<5>(0h1f)) node _T_1629 = and(_T_1627, _T_1628) node _uncommonBits_T_162 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_162 = bits(_uncommonBits_T_162, 4, 0) node _T_1630 = shr(io.in.a.bits.source, 5) node _T_1631 = eq(_T_1630, UInt<4>(0hb)) node _T_1632 = leq(UInt<1>(0h0), uncommonBits_162) node _T_1633 = and(_T_1631, _T_1632) node _T_1634 = leq(uncommonBits_162, UInt<5>(0h1f)) node _T_1635 = and(_T_1633, _T_1634) node _uncommonBits_T_163 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_163 = bits(_uncommonBits_T_163, 4, 0) node _T_1636 = shr(io.in.a.bits.source, 5) node _T_1637 = eq(_T_1636, UInt<4>(0ha)) node _T_1638 = leq(UInt<1>(0h0), uncommonBits_163) node _T_1639 = and(_T_1637, _T_1638) node _T_1640 = leq(uncommonBits_163, UInt<5>(0h1f)) node _T_1641 = and(_T_1639, _T_1640) node _uncommonBits_T_164 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_164 = bits(_uncommonBits_T_164, 4, 0) node _T_1642 = shr(io.in.a.bits.source, 5) node _T_1643 = eq(_T_1642, UInt<4>(0h9)) node _T_1644 = leq(UInt<1>(0h0), uncommonBits_164) node _T_1645 = and(_T_1643, _T_1644) node _T_1646 = leq(uncommonBits_164, UInt<5>(0h1f)) node _T_1647 = and(_T_1645, _T_1646) node _uncommonBits_T_165 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_165 = bits(_uncommonBits_T_165, 4, 0) node _T_1648 = shr(io.in.a.bits.source, 5) node _T_1649 = eq(_T_1648, UInt<4>(0h8)) node _T_1650 = leq(UInt<1>(0h0), uncommonBits_165) node _T_1651 = and(_T_1649, _T_1650) node _T_1652 = leq(uncommonBits_165, UInt<5>(0h1f)) node _T_1653 = and(_T_1651, _T_1652) node _uncommonBits_T_166 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_166 = bits(_uncommonBits_T_166, 1, 0) node _T_1654 = shr(io.in.a.bits.source, 2) node _T_1655 = eq(_T_1654, UInt<7>(0h7a)) node _T_1656 = leq(UInt<1>(0h0), uncommonBits_166) node _T_1657 = and(_T_1655, _T_1656) node _T_1658 = leq(uncommonBits_166, UInt<2>(0h3)) node _T_1659 = and(_T_1657, _T_1658) node _uncommonBits_T_167 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_167 = bits(_uncommonBits_T_167, 1, 0) node _T_1660 = shr(io.in.a.bits.source, 2) node _T_1661 = eq(_T_1660, UInt<7>(0h79)) node _T_1662 = leq(UInt<1>(0h0), uncommonBits_167) node _T_1663 = and(_T_1661, _T_1662) node _T_1664 = leq(uncommonBits_167, UInt<2>(0h3)) node _T_1665 = and(_T_1663, _T_1664) node _uncommonBits_T_168 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_168 = bits(_uncommonBits_T_168, 4, 0) node _T_1666 = shr(io.in.a.bits.source, 5) node _T_1667 = eq(_T_1666, UInt<3>(0h7)) node _T_1668 = leq(UInt<1>(0h0), uncommonBits_168) node _T_1669 = and(_T_1667, _T_1668) node _T_1670 = leq(uncommonBits_168, UInt<5>(0h1f)) node _T_1671 = and(_T_1669, _T_1670) node _uncommonBits_T_169 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_169 = bits(_uncommonBits_T_169, 4, 0) node _T_1672 = shr(io.in.a.bits.source, 5) node _T_1673 = eq(_T_1672, UInt<3>(0h6)) node _T_1674 = leq(UInt<1>(0h0), uncommonBits_169) node _T_1675 = and(_T_1673, _T_1674) node _T_1676 = leq(uncommonBits_169, UInt<5>(0h1f)) node _T_1677 = and(_T_1675, _T_1676) node _uncommonBits_T_170 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_170 = bits(_uncommonBits_T_170, 4, 0) node _T_1678 = shr(io.in.a.bits.source, 5) node _T_1679 = eq(_T_1678, UInt<3>(0h5)) node _T_1680 = leq(UInt<1>(0h0), uncommonBits_170) node _T_1681 = and(_T_1679, _T_1680) node _T_1682 = leq(uncommonBits_170, UInt<5>(0h1f)) node _T_1683 = and(_T_1681, _T_1682) node _uncommonBits_T_171 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_171 = bits(_uncommonBits_T_171, 4, 0) node _T_1684 = shr(io.in.a.bits.source, 5) node _T_1685 = eq(_T_1684, UInt<3>(0h4)) node _T_1686 = leq(UInt<1>(0h0), uncommonBits_171) node _T_1687 = and(_T_1685, _T_1686) node _T_1688 = leq(uncommonBits_171, UInt<5>(0h1f)) node _T_1689 = and(_T_1687, _T_1688) node _uncommonBits_T_172 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_172 = bits(_uncommonBits_T_172, 4, 0) node _T_1690 = shr(io.in.a.bits.source, 5) node _T_1691 = eq(_T_1690, UInt<2>(0h3)) node _T_1692 = leq(UInt<1>(0h0), uncommonBits_172) node _T_1693 = and(_T_1691, _T_1692) node _T_1694 = leq(uncommonBits_172, UInt<5>(0h1f)) node _T_1695 = and(_T_1693, _T_1694) node _uncommonBits_T_173 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_173 = bits(_uncommonBits_T_173, 4, 0) node _T_1696 = shr(io.in.a.bits.source, 5) node _T_1697 = eq(_T_1696, UInt<2>(0h2)) node _T_1698 = leq(UInt<1>(0h0), uncommonBits_173) node _T_1699 = and(_T_1697, _T_1698) node _T_1700 = leq(uncommonBits_173, UInt<5>(0h1f)) node _T_1701 = and(_T_1699, _T_1700) node _uncommonBits_T_174 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_174 = bits(_uncommonBits_T_174, 4, 0) node _T_1702 = shr(io.in.a.bits.source, 5) node _T_1703 = eq(_T_1702, UInt<1>(0h1)) node _T_1704 = leq(UInt<1>(0h0), uncommonBits_174) node _T_1705 = and(_T_1703, _T_1704) node _T_1706 = leq(uncommonBits_174, UInt<5>(0h1f)) node _T_1707 = and(_T_1705, _T_1706) node _uncommonBits_T_175 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_175 = bits(_uncommonBits_T_175, 4, 0) node _T_1708 = shr(io.in.a.bits.source, 5) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) node _T_1710 = leq(UInt<1>(0h0), uncommonBits_175) node _T_1711 = and(_T_1709, _T_1710) node _T_1712 = leq(uncommonBits_175, UInt<5>(0h1f)) node _T_1713 = and(_T_1711, _T_1712) node _T_1714 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1715 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1716 = or(_T_1581, _T_1587) node _T_1717 = or(_T_1716, _T_1593) node _T_1718 = or(_T_1717, _T_1599) node _T_1719 = or(_T_1718, _T_1605) node _T_1720 = or(_T_1719, _T_1611) node _T_1721 = or(_T_1720, _T_1617) node _T_1722 = or(_T_1721, _T_1623) node _T_1723 = or(_T_1722, _T_1629) node _T_1724 = or(_T_1723, _T_1635) node _T_1725 = or(_T_1724, _T_1641) node _T_1726 = or(_T_1725, _T_1647) node _T_1727 = or(_T_1726, _T_1653) node _T_1728 = or(_T_1727, _T_1659) node _T_1729 = or(_T_1728, _T_1665) node _T_1730 = or(_T_1729, _T_1671) node _T_1731 = or(_T_1730, _T_1677) node _T_1732 = or(_T_1731, _T_1683) node _T_1733 = or(_T_1732, _T_1689) node _T_1734 = or(_T_1733, _T_1695) node _T_1735 = or(_T_1734, _T_1701) node _T_1736 = or(_T_1735, _T_1707) node _T_1737 = or(_T_1736, _T_1713) node _T_1738 = or(_T_1737, _T_1714) node _T_1739 = or(_T_1738, _T_1715) node _T_1740 = and(_T_1580, _T_1739) node _T_1741 = or(UInt<1>(0h0), _T_1740) node _T_1742 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1743 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = or(UInt<1>(0h0), _T_1744) node _T_1746 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<17>(0h10000))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1752 = cvt(_T_1751) node _T_1753 = and(_T_1752, asSInt(UInt<29>(0h10000000))) node _T_1754 = asSInt(_T_1753) node _T_1755 = eq(_T_1754, asSInt(UInt<1>(0h0))) node _T_1756 = or(_T_1750, _T_1755) node _T_1757 = and(_T_1745, _T_1756) node _T_1758 = or(UInt<1>(0h0), _T_1757) node _T_1759 = and(_T_1741, _T_1758) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_31 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(source_ok, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1769 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_34 node _T_1773 = not(mask) node _T_1774 = and(io.in.a.bits.mask, _T_1773) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(_T_1775, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1775, UInt<1>(0h1), "") : assert_35 node _T_1779 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1779 : node _T_1780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1782 = and(_T_1780, _T_1781) node _T_1783 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_176 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_176 = bits(_uncommonBits_T_176, 1, 0) node _T_1784 = shr(io.in.a.bits.source, 2) node _T_1785 = eq(_T_1784, UInt<7>(0h70)) node _T_1786 = leq(UInt<1>(0h0), uncommonBits_176) node _T_1787 = and(_T_1785, _T_1786) node _T_1788 = leq(uncommonBits_176, UInt<2>(0h3)) node _T_1789 = and(_T_1787, _T_1788) node _uncommonBits_T_177 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_177 = bits(_uncommonBits_T_177, 1, 0) node _T_1790 = shr(io.in.a.bits.source, 2) node _T_1791 = eq(_T_1790, UInt<7>(0h71)) node _T_1792 = leq(UInt<1>(0h0), uncommonBits_177) node _T_1793 = and(_T_1791, _T_1792) node _T_1794 = leq(uncommonBits_177, UInt<2>(0h3)) node _T_1795 = and(_T_1793, _T_1794) node _uncommonBits_T_178 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_178 = bits(_uncommonBits_T_178, 1, 0) node _T_1796 = shr(io.in.a.bits.source, 2) node _T_1797 = eq(_T_1796, UInt<7>(0h72)) node _T_1798 = leq(UInt<1>(0h0), uncommonBits_178) node _T_1799 = and(_T_1797, _T_1798) node _T_1800 = leq(uncommonBits_178, UInt<2>(0h3)) node _T_1801 = and(_T_1799, _T_1800) node _uncommonBits_T_179 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_179 = bits(_uncommonBits_T_179, 1, 0) node _T_1802 = shr(io.in.a.bits.source, 2) node _T_1803 = eq(_T_1802, UInt<7>(0h73)) node _T_1804 = leq(UInt<1>(0h0), uncommonBits_179) node _T_1805 = and(_T_1803, _T_1804) node _T_1806 = leq(uncommonBits_179, UInt<2>(0h3)) node _T_1807 = and(_T_1805, _T_1806) node _uncommonBits_T_180 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_180 = bits(_uncommonBits_T_180, 1, 0) node _T_1808 = shr(io.in.a.bits.source, 2) node _T_1809 = eq(_T_1808, UInt<7>(0h7c)) node _T_1810 = leq(UInt<1>(0h0), uncommonBits_180) node _T_1811 = and(_T_1809, _T_1810) node _T_1812 = leq(uncommonBits_180, UInt<2>(0h3)) node _T_1813 = and(_T_1811, _T_1812) node _uncommonBits_T_181 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_181 = bits(_uncommonBits_T_181, 1, 0) node _T_1814 = shr(io.in.a.bits.source, 2) node _T_1815 = eq(_T_1814, UInt<7>(0h7b)) node _T_1816 = leq(UInt<1>(0h0), uncommonBits_181) node _T_1817 = and(_T_1815, _T_1816) node _T_1818 = leq(uncommonBits_181, UInt<2>(0h3)) node _T_1819 = and(_T_1817, _T_1818) node _uncommonBits_T_182 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_182 = bits(_uncommonBits_T_182, 4, 0) node _T_1820 = shr(io.in.a.bits.source, 5) node _T_1821 = eq(_T_1820, UInt<4>(0hd)) node _T_1822 = leq(UInt<1>(0h0), uncommonBits_182) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = leq(uncommonBits_182, UInt<5>(0h1f)) node _T_1825 = and(_T_1823, _T_1824) node _uncommonBits_T_183 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_183 = bits(_uncommonBits_T_183, 4, 0) node _T_1826 = shr(io.in.a.bits.source, 5) node _T_1827 = eq(_T_1826, UInt<4>(0hc)) node _T_1828 = leq(UInt<1>(0h0), uncommonBits_183) node _T_1829 = and(_T_1827, _T_1828) node _T_1830 = leq(uncommonBits_183, UInt<5>(0h1f)) node _T_1831 = and(_T_1829, _T_1830) node _uncommonBits_T_184 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_184 = bits(_uncommonBits_T_184, 4, 0) node _T_1832 = shr(io.in.a.bits.source, 5) node _T_1833 = eq(_T_1832, UInt<4>(0hb)) node _T_1834 = leq(UInt<1>(0h0), uncommonBits_184) node _T_1835 = and(_T_1833, _T_1834) node _T_1836 = leq(uncommonBits_184, UInt<5>(0h1f)) node _T_1837 = and(_T_1835, _T_1836) node _uncommonBits_T_185 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_185 = bits(_uncommonBits_T_185, 4, 0) node _T_1838 = shr(io.in.a.bits.source, 5) node _T_1839 = eq(_T_1838, UInt<4>(0ha)) node _T_1840 = leq(UInt<1>(0h0), uncommonBits_185) node _T_1841 = and(_T_1839, _T_1840) node _T_1842 = leq(uncommonBits_185, UInt<5>(0h1f)) node _T_1843 = and(_T_1841, _T_1842) node _uncommonBits_T_186 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_186 = bits(_uncommonBits_T_186, 4, 0) node _T_1844 = shr(io.in.a.bits.source, 5) node _T_1845 = eq(_T_1844, UInt<4>(0h9)) node _T_1846 = leq(UInt<1>(0h0), uncommonBits_186) node _T_1847 = and(_T_1845, _T_1846) node _T_1848 = leq(uncommonBits_186, UInt<5>(0h1f)) node _T_1849 = and(_T_1847, _T_1848) node _uncommonBits_T_187 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_187 = bits(_uncommonBits_T_187, 4, 0) node _T_1850 = shr(io.in.a.bits.source, 5) node _T_1851 = eq(_T_1850, UInt<4>(0h8)) node _T_1852 = leq(UInt<1>(0h0), uncommonBits_187) node _T_1853 = and(_T_1851, _T_1852) node _T_1854 = leq(uncommonBits_187, UInt<5>(0h1f)) node _T_1855 = and(_T_1853, _T_1854) node _uncommonBits_T_188 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_188 = bits(_uncommonBits_T_188, 1, 0) node _T_1856 = shr(io.in.a.bits.source, 2) node _T_1857 = eq(_T_1856, UInt<7>(0h7a)) node _T_1858 = leq(UInt<1>(0h0), uncommonBits_188) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = leq(uncommonBits_188, UInt<2>(0h3)) node _T_1861 = and(_T_1859, _T_1860) node _uncommonBits_T_189 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_189 = bits(_uncommonBits_T_189, 1, 0) node _T_1862 = shr(io.in.a.bits.source, 2) node _T_1863 = eq(_T_1862, UInt<7>(0h79)) node _T_1864 = leq(UInt<1>(0h0), uncommonBits_189) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = leq(uncommonBits_189, UInt<2>(0h3)) node _T_1867 = and(_T_1865, _T_1866) node _uncommonBits_T_190 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_190 = bits(_uncommonBits_T_190, 4, 0) node _T_1868 = shr(io.in.a.bits.source, 5) node _T_1869 = eq(_T_1868, UInt<3>(0h7)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_190) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_190, UInt<5>(0h1f)) node _T_1873 = and(_T_1871, _T_1872) node _uncommonBits_T_191 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_191 = bits(_uncommonBits_T_191, 4, 0) node _T_1874 = shr(io.in.a.bits.source, 5) node _T_1875 = eq(_T_1874, UInt<3>(0h6)) node _T_1876 = leq(UInt<1>(0h0), uncommonBits_191) node _T_1877 = and(_T_1875, _T_1876) node _T_1878 = leq(uncommonBits_191, UInt<5>(0h1f)) node _T_1879 = and(_T_1877, _T_1878) node _uncommonBits_T_192 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_192 = bits(_uncommonBits_T_192, 4, 0) node _T_1880 = shr(io.in.a.bits.source, 5) node _T_1881 = eq(_T_1880, UInt<3>(0h5)) node _T_1882 = leq(UInt<1>(0h0), uncommonBits_192) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = leq(uncommonBits_192, UInt<5>(0h1f)) node _T_1885 = and(_T_1883, _T_1884) node _uncommonBits_T_193 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_193 = bits(_uncommonBits_T_193, 4, 0) node _T_1886 = shr(io.in.a.bits.source, 5) node _T_1887 = eq(_T_1886, UInt<3>(0h4)) node _T_1888 = leq(UInt<1>(0h0), uncommonBits_193) node _T_1889 = and(_T_1887, _T_1888) node _T_1890 = leq(uncommonBits_193, UInt<5>(0h1f)) node _T_1891 = and(_T_1889, _T_1890) node _uncommonBits_T_194 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_194 = bits(_uncommonBits_T_194, 4, 0) node _T_1892 = shr(io.in.a.bits.source, 5) node _T_1893 = eq(_T_1892, UInt<2>(0h3)) node _T_1894 = leq(UInt<1>(0h0), uncommonBits_194) node _T_1895 = and(_T_1893, _T_1894) node _T_1896 = leq(uncommonBits_194, UInt<5>(0h1f)) node _T_1897 = and(_T_1895, _T_1896) node _uncommonBits_T_195 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_195 = bits(_uncommonBits_T_195, 4, 0) node _T_1898 = shr(io.in.a.bits.source, 5) node _T_1899 = eq(_T_1898, UInt<2>(0h2)) node _T_1900 = leq(UInt<1>(0h0), uncommonBits_195) node _T_1901 = and(_T_1899, _T_1900) node _T_1902 = leq(uncommonBits_195, UInt<5>(0h1f)) node _T_1903 = and(_T_1901, _T_1902) node _uncommonBits_T_196 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_196 = bits(_uncommonBits_T_196, 4, 0) node _T_1904 = shr(io.in.a.bits.source, 5) node _T_1905 = eq(_T_1904, UInt<1>(0h1)) node _T_1906 = leq(UInt<1>(0h0), uncommonBits_196) node _T_1907 = and(_T_1905, _T_1906) node _T_1908 = leq(uncommonBits_196, UInt<5>(0h1f)) node _T_1909 = and(_T_1907, _T_1908) node _uncommonBits_T_197 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_197 = bits(_uncommonBits_T_197, 4, 0) node _T_1910 = shr(io.in.a.bits.source, 5) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) node _T_1912 = leq(UInt<1>(0h0), uncommonBits_197) node _T_1913 = and(_T_1911, _T_1912) node _T_1914 = leq(uncommonBits_197, UInt<5>(0h1f)) node _T_1915 = and(_T_1913, _T_1914) node _T_1916 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_1917 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_1918 = or(_T_1783, _T_1789) node _T_1919 = or(_T_1918, _T_1795) node _T_1920 = or(_T_1919, _T_1801) node _T_1921 = or(_T_1920, _T_1807) node _T_1922 = or(_T_1921, _T_1813) node _T_1923 = or(_T_1922, _T_1819) node _T_1924 = or(_T_1923, _T_1825) node _T_1925 = or(_T_1924, _T_1831) node _T_1926 = or(_T_1925, _T_1837) node _T_1927 = or(_T_1926, _T_1843) node _T_1928 = or(_T_1927, _T_1849) node _T_1929 = or(_T_1928, _T_1855) node _T_1930 = or(_T_1929, _T_1861) node _T_1931 = or(_T_1930, _T_1867) node _T_1932 = or(_T_1931, _T_1873) node _T_1933 = or(_T_1932, _T_1879) node _T_1934 = or(_T_1933, _T_1885) node _T_1935 = or(_T_1934, _T_1891) node _T_1936 = or(_T_1935, _T_1897) node _T_1937 = or(_T_1936, _T_1903) node _T_1938 = or(_T_1937, _T_1909) node _T_1939 = or(_T_1938, _T_1915) node _T_1940 = or(_T_1939, _T_1916) node _T_1941 = or(_T_1940, _T_1917) node _T_1942 = and(_T_1782, _T_1941) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1945 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1946 = and(_T_1944, _T_1945) node _T_1947 = or(UInt<1>(0h0), _T_1946) node _T_1948 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<17>(0h10000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1952, _T_1957) node _T_1959 = and(_T_1947, _T_1958) node _T_1960 = or(UInt<1>(0h0), _T_1959) node _T_1961 = and(_T_1943, _T_1960) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_36 node _T_1965 = asUInt(reset) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) when _T_1966 : node _T_1967 = eq(source_ok, UInt<1>(0h0)) when _T_1967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(is_aligned, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1971 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1972 = asUInt(reset) node _T_1973 = eq(_T_1972, UInt<1>(0h0)) when _T_1973 : node _T_1974 = eq(_T_1971, UInt<1>(0h0)) when _T_1974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1971, UInt<1>(0h1), "") : assert_39 node _T_1975 = eq(io.in.a.bits.mask, mask) node _T_1976 = asUInt(reset) node _T_1977 = eq(_T_1976, UInt<1>(0h0)) when _T_1977 : node _T_1978 = eq(_T_1975, UInt<1>(0h0)) when _T_1978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1975, UInt<1>(0h1), "") : assert_40 node _T_1979 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1979 : node _T_1980 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1981 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1982 = and(_T_1980, _T_1981) node _T_1983 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_198 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_198 = bits(_uncommonBits_T_198, 1, 0) node _T_1984 = shr(io.in.a.bits.source, 2) node _T_1985 = eq(_T_1984, UInt<7>(0h70)) node _T_1986 = leq(UInt<1>(0h0), uncommonBits_198) node _T_1987 = and(_T_1985, _T_1986) node _T_1988 = leq(uncommonBits_198, UInt<2>(0h3)) node _T_1989 = and(_T_1987, _T_1988) node _uncommonBits_T_199 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_199 = bits(_uncommonBits_T_199, 1, 0) node _T_1990 = shr(io.in.a.bits.source, 2) node _T_1991 = eq(_T_1990, UInt<7>(0h71)) node _T_1992 = leq(UInt<1>(0h0), uncommonBits_199) node _T_1993 = and(_T_1991, _T_1992) node _T_1994 = leq(uncommonBits_199, UInt<2>(0h3)) node _T_1995 = and(_T_1993, _T_1994) node _uncommonBits_T_200 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_200 = bits(_uncommonBits_T_200, 1, 0) node _T_1996 = shr(io.in.a.bits.source, 2) node _T_1997 = eq(_T_1996, UInt<7>(0h72)) node _T_1998 = leq(UInt<1>(0h0), uncommonBits_200) node _T_1999 = and(_T_1997, _T_1998) node _T_2000 = leq(uncommonBits_200, UInt<2>(0h3)) node _T_2001 = and(_T_1999, _T_2000) node _uncommonBits_T_201 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_201 = bits(_uncommonBits_T_201, 1, 0) node _T_2002 = shr(io.in.a.bits.source, 2) node _T_2003 = eq(_T_2002, UInt<7>(0h73)) node _T_2004 = leq(UInt<1>(0h0), uncommonBits_201) node _T_2005 = and(_T_2003, _T_2004) node _T_2006 = leq(uncommonBits_201, UInt<2>(0h3)) node _T_2007 = and(_T_2005, _T_2006) node _uncommonBits_T_202 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_202 = bits(_uncommonBits_T_202, 1, 0) node _T_2008 = shr(io.in.a.bits.source, 2) node _T_2009 = eq(_T_2008, UInt<7>(0h7c)) node _T_2010 = leq(UInt<1>(0h0), uncommonBits_202) node _T_2011 = and(_T_2009, _T_2010) node _T_2012 = leq(uncommonBits_202, UInt<2>(0h3)) node _T_2013 = and(_T_2011, _T_2012) node _uncommonBits_T_203 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_203 = bits(_uncommonBits_T_203, 1, 0) node _T_2014 = shr(io.in.a.bits.source, 2) node _T_2015 = eq(_T_2014, UInt<7>(0h7b)) node _T_2016 = leq(UInt<1>(0h0), uncommonBits_203) node _T_2017 = and(_T_2015, _T_2016) node _T_2018 = leq(uncommonBits_203, UInt<2>(0h3)) node _T_2019 = and(_T_2017, _T_2018) node _uncommonBits_T_204 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_204 = bits(_uncommonBits_T_204, 4, 0) node _T_2020 = shr(io.in.a.bits.source, 5) node _T_2021 = eq(_T_2020, UInt<4>(0hd)) node _T_2022 = leq(UInt<1>(0h0), uncommonBits_204) node _T_2023 = and(_T_2021, _T_2022) node _T_2024 = leq(uncommonBits_204, UInt<5>(0h1f)) node _T_2025 = and(_T_2023, _T_2024) node _uncommonBits_T_205 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_205 = bits(_uncommonBits_T_205, 4, 0) node _T_2026 = shr(io.in.a.bits.source, 5) node _T_2027 = eq(_T_2026, UInt<4>(0hc)) node _T_2028 = leq(UInt<1>(0h0), uncommonBits_205) node _T_2029 = and(_T_2027, _T_2028) node _T_2030 = leq(uncommonBits_205, UInt<5>(0h1f)) node _T_2031 = and(_T_2029, _T_2030) node _uncommonBits_T_206 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_206 = bits(_uncommonBits_T_206, 4, 0) node _T_2032 = shr(io.in.a.bits.source, 5) node _T_2033 = eq(_T_2032, UInt<4>(0hb)) node _T_2034 = leq(UInt<1>(0h0), uncommonBits_206) node _T_2035 = and(_T_2033, _T_2034) node _T_2036 = leq(uncommonBits_206, UInt<5>(0h1f)) node _T_2037 = and(_T_2035, _T_2036) node _uncommonBits_T_207 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_207 = bits(_uncommonBits_T_207, 4, 0) node _T_2038 = shr(io.in.a.bits.source, 5) node _T_2039 = eq(_T_2038, UInt<4>(0ha)) node _T_2040 = leq(UInt<1>(0h0), uncommonBits_207) node _T_2041 = and(_T_2039, _T_2040) node _T_2042 = leq(uncommonBits_207, UInt<5>(0h1f)) node _T_2043 = and(_T_2041, _T_2042) node _uncommonBits_T_208 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_208 = bits(_uncommonBits_T_208, 4, 0) node _T_2044 = shr(io.in.a.bits.source, 5) node _T_2045 = eq(_T_2044, UInt<4>(0h9)) node _T_2046 = leq(UInt<1>(0h0), uncommonBits_208) node _T_2047 = and(_T_2045, _T_2046) node _T_2048 = leq(uncommonBits_208, UInt<5>(0h1f)) node _T_2049 = and(_T_2047, _T_2048) node _uncommonBits_T_209 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_209 = bits(_uncommonBits_T_209, 4, 0) node _T_2050 = shr(io.in.a.bits.source, 5) node _T_2051 = eq(_T_2050, UInt<4>(0h8)) node _T_2052 = leq(UInt<1>(0h0), uncommonBits_209) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = leq(uncommonBits_209, UInt<5>(0h1f)) node _T_2055 = and(_T_2053, _T_2054) node _uncommonBits_T_210 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_210 = bits(_uncommonBits_T_210, 1, 0) node _T_2056 = shr(io.in.a.bits.source, 2) node _T_2057 = eq(_T_2056, UInt<7>(0h7a)) node _T_2058 = leq(UInt<1>(0h0), uncommonBits_210) node _T_2059 = and(_T_2057, _T_2058) node _T_2060 = leq(uncommonBits_210, UInt<2>(0h3)) node _T_2061 = and(_T_2059, _T_2060) node _uncommonBits_T_211 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_211 = bits(_uncommonBits_T_211, 1, 0) node _T_2062 = shr(io.in.a.bits.source, 2) node _T_2063 = eq(_T_2062, UInt<7>(0h79)) node _T_2064 = leq(UInt<1>(0h0), uncommonBits_211) node _T_2065 = and(_T_2063, _T_2064) node _T_2066 = leq(uncommonBits_211, UInt<2>(0h3)) node _T_2067 = and(_T_2065, _T_2066) node _uncommonBits_T_212 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_212 = bits(_uncommonBits_T_212, 4, 0) node _T_2068 = shr(io.in.a.bits.source, 5) node _T_2069 = eq(_T_2068, UInt<3>(0h7)) node _T_2070 = leq(UInt<1>(0h0), uncommonBits_212) node _T_2071 = and(_T_2069, _T_2070) node _T_2072 = leq(uncommonBits_212, UInt<5>(0h1f)) node _T_2073 = and(_T_2071, _T_2072) node _uncommonBits_T_213 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_213 = bits(_uncommonBits_T_213, 4, 0) node _T_2074 = shr(io.in.a.bits.source, 5) node _T_2075 = eq(_T_2074, UInt<3>(0h6)) node _T_2076 = leq(UInt<1>(0h0), uncommonBits_213) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = leq(uncommonBits_213, UInt<5>(0h1f)) node _T_2079 = and(_T_2077, _T_2078) node _uncommonBits_T_214 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_214 = bits(_uncommonBits_T_214, 4, 0) node _T_2080 = shr(io.in.a.bits.source, 5) node _T_2081 = eq(_T_2080, UInt<3>(0h5)) node _T_2082 = leq(UInt<1>(0h0), uncommonBits_214) node _T_2083 = and(_T_2081, _T_2082) node _T_2084 = leq(uncommonBits_214, UInt<5>(0h1f)) node _T_2085 = and(_T_2083, _T_2084) node _uncommonBits_T_215 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_215 = bits(_uncommonBits_T_215, 4, 0) node _T_2086 = shr(io.in.a.bits.source, 5) node _T_2087 = eq(_T_2086, UInt<3>(0h4)) node _T_2088 = leq(UInt<1>(0h0), uncommonBits_215) node _T_2089 = and(_T_2087, _T_2088) node _T_2090 = leq(uncommonBits_215, UInt<5>(0h1f)) node _T_2091 = and(_T_2089, _T_2090) node _uncommonBits_T_216 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_216 = bits(_uncommonBits_T_216, 4, 0) node _T_2092 = shr(io.in.a.bits.source, 5) node _T_2093 = eq(_T_2092, UInt<2>(0h3)) node _T_2094 = leq(UInt<1>(0h0), uncommonBits_216) node _T_2095 = and(_T_2093, _T_2094) node _T_2096 = leq(uncommonBits_216, UInt<5>(0h1f)) node _T_2097 = and(_T_2095, _T_2096) node _uncommonBits_T_217 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_217 = bits(_uncommonBits_T_217, 4, 0) node _T_2098 = shr(io.in.a.bits.source, 5) node _T_2099 = eq(_T_2098, UInt<2>(0h2)) node _T_2100 = leq(UInt<1>(0h0), uncommonBits_217) node _T_2101 = and(_T_2099, _T_2100) node _T_2102 = leq(uncommonBits_217, UInt<5>(0h1f)) node _T_2103 = and(_T_2101, _T_2102) node _uncommonBits_T_218 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_218 = bits(_uncommonBits_T_218, 4, 0) node _T_2104 = shr(io.in.a.bits.source, 5) node _T_2105 = eq(_T_2104, UInt<1>(0h1)) node _T_2106 = leq(UInt<1>(0h0), uncommonBits_218) node _T_2107 = and(_T_2105, _T_2106) node _T_2108 = leq(uncommonBits_218, UInt<5>(0h1f)) node _T_2109 = and(_T_2107, _T_2108) node _uncommonBits_T_219 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_219 = bits(_uncommonBits_T_219, 4, 0) node _T_2110 = shr(io.in.a.bits.source, 5) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) node _T_2112 = leq(UInt<1>(0h0), uncommonBits_219) node _T_2113 = and(_T_2111, _T_2112) node _T_2114 = leq(uncommonBits_219, UInt<5>(0h1f)) node _T_2115 = and(_T_2113, _T_2114) node _T_2116 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2117 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2118 = or(_T_1983, _T_1989) node _T_2119 = or(_T_2118, _T_1995) node _T_2120 = or(_T_2119, _T_2001) node _T_2121 = or(_T_2120, _T_2007) node _T_2122 = or(_T_2121, _T_2013) node _T_2123 = or(_T_2122, _T_2019) node _T_2124 = or(_T_2123, _T_2025) node _T_2125 = or(_T_2124, _T_2031) node _T_2126 = or(_T_2125, _T_2037) node _T_2127 = or(_T_2126, _T_2043) node _T_2128 = or(_T_2127, _T_2049) node _T_2129 = or(_T_2128, _T_2055) node _T_2130 = or(_T_2129, _T_2061) node _T_2131 = or(_T_2130, _T_2067) node _T_2132 = or(_T_2131, _T_2073) node _T_2133 = or(_T_2132, _T_2079) node _T_2134 = or(_T_2133, _T_2085) node _T_2135 = or(_T_2134, _T_2091) node _T_2136 = or(_T_2135, _T_2097) node _T_2137 = or(_T_2136, _T_2103) node _T_2138 = or(_T_2137, _T_2109) node _T_2139 = or(_T_2138, _T_2115) node _T_2140 = or(_T_2139, _T_2116) node _T_2141 = or(_T_2140, _T_2117) node _T_2142 = and(_T_1982, _T_2141) node _T_2143 = or(UInt<1>(0h0), _T_2142) node _T_2144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2145 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_2146 = and(_T_2144, _T_2145) node _T_2147 = or(UInt<1>(0h0), _T_2146) node _T_2148 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_2149 = cvt(_T_2148) node _T_2150 = and(_T_2149, asSInt(UInt<17>(0h10000))) node _T_2151 = asSInt(_T_2150) node _T_2152 = eq(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_2154 = cvt(_T_2153) node _T_2155 = and(_T_2154, asSInt(UInt<29>(0h10000000))) node _T_2156 = asSInt(_T_2155) node _T_2157 = eq(_T_2156, asSInt(UInt<1>(0h0))) node _T_2158 = or(_T_2152, _T_2157) node _T_2159 = and(_T_2147, _T_2158) node _T_2160 = or(UInt<1>(0h0), _T_2159) node _T_2161 = and(_T_2143, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_41 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(source_ok, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_2168 = asUInt(reset) node _T_2169 = eq(_T_2168, UInt<1>(0h0)) when _T_2169 : node _T_2170 = eq(is_aligned, UInt<1>(0h0)) when _T_2170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_2171 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_44 node _T_2175 = eq(io.in.a.bits.mask, mask) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_45 node _T_2179 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_2179 : node _T_2180 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2181 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_2182 = and(_T_2180, _T_2181) node _T_2183 = eq(io.in.a.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_220 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_220 = bits(_uncommonBits_T_220, 1, 0) node _T_2184 = shr(io.in.a.bits.source, 2) node _T_2185 = eq(_T_2184, UInt<7>(0h70)) node _T_2186 = leq(UInt<1>(0h0), uncommonBits_220) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = leq(uncommonBits_220, UInt<2>(0h3)) node _T_2189 = and(_T_2187, _T_2188) node _uncommonBits_T_221 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_221 = bits(_uncommonBits_T_221, 1, 0) node _T_2190 = shr(io.in.a.bits.source, 2) node _T_2191 = eq(_T_2190, UInt<7>(0h71)) node _T_2192 = leq(UInt<1>(0h0), uncommonBits_221) node _T_2193 = and(_T_2191, _T_2192) node _T_2194 = leq(uncommonBits_221, UInt<2>(0h3)) node _T_2195 = and(_T_2193, _T_2194) node _uncommonBits_T_222 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_222 = bits(_uncommonBits_T_222, 1, 0) node _T_2196 = shr(io.in.a.bits.source, 2) node _T_2197 = eq(_T_2196, UInt<7>(0h72)) node _T_2198 = leq(UInt<1>(0h0), uncommonBits_222) node _T_2199 = and(_T_2197, _T_2198) node _T_2200 = leq(uncommonBits_222, UInt<2>(0h3)) node _T_2201 = and(_T_2199, _T_2200) node _uncommonBits_T_223 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_223 = bits(_uncommonBits_T_223, 1, 0) node _T_2202 = shr(io.in.a.bits.source, 2) node _T_2203 = eq(_T_2202, UInt<7>(0h73)) node _T_2204 = leq(UInt<1>(0h0), uncommonBits_223) node _T_2205 = and(_T_2203, _T_2204) node _T_2206 = leq(uncommonBits_223, UInt<2>(0h3)) node _T_2207 = and(_T_2205, _T_2206) node _uncommonBits_T_224 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_224 = bits(_uncommonBits_T_224, 1, 0) node _T_2208 = shr(io.in.a.bits.source, 2) node _T_2209 = eq(_T_2208, UInt<7>(0h7c)) node _T_2210 = leq(UInt<1>(0h0), uncommonBits_224) node _T_2211 = and(_T_2209, _T_2210) node _T_2212 = leq(uncommonBits_224, UInt<2>(0h3)) node _T_2213 = and(_T_2211, _T_2212) node _uncommonBits_T_225 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_225 = bits(_uncommonBits_T_225, 1, 0) node _T_2214 = shr(io.in.a.bits.source, 2) node _T_2215 = eq(_T_2214, UInt<7>(0h7b)) node _T_2216 = leq(UInt<1>(0h0), uncommonBits_225) node _T_2217 = and(_T_2215, _T_2216) node _T_2218 = leq(uncommonBits_225, UInt<2>(0h3)) node _T_2219 = and(_T_2217, _T_2218) node _uncommonBits_T_226 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_226 = bits(_uncommonBits_T_226, 4, 0) node _T_2220 = shr(io.in.a.bits.source, 5) node _T_2221 = eq(_T_2220, UInt<4>(0hd)) node _T_2222 = leq(UInt<1>(0h0), uncommonBits_226) node _T_2223 = and(_T_2221, _T_2222) node _T_2224 = leq(uncommonBits_226, UInt<5>(0h1f)) node _T_2225 = and(_T_2223, _T_2224) node _uncommonBits_T_227 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_227 = bits(_uncommonBits_T_227, 4, 0) node _T_2226 = shr(io.in.a.bits.source, 5) node _T_2227 = eq(_T_2226, UInt<4>(0hc)) node _T_2228 = leq(UInt<1>(0h0), uncommonBits_227) node _T_2229 = and(_T_2227, _T_2228) node _T_2230 = leq(uncommonBits_227, UInt<5>(0h1f)) node _T_2231 = and(_T_2229, _T_2230) node _uncommonBits_T_228 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_228 = bits(_uncommonBits_T_228, 4, 0) node _T_2232 = shr(io.in.a.bits.source, 5) node _T_2233 = eq(_T_2232, UInt<4>(0hb)) node _T_2234 = leq(UInt<1>(0h0), uncommonBits_228) node _T_2235 = and(_T_2233, _T_2234) node _T_2236 = leq(uncommonBits_228, UInt<5>(0h1f)) node _T_2237 = and(_T_2235, _T_2236) node _uncommonBits_T_229 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_229 = bits(_uncommonBits_T_229, 4, 0) node _T_2238 = shr(io.in.a.bits.source, 5) node _T_2239 = eq(_T_2238, UInt<4>(0ha)) node _T_2240 = leq(UInt<1>(0h0), uncommonBits_229) node _T_2241 = and(_T_2239, _T_2240) node _T_2242 = leq(uncommonBits_229, UInt<5>(0h1f)) node _T_2243 = and(_T_2241, _T_2242) node _uncommonBits_T_230 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_230 = bits(_uncommonBits_T_230, 4, 0) node _T_2244 = shr(io.in.a.bits.source, 5) node _T_2245 = eq(_T_2244, UInt<4>(0h9)) node _T_2246 = leq(UInt<1>(0h0), uncommonBits_230) node _T_2247 = and(_T_2245, _T_2246) node _T_2248 = leq(uncommonBits_230, UInt<5>(0h1f)) node _T_2249 = and(_T_2247, _T_2248) node _uncommonBits_T_231 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_231 = bits(_uncommonBits_T_231, 4, 0) node _T_2250 = shr(io.in.a.bits.source, 5) node _T_2251 = eq(_T_2250, UInt<4>(0h8)) node _T_2252 = leq(UInt<1>(0h0), uncommonBits_231) node _T_2253 = and(_T_2251, _T_2252) node _T_2254 = leq(uncommonBits_231, UInt<5>(0h1f)) node _T_2255 = and(_T_2253, _T_2254) node _uncommonBits_T_232 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_232 = bits(_uncommonBits_T_232, 1, 0) node _T_2256 = shr(io.in.a.bits.source, 2) node _T_2257 = eq(_T_2256, UInt<7>(0h7a)) node _T_2258 = leq(UInt<1>(0h0), uncommonBits_232) node _T_2259 = and(_T_2257, _T_2258) node _T_2260 = leq(uncommonBits_232, UInt<2>(0h3)) node _T_2261 = and(_T_2259, _T_2260) node _uncommonBits_T_233 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_233 = bits(_uncommonBits_T_233, 1, 0) node _T_2262 = shr(io.in.a.bits.source, 2) node _T_2263 = eq(_T_2262, UInt<7>(0h79)) node _T_2264 = leq(UInt<1>(0h0), uncommonBits_233) node _T_2265 = and(_T_2263, _T_2264) node _T_2266 = leq(uncommonBits_233, UInt<2>(0h3)) node _T_2267 = and(_T_2265, _T_2266) node _uncommonBits_T_234 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_234 = bits(_uncommonBits_T_234, 4, 0) node _T_2268 = shr(io.in.a.bits.source, 5) node _T_2269 = eq(_T_2268, UInt<3>(0h7)) node _T_2270 = leq(UInt<1>(0h0), uncommonBits_234) node _T_2271 = and(_T_2269, _T_2270) node _T_2272 = leq(uncommonBits_234, UInt<5>(0h1f)) node _T_2273 = and(_T_2271, _T_2272) node _uncommonBits_T_235 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_235 = bits(_uncommonBits_T_235, 4, 0) node _T_2274 = shr(io.in.a.bits.source, 5) node _T_2275 = eq(_T_2274, UInt<3>(0h6)) node _T_2276 = leq(UInt<1>(0h0), uncommonBits_235) node _T_2277 = and(_T_2275, _T_2276) node _T_2278 = leq(uncommonBits_235, UInt<5>(0h1f)) node _T_2279 = and(_T_2277, _T_2278) node _uncommonBits_T_236 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_236 = bits(_uncommonBits_T_236, 4, 0) node _T_2280 = shr(io.in.a.bits.source, 5) node _T_2281 = eq(_T_2280, UInt<3>(0h5)) node _T_2282 = leq(UInt<1>(0h0), uncommonBits_236) node _T_2283 = and(_T_2281, _T_2282) node _T_2284 = leq(uncommonBits_236, UInt<5>(0h1f)) node _T_2285 = and(_T_2283, _T_2284) node _uncommonBits_T_237 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_237 = bits(_uncommonBits_T_237, 4, 0) node _T_2286 = shr(io.in.a.bits.source, 5) node _T_2287 = eq(_T_2286, UInt<3>(0h4)) node _T_2288 = leq(UInt<1>(0h0), uncommonBits_237) node _T_2289 = and(_T_2287, _T_2288) node _T_2290 = leq(uncommonBits_237, UInt<5>(0h1f)) node _T_2291 = and(_T_2289, _T_2290) node _uncommonBits_T_238 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_238 = bits(_uncommonBits_T_238, 4, 0) node _T_2292 = shr(io.in.a.bits.source, 5) node _T_2293 = eq(_T_2292, UInt<2>(0h3)) node _T_2294 = leq(UInt<1>(0h0), uncommonBits_238) node _T_2295 = and(_T_2293, _T_2294) node _T_2296 = leq(uncommonBits_238, UInt<5>(0h1f)) node _T_2297 = and(_T_2295, _T_2296) node _uncommonBits_T_239 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_239 = bits(_uncommonBits_T_239, 4, 0) node _T_2298 = shr(io.in.a.bits.source, 5) node _T_2299 = eq(_T_2298, UInt<2>(0h2)) node _T_2300 = leq(UInt<1>(0h0), uncommonBits_239) node _T_2301 = and(_T_2299, _T_2300) node _T_2302 = leq(uncommonBits_239, UInt<5>(0h1f)) node _T_2303 = and(_T_2301, _T_2302) node _uncommonBits_T_240 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_240 = bits(_uncommonBits_T_240, 4, 0) node _T_2304 = shr(io.in.a.bits.source, 5) node _T_2305 = eq(_T_2304, UInt<1>(0h1)) node _T_2306 = leq(UInt<1>(0h0), uncommonBits_240) node _T_2307 = and(_T_2305, _T_2306) node _T_2308 = leq(uncommonBits_240, UInt<5>(0h1f)) node _T_2309 = and(_T_2307, _T_2308) node _uncommonBits_T_241 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_241 = bits(_uncommonBits_T_241, 4, 0) node _T_2310 = shr(io.in.a.bits.source, 5) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) node _T_2312 = leq(UInt<1>(0h0), uncommonBits_241) node _T_2313 = and(_T_2311, _T_2312) node _T_2314 = leq(uncommonBits_241, UInt<5>(0h1f)) node _T_2315 = and(_T_2313, _T_2314) node _T_2316 = eq(io.in.a.bits.source, UInt<9>(0h1e0)) node _T_2317 = eq(io.in.a.bits.source, UInt<9>(0h1e2)) node _T_2318 = or(_T_2183, _T_2189) node _T_2319 = or(_T_2318, _T_2195) node _T_2320 = or(_T_2319, _T_2201) node _T_2321 = or(_T_2320, _T_2207) node _T_2322 = or(_T_2321, _T_2213) node _T_2323 = or(_T_2322, _T_2219) node _T_2324 = or(_T_2323, _T_2225) node _T_2325 = or(_T_2324, _T_2231) node _T_2326 = or(_T_2325, _T_2237) node _T_2327 = or(_T_2326, _T_2243) node _T_2328 = or(_T_2327, _T_2249) node _T_2329 = or(_T_2328, _T_2255) node _T_2330 = or(_T_2329, _T_2261) node _T_2331 = or(_T_2330, _T_2267) node _T_2332 = or(_T_2331, _T_2273) node _T_2333 = or(_T_2332, _T_2279) node _T_2334 = or(_T_2333, _T_2285) node _T_2335 = or(_T_2334, _T_2291) node _T_2336 = or(_T_2335, _T_2297) node _T_2337 = or(_T_2336, _T_2303) node _T_2338 = or(_T_2337, _T_2309) node _T_2339 = or(_T_2338, _T_2315) node _T_2340 = or(_T_2339, _T_2316) node _T_2341 = or(_T_2340, _T_2317) node _T_2342 = and(_T_2182, _T_2341) node _T_2343 = or(UInt<1>(0h0), _T_2342) node _T_2344 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_2345 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_2346 = and(_T_2344, _T_2345) node _T_2347 = or(UInt<1>(0h0), _T_2346) node _T_2348 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_2349 = cvt(_T_2348) node _T_2350 = and(_T_2349, asSInt(UInt<17>(0h10000))) node _T_2351 = asSInt(_T_2350) node _T_2352 = eq(_T_2351, asSInt(UInt<1>(0h0))) node _T_2353 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_2354 = cvt(_T_2353) node _T_2355 = and(_T_2354, asSInt(UInt<29>(0h10000000))) node _T_2356 = asSInt(_T_2355) node _T_2357 = eq(_T_2356, asSInt(UInt<1>(0h0))) node _T_2358 = or(_T_2352, _T_2357) node _T_2359 = and(_T_2347, _T_2358) node _T_2360 = or(UInt<1>(0h0), _T_2359) node _T_2361 = and(_T_2343, _T_2360) node _T_2362 = asUInt(reset) node _T_2363 = eq(_T_2362, UInt<1>(0h0)) when _T_2363 : node _T_2364 = eq(_T_2361, UInt<1>(0h0)) when _T_2364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_2361, UInt<1>(0h1), "") : assert_46 node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(source_ok, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_2368 = asUInt(reset) node _T_2369 = eq(_T_2368, UInt<1>(0h0)) when _T_2369 : node _T_2370 = eq(is_aligned, UInt<1>(0h0)) when _T_2370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_2371 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_2372 = asUInt(reset) node _T_2373 = eq(_T_2372, UInt<1>(0h0)) when _T_2373 : node _T_2374 = eq(_T_2371, UInt<1>(0h0)) when _T_2374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_2371, UInt<1>(0h1), "") : assert_49 node _T_2375 = eq(io.in.a.bits.mask, mask) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_50 node _T_2379 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_2383 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_52 node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 1, 0) node _source_ok_T_159 = shr(io.in.d.bits.source, 2) node _source_ok_T_160 = eq(_source_ok_T_159, UInt<7>(0h70)) node _source_ok_T_161 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_162 = and(_source_ok_T_160, _source_ok_T_161) node _source_ok_T_163 = leq(source_ok_uncommonBits_22, UInt<2>(0h3)) node _source_ok_T_164 = and(_source_ok_T_162, _source_ok_T_163) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 1, 0) node _source_ok_T_165 = shr(io.in.d.bits.source, 2) node _source_ok_T_166 = eq(_source_ok_T_165, UInt<7>(0h71)) node _source_ok_T_167 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_168 = and(_source_ok_T_166, _source_ok_T_167) node _source_ok_T_169 = leq(source_ok_uncommonBits_23, UInt<2>(0h3)) node _source_ok_T_170 = and(_source_ok_T_168, _source_ok_T_169) node _source_ok_uncommonBits_T_24 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_24 = bits(_source_ok_uncommonBits_T_24, 1, 0) node _source_ok_T_171 = shr(io.in.d.bits.source, 2) node _source_ok_T_172 = eq(_source_ok_T_171, UInt<7>(0h72)) node _source_ok_T_173 = leq(UInt<1>(0h0), source_ok_uncommonBits_24) node _source_ok_T_174 = and(_source_ok_T_172, _source_ok_T_173) node _source_ok_T_175 = leq(source_ok_uncommonBits_24, UInt<2>(0h3)) node _source_ok_T_176 = and(_source_ok_T_174, _source_ok_T_175) node _source_ok_uncommonBits_T_25 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_25 = bits(_source_ok_uncommonBits_T_25, 1, 0) node _source_ok_T_177 = shr(io.in.d.bits.source, 2) node _source_ok_T_178 = eq(_source_ok_T_177, UInt<7>(0h73)) node _source_ok_T_179 = leq(UInt<1>(0h0), source_ok_uncommonBits_25) node _source_ok_T_180 = and(_source_ok_T_178, _source_ok_T_179) node _source_ok_T_181 = leq(source_ok_uncommonBits_25, UInt<2>(0h3)) node _source_ok_T_182 = and(_source_ok_T_180, _source_ok_T_181) node _source_ok_uncommonBits_T_26 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_26 = bits(_source_ok_uncommonBits_T_26, 1, 0) node _source_ok_T_183 = shr(io.in.d.bits.source, 2) node _source_ok_T_184 = eq(_source_ok_T_183, UInt<7>(0h7c)) node _source_ok_T_185 = leq(UInt<1>(0h0), source_ok_uncommonBits_26) node _source_ok_T_186 = and(_source_ok_T_184, _source_ok_T_185) node _source_ok_T_187 = leq(source_ok_uncommonBits_26, UInt<2>(0h3)) node _source_ok_T_188 = and(_source_ok_T_186, _source_ok_T_187) node _source_ok_uncommonBits_T_27 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_27 = bits(_source_ok_uncommonBits_T_27, 1, 0) node _source_ok_T_189 = shr(io.in.d.bits.source, 2) node _source_ok_T_190 = eq(_source_ok_T_189, UInt<7>(0h7b)) node _source_ok_T_191 = leq(UInt<1>(0h0), source_ok_uncommonBits_27) node _source_ok_T_192 = and(_source_ok_T_190, _source_ok_T_191) node _source_ok_T_193 = leq(source_ok_uncommonBits_27, UInt<2>(0h3)) node _source_ok_T_194 = and(_source_ok_T_192, _source_ok_T_193) node _source_ok_uncommonBits_T_28 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_28 = bits(_source_ok_uncommonBits_T_28, 4, 0) node _source_ok_T_195 = shr(io.in.d.bits.source, 5) node _source_ok_T_196 = eq(_source_ok_T_195, UInt<4>(0hd)) node _source_ok_T_197 = leq(UInt<1>(0h0), source_ok_uncommonBits_28) node _source_ok_T_198 = and(_source_ok_T_196, _source_ok_T_197) node _source_ok_T_199 = leq(source_ok_uncommonBits_28, UInt<5>(0h1f)) node _source_ok_T_200 = and(_source_ok_T_198, _source_ok_T_199) node _source_ok_uncommonBits_T_29 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_29 = bits(_source_ok_uncommonBits_T_29, 4, 0) node _source_ok_T_201 = shr(io.in.d.bits.source, 5) node _source_ok_T_202 = eq(_source_ok_T_201, UInt<4>(0hc)) node _source_ok_T_203 = leq(UInt<1>(0h0), source_ok_uncommonBits_29) node _source_ok_T_204 = and(_source_ok_T_202, _source_ok_T_203) node _source_ok_T_205 = leq(source_ok_uncommonBits_29, UInt<5>(0h1f)) node _source_ok_T_206 = and(_source_ok_T_204, _source_ok_T_205) node _source_ok_uncommonBits_T_30 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_30 = bits(_source_ok_uncommonBits_T_30, 4, 0) node _source_ok_T_207 = shr(io.in.d.bits.source, 5) node _source_ok_T_208 = eq(_source_ok_T_207, UInt<4>(0hb)) node _source_ok_T_209 = leq(UInt<1>(0h0), source_ok_uncommonBits_30) node _source_ok_T_210 = and(_source_ok_T_208, _source_ok_T_209) node _source_ok_T_211 = leq(source_ok_uncommonBits_30, UInt<5>(0h1f)) node _source_ok_T_212 = and(_source_ok_T_210, _source_ok_T_211) node _source_ok_uncommonBits_T_31 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_31 = bits(_source_ok_uncommonBits_T_31, 4, 0) node _source_ok_T_213 = shr(io.in.d.bits.source, 5) node _source_ok_T_214 = eq(_source_ok_T_213, UInt<4>(0ha)) node _source_ok_T_215 = leq(UInt<1>(0h0), source_ok_uncommonBits_31) node _source_ok_T_216 = and(_source_ok_T_214, _source_ok_T_215) node _source_ok_T_217 = leq(source_ok_uncommonBits_31, UInt<5>(0h1f)) node _source_ok_T_218 = and(_source_ok_T_216, _source_ok_T_217) node _source_ok_uncommonBits_T_32 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_32 = bits(_source_ok_uncommonBits_T_32, 4, 0) node _source_ok_T_219 = shr(io.in.d.bits.source, 5) node _source_ok_T_220 = eq(_source_ok_T_219, UInt<4>(0h9)) node _source_ok_T_221 = leq(UInt<1>(0h0), source_ok_uncommonBits_32) node _source_ok_T_222 = and(_source_ok_T_220, _source_ok_T_221) node _source_ok_T_223 = leq(source_ok_uncommonBits_32, UInt<5>(0h1f)) node _source_ok_T_224 = and(_source_ok_T_222, _source_ok_T_223) node _source_ok_uncommonBits_T_33 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_33 = bits(_source_ok_uncommonBits_T_33, 4, 0) node _source_ok_T_225 = shr(io.in.d.bits.source, 5) node _source_ok_T_226 = eq(_source_ok_T_225, UInt<4>(0h8)) node _source_ok_T_227 = leq(UInt<1>(0h0), source_ok_uncommonBits_33) node _source_ok_T_228 = and(_source_ok_T_226, _source_ok_T_227) node _source_ok_T_229 = leq(source_ok_uncommonBits_33, UInt<5>(0h1f)) node _source_ok_T_230 = and(_source_ok_T_228, _source_ok_T_229) node _source_ok_uncommonBits_T_34 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_34 = bits(_source_ok_uncommonBits_T_34, 1, 0) node _source_ok_T_231 = shr(io.in.d.bits.source, 2) node _source_ok_T_232 = eq(_source_ok_T_231, UInt<7>(0h7a)) node _source_ok_T_233 = leq(UInt<1>(0h0), source_ok_uncommonBits_34) node _source_ok_T_234 = and(_source_ok_T_232, _source_ok_T_233) node _source_ok_T_235 = leq(source_ok_uncommonBits_34, UInt<2>(0h3)) node _source_ok_T_236 = and(_source_ok_T_234, _source_ok_T_235) node _source_ok_uncommonBits_T_35 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_35 = bits(_source_ok_uncommonBits_T_35, 1, 0) node _source_ok_T_237 = shr(io.in.d.bits.source, 2) node _source_ok_T_238 = eq(_source_ok_T_237, UInt<7>(0h79)) node _source_ok_T_239 = leq(UInt<1>(0h0), source_ok_uncommonBits_35) node _source_ok_T_240 = and(_source_ok_T_238, _source_ok_T_239) node _source_ok_T_241 = leq(source_ok_uncommonBits_35, UInt<2>(0h3)) node _source_ok_T_242 = and(_source_ok_T_240, _source_ok_T_241) node _source_ok_uncommonBits_T_36 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_36 = bits(_source_ok_uncommonBits_T_36, 4, 0) node _source_ok_T_243 = shr(io.in.d.bits.source, 5) node _source_ok_T_244 = eq(_source_ok_T_243, UInt<3>(0h7)) node _source_ok_T_245 = leq(UInt<1>(0h0), source_ok_uncommonBits_36) node _source_ok_T_246 = and(_source_ok_T_244, _source_ok_T_245) node _source_ok_T_247 = leq(source_ok_uncommonBits_36, UInt<5>(0h1f)) node _source_ok_T_248 = and(_source_ok_T_246, _source_ok_T_247) node _source_ok_uncommonBits_T_37 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_37 = bits(_source_ok_uncommonBits_T_37, 4, 0) node _source_ok_T_249 = shr(io.in.d.bits.source, 5) node _source_ok_T_250 = eq(_source_ok_T_249, UInt<3>(0h6)) node _source_ok_T_251 = leq(UInt<1>(0h0), source_ok_uncommonBits_37) node _source_ok_T_252 = and(_source_ok_T_250, _source_ok_T_251) node _source_ok_T_253 = leq(source_ok_uncommonBits_37, UInt<5>(0h1f)) node _source_ok_T_254 = and(_source_ok_T_252, _source_ok_T_253) node _source_ok_uncommonBits_T_38 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_38 = bits(_source_ok_uncommonBits_T_38, 4, 0) node _source_ok_T_255 = shr(io.in.d.bits.source, 5) node _source_ok_T_256 = eq(_source_ok_T_255, UInt<3>(0h5)) node _source_ok_T_257 = leq(UInt<1>(0h0), source_ok_uncommonBits_38) node _source_ok_T_258 = and(_source_ok_T_256, _source_ok_T_257) node _source_ok_T_259 = leq(source_ok_uncommonBits_38, UInt<5>(0h1f)) node _source_ok_T_260 = and(_source_ok_T_258, _source_ok_T_259) node _source_ok_uncommonBits_T_39 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_39 = bits(_source_ok_uncommonBits_T_39, 4, 0) node _source_ok_T_261 = shr(io.in.d.bits.source, 5) node _source_ok_T_262 = eq(_source_ok_T_261, UInt<3>(0h4)) node _source_ok_T_263 = leq(UInt<1>(0h0), source_ok_uncommonBits_39) node _source_ok_T_264 = and(_source_ok_T_262, _source_ok_T_263) node _source_ok_T_265 = leq(source_ok_uncommonBits_39, UInt<5>(0h1f)) node _source_ok_T_266 = and(_source_ok_T_264, _source_ok_T_265) node _source_ok_uncommonBits_T_40 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_40 = bits(_source_ok_uncommonBits_T_40, 4, 0) node _source_ok_T_267 = shr(io.in.d.bits.source, 5) node _source_ok_T_268 = eq(_source_ok_T_267, UInt<2>(0h3)) node _source_ok_T_269 = leq(UInt<1>(0h0), source_ok_uncommonBits_40) node _source_ok_T_270 = and(_source_ok_T_268, _source_ok_T_269) node _source_ok_T_271 = leq(source_ok_uncommonBits_40, UInt<5>(0h1f)) node _source_ok_T_272 = and(_source_ok_T_270, _source_ok_T_271) node _source_ok_uncommonBits_T_41 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_41 = bits(_source_ok_uncommonBits_T_41, 4, 0) node _source_ok_T_273 = shr(io.in.d.bits.source, 5) node _source_ok_T_274 = eq(_source_ok_T_273, UInt<2>(0h2)) node _source_ok_T_275 = leq(UInt<1>(0h0), source_ok_uncommonBits_41) node _source_ok_T_276 = and(_source_ok_T_274, _source_ok_T_275) node _source_ok_T_277 = leq(source_ok_uncommonBits_41, UInt<5>(0h1f)) node _source_ok_T_278 = and(_source_ok_T_276, _source_ok_T_277) node _source_ok_uncommonBits_T_42 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_42 = bits(_source_ok_uncommonBits_T_42, 4, 0) node _source_ok_T_279 = shr(io.in.d.bits.source, 5) node _source_ok_T_280 = eq(_source_ok_T_279, UInt<1>(0h1)) node _source_ok_T_281 = leq(UInt<1>(0h0), source_ok_uncommonBits_42) node _source_ok_T_282 = and(_source_ok_T_280, _source_ok_T_281) node _source_ok_T_283 = leq(source_ok_uncommonBits_42, UInt<5>(0h1f)) node _source_ok_T_284 = and(_source_ok_T_282, _source_ok_T_283) node _source_ok_uncommonBits_T_43 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_43 = bits(_source_ok_uncommonBits_T_43, 4, 0) node _source_ok_T_285 = shr(io.in.d.bits.source, 5) node _source_ok_T_286 = eq(_source_ok_T_285, UInt<1>(0h0)) node _source_ok_T_287 = leq(UInt<1>(0h0), source_ok_uncommonBits_43) node _source_ok_T_288 = and(_source_ok_T_286, _source_ok_T_287) node _source_ok_T_289 = leq(source_ok_uncommonBits_43, UInt<5>(0h1f)) node _source_ok_T_290 = and(_source_ok_T_288, _source_ok_T_289) node _source_ok_T_291 = eq(io.in.d.bits.source, UInt<9>(0h1e0)) node _source_ok_T_292 = eq(io.in.d.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE_1 : UInt<1>[25] connect _source_ok_WIRE_1[0], _source_ok_T_158 connect _source_ok_WIRE_1[1], _source_ok_T_164 connect _source_ok_WIRE_1[2], _source_ok_T_170 connect _source_ok_WIRE_1[3], _source_ok_T_176 connect _source_ok_WIRE_1[4], _source_ok_T_182 connect _source_ok_WIRE_1[5], _source_ok_T_188 connect _source_ok_WIRE_1[6], _source_ok_T_194 connect _source_ok_WIRE_1[7], _source_ok_T_200 connect _source_ok_WIRE_1[8], _source_ok_T_206 connect _source_ok_WIRE_1[9], _source_ok_T_212 connect _source_ok_WIRE_1[10], _source_ok_T_218 connect _source_ok_WIRE_1[11], _source_ok_T_224 connect _source_ok_WIRE_1[12], _source_ok_T_230 connect _source_ok_WIRE_1[13], _source_ok_T_236 connect _source_ok_WIRE_1[14], _source_ok_T_242 connect _source_ok_WIRE_1[15], _source_ok_T_248 connect _source_ok_WIRE_1[16], _source_ok_T_254 connect _source_ok_WIRE_1[17], _source_ok_T_260 connect _source_ok_WIRE_1[18], _source_ok_T_266 connect _source_ok_WIRE_1[19], _source_ok_T_272 connect _source_ok_WIRE_1[20], _source_ok_T_278 connect _source_ok_WIRE_1[21], _source_ok_T_284 connect _source_ok_WIRE_1[22], _source_ok_T_290 connect _source_ok_WIRE_1[23], _source_ok_T_291 connect _source_ok_WIRE_1[24], _source_ok_T_292 node _source_ok_T_293 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_294 = or(_source_ok_T_293, _source_ok_WIRE_1[2]) node _source_ok_T_295 = or(_source_ok_T_294, _source_ok_WIRE_1[3]) node _source_ok_T_296 = or(_source_ok_T_295, _source_ok_WIRE_1[4]) node _source_ok_T_297 = or(_source_ok_T_296, _source_ok_WIRE_1[5]) node _source_ok_T_298 = or(_source_ok_T_297, _source_ok_WIRE_1[6]) node _source_ok_T_299 = or(_source_ok_T_298, _source_ok_WIRE_1[7]) node _source_ok_T_300 = or(_source_ok_T_299, _source_ok_WIRE_1[8]) node _source_ok_T_301 = or(_source_ok_T_300, _source_ok_WIRE_1[9]) node _source_ok_T_302 = or(_source_ok_T_301, _source_ok_WIRE_1[10]) node _source_ok_T_303 = or(_source_ok_T_302, _source_ok_WIRE_1[11]) node _source_ok_T_304 = or(_source_ok_T_303, _source_ok_WIRE_1[12]) node _source_ok_T_305 = or(_source_ok_T_304, _source_ok_WIRE_1[13]) node _source_ok_T_306 = or(_source_ok_T_305, _source_ok_WIRE_1[14]) node _source_ok_T_307 = or(_source_ok_T_306, _source_ok_WIRE_1[15]) node _source_ok_T_308 = or(_source_ok_T_307, _source_ok_WIRE_1[16]) node _source_ok_T_309 = or(_source_ok_T_308, _source_ok_WIRE_1[17]) node _source_ok_T_310 = or(_source_ok_T_309, _source_ok_WIRE_1[18]) node _source_ok_T_311 = or(_source_ok_T_310, _source_ok_WIRE_1[19]) node _source_ok_T_312 = or(_source_ok_T_311, _source_ok_WIRE_1[20]) node _source_ok_T_313 = or(_source_ok_T_312, _source_ok_WIRE_1[21]) node _source_ok_T_314 = or(_source_ok_T_313, _source_ok_WIRE_1[22]) node _source_ok_T_315 = or(_source_ok_T_314, _source_ok_WIRE_1[23]) node source_ok_1 = or(_source_ok_T_315, _source_ok_WIRE_1[24]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_2387 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_2387 : node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(source_ok_1, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_2391 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_54 node _T_2395 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2396 = asUInt(reset) node _T_2397 = eq(_T_2396, UInt<1>(0h0)) when _T_2397 : node _T_2398 = eq(_T_2395, UInt<1>(0h0)) when _T_2398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_2395, UInt<1>(0h1), "") : assert_55 node _T_2399 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_56 node _T_2403 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_57 node _T_2407 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_2407 : node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(source_ok_1, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_2411 = asUInt(reset) node _T_2412 = eq(_T_2411, UInt<1>(0h0)) when _T_2412 : node _T_2413 = eq(sink_ok, UInt<1>(0h0)) when _T_2413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_2414 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2415 = asUInt(reset) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) when _T_2416 : node _T_2417 = eq(_T_2414, UInt<1>(0h0)) when _T_2417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_2414, UInt<1>(0h1), "") : assert_60 node _T_2418 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2419 = asUInt(reset) node _T_2420 = eq(_T_2419, UInt<1>(0h0)) when _T_2420 : node _T_2421 = eq(_T_2418, UInt<1>(0h0)) when _T_2421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_2418, UInt<1>(0h1), "") : assert_61 node _T_2422 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2423 = asUInt(reset) node _T_2424 = eq(_T_2423, UInt<1>(0h0)) when _T_2424 : node _T_2425 = eq(_T_2422, UInt<1>(0h0)) when _T_2425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_2422, UInt<1>(0h1), "") : assert_62 node _T_2426 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(_T_2426, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_2426, UInt<1>(0h1), "") : assert_63 node _T_2430 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2431 = or(UInt<1>(0h1), _T_2430) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_64 node _T_2435 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_2435 : node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(source_ok_1, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_2439 = asUInt(reset) node _T_2440 = eq(_T_2439, UInt<1>(0h0)) when _T_2440 : node _T_2441 = eq(sink_ok, UInt<1>(0h0)) when _T_2441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_2442 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_67 node _T_2446 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_68 node _T_2450 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_2451 = asUInt(reset) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) when _T_2452 : node _T_2453 = eq(_T_2450, UInt<1>(0h0)) when _T_2453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_2450, UInt<1>(0h1), "") : assert_69 node _T_2454 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2455 = or(_T_2454, io.in.d.bits.corrupt) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_70 node _T_2459 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2460 = or(UInt<1>(0h1), _T_2459) node _T_2461 = asUInt(reset) node _T_2462 = eq(_T_2461, UInt<1>(0h0)) when _T_2462 : node _T_2463 = eq(_T_2460, UInt<1>(0h0)) when _T_2463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_2460, UInt<1>(0h1), "") : assert_71 node _T_2464 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_2464 : node _T_2465 = asUInt(reset) node _T_2466 = eq(_T_2465, UInt<1>(0h0)) when _T_2466 : node _T_2467 = eq(source_ok_1, UInt<1>(0h0)) when _T_2467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_2468 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_73 node _T_2472 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_74 node _T_2476 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2477 = or(UInt<1>(0h1), _T_2476) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_75 node _T_2481 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_2481 : node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(source_ok_1, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_2485 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2486 = asUInt(reset) node _T_2487 = eq(_T_2486, UInt<1>(0h0)) when _T_2487 : node _T_2488 = eq(_T_2485, UInt<1>(0h0)) when _T_2488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_2485, UInt<1>(0h1), "") : assert_77 node _T_2489 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2490 = or(_T_2489, io.in.d.bits.corrupt) node _T_2491 = asUInt(reset) node _T_2492 = eq(_T_2491, UInt<1>(0h0)) when _T_2492 : node _T_2493 = eq(_T_2490, UInt<1>(0h0)) when _T_2493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_2490, UInt<1>(0h1), "") : assert_78 node _T_2494 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2495 = or(UInt<1>(0h1), _T_2494) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_79 node _T_2499 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_2499 : node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(source_ok_1, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_2503 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_2504 = asUInt(reset) node _T_2505 = eq(_T_2504, UInt<1>(0h0)) when _T_2505 : node _T_2506 = eq(_T_2503, UInt<1>(0h0)) when _T_2506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_2503, UInt<1>(0h1), "") : assert_81 node _T_2507 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_2508 = asUInt(reset) node _T_2509 = eq(_T_2508, UInt<1>(0h0)) when _T_2509 : node _T_2510 = eq(_T_2507, UInt<1>(0h0)) when _T_2510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_2507, UInt<1>(0h1), "") : assert_82 node _T_2511 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2512 = or(UInt<1>(0h1), _T_2511) node _T_2513 = asUInt(reset) node _T_2514 = eq(_T_2513, UInt<1>(0h0)) when _T_2514 : node _T_2515 = eq(_T_2512, UInt<1>(0h0)) when _T_2515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2512, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_2516 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_2517 = asUInt(reset) node _T_2518 = eq(_T_2517, UInt<1>(0h0)) when _T_2518 : node _T_2519 = eq(_T_2516, UInt<1>(0h0)) when _T_2519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2516, UInt<1>(0h1), "") : assert_84 node _T_2520 = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) node _T_2522 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2523 = cvt(_T_2522) node _T_2524 = and(_T_2523, asSInt(UInt<1>(0h0))) node _T_2525 = asSInt(_T_2524) node _T_2526 = eq(_T_2525, asSInt(UInt<1>(0h0))) node _T_2527 = or(_T_2521, _T_2526) node _uncommonBits_T_242 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_242 = bits(_uncommonBits_T_242, 1, 0) node _T_2528 = shr(io.in.b.bits.source, 2) node _T_2529 = eq(_T_2528, UInt<7>(0h70)) node _T_2530 = leq(UInt<1>(0h0), uncommonBits_242) node _T_2531 = and(_T_2529, _T_2530) node _T_2532 = leq(uncommonBits_242, UInt<2>(0h3)) node _T_2533 = and(_T_2531, _T_2532) node _T_2534 = eq(_T_2533, UInt<1>(0h0)) node _T_2535 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2536 = cvt(_T_2535) node _T_2537 = and(_T_2536, asSInt(UInt<1>(0h0))) node _T_2538 = asSInt(_T_2537) node _T_2539 = eq(_T_2538, asSInt(UInt<1>(0h0))) node _T_2540 = or(_T_2534, _T_2539) node _uncommonBits_T_243 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_243 = bits(_uncommonBits_T_243, 1, 0) node _T_2541 = shr(io.in.b.bits.source, 2) node _T_2542 = eq(_T_2541, UInt<7>(0h71)) node _T_2543 = leq(UInt<1>(0h0), uncommonBits_243) node _T_2544 = and(_T_2542, _T_2543) node _T_2545 = leq(uncommonBits_243, UInt<2>(0h3)) node _T_2546 = and(_T_2544, _T_2545) node _T_2547 = eq(_T_2546, UInt<1>(0h0)) node _T_2548 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2549 = cvt(_T_2548) node _T_2550 = and(_T_2549, asSInt(UInt<1>(0h0))) node _T_2551 = asSInt(_T_2550) node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0))) node _T_2553 = or(_T_2547, _T_2552) node _uncommonBits_T_244 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_244 = bits(_uncommonBits_T_244, 1, 0) node _T_2554 = shr(io.in.b.bits.source, 2) node _T_2555 = eq(_T_2554, UInt<7>(0h72)) node _T_2556 = leq(UInt<1>(0h0), uncommonBits_244) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = leq(uncommonBits_244, UInt<2>(0h3)) node _T_2559 = and(_T_2557, _T_2558) node _T_2560 = eq(_T_2559, UInt<1>(0h0)) node _T_2561 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2562 = cvt(_T_2561) node _T_2563 = and(_T_2562, asSInt(UInt<1>(0h0))) node _T_2564 = asSInt(_T_2563) node _T_2565 = eq(_T_2564, asSInt(UInt<1>(0h0))) node _T_2566 = or(_T_2560, _T_2565) node _uncommonBits_T_245 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_245 = bits(_uncommonBits_T_245, 1, 0) node _T_2567 = shr(io.in.b.bits.source, 2) node _T_2568 = eq(_T_2567, UInt<7>(0h73)) node _T_2569 = leq(UInt<1>(0h0), uncommonBits_245) node _T_2570 = and(_T_2568, _T_2569) node _T_2571 = leq(uncommonBits_245, UInt<2>(0h3)) node _T_2572 = and(_T_2570, _T_2571) node _T_2573 = eq(_T_2572, UInt<1>(0h0)) node _T_2574 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2575 = cvt(_T_2574) node _T_2576 = and(_T_2575, asSInt(UInt<1>(0h0))) node _T_2577 = asSInt(_T_2576) node _T_2578 = eq(_T_2577, asSInt(UInt<1>(0h0))) node _T_2579 = or(_T_2573, _T_2578) node _uncommonBits_T_246 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_246 = bits(_uncommonBits_T_246, 1, 0) node _T_2580 = shr(io.in.b.bits.source, 2) node _T_2581 = eq(_T_2580, UInt<7>(0h7c)) node _T_2582 = leq(UInt<1>(0h0), uncommonBits_246) node _T_2583 = and(_T_2581, _T_2582) node _T_2584 = leq(uncommonBits_246, UInt<2>(0h3)) node _T_2585 = and(_T_2583, _T_2584) node _T_2586 = eq(_T_2585, UInt<1>(0h0)) node _T_2587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2588 = cvt(_T_2587) node _T_2589 = and(_T_2588, asSInt(UInt<1>(0h0))) node _T_2590 = asSInt(_T_2589) node _T_2591 = eq(_T_2590, asSInt(UInt<1>(0h0))) node _T_2592 = or(_T_2586, _T_2591) node _uncommonBits_T_247 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_247 = bits(_uncommonBits_T_247, 1, 0) node _T_2593 = shr(io.in.b.bits.source, 2) node _T_2594 = eq(_T_2593, UInt<7>(0h7b)) node _T_2595 = leq(UInt<1>(0h0), uncommonBits_247) node _T_2596 = and(_T_2594, _T_2595) node _T_2597 = leq(uncommonBits_247, UInt<2>(0h3)) node _T_2598 = and(_T_2596, _T_2597) node _T_2599 = eq(_T_2598, UInt<1>(0h0)) node _T_2600 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2601 = cvt(_T_2600) node _T_2602 = and(_T_2601, asSInt(UInt<1>(0h0))) node _T_2603 = asSInt(_T_2602) node _T_2604 = eq(_T_2603, asSInt(UInt<1>(0h0))) node _T_2605 = or(_T_2599, _T_2604) node _uncommonBits_T_248 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_248 = bits(_uncommonBits_T_248, 4, 0) node _T_2606 = shr(io.in.b.bits.source, 5) node _T_2607 = eq(_T_2606, UInt<4>(0hd)) node _T_2608 = leq(UInt<1>(0h0), uncommonBits_248) node _T_2609 = and(_T_2607, _T_2608) node _T_2610 = leq(uncommonBits_248, UInt<5>(0h1f)) node _T_2611 = and(_T_2609, _T_2610) node _T_2612 = eq(_T_2611, UInt<1>(0h0)) node _T_2613 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2614 = cvt(_T_2613) node _T_2615 = and(_T_2614, asSInt(UInt<1>(0h0))) node _T_2616 = asSInt(_T_2615) node _T_2617 = eq(_T_2616, asSInt(UInt<1>(0h0))) node _T_2618 = or(_T_2612, _T_2617) node _uncommonBits_T_249 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_249 = bits(_uncommonBits_T_249, 4, 0) node _T_2619 = shr(io.in.b.bits.source, 5) node _T_2620 = eq(_T_2619, UInt<4>(0hc)) node _T_2621 = leq(UInt<1>(0h0), uncommonBits_249) node _T_2622 = and(_T_2620, _T_2621) node _T_2623 = leq(uncommonBits_249, UInt<5>(0h1f)) node _T_2624 = and(_T_2622, _T_2623) node _T_2625 = eq(_T_2624, UInt<1>(0h0)) node _T_2626 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2627 = cvt(_T_2626) node _T_2628 = and(_T_2627, asSInt(UInt<1>(0h0))) node _T_2629 = asSInt(_T_2628) node _T_2630 = eq(_T_2629, asSInt(UInt<1>(0h0))) node _T_2631 = or(_T_2625, _T_2630) node _uncommonBits_T_250 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_250 = bits(_uncommonBits_T_250, 4, 0) node _T_2632 = shr(io.in.b.bits.source, 5) node _T_2633 = eq(_T_2632, UInt<4>(0hb)) node _T_2634 = leq(UInt<1>(0h0), uncommonBits_250) node _T_2635 = and(_T_2633, _T_2634) node _T_2636 = leq(uncommonBits_250, UInt<5>(0h1f)) node _T_2637 = and(_T_2635, _T_2636) node _T_2638 = eq(_T_2637, UInt<1>(0h0)) node _T_2639 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2640 = cvt(_T_2639) node _T_2641 = and(_T_2640, asSInt(UInt<1>(0h0))) node _T_2642 = asSInt(_T_2641) node _T_2643 = eq(_T_2642, asSInt(UInt<1>(0h0))) node _T_2644 = or(_T_2638, _T_2643) node _uncommonBits_T_251 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_251 = bits(_uncommonBits_T_251, 4, 0) node _T_2645 = shr(io.in.b.bits.source, 5) node _T_2646 = eq(_T_2645, UInt<4>(0ha)) node _T_2647 = leq(UInt<1>(0h0), uncommonBits_251) node _T_2648 = and(_T_2646, _T_2647) node _T_2649 = leq(uncommonBits_251, UInt<5>(0h1f)) node _T_2650 = and(_T_2648, _T_2649) node _T_2651 = eq(_T_2650, UInt<1>(0h0)) node _T_2652 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2653 = cvt(_T_2652) node _T_2654 = and(_T_2653, asSInt(UInt<1>(0h0))) node _T_2655 = asSInt(_T_2654) node _T_2656 = eq(_T_2655, asSInt(UInt<1>(0h0))) node _T_2657 = or(_T_2651, _T_2656) node _uncommonBits_T_252 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_252 = bits(_uncommonBits_T_252, 4, 0) node _T_2658 = shr(io.in.b.bits.source, 5) node _T_2659 = eq(_T_2658, UInt<4>(0h9)) node _T_2660 = leq(UInt<1>(0h0), uncommonBits_252) node _T_2661 = and(_T_2659, _T_2660) node _T_2662 = leq(uncommonBits_252, UInt<5>(0h1f)) node _T_2663 = and(_T_2661, _T_2662) node _T_2664 = eq(_T_2663, UInt<1>(0h0)) node _T_2665 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2666 = cvt(_T_2665) node _T_2667 = and(_T_2666, asSInt(UInt<1>(0h0))) node _T_2668 = asSInt(_T_2667) node _T_2669 = eq(_T_2668, asSInt(UInt<1>(0h0))) node _T_2670 = or(_T_2664, _T_2669) node _uncommonBits_T_253 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_253 = bits(_uncommonBits_T_253, 4, 0) node _T_2671 = shr(io.in.b.bits.source, 5) node _T_2672 = eq(_T_2671, UInt<4>(0h8)) node _T_2673 = leq(UInt<1>(0h0), uncommonBits_253) node _T_2674 = and(_T_2672, _T_2673) node _T_2675 = leq(uncommonBits_253, UInt<5>(0h1f)) node _T_2676 = and(_T_2674, _T_2675) node _T_2677 = eq(_T_2676, UInt<1>(0h0)) node _T_2678 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2679 = cvt(_T_2678) node _T_2680 = and(_T_2679, asSInt(UInt<1>(0h0))) node _T_2681 = asSInt(_T_2680) node _T_2682 = eq(_T_2681, asSInt(UInt<1>(0h0))) node _T_2683 = or(_T_2677, _T_2682) node _uncommonBits_T_254 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_254 = bits(_uncommonBits_T_254, 1, 0) node _T_2684 = shr(io.in.b.bits.source, 2) node _T_2685 = eq(_T_2684, UInt<7>(0h7a)) node _T_2686 = leq(UInt<1>(0h0), uncommonBits_254) node _T_2687 = and(_T_2685, _T_2686) node _T_2688 = leq(uncommonBits_254, UInt<2>(0h3)) node _T_2689 = and(_T_2687, _T_2688) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) node _T_2691 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2692 = cvt(_T_2691) node _T_2693 = and(_T_2692, asSInt(UInt<1>(0h0))) node _T_2694 = asSInt(_T_2693) node _T_2695 = eq(_T_2694, asSInt(UInt<1>(0h0))) node _T_2696 = or(_T_2690, _T_2695) node _uncommonBits_T_255 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_255 = bits(_uncommonBits_T_255, 1, 0) node _T_2697 = shr(io.in.b.bits.source, 2) node _T_2698 = eq(_T_2697, UInt<7>(0h79)) node _T_2699 = leq(UInt<1>(0h0), uncommonBits_255) node _T_2700 = and(_T_2698, _T_2699) node _T_2701 = leq(uncommonBits_255, UInt<2>(0h3)) node _T_2702 = and(_T_2700, _T_2701) node _T_2703 = eq(_T_2702, UInt<1>(0h0)) node _T_2704 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2705 = cvt(_T_2704) node _T_2706 = and(_T_2705, asSInt(UInt<1>(0h0))) node _T_2707 = asSInt(_T_2706) node _T_2708 = eq(_T_2707, asSInt(UInt<1>(0h0))) node _T_2709 = or(_T_2703, _T_2708) node _uncommonBits_T_256 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_256 = bits(_uncommonBits_T_256, 4, 0) node _T_2710 = shr(io.in.b.bits.source, 5) node _T_2711 = eq(_T_2710, UInt<3>(0h7)) node _T_2712 = leq(UInt<1>(0h0), uncommonBits_256) node _T_2713 = and(_T_2711, _T_2712) node _T_2714 = leq(uncommonBits_256, UInt<5>(0h1f)) node _T_2715 = and(_T_2713, _T_2714) node _T_2716 = eq(_T_2715, UInt<1>(0h0)) node _T_2717 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2718 = cvt(_T_2717) node _T_2719 = and(_T_2718, asSInt(UInt<1>(0h0))) node _T_2720 = asSInt(_T_2719) node _T_2721 = eq(_T_2720, asSInt(UInt<1>(0h0))) node _T_2722 = or(_T_2716, _T_2721) node _uncommonBits_T_257 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_257 = bits(_uncommonBits_T_257, 4, 0) node _T_2723 = shr(io.in.b.bits.source, 5) node _T_2724 = eq(_T_2723, UInt<3>(0h6)) node _T_2725 = leq(UInt<1>(0h0), uncommonBits_257) node _T_2726 = and(_T_2724, _T_2725) node _T_2727 = leq(uncommonBits_257, UInt<5>(0h1f)) node _T_2728 = and(_T_2726, _T_2727) node _T_2729 = eq(_T_2728, UInt<1>(0h0)) node _T_2730 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2731 = cvt(_T_2730) node _T_2732 = and(_T_2731, asSInt(UInt<1>(0h0))) node _T_2733 = asSInt(_T_2732) node _T_2734 = eq(_T_2733, asSInt(UInt<1>(0h0))) node _T_2735 = or(_T_2729, _T_2734) node _uncommonBits_T_258 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_258 = bits(_uncommonBits_T_258, 4, 0) node _T_2736 = shr(io.in.b.bits.source, 5) node _T_2737 = eq(_T_2736, UInt<3>(0h5)) node _T_2738 = leq(UInt<1>(0h0), uncommonBits_258) node _T_2739 = and(_T_2737, _T_2738) node _T_2740 = leq(uncommonBits_258, UInt<5>(0h1f)) node _T_2741 = and(_T_2739, _T_2740) node _T_2742 = eq(_T_2741, UInt<1>(0h0)) node _T_2743 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2744 = cvt(_T_2743) node _T_2745 = and(_T_2744, asSInt(UInt<1>(0h0))) node _T_2746 = asSInt(_T_2745) node _T_2747 = eq(_T_2746, asSInt(UInt<1>(0h0))) node _T_2748 = or(_T_2742, _T_2747) node _uncommonBits_T_259 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_259 = bits(_uncommonBits_T_259, 4, 0) node _T_2749 = shr(io.in.b.bits.source, 5) node _T_2750 = eq(_T_2749, UInt<3>(0h4)) node _T_2751 = leq(UInt<1>(0h0), uncommonBits_259) node _T_2752 = and(_T_2750, _T_2751) node _T_2753 = leq(uncommonBits_259, UInt<5>(0h1f)) node _T_2754 = and(_T_2752, _T_2753) node _T_2755 = eq(_T_2754, UInt<1>(0h0)) node _T_2756 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2757 = cvt(_T_2756) node _T_2758 = and(_T_2757, asSInt(UInt<1>(0h0))) node _T_2759 = asSInt(_T_2758) node _T_2760 = eq(_T_2759, asSInt(UInt<1>(0h0))) node _T_2761 = or(_T_2755, _T_2760) node _uncommonBits_T_260 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_260 = bits(_uncommonBits_T_260, 4, 0) node _T_2762 = shr(io.in.b.bits.source, 5) node _T_2763 = eq(_T_2762, UInt<2>(0h3)) node _T_2764 = leq(UInt<1>(0h0), uncommonBits_260) node _T_2765 = and(_T_2763, _T_2764) node _T_2766 = leq(uncommonBits_260, UInt<5>(0h1f)) node _T_2767 = and(_T_2765, _T_2766) node _T_2768 = eq(_T_2767, UInt<1>(0h0)) node _T_2769 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2770 = cvt(_T_2769) node _T_2771 = and(_T_2770, asSInt(UInt<1>(0h0))) node _T_2772 = asSInt(_T_2771) node _T_2773 = eq(_T_2772, asSInt(UInt<1>(0h0))) node _T_2774 = or(_T_2768, _T_2773) node _uncommonBits_T_261 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_261 = bits(_uncommonBits_T_261, 4, 0) node _T_2775 = shr(io.in.b.bits.source, 5) node _T_2776 = eq(_T_2775, UInt<2>(0h2)) node _T_2777 = leq(UInt<1>(0h0), uncommonBits_261) node _T_2778 = and(_T_2776, _T_2777) node _T_2779 = leq(uncommonBits_261, UInt<5>(0h1f)) node _T_2780 = and(_T_2778, _T_2779) node _T_2781 = eq(_T_2780, UInt<1>(0h0)) node _T_2782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2783 = cvt(_T_2782) node _T_2784 = and(_T_2783, asSInt(UInt<1>(0h0))) node _T_2785 = asSInt(_T_2784) node _T_2786 = eq(_T_2785, asSInt(UInt<1>(0h0))) node _T_2787 = or(_T_2781, _T_2786) node _uncommonBits_T_262 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_262 = bits(_uncommonBits_T_262, 4, 0) node _T_2788 = shr(io.in.b.bits.source, 5) node _T_2789 = eq(_T_2788, UInt<1>(0h1)) node _T_2790 = leq(UInt<1>(0h0), uncommonBits_262) node _T_2791 = and(_T_2789, _T_2790) node _T_2792 = leq(uncommonBits_262, UInt<5>(0h1f)) node _T_2793 = and(_T_2791, _T_2792) node _T_2794 = eq(_T_2793, UInt<1>(0h0)) node _T_2795 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2796 = cvt(_T_2795) node _T_2797 = and(_T_2796, asSInt(UInt<1>(0h0))) node _T_2798 = asSInt(_T_2797) node _T_2799 = eq(_T_2798, asSInt(UInt<1>(0h0))) node _T_2800 = or(_T_2794, _T_2799) node _uncommonBits_T_263 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_263 = bits(_uncommonBits_T_263, 4, 0) node _T_2801 = shr(io.in.b.bits.source, 5) node _T_2802 = eq(_T_2801, UInt<1>(0h0)) node _T_2803 = leq(UInt<1>(0h0), uncommonBits_263) node _T_2804 = and(_T_2802, _T_2803) node _T_2805 = leq(uncommonBits_263, UInt<5>(0h1f)) node _T_2806 = and(_T_2804, _T_2805) node _T_2807 = eq(_T_2806, UInt<1>(0h0)) node _T_2808 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2809 = cvt(_T_2808) node _T_2810 = and(_T_2809, asSInt(UInt<1>(0h0))) node _T_2811 = asSInt(_T_2810) node _T_2812 = eq(_T_2811, asSInt(UInt<1>(0h0))) node _T_2813 = or(_T_2807, _T_2812) node _T_2814 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _T_2815 = eq(_T_2814, UInt<1>(0h0)) node _T_2816 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2817 = cvt(_T_2816) node _T_2818 = and(_T_2817, asSInt(UInt<1>(0h0))) node _T_2819 = asSInt(_T_2818) node _T_2820 = eq(_T_2819, asSInt(UInt<1>(0h0))) node _T_2821 = or(_T_2815, _T_2820) node _T_2822 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) node _T_2823 = eq(_T_2822, UInt<1>(0h0)) node _T_2824 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_2825 = cvt(_T_2824) node _T_2826 = and(_T_2825, asSInt(UInt<1>(0h0))) node _T_2827 = asSInt(_T_2826) node _T_2828 = eq(_T_2827, asSInt(UInt<1>(0h0))) node _T_2829 = or(_T_2823, _T_2828) node _T_2830 = and(_T_2527, _T_2540) node _T_2831 = and(_T_2830, _T_2553) node _T_2832 = and(_T_2831, _T_2566) node _T_2833 = and(_T_2832, _T_2579) node _T_2834 = and(_T_2833, _T_2592) node _T_2835 = and(_T_2834, _T_2605) node _T_2836 = and(_T_2835, _T_2618) node _T_2837 = and(_T_2836, _T_2631) node _T_2838 = and(_T_2837, _T_2644) node _T_2839 = and(_T_2838, _T_2657) node _T_2840 = and(_T_2839, _T_2670) node _T_2841 = and(_T_2840, _T_2683) node _T_2842 = and(_T_2841, _T_2696) node _T_2843 = and(_T_2842, _T_2709) node _T_2844 = and(_T_2843, _T_2722) node _T_2845 = and(_T_2844, _T_2735) node _T_2846 = and(_T_2845, _T_2748) node _T_2847 = and(_T_2846, _T_2761) node _T_2848 = and(_T_2847, _T_2774) node _T_2849 = and(_T_2848, _T_2787) node _T_2850 = and(_T_2849, _T_2800) node _T_2851 = and(_T_2850, _T_2813) node _T_2852 = and(_T_2851, _T_2821) node _T_2853 = and(_T_2852, _T_2829) node _T_2854 = asUInt(reset) node _T_2855 = eq(_T_2854, UInt<1>(0h0)) when _T_2855 : node _T_2856 = eq(_T_2853, UInt<1>(0h0)) when _T_2856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2853, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<7>(0h70)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<7>(0h71)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<7>(0h72)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<7>(0h73)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 1, 0) node _legal_source_T_25 = shr(io.in.b.bits.source, 2) node _legal_source_T_26 = eq(_legal_source_T_25, UInt<7>(0h7c)) node _legal_source_T_27 = leq(UInt<1>(0h0), legal_source_uncommonBits_4) node _legal_source_T_28 = and(_legal_source_T_26, _legal_source_T_27) node _legal_source_T_29 = leq(legal_source_uncommonBits_4, UInt<2>(0h3)) node _legal_source_T_30 = and(_legal_source_T_28, _legal_source_T_29) node _legal_source_uncommonBits_T_5 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_5 = bits(_legal_source_uncommonBits_T_5, 1, 0) node _legal_source_T_31 = shr(io.in.b.bits.source, 2) node _legal_source_T_32 = eq(_legal_source_T_31, UInt<7>(0h7b)) node _legal_source_T_33 = leq(UInt<1>(0h0), legal_source_uncommonBits_5) node _legal_source_T_34 = and(_legal_source_T_32, _legal_source_T_33) node _legal_source_T_35 = leq(legal_source_uncommonBits_5, UInt<2>(0h3)) node _legal_source_T_36 = and(_legal_source_T_34, _legal_source_T_35) node _legal_source_uncommonBits_T_6 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_6 = bits(_legal_source_uncommonBits_T_6, 4, 0) node _legal_source_T_37 = shr(io.in.b.bits.source, 5) node _legal_source_T_38 = eq(_legal_source_T_37, UInt<4>(0hd)) node _legal_source_T_39 = leq(UInt<1>(0h0), legal_source_uncommonBits_6) node _legal_source_T_40 = and(_legal_source_T_38, _legal_source_T_39) node _legal_source_T_41 = leq(legal_source_uncommonBits_6, UInt<5>(0h1f)) node _legal_source_T_42 = and(_legal_source_T_40, _legal_source_T_41) node _legal_source_uncommonBits_T_7 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_7 = bits(_legal_source_uncommonBits_T_7, 4, 0) node _legal_source_T_43 = shr(io.in.b.bits.source, 5) node _legal_source_T_44 = eq(_legal_source_T_43, UInt<4>(0hc)) node _legal_source_T_45 = leq(UInt<1>(0h0), legal_source_uncommonBits_7) node _legal_source_T_46 = and(_legal_source_T_44, _legal_source_T_45) node _legal_source_T_47 = leq(legal_source_uncommonBits_7, UInt<5>(0h1f)) node _legal_source_T_48 = and(_legal_source_T_46, _legal_source_T_47) node _legal_source_uncommonBits_T_8 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_8 = bits(_legal_source_uncommonBits_T_8, 4, 0) node _legal_source_T_49 = shr(io.in.b.bits.source, 5) node _legal_source_T_50 = eq(_legal_source_T_49, UInt<4>(0hb)) node _legal_source_T_51 = leq(UInt<1>(0h0), legal_source_uncommonBits_8) node _legal_source_T_52 = and(_legal_source_T_50, _legal_source_T_51) node _legal_source_T_53 = leq(legal_source_uncommonBits_8, UInt<5>(0h1f)) node _legal_source_T_54 = and(_legal_source_T_52, _legal_source_T_53) node _legal_source_uncommonBits_T_9 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_9 = bits(_legal_source_uncommonBits_T_9, 4, 0) node _legal_source_T_55 = shr(io.in.b.bits.source, 5) node _legal_source_T_56 = eq(_legal_source_T_55, UInt<4>(0ha)) node _legal_source_T_57 = leq(UInt<1>(0h0), legal_source_uncommonBits_9) node _legal_source_T_58 = and(_legal_source_T_56, _legal_source_T_57) node _legal_source_T_59 = leq(legal_source_uncommonBits_9, UInt<5>(0h1f)) node _legal_source_T_60 = and(_legal_source_T_58, _legal_source_T_59) node _legal_source_uncommonBits_T_10 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_10 = bits(_legal_source_uncommonBits_T_10, 4, 0) node _legal_source_T_61 = shr(io.in.b.bits.source, 5) node _legal_source_T_62 = eq(_legal_source_T_61, UInt<4>(0h9)) node _legal_source_T_63 = leq(UInt<1>(0h0), legal_source_uncommonBits_10) node _legal_source_T_64 = and(_legal_source_T_62, _legal_source_T_63) node _legal_source_T_65 = leq(legal_source_uncommonBits_10, UInt<5>(0h1f)) node _legal_source_T_66 = and(_legal_source_T_64, _legal_source_T_65) node _legal_source_uncommonBits_T_11 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_11 = bits(_legal_source_uncommonBits_T_11, 4, 0) node _legal_source_T_67 = shr(io.in.b.bits.source, 5) node _legal_source_T_68 = eq(_legal_source_T_67, UInt<4>(0h8)) node _legal_source_T_69 = leq(UInt<1>(0h0), legal_source_uncommonBits_11) node _legal_source_T_70 = and(_legal_source_T_68, _legal_source_T_69) node _legal_source_T_71 = leq(legal_source_uncommonBits_11, UInt<5>(0h1f)) node _legal_source_T_72 = and(_legal_source_T_70, _legal_source_T_71) node _legal_source_uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_12 = bits(_legal_source_uncommonBits_T_12, 1, 0) node _legal_source_T_73 = shr(io.in.b.bits.source, 2) node _legal_source_T_74 = eq(_legal_source_T_73, UInt<7>(0h7a)) node _legal_source_T_75 = leq(UInt<1>(0h0), legal_source_uncommonBits_12) node _legal_source_T_76 = and(_legal_source_T_74, _legal_source_T_75) node _legal_source_T_77 = leq(legal_source_uncommonBits_12, UInt<2>(0h3)) node _legal_source_T_78 = and(_legal_source_T_76, _legal_source_T_77) node _legal_source_uncommonBits_T_13 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_13 = bits(_legal_source_uncommonBits_T_13, 1, 0) node _legal_source_T_79 = shr(io.in.b.bits.source, 2) node _legal_source_T_80 = eq(_legal_source_T_79, UInt<7>(0h79)) node _legal_source_T_81 = leq(UInt<1>(0h0), legal_source_uncommonBits_13) node _legal_source_T_82 = and(_legal_source_T_80, _legal_source_T_81) node _legal_source_T_83 = leq(legal_source_uncommonBits_13, UInt<2>(0h3)) node _legal_source_T_84 = and(_legal_source_T_82, _legal_source_T_83) node _legal_source_uncommonBits_T_14 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_14 = bits(_legal_source_uncommonBits_T_14, 4, 0) node _legal_source_T_85 = shr(io.in.b.bits.source, 5) node _legal_source_T_86 = eq(_legal_source_T_85, UInt<3>(0h7)) node _legal_source_T_87 = leq(UInt<1>(0h0), legal_source_uncommonBits_14) node _legal_source_T_88 = and(_legal_source_T_86, _legal_source_T_87) node _legal_source_T_89 = leq(legal_source_uncommonBits_14, UInt<5>(0h1f)) node _legal_source_T_90 = and(_legal_source_T_88, _legal_source_T_89) node _legal_source_uncommonBits_T_15 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_15 = bits(_legal_source_uncommonBits_T_15, 4, 0) node _legal_source_T_91 = shr(io.in.b.bits.source, 5) node _legal_source_T_92 = eq(_legal_source_T_91, UInt<3>(0h6)) node _legal_source_T_93 = leq(UInt<1>(0h0), legal_source_uncommonBits_15) node _legal_source_T_94 = and(_legal_source_T_92, _legal_source_T_93) node _legal_source_T_95 = leq(legal_source_uncommonBits_15, UInt<5>(0h1f)) node _legal_source_T_96 = and(_legal_source_T_94, _legal_source_T_95) node _legal_source_uncommonBits_T_16 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_16 = bits(_legal_source_uncommonBits_T_16, 4, 0) node _legal_source_T_97 = shr(io.in.b.bits.source, 5) node _legal_source_T_98 = eq(_legal_source_T_97, UInt<3>(0h5)) node _legal_source_T_99 = leq(UInt<1>(0h0), legal_source_uncommonBits_16) node _legal_source_T_100 = and(_legal_source_T_98, _legal_source_T_99) node _legal_source_T_101 = leq(legal_source_uncommonBits_16, UInt<5>(0h1f)) node _legal_source_T_102 = and(_legal_source_T_100, _legal_source_T_101) node _legal_source_uncommonBits_T_17 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_17 = bits(_legal_source_uncommonBits_T_17, 4, 0) node _legal_source_T_103 = shr(io.in.b.bits.source, 5) node _legal_source_T_104 = eq(_legal_source_T_103, UInt<3>(0h4)) node _legal_source_T_105 = leq(UInt<1>(0h0), legal_source_uncommonBits_17) node _legal_source_T_106 = and(_legal_source_T_104, _legal_source_T_105) node _legal_source_T_107 = leq(legal_source_uncommonBits_17, UInt<5>(0h1f)) node _legal_source_T_108 = and(_legal_source_T_106, _legal_source_T_107) node _legal_source_uncommonBits_T_18 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_18 = bits(_legal_source_uncommonBits_T_18, 4, 0) node _legal_source_T_109 = shr(io.in.b.bits.source, 5) node _legal_source_T_110 = eq(_legal_source_T_109, UInt<2>(0h3)) node _legal_source_T_111 = leq(UInt<1>(0h0), legal_source_uncommonBits_18) node _legal_source_T_112 = and(_legal_source_T_110, _legal_source_T_111) node _legal_source_T_113 = leq(legal_source_uncommonBits_18, UInt<5>(0h1f)) node _legal_source_T_114 = and(_legal_source_T_112, _legal_source_T_113) node _legal_source_uncommonBits_T_19 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_19 = bits(_legal_source_uncommonBits_T_19, 4, 0) node _legal_source_T_115 = shr(io.in.b.bits.source, 5) node _legal_source_T_116 = eq(_legal_source_T_115, UInt<2>(0h2)) node _legal_source_T_117 = leq(UInt<1>(0h0), legal_source_uncommonBits_19) node _legal_source_T_118 = and(_legal_source_T_116, _legal_source_T_117) node _legal_source_T_119 = leq(legal_source_uncommonBits_19, UInt<5>(0h1f)) node _legal_source_T_120 = and(_legal_source_T_118, _legal_source_T_119) node _legal_source_uncommonBits_T_20 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_20 = bits(_legal_source_uncommonBits_T_20, 4, 0) node _legal_source_T_121 = shr(io.in.b.bits.source, 5) node _legal_source_T_122 = eq(_legal_source_T_121, UInt<1>(0h1)) node _legal_source_T_123 = leq(UInt<1>(0h0), legal_source_uncommonBits_20) node _legal_source_T_124 = and(_legal_source_T_122, _legal_source_T_123) node _legal_source_T_125 = leq(legal_source_uncommonBits_20, UInt<5>(0h1f)) node _legal_source_T_126 = and(_legal_source_T_124, _legal_source_T_125) node _legal_source_uncommonBits_T_21 = or(io.in.b.bits.source, UInt<5>(0h0)) node legal_source_uncommonBits_21 = bits(_legal_source_uncommonBits_T_21, 4, 0) node _legal_source_T_127 = shr(io.in.b.bits.source, 5) node _legal_source_T_128 = eq(_legal_source_T_127, UInt<1>(0h0)) node _legal_source_T_129 = leq(UInt<1>(0h0), legal_source_uncommonBits_21) node _legal_source_T_130 = and(_legal_source_T_128, _legal_source_T_129) node _legal_source_T_131 = leq(legal_source_uncommonBits_21, UInt<5>(0h1f)) node _legal_source_T_132 = and(_legal_source_T_130, _legal_source_T_131) node _legal_source_T_133 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _legal_source_T_134 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) wire _legal_source_WIRE : UInt<1>[25] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_30 connect _legal_source_WIRE[6], _legal_source_T_36 connect _legal_source_WIRE[7], _legal_source_T_42 connect _legal_source_WIRE[8], _legal_source_T_48 connect _legal_source_WIRE[9], _legal_source_T_54 connect _legal_source_WIRE[10], _legal_source_T_60 connect _legal_source_WIRE[11], _legal_source_T_66 connect _legal_source_WIRE[12], _legal_source_T_72 connect _legal_source_WIRE[13], _legal_source_T_78 connect _legal_source_WIRE[14], _legal_source_T_84 connect _legal_source_WIRE[15], _legal_source_T_90 connect _legal_source_WIRE[16], _legal_source_T_96 connect _legal_source_WIRE[17], _legal_source_T_102 connect _legal_source_WIRE[18], _legal_source_T_108 connect _legal_source_WIRE[19], _legal_source_T_114 connect _legal_source_WIRE[20], _legal_source_T_120 connect _legal_source_WIRE[21], _legal_source_T_126 connect _legal_source_WIRE[22], _legal_source_T_132 connect _legal_source_WIRE[23], _legal_source_T_133 connect _legal_source_WIRE[24], _legal_source_T_134 node _legal_source_T_135 = mux(_legal_source_WIRE[0], UInt<9>(0h1d0), UInt<1>(0h0)) node _legal_source_T_136 = mux(_legal_source_WIRE[1], UInt<9>(0h1c0), UInt<1>(0h0)) node _legal_source_T_137 = mux(_legal_source_WIRE[2], UInt<9>(0h1c4), UInt<1>(0h0)) node _legal_source_T_138 = mux(_legal_source_WIRE[3], UInt<9>(0h1c8), UInt<1>(0h0)) node _legal_source_T_139 = mux(_legal_source_WIRE[4], UInt<9>(0h1cc), UInt<1>(0h0)) node _legal_source_T_140 = mux(_legal_source_WIRE[5], UInt<9>(0h1f0), UInt<1>(0h0)) node _legal_source_T_141 = mux(_legal_source_WIRE[6], UInt<9>(0h1ec), UInt<1>(0h0)) node _legal_source_T_142 = mux(_legal_source_WIRE[7], UInt<9>(0h1a0), UInt<1>(0h0)) node _legal_source_T_143 = mux(_legal_source_WIRE[8], UInt<9>(0h180), UInt<1>(0h0)) node _legal_source_T_144 = mux(_legal_source_WIRE[9], UInt<9>(0h160), UInt<1>(0h0)) node _legal_source_T_145 = mux(_legal_source_WIRE[10], UInt<9>(0h140), UInt<1>(0h0)) node _legal_source_T_146 = mux(_legal_source_WIRE[11], UInt<9>(0h120), UInt<1>(0h0)) node _legal_source_T_147 = mux(_legal_source_WIRE[12], UInt<9>(0h100), UInt<1>(0h0)) node _legal_source_T_148 = mux(_legal_source_WIRE[13], UInt<9>(0h1e8), UInt<1>(0h0)) node _legal_source_T_149 = mux(_legal_source_WIRE[14], UInt<9>(0h1e4), UInt<1>(0h0)) node _legal_source_T_150 = mux(_legal_source_WIRE[15], UInt<8>(0he0), UInt<1>(0h0)) node _legal_source_T_151 = mux(_legal_source_WIRE[16], UInt<8>(0hc0), UInt<1>(0h0)) node _legal_source_T_152 = mux(_legal_source_WIRE[17], UInt<8>(0ha0), UInt<1>(0h0)) node _legal_source_T_153 = mux(_legal_source_WIRE[18], UInt<8>(0h80), UInt<1>(0h0)) node _legal_source_T_154 = mux(_legal_source_WIRE[19], UInt<7>(0h60), UInt<1>(0h0)) node _legal_source_T_155 = mux(_legal_source_WIRE[20], UInt<7>(0h40), UInt<1>(0h0)) node _legal_source_T_156 = mux(_legal_source_WIRE[21], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_157 = mux(_legal_source_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_158 = mux(_legal_source_WIRE[23], UInt<9>(0h1e0), UInt<1>(0h0)) node _legal_source_T_159 = mux(_legal_source_WIRE[24], UInt<9>(0h1e2), UInt<1>(0h0)) node _legal_source_T_160 = or(_legal_source_T_135, _legal_source_T_136) node _legal_source_T_161 = or(_legal_source_T_160, _legal_source_T_137) node _legal_source_T_162 = or(_legal_source_T_161, _legal_source_T_138) node _legal_source_T_163 = or(_legal_source_T_162, _legal_source_T_139) node _legal_source_T_164 = or(_legal_source_T_163, _legal_source_T_140) node _legal_source_T_165 = or(_legal_source_T_164, _legal_source_T_141) node _legal_source_T_166 = or(_legal_source_T_165, _legal_source_T_142) node _legal_source_T_167 = or(_legal_source_T_166, _legal_source_T_143) node _legal_source_T_168 = or(_legal_source_T_167, _legal_source_T_144) node _legal_source_T_169 = or(_legal_source_T_168, _legal_source_T_145) node _legal_source_T_170 = or(_legal_source_T_169, _legal_source_T_146) node _legal_source_T_171 = or(_legal_source_T_170, _legal_source_T_147) node _legal_source_T_172 = or(_legal_source_T_171, _legal_source_T_148) node _legal_source_T_173 = or(_legal_source_T_172, _legal_source_T_149) node _legal_source_T_174 = or(_legal_source_T_173, _legal_source_T_150) node _legal_source_T_175 = or(_legal_source_T_174, _legal_source_T_151) node _legal_source_T_176 = or(_legal_source_T_175, _legal_source_T_152) node _legal_source_T_177 = or(_legal_source_T_176, _legal_source_T_153) node _legal_source_T_178 = or(_legal_source_T_177, _legal_source_T_154) node _legal_source_T_179 = or(_legal_source_T_178, _legal_source_T_155) node _legal_source_T_180 = or(_legal_source_T_179, _legal_source_T_156) node _legal_source_T_181 = or(_legal_source_T_180, _legal_source_T_157) node _legal_source_T_182 = or(_legal_source_T_181, _legal_source_T_158) node _legal_source_T_183 = or(_legal_source_T_182, _legal_source_T_159) wire _legal_source_WIRE_1 : UInt<9> connect _legal_source_WIRE_1, _legal_source_T_183 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_2857 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_2857 : node _T_2858 = eq(io.in.b.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_264 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_264 = bits(_uncommonBits_T_264, 1, 0) node _T_2859 = shr(io.in.b.bits.source, 2) node _T_2860 = eq(_T_2859, UInt<7>(0h70)) node _T_2861 = leq(UInt<1>(0h0), uncommonBits_264) node _T_2862 = and(_T_2860, _T_2861) node _T_2863 = leq(uncommonBits_264, UInt<2>(0h3)) node _T_2864 = and(_T_2862, _T_2863) node _uncommonBits_T_265 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_265 = bits(_uncommonBits_T_265, 1, 0) node _T_2865 = shr(io.in.b.bits.source, 2) node _T_2866 = eq(_T_2865, UInt<7>(0h71)) node _T_2867 = leq(UInt<1>(0h0), uncommonBits_265) node _T_2868 = and(_T_2866, _T_2867) node _T_2869 = leq(uncommonBits_265, UInt<2>(0h3)) node _T_2870 = and(_T_2868, _T_2869) node _uncommonBits_T_266 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_266 = bits(_uncommonBits_T_266, 1, 0) node _T_2871 = shr(io.in.b.bits.source, 2) node _T_2872 = eq(_T_2871, UInt<7>(0h72)) node _T_2873 = leq(UInt<1>(0h0), uncommonBits_266) node _T_2874 = and(_T_2872, _T_2873) node _T_2875 = leq(uncommonBits_266, UInt<2>(0h3)) node _T_2876 = and(_T_2874, _T_2875) node _uncommonBits_T_267 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_267 = bits(_uncommonBits_T_267, 1, 0) node _T_2877 = shr(io.in.b.bits.source, 2) node _T_2878 = eq(_T_2877, UInt<7>(0h73)) node _T_2879 = leq(UInt<1>(0h0), uncommonBits_267) node _T_2880 = and(_T_2878, _T_2879) node _T_2881 = leq(uncommonBits_267, UInt<2>(0h3)) node _T_2882 = and(_T_2880, _T_2881) node _uncommonBits_T_268 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_268 = bits(_uncommonBits_T_268, 1, 0) node _T_2883 = shr(io.in.b.bits.source, 2) node _T_2884 = eq(_T_2883, UInt<7>(0h7c)) node _T_2885 = leq(UInt<1>(0h0), uncommonBits_268) node _T_2886 = and(_T_2884, _T_2885) node _T_2887 = leq(uncommonBits_268, UInt<2>(0h3)) node _T_2888 = and(_T_2886, _T_2887) node _uncommonBits_T_269 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_269 = bits(_uncommonBits_T_269, 1, 0) node _T_2889 = shr(io.in.b.bits.source, 2) node _T_2890 = eq(_T_2889, UInt<7>(0h7b)) node _T_2891 = leq(UInt<1>(0h0), uncommonBits_269) node _T_2892 = and(_T_2890, _T_2891) node _T_2893 = leq(uncommonBits_269, UInt<2>(0h3)) node _T_2894 = and(_T_2892, _T_2893) node _uncommonBits_T_270 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_270 = bits(_uncommonBits_T_270, 4, 0) node _T_2895 = shr(io.in.b.bits.source, 5) node _T_2896 = eq(_T_2895, UInt<4>(0hd)) node _T_2897 = leq(UInt<1>(0h0), uncommonBits_270) node _T_2898 = and(_T_2896, _T_2897) node _T_2899 = leq(uncommonBits_270, UInt<5>(0h1f)) node _T_2900 = and(_T_2898, _T_2899) node _uncommonBits_T_271 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_271 = bits(_uncommonBits_T_271, 4, 0) node _T_2901 = shr(io.in.b.bits.source, 5) node _T_2902 = eq(_T_2901, UInt<4>(0hc)) node _T_2903 = leq(UInt<1>(0h0), uncommonBits_271) node _T_2904 = and(_T_2902, _T_2903) node _T_2905 = leq(uncommonBits_271, UInt<5>(0h1f)) node _T_2906 = and(_T_2904, _T_2905) node _uncommonBits_T_272 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_272 = bits(_uncommonBits_T_272, 4, 0) node _T_2907 = shr(io.in.b.bits.source, 5) node _T_2908 = eq(_T_2907, UInt<4>(0hb)) node _T_2909 = leq(UInt<1>(0h0), uncommonBits_272) node _T_2910 = and(_T_2908, _T_2909) node _T_2911 = leq(uncommonBits_272, UInt<5>(0h1f)) node _T_2912 = and(_T_2910, _T_2911) node _uncommonBits_T_273 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_273 = bits(_uncommonBits_T_273, 4, 0) node _T_2913 = shr(io.in.b.bits.source, 5) node _T_2914 = eq(_T_2913, UInt<4>(0ha)) node _T_2915 = leq(UInt<1>(0h0), uncommonBits_273) node _T_2916 = and(_T_2914, _T_2915) node _T_2917 = leq(uncommonBits_273, UInt<5>(0h1f)) node _T_2918 = and(_T_2916, _T_2917) node _uncommonBits_T_274 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_274 = bits(_uncommonBits_T_274, 4, 0) node _T_2919 = shr(io.in.b.bits.source, 5) node _T_2920 = eq(_T_2919, UInt<4>(0h9)) node _T_2921 = leq(UInt<1>(0h0), uncommonBits_274) node _T_2922 = and(_T_2920, _T_2921) node _T_2923 = leq(uncommonBits_274, UInt<5>(0h1f)) node _T_2924 = and(_T_2922, _T_2923) node _uncommonBits_T_275 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_275 = bits(_uncommonBits_T_275, 4, 0) node _T_2925 = shr(io.in.b.bits.source, 5) node _T_2926 = eq(_T_2925, UInt<4>(0h8)) node _T_2927 = leq(UInt<1>(0h0), uncommonBits_275) node _T_2928 = and(_T_2926, _T_2927) node _T_2929 = leq(uncommonBits_275, UInt<5>(0h1f)) node _T_2930 = and(_T_2928, _T_2929) node _uncommonBits_T_276 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_276 = bits(_uncommonBits_T_276, 1, 0) node _T_2931 = shr(io.in.b.bits.source, 2) node _T_2932 = eq(_T_2931, UInt<7>(0h7a)) node _T_2933 = leq(UInt<1>(0h0), uncommonBits_276) node _T_2934 = and(_T_2932, _T_2933) node _T_2935 = leq(uncommonBits_276, UInt<2>(0h3)) node _T_2936 = and(_T_2934, _T_2935) node _uncommonBits_T_277 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_277 = bits(_uncommonBits_T_277, 1, 0) node _T_2937 = shr(io.in.b.bits.source, 2) node _T_2938 = eq(_T_2937, UInt<7>(0h79)) node _T_2939 = leq(UInt<1>(0h0), uncommonBits_277) node _T_2940 = and(_T_2938, _T_2939) node _T_2941 = leq(uncommonBits_277, UInt<2>(0h3)) node _T_2942 = and(_T_2940, _T_2941) node _uncommonBits_T_278 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_278 = bits(_uncommonBits_T_278, 4, 0) node _T_2943 = shr(io.in.b.bits.source, 5) node _T_2944 = eq(_T_2943, UInt<3>(0h7)) node _T_2945 = leq(UInt<1>(0h0), uncommonBits_278) node _T_2946 = and(_T_2944, _T_2945) node _T_2947 = leq(uncommonBits_278, UInt<5>(0h1f)) node _T_2948 = and(_T_2946, _T_2947) node _uncommonBits_T_279 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_279 = bits(_uncommonBits_T_279, 4, 0) node _T_2949 = shr(io.in.b.bits.source, 5) node _T_2950 = eq(_T_2949, UInt<3>(0h6)) node _T_2951 = leq(UInt<1>(0h0), uncommonBits_279) node _T_2952 = and(_T_2950, _T_2951) node _T_2953 = leq(uncommonBits_279, UInt<5>(0h1f)) node _T_2954 = and(_T_2952, _T_2953) node _uncommonBits_T_280 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_280 = bits(_uncommonBits_T_280, 4, 0) node _T_2955 = shr(io.in.b.bits.source, 5) node _T_2956 = eq(_T_2955, UInt<3>(0h5)) node _T_2957 = leq(UInt<1>(0h0), uncommonBits_280) node _T_2958 = and(_T_2956, _T_2957) node _T_2959 = leq(uncommonBits_280, UInt<5>(0h1f)) node _T_2960 = and(_T_2958, _T_2959) node _uncommonBits_T_281 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_281 = bits(_uncommonBits_T_281, 4, 0) node _T_2961 = shr(io.in.b.bits.source, 5) node _T_2962 = eq(_T_2961, UInt<3>(0h4)) node _T_2963 = leq(UInt<1>(0h0), uncommonBits_281) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = leq(uncommonBits_281, UInt<5>(0h1f)) node _T_2966 = and(_T_2964, _T_2965) node _uncommonBits_T_282 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_282 = bits(_uncommonBits_T_282, 4, 0) node _T_2967 = shr(io.in.b.bits.source, 5) node _T_2968 = eq(_T_2967, UInt<2>(0h3)) node _T_2969 = leq(UInt<1>(0h0), uncommonBits_282) node _T_2970 = and(_T_2968, _T_2969) node _T_2971 = leq(uncommonBits_282, UInt<5>(0h1f)) node _T_2972 = and(_T_2970, _T_2971) node _uncommonBits_T_283 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_283 = bits(_uncommonBits_T_283, 4, 0) node _T_2973 = shr(io.in.b.bits.source, 5) node _T_2974 = eq(_T_2973, UInt<2>(0h2)) node _T_2975 = leq(UInt<1>(0h0), uncommonBits_283) node _T_2976 = and(_T_2974, _T_2975) node _T_2977 = leq(uncommonBits_283, UInt<5>(0h1f)) node _T_2978 = and(_T_2976, _T_2977) node _uncommonBits_T_284 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_284 = bits(_uncommonBits_T_284, 4, 0) node _T_2979 = shr(io.in.b.bits.source, 5) node _T_2980 = eq(_T_2979, UInt<1>(0h1)) node _T_2981 = leq(UInt<1>(0h0), uncommonBits_284) node _T_2982 = and(_T_2980, _T_2981) node _T_2983 = leq(uncommonBits_284, UInt<5>(0h1f)) node _T_2984 = and(_T_2982, _T_2983) node _uncommonBits_T_285 = or(io.in.b.bits.source, UInt<5>(0h0)) node uncommonBits_285 = bits(_uncommonBits_T_285, 4, 0) node _T_2985 = shr(io.in.b.bits.source, 5) node _T_2986 = eq(_T_2985, UInt<1>(0h0)) node _T_2987 = leq(UInt<1>(0h0), uncommonBits_285) node _T_2988 = and(_T_2986, _T_2987) node _T_2989 = leq(uncommonBits_285, UInt<5>(0h1f)) node _T_2990 = and(_T_2988, _T_2989) node _T_2991 = eq(io.in.b.bits.source, UInt<9>(0h1e0)) node _T_2992 = eq(io.in.b.bits.source, UInt<9>(0h1e2)) wire _WIRE_4 : UInt<1>[25] connect _WIRE_4[0], _T_2858 connect _WIRE_4[1], _T_2864 connect _WIRE_4[2], _T_2870 connect _WIRE_4[3], _T_2876 connect _WIRE_4[4], _T_2882 connect _WIRE_4[5], _T_2888 connect _WIRE_4[6], _T_2894 connect _WIRE_4[7], _T_2900 connect _WIRE_4[8], _T_2906 connect _WIRE_4[9], _T_2912 connect _WIRE_4[10], _T_2918 connect _WIRE_4[11], _T_2924 connect _WIRE_4[12], _T_2930 connect _WIRE_4[13], _T_2936 connect _WIRE_4[14], _T_2942 connect _WIRE_4[15], _T_2948 connect _WIRE_4[16], _T_2954 connect _WIRE_4[17], _T_2960 connect _WIRE_4[18], _T_2966 connect _WIRE_4[19], _T_2972 connect _WIRE_4[20], _T_2978 connect _WIRE_4[21], _T_2984 connect _WIRE_4[22], _T_2990 connect _WIRE_4[23], _T_2991 connect _WIRE_4[24], _T_2992 node _T_2993 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_2994 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2995 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2996 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2997 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2998 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2999 = mux(_WIRE_4[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_3000 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_3001 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_3002 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_3003 = mux(_WIRE_4[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_3004 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_3005 = mux(_WIRE_4[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_3006 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_3007 = mux(_WIRE_4[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_3008 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_3009 = mux(_WIRE_4[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_3010 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_3011 = mux(_WIRE_4[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_3012 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_3013 = mux(_WIRE_4[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_3014 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_3015 = mux(_WIRE_4[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_3016 = mux(_WIRE_4[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_3017 = mux(_WIRE_4[23], _T_2993, UInt<1>(0h0)) node _T_3018 = mux(_WIRE_4[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_3019 = or(_T_2994, _T_2995) node _T_3020 = or(_T_3019, _T_2996) node _T_3021 = or(_T_3020, _T_2997) node _T_3022 = or(_T_3021, _T_2998) node _T_3023 = or(_T_3022, _T_2999) node _T_3024 = or(_T_3023, _T_3000) node _T_3025 = or(_T_3024, _T_3001) node _T_3026 = or(_T_3025, _T_3002) node _T_3027 = or(_T_3026, _T_3003) node _T_3028 = or(_T_3027, _T_3004) node _T_3029 = or(_T_3028, _T_3005) node _T_3030 = or(_T_3029, _T_3006) node _T_3031 = or(_T_3030, _T_3007) node _T_3032 = or(_T_3031, _T_3008) node _T_3033 = or(_T_3032, _T_3009) node _T_3034 = or(_T_3033, _T_3010) node _T_3035 = or(_T_3034, _T_3011) node _T_3036 = or(_T_3035, _T_3012) node _T_3037 = or(_T_3036, _T_3013) node _T_3038 = or(_T_3037, _T_3014) node _T_3039 = or(_T_3038, _T_3015) node _T_3040 = or(_T_3039, _T_3016) node _T_3041 = or(_T_3040, _T_3017) node _T_3042 = or(_T_3041, _T_3018) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_3042 node _T_3043 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3044 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3045 = and(_T_3043, _T_3044) node _T_3046 = or(UInt<1>(0h0), _T_3045) node _T_3047 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3048 = cvt(_T_3047) node _T_3049 = and(_T_3048, asSInt(UInt<17>(0h10000))) node _T_3050 = asSInt(_T_3049) node _T_3051 = eq(_T_3050, asSInt(UInt<1>(0h0))) node _T_3052 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3053 = cvt(_T_3052) node _T_3054 = and(_T_3053, asSInt(UInt<29>(0h10000000))) node _T_3055 = asSInt(_T_3054) node _T_3056 = eq(_T_3055, asSInt(UInt<1>(0h0))) node _T_3057 = or(_T_3051, _T_3056) node _T_3058 = and(_T_3046, _T_3057) node _T_3059 = or(UInt<1>(0h0), _T_3058) node _T_3060 = and(_WIRE_5, _T_3059) node _T_3061 = asUInt(reset) node _T_3062 = eq(_T_3061, UInt<1>(0h0)) when _T_3062 : node _T_3063 = eq(_T_3060, UInt<1>(0h0)) when _T_3063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_3060, UInt<1>(0h1), "") : assert_86 node _T_3064 = asUInt(reset) node _T_3065 = eq(_T_3064, UInt<1>(0h0)) when _T_3065 : node _T_3066 = eq(address_ok, UInt<1>(0h0)) when _T_3066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_3067 = asUInt(reset) node _T_3068 = eq(_T_3067, UInt<1>(0h0)) when _T_3068 : node _T_3069 = eq(legal_source, UInt<1>(0h0)) when _T_3069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_3070 = asUInt(reset) node _T_3071 = eq(_T_3070, UInt<1>(0h0)) when _T_3071 : node _T_3072 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_3073 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_3074 = asUInt(reset) node _T_3075 = eq(_T_3074, UInt<1>(0h0)) when _T_3075 : node _T_3076 = eq(_T_3073, UInt<1>(0h0)) when _T_3076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_3073, UInt<1>(0h1), "") : assert_90 node _T_3077 = eq(io.in.b.bits.mask, mask_1) node _T_3078 = asUInt(reset) node _T_3079 = eq(_T_3078, UInt<1>(0h0)) when _T_3079 : node _T_3080 = eq(_T_3077, UInt<1>(0h0)) when _T_3080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_3077, UInt<1>(0h1), "") : assert_91 node _T_3081 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3082 = asUInt(reset) node _T_3083 = eq(_T_3082, UInt<1>(0h0)) when _T_3083 : node _T_3084 = eq(_T_3081, UInt<1>(0h0)) when _T_3084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_3081, UInt<1>(0h1), "") : assert_92 node _T_3085 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_3085 : node _T_3086 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3087 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3088 = and(_T_3086, _T_3087) node _T_3089 = or(UInt<1>(0h0), _T_3088) node _T_3090 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3091 = cvt(_T_3090) node _T_3092 = and(_T_3091, asSInt(UInt<17>(0h10000))) node _T_3093 = asSInt(_T_3092) node _T_3094 = eq(_T_3093, asSInt(UInt<1>(0h0))) node _T_3095 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3096 = cvt(_T_3095) node _T_3097 = and(_T_3096, asSInt(UInt<29>(0h10000000))) node _T_3098 = asSInt(_T_3097) node _T_3099 = eq(_T_3098, asSInt(UInt<1>(0h0))) node _T_3100 = or(_T_3094, _T_3099) node _T_3101 = and(_T_3089, _T_3100) node _T_3102 = or(UInt<1>(0h0), _T_3101) node _T_3103 = and(UInt<1>(0h0), _T_3102) node _T_3104 = asUInt(reset) node _T_3105 = eq(_T_3104, UInt<1>(0h0)) when _T_3105 : node _T_3106 = eq(_T_3103, UInt<1>(0h0)) when _T_3106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_3103, UInt<1>(0h1), "") : assert_93 node _T_3107 = asUInt(reset) node _T_3108 = eq(_T_3107, UInt<1>(0h0)) when _T_3108 : node _T_3109 = eq(address_ok, UInt<1>(0h0)) when _T_3109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_3110 = asUInt(reset) node _T_3111 = eq(_T_3110, UInt<1>(0h0)) when _T_3111 : node _T_3112 = eq(legal_source, UInt<1>(0h0)) when _T_3112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_3113 = asUInt(reset) node _T_3114 = eq(_T_3113, UInt<1>(0h0)) when _T_3114 : node _T_3115 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_3116 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3117 = asUInt(reset) node _T_3118 = eq(_T_3117, UInt<1>(0h0)) when _T_3118 : node _T_3119 = eq(_T_3116, UInt<1>(0h0)) when _T_3119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_3116, UInt<1>(0h1), "") : assert_97 node _T_3120 = eq(io.in.b.bits.mask, mask_1) node _T_3121 = asUInt(reset) node _T_3122 = eq(_T_3121, UInt<1>(0h0)) when _T_3122 : node _T_3123 = eq(_T_3120, UInt<1>(0h0)) when _T_3123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_3120, UInt<1>(0h1), "") : assert_98 node _T_3124 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3125 = asUInt(reset) node _T_3126 = eq(_T_3125, UInt<1>(0h0)) when _T_3126 : node _T_3127 = eq(_T_3124, UInt<1>(0h0)) when _T_3127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_3124, UInt<1>(0h1), "") : assert_99 node _T_3128 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_3128 : node _T_3129 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3130 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3131 = and(_T_3129, _T_3130) node _T_3132 = or(UInt<1>(0h0), _T_3131) node _T_3133 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3134 = cvt(_T_3133) node _T_3135 = and(_T_3134, asSInt(UInt<17>(0h10000))) node _T_3136 = asSInt(_T_3135) node _T_3137 = eq(_T_3136, asSInt(UInt<1>(0h0))) node _T_3138 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3139 = cvt(_T_3138) node _T_3140 = and(_T_3139, asSInt(UInt<29>(0h10000000))) node _T_3141 = asSInt(_T_3140) node _T_3142 = eq(_T_3141, asSInt(UInt<1>(0h0))) node _T_3143 = or(_T_3137, _T_3142) node _T_3144 = and(_T_3132, _T_3143) node _T_3145 = or(UInt<1>(0h0), _T_3144) node _T_3146 = and(UInt<1>(0h0), _T_3145) node _T_3147 = asUInt(reset) node _T_3148 = eq(_T_3147, UInt<1>(0h0)) when _T_3148 : node _T_3149 = eq(_T_3146, UInt<1>(0h0)) when _T_3149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_3146, UInt<1>(0h1), "") : assert_100 node _T_3150 = asUInt(reset) node _T_3151 = eq(_T_3150, UInt<1>(0h0)) when _T_3151 : node _T_3152 = eq(address_ok, UInt<1>(0h0)) when _T_3152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_3153 = asUInt(reset) node _T_3154 = eq(_T_3153, UInt<1>(0h0)) when _T_3154 : node _T_3155 = eq(legal_source, UInt<1>(0h0)) when _T_3155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_3156 = asUInt(reset) node _T_3157 = eq(_T_3156, UInt<1>(0h0)) when _T_3157 : node _T_3158 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_3159 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3160 = asUInt(reset) node _T_3161 = eq(_T_3160, UInt<1>(0h0)) when _T_3161 : node _T_3162 = eq(_T_3159, UInt<1>(0h0)) when _T_3162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_3159, UInt<1>(0h1), "") : assert_104 node _T_3163 = eq(io.in.b.bits.mask, mask_1) node _T_3164 = asUInt(reset) node _T_3165 = eq(_T_3164, UInt<1>(0h0)) when _T_3165 : node _T_3166 = eq(_T_3163, UInt<1>(0h0)) when _T_3166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_3163, UInt<1>(0h1), "") : assert_105 node _T_3167 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_3167 : node _T_3168 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3169 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3170 = and(_T_3168, _T_3169) node _T_3171 = or(UInt<1>(0h0), _T_3170) node _T_3172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3173 = cvt(_T_3172) node _T_3174 = and(_T_3173, asSInt(UInt<17>(0h10000))) node _T_3175 = asSInt(_T_3174) node _T_3176 = eq(_T_3175, asSInt(UInt<1>(0h0))) node _T_3177 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3178 = cvt(_T_3177) node _T_3179 = and(_T_3178, asSInt(UInt<29>(0h10000000))) node _T_3180 = asSInt(_T_3179) node _T_3181 = eq(_T_3180, asSInt(UInt<1>(0h0))) node _T_3182 = or(_T_3176, _T_3181) node _T_3183 = and(_T_3171, _T_3182) node _T_3184 = or(UInt<1>(0h0), _T_3183) node _T_3185 = and(UInt<1>(0h0), _T_3184) node _T_3186 = asUInt(reset) node _T_3187 = eq(_T_3186, UInt<1>(0h0)) when _T_3187 : node _T_3188 = eq(_T_3185, UInt<1>(0h0)) when _T_3188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_3185, UInt<1>(0h1), "") : assert_106 node _T_3189 = asUInt(reset) node _T_3190 = eq(_T_3189, UInt<1>(0h0)) when _T_3190 : node _T_3191 = eq(address_ok, UInt<1>(0h0)) when _T_3191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_3192 = asUInt(reset) node _T_3193 = eq(_T_3192, UInt<1>(0h0)) when _T_3193 : node _T_3194 = eq(legal_source, UInt<1>(0h0)) when _T_3194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_3195 = asUInt(reset) node _T_3196 = eq(_T_3195, UInt<1>(0h0)) when _T_3196 : node _T_3197 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_3198 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_3199 = asUInt(reset) node _T_3200 = eq(_T_3199, UInt<1>(0h0)) when _T_3200 : node _T_3201 = eq(_T_3198, UInt<1>(0h0)) when _T_3201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_3198, UInt<1>(0h1), "") : assert_110 node _T_3202 = not(mask_1) node _T_3203 = and(io.in.b.bits.mask, _T_3202) node _T_3204 = eq(_T_3203, UInt<1>(0h0)) node _T_3205 = asUInt(reset) node _T_3206 = eq(_T_3205, UInt<1>(0h0)) when _T_3206 : node _T_3207 = eq(_T_3204, UInt<1>(0h0)) when _T_3207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_3204, UInt<1>(0h1), "") : assert_111 node _T_3208 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_3208 : node _T_3209 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3210 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3211 = and(_T_3209, _T_3210) node _T_3212 = or(UInt<1>(0h0), _T_3211) node _T_3213 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3214 = cvt(_T_3213) node _T_3215 = and(_T_3214, asSInt(UInt<17>(0h10000))) node _T_3216 = asSInt(_T_3215) node _T_3217 = eq(_T_3216, asSInt(UInt<1>(0h0))) node _T_3218 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3219 = cvt(_T_3218) node _T_3220 = and(_T_3219, asSInt(UInt<29>(0h10000000))) node _T_3221 = asSInt(_T_3220) node _T_3222 = eq(_T_3221, asSInt(UInt<1>(0h0))) node _T_3223 = or(_T_3217, _T_3222) node _T_3224 = and(_T_3212, _T_3223) node _T_3225 = or(UInt<1>(0h0), _T_3224) node _T_3226 = and(UInt<1>(0h0), _T_3225) node _T_3227 = asUInt(reset) node _T_3228 = eq(_T_3227, UInt<1>(0h0)) when _T_3228 : node _T_3229 = eq(_T_3226, UInt<1>(0h0)) when _T_3229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_3226, UInt<1>(0h1), "") : assert_112 node _T_3230 = asUInt(reset) node _T_3231 = eq(_T_3230, UInt<1>(0h0)) when _T_3231 : node _T_3232 = eq(address_ok, UInt<1>(0h0)) when _T_3232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_3233 = asUInt(reset) node _T_3234 = eq(_T_3233, UInt<1>(0h0)) when _T_3234 : node _T_3235 = eq(legal_source, UInt<1>(0h0)) when _T_3235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_3236 = asUInt(reset) node _T_3237 = eq(_T_3236, UInt<1>(0h0)) when _T_3237 : node _T_3238 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_3239 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_3240 = asUInt(reset) node _T_3241 = eq(_T_3240, UInt<1>(0h0)) when _T_3241 : node _T_3242 = eq(_T_3239, UInt<1>(0h0)) when _T_3242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_3239, UInt<1>(0h1), "") : assert_116 node _T_3243 = eq(io.in.b.bits.mask, mask_1) node _T_3244 = asUInt(reset) node _T_3245 = eq(_T_3244, UInt<1>(0h0)) when _T_3245 : node _T_3246 = eq(_T_3243, UInt<1>(0h0)) when _T_3246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_3243, UInt<1>(0h1), "") : assert_117 node _T_3247 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_3247 : node _T_3248 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3249 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3250 = and(_T_3248, _T_3249) node _T_3251 = or(UInt<1>(0h0), _T_3250) node _T_3252 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3253 = cvt(_T_3252) node _T_3254 = and(_T_3253, asSInt(UInt<17>(0h10000))) node _T_3255 = asSInt(_T_3254) node _T_3256 = eq(_T_3255, asSInt(UInt<1>(0h0))) node _T_3257 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3258 = cvt(_T_3257) node _T_3259 = and(_T_3258, asSInt(UInt<29>(0h10000000))) node _T_3260 = asSInt(_T_3259) node _T_3261 = eq(_T_3260, asSInt(UInt<1>(0h0))) node _T_3262 = or(_T_3256, _T_3261) node _T_3263 = and(_T_3251, _T_3262) node _T_3264 = or(UInt<1>(0h0), _T_3263) node _T_3265 = and(UInt<1>(0h0), _T_3264) node _T_3266 = asUInt(reset) node _T_3267 = eq(_T_3266, UInt<1>(0h0)) when _T_3267 : node _T_3268 = eq(_T_3265, UInt<1>(0h0)) when _T_3268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_3265, UInt<1>(0h1), "") : assert_118 node _T_3269 = asUInt(reset) node _T_3270 = eq(_T_3269, UInt<1>(0h0)) when _T_3270 : node _T_3271 = eq(address_ok, UInt<1>(0h0)) when _T_3271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_3272 = asUInt(reset) node _T_3273 = eq(_T_3272, UInt<1>(0h0)) when _T_3273 : node _T_3274 = eq(legal_source, UInt<1>(0h0)) when _T_3274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_3275 = asUInt(reset) node _T_3276 = eq(_T_3275, UInt<1>(0h0)) when _T_3276 : node _T_3277 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_3278 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_3279 = asUInt(reset) node _T_3280 = eq(_T_3279, UInt<1>(0h0)) when _T_3280 : node _T_3281 = eq(_T_3278, UInt<1>(0h0)) when _T_3281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_3278, UInt<1>(0h1), "") : assert_122 node _T_3282 = eq(io.in.b.bits.mask, mask_1) node _T_3283 = asUInt(reset) node _T_3284 = eq(_T_3283, UInt<1>(0h0)) when _T_3284 : node _T_3285 = eq(_T_3282, UInt<1>(0h0)) when _T_3285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_3282, UInt<1>(0h1), "") : assert_123 node _T_3286 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_3286 : node _T_3287 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_3288 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_3289 = and(_T_3287, _T_3288) node _T_3290 = or(UInt<1>(0h0), _T_3289) node _T_3291 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_3292 = cvt(_T_3291) node _T_3293 = and(_T_3292, asSInt(UInt<17>(0h10000))) node _T_3294 = asSInt(_T_3293) node _T_3295 = eq(_T_3294, asSInt(UInt<1>(0h0))) node _T_3296 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_3297 = cvt(_T_3296) node _T_3298 = and(_T_3297, asSInt(UInt<29>(0h10000000))) node _T_3299 = asSInt(_T_3298) node _T_3300 = eq(_T_3299, asSInt(UInt<1>(0h0))) node _T_3301 = or(_T_3295, _T_3300) node _T_3302 = and(_T_3290, _T_3301) node _T_3303 = or(UInt<1>(0h0), _T_3302) node _T_3304 = and(UInt<1>(0h0), _T_3303) node _T_3305 = asUInt(reset) node _T_3306 = eq(_T_3305, UInt<1>(0h0)) when _T_3306 : node _T_3307 = eq(_T_3304, UInt<1>(0h0)) when _T_3307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_3304, UInt<1>(0h1), "") : assert_124 node _T_3308 = asUInt(reset) node _T_3309 = eq(_T_3308, UInt<1>(0h0)) when _T_3309 : node _T_3310 = eq(address_ok, UInt<1>(0h0)) when _T_3310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_3311 = asUInt(reset) node _T_3312 = eq(_T_3311, UInt<1>(0h0)) when _T_3312 : node _T_3313 = eq(legal_source, UInt<1>(0h0)) when _T_3313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_3314 = asUInt(reset) node _T_3315 = eq(_T_3314, UInt<1>(0h0)) when _T_3315 : node _T_3316 = eq(is_aligned_1, UInt<1>(0h0)) when _T_3316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_3317 = eq(io.in.b.bits.mask, mask_1) node _T_3318 = asUInt(reset) node _T_3319 = eq(_T_3318, UInt<1>(0h0)) when _T_3319 : node _T_3320 = eq(_T_3317, UInt<1>(0h0)) when _T_3320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_3317, UInt<1>(0h1), "") : assert_128 node _T_3321 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_3322 = asUInt(reset) node _T_3323 = eq(_T_3322, UInt<1>(0h0)) when _T_3323 : node _T_3324 = eq(_T_3321, UInt<1>(0h0)) when _T_3324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_3321, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_3325 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_3326 = asUInt(reset) node _T_3327 = eq(_T_3326, UInt<1>(0h0)) when _T_3327 : node _T_3328 = eq(_T_3325, UInt<1>(0h0)) when _T_3328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_3325, UInt<1>(0h1), "") : assert_130 node _source_ok_T_316 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _source_ok_uncommonBits_T_44 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_44 = bits(_source_ok_uncommonBits_T_44, 1, 0) node _source_ok_T_317 = shr(io.in.c.bits.source, 2) node _source_ok_T_318 = eq(_source_ok_T_317, UInt<7>(0h70)) node _source_ok_T_319 = leq(UInt<1>(0h0), source_ok_uncommonBits_44) node _source_ok_T_320 = and(_source_ok_T_318, _source_ok_T_319) node _source_ok_T_321 = leq(source_ok_uncommonBits_44, UInt<2>(0h3)) node _source_ok_T_322 = and(_source_ok_T_320, _source_ok_T_321) node _source_ok_uncommonBits_T_45 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_45 = bits(_source_ok_uncommonBits_T_45, 1, 0) node _source_ok_T_323 = shr(io.in.c.bits.source, 2) node _source_ok_T_324 = eq(_source_ok_T_323, UInt<7>(0h71)) node _source_ok_T_325 = leq(UInt<1>(0h0), source_ok_uncommonBits_45) node _source_ok_T_326 = and(_source_ok_T_324, _source_ok_T_325) node _source_ok_T_327 = leq(source_ok_uncommonBits_45, UInt<2>(0h3)) node _source_ok_T_328 = and(_source_ok_T_326, _source_ok_T_327) node _source_ok_uncommonBits_T_46 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_46 = bits(_source_ok_uncommonBits_T_46, 1, 0) node _source_ok_T_329 = shr(io.in.c.bits.source, 2) node _source_ok_T_330 = eq(_source_ok_T_329, UInt<7>(0h72)) node _source_ok_T_331 = leq(UInt<1>(0h0), source_ok_uncommonBits_46) node _source_ok_T_332 = and(_source_ok_T_330, _source_ok_T_331) node _source_ok_T_333 = leq(source_ok_uncommonBits_46, UInt<2>(0h3)) node _source_ok_T_334 = and(_source_ok_T_332, _source_ok_T_333) node _source_ok_uncommonBits_T_47 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_47 = bits(_source_ok_uncommonBits_T_47, 1, 0) node _source_ok_T_335 = shr(io.in.c.bits.source, 2) node _source_ok_T_336 = eq(_source_ok_T_335, UInt<7>(0h73)) node _source_ok_T_337 = leq(UInt<1>(0h0), source_ok_uncommonBits_47) node _source_ok_T_338 = and(_source_ok_T_336, _source_ok_T_337) node _source_ok_T_339 = leq(source_ok_uncommonBits_47, UInt<2>(0h3)) node _source_ok_T_340 = and(_source_ok_T_338, _source_ok_T_339) node _source_ok_uncommonBits_T_48 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_48 = bits(_source_ok_uncommonBits_T_48, 1, 0) node _source_ok_T_341 = shr(io.in.c.bits.source, 2) node _source_ok_T_342 = eq(_source_ok_T_341, UInt<7>(0h7c)) node _source_ok_T_343 = leq(UInt<1>(0h0), source_ok_uncommonBits_48) node _source_ok_T_344 = and(_source_ok_T_342, _source_ok_T_343) node _source_ok_T_345 = leq(source_ok_uncommonBits_48, UInt<2>(0h3)) node _source_ok_T_346 = and(_source_ok_T_344, _source_ok_T_345) node _source_ok_uncommonBits_T_49 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_49 = bits(_source_ok_uncommonBits_T_49, 1, 0) node _source_ok_T_347 = shr(io.in.c.bits.source, 2) node _source_ok_T_348 = eq(_source_ok_T_347, UInt<7>(0h7b)) node _source_ok_T_349 = leq(UInt<1>(0h0), source_ok_uncommonBits_49) node _source_ok_T_350 = and(_source_ok_T_348, _source_ok_T_349) node _source_ok_T_351 = leq(source_ok_uncommonBits_49, UInt<2>(0h3)) node _source_ok_T_352 = and(_source_ok_T_350, _source_ok_T_351) node _source_ok_uncommonBits_T_50 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_50 = bits(_source_ok_uncommonBits_T_50, 4, 0) node _source_ok_T_353 = shr(io.in.c.bits.source, 5) node _source_ok_T_354 = eq(_source_ok_T_353, UInt<4>(0hd)) node _source_ok_T_355 = leq(UInt<1>(0h0), source_ok_uncommonBits_50) node _source_ok_T_356 = and(_source_ok_T_354, _source_ok_T_355) node _source_ok_T_357 = leq(source_ok_uncommonBits_50, UInt<5>(0h1f)) node _source_ok_T_358 = and(_source_ok_T_356, _source_ok_T_357) node _source_ok_uncommonBits_T_51 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_51 = bits(_source_ok_uncommonBits_T_51, 4, 0) node _source_ok_T_359 = shr(io.in.c.bits.source, 5) node _source_ok_T_360 = eq(_source_ok_T_359, UInt<4>(0hc)) node _source_ok_T_361 = leq(UInt<1>(0h0), source_ok_uncommonBits_51) node _source_ok_T_362 = and(_source_ok_T_360, _source_ok_T_361) node _source_ok_T_363 = leq(source_ok_uncommonBits_51, UInt<5>(0h1f)) node _source_ok_T_364 = and(_source_ok_T_362, _source_ok_T_363) node _source_ok_uncommonBits_T_52 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_52 = bits(_source_ok_uncommonBits_T_52, 4, 0) node _source_ok_T_365 = shr(io.in.c.bits.source, 5) node _source_ok_T_366 = eq(_source_ok_T_365, UInt<4>(0hb)) node _source_ok_T_367 = leq(UInt<1>(0h0), source_ok_uncommonBits_52) node _source_ok_T_368 = and(_source_ok_T_366, _source_ok_T_367) node _source_ok_T_369 = leq(source_ok_uncommonBits_52, UInt<5>(0h1f)) node _source_ok_T_370 = and(_source_ok_T_368, _source_ok_T_369) node _source_ok_uncommonBits_T_53 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_53 = bits(_source_ok_uncommonBits_T_53, 4, 0) node _source_ok_T_371 = shr(io.in.c.bits.source, 5) node _source_ok_T_372 = eq(_source_ok_T_371, UInt<4>(0ha)) node _source_ok_T_373 = leq(UInt<1>(0h0), source_ok_uncommonBits_53) node _source_ok_T_374 = and(_source_ok_T_372, _source_ok_T_373) node _source_ok_T_375 = leq(source_ok_uncommonBits_53, UInt<5>(0h1f)) node _source_ok_T_376 = and(_source_ok_T_374, _source_ok_T_375) node _source_ok_uncommonBits_T_54 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_54 = bits(_source_ok_uncommonBits_T_54, 4, 0) node _source_ok_T_377 = shr(io.in.c.bits.source, 5) node _source_ok_T_378 = eq(_source_ok_T_377, UInt<4>(0h9)) node _source_ok_T_379 = leq(UInt<1>(0h0), source_ok_uncommonBits_54) node _source_ok_T_380 = and(_source_ok_T_378, _source_ok_T_379) node _source_ok_T_381 = leq(source_ok_uncommonBits_54, UInt<5>(0h1f)) node _source_ok_T_382 = and(_source_ok_T_380, _source_ok_T_381) node _source_ok_uncommonBits_T_55 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_55 = bits(_source_ok_uncommonBits_T_55, 4, 0) node _source_ok_T_383 = shr(io.in.c.bits.source, 5) node _source_ok_T_384 = eq(_source_ok_T_383, UInt<4>(0h8)) node _source_ok_T_385 = leq(UInt<1>(0h0), source_ok_uncommonBits_55) node _source_ok_T_386 = and(_source_ok_T_384, _source_ok_T_385) node _source_ok_T_387 = leq(source_ok_uncommonBits_55, UInt<5>(0h1f)) node _source_ok_T_388 = and(_source_ok_T_386, _source_ok_T_387) node _source_ok_uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_56 = bits(_source_ok_uncommonBits_T_56, 1, 0) node _source_ok_T_389 = shr(io.in.c.bits.source, 2) node _source_ok_T_390 = eq(_source_ok_T_389, UInt<7>(0h7a)) node _source_ok_T_391 = leq(UInt<1>(0h0), source_ok_uncommonBits_56) node _source_ok_T_392 = and(_source_ok_T_390, _source_ok_T_391) node _source_ok_T_393 = leq(source_ok_uncommonBits_56, UInt<2>(0h3)) node _source_ok_T_394 = and(_source_ok_T_392, _source_ok_T_393) node _source_ok_uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_57 = bits(_source_ok_uncommonBits_T_57, 1, 0) node _source_ok_T_395 = shr(io.in.c.bits.source, 2) node _source_ok_T_396 = eq(_source_ok_T_395, UInt<7>(0h79)) node _source_ok_T_397 = leq(UInt<1>(0h0), source_ok_uncommonBits_57) node _source_ok_T_398 = and(_source_ok_T_396, _source_ok_T_397) node _source_ok_T_399 = leq(source_ok_uncommonBits_57, UInt<2>(0h3)) node _source_ok_T_400 = and(_source_ok_T_398, _source_ok_T_399) node _source_ok_uncommonBits_T_58 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_58 = bits(_source_ok_uncommonBits_T_58, 4, 0) node _source_ok_T_401 = shr(io.in.c.bits.source, 5) node _source_ok_T_402 = eq(_source_ok_T_401, UInt<3>(0h7)) node _source_ok_T_403 = leq(UInt<1>(0h0), source_ok_uncommonBits_58) node _source_ok_T_404 = and(_source_ok_T_402, _source_ok_T_403) node _source_ok_T_405 = leq(source_ok_uncommonBits_58, UInt<5>(0h1f)) node _source_ok_T_406 = and(_source_ok_T_404, _source_ok_T_405) node _source_ok_uncommonBits_T_59 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_59 = bits(_source_ok_uncommonBits_T_59, 4, 0) node _source_ok_T_407 = shr(io.in.c.bits.source, 5) node _source_ok_T_408 = eq(_source_ok_T_407, UInt<3>(0h6)) node _source_ok_T_409 = leq(UInt<1>(0h0), source_ok_uncommonBits_59) node _source_ok_T_410 = and(_source_ok_T_408, _source_ok_T_409) node _source_ok_T_411 = leq(source_ok_uncommonBits_59, UInt<5>(0h1f)) node _source_ok_T_412 = and(_source_ok_T_410, _source_ok_T_411) node _source_ok_uncommonBits_T_60 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_60 = bits(_source_ok_uncommonBits_T_60, 4, 0) node _source_ok_T_413 = shr(io.in.c.bits.source, 5) node _source_ok_T_414 = eq(_source_ok_T_413, UInt<3>(0h5)) node _source_ok_T_415 = leq(UInt<1>(0h0), source_ok_uncommonBits_60) node _source_ok_T_416 = and(_source_ok_T_414, _source_ok_T_415) node _source_ok_T_417 = leq(source_ok_uncommonBits_60, UInt<5>(0h1f)) node _source_ok_T_418 = and(_source_ok_T_416, _source_ok_T_417) node _source_ok_uncommonBits_T_61 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_61 = bits(_source_ok_uncommonBits_T_61, 4, 0) node _source_ok_T_419 = shr(io.in.c.bits.source, 5) node _source_ok_T_420 = eq(_source_ok_T_419, UInt<3>(0h4)) node _source_ok_T_421 = leq(UInt<1>(0h0), source_ok_uncommonBits_61) node _source_ok_T_422 = and(_source_ok_T_420, _source_ok_T_421) node _source_ok_T_423 = leq(source_ok_uncommonBits_61, UInt<5>(0h1f)) node _source_ok_T_424 = and(_source_ok_T_422, _source_ok_T_423) node _source_ok_uncommonBits_T_62 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_62 = bits(_source_ok_uncommonBits_T_62, 4, 0) node _source_ok_T_425 = shr(io.in.c.bits.source, 5) node _source_ok_T_426 = eq(_source_ok_T_425, UInt<2>(0h3)) node _source_ok_T_427 = leq(UInt<1>(0h0), source_ok_uncommonBits_62) node _source_ok_T_428 = and(_source_ok_T_426, _source_ok_T_427) node _source_ok_T_429 = leq(source_ok_uncommonBits_62, UInt<5>(0h1f)) node _source_ok_T_430 = and(_source_ok_T_428, _source_ok_T_429) node _source_ok_uncommonBits_T_63 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_63 = bits(_source_ok_uncommonBits_T_63, 4, 0) node _source_ok_T_431 = shr(io.in.c.bits.source, 5) node _source_ok_T_432 = eq(_source_ok_T_431, UInt<2>(0h2)) node _source_ok_T_433 = leq(UInt<1>(0h0), source_ok_uncommonBits_63) node _source_ok_T_434 = and(_source_ok_T_432, _source_ok_T_433) node _source_ok_T_435 = leq(source_ok_uncommonBits_63, UInt<5>(0h1f)) node _source_ok_T_436 = and(_source_ok_T_434, _source_ok_T_435) node _source_ok_uncommonBits_T_64 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_64 = bits(_source_ok_uncommonBits_T_64, 4, 0) node _source_ok_T_437 = shr(io.in.c.bits.source, 5) node _source_ok_T_438 = eq(_source_ok_T_437, UInt<1>(0h1)) node _source_ok_T_439 = leq(UInt<1>(0h0), source_ok_uncommonBits_64) node _source_ok_T_440 = and(_source_ok_T_438, _source_ok_T_439) node _source_ok_T_441 = leq(source_ok_uncommonBits_64, UInt<5>(0h1f)) node _source_ok_T_442 = and(_source_ok_T_440, _source_ok_T_441) node _source_ok_uncommonBits_T_65 = or(io.in.c.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_65 = bits(_source_ok_uncommonBits_T_65, 4, 0) node _source_ok_T_443 = shr(io.in.c.bits.source, 5) node _source_ok_T_444 = eq(_source_ok_T_443, UInt<1>(0h0)) node _source_ok_T_445 = leq(UInt<1>(0h0), source_ok_uncommonBits_65) node _source_ok_T_446 = and(_source_ok_T_444, _source_ok_T_445) node _source_ok_T_447 = leq(source_ok_uncommonBits_65, UInt<5>(0h1f)) node _source_ok_T_448 = and(_source_ok_T_446, _source_ok_T_447) node _source_ok_T_449 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _source_ok_T_450 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _source_ok_WIRE_2 : UInt<1>[25] connect _source_ok_WIRE_2[0], _source_ok_T_316 connect _source_ok_WIRE_2[1], _source_ok_T_322 connect _source_ok_WIRE_2[2], _source_ok_T_328 connect _source_ok_WIRE_2[3], _source_ok_T_334 connect _source_ok_WIRE_2[4], _source_ok_T_340 connect _source_ok_WIRE_2[5], _source_ok_T_346 connect _source_ok_WIRE_2[6], _source_ok_T_352 connect _source_ok_WIRE_2[7], _source_ok_T_358 connect _source_ok_WIRE_2[8], _source_ok_T_364 connect _source_ok_WIRE_2[9], _source_ok_T_370 connect _source_ok_WIRE_2[10], _source_ok_T_376 connect _source_ok_WIRE_2[11], _source_ok_T_382 connect _source_ok_WIRE_2[12], _source_ok_T_388 connect _source_ok_WIRE_2[13], _source_ok_T_394 connect _source_ok_WIRE_2[14], _source_ok_T_400 connect _source_ok_WIRE_2[15], _source_ok_T_406 connect _source_ok_WIRE_2[16], _source_ok_T_412 connect _source_ok_WIRE_2[17], _source_ok_T_418 connect _source_ok_WIRE_2[18], _source_ok_T_424 connect _source_ok_WIRE_2[19], _source_ok_T_430 connect _source_ok_WIRE_2[20], _source_ok_T_436 connect _source_ok_WIRE_2[21], _source_ok_T_442 connect _source_ok_WIRE_2[22], _source_ok_T_448 connect _source_ok_WIRE_2[23], _source_ok_T_449 connect _source_ok_WIRE_2[24], _source_ok_T_450 node _source_ok_T_451 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_452 = or(_source_ok_T_451, _source_ok_WIRE_2[2]) node _source_ok_T_453 = or(_source_ok_T_452, _source_ok_WIRE_2[3]) node _source_ok_T_454 = or(_source_ok_T_453, _source_ok_WIRE_2[4]) node _source_ok_T_455 = or(_source_ok_T_454, _source_ok_WIRE_2[5]) node _source_ok_T_456 = or(_source_ok_T_455, _source_ok_WIRE_2[6]) node _source_ok_T_457 = or(_source_ok_T_456, _source_ok_WIRE_2[7]) node _source_ok_T_458 = or(_source_ok_T_457, _source_ok_WIRE_2[8]) node _source_ok_T_459 = or(_source_ok_T_458, _source_ok_WIRE_2[9]) node _source_ok_T_460 = or(_source_ok_T_459, _source_ok_WIRE_2[10]) node _source_ok_T_461 = or(_source_ok_T_460, _source_ok_WIRE_2[11]) node _source_ok_T_462 = or(_source_ok_T_461, _source_ok_WIRE_2[12]) node _source_ok_T_463 = or(_source_ok_T_462, _source_ok_WIRE_2[13]) node _source_ok_T_464 = or(_source_ok_T_463, _source_ok_WIRE_2[14]) node _source_ok_T_465 = or(_source_ok_T_464, _source_ok_WIRE_2[15]) node _source_ok_T_466 = or(_source_ok_T_465, _source_ok_WIRE_2[16]) node _source_ok_T_467 = or(_source_ok_T_466, _source_ok_WIRE_2[17]) node _source_ok_T_468 = or(_source_ok_T_467, _source_ok_WIRE_2[18]) node _source_ok_T_469 = or(_source_ok_T_468, _source_ok_WIRE_2[19]) node _source_ok_T_470 = or(_source_ok_T_469, _source_ok_WIRE_2[20]) node _source_ok_T_471 = or(_source_ok_T_470, _source_ok_WIRE_2[21]) node _source_ok_T_472 = or(_source_ok_T_471, _source_ok_WIRE_2[22]) node _source_ok_T_473 = or(_source_ok_T_472, _source_ok_WIRE_2[23]) node source_ok_2 = or(_source_ok_T_473, _source_ok_WIRE_2[24]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_3329 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _T_3330 = eq(_T_3329, UInt<1>(0h0)) node _T_3331 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3332 = cvt(_T_3331) node _T_3333 = and(_T_3332, asSInt(UInt<1>(0h0))) node _T_3334 = asSInt(_T_3333) node _T_3335 = eq(_T_3334, asSInt(UInt<1>(0h0))) node _T_3336 = or(_T_3330, _T_3335) node _uncommonBits_T_286 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_286 = bits(_uncommonBits_T_286, 1, 0) node _T_3337 = shr(io.in.c.bits.source, 2) node _T_3338 = eq(_T_3337, UInt<7>(0h70)) node _T_3339 = leq(UInt<1>(0h0), uncommonBits_286) node _T_3340 = and(_T_3338, _T_3339) node _T_3341 = leq(uncommonBits_286, UInt<2>(0h3)) node _T_3342 = and(_T_3340, _T_3341) node _T_3343 = eq(_T_3342, UInt<1>(0h0)) node _T_3344 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3345 = cvt(_T_3344) node _T_3346 = and(_T_3345, asSInt(UInt<1>(0h0))) node _T_3347 = asSInt(_T_3346) node _T_3348 = eq(_T_3347, asSInt(UInt<1>(0h0))) node _T_3349 = or(_T_3343, _T_3348) node _uncommonBits_T_287 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_287 = bits(_uncommonBits_T_287, 1, 0) node _T_3350 = shr(io.in.c.bits.source, 2) node _T_3351 = eq(_T_3350, UInt<7>(0h71)) node _T_3352 = leq(UInt<1>(0h0), uncommonBits_287) node _T_3353 = and(_T_3351, _T_3352) node _T_3354 = leq(uncommonBits_287, UInt<2>(0h3)) node _T_3355 = and(_T_3353, _T_3354) node _T_3356 = eq(_T_3355, UInt<1>(0h0)) node _T_3357 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3358 = cvt(_T_3357) node _T_3359 = and(_T_3358, asSInt(UInt<1>(0h0))) node _T_3360 = asSInt(_T_3359) node _T_3361 = eq(_T_3360, asSInt(UInt<1>(0h0))) node _T_3362 = or(_T_3356, _T_3361) node _uncommonBits_T_288 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_288 = bits(_uncommonBits_T_288, 1, 0) node _T_3363 = shr(io.in.c.bits.source, 2) node _T_3364 = eq(_T_3363, UInt<7>(0h72)) node _T_3365 = leq(UInt<1>(0h0), uncommonBits_288) node _T_3366 = and(_T_3364, _T_3365) node _T_3367 = leq(uncommonBits_288, UInt<2>(0h3)) node _T_3368 = and(_T_3366, _T_3367) node _T_3369 = eq(_T_3368, UInt<1>(0h0)) node _T_3370 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3371 = cvt(_T_3370) node _T_3372 = and(_T_3371, asSInt(UInt<1>(0h0))) node _T_3373 = asSInt(_T_3372) node _T_3374 = eq(_T_3373, asSInt(UInt<1>(0h0))) node _T_3375 = or(_T_3369, _T_3374) node _uncommonBits_T_289 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_289 = bits(_uncommonBits_T_289, 1, 0) node _T_3376 = shr(io.in.c.bits.source, 2) node _T_3377 = eq(_T_3376, UInt<7>(0h73)) node _T_3378 = leq(UInt<1>(0h0), uncommonBits_289) node _T_3379 = and(_T_3377, _T_3378) node _T_3380 = leq(uncommonBits_289, UInt<2>(0h3)) node _T_3381 = and(_T_3379, _T_3380) node _T_3382 = eq(_T_3381, UInt<1>(0h0)) node _T_3383 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3384 = cvt(_T_3383) node _T_3385 = and(_T_3384, asSInt(UInt<1>(0h0))) node _T_3386 = asSInt(_T_3385) node _T_3387 = eq(_T_3386, asSInt(UInt<1>(0h0))) node _T_3388 = or(_T_3382, _T_3387) node _uncommonBits_T_290 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_290 = bits(_uncommonBits_T_290, 1, 0) node _T_3389 = shr(io.in.c.bits.source, 2) node _T_3390 = eq(_T_3389, UInt<7>(0h7c)) node _T_3391 = leq(UInt<1>(0h0), uncommonBits_290) node _T_3392 = and(_T_3390, _T_3391) node _T_3393 = leq(uncommonBits_290, UInt<2>(0h3)) node _T_3394 = and(_T_3392, _T_3393) node _T_3395 = eq(_T_3394, UInt<1>(0h0)) node _T_3396 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3397 = cvt(_T_3396) node _T_3398 = and(_T_3397, asSInt(UInt<1>(0h0))) node _T_3399 = asSInt(_T_3398) node _T_3400 = eq(_T_3399, asSInt(UInt<1>(0h0))) node _T_3401 = or(_T_3395, _T_3400) node _uncommonBits_T_291 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_291 = bits(_uncommonBits_T_291, 1, 0) node _T_3402 = shr(io.in.c.bits.source, 2) node _T_3403 = eq(_T_3402, UInt<7>(0h7b)) node _T_3404 = leq(UInt<1>(0h0), uncommonBits_291) node _T_3405 = and(_T_3403, _T_3404) node _T_3406 = leq(uncommonBits_291, UInt<2>(0h3)) node _T_3407 = and(_T_3405, _T_3406) node _T_3408 = eq(_T_3407, UInt<1>(0h0)) node _T_3409 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3410 = cvt(_T_3409) node _T_3411 = and(_T_3410, asSInt(UInt<1>(0h0))) node _T_3412 = asSInt(_T_3411) node _T_3413 = eq(_T_3412, asSInt(UInt<1>(0h0))) node _T_3414 = or(_T_3408, _T_3413) node _uncommonBits_T_292 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_292 = bits(_uncommonBits_T_292, 4, 0) node _T_3415 = shr(io.in.c.bits.source, 5) node _T_3416 = eq(_T_3415, UInt<4>(0hd)) node _T_3417 = leq(UInt<1>(0h0), uncommonBits_292) node _T_3418 = and(_T_3416, _T_3417) node _T_3419 = leq(uncommonBits_292, UInt<5>(0h1f)) node _T_3420 = and(_T_3418, _T_3419) node _T_3421 = eq(_T_3420, UInt<1>(0h0)) node _T_3422 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3423 = cvt(_T_3422) node _T_3424 = and(_T_3423, asSInt(UInt<1>(0h0))) node _T_3425 = asSInt(_T_3424) node _T_3426 = eq(_T_3425, asSInt(UInt<1>(0h0))) node _T_3427 = or(_T_3421, _T_3426) node _uncommonBits_T_293 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_293 = bits(_uncommonBits_T_293, 4, 0) node _T_3428 = shr(io.in.c.bits.source, 5) node _T_3429 = eq(_T_3428, UInt<4>(0hc)) node _T_3430 = leq(UInt<1>(0h0), uncommonBits_293) node _T_3431 = and(_T_3429, _T_3430) node _T_3432 = leq(uncommonBits_293, UInt<5>(0h1f)) node _T_3433 = and(_T_3431, _T_3432) node _T_3434 = eq(_T_3433, UInt<1>(0h0)) node _T_3435 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3436 = cvt(_T_3435) node _T_3437 = and(_T_3436, asSInt(UInt<1>(0h0))) node _T_3438 = asSInt(_T_3437) node _T_3439 = eq(_T_3438, asSInt(UInt<1>(0h0))) node _T_3440 = or(_T_3434, _T_3439) node _uncommonBits_T_294 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_294 = bits(_uncommonBits_T_294, 4, 0) node _T_3441 = shr(io.in.c.bits.source, 5) node _T_3442 = eq(_T_3441, UInt<4>(0hb)) node _T_3443 = leq(UInt<1>(0h0), uncommonBits_294) node _T_3444 = and(_T_3442, _T_3443) node _T_3445 = leq(uncommonBits_294, UInt<5>(0h1f)) node _T_3446 = and(_T_3444, _T_3445) node _T_3447 = eq(_T_3446, UInt<1>(0h0)) node _T_3448 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3449 = cvt(_T_3448) node _T_3450 = and(_T_3449, asSInt(UInt<1>(0h0))) node _T_3451 = asSInt(_T_3450) node _T_3452 = eq(_T_3451, asSInt(UInt<1>(0h0))) node _T_3453 = or(_T_3447, _T_3452) node _uncommonBits_T_295 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_295 = bits(_uncommonBits_T_295, 4, 0) node _T_3454 = shr(io.in.c.bits.source, 5) node _T_3455 = eq(_T_3454, UInt<4>(0ha)) node _T_3456 = leq(UInt<1>(0h0), uncommonBits_295) node _T_3457 = and(_T_3455, _T_3456) node _T_3458 = leq(uncommonBits_295, UInt<5>(0h1f)) node _T_3459 = and(_T_3457, _T_3458) node _T_3460 = eq(_T_3459, UInt<1>(0h0)) node _T_3461 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3462 = cvt(_T_3461) node _T_3463 = and(_T_3462, asSInt(UInt<1>(0h0))) node _T_3464 = asSInt(_T_3463) node _T_3465 = eq(_T_3464, asSInt(UInt<1>(0h0))) node _T_3466 = or(_T_3460, _T_3465) node _uncommonBits_T_296 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_296 = bits(_uncommonBits_T_296, 4, 0) node _T_3467 = shr(io.in.c.bits.source, 5) node _T_3468 = eq(_T_3467, UInt<4>(0h9)) node _T_3469 = leq(UInt<1>(0h0), uncommonBits_296) node _T_3470 = and(_T_3468, _T_3469) node _T_3471 = leq(uncommonBits_296, UInt<5>(0h1f)) node _T_3472 = and(_T_3470, _T_3471) node _T_3473 = eq(_T_3472, UInt<1>(0h0)) node _T_3474 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3475 = cvt(_T_3474) node _T_3476 = and(_T_3475, asSInt(UInt<1>(0h0))) node _T_3477 = asSInt(_T_3476) node _T_3478 = eq(_T_3477, asSInt(UInt<1>(0h0))) node _T_3479 = or(_T_3473, _T_3478) node _uncommonBits_T_297 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_297 = bits(_uncommonBits_T_297, 4, 0) node _T_3480 = shr(io.in.c.bits.source, 5) node _T_3481 = eq(_T_3480, UInt<4>(0h8)) node _T_3482 = leq(UInt<1>(0h0), uncommonBits_297) node _T_3483 = and(_T_3481, _T_3482) node _T_3484 = leq(uncommonBits_297, UInt<5>(0h1f)) node _T_3485 = and(_T_3483, _T_3484) node _T_3486 = eq(_T_3485, UInt<1>(0h0)) node _T_3487 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3488 = cvt(_T_3487) node _T_3489 = and(_T_3488, asSInt(UInt<1>(0h0))) node _T_3490 = asSInt(_T_3489) node _T_3491 = eq(_T_3490, asSInt(UInt<1>(0h0))) node _T_3492 = or(_T_3486, _T_3491) node _uncommonBits_T_298 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_298 = bits(_uncommonBits_T_298, 1, 0) node _T_3493 = shr(io.in.c.bits.source, 2) node _T_3494 = eq(_T_3493, UInt<7>(0h7a)) node _T_3495 = leq(UInt<1>(0h0), uncommonBits_298) node _T_3496 = and(_T_3494, _T_3495) node _T_3497 = leq(uncommonBits_298, UInt<2>(0h3)) node _T_3498 = and(_T_3496, _T_3497) node _T_3499 = eq(_T_3498, UInt<1>(0h0)) node _T_3500 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3501 = cvt(_T_3500) node _T_3502 = and(_T_3501, asSInt(UInt<1>(0h0))) node _T_3503 = asSInt(_T_3502) node _T_3504 = eq(_T_3503, asSInt(UInt<1>(0h0))) node _T_3505 = or(_T_3499, _T_3504) node _uncommonBits_T_299 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_299 = bits(_uncommonBits_T_299, 1, 0) node _T_3506 = shr(io.in.c.bits.source, 2) node _T_3507 = eq(_T_3506, UInt<7>(0h79)) node _T_3508 = leq(UInt<1>(0h0), uncommonBits_299) node _T_3509 = and(_T_3507, _T_3508) node _T_3510 = leq(uncommonBits_299, UInt<2>(0h3)) node _T_3511 = and(_T_3509, _T_3510) node _T_3512 = eq(_T_3511, UInt<1>(0h0)) node _T_3513 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3514 = cvt(_T_3513) node _T_3515 = and(_T_3514, asSInt(UInt<1>(0h0))) node _T_3516 = asSInt(_T_3515) node _T_3517 = eq(_T_3516, asSInt(UInt<1>(0h0))) node _T_3518 = or(_T_3512, _T_3517) node _uncommonBits_T_300 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_300 = bits(_uncommonBits_T_300, 4, 0) node _T_3519 = shr(io.in.c.bits.source, 5) node _T_3520 = eq(_T_3519, UInt<3>(0h7)) node _T_3521 = leq(UInt<1>(0h0), uncommonBits_300) node _T_3522 = and(_T_3520, _T_3521) node _T_3523 = leq(uncommonBits_300, UInt<5>(0h1f)) node _T_3524 = and(_T_3522, _T_3523) node _T_3525 = eq(_T_3524, UInt<1>(0h0)) node _T_3526 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3527 = cvt(_T_3526) node _T_3528 = and(_T_3527, asSInt(UInt<1>(0h0))) node _T_3529 = asSInt(_T_3528) node _T_3530 = eq(_T_3529, asSInt(UInt<1>(0h0))) node _T_3531 = or(_T_3525, _T_3530) node _uncommonBits_T_301 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_301 = bits(_uncommonBits_T_301, 4, 0) node _T_3532 = shr(io.in.c.bits.source, 5) node _T_3533 = eq(_T_3532, UInt<3>(0h6)) node _T_3534 = leq(UInt<1>(0h0), uncommonBits_301) node _T_3535 = and(_T_3533, _T_3534) node _T_3536 = leq(uncommonBits_301, UInt<5>(0h1f)) node _T_3537 = and(_T_3535, _T_3536) node _T_3538 = eq(_T_3537, UInt<1>(0h0)) node _T_3539 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3540 = cvt(_T_3539) node _T_3541 = and(_T_3540, asSInt(UInt<1>(0h0))) node _T_3542 = asSInt(_T_3541) node _T_3543 = eq(_T_3542, asSInt(UInt<1>(0h0))) node _T_3544 = or(_T_3538, _T_3543) node _uncommonBits_T_302 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_302 = bits(_uncommonBits_T_302, 4, 0) node _T_3545 = shr(io.in.c.bits.source, 5) node _T_3546 = eq(_T_3545, UInt<3>(0h5)) node _T_3547 = leq(UInt<1>(0h0), uncommonBits_302) node _T_3548 = and(_T_3546, _T_3547) node _T_3549 = leq(uncommonBits_302, UInt<5>(0h1f)) node _T_3550 = and(_T_3548, _T_3549) node _T_3551 = eq(_T_3550, UInt<1>(0h0)) node _T_3552 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3553 = cvt(_T_3552) node _T_3554 = and(_T_3553, asSInt(UInt<1>(0h0))) node _T_3555 = asSInt(_T_3554) node _T_3556 = eq(_T_3555, asSInt(UInt<1>(0h0))) node _T_3557 = or(_T_3551, _T_3556) node _uncommonBits_T_303 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_303 = bits(_uncommonBits_T_303, 4, 0) node _T_3558 = shr(io.in.c.bits.source, 5) node _T_3559 = eq(_T_3558, UInt<3>(0h4)) node _T_3560 = leq(UInt<1>(0h0), uncommonBits_303) node _T_3561 = and(_T_3559, _T_3560) node _T_3562 = leq(uncommonBits_303, UInt<5>(0h1f)) node _T_3563 = and(_T_3561, _T_3562) node _T_3564 = eq(_T_3563, UInt<1>(0h0)) node _T_3565 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3566 = cvt(_T_3565) node _T_3567 = and(_T_3566, asSInt(UInt<1>(0h0))) node _T_3568 = asSInt(_T_3567) node _T_3569 = eq(_T_3568, asSInt(UInt<1>(0h0))) node _T_3570 = or(_T_3564, _T_3569) node _uncommonBits_T_304 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_304 = bits(_uncommonBits_T_304, 4, 0) node _T_3571 = shr(io.in.c.bits.source, 5) node _T_3572 = eq(_T_3571, UInt<2>(0h3)) node _T_3573 = leq(UInt<1>(0h0), uncommonBits_304) node _T_3574 = and(_T_3572, _T_3573) node _T_3575 = leq(uncommonBits_304, UInt<5>(0h1f)) node _T_3576 = and(_T_3574, _T_3575) node _T_3577 = eq(_T_3576, UInt<1>(0h0)) node _T_3578 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3579 = cvt(_T_3578) node _T_3580 = and(_T_3579, asSInt(UInt<1>(0h0))) node _T_3581 = asSInt(_T_3580) node _T_3582 = eq(_T_3581, asSInt(UInt<1>(0h0))) node _T_3583 = or(_T_3577, _T_3582) node _uncommonBits_T_305 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_305 = bits(_uncommonBits_T_305, 4, 0) node _T_3584 = shr(io.in.c.bits.source, 5) node _T_3585 = eq(_T_3584, UInt<2>(0h2)) node _T_3586 = leq(UInt<1>(0h0), uncommonBits_305) node _T_3587 = and(_T_3585, _T_3586) node _T_3588 = leq(uncommonBits_305, UInt<5>(0h1f)) node _T_3589 = and(_T_3587, _T_3588) node _T_3590 = eq(_T_3589, UInt<1>(0h0)) node _T_3591 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3592 = cvt(_T_3591) node _T_3593 = and(_T_3592, asSInt(UInt<1>(0h0))) node _T_3594 = asSInt(_T_3593) node _T_3595 = eq(_T_3594, asSInt(UInt<1>(0h0))) node _T_3596 = or(_T_3590, _T_3595) node _uncommonBits_T_306 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_306 = bits(_uncommonBits_T_306, 4, 0) node _T_3597 = shr(io.in.c.bits.source, 5) node _T_3598 = eq(_T_3597, UInt<1>(0h1)) node _T_3599 = leq(UInt<1>(0h0), uncommonBits_306) node _T_3600 = and(_T_3598, _T_3599) node _T_3601 = leq(uncommonBits_306, UInt<5>(0h1f)) node _T_3602 = and(_T_3600, _T_3601) node _T_3603 = eq(_T_3602, UInt<1>(0h0)) node _T_3604 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3605 = cvt(_T_3604) node _T_3606 = and(_T_3605, asSInt(UInt<1>(0h0))) node _T_3607 = asSInt(_T_3606) node _T_3608 = eq(_T_3607, asSInt(UInt<1>(0h0))) node _T_3609 = or(_T_3603, _T_3608) node _uncommonBits_T_307 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_307 = bits(_uncommonBits_T_307, 4, 0) node _T_3610 = shr(io.in.c.bits.source, 5) node _T_3611 = eq(_T_3610, UInt<1>(0h0)) node _T_3612 = leq(UInt<1>(0h0), uncommonBits_307) node _T_3613 = and(_T_3611, _T_3612) node _T_3614 = leq(uncommonBits_307, UInt<5>(0h1f)) node _T_3615 = and(_T_3613, _T_3614) node _T_3616 = eq(_T_3615, UInt<1>(0h0)) node _T_3617 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3618 = cvt(_T_3617) node _T_3619 = and(_T_3618, asSInt(UInt<1>(0h0))) node _T_3620 = asSInt(_T_3619) node _T_3621 = eq(_T_3620, asSInt(UInt<1>(0h0))) node _T_3622 = or(_T_3616, _T_3621) node _T_3623 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_3624 = eq(_T_3623, UInt<1>(0h0)) node _T_3625 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3626 = cvt(_T_3625) node _T_3627 = and(_T_3626, asSInt(UInt<1>(0h0))) node _T_3628 = asSInt(_T_3627) node _T_3629 = eq(_T_3628, asSInt(UInt<1>(0h0))) node _T_3630 = or(_T_3624, _T_3629) node _T_3631 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_3632 = eq(_T_3631, UInt<1>(0h0)) node _T_3633 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_3634 = cvt(_T_3633) node _T_3635 = and(_T_3634, asSInt(UInt<1>(0h0))) node _T_3636 = asSInt(_T_3635) node _T_3637 = eq(_T_3636, asSInt(UInt<1>(0h0))) node _T_3638 = or(_T_3632, _T_3637) node _T_3639 = and(_T_3336, _T_3349) node _T_3640 = and(_T_3639, _T_3362) node _T_3641 = and(_T_3640, _T_3375) node _T_3642 = and(_T_3641, _T_3388) node _T_3643 = and(_T_3642, _T_3401) node _T_3644 = and(_T_3643, _T_3414) node _T_3645 = and(_T_3644, _T_3427) node _T_3646 = and(_T_3645, _T_3440) node _T_3647 = and(_T_3646, _T_3453) node _T_3648 = and(_T_3647, _T_3466) node _T_3649 = and(_T_3648, _T_3479) node _T_3650 = and(_T_3649, _T_3492) node _T_3651 = and(_T_3650, _T_3505) node _T_3652 = and(_T_3651, _T_3518) node _T_3653 = and(_T_3652, _T_3531) node _T_3654 = and(_T_3653, _T_3544) node _T_3655 = and(_T_3654, _T_3557) node _T_3656 = and(_T_3655, _T_3570) node _T_3657 = and(_T_3656, _T_3583) node _T_3658 = and(_T_3657, _T_3596) node _T_3659 = and(_T_3658, _T_3609) node _T_3660 = and(_T_3659, _T_3622) node _T_3661 = and(_T_3660, _T_3630) node _T_3662 = and(_T_3661, _T_3638) node _T_3663 = asUInt(reset) node _T_3664 = eq(_T_3663, UInt<1>(0h0)) when _T_3664 : node _T_3665 = eq(_T_3662, UInt<1>(0h0)) when _T_3665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_3662, UInt<1>(0h1), "") : assert_131 node _T_3666 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_3666 : node _T_3667 = asUInt(reset) node _T_3668 = eq(_T_3667, UInt<1>(0h0)) when _T_3668 : node _T_3669 = eq(address_ok_1, UInt<1>(0h0)) when _T_3669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_3670 = asUInt(reset) node _T_3671 = eq(_T_3670, UInt<1>(0h0)) when _T_3671 : node _T_3672 = eq(source_ok_2, UInt<1>(0h0)) when _T_3672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_3673 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_3674 = asUInt(reset) node _T_3675 = eq(_T_3674, UInt<1>(0h0)) when _T_3675 : node _T_3676 = eq(_T_3673, UInt<1>(0h0)) when _T_3676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_3673, UInt<1>(0h1), "") : assert_134 node _T_3677 = asUInt(reset) node _T_3678 = eq(_T_3677, UInt<1>(0h0)) when _T_3678 : node _T_3679 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_3680 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_3681 = asUInt(reset) node _T_3682 = eq(_T_3681, UInt<1>(0h0)) when _T_3682 : node _T_3683 = eq(_T_3680, UInt<1>(0h0)) when _T_3683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_3680, UInt<1>(0h1), "") : assert_136 node _T_3684 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_3685 = asUInt(reset) node _T_3686 = eq(_T_3685, UInt<1>(0h0)) when _T_3686 : node _T_3687 = eq(_T_3684, UInt<1>(0h0)) when _T_3687 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_3684, UInt<1>(0h1), "") : assert_137 node _T_3688 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_3688 : node _T_3689 = asUInt(reset) node _T_3690 = eq(_T_3689, UInt<1>(0h0)) when _T_3690 : node _T_3691 = eq(address_ok_1, UInt<1>(0h0)) when _T_3691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_3692 = asUInt(reset) node _T_3693 = eq(_T_3692, UInt<1>(0h0)) when _T_3693 : node _T_3694 = eq(source_ok_2, UInt<1>(0h0)) when _T_3694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_3695 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_3696 = asUInt(reset) node _T_3697 = eq(_T_3696, UInt<1>(0h0)) when _T_3697 : node _T_3698 = eq(_T_3695, UInt<1>(0h0)) when _T_3698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_3695, UInt<1>(0h1), "") : assert_140 node _T_3699 = asUInt(reset) node _T_3700 = eq(_T_3699, UInt<1>(0h0)) when _T_3700 : node _T_3701 = eq(is_aligned_2, UInt<1>(0h0)) when _T_3701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_3702 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_3703 = asUInt(reset) node _T_3704 = eq(_T_3703, UInt<1>(0h0)) when _T_3704 : node _T_3705 = eq(_T_3702, UInt<1>(0h0)) when _T_3705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_3702, UInt<1>(0h1), "") : assert_142 node _T_3706 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_3706 : node _T_3707 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_3708 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_3709 = and(_T_3707, _T_3708) node _T_3710 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_308 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_308 = bits(_uncommonBits_T_308, 1, 0) node _T_3711 = shr(io.in.c.bits.source, 2) node _T_3712 = eq(_T_3711, UInt<7>(0h70)) node _T_3713 = leq(UInt<1>(0h0), uncommonBits_308) node _T_3714 = and(_T_3712, _T_3713) node _T_3715 = leq(uncommonBits_308, UInt<2>(0h3)) node _T_3716 = and(_T_3714, _T_3715) node _uncommonBits_T_309 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_309 = bits(_uncommonBits_T_309, 1, 0) node _T_3717 = shr(io.in.c.bits.source, 2) node _T_3718 = eq(_T_3717, UInt<7>(0h71)) node _T_3719 = leq(UInt<1>(0h0), uncommonBits_309) node _T_3720 = and(_T_3718, _T_3719) node _T_3721 = leq(uncommonBits_309, UInt<2>(0h3)) node _T_3722 = and(_T_3720, _T_3721) node _uncommonBits_T_310 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_310 = bits(_uncommonBits_T_310, 1, 0) node _T_3723 = shr(io.in.c.bits.source, 2) node _T_3724 = eq(_T_3723, UInt<7>(0h72)) node _T_3725 = leq(UInt<1>(0h0), uncommonBits_310) node _T_3726 = and(_T_3724, _T_3725) node _T_3727 = leq(uncommonBits_310, UInt<2>(0h3)) node _T_3728 = and(_T_3726, _T_3727) node _uncommonBits_T_311 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_311 = bits(_uncommonBits_T_311, 1, 0) node _T_3729 = shr(io.in.c.bits.source, 2) node _T_3730 = eq(_T_3729, UInt<7>(0h73)) node _T_3731 = leq(UInt<1>(0h0), uncommonBits_311) node _T_3732 = and(_T_3730, _T_3731) node _T_3733 = leq(uncommonBits_311, UInt<2>(0h3)) node _T_3734 = and(_T_3732, _T_3733) node _uncommonBits_T_312 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_312 = bits(_uncommonBits_T_312, 1, 0) node _T_3735 = shr(io.in.c.bits.source, 2) node _T_3736 = eq(_T_3735, UInt<7>(0h7c)) node _T_3737 = leq(UInt<1>(0h0), uncommonBits_312) node _T_3738 = and(_T_3736, _T_3737) node _T_3739 = leq(uncommonBits_312, UInt<2>(0h3)) node _T_3740 = and(_T_3738, _T_3739) node _uncommonBits_T_313 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_313 = bits(_uncommonBits_T_313, 1, 0) node _T_3741 = shr(io.in.c.bits.source, 2) node _T_3742 = eq(_T_3741, UInt<7>(0h7b)) node _T_3743 = leq(UInt<1>(0h0), uncommonBits_313) node _T_3744 = and(_T_3742, _T_3743) node _T_3745 = leq(uncommonBits_313, UInt<2>(0h3)) node _T_3746 = and(_T_3744, _T_3745) node _uncommonBits_T_314 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_314 = bits(_uncommonBits_T_314, 4, 0) node _T_3747 = shr(io.in.c.bits.source, 5) node _T_3748 = eq(_T_3747, UInt<4>(0hd)) node _T_3749 = leq(UInt<1>(0h0), uncommonBits_314) node _T_3750 = and(_T_3748, _T_3749) node _T_3751 = leq(uncommonBits_314, UInt<5>(0h1f)) node _T_3752 = and(_T_3750, _T_3751) node _uncommonBits_T_315 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_315 = bits(_uncommonBits_T_315, 4, 0) node _T_3753 = shr(io.in.c.bits.source, 5) node _T_3754 = eq(_T_3753, UInt<4>(0hc)) node _T_3755 = leq(UInt<1>(0h0), uncommonBits_315) node _T_3756 = and(_T_3754, _T_3755) node _T_3757 = leq(uncommonBits_315, UInt<5>(0h1f)) node _T_3758 = and(_T_3756, _T_3757) node _uncommonBits_T_316 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_316 = bits(_uncommonBits_T_316, 4, 0) node _T_3759 = shr(io.in.c.bits.source, 5) node _T_3760 = eq(_T_3759, UInt<4>(0hb)) node _T_3761 = leq(UInt<1>(0h0), uncommonBits_316) node _T_3762 = and(_T_3760, _T_3761) node _T_3763 = leq(uncommonBits_316, UInt<5>(0h1f)) node _T_3764 = and(_T_3762, _T_3763) node _uncommonBits_T_317 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_317 = bits(_uncommonBits_T_317, 4, 0) node _T_3765 = shr(io.in.c.bits.source, 5) node _T_3766 = eq(_T_3765, UInt<4>(0ha)) node _T_3767 = leq(UInt<1>(0h0), uncommonBits_317) node _T_3768 = and(_T_3766, _T_3767) node _T_3769 = leq(uncommonBits_317, UInt<5>(0h1f)) node _T_3770 = and(_T_3768, _T_3769) node _uncommonBits_T_318 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_318 = bits(_uncommonBits_T_318, 4, 0) node _T_3771 = shr(io.in.c.bits.source, 5) node _T_3772 = eq(_T_3771, UInt<4>(0h9)) node _T_3773 = leq(UInt<1>(0h0), uncommonBits_318) node _T_3774 = and(_T_3772, _T_3773) node _T_3775 = leq(uncommonBits_318, UInt<5>(0h1f)) node _T_3776 = and(_T_3774, _T_3775) node _uncommonBits_T_319 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_319 = bits(_uncommonBits_T_319, 4, 0) node _T_3777 = shr(io.in.c.bits.source, 5) node _T_3778 = eq(_T_3777, UInt<4>(0h8)) node _T_3779 = leq(UInt<1>(0h0), uncommonBits_319) node _T_3780 = and(_T_3778, _T_3779) node _T_3781 = leq(uncommonBits_319, UInt<5>(0h1f)) node _T_3782 = and(_T_3780, _T_3781) node _uncommonBits_T_320 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_320 = bits(_uncommonBits_T_320, 1, 0) node _T_3783 = shr(io.in.c.bits.source, 2) node _T_3784 = eq(_T_3783, UInt<7>(0h7a)) node _T_3785 = leq(UInt<1>(0h0), uncommonBits_320) node _T_3786 = and(_T_3784, _T_3785) node _T_3787 = leq(uncommonBits_320, UInt<2>(0h3)) node _T_3788 = and(_T_3786, _T_3787) node _uncommonBits_T_321 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_321 = bits(_uncommonBits_T_321, 1, 0) node _T_3789 = shr(io.in.c.bits.source, 2) node _T_3790 = eq(_T_3789, UInt<7>(0h79)) node _T_3791 = leq(UInt<1>(0h0), uncommonBits_321) node _T_3792 = and(_T_3790, _T_3791) node _T_3793 = leq(uncommonBits_321, UInt<2>(0h3)) node _T_3794 = and(_T_3792, _T_3793) node _uncommonBits_T_322 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_322 = bits(_uncommonBits_T_322, 4, 0) node _T_3795 = shr(io.in.c.bits.source, 5) node _T_3796 = eq(_T_3795, UInt<3>(0h7)) node _T_3797 = leq(UInt<1>(0h0), uncommonBits_322) node _T_3798 = and(_T_3796, _T_3797) node _T_3799 = leq(uncommonBits_322, UInt<5>(0h1f)) node _T_3800 = and(_T_3798, _T_3799) node _uncommonBits_T_323 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_323 = bits(_uncommonBits_T_323, 4, 0) node _T_3801 = shr(io.in.c.bits.source, 5) node _T_3802 = eq(_T_3801, UInt<3>(0h6)) node _T_3803 = leq(UInt<1>(0h0), uncommonBits_323) node _T_3804 = and(_T_3802, _T_3803) node _T_3805 = leq(uncommonBits_323, UInt<5>(0h1f)) node _T_3806 = and(_T_3804, _T_3805) node _uncommonBits_T_324 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_324 = bits(_uncommonBits_T_324, 4, 0) node _T_3807 = shr(io.in.c.bits.source, 5) node _T_3808 = eq(_T_3807, UInt<3>(0h5)) node _T_3809 = leq(UInt<1>(0h0), uncommonBits_324) node _T_3810 = and(_T_3808, _T_3809) node _T_3811 = leq(uncommonBits_324, UInt<5>(0h1f)) node _T_3812 = and(_T_3810, _T_3811) node _uncommonBits_T_325 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_325 = bits(_uncommonBits_T_325, 4, 0) node _T_3813 = shr(io.in.c.bits.source, 5) node _T_3814 = eq(_T_3813, UInt<3>(0h4)) node _T_3815 = leq(UInt<1>(0h0), uncommonBits_325) node _T_3816 = and(_T_3814, _T_3815) node _T_3817 = leq(uncommonBits_325, UInt<5>(0h1f)) node _T_3818 = and(_T_3816, _T_3817) node _uncommonBits_T_326 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_326 = bits(_uncommonBits_T_326, 4, 0) node _T_3819 = shr(io.in.c.bits.source, 5) node _T_3820 = eq(_T_3819, UInt<2>(0h3)) node _T_3821 = leq(UInt<1>(0h0), uncommonBits_326) node _T_3822 = and(_T_3820, _T_3821) node _T_3823 = leq(uncommonBits_326, UInt<5>(0h1f)) node _T_3824 = and(_T_3822, _T_3823) node _uncommonBits_T_327 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_327 = bits(_uncommonBits_T_327, 4, 0) node _T_3825 = shr(io.in.c.bits.source, 5) node _T_3826 = eq(_T_3825, UInt<2>(0h2)) node _T_3827 = leq(UInt<1>(0h0), uncommonBits_327) node _T_3828 = and(_T_3826, _T_3827) node _T_3829 = leq(uncommonBits_327, UInt<5>(0h1f)) node _T_3830 = and(_T_3828, _T_3829) node _uncommonBits_T_328 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_328 = bits(_uncommonBits_T_328, 4, 0) node _T_3831 = shr(io.in.c.bits.source, 5) node _T_3832 = eq(_T_3831, UInt<1>(0h1)) node _T_3833 = leq(UInt<1>(0h0), uncommonBits_328) node _T_3834 = and(_T_3832, _T_3833) node _T_3835 = leq(uncommonBits_328, UInt<5>(0h1f)) node _T_3836 = and(_T_3834, _T_3835) node _uncommonBits_T_329 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_329 = bits(_uncommonBits_T_329, 4, 0) node _T_3837 = shr(io.in.c.bits.source, 5) node _T_3838 = eq(_T_3837, UInt<1>(0h0)) node _T_3839 = leq(UInt<1>(0h0), uncommonBits_329) node _T_3840 = and(_T_3838, _T_3839) node _T_3841 = leq(uncommonBits_329, UInt<5>(0h1f)) node _T_3842 = and(_T_3840, _T_3841) node _T_3843 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_3844 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_3845 = or(_T_3710, _T_3716) node _T_3846 = or(_T_3845, _T_3722) node _T_3847 = or(_T_3846, _T_3728) node _T_3848 = or(_T_3847, _T_3734) node _T_3849 = or(_T_3848, _T_3740) node _T_3850 = or(_T_3849, _T_3746) node _T_3851 = or(_T_3850, _T_3752) node _T_3852 = or(_T_3851, _T_3758) node _T_3853 = or(_T_3852, _T_3764) node _T_3854 = or(_T_3853, _T_3770) node _T_3855 = or(_T_3854, _T_3776) node _T_3856 = or(_T_3855, _T_3782) node _T_3857 = or(_T_3856, _T_3788) node _T_3858 = or(_T_3857, _T_3794) node _T_3859 = or(_T_3858, _T_3800) node _T_3860 = or(_T_3859, _T_3806) node _T_3861 = or(_T_3860, _T_3812) node _T_3862 = or(_T_3861, _T_3818) node _T_3863 = or(_T_3862, _T_3824) node _T_3864 = or(_T_3863, _T_3830) node _T_3865 = or(_T_3864, _T_3836) node _T_3866 = or(_T_3865, _T_3842) node _T_3867 = or(_T_3866, _T_3843) node _T_3868 = or(_T_3867, _T_3844) node _T_3869 = and(_T_3709, _T_3868) node _T_3870 = or(UInt<1>(0h0), _T_3869) node _T_3871 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_3872 = or(UInt<1>(0h0), _T_3871) node _T_3873 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_3874 = cvt(_T_3873) node _T_3875 = and(_T_3874, asSInt(UInt<17>(0h10000))) node _T_3876 = asSInt(_T_3875) node _T_3877 = eq(_T_3876, asSInt(UInt<1>(0h0))) node _T_3878 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_3879 = cvt(_T_3878) node _T_3880 = and(_T_3879, asSInt(UInt<29>(0h10000000))) node _T_3881 = asSInt(_T_3880) node _T_3882 = eq(_T_3881, asSInt(UInt<1>(0h0))) node _T_3883 = or(_T_3877, _T_3882) node _T_3884 = and(_T_3872, _T_3883) node _T_3885 = or(UInt<1>(0h0), _T_3884) node _T_3886 = and(_T_3870, _T_3885) node _T_3887 = asUInt(reset) node _T_3888 = eq(_T_3887, UInt<1>(0h0)) when _T_3888 : node _T_3889 = eq(_T_3886, UInt<1>(0h0)) when _T_3889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_3886, UInt<1>(0h1), "") : assert_143 node _T_3890 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_330 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_330 = bits(_uncommonBits_T_330, 1, 0) node _T_3891 = shr(io.in.c.bits.source, 2) node _T_3892 = eq(_T_3891, UInt<7>(0h70)) node _T_3893 = leq(UInt<1>(0h0), uncommonBits_330) node _T_3894 = and(_T_3892, _T_3893) node _T_3895 = leq(uncommonBits_330, UInt<2>(0h3)) node _T_3896 = and(_T_3894, _T_3895) node _uncommonBits_T_331 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_331 = bits(_uncommonBits_T_331, 1, 0) node _T_3897 = shr(io.in.c.bits.source, 2) node _T_3898 = eq(_T_3897, UInt<7>(0h71)) node _T_3899 = leq(UInt<1>(0h0), uncommonBits_331) node _T_3900 = and(_T_3898, _T_3899) node _T_3901 = leq(uncommonBits_331, UInt<2>(0h3)) node _T_3902 = and(_T_3900, _T_3901) node _uncommonBits_T_332 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_332 = bits(_uncommonBits_T_332, 1, 0) node _T_3903 = shr(io.in.c.bits.source, 2) node _T_3904 = eq(_T_3903, UInt<7>(0h72)) node _T_3905 = leq(UInt<1>(0h0), uncommonBits_332) node _T_3906 = and(_T_3904, _T_3905) node _T_3907 = leq(uncommonBits_332, UInt<2>(0h3)) node _T_3908 = and(_T_3906, _T_3907) node _uncommonBits_T_333 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_333 = bits(_uncommonBits_T_333, 1, 0) node _T_3909 = shr(io.in.c.bits.source, 2) node _T_3910 = eq(_T_3909, UInt<7>(0h73)) node _T_3911 = leq(UInt<1>(0h0), uncommonBits_333) node _T_3912 = and(_T_3910, _T_3911) node _T_3913 = leq(uncommonBits_333, UInt<2>(0h3)) node _T_3914 = and(_T_3912, _T_3913) node _uncommonBits_T_334 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_334 = bits(_uncommonBits_T_334, 1, 0) node _T_3915 = shr(io.in.c.bits.source, 2) node _T_3916 = eq(_T_3915, UInt<7>(0h7c)) node _T_3917 = leq(UInt<1>(0h0), uncommonBits_334) node _T_3918 = and(_T_3916, _T_3917) node _T_3919 = leq(uncommonBits_334, UInt<2>(0h3)) node _T_3920 = and(_T_3918, _T_3919) node _uncommonBits_T_335 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_335 = bits(_uncommonBits_T_335, 1, 0) node _T_3921 = shr(io.in.c.bits.source, 2) node _T_3922 = eq(_T_3921, UInt<7>(0h7b)) node _T_3923 = leq(UInt<1>(0h0), uncommonBits_335) node _T_3924 = and(_T_3922, _T_3923) node _T_3925 = leq(uncommonBits_335, UInt<2>(0h3)) node _T_3926 = and(_T_3924, _T_3925) node _uncommonBits_T_336 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_336 = bits(_uncommonBits_T_336, 4, 0) node _T_3927 = shr(io.in.c.bits.source, 5) node _T_3928 = eq(_T_3927, UInt<4>(0hd)) node _T_3929 = leq(UInt<1>(0h0), uncommonBits_336) node _T_3930 = and(_T_3928, _T_3929) node _T_3931 = leq(uncommonBits_336, UInt<5>(0h1f)) node _T_3932 = and(_T_3930, _T_3931) node _uncommonBits_T_337 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_337 = bits(_uncommonBits_T_337, 4, 0) node _T_3933 = shr(io.in.c.bits.source, 5) node _T_3934 = eq(_T_3933, UInt<4>(0hc)) node _T_3935 = leq(UInt<1>(0h0), uncommonBits_337) node _T_3936 = and(_T_3934, _T_3935) node _T_3937 = leq(uncommonBits_337, UInt<5>(0h1f)) node _T_3938 = and(_T_3936, _T_3937) node _uncommonBits_T_338 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_338 = bits(_uncommonBits_T_338, 4, 0) node _T_3939 = shr(io.in.c.bits.source, 5) node _T_3940 = eq(_T_3939, UInt<4>(0hb)) node _T_3941 = leq(UInt<1>(0h0), uncommonBits_338) node _T_3942 = and(_T_3940, _T_3941) node _T_3943 = leq(uncommonBits_338, UInt<5>(0h1f)) node _T_3944 = and(_T_3942, _T_3943) node _uncommonBits_T_339 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_339 = bits(_uncommonBits_T_339, 4, 0) node _T_3945 = shr(io.in.c.bits.source, 5) node _T_3946 = eq(_T_3945, UInt<4>(0ha)) node _T_3947 = leq(UInt<1>(0h0), uncommonBits_339) node _T_3948 = and(_T_3946, _T_3947) node _T_3949 = leq(uncommonBits_339, UInt<5>(0h1f)) node _T_3950 = and(_T_3948, _T_3949) node _uncommonBits_T_340 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_340 = bits(_uncommonBits_T_340, 4, 0) node _T_3951 = shr(io.in.c.bits.source, 5) node _T_3952 = eq(_T_3951, UInt<4>(0h9)) node _T_3953 = leq(UInt<1>(0h0), uncommonBits_340) node _T_3954 = and(_T_3952, _T_3953) node _T_3955 = leq(uncommonBits_340, UInt<5>(0h1f)) node _T_3956 = and(_T_3954, _T_3955) node _uncommonBits_T_341 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_341 = bits(_uncommonBits_T_341, 4, 0) node _T_3957 = shr(io.in.c.bits.source, 5) node _T_3958 = eq(_T_3957, UInt<4>(0h8)) node _T_3959 = leq(UInt<1>(0h0), uncommonBits_341) node _T_3960 = and(_T_3958, _T_3959) node _T_3961 = leq(uncommonBits_341, UInt<5>(0h1f)) node _T_3962 = and(_T_3960, _T_3961) node _uncommonBits_T_342 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_342 = bits(_uncommonBits_T_342, 1, 0) node _T_3963 = shr(io.in.c.bits.source, 2) node _T_3964 = eq(_T_3963, UInt<7>(0h7a)) node _T_3965 = leq(UInt<1>(0h0), uncommonBits_342) node _T_3966 = and(_T_3964, _T_3965) node _T_3967 = leq(uncommonBits_342, UInt<2>(0h3)) node _T_3968 = and(_T_3966, _T_3967) node _uncommonBits_T_343 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_343 = bits(_uncommonBits_T_343, 1, 0) node _T_3969 = shr(io.in.c.bits.source, 2) node _T_3970 = eq(_T_3969, UInt<7>(0h79)) node _T_3971 = leq(UInt<1>(0h0), uncommonBits_343) node _T_3972 = and(_T_3970, _T_3971) node _T_3973 = leq(uncommonBits_343, UInt<2>(0h3)) node _T_3974 = and(_T_3972, _T_3973) node _uncommonBits_T_344 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_344 = bits(_uncommonBits_T_344, 4, 0) node _T_3975 = shr(io.in.c.bits.source, 5) node _T_3976 = eq(_T_3975, UInt<3>(0h7)) node _T_3977 = leq(UInt<1>(0h0), uncommonBits_344) node _T_3978 = and(_T_3976, _T_3977) node _T_3979 = leq(uncommonBits_344, UInt<5>(0h1f)) node _T_3980 = and(_T_3978, _T_3979) node _uncommonBits_T_345 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_345 = bits(_uncommonBits_T_345, 4, 0) node _T_3981 = shr(io.in.c.bits.source, 5) node _T_3982 = eq(_T_3981, UInt<3>(0h6)) node _T_3983 = leq(UInt<1>(0h0), uncommonBits_345) node _T_3984 = and(_T_3982, _T_3983) node _T_3985 = leq(uncommonBits_345, UInt<5>(0h1f)) node _T_3986 = and(_T_3984, _T_3985) node _uncommonBits_T_346 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_346 = bits(_uncommonBits_T_346, 4, 0) node _T_3987 = shr(io.in.c.bits.source, 5) node _T_3988 = eq(_T_3987, UInt<3>(0h5)) node _T_3989 = leq(UInt<1>(0h0), uncommonBits_346) node _T_3990 = and(_T_3988, _T_3989) node _T_3991 = leq(uncommonBits_346, UInt<5>(0h1f)) node _T_3992 = and(_T_3990, _T_3991) node _uncommonBits_T_347 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_347 = bits(_uncommonBits_T_347, 4, 0) node _T_3993 = shr(io.in.c.bits.source, 5) node _T_3994 = eq(_T_3993, UInt<3>(0h4)) node _T_3995 = leq(UInt<1>(0h0), uncommonBits_347) node _T_3996 = and(_T_3994, _T_3995) node _T_3997 = leq(uncommonBits_347, UInt<5>(0h1f)) node _T_3998 = and(_T_3996, _T_3997) node _uncommonBits_T_348 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_348 = bits(_uncommonBits_T_348, 4, 0) node _T_3999 = shr(io.in.c.bits.source, 5) node _T_4000 = eq(_T_3999, UInt<2>(0h3)) node _T_4001 = leq(UInt<1>(0h0), uncommonBits_348) node _T_4002 = and(_T_4000, _T_4001) node _T_4003 = leq(uncommonBits_348, UInt<5>(0h1f)) node _T_4004 = and(_T_4002, _T_4003) node _uncommonBits_T_349 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_349 = bits(_uncommonBits_T_349, 4, 0) node _T_4005 = shr(io.in.c.bits.source, 5) node _T_4006 = eq(_T_4005, UInt<2>(0h2)) node _T_4007 = leq(UInt<1>(0h0), uncommonBits_349) node _T_4008 = and(_T_4006, _T_4007) node _T_4009 = leq(uncommonBits_349, UInt<5>(0h1f)) node _T_4010 = and(_T_4008, _T_4009) node _uncommonBits_T_350 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_350 = bits(_uncommonBits_T_350, 4, 0) node _T_4011 = shr(io.in.c.bits.source, 5) node _T_4012 = eq(_T_4011, UInt<1>(0h1)) node _T_4013 = leq(UInt<1>(0h0), uncommonBits_350) node _T_4014 = and(_T_4012, _T_4013) node _T_4015 = leq(uncommonBits_350, UInt<5>(0h1f)) node _T_4016 = and(_T_4014, _T_4015) node _uncommonBits_T_351 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_351 = bits(_uncommonBits_T_351, 4, 0) node _T_4017 = shr(io.in.c.bits.source, 5) node _T_4018 = eq(_T_4017, UInt<1>(0h0)) node _T_4019 = leq(UInt<1>(0h0), uncommonBits_351) node _T_4020 = and(_T_4018, _T_4019) node _T_4021 = leq(uncommonBits_351, UInt<5>(0h1f)) node _T_4022 = and(_T_4020, _T_4021) node _T_4023 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4024 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _WIRE_6 : UInt<1>[25] connect _WIRE_6[0], _T_3890 connect _WIRE_6[1], _T_3896 connect _WIRE_6[2], _T_3902 connect _WIRE_6[3], _T_3908 connect _WIRE_6[4], _T_3914 connect _WIRE_6[5], _T_3920 connect _WIRE_6[6], _T_3926 connect _WIRE_6[7], _T_3932 connect _WIRE_6[8], _T_3938 connect _WIRE_6[9], _T_3944 connect _WIRE_6[10], _T_3950 connect _WIRE_6[11], _T_3956 connect _WIRE_6[12], _T_3962 connect _WIRE_6[13], _T_3968 connect _WIRE_6[14], _T_3974 connect _WIRE_6[15], _T_3980 connect _WIRE_6[16], _T_3986 connect _WIRE_6[17], _T_3992 connect _WIRE_6[18], _T_3998 connect _WIRE_6[19], _T_4004 connect _WIRE_6[20], _T_4010 connect _WIRE_6[21], _T_4016 connect _WIRE_6[22], _T_4022 connect _WIRE_6[23], _T_4023 connect _WIRE_6[24], _T_4024 node _T_4025 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4026 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_4027 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_4028 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_4029 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_4030 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_4031 = mux(_WIRE_6[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_4032 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_4033 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_4034 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_4035 = mux(_WIRE_6[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_4036 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_4037 = mux(_WIRE_6[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_4038 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_4039 = mux(_WIRE_6[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_4040 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_4041 = mux(_WIRE_6[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_4042 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_4043 = mux(_WIRE_6[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_4044 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_4045 = mux(_WIRE_6[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_4046 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_4047 = mux(_WIRE_6[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_4048 = mux(_WIRE_6[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_4049 = mux(_WIRE_6[23], _T_4025, UInt<1>(0h0)) node _T_4050 = mux(_WIRE_6[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_4051 = or(_T_4026, _T_4027) node _T_4052 = or(_T_4051, _T_4028) node _T_4053 = or(_T_4052, _T_4029) node _T_4054 = or(_T_4053, _T_4030) node _T_4055 = or(_T_4054, _T_4031) node _T_4056 = or(_T_4055, _T_4032) node _T_4057 = or(_T_4056, _T_4033) node _T_4058 = or(_T_4057, _T_4034) node _T_4059 = or(_T_4058, _T_4035) node _T_4060 = or(_T_4059, _T_4036) node _T_4061 = or(_T_4060, _T_4037) node _T_4062 = or(_T_4061, _T_4038) node _T_4063 = or(_T_4062, _T_4039) node _T_4064 = or(_T_4063, _T_4040) node _T_4065 = or(_T_4064, _T_4041) node _T_4066 = or(_T_4065, _T_4042) node _T_4067 = or(_T_4066, _T_4043) node _T_4068 = or(_T_4067, _T_4044) node _T_4069 = or(_T_4068, _T_4045) node _T_4070 = or(_T_4069, _T_4046) node _T_4071 = or(_T_4070, _T_4047) node _T_4072 = or(_T_4071, _T_4048) node _T_4073 = or(_T_4072, _T_4049) node _T_4074 = or(_T_4073, _T_4050) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_4074 node _T_4075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4077 = and(_T_4075, _T_4076) node _T_4078 = or(UInt<1>(0h0), _T_4077) node _T_4079 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4080 = cvt(_T_4079) node _T_4081 = and(_T_4080, asSInt(UInt<17>(0h10000))) node _T_4082 = asSInt(_T_4081) node _T_4083 = eq(_T_4082, asSInt(UInt<1>(0h0))) node _T_4084 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4085 = cvt(_T_4084) node _T_4086 = and(_T_4085, asSInt(UInt<29>(0h10000000))) node _T_4087 = asSInt(_T_4086) node _T_4088 = eq(_T_4087, asSInt(UInt<1>(0h0))) node _T_4089 = or(_T_4083, _T_4088) node _T_4090 = and(_T_4078, _T_4089) node _T_4091 = or(UInt<1>(0h0), _T_4090) node _T_4092 = and(_WIRE_7, _T_4091) node _T_4093 = asUInt(reset) node _T_4094 = eq(_T_4093, UInt<1>(0h0)) when _T_4094 : node _T_4095 = eq(_T_4092, UInt<1>(0h0)) when _T_4095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_4092, UInt<1>(0h1), "") : assert_144 node _T_4096 = asUInt(reset) node _T_4097 = eq(_T_4096, UInt<1>(0h0)) when _T_4097 : node _T_4098 = eq(source_ok_2, UInt<1>(0h0)) when _T_4098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_4099 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_4100 = asUInt(reset) node _T_4101 = eq(_T_4100, UInt<1>(0h0)) when _T_4101 : node _T_4102 = eq(_T_4099, UInt<1>(0h0)) when _T_4102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_4099, UInt<1>(0h1), "") : assert_146 node _T_4103 = asUInt(reset) node _T_4104 = eq(_T_4103, UInt<1>(0h0)) when _T_4104 : node _T_4105 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_4106 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_4107 = asUInt(reset) node _T_4108 = eq(_T_4107, UInt<1>(0h0)) when _T_4108 : node _T_4109 = eq(_T_4106, UInt<1>(0h0)) when _T_4109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_4106, UInt<1>(0h1), "") : assert_148 node _T_4110 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4111 = asUInt(reset) node _T_4112 = eq(_T_4111, UInt<1>(0h0)) when _T_4112 : node _T_4113 = eq(_T_4110, UInt<1>(0h0)) when _T_4113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_4110, UInt<1>(0h1), "") : assert_149 node _T_4114 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_4114 : node _T_4115 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4116 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4117 = and(_T_4115, _T_4116) node _T_4118 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_352 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_352 = bits(_uncommonBits_T_352, 1, 0) node _T_4119 = shr(io.in.c.bits.source, 2) node _T_4120 = eq(_T_4119, UInt<7>(0h70)) node _T_4121 = leq(UInt<1>(0h0), uncommonBits_352) node _T_4122 = and(_T_4120, _T_4121) node _T_4123 = leq(uncommonBits_352, UInt<2>(0h3)) node _T_4124 = and(_T_4122, _T_4123) node _uncommonBits_T_353 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_353 = bits(_uncommonBits_T_353, 1, 0) node _T_4125 = shr(io.in.c.bits.source, 2) node _T_4126 = eq(_T_4125, UInt<7>(0h71)) node _T_4127 = leq(UInt<1>(0h0), uncommonBits_353) node _T_4128 = and(_T_4126, _T_4127) node _T_4129 = leq(uncommonBits_353, UInt<2>(0h3)) node _T_4130 = and(_T_4128, _T_4129) node _uncommonBits_T_354 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_354 = bits(_uncommonBits_T_354, 1, 0) node _T_4131 = shr(io.in.c.bits.source, 2) node _T_4132 = eq(_T_4131, UInt<7>(0h72)) node _T_4133 = leq(UInt<1>(0h0), uncommonBits_354) node _T_4134 = and(_T_4132, _T_4133) node _T_4135 = leq(uncommonBits_354, UInt<2>(0h3)) node _T_4136 = and(_T_4134, _T_4135) node _uncommonBits_T_355 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_355 = bits(_uncommonBits_T_355, 1, 0) node _T_4137 = shr(io.in.c.bits.source, 2) node _T_4138 = eq(_T_4137, UInt<7>(0h73)) node _T_4139 = leq(UInt<1>(0h0), uncommonBits_355) node _T_4140 = and(_T_4138, _T_4139) node _T_4141 = leq(uncommonBits_355, UInt<2>(0h3)) node _T_4142 = and(_T_4140, _T_4141) node _uncommonBits_T_356 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_356 = bits(_uncommonBits_T_356, 1, 0) node _T_4143 = shr(io.in.c.bits.source, 2) node _T_4144 = eq(_T_4143, UInt<7>(0h7c)) node _T_4145 = leq(UInt<1>(0h0), uncommonBits_356) node _T_4146 = and(_T_4144, _T_4145) node _T_4147 = leq(uncommonBits_356, UInt<2>(0h3)) node _T_4148 = and(_T_4146, _T_4147) node _uncommonBits_T_357 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_357 = bits(_uncommonBits_T_357, 1, 0) node _T_4149 = shr(io.in.c.bits.source, 2) node _T_4150 = eq(_T_4149, UInt<7>(0h7b)) node _T_4151 = leq(UInt<1>(0h0), uncommonBits_357) node _T_4152 = and(_T_4150, _T_4151) node _T_4153 = leq(uncommonBits_357, UInt<2>(0h3)) node _T_4154 = and(_T_4152, _T_4153) node _uncommonBits_T_358 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_358 = bits(_uncommonBits_T_358, 4, 0) node _T_4155 = shr(io.in.c.bits.source, 5) node _T_4156 = eq(_T_4155, UInt<4>(0hd)) node _T_4157 = leq(UInt<1>(0h0), uncommonBits_358) node _T_4158 = and(_T_4156, _T_4157) node _T_4159 = leq(uncommonBits_358, UInt<5>(0h1f)) node _T_4160 = and(_T_4158, _T_4159) node _uncommonBits_T_359 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_359 = bits(_uncommonBits_T_359, 4, 0) node _T_4161 = shr(io.in.c.bits.source, 5) node _T_4162 = eq(_T_4161, UInt<4>(0hc)) node _T_4163 = leq(UInt<1>(0h0), uncommonBits_359) node _T_4164 = and(_T_4162, _T_4163) node _T_4165 = leq(uncommonBits_359, UInt<5>(0h1f)) node _T_4166 = and(_T_4164, _T_4165) node _uncommonBits_T_360 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_360 = bits(_uncommonBits_T_360, 4, 0) node _T_4167 = shr(io.in.c.bits.source, 5) node _T_4168 = eq(_T_4167, UInt<4>(0hb)) node _T_4169 = leq(UInt<1>(0h0), uncommonBits_360) node _T_4170 = and(_T_4168, _T_4169) node _T_4171 = leq(uncommonBits_360, UInt<5>(0h1f)) node _T_4172 = and(_T_4170, _T_4171) node _uncommonBits_T_361 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_361 = bits(_uncommonBits_T_361, 4, 0) node _T_4173 = shr(io.in.c.bits.source, 5) node _T_4174 = eq(_T_4173, UInt<4>(0ha)) node _T_4175 = leq(UInt<1>(0h0), uncommonBits_361) node _T_4176 = and(_T_4174, _T_4175) node _T_4177 = leq(uncommonBits_361, UInt<5>(0h1f)) node _T_4178 = and(_T_4176, _T_4177) node _uncommonBits_T_362 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_362 = bits(_uncommonBits_T_362, 4, 0) node _T_4179 = shr(io.in.c.bits.source, 5) node _T_4180 = eq(_T_4179, UInt<4>(0h9)) node _T_4181 = leq(UInt<1>(0h0), uncommonBits_362) node _T_4182 = and(_T_4180, _T_4181) node _T_4183 = leq(uncommonBits_362, UInt<5>(0h1f)) node _T_4184 = and(_T_4182, _T_4183) node _uncommonBits_T_363 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_363 = bits(_uncommonBits_T_363, 4, 0) node _T_4185 = shr(io.in.c.bits.source, 5) node _T_4186 = eq(_T_4185, UInt<4>(0h8)) node _T_4187 = leq(UInt<1>(0h0), uncommonBits_363) node _T_4188 = and(_T_4186, _T_4187) node _T_4189 = leq(uncommonBits_363, UInt<5>(0h1f)) node _T_4190 = and(_T_4188, _T_4189) node _uncommonBits_T_364 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_364 = bits(_uncommonBits_T_364, 1, 0) node _T_4191 = shr(io.in.c.bits.source, 2) node _T_4192 = eq(_T_4191, UInt<7>(0h7a)) node _T_4193 = leq(UInt<1>(0h0), uncommonBits_364) node _T_4194 = and(_T_4192, _T_4193) node _T_4195 = leq(uncommonBits_364, UInt<2>(0h3)) node _T_4196 = and(_T_4194, _T_4195) node _uncommonBits_T_365 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_365 = bits(_uncommonBits_T_365, 1, 0) node _T_4197 = shr(io.in.c.bits.source, 2) node _T_4198 = eq(_T_4197, UInt<7>(0h79)) node _T_4199 = leq(UInt<1>(0h0), uncommonBits_365) node _T_4200 = and(_T_4198, _T_4199) node _T_4201 = leq(uncommonBits_365, UInt<2>(0h3)) node _T_4202 = and(_T_4200, _T_4201) node _uncommonBits_T_366 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_366 = bits(_uncommonBits_T_366, 4, 0) node _T_4203 = shr(io.in.c.bits.source, 5) node _T_4204 = eq(_T_4203, UInt<3>(0h7)) node _T_4205 = leq(UInt<1>(0h0), uncommonBits_366) node _T_4206 = and(_T_4204, _T_4205) node _T_4207 = leq(uncommonBits_366, UInt<5>(0h1f)) node _T_4208 = and(_T_4206, _T_4207) node _uncommonBits_T_367 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_367 = bits(_uncommonBits_T_367, 4, 0) node _T_4209 = shr(io.in.c.bits.source, 5) node _T_4210 = eq(_T_4209, UInt<3>(0h6)) node _T_4211 = leq(UInt<1>(0h0), uncommonBits_367) node _T_4212 = and(_T_4210, _T_4211) node _T_4213 = leq(uncommonBits_367, UInt<5>(0h1f)) node _T_4214 = and(_T_4212, _T_4213) node _uncommonBits_T_368 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_368 = bits(_uncommonBits_T_368, 4, 0) node _T_4215 = shr(io.in.c.bits.source, 5) node _T_4216 = eq(_T_4215, UInt<3>(0h5)) node _T_4217 = leq(UInt<1>(0h0), uncommonBits_368) node _T_4218 = and(_T_4216, _T_4217) node _T_4219 = leq(uncommonBits_368, UInt<5>(0h1f)) node _T_4220 = and(_T_4218, _T_4219) node _uncommonBits_T_369 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_369 = bits(_uncommonBits_T_369, 4, 0) node _T_4221 = shr(io.in.c.bits.source, 5) node _T_4222 = eq(_T_4221, UInt<3>(0h4)) node _T_4223 = leq(UInt<1>(0h0), uncommonBits_369) node _T_4224 = and(_T_4222, _T_4223) node _T_4225 = leq(uncommonBits_369, UInt<5>(0h1f)) node _T_4226 = and(_T_4224, _T_4225) node _uncommonBits_T_370 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_370 = bits(_uncommonBits_T_370, 4, 0) node _T_4227 = shr(io.in.c.bits.source, 5) node _T_4228 = eq(_T_4227, UInt<2>(0h3)) node _T_4229 = leq(UInt<1>(0h0), uncommonBits_370) node _T_4230 = and(_T_4228, _T_4229) node _T_4231 = leq(uncommonBits_370, UInt<5>(0h1f)) node _T_4232 = and(_T_4230, _T_4231) node _uncommonBits_T_371 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_371 = bits(_uncommonBits_T_371, 4, 0) node _T_4233 = shr(io.in.c.bits.source, 5) node _T_4234 = eq(_T_4233, UInt<2>(0h2)) node _T_4235 = leq(UInt<1>(0h0), uncommonBits_371) node _T_4236 = and(_T_4234, _T_4235) node _T_4237 = leq(uncommonBits_371, UInt<5>(0h1f)) node _T_4238 = and(_T_4236, _T_4237) node _uncommonBits_T_372 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_372 = bits(_uncommonBits_T_372, 4, 0) node _T_4239 = shr(io.in.c.bits.source, 5) node _T_4240 = eq(_T_4239, UInt<1>(0h1)) node _T_4241 = leq(UInt<1>(0h0), uncommonBits_372) node _T_4242 = and(_T_4240, _T_4241) node _T_4243 = leq(uncommonBits_372, UInt<5>(0h1f)) node _T_4244 = and(_T_4242, _T_4243) node _uncommonBits_T_373 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_373 = bits(_uncommonBits_T_373, 4, 0) node _T_4245 = shr(io.in.c.bits.source, 5) node _T_4246 = eq(_T_4245, UInt<1>(0h0)) node _T_4247 = leq(UInt<1>(0h0), uncommonBits_373) node _T_4248 = and(_T_4246, _T_4247) node _T_4249 = leq(uncommonBits_373, UInt<5>(0h1f)) node _T_4250 = and(_T_4248, _T_4249) node _T_4251 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4252 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) node _T_4253 = or(_T_4118, _T_4124) node _T_4254 = or(_T_4253, _T_4130) node _T_4255 = or(_T_4254, _T_4136) node _T_4256 = or(_T_4255, _T_4142) node _T_4257 = or(_T_4256, _T_4148) node _T_4258 = or(_T_4257, _T_4154) node _T_4259 = or(_T_4258, _T_4160) node _T_4260 = or(_T_4259, _T_4166) node _T_4261 = or(_T_4260, _T_4172) node _T_4262 = or(_T_4261, _T_4178) node _T_4263 = or(_T_4262, _T_4184) node _T_4264 = or(_T_4263, _T_4190) node _T_4265 = or(_T_4264, _T_4196) node _T_4266 = or(_T_4265, _T_4202) node _T_4267 = or(_T_4266, _T_4208) node _T_4268 = or(_T_4267, _T_4214) node _T_4269 = or(_T_4268, _T_4220) node _T_4270 = or(_T_4269, _T_4226) node _T_4271 = or(_T_4270, _T_4232) node _T_4272 = or(_T_4271, _T_4238) node _T_4273 = or(_T_4272, _T_4244) node _T_4274 = or(_T_4273, _T_4250) node _T_4275 = or(_T_4274, _T_4251) node _T_4276 = or(_T_4275, _T_4252) node _T_4277 = and(_T_4117, _T_4276) node _T_4278 = or(UInt<1>(0h0), _T_4277) node _T_4279 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4280 = or(UInt<1>(0h0), _T_4279) node _T_4281 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4282 = cvt(_T_4281) node _T_4283 = and(_T_4282, asSInt(UInt<17>(0h10000))) node _T_4284 = asSInt(_T_4283) node _T_4285 = eq(_T_4284, asSInt(UInt<1>(0h0))) node _T_4286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4287 = cvt(_T_4286) node _T_4288 = and(_T_4287, asSInt(UInt<29>(0h10000000))) node _T_4289 = asSInt(_T_4288) node _T_4290 = eq(_T_4289, asSInt(UInt<1>(0h0))) node _T_4291 = or(_T_4285, _T_4290) node _T_4292 = and(_T_4280, _T_4291) node _T_4293 = or(UInt<1>(0h0), _T_4292) node _T_4294 = and(_T_4278, _T_4293) node _T_4295 = asUInt(reset) node _T_4296 = eq(_T_4295, UInt<1>(0h0)) when _T_4296 : node _T_4297 = eq(_T_4294, UInt<1>(0h0)) when _T_4297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_4294, UInt<1>(0h1), "") : assert_150 node _T_4298 = eq(io.in.c.bits.source, UInt<9>(0h1d0)) node _uncommonBits_T_374 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_374 = bits(_uncommonBits_T_374, 1, 0) node _T_4299 = shr(io.in.c.bits.source, 2) node _T_4300 = eq(_T_4299, UInt<7>(0h70)) node _T_4301 = leq(UInt<1>(0h0), uncommonBits_374) node _T_4302 = and(_T_4300, _T_4301) node _T_4303 = leq(uncommonBits_374, UInt<2>(0h3)) node _T_4304 = and(_T_4302, _T_4303) node _uncommonBits_T_375 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_375 = bits(_uncommonBits_T_375, 1, 0) node _T_4305 = shr(io.in.c.bits.source, 2) node _T_4306 = eq(_T_4305, UInt<7>(0h71)) node _T_4307 = leq(UInt<1>(0h0), uncommonBits_375) node _T_4308 = and(_T_4306, _T_4307) node _T_4309 = leq(uncommonBits_375, UInt<2>(0h3)) node _T_4310 = and(_T_4308, _T_4309) node _uncommonBits_T_376 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_376 = bits(_uncommonBits_T_376, 1, 0) node _T_4311 = shr(io.in.c.bits.source, 2) node _T_4312 = eq(_T_4311, UInt<7>(0h72)) node _T_4313 = leq(UInt<1>(0h0), uncommonBits_376) node _T_4314 = and(_T_4312, _T_4313) node _T_4315 = leq(uncommonBits_376, UInt<2>(0h3)) node _T_4316 = and(_T_4314, _T_4315) node _uncommonBits_T_377 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_377 = bits(_uncommonBits_T_377, 1, 0) node _T_4317 = shr(io.in.c.bits.source, 2) node _T_4318 = eq(_T_4317, UInt<7>(0h73)) node _T_4319 = leq(UInt<1>(0h0), uncommonBits_377) node _T_4320 = and(_T_4318, _T_4319) node _T_4321 = leq(uncommonBits_377, UInt<2>(0h3)) node _T_4322 = and(_T_4320, _T_4321) node _uncommonBits_T_378 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_378 = bits(_uncommonBits_T_378, 1, 0) node _T_4323 = shr(io.in.c.bits.source, 2) node _T_4324 = eq(_T_4323, UInt<7>(0h7c)) node _T_4325 = leq(UInt<1>(0h0), uncommonBits_378) node _T_4326 = and(_T_4324, _T_4325) node _T_4327 = leq(uncommonBits_378, UInt<2>(0h3)) node _T_4328 = and(_T_4326, _T_4327) node _uncommonBits_T_379 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_379 = bits(_uncommonBits_T_379, 1, 0) node _T_4329 = shr(io.in.c.bits.source, 2) node _T_4330 = eq(_T_4329, UInt<7>(0h7b)) node _T_4331 = leq(UInt<1>(0h0), uncommonBits_379) node _T_4332 = and(_T_4330, _T_4331) node _T_4333 = leq(uncommonBits_379, UInt<2>(0h3)) node _T_4334 = and(_T_4332, _T_4333) node _uncommonBits_T_380 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_380 = bits(_uncommonBits_T_380, 4, 0) node _T_4335 = shr(io.in.c.bits.source, 5) node _T_4336 = eq(_T_4335, UInt<4>(0hd)) node _T_4337 = leq(UInt<1>(0h0), uncommonBits_380) node _T_4338 = and(_T_4336, _T_4337) node _T_4339 = leq(uncommonBits_380, UInt<5>(0h1f)) node _T_4340 = and(_T_4338, _T_4339) node _uncommonBits_T_381 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_381 = bits(_uncommonBits_T_381, 4, 0) node _T_4341 = shr(io.in.c.bits.source, 5) node _T_4342 = eq(_T_4341, UInt<4>(0hc)) node _T_4343 = leq(UInt<1>(0h0), uncommonBits_381) node _T_4344 = and(_T_4342, _T_4343) node _T_4345 = leq(uncommonBits_381, UInt<5>(0h1f)) node _T_4346 = and(_T_4344, _T_4345) node _uncommonBits_T_382 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_382 = bits(_uncommonBits_T_382, 4, 0) node _T_4347 = shr(io.in.c.bits.source, 5) node _T_4348 = eq(_T_4347, UInt<4>(0hb)) node _T_4349 = leq(UInt<1>(0h0), uncommonBits_382) node _T_4350 = and(_T_4348, _T_4349) node _T_4351 = leq(uncommonBits_382, UInt<5>(0h1f)) node _T_4352 = and(_T_4350, _T_4351) node _uncommonBits_T_383 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_383 = bits(_uncommonBits_T_383, 4, 0) node _T_4353 = shr(io.in.c.bits.source, 5) node _T_4354 = eq(_T_4353, UInt<4>(0ha)) node _T_4355 = leq(UInt<1>(0h0), uncommonBits_383) node _T_4356 = and(_T_4354, _T_4355) node _T_4357 = leq(uncommonBits_383, UInt<5>(0h1f)) node _T_4358 = and(_T_4356, _T_4357) node _uncommonBits_T_384 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_384 = bits(_uncommonBits_T_384, 4, 0) node _T_4359 = shr(io.in.c.bits.source, 5) node _T_4360 = eq(_T_4359, UInt<4>(0h9)) node _T_4361 = leq(UInt<1>(0h0), uncommonBits_384) node _T_4362 = and(_T_4360, _T_4361) node _T_4363 = leq(uncommonBits_384, UInt<5>(0h1f)) node _T_4364 = and(_T_4362, _T_4363) node _uncommonBits_T_385 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_385 = bits(_uncommonBits_T_385, 4, 0) node _T_4365 = shr(io.in.c.bits.source, 5) node _T_4366 = eq(_T_4365, UInt<4>(0h8)) node _T_4367 = leq(UInt<1>(0h0), uncommonBits_385) node _T_4368 = and(_T_4366, _T_4367) node _T_4369 = leq(uncommonBits_385, UInt<5>(0h1f)) node _T_4370 = and(_T_4368, _T_4369) node _uncommonBits_T_386 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_386 = bits(_uncommonBits_T_386, 1, 0) node _T_4371 = shr(io.in.c.bits.source, 2) node _T_4372 = eq(_T_4371, UInt<7>(0h7a)) node _T_4373 = leq(UInt<1>(0h0), uncommonBits_386) node _T_4374 = and(_T_4372, _T_4373) node _T_4375 = leq(uncommonBits_386, UInt<2>(0h3)) node _T_4376 = and(_T_4374, _T_4375) node _uncommonBits_T_387 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_387 = bits(_uncommonBits_T_387, 1, 0) node _T_4377 = shr(io.in.c.bits.source, 2) node _T_4378 = eq(_T_4377, UInt<7>(0h79)) node _T_4379 = leq(UInt<1>(0h0), uncommonBits_387) node _T_4380 = and(_T_4378, _T_4379) node _T_4381 = leq(uncommonBits_387, UInt<2>(0h3)) node _T_4382 = and(_T_4380, _T_4381) node _uncommonBits_T_388 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_388 = bits(_uncommonBits_T_388, 4, 0) node _T_4383 = shr(io.in.c.bits.source, 5) node _T_4384 = eq(_T_4383, UInt<3>(0h7)) node _T_4385 = leq(UInt<1>(0h0), uncommonBits_388) node _T_4386 = and(_T_4384, _T_4385) node _T_4387 = leq(uncommonBits_388, UInt<5>(0h1f)) node _T_4388 = and(_T_4386, _T_4387) node _uncommonBits_T_389 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_389 = bits(_uncommonBits_T_389, 4, 0) node _T_4389 = shr(io.in.c.bits.source, 5) node _T_4390 = eq(_T_4389, UInt<3>(0h6)) node _T_4391 = leq(UInt<1>(0h0), uncommonBits_389) node _T_4392 = and(_T_4390, _T_4391) node _T_4393 = leq(uncommonBits_389, UInt<5>(0h1f)) node _T_4394 = and(_T_4392, _T_4393) node _uncommonBits_T_390 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_390 = bits(_uncommonBits_T_390, 4, 0) node _T_4395 = shr(io.in.c.bits.source, 5) node _T_4396 = eq(_T_4395, UInt<3>(0h5)) node _T_4397 = leq(UInt<1>(0h0), uncommonBits_390) node _T_4398 = and(_T_4396, _T_4397) node _T_4399 = leq(uncommonBits_390, UInt<5>(0h1f)) node _T_4400 = and(_T_4398, _T_4399) node _uncommonBits_T_391 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_391 = bits(_uncommonBits_T_391, 4, 0) node _T_4401 = shr(io.in.c.bits.source, 5) node _T_4402 = eq(_T_4401, UInt<3>(0h4)) node _T_4403 = leq(UInt<1>(0h0), uncommonBits_391) node _T_4404 = and(_T_4402, _T_4403) node _T_4405 = leq(uncommonBits_391, UInt<5>(0h1f)) node _T_4406 = and(_T_4404, _T_4405) node _uncommonBits_T_392 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_392 = bits(_uncommonBits_T_392, 4, 0) node _T_4407 = shr(io.in.c.bits.source, 5) node _T_4408 = eq(_T_4407, UInt<2>(0h3)) node _T_4409 = leq(UInt<1>(0h0), uncommonBits_392) node _T_4410 = and(_T_4408, _T_4409) node _T_4411 = leq(uncommonBits_392, UInt<5>(0h1f)) node _T_4412 = and(_T_4410, _T_4411) node _uncommonBits_T_393 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_393 = bits(_uncommonBits_T_393, 4, 0) node _T_4413 = shr(io.in.c.bits.source, 5) node _T_4414 = eq(_T_4413, UInt<2>(0h2)) node _T_4415 = leq(UInt<1>(0h0), uncommonBits_393) node _T_4416 = and(_T_4414, _T_4415) node _T_4417 = leq(uncommonBits_393, UInt<5>(0h1f)) node _T_4418 = and(_T_4416, _T_4417) node _uncommonBits_T_394 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_394 = bits(_uncommonBits_T_394, 4, 0) node _T_4419 = shr(io.in.c.bits.source, 5) node _T_4420 = eq(_T_4419, UInt<1>(0h1)) node _T_4421 = leq(UInt<1>(0h0), uncommonBits_394) node _T_4422 = and(_T_4420, _T_4421) node _T_4423 = leq(uncommonBits_394, UInt<5>(0h1f)) node _T_4424 = and(_T_4422, _T_4423) node _uncommonBits_T_395 = or(io.in.c.bits.source, UInt<5>(0h0)) node uncommonBits_395 = bits(_uncommonBits_T_395, 4, 0) node _T_4425 = shr(io.in.c.bits.source, 5) node _T_4426 = eq(_T_4425, UInt<1>(0h0)) node _T_4427 = leq(UInt<1>(0h0), uncommonBits_395) node _T_4428 = and(_T_4426, _T_4427) node _T_4429 = leq(uncommonBits_395, UInt<5>(0h1f)) node _T_4430 = and(_T_4428, _T_4429) node _T_4431 = eq(io.in.c.bits.source, UInt<9>(0h1e0)) node _T_4432 = eq(io.in.c.bits.source, UInt<9>(0h1e2)) wire _WIRE_8 : UInt<1>[25] connect _WIRE_8[0], _T_4298 connect _WIRE_8[1], _T_4304 connect _WIRE_8[2], _T_4310 connect _WIRE_8[3], _T_4316 connect _WIRE_8[4], _T_4322 connect _WIRE_8[5], _T_4328 connect _WIRE_8[6], _T_4334 connect _WIRE_8[7], _T_4340 connect _WIRE_8[8], _T_4346 connect _WIRE_8[9], _T_4352 connect _WIRE_8[10], _T_4358 connect _WIRE_8[11], _T_4364 connect _WIRE_8[12], _T_4370 connect _WIRE_8[13], _T_4376 connect _WIRE_8[14], _T_4382 connect _WIRE_8[15], _T_4388 connect _WIRE_8[16], _T_4394 connect _WIRE_8[17], _T_4400 connect _WIRE_8[18], _T_4406 connect _WIRE_8[19], _T_4412 connect _WIRE_8[20], _T_4418 connect _WIRE_8[21], _T_4424 connect _WIRE_8[22], _T_4430 connect _WIRE_8[23], _T_4431 connect _WIRE_8[24], _T_4432 node _T_4433 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_4434 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_4435 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_4436 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_4437 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_4438 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_4439 = mux(_WIRE_8[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_4440 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_4441 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_4442 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_4443 = mux(_WIRE_8[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_4444 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_4445 = mux(_WIRE_8[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_4446 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_4447 = mux(_WIRE_8[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_4448 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_4449 = mux(_WIRE_8[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_4450 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_4451 = mux(_WIRE_8[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_4452 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_4453 = mux(_WIRE_8[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_4454 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_4455 = mux(_WIRE_8[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_4456 = mux(_WIRE_8[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_4457 = mux(_WIRE_8[23], _T_4433, UInt<1>(0h0)) node _T_4458 = mux(_WIRE_8[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_4459 = or(_T_4434, _T_4435) node _T_4460 = or(_T_4459, _T_4436) node _T_4461 = or(_T_4460, _T_4437) node _T_4462 = or(_T_4461, _T_4438) node _T_4463 = or(_T_4462, _T_4439) node _T_4464 = or(_T_4463, _T_4440) node _T_4465 = or(_T_4464, _T_4441) node _T_4466 = or(_T_4465, _T_4442) node _T_4467 = or(_T_4466, _T_4443) node _T_4468 = or(_T_4467, _T_4444) node _T_4469 = or(_T_4468, _T_4445) node _T_4470 = or(_T_4469, _T_4446) node _T_4471 = or(_T_4470, _T_4447) node _T_4472 = or(_T_4471, _T_4448) node _T_4473 = or(_T_4472, _T_4449) node _T_4474 = or(_T_4473, _T_4450) node _T_4475 = or(_T_4474, _T_4451) node _T_4476 = or(_T_4475, _T_4452) node _T_4477 = or(_T_4476, _T_4453) node _T_4478 = or(_T_4477, _T_4454) node _T_4479 = or(_T_4478, _T_4455) node _T_4480 = or(_T_4479, _T_4456) node _T_4481 = or(_T_4480, _T_4457) node _T_4482 = or(_T_4481, _T_4458) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_4482 node _T_4483 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_4484 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_4485 = and(_T_4483, _T_4484) node _T_4486 = or(UInt<1>(0h0), _T_4485) node _T_4487 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_4488 = cvt(_T_4487) node _T_4489 = and(_T_4488, asSInt(UInt<17>(0h10000))) node _T_4490 = asSInt(_T_4489) node _T_4491 = eq(_T_4490, asSInt(UInt<1>(0h0))) node _T_4492 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_4493 = cvt(_T_4492) node _T_4494 = and(_T_4493, asSInt(UInt<29>(0h10000000))) node _T_4495 = asSInt(_T_4494) node _T_4496 = eq(_T_4495, asSInt(UInt<1>(0h0))) node _T_4497 = or(_T_4491, _T_4496) node _T_4498 = and(_T_4486, _T_4497) node _T_4499 = or(UInt<1>(0h0), _T_4498) node _T_4500 = and(_WIRE_9, _T_4499) node _T_4501 = asUInt(reset) node _T_4502 = eq(_T_4501, UInt<1>(0h0)) when _T_4502 : node _T_4503 = eq(_T_4500, UInt<1>(0h0)) when _T_4503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_4500, UInt<1>(0h1), "") : assert_151 node _T_4504 = asUInt(reset) node _T_4505 = eq(_T_4504, UInt<1>(0h0)) when _T_4505 : node _T_4506 = eq(source_ok_2, UInt<1>(0h0)) when _T_4506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_4507 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_4508 = asUInt(reset) node _T_4509 = eq(_T_4508, UInt<1>(0h0)) when _T_4509 : node _T_4510 = eq(_T_4507, UInt<1>(0h0)) when _T_4510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_4507, UInt<1>(0h1), "") : assert_153 node _T_4511 = asUInt(reset) node _T_4512 = eq(_T_4511, UInt<1>(0h0)) when _T_4512 : node _T_4513 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_4514 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_4515 = asUInt(reset) node _T_4516 = eq(_T_4515, UInt<1>(0h0)) when _T_4516 : node _T_4517 = eq(_T_4514, UInt<1>(0h0)) when _T_4517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_4514, UInt<1>(0h1), "") : assert_155 node _T_4518 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_4518 : node _T_4519 = asUInt(reset) node _T_4520 = eq(_T_4519, UInt<1>(0h0)) when _T_4520 : node _T_4521 = eq(address_ok_1, UInt<1>(0h0)) when _T_4521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_4522 = asUInt(reset) node _T_4523 = eq(_T_4522, UInt<1>(0h0)) when _T_4523 : node _T_4524 = eq(source_ok_2, UInt<1>(0h0)) when _T_4524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_4525 = asUInt(reset) node _T_4526 = eq(_T_4525, UInt<1>(0h0)) when _T_4526 : node _T_4527 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_4528 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4529 = asUInt(reset) node _T_4530 = eq(_T_4529, UInt<1>(0h0)) when _T_4530 : node _T_4531 = eq(_T_4528, UInt<1>(0h0)) when _T_4531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_4528, UInt<1>(0h1), "") : assert_159 node _T_4532 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4533 = asUInt(reset) node _T_4534 = eq(_T_4533, UInt<1>(0h0)) when _T_4534 : node _T_4535 = eq(_T_4532, UInt<1>(0h0)) when _T_4535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_4532, UInt<1>(0h1), "") : assert_160 node _T_4536 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_4536 : node _T_4537 = asUInt(reset) node _T_4538 = eq(_T_4537, UInt<1>(0h0)) when _T_4538 : node _T_4539 = eq(address_ok_1, UInt<1>(0h0)) when _T_4539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_4540 = asUInt(reset) node _T_4541 = eq(_T_4540, UInt<1>(0h0)) when _T_4541 : node _T_4542 = eq(source_ok_2, UInt<1>(0h0)) when _T_4542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_4543 = asUInt(reset) node _T_4544 = eq(_T_4543, UInt<1>(0h0)) when _T_4544 : node _T_4545 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_4546 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4547 = asUInt(reset) node _T_4548 = eq(_T_4547, UInt<1>(0h0)) when _T_4548 : node _T_4549 = eq(_T_4546, UInt<1>(0h0)) when _T_4549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_4546, UInt<1>(0h1), "") : assert_164 node _T_4550 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_4550 : node _T_4551 = asUInt(reset) node _T_4552 = eq(_T_4551, UInt<1>(0h0)) when _T_4552 : node _T_4553 = eq(address_ok_1, UInt<1>(0h0)) when _T_4553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_4554 = asUInt(reset) node _T_4555 = eq(_T_4554, UInt<1>(0h0)) when _T_4555 : node _T_4556 = eq(source_ok_2, UInt<1>(0h0)) when _T_4556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_4557 = asUInt(reset) node _T_4558 = eq(_T_4557, UInt<1>(0h0)) when _T_4558 : node _T_4559 = eq(is_aligned_2, UInt<1>(0h0)) when _T_4559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_4560 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_4561 = asUInt(reset) node _T_4562 = eq(_T_4561, UInt<1>(0h0)) when _T_4562 : node _T_4563 = eq(_T_4560, UInt<1>(0h0)) when _T_4563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_4560, UInt<1>(0h1), "") : assert_168 node _T_4564 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_4565 = asUInt(reset) node _T_4566 = eq(_T_4565, UInt<1>(0h0)) when _T_4566 : node _T_4567 = eq(_T_4564, UInt<1>(0h0)) when _T_4567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_4564, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_4568 = asUInt(reset) node _T_4569 = eq(_T_4568, UInt<1>(0h0)) when _T_4569 : node _T_4570 = eq(sink_ok_1, UInt<1>(0h0)) when _T_4570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_4571 = eq(a_first, UInt<1>(0h0)) node _T_4572 = and(io.in.a.valid, _T_4571) when _T_4572 : node _T_4573 = eq(io.in.a.bits.opcode, opcode) node _T_4574 = asUInt(reset) node _T_4575 = eq(_T_4574, UInt<1>(0h0)) when _T_4575 : node _T_4576 = eq(_T_4573, UInt<1>(0h0)) when _T_4576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_4573, UInt<1>(0h1), "") : assert_171 node _T_4577 = eq(io.in.a.bits.param, param) node _T_4578 = asUInt(reset) node _T_4579 = eq(_T_4578, UInt<1>(0h0)) when _T_4579 : node _T_4580 = eq(_T_4577, UInt<1>(0h0)) when _T_4580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_4577, UInt<1>(0h1), "") : assert_172 node _T_4581 = eq(io.in.a.bits.size, size) node _T_4582 = asUInt(reset) node _T_4583 = eq(_T_4582, UInt<1>(0h0)) when _T_4583 : node _T_4584 = eq(_T_4581, UInt<1>(0h0)) when _T_4584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_4581, UInt<1>(0h1), "") : assert_173 node _T_4585 = eq(io.in.a.bits.source, source) node _T_4586 = asUInt(reset) node _T_4587 = eq(_T_4586, UInt<1>(0h0)) when _T_4587 : node _T_4588 = eq(_T_4585, UInt<1>(0h0)) when _T_4588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_4585, UInt<1>(0h1), "") : assert_174 node _T_4589 = eq(io.in.a.bits.address, address) node _T_4590 = asUInt(reset) node _T_4591 = eq(_T_4590, UInt<1>(0h0)) when _T_4591 : node _T_4592 = eq(_T_4589, UInt<1>(0h0)) when _T_4592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_4589, UInt<1>(0h1), "") : assert_175 node _T_4593 = and(io.in.a.ready, io.in.a.valid) node _T_4594 = and(_T_4593, a_first) when _T_4594 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_4595 = eq(d_first, UInt<1>(0h0)) node _T_4596 = and(io.in.d.valid, _T_4595) when _T_4596 : node _T_4597 = eq(io.in.d.bits.opcode, opcode_1) node _T_4598 = asUInt(reset) node _T_4599 = eq(_T_4598, UInt<1>(0h0)) when _T_4599 : node _T_4600 = eq(_T_4597, UInt<1>(0h0)) when _T_4600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_4597, UInt<1>(0h1), "") : assert_176 node _T_4601 = eq(io.in.d.bits.param, param_1) node _T_4602 = asUInt(reset) node _T_4603 = eq(_T_4602, UInt<1>(0h0)) when _T_4603 : node _T_4604 = eq(_T_4601, UInt<1>(0h0)) when _T_4604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_4601, UInt<1>(0h1), "") : assert_177 node _T_4605 = eq(io.in.d.bits.size, size_1) node _T_4606 = asUInt(reset) node _T_4607 = eq(_T_4606, UInt<1>(0h0)) when _T_4607 : node _T_4608 = eq(_T_4605, UInt<1>(0h0)) when _T_4608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_4605, UInt<1>(0h1), "") : assert_178 node _T_4609 = eq(io.in.d.bits.source, source_1) node _T_4610 = asUInt(reset) node _T_4611 = eq(_T_4610, UInt<1>(0h0)) when _T_4611 : node _T_4612 = eq(_T_4609, UInt<1>(0h0)) when _T_4612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_4609, UInt<1>(0h1), "") : assert_179 node _T_4613 = eq(io.in.d.bits.sink, sink) node _T_4614 = asUInt(reset) node _T_4615 = eq(_T_4614, UInt<1>(0h0)) when _T_4615 : node _T_4616 = eq(_T_4613, UInt<1>(0h0)) when _T_4616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_4613, UInt<1>(0h1), "") : assert_180 node _T_4617 = eq(io.in.d.bits.denied, denied) node _T_4618 = asUInt(reset) node _T_4619 = eq(_T_4618, UInt<1>(0h0)) when _T_4619 : node _T_4620 = eq(_T_4617, UInt<1>(0h0)) when _T_4620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_4617, UInt<1>(0h1), "") : assert_181 node _T_4621 = and(io.in.d.ready, io.in.d.valid) node _T_4622 = and(_T_4621, d_first) when _T_4622 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_4623 = eq(b_first, UInt<1>(0h0)) node _T_4624 = and(io.in.b.valid, _T_4623) when _T_4624 : node _T_4625 = eq(io.in.b.bits.opcode, opcode_2) node _T_4626 = asUInt(reset) node _T_4627 = eq(_T_4626, UInt<1>(0h0)) when _T_4627 : node _T_4628 = eq(_T_4625, UInt<1>(0h0)) when _T_4628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_4625, UInt<1>(0h1), "") : assert_182 node _T_4629 = eq(io.in.b.bits.param, param_2) node _T_4630 = asUInt(reset) node _T_4631 = eq(_T_4630, UInt<1>(0h0)) when _T_4631 : node _T_4632 = eq(_T_4629, UInt<1>(0h0)) when _T_4632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_4629, UInt<1>(0h1), "") : assert_183 node _T_4633 = eq(io.in.b.bits.size, size_2) node _T_4634 = asUInt(reset) node _T_4635 = eq(_T_4634, UInt<1>(0h0)) when _T_4635 : node _T_4636 = eq(_T_4633, UInt<1>(0h0)) when _T_4636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_4633, UInt<1>(0h1), "") : assert_184 node _T_4637 = eq(io.in.b.bits.source, source_2) node _T_4638 = asUInt(reset) node _T_4639 = eq(_T_4638, UInt<1>(0h0)) when _T_4639 : node _T_4640 = eq(_T_4637, UInt<1>(0h0)) when _T_4640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_4637, UInt<1>(0h1), "") : assert_185 node _T_4641 = eq(io.in.b.bits.address, address_1) node _T_4642 = asUInt(reset) node _T_4643 = eq(_T_4642, UInt<1>(0h0)) when _T_4643 : node _T_4644 = eq(_T_4641, UInt<1>(0h0)) when _T_4644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_4641, UInt<1>(0h1), "") : assert_186 node _T_4645 = and(io.in.b.ready, io.in.b.valid) node _T_4646 = and(_T_4645, b_first) when _T_4646 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_4647 = eq(c_first, UInt<1>(0h0)) node _T_4648 = and(io.in.c.valid, _T_4647) when _T_4648 : node _T_4649 = eq(io.in.c.bits.opcode, opcode_3) node _T_4650 = asUInt(reset) node _T_4651 = eq(_T_4650, UInt<1>(0h0)) when _T_4651 : node _T_4652 = eq(_T_4649, UInt<1>(0h0)) when _T_4652 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_4649, UInt<1>(0h1), "") : assert_187 node _T_4653 = eq(io.in.c.bits.param, param_3) node _T_4654 = asUInt(reset) node _T_4655 = eq(_T_4654, UInt<1>(0h0)) when _T_4655 : node _T_4656 = eq(_T_4653, UInt<1>(0h0)) when _T_4656 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_4653, UInt<1>(0h1), "") : assert_188 node _T_4657 = eq(io.in.c.bits.size, size_3) node _T_4658 = asUInt(reset) node _T_4659 = eq(_T_4658, UInt<1>(0h0)) when _T_4659 : node _T_4660 = eq(_T_4657, UInt<1>(0h0)) when _T_4660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_4657, UInt<1>(0h1), "") : assert_189 node _T_4661 = eq(io.in.c.bits.source, source_3) node _T_4662 = asUInt(reset) node _T_4663 = eq(_T_4662, UInt<1>(0h0)) when _T_4663 : node _T_4664 = eq(_T_4661, UInt<1>(0h0)) when _T_4664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_4661, UInt<1>(0h1), "") : assert_190 node _T_4665 = eq(io.in.c.bits.address, address_2) node _T_4666 = asUInt(reset) node _T_4667 = eq(_T_4666, UInt<1>(0h0)) when _T_4667 : node _T_4668 = eq(_T_4665, UInt<1>(0h0)) when _T_4668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_4665, UInt<1>(0h1), "") : assert_191 node _T_4669 = and(io.in.c.ready, io.in.c.valid) node _T_4670 = and(_T_4669, c_first) when _T_4670 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<500>, clock, reset, UInt<500>(0h0) regreset inflight_opcodes : UInt<2000>, clock, reset, UInt<2000>(0h0) regreset inflight_sizes : UInt<2000>, clock, reset, UInt<2000>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<500> connect a_set, UInt<500>(0h0) wire a_set_wo_ready : UInt<500> connect a_set_wo_ready, UInt<500>(0h0) wire a_opcodes_set : UInt<2000> connect a_opcodes_set, UInt<2000>(0h0) wire a_sizes_set : UInt<2000> connect a_sizes_set, UInt<2000>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_4671 = and(io.in.a.valid, a_first_1) node _T_4672 = and(_T_4671, UInt<1>(0h1)) when _T_4672 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_4673 = and(io.in.a.ready, io.in.a.valid) node _T_4674 = and(_T_4673, a_first_1) node _T_4675 = and(_T_4674, UInt<1>(0h1)) when _T_4675 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_4676 = dshr(inflight, io.in.a.bits.source) node _T_4677 = bits(_T_4676, 0, 0) node _T_4678 = eq(_T_4677, UInt<1>(0h0)) node _T_4679 = asUInt(reset) node _T_4680 = eq(_T_4679, UInt<1>(0h0)) when _T_4680 : node _T_4681 = eq(_T_4678, UInt<1>(0h0)) when _T_4681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_4678, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<500> connect d_clr, UInt<500>(0h0) wire d_clr_wo_ready : UInt<500> connect d_clr_wo_ready, UInt<500>(0h0) wire d_opcodes_clr : UInt<2000> connect d_opcodes_clr, UInt<2000>(0h0) wire d_sizes_clr : UInt<2000> connect d_sizes_clr, UInt<2000>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_4682 = and(io.in.d.valid, d_first_1) node _T_4683 = and(_T_4682, UInt<1>(0h1)) node _T_4684 = eq(d_release_ack, UInt<1>(0h0)) node _T_4685 = and(_T_4683, _T_4684) when _T_4685 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_4686 = and(io.in.d.ready, io.in.d.valid) node _T_4687 = and(_T_4686, d_first_1) node _T_4688 = and(_T_4687, UInt<1>(0h1)) node _T_4689 = eq(d_release_ack, UInt<1>(0h0)) node _T_4690 = and(_T_4688, _T_4689) when _T_4690 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_4691 = and(io.in.d.valid, d_first_1) node _T_4692 = and(_T_4691, UInt<1>(0h1)) node _T_4693 = eq(d_release_ack, UInt<1>(0h0)) node _T_4694 = and(_T_4692, _T_4693) when _T_4694 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_4695 = dshr(inflight, io.in.d.bits.source) node _T_4696 = bits(_T_4695, 0, 0) node _T_4697 = or(_T_4696, same_cycle_resp) node _T_4698 = asUInt(reset) node _T_4699 = eq(_T_4698, UInt<1>(0h0)) when _T_4699 : node _T_4700 = eq(_T_4697, UInt<1>(0h0)) when _T_4700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_4697, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_4701 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_4702 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_4703 = or(_T_4701, _T_4702) node _T_4704 = asUInt(reset) node _T_4705 = eq(_T_4704, UInt<1>(0h0)) when _T_4705 : node _T_4706 = eq(_T_4703, UInt<1>(0h0)) when _T_4706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_4703, UInt<1>(0h1), "") : assert_194 node _T_4707 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_4708 = asUInt(reset) node _T_4709 = eq(_T_4708, UInt<1>(0h0)) when _T_4709 : node _T_4710 = eq(_T_4707, UInt<1>(0h0)) when _T_4710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_4707, UInt<1>(0h1), "") : assert_195 else : node _T_4711 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_4712 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_4713 = or(_T_4711, _T_4712) node _T_4714 = asUInt(reset) node _T_4715 = eq(_T_4714, UInt<1>(0h0)) when _T_4715 : node _T_4716 = eq(_T_4713, UInt<1>(0h0)) when _T_4716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_4713, UInt<1>(0h1), "") : assert_196 node _T_4717 = eq(io.in.d.bits.size, a_size_lookup) node _T_4718 = asUInt(reset) node _T_4719 = eq(_T_4718, UInt<1>(0h0)) when _T_4719 : node _T_4720 = eq(_T_4717, UInt<1>(0h0)) when _T_4720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_4717, UInt<1>(0h1), "") : assert_197 node _T_4721 = and(io.in.d.valid, d_first_1) node _T_4722 = and(_T_4721, a_first_1) node _T_4723 = and(_T_4722, io.in.a.valid) node _T_4724 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_4725 = and(_T_4723, _T_4724) node _T_4726 = eq(d_release_ack, UInt<1>(0h0)) node _T_4727 = and(_T_4725, _T_4726) when _T_4727 : node _T_4728 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_4729 = or(_T_4728, io.in.a.ready) node _T_4730 = asUInt(reset) node _T_4731 = eq(_T_4730, UInt<1>(0h0)) when _T_4731 : node _T_4732 = eq(_T_4729, UInt<1>(0h0)) when _T_4732 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_4729, UInt<1>(0h1), "") : assert_198 node _T_4733 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_4734 = orr(a_set_wo_ready) node _T_4735 = eq(_T_4734, UInt<1>(0h0)) node _T_4736 = or(_T_4733, _T_4735) node _T_4737 = asUInt(reset) node _T_4738 = eq(_T_4737, UInt<1>(0h0)) when _T_4738 : node _T_4739 = eq(_T_4736, UInt<1>(0h0)) when _T_4739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_4736, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_104 node _T_4740 = orr(inflight) node _T_4741 = eq(_T_4740, UInt<1>(0h0)) node _T_4742 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_4743 = or(_T_4741, _T_4742) node _T_4744 = lt(watchdog, plusarg_reader.out) node _T_4745 = or(_T_4743, _T_4744) node _T_4746 = asUInt(reset) node _T_4747 = eq(_T_4746, UInt<1>(0h0)) when _T_4747 : node _T_4748 = eq(_T_4745, UInt<1>(0h0)) when _T_4748 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_4745, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_4749 = and(io.in.a.ready, io.in.a.valid) node _T_4750 = and(io.in.d.ready, io.in.d.valid) node _T_4751 = or(_T_4749, _T_4750) when _T_4751 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<500>, clock, reset, UInt<500>(0h0) regreset inflight_opcodes_1 : UInt<2000>, clock, reset, UInt<2000>(0h0) regreset inflight_sizes_1 : UInt<2000>, clock, reset, UInt<2000>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<500> connect c_set, UInt<500>(0h0) wire c_set_wo_ready : UInt<500> connect c_set_wo_ready, UInt<500>(0h0) wire c_opcodes_set : UInt<2000> connect c_opcodes_set, UInt<2000>(0h0) wire c_sizes_set : UInt<2000> connect c_sizes_set, UInt<2000>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_4752 = and(io.in.c.valid, c_first_1) node _T_4753 = bits(io.in.c.bits.opcode, 2, 2) node _T_4754 = bits(io.in.c.bits.opcode, 1, 1) node _T_4755 = and(_T_4753, _T_4754) node _T_4756 = and(_T_4752, _T_4755) when _T_4756 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_4757 = and(io.in.c.ready, io.in.c.valid) node _T_4758 = and(_T_4757, c_first_1) node _T_4759 = bits(io.in.c.bits.opcode, 2, 2) node _T_4760 = bits(io.in.c.bits.opcode, 1, 1) node _T_4761 = and(_T_4759, _T_4760) node _T_4762 = and(_T_4758, _T_4761) when _T_4762 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_4763 = dshr(inflight_1, io.in.c.bits.source) node _T_4764 = bits(_T_4763, 0, 0) node _T_4765 = eq(_T_4764, UInt<1>(0h0)) node _T_4766 = asUInt(reset) node _T_4767 = eq(_T_4766, UInt<1>(0h0)) when _T_4767 : node _T_4768 = eq(_T_4765, UInt<1>(0h0)) when _T_4768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_4765, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<500> connect d_clr_1, UInt<500>(0h0) wire d_clr_wo_ready_1 : UInt<500> connect d_clr_wo_ready_1, UInt<500>(0h0) wire d_opcodes_clr_1 : UInt<2000> connect d_opcodes_clr_1, UInt<2000>(0h0) wire d_sizes_clr_1 : UInt<2000> connect d_sizes_clr_1, UInt<2000>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_4769 = and(io.in.d.valid, d_first_2) node _T_4770 = and(_T_4769, UInt<1>(0h1)) node _T_4771 = and(_T_4770, d_release_ack_1) when _T_4771 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_4772 = and(io.in.d.ready, io.in.d.valid) node _T_4773 = and(_T_4772, d_first_2) node _T_4774 = and(_T_4773, UInt<1>(0h1)) node _T_4775 = and(_T_4774, d_release_ack_1) when _T_4775 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_4776 = and(io.in.d.valid, d_first_2) node _T_4777 = and(_T_4776, UInt<1>(0h1)) node _T_4778 = and(_T_4777, d_release_ack_1) when _T_4778 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_4779 = dshr(inflight_1, io.in.d.bits.source) node _T_4780 = bits(_T_4779, 0, 0) node _T_4781 = or(_T_4780, same_cycle_resp_1) node _T_4782 = asUInt(reset) node _T_4783 = eq(_T_4782, UInt<1>(0h0)) when _T_4783 : node _T_4784 = eq(_T_4781, UInt<1>(0h0)) when _T_4784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_4781, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_4785 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_4786 = asUInt(reset) node _T_4787 = eq(_T_4786, UInt<1>(0h0)) when _T_4787 : node _T_4788 = eq(_T_4785, UInt<1>(0h0)) when _T_4788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_4785, UInt<1>(0h1), "") : assert_203 else : node _T_4789 = eq(io.in.d.bits.size, c_size_lookup) node _T_4790 = asUInt(reset) node _T_4791 = eq(_T_4790, UInt<1>(0h0)) when _T_4791 : node _T_4792 = eq(_T_4789, UInt<1>(0h0)) when _T_4792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_4789, UInt<1>(0h1), "") : assert_204 node _T_4793 = and(io.in.d.valid, d_first_2) node _T_4794 = and(_T_4793, c_first_1) node _T_4795 = and(_T_4794, io.in.c.valid) node _T_4796 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_4797 = and(_T_4795, _T_4796) node _T_4798 = and(_T_4797, d_release_ack_1) node _T_4799 = eq(c_probe_ack, UInt<1>(0h0)) node _T_4800 = and(_T_4798, _T_4799) when _T_4800 : node _T_4801 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_4802 = or(_T_4801, io.in.c.ready) node _T_4803 = asUInt(reset) node _T_4804 = eq(_T_4803, UInt<1>(0h0)) when _T_4804 : node _T_4805 = eq(_T_4802, UInt<1>(0h0)) when _T_4805 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_4802, UInt<1>(0h1), "") : assert_205 node _T_4806 = orr(c_set_wo_ready) when _T_4806 : node _T_4807 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_4808 = asUInt(reset) node _T_4809 = eq(_T_4808, UInt<1>(0h0)) when _T_4809 : node _T_4810 = eq(_T_4807, UInt<1>(0h0)) when _T_4810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_4807, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_105 node _T_4811 = orr(inflight_1) node _T_4812 = eq(_T_4811, UInt<1>(0h0)) node _T_4813 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_4814 = or(_T_4812, _T_4813) node _T_4815 = lt(watchdog_1, plusarg_reader_1.out) node _T_4816 = or(_T_4814, _T_4815) node _T_4817 = asUInt(reset) node _T_4818 = eq(_T_4817, UInt<1>(0h0)) when _T_4818 : node _T_4819 = eq(_T_4816, UInt<1>(0h0)) when _T_4819 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_4816, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_4820 = and(io.in.c.ready, io.in.c.valid) node _T_4821 = and(io.in.d.ready, io.in.d.valid) node _T_4822 = or(_T_4820, _T_4821) when _T_4822 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_4823 = and(io.in.d.ready, io.in.d.valid) node _T_4824 = and(_T_4823, d_first_3) node _T_4825 = bits(io.in.d.bits.opcode, 2, 2) node _T_4826 = bits(io.in.d.bits.opcode, 1, 1) node _T_4827 = eq(_T_4826, UInt<1>(0h0)) node _T_4828 = and(_T_4825, _T_4827) node _T_4829 = and(_T_4824, _T_4828) when _T_4829 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_4830 = dshr(inflight_2, io.in.d.bits.sink) node _T_4831 = bits(_T_4830, 0, 0) node _T_4832 = eq(_T_4831, UInt<1>(0h0)) node _T_4833 = asUInt(reset) node _T_4834 = eq(_T_4833, UInt<1>(0h0)) when _T_4834 : node _T_4835 = eq(_T_4832, UInt<1>(0h0)) when _T_4835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_4832, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_4836 = and(io.in.e.ready, io.in.e.valid) node _T_4837 = and(_T_4836, UInt<1>(0h1)) node _T_4838 = and(_T_4837, UInt<1>(0h1)) when _T_4838 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_4839 = or(d_set, inflight_2) node _T_4840 = dshr(_T_4839, io.in.e.bits.sink) node _T_4841 = bits(_T_4840, 0, 0) node _T_4842 = asUInt(reset) node _T_4843 = eq(_T_4842, UInt<1>(0h0)) when _T_4843 : node _T_4844 = eq(_T_4841, UInt<1>(0h0)) when _T_4844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_4841, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_52( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_161 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_163 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_167 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_169 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_173 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_175 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_179 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_181 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_185 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_187 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_191 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_193 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_197 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_199 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_203 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_205 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_209 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_211 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_215 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_217 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_221 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_223 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_227 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_229 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_233 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_235 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_239 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_241 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_245 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_247 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_251 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_253 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_257 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_259 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_263 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_265 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_269 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_271 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_275 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_277 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_281 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_283 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_287 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_289 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_101 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_105 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_107 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_111 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_113 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_117 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_119 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_123 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_125 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_129 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_131 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_133 = 1'h1; // @[Parameters.scala:46:9] wire _legal_source_WIRE_23 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_319 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_321 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_325 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_327 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_331 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_333 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_337 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_339 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_343 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_345 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_349 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_351 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_355 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_357 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_361 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_363 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_367 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_369 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_373 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_375 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_379 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_381 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_385 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_387 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_391 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_393 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_397 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_399 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_403 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_405 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_409 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_411 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_415 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_417 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_421 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_423 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_427 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_429 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_433 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_435 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_439 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_441 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_445 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_447 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] io_in_b_bits_source = 9'h1E0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_242 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_243 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_244 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_245 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_246 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_247 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_248 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_249 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_250 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_251 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_252 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_253 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_254 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_255 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_256 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_257 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_258 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_259 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_260 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_261 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_262 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_263 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_1 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_2 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_3 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_4 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_5 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_6 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_7 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_8 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_9 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_10 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_11 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_12 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_13 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_14 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_15 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_16 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_17 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_18 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_19 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_20 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_uncommonBits_T_21 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _legal_source_T_158 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_182 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_183 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _legal_source_WIRE_1 = 9'h1E0; // @[Mux.scala:30:73] wire [8:0] _uncommonBits_T_264 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_265 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_266 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_267 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_268 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_269 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_270 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_271 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_272 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_273 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_274 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_275 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_276 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_277 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_278 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_279 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_280 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_281 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_282 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_283 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_284 = 9'h1E0; // @[Parameters.scala:52:29] wire [8:0] _uncommonBits_T_285 = 9'h1E0; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_26 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_28 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_30 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_34 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_36 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_40 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_42 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_44 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_46 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_48 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_50 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_52 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_54 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_56 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_58 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_60 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_62 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_64 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_66 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_68 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_70 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_72 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_74 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_76 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_78 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_80 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_82 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_84 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_86 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_88 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_90 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_92 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_94 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_96 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_98 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_100 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_102 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_104 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_106 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_108 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_110 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_112 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_114 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_116 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_118 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_120 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_122 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_124 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_126 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_128 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_130 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_132 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_134 = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_9 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_10 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_11 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_12 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_13 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_14 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_15 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_16 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_17 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_18 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_19 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_20 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_21 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_22 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_24 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_157 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_156 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [4:0] uncommonBits_248 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_249 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_250 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_251 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_252 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_253 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_256 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_257 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_258 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_259 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_260 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_261 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_262 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_263 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_6 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_7 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_8 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_9 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_10 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_11 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_14 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_15 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_16 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_17 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_18 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_19 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_20 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] legal_source_uncommonBits_21 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_270 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_271 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_272 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_273 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_274 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_275 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_278 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_279 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_280 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_281 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_282 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_283 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_284 = 5'h0; // @[Parameters.scala:52:56] wire [4:0] uncommonBits_285 = 5'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_242 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_243 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_244 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_245 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_246 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_247 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_254 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_255 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_4 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_5 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_12 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_13 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_264 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_265 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_266 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_267 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_268 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_269 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_276 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_277 = 2'h0; // @[Parameters.scala:52:56] wire [8:0] _legal_source_T_135 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_136 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_137 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_138 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_139 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_140 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_141 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_142 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_143 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_144 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_145 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_146 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_147 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_148 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_149 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_159 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_160 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_161 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_162 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_163 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_164 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_165 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_166 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_167 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_168 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_169 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_170 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_171 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_172 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_173 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_174 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_175 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_176 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_177 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_178 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_179 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_180 = 9'h0; // @[Mux.scala:30:73] wire [8:0] _legal_source_T_181 = 9'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_154 = 7'h0; // @[Mux.scala:30:73] wire [6:0] _legal_source_T_155 = 7'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_150 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_151 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_152 = 8'h0; // @[Mux.scala:30:73] wire [7:0] _legal_source_T_153 = 8'h0; // @[Mux.scala:30:73] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] _legal_source_T_37 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_43 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_49 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_55 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_61 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_67 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_85 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_91 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_97 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_103 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_109 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_115 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_121 = 4'hF; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_127 = 4'hF; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_1 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_7 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_13 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_19 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_25 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_31 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_73 = 7'h78; // @[Parameters.scala:54:10] wire [6:0] _legal_source_T_79 = 7'h78; // @[Parameters.scala:54:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_77 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_78 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_79 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_80 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_81 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_82 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_83 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_84 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_85 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_86 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_87 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_88 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_89 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_90 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_91 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_92 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_93 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_94 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_95 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_96 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_97 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_98 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_99 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_100 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_101 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_102 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_103 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_104 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_105 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_106 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_107 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_108 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_109 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_110 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_111 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_112 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_113 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_114 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_115 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_116 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_117 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_118 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_119 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_120 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_121 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_122 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_123 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_124 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_125 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_126 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_127 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_128 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_129 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_130 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_131 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_132 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_133 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_134 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_135 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_136 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_137 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_138 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_139 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_140 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_141 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_142 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_143 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_144 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_145 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_146 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_147 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_148 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_149 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_150 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_151 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_152 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_153 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_154 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_155 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_156 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_157 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_158 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_159 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_160 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_161 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_162 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_163 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_164 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_165 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_166 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_167 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_168 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_169 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_170 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_171 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_172 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_173 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_174 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_175 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_176 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_177 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_178 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_179 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_180 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_181 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_182 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_183 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_184 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_185 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_186 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_187 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_188 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_189 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_190 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_191 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_192 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_193 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_194 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_195 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_196 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_197 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_198 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_199 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_200 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_201 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_202 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_203 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_204 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_205 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_206 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_207 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_208 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_209 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_210 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_211 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_212 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_213 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_214 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_215 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_216 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_217 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_218 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_219 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_220 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_221 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_222 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_223 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_224 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_225 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_226 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_227 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_228 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_229 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_230 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_231 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_232 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_233 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_234 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_235 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_236 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_237 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_238 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_239 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_240 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_241 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_44 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_45 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_46 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_47 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_48 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_49 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_50 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_51 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_286 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_287 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_288 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_289 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_290 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_291 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_292 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_293 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_294 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_295 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_296 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_297 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_298 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_299 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_300 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_301 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_302 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_303 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_304 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_305 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_306 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_307 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_308 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_309 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_310 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_311 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_312 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_313 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_314 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_315 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_316 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_317 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_318 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_319 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_320 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_321 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_322 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_323 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_324 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_325 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_326 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_327 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_328 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_329 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_330 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_331 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_332 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_333 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_334 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_335 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_336 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_337 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_338 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_339 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_340 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_341 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_342 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_343 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_344 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_345 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_346 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_347 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_348 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_349 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_350 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_351 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_352 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_353 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_354 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_355 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_356 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_357 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_358 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_359 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_360 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_361 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_362 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_363 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_364 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_365 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_366 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_367 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_368 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_369 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_370 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_371 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_372 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_373 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_374 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_375 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_376 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_377 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_378 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_379 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_380 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_381 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_382 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_383 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_384 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_385 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_386 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_387 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_388 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_389 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_390 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_391 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_392 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_393 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_394 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _uncommonBits_T_395 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_22 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_23 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_24 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_25 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_26 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_27 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_28 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_29 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_30 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_31 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_32 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_33 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_34 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_35 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_36 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_37 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_38 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_39 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_40 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_41 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_42 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [8:0] _source_ok_uncommonBits_T_43 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_25 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_31 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_73 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_79 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_43 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_49 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_55 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_61 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_67 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_85 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_91 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_97 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_103 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_109 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_115 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_121 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_127 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_9 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_10 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_62 = _source_ok_T_61 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_11 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_12 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_13 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_14 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_15 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_16 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_17 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_18 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_110 = _source_ok_T_109 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_19 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_116 = _source_ok_T_115 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_118 = _source_ok_T_116; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_20 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_122 = _source_ok_T_121 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_124 = _source_ok_T_122; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_21 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_21 = _source_ok_uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_128 = _source_ok_T_127 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_130 = _source_ok_T_128; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_22 = _source_ok_T_132; // @[Parameters.scala:1138:31] wire _source_ok_T_133 = io_in_a_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_133; // @[Parameters.scala:1138:31] wire _source_ok_T_134 = io_in_a_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire _source_ok_T_135 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_156 = _source_ok_T_155 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_157 = _source_ok_T_156 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_157 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_72 = _uncommonBits_T_72[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_73 = _uncommonBits_T_73[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_74 = _uncommonBits_T_74[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_75 = _uncommonBits_T_75[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_76 = _uncommonBits_T_76[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_77 = _uncommonBits_T_77[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_80 = _uncommonBits_T_80[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_81 = _uncommonBits_T_81[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_82 = _uncommonBits_T_82[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_83 = _uncommonBits_T_83[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_84 = _uncommonBits_T_84[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_85 = _uncommonBits_T_85[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_86 = _uncommonBits_T_86[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_87 = _uncommonBits_T_87[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_88 = _uncommonBits_T_88[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_89 = _uncommonBits_T_89[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_94 = _uncommonBits_T_94[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_95 = _uncommonBits_T_95[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_96 = _uncommonBits_T_96[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_97 = _uncommonBits_T_97[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_98 = _uncommonBits_T_98[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_99 = _uncommonBits_T_99[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_102 = _uncommonBits_T_102[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_103 = _uncommonBits_T_103[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_104 = _uncommonBits_T_104[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_105 = _uncommonBits_T_105[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_106 = _uncommonBits_T_106[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_107 = _uncommonBits_T_107[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_108 = _uncommonBits_T_108[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_109 = _uncommonBits_T_109[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_110 = _uncommonBits_T_110[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_111 = _uncommonBits_T_111[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_116 = _uncommonBits_T_116[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_117 = _uncommonBits_T_117[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_118 = _uncommonBits_T_118[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_119 = _uncommonBits_T_119[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_120 = _uncommonBits_T_120[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_121 = _uncommonBits_T_121[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_123 = _uncommonBits_T_123[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_124 = _uncommonBits_T_124[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_125 = _uncommonBits_T_125[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_126 = _uncommonBits_T_126[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_127 = _uncommonBits_T_127[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_128 = _uncommonBits_T_128[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_129 = _uncommonBits_T_129[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_130 = _uncommonBits_T_130[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_131 = _uncommonBits_T_131[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_132 = _uncommonBits_T_132[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_133 = _uncommonBits_T_133[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_134 = _uncommonBits_T_134[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_135 = _uncommonBits_T_135[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_136 = _uncommonBits_T_136[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_137 = _uncommonBits_T_137[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_138 = _uncommonBits_T_138[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_139 = _uncommonBits_T_139[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_140 = _uncommonBits_T_140[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_141 = _uncommonBits_T_141[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_142 = _uncommonBits_T_142[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_143 = _uncommonBits_T_143[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_144 = _uncommonBits_T_144[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_145 = _uncommonBits_T_145[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_146 = _uncommonBits_T_146[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_147 = _uncommonBits_T_147[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_148 = _uncommonBits_T_148[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_149 = _uncommonBits_T_149[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_150 = _uncommonBits_T_150[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_151 = _uncommonBits_T_151[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_152 = _uncommonBits_T_152[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_153 = _uncommonBits_T_153[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_154 = _uncommonBits_T_154[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_155 = _uncommonBits_T_155[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_156 = _uncommonBits_T_156[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_157 = _uncommonBits_T_157[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_158 = _uncommonBits_T_158[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_159 = _uncommonBits_T_159[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_160 = _uncommonBits_T_160[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_161 = _uncommonBits_T_161[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_162 = _uncommonBits_T_162[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_163 = _uncommonBits_T_163[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_164 = _uncommonBits_T_164[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_165 = _uncommonBits_T_165[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_166 = _uncommonBits_T_166[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_167 = _uncommonBits_T_167[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_168 = _uncommonBits_T_168[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_169 = _uncommonBits_T_169[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_170 = _uncommonBits_T_170[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_171 = _uncommonBits_T_171[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_172 = _uncommonBits_T_172[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_173 = _uncommonBits_T_173[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_174 = _uncommonBits_T_174[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_175 = _uncommonBits_T_175[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_176 = _uncommonBits_T_176[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_177 = _uncommonBits_T_177[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_178 = _uncommonBits_T_178[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_179 = _uncommonBits_T_179[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_180 = _uncommonBits_T_180[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_181 = _uncommonBits_T_181[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_182 = _uncommonBits_T_182[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_183 = _uncommonBits_T_183[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_184 = _uncommonBits_T_184[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_185 = _uncommonBits_T_185[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_186 = _uncommonBits_T_186[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_187 = _uncommonBits_T_187[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_188 = _uncommonBits_T_188[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_189 = _uncommonBits_T_189[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_190 = _uncommonBits_T_190[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_191 = _uncommonBits_T_191[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_192 = _uncommonBits_T_192[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_193 = _uncommonBits_T_193[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_194 = _uncommonBits_T_194[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_195 = _uncommonBits_T_195[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_196 = _uncommonBits_T_196[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_197 = _uncommonBits_T_197[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_198 = _uncommonBits_T_198[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_199 = _uncommonBits_T_199[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_200 = _uncommonBits_T_200[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_201 = _uncommonBits_T_201[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_202 = _uncommonBits_T_202[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_203 = _uncommonBits_T_203[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_204 = _uncommonBits_T_204[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_205 = _uncommonBits_T_205[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_206 = _uncommonBits_T_206[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_207 = _uncommonBits_T_207[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_208 = _uncommonBits_T_208[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_209 = _uncommonBits_T_209[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_210 = _uncommonBits_T_210[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_211 = _uncommonBits_T_211[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_212 = _uncommonBits_T_212[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_213 = _uncommonBits_T_213[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_214 = _uncommonBits_T_214[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_215 = _uncommonBits_T_215[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_216 = _uncommonBits_T_216[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_217 = _uncommonBits_T_217[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_218 = _uncommonBits_T_218[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_219 = _uncommonBits_T_219[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_220 = _uncommonBits_T_220[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_221 = _uncommonBits_T_221[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_222 = _uncommonBits_T_222[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_223 = _uncommonBits_T_223[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_224 = _uncommonBits_T_224[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_225 = _uncommonBits_T_225[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_226 = _uncommonBits_T_226[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_227 = _uncommonBits_T_227[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_228 = _uncommonBits_T_228[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_229 = _uncommonBits_T_229[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_230 = _uncommonBits_T_230[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_231 = _uncommonBits_T_231[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_232 = _uncommonBits_T_232[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_233 = _uncommonBits_T_233[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_234 = _uncommonBits_T_234[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_235 = _uncommonBits_T_235[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_236 = _uncommonBits_T_236[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_237 = _uncommonBits_T_237[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_238 = _uncommonBits_T_238[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_239 = _uncommonBits_T_239[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_240 = _uncommonBits_T_240[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_241 = _uncommonBits_T_241[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_158 = io_in_d_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_158; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_22 = _source_ok_uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_159 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_165 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_171 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_177 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_183 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_189 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_231 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_237 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_160 = _source_ok_T_159 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_162 = _source_ok_T_160; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_164 = _source_ok_T_162; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_164; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_23 = _source_ok_uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_166 = _source_ok_T_165 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_168 = _source_ok_T_166; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_170 = _source_ok_T_168; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_170; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_24 = _source_ok_uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_172 = _source_ok_T_171 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_174 = _source_ok_T_172; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_176 = _source_ok_T_174; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_176; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_25 = _source_ok_uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_178 = _source_ok_T_177 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_180 = _source_ok_T_178; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_182 = _source_ok_T_180; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_182; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_26 = _source_ok_uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_184 = _source_ok_T_183 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_186 = _source_ok_T_184; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_188 = _source_ok_T_186; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_188; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_27 = _source_ok_uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_190 = _source_ok_T_189 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_192 = _source_ok_T_190; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_194 = _source_ok_T_192; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_194; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_28 = _source_ok_uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_195 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_201 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_207 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_213 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_219 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_225 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_243 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_249 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_255 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_261 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_267 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_273 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_279 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_285 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_196 = _source_ok_T_195 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_198 = _source_ok_T_196; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_200 = _source_ok_T_198; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_200; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_29 = _source_ok_uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_202 = _source_ok_T_201 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_204 = _source_ok_T_202; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_206 = _source_ok_T_204; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_206; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_30 = _source_ok_uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_208 = _source_ok_T_207 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_210 = _source_ok_T_208; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_212 = _source_ok_T_210; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_9 = _source_ok_T_212; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_31 = _source_ok_uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_214 = _source_ok_T_213 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_216 = _source_ok_T_214; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_218 = _source_ok_T_216; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_10 = _source_ok_T_218; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_32 = _source_ok_uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_220 = _source_ok_T_219 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_222 = _source_ok_T_220; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_224 = _source_ok_T_222; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_11 = _source_ok_T_224; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_33 = _source_ok_uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_226 = _source_ok_T_225 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_228 = _source_ok_T_226; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_230 = _source_ok_T_228; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_12 = _source_ok_T_230; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_34 = _source_ok_uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_232 = _source_ok_T_231 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_234 = _source_ok_T_232; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_236 = _source_ok_T_234; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_13 = _source_ok_T_236; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_35 = _source_ok_uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_238 = _source_ok_T_237 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_240 = _source_ok_T_238; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_242 = _source_ok_T_240; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_14 = _source_ok_T_242; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_36 = _source_ok_uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_244 = _source_ok_T_243 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_246 = _source_ok_T_244; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_248 = _source_ok_T_246; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_15 = _source_ok_T_248; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_37 = _source_ok_uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_250 = _source_ok_T_249 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_252 = _source_ok_T_250; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_254 = _source_ok_T_252; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_16 = _source_ok_T_254; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_38 = _source_ok_uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_256 = _source_ok_T_255 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_258 = _source_ok_T_256; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_260 = _source_ok_T_258; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_17 = _source_ok_T_260; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_39 = _source_ok_uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_262 = _source_ok_T_261 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_264 = _source_ok_T_262; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_266 = _source_ok_T_264; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_18 = _source_ok_T_266; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_40 = _source_ok_uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_268 = _source_ok_T_267 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_270 = _source_ok_T_268; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_272 = _source_ok_T_270; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_19 = _source_ok_T_272; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_41 = _source_ok_uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_274 = _source_ok_T_273 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_276 = _source_ok_T_274; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_278 = _source_ok_T_276; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_20 = _source_ok_T_278; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_42 = _source_ok_uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_280 = _source_ok_T_279 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_282 = _source_ok_T_280; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_284 = _source_ok_T_282; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_21 = _source_ok_T_284; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_43 = _source_ok_uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_286 = _source_ok_T_285 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_288 = _source_ok_T_286; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_290 = _source_ok_T_288; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_22 = _source_ok_T_290; // @[Parameters.scala:1138:31] wire _source_ok_T_291 = io_in_d_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_291; // @[Parameters.scala:1138:31] wire _source_ok_T_292 = io_in_d_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_292; // @[Parameters.scala:1138:31] wire _source_ok_T_293 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_294 = _source_ok_T_293 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_295 = _source_ok_T_294 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_296 = _source_ok_T_295 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_297 = _source_ok_T_296 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_298 = _source_ok_T_297 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_299 = _source_ok_T_298 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_300 = _source_ok_T_299 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_301 = _source_ok_T_300 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_302 = _source_ok_T_301 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_303 = _source_ok_T_302 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_304 = _source_ok_T_303 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_305 = _source_ok_T_304 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_306 = _source_ok_T_305 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_307 = _source_ok_T_306 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_308 = _source_ok_T_307 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_309 = _source_ok_T_308 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_310 = _source_ok_T_309 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_311 = _source_ok_T_310 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_312 = _source_ok_T_311 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_313 = _source_ok_T_312 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_314 = _source_ok_T_313 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_315 = _source_ok_T_314 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_315 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_316 = io_in_c_bits_source_0 == 9'h1D0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_316; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_44 = _source_ok_uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [6:0] _source_ok_T_317 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_323 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_329 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_335 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_341 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_347 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_389 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire [6:0] _source_ok_T_395 = io_in_c_bits_source_0[8:2]; // @[Monitor.scala:36:7] wire _source_ok_T_318 = _source_ok_T_317 == 7'h70; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_320 = _source_ok_T_318; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_322 = _source_ok_T_320; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_322; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_45 = _source_ok_uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_324 = _source_ok_T_323 == 7'h71; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_326 = _source_ok_T_324; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_328 = _source_ok_T_326; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_328; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_46 = _source_ok_uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_330 = _source_ok_T_329 == 7'h72; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_332 = _source_ok_T_330; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_334 = _source_ok_T_332; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_334; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_47 = _source_ok_uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_336 = _source_ok_T_335 == 7'h73; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_338 = _source_ok_T_336; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_340 = _source_ok_T_338; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_340; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_48 = _source_ok_uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_342 = _source_ok_T_341 == 7'h7C; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_344 = _source_ok_T_342; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_346 = _source_ok_T_344; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_346; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_49 = _source_ok_uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_348 = _source_ok_T_347 == 7'h7B; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_350 = _source_ok_T_348; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_352 = _source_ok_T_350; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_6 = _source_ok_T_352; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_50 = _source_ok_uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_353 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_359 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_365 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_371 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_377 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_383 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_401 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_407 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_413 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_419 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_425 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_431 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_437 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_443 = io_in_c_bits_source_0[8:5]; // @[Monitor.scala:36:7] wire _source_ok_T_354 = _source_ok_T_353 == 4'hD; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_356 = _source_ok_T_354; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_358 = _source_ok_T_356; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_7 = _source_ok_T_358; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_51 = _source_ok_uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_360 = _source_ok_T_359 == 4'hC; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_362 = _source_ok_T_360; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_364 = _source_ok_T_362; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_8 = _source_ok_T_364; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_52 = _source_ok_uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_366 = _source_ok_T_365 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_368 = _source_ok_T_366; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_370 = _source_ok_T_368; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_9 = _source_ok_T_370; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_53 = _source_ok_uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_372 = _source_ok_T_371 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_374 = _source_ok_T_372; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_376 = _source_ok_T_374; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_10 = _source_ok_T_376; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_54 = _source_ok_uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_378 = _source_ok_T_377 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_380 = _source_ok_T_378; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_382 = _source_ok_T_380; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_11 = _source_ok_T_382; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_55 = _source_ok_uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_384 = _source_ok_T_383 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_386 = _source_ok_T_384; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_388 = _source_ok_T_386; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_12 = _source_ok_T_388; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_56 = _source_ok_uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_390 = _source_ok_T_389 == 7'h7A; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_392 = _source_ok_T_390; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_394 = _source_ok_T_392; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_13 = _source_ok_T_394; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_57 = _source_ok_uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_396 = _source_ok_T_395 == 7'h79; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_398 = _source_ok_T_396; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_400 = _source_ok_T_398; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_14 = _source_ok_T_400; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_58 = _source_ok_uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_402 = _source_ok_T_401 == 4'h7; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_404 = _source_ok_T_402; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_406 = _source_ok_T_404; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_15 = _source_ok_T_406; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_59 = _source_ok_uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_408 = _source_ok_T_407 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_410 = _source_ok_T_408; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_412 = _source_ok_T_410; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_16 = _source_ok_T_412; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_60 = _source_ok_uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_414 = _source_ok_T_413 == 4'h5; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_416 = _source_ok_T_414; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_418 = _source_ok_T_416; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_17 = _source_ok_T_418; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_61 = _source_ok_uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_420 = _source_ok_T_419 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_422 = _source_ok_T_420; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_424 = _source_ok_T_422; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_18 = _source_ok_T_424; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_62 = _source_ok_uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_426 = _source_ok_T_425 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_428 = _source_ok_T_426; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_430 = _source_ok_T_428; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_19 = _source_ok_T_430; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_63 = _source_ok_uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_432 = _source_ok_T_431 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_434 = _source_ok_T_432; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_436 = _source_ok_T_434; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_20 = _source_ok_T_436; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_64 = _source_ok_uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_438 = _source_ok_T_437 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_440 = _source_ok_T_438; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_442 = _source_ok_T_440; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_21 = _source_ok_T_442; // @[Parameters.scala:1138:31] wire [4:0] source_ok_uncommonBits_65 = _source_ok_uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_444 = _source_ok_T_443 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_446 = _source_ok_T_444; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_448 = _source_ok_T_446; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_22 = _source_ok_T_448; // @[Parameters.scala:1138:31] wire _source_ok_T_449 = io_in_c_bits_source_0 == 9'h1E0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_23 = _source_ok_T_449; // @[Parameters.scala:1138:31] wire _source_ok_T_450 = io_in_c_bits_source_0 == 9'h1E2; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_24 = _source_ok_T_450; // @[Parameters.scala:1138:31] wire _source_ok_T_451 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_452 = _source_ok_T_451 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_453 = _source_ok_T_452 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_454 = _source_ok_T_453 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_455 = _source_ok_T_454 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_456 = _source_ok_T_455 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_457 = _source_ok_T_456 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_458 = _source_ok_T_457 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_459 = _source_ok_T_458 | _source_ok_WIRE_2_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_460 = _source_ok_T_459 | _source_ok_WIRE_2_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_461 = _source_ok_T_460 | _source_ok_WIRE_2_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_462 = _source_ok_T_461 | _source_ok_WIRE_2_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_463 = _source_ok_T_462 | _source_ok_WIRE_2_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_464 = _source_ok_T_463 | _source_ok_WIRE_2_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_465 = _source_ok_T_464 | _source_ok_WIRE_2_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_466 = _source_ok_T_465 | _source_ok_WIRE_2_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_467 = _source_ok_T_466 | _source_ok_WIRE_2_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_468 = _source_ok_T_467 | _source_ok_WIRE_2_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_469 = _source_ok_T_468 | _source_ok_WIRE_2_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_470 = _source_ok_T_469 | _source_ok_WIRE_2_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_471 = _source_ok_T_470 | _source_ok_WIRE_2_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_472 = _source_ok_T_471 | _source_ok_WIRE_2_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_473 = _source_ok_T_472 | _source_ok_WIRE_2_23; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_473 | _source_ok_WIRE_2_24; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_286 = _uncommonBits_T_286[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_287 = _uncommonBits_T_287[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_288 = _uncommonBits_T_288[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_289 = _uncommonBits_T_289[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_290 = _uncommonBits_T_290[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_291 = _uncommonBits_T_291[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_292 = _uncommonBits_T_292[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_293 = _uncommonBits_T_293[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_294 = _uncommonBits_T_294[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_295 = _uncommonBits_T_295[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_296 = _uncommonBits_T_296[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_297 = _uncommonBits_T_297[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_298 = _uncommonBits_T_298[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_299 = _uncommonBits_T_299[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_300 = _uncommonBits_T_300[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_301 = _uncommonBits_T_301[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_302 = _uncommonBits_T_302[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_303 = _uncommonBits_T_303[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_304 = _uncommonBits_T_304[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_305 = _uncommonBits_T_305[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_306 = _uncommonBits_T_306[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_307 = _uncommonBits_T_307[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_308 = _uncommonBits_T_308[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_309 = _uncommonBits_T_309[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_310 = _uncommonBits_T_310[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_311 = _uncommonBits_T_311[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_312 = _uncommonBits_T_312[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_313 = _uncommonBits_T_313[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_314 = _uncommonBits_T_314[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_315 = _uncommonBits_T_315[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_316 = _uncommonBits_T_316[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_317 = _uncommonBits_T_317[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_318 = _uncommonBits_T_318[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_319 = _uncommonBits_T_319[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_320 = _uncommonBits_T_320[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_321 = _uncommonBits_T_321[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_322 = _uncommonBits_T_322[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_323 = _uncommonBits_T_323[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_324 = _uncommonBits_T_324[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_325 = _uncommonBits_T_325[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_326 = _uncommonBits_T_326[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_327 = _uncommonBits_T_327[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_328 = _uncommonBits_T_328[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_329 = _uncommonBits_T_329[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_330 = _uncommonBits_T_330[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_331 = _uncommonBits_T_331[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_332 = _uncommonBits_T_332[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_333 = _uncommonBits_T_333[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_334 = _uncommonBits_T_334[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_335 = _uncommonBits_T_335[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_336 = _uncommonBits_T_336[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_337 = _uncommonBits_T_337[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_338 = _uncommonBits_T_338[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_339 = _uncommonBits_T_339[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_340 = _uncommonBits_T_340[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_341 = _uncommonBits_T_341[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_342 = _uncommonBits_T_342[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_343 = _uncommonBits_T_343[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_344 = _uncommonBits_T_344[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_345 = _uncommonBits_T_345[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_346 = _uncommonBits_T_346[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_347 = _uncommonBits_T_347[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_348 = _uncommonBits_T_348[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_349 = _uncommonBits_T_349[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_350 = _uncommonBits_T_350[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_351 = _uncommonBits_T_351[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_352 = _uncommonBits_T_352[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_353 = _uncommonBits_T_353[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_354 = _uncommonBits_T_354[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_355 = _uncommonBits_T_355[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_356 = _uncommonBits_T_356[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_357 = _uncommonBits_T_357[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_358 = _uncommonBits_T_358[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_359 = _uncommonBits_T_359[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_360 = _uncommonBits_T_360[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_361 = _uncommonBits_T_361[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_362 = _uncommonBits_T_362[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_363 = _uncommonBits_T_363[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_364 = _uncommonBits_T_364[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_365 = _uncommonBits_T_365[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_366 = _uncommonBits_T_366[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_367 = _uncommonBits_T_367[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_368 = _uncommonBits_T_368[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_369 = _uncommonBits_T_369[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_370 = _uncommonBits_T_370[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_371 = _uncommonBits_T_371[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_372 = _uncommonBits_T_372[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_373 = _uncommonBits_T_373[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_374 = _uncommonBits_T_374[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_375 = _uncommonBits_T_375[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_376 = _uncommonBits_T_376[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_377 = _uncommonBits_T_377[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_378 = _uncommonBits_T_378[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_379 = _uncommonBits_T_379[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_380 = _uncommonBits_T_380[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_381 = _uncommonBits_T_381[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_382 = _uncommonBits_T_382[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_383 = _uncommonBits_T_383[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_384 = _uncommonBits_T_384[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_385 = _uncommonBits_T_385[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_386 = _uncommonBits_T_386[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_387 = _uncommonBits_T_387[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_388 = _uncommonBits_T_388[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_389 = _uncommonBits_T_389[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_390 = _uncommonBits_T_390[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_391 = _uncommonBits_T_391[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_392 = _uncommonBits_T_392[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_393 = _uncommonBits_T_393[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_394 = _uncommonBits_T_394[4:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_395 = _uncommonBits_T_395[4:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_4749 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_4749; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_4749; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [8:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_4823 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_4823; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_4823; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [8:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_4820 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_4820; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_4820; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [8:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [499:0] inflight; // @[Monitor.scala:614:27] reg [1999:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1999:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [499:0] a_set; // @[Monitor.scala:626:34] wire [499:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [1999:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1999:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [11:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [1999:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [1999:0] _a_opcode_lookup_T_6 = {1996'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [1999:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1999:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [1999:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1999:0] _a_size_lookup_T_6 = {1996'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [1999:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1999:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [511:0] _GEN_5 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [511:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4675 = _T_4749 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_4675 ? _a_set_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_4675 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_4675 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [11:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_4675 ? _a_opcodes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_4675 ? _a_sizes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [499:0] d_clr; // @[Monitor.scala:664:34] wire [499:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [1999:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1999:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_4721 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [511:0] _GEN_8 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_4721 & ~d_release_ack ? _d_clr_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4690 = _T_4823 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_4690 ? _d_clr_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_4690 ? _d_opcodes_clr_T_5[1999:0] : 2000'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_4690 ? _d_sizes_clr_T_5[1999:0] : 2000'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [499:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [499:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [499:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [1999:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [1999:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [1999:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1999:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1999:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1999:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [499:0] inflight_1; // @[Monitor.scala:726:35] reg [1999:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [1999:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [499:0] c_set; // @[Monitor.scala:738:34] wire [499:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [1999:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [1999:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [1999:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [1999:0] _c_opcode_lookup_T_6 = {1996'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [1999:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1999:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1999:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1999:0] _c_size_lookup_T_6 = {1996'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [1999:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1999:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [511:0] _GEN_9 = 512'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [511:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [511:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4762 = _T_4820 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_4762 ? _c_set_T[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_4762 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_4762 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [11:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [11:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [11:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [4098:0] _c_opcodes_set_T_1 = {4095'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_4762 ? _c_opcodes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [4098:0] _c_sizes_set_T_1 = {4095'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_4762 ? _c_sizes_set_T_1[1999:0] : 2000'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [499:0] d_clr_1; // @[Monitor.scala:774:34] wire [499:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [1999:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1999:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_4793 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_4793 & d_release_ack_1 ? _d_clr_wo_ready_T_1[499:0] : 500'h0; // @[OneHot.scala:58:35] wire _T_4775 = _T_4823 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_4775 ? _d_clr_T_1[499:0] : 500'h0; // @[OneHot.scala:58:35] wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_4775 ? _d_opcodes_clr_T_11[1999:0] : 2000'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_4775 ? _d_sizes_clr_T_11[1999:0] : 2000'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [499:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [499:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [499:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [1999:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [1999:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [1999:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1999:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [1999:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1999:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_4829 = _T_4823 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_4829 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_16 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_16 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i1_e8_s24_16(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_16 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_9 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue2_EgressFlit_9 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31) node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34) node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h9), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h5), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h15), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h3), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h11), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0hf), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h17), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0hb), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37) node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38) node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39) node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40) node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41) node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42) node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43) node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44) node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45) node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46) node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow

module EgressUnit_9( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_91 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_216 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_217 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_218 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_219 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_91( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module SourceD_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<128>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, flip bs_rdat : { data : UInt<128>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_wdat : { data : UInt<128>}, flip evict_req : { set : UInt<11>, way : UInt<4>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<11>, way : UInt<4>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<2>, clock, reset, UInt<2>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<2> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<2>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<4>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 3, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node s1_mask_sub_0_1 = geq(s1_req.size, UInt<3>(0h4)) node s1_mask_size = bits(s1_mask_sizeOH, 3, 3) node s1_mask_bit = bits(s1_req.offset, 3, 3) node s1_mask_nbit = eq(s1_mask_bit, UInt<1>(0h0)) node s1_mask_eq = and(UInt<1>(0h1), s1_mask_nbit) node _s1_mask_acc_T = and(s1_mask_size, s1_mask_eq) node s1_mask_acc = or(s1_mask_sub_0_1, _s1_mask_acc_T) node s1_mask_eq_1 = and(UInt<1>(0h1), s1_mask_bit) node _s1_mask_acc_T_1 = and(s1_mask_size, s1_mask_eq_1) node s1_mask_acc_1 = or(s1_mask_sub_0_1, _s1_mask_acc_T_1) node _s1_mask_T = cat(s1_mask_acc_1, s1_mask_acc) node _s1_mask_T_1 = not(s1_bypass) node s1_mask = and(_s1_mask_T, _s1_mask_T_1) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 4) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 4) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded_6 connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<2>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<2>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<16>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node _T_18 = eq(io.rel_pop.ready, UInt<1>(0h0)) node _T_19 = and(io.rel_pop.valid, _T_18) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_20 = and(s2_valid, s3_ready) when _T_20 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_21 = eq(s3_ready, UInt<1>(0h0)) node _T_22 = and(s2_valid, _T_21) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<2>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<2>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass, 1, 1) node _s3_rdata_T_2 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_3 = bits(s3_bypass_data, 127, 64) node _s3_rdata_T_4 = bits(queue.io.deq.bits.data, 63, 0) node _s3_rdata_T_5 = bits(queue.io.deq.bits.data, 127, 64) node _s3_rdata_T_6 = mux(_s3_rdata_T, _s3_rdata_T_2, _s3_rdata_T_4) node _s3_rdata_T_7 = mux(_s3_rdata_T_1, _s3_rdata_T_3, _s3_rdata_T_5) node s3_rdata = cat(_s3_rdata_T_7, _s3_rdata_T_6) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_23 = eq(s3_full, UInt<1>(0h0)) node _T_24 = eq(s3_need_r, UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = or(_T_25, queue.io.deq.valid) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1 assert(clock, _T_26, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_30 = and(s3_valid, s4_ready) when _T_30 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_31 = eq(s4_ready, UInt<1>(0h0)) node _T_32 = and(s3_valid, _T_31) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<2>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<128>, mask : UInt<16>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<128>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics_6 connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = bits(s4_pdata.mask, 8, 8) node _io_bs_wadr_bits_mask_T_9 = bits(s4_pdata.mask, 9, 9) node _io_bs_wadr_bits_mask_T_10 = bits(s4_pdata.mask, 10, 10) node _io_bs_wadr_bits_mask_T_11 = bits(s4_pdata.mask, 11, 11) node _io_bs_wadr_bits_mask_T_12 = bits(s4_pdata.mask, 12, 12) node _io_bs_wadr_bits_mask_T_13 = bits(s4_pdata.mask, 13, 13) node _io_bs_wadr_bits_mask_T_14 = bits(s4_pdata.mask, 14, 14) node _io_bs_wadr_bits_mask_T_15 = bits(s4_pdata.mask, 15, 15) node _io_bs_wadr_bits_mask_T_16 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_17 = or(_io_bs_wadr_bits_mask_T_16, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_18 = or(_io_bs_wadr_bits_mask_T_17, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_19 = or(_io_bs_wadr_bits_mask_T_18, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_20 = or(_io_bs_wadr_bits_mask_T_19, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_21 = or(_io_bs_wadr_bits_mask_T_20, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_22 = or(_io_bs_wadr_bits_mask_T_21, _io_bs_wadr_bits_mask_T_7) node _io_bs_wadr_bits_mask_T_23 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_9) node _io_bs_wadr_bits_mask_T_24 = or(_io_bs_wadr_bits_mask_T_23, _io_bs_wadr_bits_mask_T_10) node _io_bs_wadr_bits_mask_T_25 = or(_io_bs_wadr_bits_mask_T_24, _io_bs_wadr_bits_mask_T_11) node _io_bs_wadr_bits_mask_T_26 = or(_io_bs_wadr_bits_mask_T_25, _io_bs_wadr_bits_mask_T_12) node _io_bs_wadr_bits_mask_T_27 = or(_io_bs_wadr_bits_mask_T_26, _io_bs_wadr_bits_mask_T_13) node _io_bs_wadr_bits_mask_T_28 = or(_io_bs_wadr_bits_mask_T_27, _io_bs_wadr_bits_mask_T_14) node _io_bs_wadr_bits_mask_T_29 = or(_io_bs_wadr_bits_mask_T_28, _io_bs_wadr_bits_mask_T_15) node _io_bs_wadr_bits_mask_T_30 = cat(_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_30 connect io.bs_wdat.data, atomics.io.data_out node _T_33 = and(s4_full, s4_need_pb) node _T_34 = and(_T_33, s4_pdata.corrupt) node _T_35 = eq(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _T_39 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_40 = and(io.bs_wadr.valid, _T_39) node _T_41 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_42 = and(s4_req.prio[0], _T_41) node _T_43 = eq(s4_req.param, UInt<3>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_46 = and(s4_req.prio[0], _T_45) node _T_47 = eq(s4_req.param, UInt<3>(0h1)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_50 = and(s4_req.prio[0], _T_49) node _T_51 = eq(s4_req.param, UInt<3>(0h2)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_54 = and(s4_req.prio[0], _T_53) node _T_55 = eq(s4_req.param, UInt<3>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_58 = and(s4_req.prio[0], _T_57) node _T_59 = eq(s4_req.param, UInt<3>(0h4)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_62 = and(s4_req.prio[0], _T_61) node _T_63 = eq(s4_req.param, UInt<3>(0h0)) node _T_64 = and(_T_62, _T_63) node _T_65 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_66 = and(s4_req.prio[0], _T_65) node _T_67 = eq(s4_req.param, UInt<3>(0h1)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_70 = and(s4_req.prio[0], _T_69) node _T_71 = eq(s4_req.param, UInt<3>(0h2)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_74 = and(s4_req.prio[0], _T_73) node _T_75 = eq(s4_req.param, UInt<3>(0h3)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(s4_need_bs, UInt<1>(0h0)) node _T_78 = or(io.bs_wadr.ready, _T_77) when _T_78 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<2>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<128>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<2>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<128>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<128>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<4>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 3, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass_sub_0_1 = geq(pre_s4_req.size, UInt<3>(0h4)) node pre_s3_4_bypass_size = bits(pre_s3_4_bypass_sizeOH, 3, 3) node pre_s3_4_bypass_bit = bits(pre_s4_req.offset, 3, 3) node pre_s3_4_bypass_nbit = eq(pre_s3_4_bypass_bit, UInt<1>(0h0)) node pre_s3_4_bypass_eq = and(UInt<1>(0h1), pre_s3_4_bypass_nbit) node _pre_s3_4_bypass_acc_T = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq) node pre_s3_4_bypass_acc = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T) node pre_s3_4_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_4_bypass_bit) node _pre_s3_4_bypass_acc_T_1 = and(pre_s3_4_bypass_size, pre_s3_4_bypass_eq_1) node pre_s3_4_bypass_acc_1 = or(pre_s3_4_bypass_sub_0_1, _pre_s3_4_bypass_acc_T_1) node _pre_s3_4_bypass_T = cat(pre_s3_4_bypass_acc_1, pre_s3_4_bypass_acc) node pre_s3_4_bypass = mux(pre_s3_4_match, _pre_s3_4_bypass_T, UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<4>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 3, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass_sub_0_1 = geq(pre_s5_req.size, UInt<3>(0h4)) node pre_s3_5_bypass_size = bits(pre_s3_5_bypass_sizeOH, 3, 3) node pre_s3_5_bypass_bit = bits(pre_s5_req.offset, 3, 3) node pre_s3_5_bypass_nbit = eq(pre_s3_5_bypass_bit, UInt<1>(0h0)) node pre_s3_5_bypass_eq = and(UInt<1>(0h1), pre_s3_5_bypass_nbit) node _pre_s3_5_bypass_acc_T = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq) node pre_s3_5_bypass_acc = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T) node pre_s3_5_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_5_bypass_bit) node _pre_s3_5_bypass_acc_T_1 = and(pre_s3_5_bypass_size, pre_s3_5_bypass_eq_1) node pre_s3_5_bypass_acc_1 = or(pre_s3_5_bypass_sub_0_1, _pre_s3_5_bypass_acc_T_1) node _pre_s3_5_bypass_T = cat(pre_s3_5_bypass_acc_1, pre_s3_5_bypass_acc) node pre_s3_5_bypass = mux(pre_s3_5_match, _pre_s3_5_bypass_T, UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<4>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 3, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass_sub_0_1 = geq(pre_s6_req.size, UInt<3>(0h4)) node pre_s3_6_bypass_size = bits(pre_s3_6_bypass_sizeOH, 3, 3) node pre_s3_6_bypass_bit = bits(pre_s6_req.offset, 3, 3) node pre_s3_6_bypass_nbit = eq(pre_s3_6_bypass_bit, UInt<1>(0h0)) node pre_s3_6_bypass_eq = and(UInt<1>(0h1), pre_s3_6_bypass_nbit) node _pre_s3_6_bypass_acc_T = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq) node pre_s3_6_bypass_acc = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T) node pre_s3_6_bypass_eq_1 = and(UInt<1>(0h1), pre_s3_6_bypass_bit) node _pre_s3_6_bypass_acc_T_1 = and(pre_s3_6_bypass_size, pre_s3_6_bypass_eq_1) node pre_s3_6_bypass_acc_1 = or(pre_s3_6_bypass_sub_0_1, _pre_s3_6_bypass_acc_T_1) node _pre_s3_6_bypass_T = cat(pre_s3_6_bypass_acc_1, pre_s3_6_bypass_acc) node pre_s3_6_bypass = mux(pre_s3_6_match, _pre_s3_6_bypass_T, UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s3_6_bypass, 1, 1) node _s3_bypass_data_T_2 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_3 = bits(pre_s6_dat, 127, 64) node _s3_bypass_data_T_4 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_5 = bits(pre_s7_dat, 127, 64) node _s3_bypass_data_T_6 = mux(_s3_bypass_data_T, _s3_bypass_data_T_2, _s3_bypass_data_T_4) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_1, _s3_bypass_data_T_3, _s3_bypass_data_T_5) node _s3_bypass_data_T_8 = cat(_s3_bypass_data_T_7, _s3_bypass_data_T_6) node _s3_bypass_data_T_9 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_10 = bits(pre_s3_5_bypass, 1, 1) node _s3_bypass_data_T_11 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_12 = bits(pre_s5_dat, 127, 64) node _s3_bypass_data_T_13 = bits(_s3_bypass_data_T_8, 63, 0) node _s3_bypass_data_T_14 = bits(_s3_bypass_data_T_8, 127, 64) node _s3_bypass_data_T_15 = mux(_s3_bypass_data_T_9, _s3_bypass_data_T_11, _s3_bypass_data_T_13) node _s3_bypass_data_T_16 = mux(_s3_bypass_data_T_10, _s3_bypass_data_T_12, _s3_bypass_data_T_14) node _s3_bypass_data_T_17 = cat(_s3_bypass_data_T_16, _s3_bypass_data_T_15) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_17 node _s3_bypass_data_T_18 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_19 = bits(s3_bypass_data_REG, 1, 1) node _s3_bypass_data_T_20 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_21 = bits(atomics.io.data_out, 127, 64) node _s3_bypass_data_T_22 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_23 = bits(s3_bypass_data_REG_1, 127, 64) node _s3_bypass_data_T_24 = mux(_s3_bypass_data_T_18, _s3_bypass_data_T_20, _s3_bypass_data_T_22) node _s3_bypass_data_T_25 = mux(_s3_bypass_data_T_19, _s3_bypass_data_T_21, _s3_bypass_data_T_23) node _s3_bypass_data_T_26 = cat(_s3_bypass_data_T_25, _s3_bypass_data_T_24) connect s3_bypass_data, _s3_bypass_data_T_26 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_79 = and(io.req.valid, s2) node _T_80 = and(_T_79, s3) node _T_81 = and(_T_80, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_82 = and(io.req.valid, s2_1) node _T_83 = and(_T_82, s3_1) node _T_84 = and(_T_83, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_85 = and(io.req.valid, s2_2) node _T_86 = and(_T_85, s3_2) node _T_87 = and(_T_86, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_88 = and(io.req.valid, s2_3) node _T_89 = and(_T_88, s3_3) node _T_90 = and(_T_89, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_91 = and(io.req.valid, s2_4) node _T_92 = and(_T_91, s3_4) node _T_93 = and(_T_92, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_94 = and(io.req.valid, s2_5) node _T_95 = and(_T_94, s3_5) node _T_96 = and(_T_95, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_97 = and(io.req.valid, s2_6) node _T_98 = and(_T_97, s3_6) node _T_99 = and(_T_98, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_100 = and(io.req.valid, s2_7) node _T_101 = and(_T_100, s3_7) node _T_102 = and(_T_101, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<4>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 3, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass_sub_0_1 = geq(s2_req.size, UInt<3>(0h4)) node s1_2_bypass_size = bits(s1_2_bypass_sizeOH, 3, 3) node s1_2_bypass_bit = bits(s2_req.offset, 3, 3) node s1_2_bypass_nbit = eq(s1_2_bypass_bit, UInt<1>(0h0)) node s1_2_bypass_eq = and(UInt<1>(0h1), s1_2_bypass_nbit) node _s1_2_bypass_acc_T = and(s1_2_bypass_size, s1_2_bypass_eq) node s1_2_bypass_acc = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T) node s1_2_bypass_eq_1 = and(UInt<1>(0h1), s1_2_bypass_bit) node _s1_2_bypass_acc_T_1 = and(s1_2_bypass_size, s1_2_bypass_eq_1) node s1_2_bypass_acc_1 = or(s1_2_bypass_sub_0_1, _s1_2_bypass_acc_T_1) node _s1_2_bypass_T = cat(s1_2_bypass_acc_1, s1_2_bypass_acc) node s1_2_bypass = mux(s1_2_match, _s1_2_bypass_T, UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<4>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 3, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass_sub_0_1 = geq(s3_req.size, UInt<3>(0h4)) node s1_3_bypass_size = bits(s1_3_bypass_sizeOH, 3, 3) node s1_3_bypass_bit = bits(s3_req.offset, 3, 3) node s1_3_bypass_nbit = eq(s1_3_bypass_bit, UInt<1>(0h0)) node s1_3_bypass_eq = and(UInt<1>(0h1), s1_3_bypass_nbit) node _s1_3_bypass_acc_T = and(s1_3_bypass_size, s1_3_bypass_eq) node s1_3_bypass_acc = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T) node s1_3_bypass_eq_1 = and(UInt<1>(0h1), s1_3_bypass_bit) node _s1_3_bypass_acc_T_1 = and(s1_3_bypass_size, s1_3_bypass_eq_1) node s1_3_bypass_acc_1 = or(s1_3_bypass_sub_0_1, _s1_3_bypass_acc_T_1) node _s1_3_bypass_T = cat(s1_3_bypass_acc_1, s1_3_bypass_acc) node s1_3_bypass = mux(s1_3_match, _s1_3_bypass_T, UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<4>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 3, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass_sub_0_1 = geq(s4_req.size, UInt<3>(0h4)) node s1_4_bypass_size = bits(s1_4_bypass_sizeOH, 3, 3) node s1_4_bypass_bit = bits(s4_req.offset, 3, 3) node s1_4_bypass_nbit = eq(s1_4_bypass_bit, UInt<1>(0h0)) node s1_4_bypass_eq = and(UInt<1>(0h1), s1_4_bypass_nbit) node _s1_4_bypass_acc_T = and(s1_4_bypass_size, s1_4_bypass_eq) node s1_4_bypass_acc = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T) node s1_4_bypass_eq_1 = and(UInt<1>(0h1), s1_4_bypass_bit) node _s1_4_bypass_acc_T_1 = and(s1_4_bypass_size, s1_4_bypass_eq_1) node s1_4_bypass_acc_1 = or(s1_4_bypass_sub_0_1, _s1_4_bypass_acc_T_1) node _s1_4_bypass_T = cat(s1_4_bypass_acc_1, s1_4_bypass_acc) node s1_4_bypass = mux(s1_4_match, _s1_4_bypass_T, UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22

module SourceD_6( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [8:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [10:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [3:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [10:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [10:0] io_evict_req_set, // @[SourceD.scala:50:14] input [3:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [10:0] io_grant_req_set, // @[SourceD.scala:50:14] input [3:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [10:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [3:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [10:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [3:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [3:0] s1_req_way; // @[SourceD.scala:88:19] wire [10:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [10:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [8:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [10:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [8:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 | _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 | _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = |s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [8:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [10:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [3:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [8:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [10:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [3:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [8:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [10:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [8:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [10:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [3:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [8:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [10:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 | _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 | _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 | _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 | _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 | _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 | _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]

Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_11 : input clock : Clock input reset : Reset output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<4>(0hf)) when _T : connect doing_reset, UInt<1>(0h0) reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0)) node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0) wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect f2_entry, entries[_f2_entry_T_1] node _T_1 = eq(io.update_idx, io.f2_req_idx) node _T_2 = and(io.update_repair, _T_1) when _T_2 : connect f2_entry.s_cnt, io.update_meta.s_cnt else : node _T_3 = eq(io.update_idx, io.f2_req_idx) node _T_4 = and(io.update_mispredict, _T_3) when _T_4 : connect f2_entry.s_cnt, UInt<1>(0h0) reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f3_entry, f2_entry reg f3_scnt_REG : UInt, clock connect f3_scnt_REG, io.f2_req_idx node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) node _f3_tag_T = bits(io.f2_req_idx, 13, 4) reg f3_tag : UInt, clock connect f3_tag, _f3_tag_T connect io.f3_pred, io.f3_pred_in connect io.f3_meta.s_cnt, f3_scnt node _T_5 = eq(f3_entry.tag, f3_tag) when _T_5 : node _T_6 = eq(f3_scnt, f3_entry.p_cnt) node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) connect io.f3_pred, _io_f3_pred_T reg f4_fire : UInt<1>, clock connect f4_fire, io.f3_req_fire reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock connect f4_entry, f3_entry reg f4_tag : UInt, clock connect f4_tag, f3_tag reg f4_scnt : UInt, clock connect f4_scnt, f3_scnt reg f4_idx_REG : UInt, clock connect f4_idx_REG, io.f2_req_idx reg f4_idx : UInt, clock connect f4_idx, f4_idx_REG when f4_fire : node _T_9 = eq(f4_entry.tag, f4_tag) when _T_9 : node _T_10 = eq(f4_scnt, f4_entry.p_cnt) node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) node _T_12 = and(_T_10, _T_11) when _T_12 : node _T_13 = or(f4_idx, UInt<4>(0h0)) node _T_14 = bits(_T_13, 3, 0) connect entries[_T_14].age, UInt<3>(0h7) node _T_15 = or(f4_idx, UInt<4>(0h0)) node _T_16 = bits(_T_15, 3, 0) connect entries[_T_16].s_cnt, UInt<1>(0h0) else : node _T_17 = or(f4_idx, UInt<4>(0h0)) node _T_18 = bits(_T_17, 3, 0) node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 node _T_19 = or(f4_idx, UInt<4>(0h0)) node _T_20 = bits(_T_19, 3, 0) node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) node _entries_age_T_2 = tail(_entries_age_T_1, 1) node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) connect entries[_T_20].age, _entries_age_T_3 node _entry_T = or(io.update_idx, UInt<4>(0h0)) node _entry_T_1 = bits(_entry_T, 3, 0) node tag = bits(io.update_idx, 13, 4) node tag_match = eq(entries[_entry_T_1].tag, tag) node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect wentry, entries[_entry_T_1] node _T_21 = eq(doing_reset, UInt<1>(0h0)) node _T_22 = and(io.update_mispredict, _T_21) when _T_22 : node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_24 = and(_T_23, tag_match) when _T_24 : connect wentry.s_cnt, UInt<1>(0h0) connect wentry.conf, UInt<1>(0h0) else : node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) node _T_26 = eq(tag_match, UInt<1>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : skip else : node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_29 = and(_T_28, tag_match) node _T_30 = and(_T_29, ctr_match) when _T_30 : node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) connect wentry.conf, _wentry_conf_T_1 connect wentry.s_cnt, UInt<1>(0h0) else : node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_32 = and(_T_31, tag_match) node _T_33 = eq(ctr_match, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) when _T_34 : connect wentry.conf, UInt<1>(0h0) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_36 = eq(tag_match, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt else : node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_41 = eq(tag_match, UInt<1>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) when _T_44 : node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) node _wentry_age_T_1 = tail(_wentry_age_T, 1) connect wentry.age, _wentry_age_T_1 else : node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_46 = and(_T_45, tag_match) node _T_47 = and(_T_46, ctr_match) when _T_47 : connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_49 = and(_T_48, tag_match) node _T_50 = eq(ctr_match, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect wentry.p_cnt, io.update_meta.s_cnt connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) else : node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) node _T_53 = eq(tag_match, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) when _T_54 : connect wentry.tag, tag connect wentry.conf, UInt<1>(0h1) connect wentry.age, UInt<3>(0h7) connect wentry.s_cnt, UInt<1>(0h0) connect wentry.p_cnt, io.update_meta.s_cnt node _T_55 = or(io.update_idx, UInt<4>(0h0)) node _T_56 = bits(_T_55, 3, 0) connect entries[_T_56], wentry else : node _T_57 = eq(doing_reset, UInt<1>(0h0)) node _T_58 = and(io.update_repair, _T_57) when _T_58 : node _T_59 = eq(io.update_idx, f4_idx) node _T_60 = and(f4_fire, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = and(tag_match, _T_61) when _T_62 : connect wentry.s_cnt, io.update_meta.s_cnt node _T_63 = or(io.update_idx, UInt<4>(0h0)) node _T_64 = bits(_T_63, 3, 0) connect entries[_T_64], wentry when doing_reset : wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} connect _entries_WIRE.s_cnt, UInt<10>(0h0) connect _entries_WIRE.p_cnt, UInt<10>(0h0) connect _entries_WIRE.age, UInt<3>(0h0) connect _entries_WIRE.conf, UInt<3>(0h0) connect _entries_WIRE.tag, UInt<10>(0h0) connect entries[reset_idx], _entries_WIRE

module LoopBranchPredictorColumn_11( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_218 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_218( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_32 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_64 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_32 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<1>(0h0), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<1>(0h1), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<4>(0hd), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(route_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_65 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_32 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_25 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_26 = and(vcalloc_q.io.enq.valid, _T_25) node _T_27 = eq(_T_26, UInt<1>(0h0)) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_27, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node _c_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi, c_lo) node _c_T_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_1 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_1 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_1, c_lo_1) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node out_channel_oh_0 = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node _out_bundle_bits_out_virt_channel_T_1 = bits(_out_bundle_bits_out_virt_channel_T, 1, 1) node _out_bundle_bits_out_virt_channel_T_2 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_1, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_3 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_4 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_5 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_6 = or(_out_bundle_bits_out_virt_channel_T_2, _out_bundle_bits_out_virt_channel_T_3) node _out_bundle_bits_out_virt_channel_T_7 = or(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_4) node _out_bundle_bits_out_virt_channel_T_8 = or(_out_bundle_bits_out_virt_channel_T_7, _out_bundle_bits_out_virt_channel_T_5) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<1> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_8 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_32( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_16 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[10], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], chosen_oh : UInt<10>[1]} regreset lock_0 : UInt<10>, clock, reset, UInt<10>(0h0) node unassigned_lo_lo = cat(io.in[1].valid, io.in[0].valid) node unassigned_lo_hi_hi = cat(io.in[4].valid, io.in[3].valid) node unassigned_lo_hi = cat(unassigned_lo_hi_hi, io.in[2].valid) node unassigned_lo = cat(unassigned_lo_hi, unassigned_lo_lo) node unassigned_hi_lo = cat(io.in[6].valid, io.in[5].valid) node unassigned_hi_hi_hi = cat(io.in[9].valid, io.in[8].valid) node unassigned_hi_hi = cat(unassigned_hi_hi_hi, io.in[7].valid) node unassigned_hi = cat(unassigned_hi_hi, unassigned_hi_lo) node _unassigned_T = cat(unassigned_hi, unassigned_lo) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire choices : UInt<10>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = bits(_sel_T_2, 6, 6) node _sel_T_10 = bits(_sel_T_2, 7, 7) node _sel_T_11 = bits(_sel_T_2, 8, 8) node _sel_T_12 = bits(_sel_T_2, 9, 9) node _sel_T_13 = bits(_sel_T_2, 10, 10) node _sel_T_14 = bits(_sel_T_2, 11, 11) node _sel_T_15 = bits(_sel_T_2, 12, 12) node _sel_T_16 = bits(_sel_T_2, 13, 13) node _sel_T_17 = bits(_sel_T_2, 14, 14) node _sel_T_18 = bits(_sel_T_2, 15, 15) node _sel_T_19 = bits(_sel_T_2, 16, 16) node _sel_T_20 = bits(_sel_T_2, 17, 17) node _sel_T_21 = bits(_sel_T_2, 18, 18) node _sel_T_22 = bits(_sel_T_2, 19, 19) node _sel_T_23 = mux(_sel_T_22, UInt<20>(0h80000), UInt<20>(0h0)) node _sel_T_24 = mux(_sel_T_21, UInt<20>(0h40000), _sel_T_23) node _sel_T_25 = mux(_sel_T_20, UInt<20>(0h20000), _sel_T_24) node _sel_T_26 = mux(_sel_T_19, UInt<20>(0h10000), _sel_T_25) node _sel_T_27 = mux(_sel_T_18, UInt<20>(0h8000), _sel_T_26) node _sel_T_28 = mux(_sel_T_17, UInt<20>(0h4000), _sel_T_27) node _sel_T_29 = mux(_sel_T_16, UInt<20>(0h2000), _sel_T_28) node _sel_T_30 = mux(_sel_T_15, UInt<20>(0h1000), _sel_T_29) node _sel_T_31 = mux(_sel_T_14, UInt<20>(0h800), _sel_T_30) node _sel_T_32 = mux(_sel_T_13, UInt<20>(0h400), _sel_T_31) node _sel_T_33 = mux(_sel_T_12, UInt<20>(0h200), _sel_T_32) node _sel_T_34 = mux(_sel_T_11, UInt<20>(0h100), _sel_T_33) node _sel_T_35 = mux(_sel_T_10, UInt<20>(0h80), _sel_T_34) node _sel_T_36 = mux(_sel_T_9, UInt<20>(0h40), _sel_T_35) node _sel_T_37 = mux(_sel_T_8, UInt<20>(0h20), _sel_T_36) node _sel_T_38 = mux(_sel_T_7, UInt<20>(0h10), _sel_T_37) node _sel_T_39 = mux(_sel_T_6, UInt<20>(0h8), _sel_T_38) node _sel_T_40 = mux(_sel_T_5, UInt<20>(0h4), _sel_T_39) node _sel_T_41 = mux(_sel_T_4, UInt<20>(0h2), _sel_T_40) node sel = mux(_sel_T_3, UInt<20>(0h1), _sel_T_41) node _choices_0_T = shr(sel, 10) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = bits(_T_1, 3, 3) node _T_6 = bits(_T_1, 4, 4) node _T_7 = bits(_T_1, 5, 5) node _T_8 = bits(_T_1, 6, 6) node _T_9 = bits(_T_1, 7, 7) node _T_10 = bits(_T_1, 8, 8) node _T_11 = bits(_T_1, 9, 9) node _T_12 = mux(_T_11, UInt<10>(0h200), UInt<10>(0h0)) node _T_13 = mux(_T_10, UInt<10>(0h100), _T_12) node _T_14 = mux(_T_9, UInt<10>(0h80), _T_13) node _T_15 = mux(_T_8, UInt<10>(0h40), _T_14) node _T_16 = mux(_T_7, UInt<10>(0h20), _T_15) node _T_17 = mux(_T_6, UInt<10>(0h10), _T_16) node _T_18 = mux(_T_5, UInt<10>(0h8), _T_17) node _T_19 = mux(_T_4, UInt<10>(0h4), _T_18) node _T_20 = mux(_T_3, UInt<10>(0h2), _T_19) node _T_21 = mux(_T_2, UInt<10>(0h1), _T_20) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) connect io.in[3].ready, UInt<1>(0h0) connect io.in[4].ready, UInt<1>(0h0) connect io.in[5].ready, UInt<1>(0h0) connect io.in[6].ready, UInt<1>(0h0) connect io.in[7].ready, UInt<1>(0h0) connect io.in[8].ready, UInt<1>(0h0) connect io.in[9].ready, UInt<1>(0h0) node in_tails_lo_lo = cat(io.in[1].bits.tail, io.in[0].bits.tail) node in_tails_lo_hi_hi = cat(io.in[4].bits.tail, io.in[3].bits.tail) node in_tails_lo_hi = cat(in_tails_lo_hi_hi, io.in[2].bits.tail) node in_tails_lo = cat(in_tails_lo_hi, in_tails_lo_lo) node in_tails_hi_lo = cat(io.in[6].bits.tail, io.in[5].bits.tail) node in_tails_hi_hi_hi = cat(io.in[9].bits.tail, io.in[8].bits.tail) node in_tails_hi_hi = cat(in_tails_hi_hi_hi, io.in[7].bits.tail) node in_tails_hi = cat(in_tails_hi_hi, in_tails_hi_lo) node in_tails = cat(in_tails_hi, in_tails_lo) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node _in_valids_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_7 = and(io.in[3].valid, _in_valids_T_6) node _in_valids_T_8 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_9 = and(io.in[4].valid, _in_valids_T_8) node _in_valids_T_10 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_11 = and(io.in[5].valid, _in_valids_T_10) node _in_valids_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_13 = and(io.in[6].valid, _in_valids_T_12) node _in_valids_T_14 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_15 = and(io.in[7].valid, _in_valids_T_14) node _in_valids_T_16 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_17 = and(io.in[8].valid, _in_valids_T_16) node _in_valids_T_18 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_19 = and(io.in[9].valid, _in_valids_T_18) node in_valids_lo_lo = cat(_in_valids_T_3, _in_valids_T_1) node in_valids_lo_hi_hi = cat(_in_valids_T_9, _in_valids_T_7) node in_valids_lo_hi = cat(in_valids_lo_hi_hi, _in_valids_T_5) node in_valids_lo = cat(in_valids_lo_hi, in_valids_lo_lo) node in_valids_hi_lo = cat(_in_valids_T_13, _in_valids_T_11) node in_valids_hi_hi_hi = cat(_in_valids_T_19, _in_valids_T_17) node in_valids_hi_hi = cat(in_valids_hi_hi_hi, _in_valids_T_15) node in_valids_hi = cat(in_valids_hi_hi, in_valids_hi_lo) node in_valids = cat(in_valids_hi, in_valids_lo) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<10>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) node _io_out_0_bits_T_3 = bits(chosen, 3, 3) node _io_out_0_bits_T_4 = bits(chosen, 4, 4) node _io_out_0_bits_T_5 = bits(chosen, 5, 5) node _io_out_0_bits_T_6 = bits(chosen, 6, 6) node _io_out_0_bits_T_7 = bits(chosen, 7, 7) node _io_out_0_bits_T_8 = bits(chosen, 8, 8) node _io_out_0_bits_T_9 = bits(chosen, 9, 9) wire _io_out_0_bits_WIRE : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>} node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_11 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_12 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T_3, io.in[3].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_4, io.in[4].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_5, io.in[5].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_16 = mux(_io_out_0_bits_T_6, io.in[6].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_17 = mux(_io_out_0_bits_T_7, io.in[7].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T_8, io.in[8].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_9, io.in[9].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_20 = or(_io_out_0_bits_T_10, _io_out_0_bits_T_11) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_20, _io_out_0_bits_T_12) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_13) node _io_out_0_bits_T_23 = or(_io_out_0_bits_T_22, _io_out_0_bits_T_14) node _io_out_0_bits_T_24 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_15) node _io_out_0_bits_T_25 = or(_io_out_0_bits_T_24, _io_out_0_bits_T_16) node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_25, _io_out_0_bits_T_17) node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_18) node _io_out_0_bits_T_28 = or(_io_out_0_bits_T_27, _io_out_0_bits_T_19) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_28 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_out_0_bits_WIRE_3 : UInt<1>[10] node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_31 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_32 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_36 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_37 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_39 = or(_io_out_0_bits_T_29, _io_out_0_bits_T_30) node _io_out_0_bits_T_40 = or(_io_out_0_bits_T_39, _io_out_0_bits_T_31) node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_40, _io_out_0_bits_T_32) node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_33) node _io_out_0_bits_T_43 = or(_io_out_0_bits_T_42, _io_out_0_bits_T_34) node _io_out_0_bits_T_44 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_35) node _io_out_0_bits_T_45 = or(_io_out_0_bits_T_44, _io_out_0_bits_T_36) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_45, _io_out_0_bits_T_37) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_38) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_47 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_51 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_52 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_56 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_57 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_58 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49) node _io_out_0_bits_T_59 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_50) node _io_out_0_bits_T_60 = or(_io_out_0_bits_T_59, _io_out_0_bits_T_51) node _io_out_0_bits_T_61 = or(_io_out_0_bits_T_60, _io_out_0_bits_T_52) node _io_out_0_bits_T_62 = or(_io_out_0_bits_T_61, _io_out_0_bits_T_53) node _io_out_0_bits_T_63 = or(_io_out_0_bits_T_62, _io_out_0_bits_T_54) node _io_out_0_bits_T_64 = or(_io_out_0_bits_T_63, _io_out_0_bits_T_55) node _io_out_0_bits_T_65 = or(_io_out_0_bits_T_64, _io_out_0_bits_T_56) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_65, _io_out_0_bits_T_57) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_66 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_67 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_71 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_72 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_73 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_74 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_75 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_76 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_77 = or(_io_out_0_bits_T_67, _io_out_0_bits_T_68) node _io_out_0_bits_T_78 = or(_io_out_0_bits_T_77, _io_out_0_bits_T_69) node _io_out_0_bits_T_79 = or(_io_out_0_bits_T_78, _io_out_0_bits_T_70) node _io_out_0_bits_T_80 = or(_io_out_0_bits_T_79, _io_out_0_bits_T_71) node _io_out_0_bits_T_81 = or(_io_out_0_bits_T_80, _io_out_0_bits_T_72) node _io_out_0_bits_T_82 = or(_io_out_0_bits_T_81, _io_out_0_bits_T_73) node _io_out_0_bits_T_83 = or(_io_out_0_bits_T_82, _io_out_0_bits_T_74) node _io_out_0_bits_T_84 = or(_io_out_0_bits_T_83, _io_out_0_bits_T_75) node _io_out_0_bits_T_85 = or(_io_out_0_bits_T_84, _io_out_0_bits_T_76) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_85 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_86 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_87 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_88 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_89 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_90 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_91 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_92 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_93 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_94 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_95 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_96 = or(_io_out_0_bits_T_86, _io_out_0_bits_T_87) node _io_out_0_bits_T_97 = or(_io_out_0_bits_T_96, _io_out_0_bits_T_88) node _io_out_0_bits_T_98 = or(_io_out_0_bits_T_97, _io_out_0_bits_T_89) node _io_out_0_bits_T_99 = or(_io_out_0_bits_T_98, _io_out_0_bits_T_90) node _io_out_0_bits_T_100 = or(_io_out_0_bits_T_99, _io_out_0_bits_T_91) node _io_out_0_bits_T_101 = or(_io_out_0_bits_T_100, _io_out_0_bits_T_92) node _io_out_0_bits_T_102 = or(_io_out_0_bits_T_101, _io_out_0_bits_T_93) node _io_out_0_bits_T_103 = or(_io_out_0_bits_T_102, _io_out_0_bits_T_94) node _io_out_0_bits_T_104 = or(_io_out_0_bits_T_103, _io_out_0_bits_T_95) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_104 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_105 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_106 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_107 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_108 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_109 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_110 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_111 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_112 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_113 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_114 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_115 = or(_io_out_0_bits_T_105, _io_out_0_bits_T_106) node _io_out_0_bits_T_116 = or(_io_out_0_bits_T_115, _io_out_0_bits_T_107) node _io_out_0_bits_T_117 = or(_io_out_0_bits_T_116, _io_out_0_bits_T_108) node _io_out_0_bits_T_118 = or(_io_out_0_bits_T_117, _io_out_0_bits_T_109) node _io_out_0_bits_T_119 = or(_io_out_0_bits_T_118, _io_out_0_bits_T_110) node _io_out_0_bits_T_120 = or(_io_out_0_bits_T_119, _io_out_0_bits_T_111) node _io_out_0_bits_T_121 = or(_io_out_0_bits_T_120, _io_out_0_bits_T_112) node _io_out_0_bits_T_122 = or(_io_out_0_bits_T_121, _io_out_0_bits_T_113) node _io_out_0_bits_T_123 = or(_io_out_0_bits_T_122, _io_out_0_bits_T_114) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_123 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_124 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_125 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_126 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_127 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_128 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_129 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_130 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_131 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_132 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_133 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_134 = or(_io_out_0_bits_T_124, _io_out_0_bits_T_125) node _io_out_0_bits_T_135 = or(_io_out_0_bits_T_134, _io_out_0_bits_T_126) node _io_out_0_bits_T_136 = or(_io_out_0_bits_T_135, _io_out_0_bits_T_127) node _io_out_0_bits_T_137 = or(_io_out_0_bits_T_136, _io_out_0_bits_T_128) node _io_out_0_bits_T_138 = or(_io_out_0_bits_T_137, _io_out_0_bits_T_129) node _io_out_0_bits_T_139 = or(_io_out_0_bits_T_138, _io_out_0_bits_T_130) node _io_out_0_bits_T_140 = or(_io_out_0_bits_T_139, _io_out_0_bits_T_131) node _io_out_0_bits_T_141 = or(_io_out_0_bits_T_140, _io_out_0_bits_T_132) node _io_out_0_bits_T_142 = or(_io_out_0_bits_T_141, _io_out_0_bits_T_133) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_142 connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_143 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_144 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_145 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_146 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_147 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_148 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_149 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_150 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_151 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_152 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_153 = or(_io_out_0_bits_T_143, _io_out_0_bits_T_144) node _io_out_0_bits_T_154 = or(_io_out_0_bits_T_153, _io_out_0_bits_T_145) node _io_out_0_bits_T_155 = or(_io_out_0_bits_T_154, _io_out_0_bits_T_146) node _io_out_0_bits_T_156 = or(_io_out_0_bits_T_155, _io_out_0_bits_T_147) node _io_out_0_bits_T_157 = or(_io_out_0_bits_T_156, _io_out_0_bits_T_148) node _io_out_0_bits_T_158 = or(_io_out_0_bits_T_157, _io_out_0_bits_T_149) node _io_out_0_bits_T_159 = or(_io_out_0_bits_T_158, _io_out_0_bits_T_150) node _io_out_0_bits_T_160 = or(_io_out_0_bits_T_159, _io_out_0_bits_T_151) node _io_out_0_bits_T_161 = or(_io_out_0_bits_T_160, _io_out_0_bits_T_152) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_161 connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_162 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_163 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_164 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_165 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_166 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_167 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_168 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_169 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_170 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_171 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_172 = or(_io_out_0_bits_T_162, _io_out_0_bits_T_163) node _io_out_0_bits_T_173 = or(_io_out_0_bits_T_172, _io_out_0_bits_T_164) node _io_out_0_bits_T_174 = or(_io_out_0_bits_T_173, _io_out_0_bits_T_165) node _io_out_0_bits_T_175 = or(_io_out_0_bits_T_174, _io_out_0_bits_T_166) node _io_out_0_bits_T_176 = or(_io_out_0_bits_T_175, _io_out_0_bits_T_167) node _io_out_0_bits_T_177 = or(_io_out_0_bits_T_176, _io_out_0_bits_T_168) node _io_out_0_bits_T_178 = or(_io_out_0_bits_T_177, _io_out_0_bits_T_169) node _io_out_0_bits_T_179 = or(_io_out_0_bits_T_178, _io_out_0_bits_T_170) node _io_out_0_bits_T_180 = or(_io_out_0_bits_T_179, _io_out_0_bits_T_171) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_180 connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11 node _io_out_0_bits_T_181 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_182 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_183 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_184 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_185 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_186 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_187 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_188 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_189 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_190 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_191 = or(_io_out_0_bits_T_181, _io_out_0_bits_T_182) node _io_out_0_bits_T_192 = or(_io_out_0_bits_T_191, _io_out_0_bits_T_183) node _io_out_0_bits_T_193 = or(_io_out_0_bits_T_192, _io_out_0_bits_T_184) node _io_out_0_bits_T_194 = or(_io_out_0_bits_T_193, _io_out_0_bits_T_185) node _io_out_0_bits_T_195 = or(_io_out_0_bits_T_194, _io_out_0_bits_T_186) node _io_out_0_bits_T_196 = or(_io_out_0_bits_T_195, _io_out_0_bits_T_187) node _io_out_0_bits_T_197 = or(_io_out_0_bits_T_196, _io_out_0_bits_T_188) node _io_out_0_bits_T_198 = or(_io_out_0_bits_T_197, _io_out_0_bits_T_189) node _io_out_0_bits_T_199 = or(_io_out_0_bits_T_198, _io_out_0_bits_T_190) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_199 connect _io_out_0_bits_WIRE_3[8], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_200 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_201 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_202 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_203 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_204 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_205 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_206 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_207 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_208 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_209 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_210 = or(_io_out_0_bits_T_200, _io_out_0_bits_T_201) node _io_out_0_bits_T_211 = or(_io_out_0_bits_T_210, _io_out_0_bits_T_202) node _io_out_0_bits_T_212 = or(_io_out_0_bits_T_211, _io_out_0_bits_T_203) node _io_out_0_bits_T_213 = or(_io_out_0_bits_T_212, _io_out_0_bits_T_204) node _io_out_0_bits_T_214 = or(_io_out_0_bits_T_213, _io_out_0_bits_T_205) node _io_out_0_bits_T_215 = or(_io_out_0_bits_T_214, _io_out_0_bits_T_206) node _io_out_0_bits_T_216 = or(_io_out_0_bits_T_215, _io_out_0_bits_T_207) node _io_out_0_bits_T_217 = or(_io_out_0_bits_T_216, _io_out_0_bits_T_208) node _io_out_0_bits_T_218 = or(_io_out_0_bits_T_217, _io_out_0_bits_T_209) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_218 connect _io_out_0_bits_WIRE_3[9], _io_out_0_bits_WIRE_13 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_14 : UInt<1>[1] node _io_out_0_bits_T_219 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_220 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_221 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_222 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_223 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_224 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_225 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_226 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_227 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_228 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_229 = or(_io_out_0_bits_T_219, _io_out_0_bits_T_220) node _io_out_0_bits_T_230 = or(_io_out_0_bits_T_229, _io_out_0_bits_T_221) node _io_out_0_bits_T_231 = or(_io_out_0_bits_T_230, _io_out_0_bits_T_222) node _io_out_0_bits_T_232 = or(_io_out_0_bits_T_231, _io_out_0_bits_T_223) node _io_out_0_bits_T_233 = or(_io_out_0_bits_T_232, _io_out_0_bits_T_224) node _io_out_0_bits_T_234 = or(_io_out_0_bits_T_233, _io_out_0_bits_T_225) node _io_out_0_bits_T_235 = or(_io_out_0_bits_T_234, _io_out_0_bits_T_226) node _io_out_0_bits_T_236 = or(_io_out_0_bits_T_235, _io_out_0_bits_T_227) node _io_out_0_bits_T_237 = or(_io_out_0_bits_T_236, _io_out_0_bits_T_228) wire _io_out_0_bits_WIRE_15 : UInt<1> connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_237 connect _io_out_0_bits_WIRE_14[0], _io_out_0_bits_WIRE_15 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_14 wire _io_out_0_bits_WIRE_16 : UInt<1>[1] node _io_out_0_bits_T_238 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_239 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_240 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_241 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_242 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_243 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_244 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_245 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_246 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_247 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_248 = or(_io_out_0_bits_T_238, _io_out_0_bits_T_239) node _io_out_0_bits_T_249 = or(_io_out_0_bits_T_248, _io_out_0_bits_T_240) node _io_out_0_bits_T_250 = or(_io_out_0_bits_T_249, _io_out_0_bits_T_241) node _io_out_0_bits_T_251 = or(_io_out_0_bits_T_250, _io_out_0_bits_T_242) node _io_out_0_bits_T_252 = or(_io_out_0_bits_T_251, _io_out_0_bits_T_243) node _io_out_0_bits_T_253 = or(_io_out_0_bits_T_252, _io_out_0_bits_T_244) node _io_out_0_bits_T_254 = or(_io_out_0_bits_T_253, _io_out_0_bits_T_245) node _io_out_0_bits_T_255 = or(_io_out_0_bits_T_254, _io_out_0_bits_T_246) node _io_out_0_bits_T_256 = or(_io_out_0_bits_T_255, _io_out_0_bits_T_247) wire _io_out_0_bits_WIRE_17 : UInt<1> connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_256 connect _io_out_0_bits_WIRE_16[0], _io_out_0_bits_WIRE_17 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_16 wire _io_out_0_bits_WIRE_18 : UInt<1>[1] node _io_out_0_bits_T_257 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_258 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_259 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_260 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_261 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_262 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_263 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_264 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_265 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_266 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_267 = or(_io_out_0_bits_T_257, _io_out_0_bits_T_258) node _io_out_0_bits_T_268 = or(_io_out_0_bits_T_267, _io_out_0_bits_T_259) node _io_out_0_bits_T_269 = or(_io_out_0_bits_T_268, _io_out_0_bits_T_260) node _io_out_0_bits_T_270 = or(_io_out_0_bits_T_269, _io_out_0_bits_T_261) node _io_out_0_bits_T_271 = or(_io_out_0_bits_T_270, _io_out_0_bits_T_262) node _io_out_0_bits_T_272 = or(_io_out_0_bits_T_271, _io_out_0_bits_T_263) node _io_out_0_bits_T_273 = or(_io_out_0_bits_T_272, _io_out_0_bits_T_264) node _io_out_0_bits_T_274 = or(_io_out_0_bits_T_273, _io_out_0_bits_T_265) node _io_out_0_bits_T_275 = or(_io_out_0_bits_T_274, _io_out_0_bits_T_266) wire _io_out_0_bits_WIRE_19 : UInt<1> connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_275 connect _io_out_0_bits_WIRE_18[0], _io_out_0_bits_WIRE_19 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_18 wire _io_out_0_bits_WIRE_20 : UInt<1>[1] node _io_out_0_bits_T_276 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_277 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_278 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_279 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_280 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_281 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_282 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_283 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_284 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_285 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`4`[0], UInt<1>(0h0)) node _io_out_0_bits_T_286 = or(_io_out_0_bits_T_276, _io_out_0_bits_T_277) node _io_out_0_bits_T_287 = or(_io_out_0_bits_T_286, _io_out_0_bits_T_278) node _io_out_0_bits_T_288 = or(_io_out_0_bits_T_287, _io_out_0_bits_T_279) node _io_out_0_bits_T_289 = or(_io_out_0_bits_T_288, _io_out_0_bits_T_280) node _io_out_0_bits_T_290 = or(_io_out_0_bits_T_289, _io_out_0_bits_T_281) node _io_out_0_bits_T_291 = or(_io_out_0_bits_T_290, _io_out_0_bits_T_282) node _io_out_0_bits_T_292 = or(_io_out_0_bits_T_291, _io_out_0_bits_T_283) node _io_out_0_bits_T_293 = or(_io_out_0_bits_T_292, _io_out_0_bits_T_284) node _io_out_0_bits_T_294 = or(_io_out_0_bits_T_293, _io_out_0_bits_T_285) wire _io_out_0_bits_WIRE_21 : UInt<1> connect _io_out_0_bits_WIRE_21, _io_out_0_bits_T_294 connect _io_out_0_bits_WIRE_20[0], _io_out_0_bits_WIRE_21 connect _io_out_0_bits_WIRE_2.`4`, _io_out_0_bits_WIRE_20 wire _io_out_0_bits_WIRE_22 : UInt<1>[1] node _io_out_0_bits_T_295 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_296 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_297 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_298 = mux(_io_out_0_bits_T_3, io.in[3].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_299 = mux(_io_out_0_bits_T_4, io.in[4].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_300 = mux(_io_out_0_bits_T_5, io.in[5].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_301 = mux(_io_out_0_bits_T_6, io.in[6].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_302 = mux(_io_out_0_bits_T_7, io.in[7].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_303 = mux(_io_out_0_bits_T_8, io.in[8].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_304 = mux(_io_out_0_bits_T_9, io.in[9].bits.vc_sel.`5`[0], UInt<1>(0h0)) node _io_out_0_bits_T_305 = or(_io_out_0_bits_T_295, _io_out_0_bits_T_296) node _io_out_0_bits_T_306 = or(_io_out_0_bits_T_305, _io_out_0_bits_T_297) node _io_out_0_bits_T_307 = or(_io_out_0_bits_T_306, _io_out_0_bits_T_298) node _io_out_0_bits_T_308 = or(_io_out_0_bits_T_307, _io_out_0_bits_T_299) node _io_out_0_bits_T_309 = or(_io_out_0_bits_T_308, _io_out_0_bits_T_300) node _io_out_0_bits_T_310 = or(_io_out_0_bits_T_309, _io_out_0_bits_T_301) node _io_out_0_bits_T_311 = or(_io_out_0_bits_T_310, _io_out_0_bits_T_302) node _io_out_0_bits_T_312 = or(_io_out_0_bits_T_311, _io_out_0_bits_T_303) node _io_out_0_bits_T_313 = or(_io_out_0_bits_T_312, _io_out_0_bits_T_304) wire _io_out_0_bits_WIRE_23 : UInt<1> connect _io_out_0_bits_WIRE_23, _io_out_0_bits_T_313 connect _io_out_0_bits_WIRE_22[0], _io_out_0_bits_WIRE_23 connect _io_out_0_bits_WIRE_2.`5`, _io_out_0_bits_WIRE_22 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_22 = bits(chosen, 0, 0) node _T_23 = and(_T_22, io.out[0].ready) when _T_23 : connect io.in[0].ready, UInt<1>(0h1) node _T_24 = bits(chosen, 1, 1) node _T_25 = and(_T_24, io.out[0].ready) when _T_25 : connect io.in[1].ready, UInt<1>(0h1) node _T_26 = bits(chosen, 2, 2) node _T_27 = and(_T_26, io.out[0].ready) when _T_27 : connect io.in[2].ready, UInt<1>(0h1) node _T_28 = bits(chosen, 3, 3) node _T_29 = and(_T_28, io.out[0].ready) when _T_29 : connect io.in[3].ready, UInt<1>(0h1) node _T_30 = bits(chosen, 4, 4) node _T_31 = and(_T_30, io.out[0].ready) when _T_31 : connect io.in[4].ready, UInt<1>(0h1) node _T_32 = bits(chosen, 5, 5) node _T_33 = and(_T_32, io.out[0].ready) when _T_33 : connect io.in[5].ready, UInt<1>(0h1) node _T_34 = bits(chosen, 6, 6) node _T_35 = and(_T_34, io.out[0].ready) when _T_35 : connect io.in[6].ready, UInt<1>(0h1) node _T_36 = bits(chosen, 7, 7) node _T_37 = and(_T_36, io.out[0].ready) when _T_37 : connect io.in[7].ready, UInt<1>(0h1) node _T_38 = bits(chosen, 8, 8) node _T_39 = and(_T_38, io.out[0].ready) when _T_39 : connect io.in[8].ready, UInt<1>(0h1) node _T_40 = bits(chosen, 9, 9) node _T_41 = and(_T_40, io.out[0].ready) when _T_41 : connect io.in[9].ready, UInt<1>(0h1) node _T_42 = or(UInt<10>(0h0), chosen) node _T_43 = and(io.out[0].ready, io.out[0].valid) when _T_43 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_44 = and(io.out[0].ready, io.out[0].valid) when _T_44 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = shr(io.chosen_oh[0], 3) node _mask_T_4 = shr(io.chosen_oh[0], 4) node _mask_T_5 = shr(io.chosen_oh[0], 5) node _mask_T_6 = shr(io.chosen_oh[0], 6) node _mask_T_7 = shr(io.chosen_oh[0], 7) node _mask_T_8 = shr(io.chosen_oh[0], 8) node _mask_T_9 = shr(io.chosen_oh[0], 9) node _mask_T_10 = or(_mask_T, _mask_T_1) node _mask_T_11 = or(_mask_T_10, _mask_T_2) node _mask_T_12 = or(_mask_T_11, _mask_T_3) node _mask_T_13 = or(_mask_T_12, _mask_T_4) node _mask_T_14 = or(_mask_T_13, _mask_T_5) node _mask_T_15 = or(_mask_T_14, _mask_T_6) node _mask_T_16 = or(_mask_T_15, _mask_T_7) node _mask_T_17 = or(_mask_T_16, _mask_T_8) node _mask_T_18 = or(_mask_T_17, _mask_T_9) connect mask, _mask_T_18 else : node _mask_T_19 = not(mask) node _mask_T_20 = eq(_mask_T_19, UInt<1>(0h0)) node _mask_T_21 = shl(mask, 1) node _mask_T_22 = or(_mask_T_21, UInt<1>(0h1)) node _mask_T_23 = mux(_mask_T_20, UInt<1>(0h0), _mask_T_22) connect mask, _mask_T_23

module SwitchArbiter_16( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_3_ready, // @[SwitchAllocator.scala:18:14] input io_in_3_valid, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_3_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_5_ready, // @[SwitchAllocator.scala:18:14] input io_in_5_valid, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_5_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_8_ready, // @[SwitchAllocator.scala:18:14] input io_in_8_valid, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_8_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_9_ready, // @[SwitchAllocator.scala:18:14] input io_in_9_valid, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_9_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_5_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_4_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [9:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [9:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [9:0] unassigned = {io_in_9_valid, io_in_8_valid, 2'h0, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [9:0] mask; // @[SwitchAllocator.scala:27:21] wire [9:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [19:0] sel = _sel_T_1[0] ? 20'h1 : _sel_T_1[1] ? 20'h2 : _sel_T_1[2] ? 20'h4 : _sel_T_1[3] ? 20'h8 : _sel_T_1[4] ? 20'h10 : _sel_T_1[5] ? 20'h20 : _sel_T_1[6] ? 20'h40 : _sel_T_1[7] ? 20'h80 : _sel_T_1[8] ? 20'h100 : _sel_T_1[9] ? 20'h200 : unassigned[0] ? 20'h400 : unassigned[1] ? 20'h800 : unassigned[2] ? 20'h1000 : unassigned[3] ? 20'h2000 : unassigned[4] ? 20'h4000 : unassigned[5] ? 20'h8000 : unassigned[6] ? 20'h10000 : unassigned[7] ? 20'h20000 : unassigned[8] ? 20'h40000 : {unassigned[9], 19'h0}; // @[OneHot.scala:85:71] wire [9:0] in_valids = {io_in_9_valid, io_in_8_valid, 2'h0, io_in_5_valid, io_in_4_valid, io_in_3_valid, io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [9:0] _chosen_T_2 = in_valids & lock_0; // @[SwitchAllocator.scala:24:38, :41:24, :42:33] wire [9:0] chosen = (|{_chosen_T_2[9:8], _chosen_T_2[5:0]}) ? lock_0 : sel[9:0] | sel[19:10]; // @[Mux.scala:50:70] wire [9:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [7:0] _GEN = {_io_out_0_valid_T[9:8], _io_out_0_valid_T[5:0]}; // @[SwitchAllocator.scala:44:35] wire _GEN_0 = io_out_0_ready & (|_GEN); // @[Decoupled.scala:51:35] wire [8:0] _GEN_1 = chosen[8:0] | chosen[9:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [7:0] _GEN_2 = _GEN_1[7:0] | chosen[9:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [6:0] _GEN_3 = _GEN_2[6:0] | chosen[9:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [5:0] _GEN_4 = _GEN_3[5:0] | chosen[9:4]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [4:0] _GEN_5 = _GEN_4[4:0] | chosen[9:5]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [3:0] _GEN_6 = _GEN_5[3:0] | chosen[9:6]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_7 = _GEN_6[2:0] | chosen[9:7]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_8 = _GEN_7[1:0] | chosen[9:8]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 10'h0; // @[SwitchAllocator.scala:24:38] mask <= 10'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_0) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_9_bits_tail, ~io_in_8_bits_tail, 2'h3, ~io_in_5_bits_tail, ~io_in_4_bits_tail, ~io_in_3_bits_tail, ~io_in_2_bits_tail, ~io_in_1_bits_tail, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_0 ? {chosen[9], _GEN_1[8], _GEN_2[7], _GEN_3[6], _GEN_4[5], _GEN_5[4], _GEN_6[3], _GEN_7[2], _GEN_8[1], _GEN_8[0] | chosen[9]} : (&mask) ? 10'h0 : {mask[8:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)